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-rw-r--r--include/asm-ppc/global_data.h15
-rw-r--r--include/asm-ppc/immap_83xx.h145
-rw-r--r--include/configs/MPC8313ERDB.h9
-rw-r--r--include/configs/MPC8323ERDB.h12
-rw-r--r--include/configs/MPC832XEMDS.h12
-rw-r--r--include/configs/MPC8349EMDS.h8
-rw-r--r--include/configs/MPC8349ITX.h11
-rw-r--r--include/configs/MPC8360EMDS.h15
-rw-r--r--include/configs/MPC837XEMDS.h600
-rw-r--r--include/configs/sbc8349.h10
-rw-r--r--include/mpc83xx.h261
11 files changed, 1018 insertions, 80 deletions
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 05aee74..91acf9b 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -55,7 +55,7 @@ typedef struct global_data {
#if defined(CONFIG_MPC83XX)
/* There are other clocks in the MPC83XX */
u32 csb_clk;
-#if defined (CONFIG_MPC834X) || defined(CONFIG_MPC831X)
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
@@ -63,6 +63,12 @@ typedef struct global_data {
#if defined (CONFIG_MPC834X)
u32 usbmph_clk;
#endif /* CONFIG_MPC834X */
+#if defined(CONFIG_MPC815)
+ u32 tdm_clk;
+#endif
+#if defined(CONFIG_MPC837X)
+ u32 sdhc_clk;
+#endif
u32 core_clk;
u32 i2c1_clk;
u32 i2c2_clk;
@@ -71,6 +77,13 @@ typedef struct global_data {
u32 lclk_clk;
u32 ddr_clk;
u32 pci_clk;
+#if defined(CONFIG_MPC837X)
+ u32 pciexp1_clk;
+ u32 pciexp2_clk;
+#endif
+#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
+ u32 sata_clk;
+#endif
#if defined(CONFIG_MPC8360)
u32 ddr_sec_clk;
#endif /* CONFIG_MPC8360 */
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 0de9338..34ea295 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2004-2006 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
*
* MPC83xx Internal Memory Map
*
@@ -63,7 +63,8 @@ typedef struct sysconf83xx {
u8 res6[0x0C];
u32 ddrcdr; /* DDR Control Driver Register */
u32 ddrdsr; /* DDR Debug Status Register */
- u8 res7[0xD0];
+ u32 obir; /* Output Buffer Impedance Register */
+ u8 res7[0xCC];
} sysconf83xx_t;
/*
@@ -553,6 +554,55 @@ typedef struct security83xx {
u8 fixme[0x10000];
} security83xx_t;
+/*
+ * PCI Express
+ */
+typedef struct pex83xx {
+ u8 fixme[0x1000];
+} pex83xx_t;
+
+/*
+ * SATA
+ */
+typedef struct sata83xx {
+ u8 fixme[0x1000];
+} sata83xx_t;
+
+/*
+ * eSDHC
+ */
+typedef struct sdhc83xx {
+ u8 fixme[0x1000];
+} sdhc83xx_t;
+
+/*
+ * SerDes
+ */
+typedef struct serdes83xx {
+ u8 fixme[0x100];
+} serdes83xx_t;
+
+/*
+ * On Chip ROM
+ */
+typedef struct rom83xx {
+ u8 mem[0x10000];
+} rom83xx_t;
+
+/*
+ * TDM
+ */
+typedef struct tdm83xx {
+ u8 fixme[0x200];
+} tdm83xx_t;
+
+/*
+ * TDM DMAC
+ */
+typedef struct tdmdmac83xx {
+ u8 fixme[0x2000];
+} tdmdmac83xx_t;
+
#if defined(CONFIG_MPC834X)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
@@ -590,7 +640,7 @@ typedef struct immap {
u8 res7[0xC0000];
} immap_t;
-#elif defined(CONFIG_MPC831X)
+#elif defined(CONFIG_MPC8313)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
@@ -625,6 +675,95 @@ typedef struct immap {
u8 res7[0xC0000];
} immap_t;
+#elif defined(CONFIG_MPC8315)
+typedef struct immap {
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ gtm83xx_t gtm[2]; /* Global Timers Module */
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ gpio83xx_t gpio[1]; /* General purpose I/O module */
+ u8 res0[0x1300];
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+ fsl_i2c_t i2c[2]; /* I2C Controllers */
+ u8 res1[0x1300];
+ duart83xx_t duart[2]; /* DUART */
+ u8 res2[0x900];
+ lbus83xx_t lbus; /* Local Bus Controller Registers */
+ u8 res3[0x1000];
+ spi83xx_t spi; /* Serial Peripheral Interface */
+ dma83xx_t dma; /* DMA */
+ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
+ u8 res4[0x80];
+ ios83xx_t ios; /* Sequencer */
+ pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
+ u8 res5[0xa00];
+ pex83xx_t pciexp[2]; /* PCI Express Controller */
+ u8 res6[0xb000];
+ tdm83xx_t tdm; /* TDM Controller */
+ u8 res7[0x1e00];
+ sata83xx_t sata[2]; /* SATA Controller */
+ u8 res8[0x9000];
+ usb83xx_t usb[1]; /* USB DR Controller */
+ tsec83xx_t tsec[2];
+ u8 res9[0x6000];
+ tdmdmac83xx_t tdmdmac; /* TDM DMAC */
+ u8 res10[0x2000];
+ security83xx_t security;
+ u8 res11[0xA3000];
+ serdes83xx_t serdes[1]; /* SerDes Registers */
+ u8 res12[0x1CF00];
+} immap_t;
+
+#elif defined(CONFIG_MPC837X)
+typedef struct immap {
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ gtm83xx_t gtm[2]; /* Global Timers Module */
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ gpio83xx_t gpio[2]; /* General purpose I/O module */
+ u8 res0[0x1200];
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+ fsl_i2c_t i2c[2]; /* I2C Controllers */
+ u8 res1[0x1300];
+ duart83xx_t duart[2]; /* DUART */
+ u8 res2[0x900];
+ lbus83xx_t lbus; /* Local Bus Controller Registers */
+ u8 res3[0x1000];
+ spi83xx_t spi; /* Serial Peripheral Interface */
+ dma83xx_t dma; /* DMA */
+ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
+ u8 res4[0x80];
+ ios83xx_t ios; /* Sequencer */
+ pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
+ u8 res5[0xa00];
+ pex83xx_t pciexp[2]; /* PCI Express Controller */
+ u8 res6[0xd000];
+ sata83xx_t sata[4]; /* SATA Controller */
+ u8 res7[0x7000];
+ usb83xx_t usb[1]; /* USB DR Controller */
+ tsec83xx_t tsec[2];
+ u8 res8[0x8000];
+ sdhc83xx_t sdhc; /* SDHC Controller */
+ u8 res9[0x1000];
+ security83xx_t security;
+ u8 res10[0xA3000];
+ serdes83xx_t serdes[2]; /* SerDes Registers */
+ u8 res11[0xCE00];
+ rom83xx_t rom; /* On Chip ROM */
+} immap_t;
+
#elif defined(CONFIG_MPC8360)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 6568fe1..c9a9c83 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -178,6 +178,7 @@
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
@@ -230,11 +231,7 @@
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,8313@0"
-#define OF_SOC "soc8313@e0000000"
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH "/soc8313@e0000000/serial@4500"
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* Serial Port
@@ -326,7 +323,7 @@
*/
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
- #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 376973b..564de02 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -116,6 +116,7 @@
#undef CFG_RAMBOOT
#endif
+/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
@@ -269,12 +270,7 @@
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,8323@0"
-#define OF_SOC "soc8323@e0000000"
-#define OF_QE "qe@e0100000"
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500"
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
@@ -354,8 +350,8 @@
*/
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
- #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
- #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+ #define CFG_ENV_SECT_SIZE 0x20000
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index c9c6d88..a48b311 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -145,6 +145,7 @@
#undef CFG_RAMBOOT
#endif
+/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
@@ -320,12 +321,7 @@
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,8323@0"
-#define OF_SOC "soc8323@e0000000"
-#define OF_QE "qe@e0100000"
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500"
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
@@ -410,8 +406,8 @@
*/
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
- #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
- #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+ #define CFG_ENV_SECT_SIZE 0x20000
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 92555ba..03409bb 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -341,11 +341,7 @@
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,8349@0"
-#define OF_SOC "soc8349@e0000000"
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500"
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
@@ -456,7 +452,7 @@
*/
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
- #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 54cab52..49dc0de 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -261,6 +261,7 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
@@ -297,12 +298,8 @@ boards, we say we have two, but don't display a message if we find only one. */
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP
-
-#define OF_CPU "PowerPC,8349@0"
-#define OF_SOC "soc8349@e0000000"
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500"
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* PCI
@@ -404,8 +401,8 @@ boards, we say we have two, but don't display a message if we find only one. */
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
- #define CFG_ENV_ADDR (CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE))
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH /* Flash is not usable now */
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 41f062c..fedb8a9 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -170,6 +170,7 @@
#undef CFG_RAMBOOT
#endif
+/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
@@ -346,16 +347,8 @@
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
-#undef CONFIG_OF_FLAT_TREE
#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_HAS_BD_T 1
-#define CONFIG_OF_HAS_UBOOT_ENV 1
-
-#define OF_CPU "PowerPC,8360@0"
-#define OF_SOC "soc8360@e0000000"
-#define OF_QE "qe@e0100000"
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH "/soc8360@e0000000/serial@4500"
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
@@ -443,8 +436,8 @@
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
- #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
- #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+ #define CFG_ENV_SECT_SIZE 0x20000
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
new file mode 100644
index 0000000..0958e6b
--- /dev/null
+++ b/include/configs/MPC837XEMDS.h
@@ -0,0 +1,600 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 family */
+#define CONFIG_MPC83XX 1 /* MPC83XX family */
+#define CONFIG_MPC837X 1 /* MPC837X CPU specific */
+#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
+
+/*
+ * System Clock Setup
+ */
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
+#else
+#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ 66000000
+#endif
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66MHz, then
+ * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
+ */
+#define CFG_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_1X1 |\
+ HRCWL_SVCOD_DIV_2 |\
+ HRCWL_CSB_TO_CLKIN_6X1 |\
+ HRCWL_CORE_TO_CSB_1_5X1)
+
+#ifdef CONFIG_PCISLAVE
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_AGENT |\
+ HRCWH_PCI1_ARBITER_DISABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0XFFF00100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_RL_EXT_LEGACY |\
+ HRCWH_TSEC1M_IN_RGMII |\
+ HRCWH_TSEC2M_IN_RGMII |\
+ HRCWH_BIG_ENDIAN |\
+ HRCWH_LDP_CLEAR)
+#else
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_RL_EXT_LEGACY |\
+ HRCWH_TSEC1M_IN_RGMII |\
+ HRCWH_TSEC2M_IN_RGMII |\
+ HRCWH_BIG_ENDIAN |\
+ HRCWH_LDP_CLEAR)
+#endif
+
+/*
+ * eTSEC Clock Config
+ */
+#define CFG_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
+#define CFG_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
+
+/*
+ * System IO Config
+ */
+#define CFG_SICRH 0x00000000
+#define CFG_SICRL 0x00000000
+
+/*
+ * Output Buffer Impedance
+ */
+#define CFG_OBIR 0x31100000
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/*
+ * IMMR new address
+ */
+#define CFG_IMMR 0xE0000000
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CFG_83XX_DDR_USES_CS0
+#define CFG_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */
+
+#undef CONFIG_DDR_ECC /* support DDR ECC function */
+#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
+
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
+
+#if defined(CONFIG_SPD_EEPROM)
+#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
+#else
+/*
+ * Manually set up DDR parameters
+ * WHITE ELECTRONIC DESGGNS - W3HG64M72EEU403PD4 SO-DIMM
+ * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
+ */
+#define CFG_DDR_SIZE 512 /* MB */
+#define CFG_DDR_CS0_BNDS 0x0000001f
+#define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \
+ | 0x00010000 /* ODT_WR to CSn */ \
+ | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 )
+ /* 0x80010202 */
+#define CFG_DDR_TIMING_3 0x00000000
+#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
+ | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
+ | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
+ | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
+ | ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
+ | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
+ | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
+ | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+ /* 0x00620802 */
+#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
+ | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
+ | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
+ | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
+ | (13 << TIMING_CFG1_REFREC_SHIFT ) \
+ | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
+ | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
+ | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+ /* 0x3935d322 */
+#define CFG_DDR_TIMING_2 ( ( 2 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+ | ( 6 << TIMING_CFG2_CPO_SHIFT ) \
+ | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
+ | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
+ | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
+ | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
+ | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+ /* 0x231088c8 */
+#define CFG_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+ | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+ /* 0x03E00100 */
+#define CFG_DDR_SDRAM_CFG 0x43000000
+#define CFG_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
+#define CFG_DDR_MODE ( ( 0x0450 << SDRAM_MODE_ESD_SHIFT ) \
+ | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) )
+ /* ODT 150ohm CL=3, AL=2 on SDRAM */
+#define CFG_DDR_MODE2 0x00000000
+#endif
+
+/*
+ * Memory test
+ */
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00040000 /* memtest region */
+#define CFG_MEMTEST_END 0x00140000
+
+/*
+ * The reserved memory
+ */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
+#define CFG_LBC_LBCR 0x00000000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI /* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
+#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */
+
+#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
+#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
+
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
+ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+ BR_V) /* valid */
+#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
+ OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
+ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+/*
+ * BCSR on the Local Bus
+ */
+#define CFG_BCSR 0xF8000000
+#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
+#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
+
+#define CFG_BR1_PRELIM (CFG_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */
+#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
+
+/*
+ * NAND Flash on the Local Bus
+ */
+#define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */
+#define CFG_BR3_PRELIM ( CFG_NAND_BASE \
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V ) /* valid */
+#define CFG_OR3_PRELIM ( 0xFFFF8000 /* length 32K */ \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_1 \
+ | OR_FCM_TRLX \
+ | OR_FCM_EHTR )
+ /* 0xFFFF8396 */
+
+#define CFG_LBLAWBAR3_PRELIM CFG_NAND_BASE
+#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_FSL_I2C
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
+#define CFG_I2C2_OFFSET 0x3100
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
+#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI_MEM_BASE 0x80000000
+#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
+#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI_MMIO_BASE 0x90000000
+#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
+#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
+#define CFG_PCI_IO_BASE 0xE0300000
+#define CFG_PCI_IO_PHYS 0xE0300000
+#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
+
+#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE
+#define CFG_PCI_SLV_MEM_BUS 0x00000000
+#define CFG_PCI_SLV_MEM_SIZE 0x80000000
+
+#ifdef CONFIG_PCI
+#define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
+#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
+#endif /* CONFIG_PCI */
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET /* TSEC ethernet support */
+#define CFG_TSEC1_OFFSET 0x24000
+#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET 0x25000
+#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC1"
+#define TSEC1_PHY_ADDR 2
+#define TSEC2_PHY_ADDR 3
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "eTSEC1"
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+ #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+ #define CFG_ENV_SIZE 0x2000
+#else
+ #define CFG_NO_FLASH 1 /* Flash is not usable now */
+ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+ #define CFG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CFG_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
+#endif
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if defined(CONFIG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CFG_HID0_INIT 0x000000000
+#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CFG_HID2 HID2_HBE
+
+/*
+ * Cache Config
+ */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
+#endif
+
+/*
+ * MMU Setup
+ */
+
+/* DDR: cache cacheable */
+#define CFG_SDRAM_LOWER CFG_SDRAM_BASE
+#define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000)
+
+#define CFG_IBAT0L (CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+
+#define CFG_IBAT1L (CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+
+/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
+#define CFG_IBAT2L (CFG_IMMR | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+
+/* BCSR: cache-inhibit and guarded */
+#define CFG_IBAT3L (CFG_BCSR | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT3U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CFG_IBAT4L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT4U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_DBAT4L (CFG_FLASH_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT4U CFG_IBAT4U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10)
+#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT5L CFG_IBAT5L
+#define CFG_DBAT5U CFG_IBAT5U
+
+#ifdef CONFIG_PCI
+/* PCI MEM space: cacheable */
+#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT7L CFG_IBAT7L
+#define CFG_DBAT7U CFG_IBAT7U
+#else
+#define CFG_IBAT6L (0)
+#define CFG_IBAT6U (0)
+#define CFG_IBAT7L (0)
+#define CFG_IBAT7U (0)
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+#define CFG_DBAT7L CFG_IBAT7L
+#define CFG_DBAT7U CFG_IBAT7U
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR 00:E0:0C:00:83:79
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:E0:0C:00:83:78
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=1000000\0" \
+ "ramdiskfile=ramfs.83xx\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=mpc837xemds.dtb\0" \
+ ""
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index e7d8a5a..9efe3c4 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -310,13 +310,9 @@
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,8349@0"
-#define OF_SOC "soc8349@e0000000"
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500"
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
@@ -458,7 +454,7 @@
#define CONFIG_CMD_PING
#if defined(CONFIG_PCI)
- #define CONFG_CMD_PCI
+ #define CONFIG_CMD_PCI
#endif
#if defined(CFG_RAMBOOT)
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 4d32c6a..dba1aea 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -98,10 +98,21 @@
#define SPR_8321E_REV11 0x80660011
#define SPR_8321_REV11 0x80670011
-#define SPR_8311_REV10 0x80B30010
-#define SPR_8311E_REV10 0x80B20010
-#define SPR_8313_REV10 0x80B10010
#define SPR_8313E_REV10 0x80B00010
+#define SPR_8313_REV10 0x80B10010
+#define SPR_8311E_REV10 0x80B20010
+#define SPR_8311_REV10 0x80B30010
+#define SPR_8315E_REV10 0x80B40010
+#define SPR_8315_REV10 0x80B50010
+#define SPR_8314E_REV10 0x80B60010
+#define SPR_8314_REV10 0x80B70010
+
+#define SPR_8379E_REV10 0x80C20010
+#define SPR_8379_REV10 0x80C30010
+#define SPR_8378E_REV10 0x80C40010
+#define SPR_8378_REV10 0x80C50010
+#define SPR_8377E_REV10 0x80C60010
+#define SPR_8377_REV10 0x80C70010
/* SPCR - System Priority Configuration Register
*/
@@ -130,8 +141,8 @@
#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */
#define SPCR_TSEC2EP_SHIFT (31-31)
-#elif defined(CONFIG_MPC831X)
-/* SPCR bits - MPC831x specific */
+#elif defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
+/* SPCR bits - MPC831x and MPC837x specific */
#define SPCR_TSECDP 0x00003000 /* TSEC data priority */
#define SPCR_TSECDP_SHIFT (31-19)
#define SPCR_TSECEP 0x00000C00 /* TSEC emergency priority */
@@ -213,8 +224,8 @@
#define SICRL_URT_CTPR 0x06000000
#define SICRL_IRQ_CTPR 0x00C00000
-#elif defined(CONFIG_MPC831X)
-/* SICRL bits - MPC831x specific */
+#elif defined(CONFIG_MPC8313)
+/* SICRL bits - MPC8313 specific */
#define SICRL_LBC 0x30000000
#define SICRL_UART 0x0C000000
#define SICRL_SPI_A 0x03000000
@@ -225,7 +236,7 @@
#define SICRL_ETSEC1_A 0x0000000C
#define SICRL_ETSEC2_A 0x00000003
-/* SICRH bits - MPC831x specific */
+/* SICRH bits - MPC8313 specific */
#define SICRH_INTR_A 0x02000000
#define SICRH_INTR_B 0x00C00000
#define SICRH_IIC 0x00300000
@@ -242,6 +253,90 @@
#define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001
+#elif defined(CONFIG_MPC8315)
+/* SICRL bits - MPC8315 specific */
+#define SICRL_DMA_CH0 0xc0000000
+#define SICRL_DMA_SPI 0x30000000
+#define SICRL_UART 0x0c000000
+#define SICRL_IRQ4 0x02000000
+#define SICRL_IRQ5 0x01800000
+#define SICRL_IRQ6_7 0x00400000
+#define SICRL_IIC1 0x00300000
+#define SICRL_TDM 0x000c0000
+#define SICRL_TDM_SHARED 0x00030000
+#define SICRL_PCI_A 0x0000c000
+#define SICRL_ELBC_A 0x00003000
+#define SICRL_ETSEC1_A 0x000000c0
+#define SICRL_ETSEC1_B 0x00000030
+#define SICRL_ETSEC1_C 0x0000000c
+#define SICRL_TSEXPOBI 0x00000001
+
+/* SICRH bits - MPC8315 specific */
+#define SICRH_GPIO_0 0xc0000000
+#define SICRH_GPIO_1 0x30000000
+#define SICRH_GPIO_2 0x0c000000
+#define SICRH_GPIO_3 0x03000000
+#define SICRH_GPIO_4 0x00c00000
+#define SICRH_GPIO_5 0x00300000
+#define SICRH_GPIO_6 0x000c0000
+#define SICRH_GPIO_7 0x00030000
+#define SICRH_GPIO_8 0x0000c000
+#define SICRH_GPIO_9 0x00003000
+#define SICRH_GPIO_10 0x00000c00
+#define SICRH_GPIO_11 0x00000300
+#define SICRH_ETSEC2_A 0x000000c0
+#define SICRH_TSOBI1 0x00000002
+#define SICRH_TSOBI2 0x00000001
+
+#elif defined(CONFIG_MPC837X)
+/* SICRL bits - MPC837x specific */
+#define SICRL_USB_A 0xC0000000
+#define SICRL_USB_B 0x30000000
+#define SICRL_UART 0x0C000000
+#define SICRL_GPIO_A 0x02000000
+#define SICRL_GPIO_B 0x01000000
+#define SICRL_GPIO_C 0x00800000
+#define SICRL_GPIO_D 0x00400000
+#define SICRL_GPIO_E 0x00200000
+#define SICRL_GPIO_F 0x00180000
+#define SICRL_GPIO_G 0x00040000
+#define SICRL_GPIO_H 0x00020000
+#define SICRL_GPIO_I 0x00010000
+#define SICRL_GPIO_J 0x00008000
+#define SICRL_GPIO_K 0x00004000
+#define SICRL_GPIO_L 0x00003000
+#define SICRL_DMA_A 0x00000800
+#define SICRL_DMA_B 0x00000400
+#define SICRL_DMA_C 0x00000200
+#define SICRL_DMA_D 0x00000100
+#define SICRL_DMA_E 0x00000080
+#define SICRL_DMA_F 0x00000040
+#define SICRL_DMA_G 0x00000020
+#define SICRL_DMA_H 0x00000010
+#define SICRL_DMA_I 0x00000008
+#define SICRL_DMA_J 0x00000004
+#define SICRL_LDP_A 0x00000002
+#define SICRL_LDP_B 0x00000001
+
+/* SICRH bits - MPC837x specific */
+#define SICRH_DDR 0x80000000
+#define SICRH_TSEC1_A 0x10000000
+#define SICRH_TSEC1_B 0x08000000
+#define SICRH_TSEC2_A 0x00400000
+#define SICRH_TSEC2_B 0x00200000
+#define SICRH_TSEC2_C 0x00100000
+#define SICRH_TSEC2_D 0x00080000
+#define SICRH_TSEC2_E 0x00040000
+#define SICRH_TMR 0x00010000
+#define SICRH_GPIO2_A 0x00008000
+#define SICRH_GPIO2_B 0x00004000
+#define SICRH_GPIO2_C 0x00002000
+#define SICRH_GPIO2_D 0x00001000
+#define SICRH_GPIO2_E 0x00000C00
+#define SICRH_GPIO2_F 0x00000300
+#define SICRH_GPIO2_G 0x000000C0
+#define SICRH_GPIO2_H 0x00000030
+#define SICRH_SPI 0x00000003
#endif
/* SWCRR - System Watchdog Control Register
@@ -390,6 +485,14 @@
#define HRCWL_CE_TO_PLL_1X29 0x0000001D
#define HRCWL_CE_TO_PLL_1X30 0x0000001E
#define HRCWL_CE_TO_PLL_1X31 0x0000001F
+
+#elif defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
+#define HRCWL_SVCOD 0x30000000
+#define HRCWL_SVCOD_SHIFT 28
+#define HRCWL_SVCOD_DIV_4 0x00000000
+#define HRCWL_SVCOD_DIV_8 0x10000000
+#define HRCWL_SVCOD_DIV_2 0x20000000
+#define HRCWL_SVCOD_DIV_1 0x30000000
#endif
/* HRCWH - Hardware Reset Configuration Word High
@@ -436,11 +539,14 @@
#if defined(CONFIG_MPC834X)
#define HRCWH_ROM_LOC_PCI2 0x00200000
#endif
+#if defined(CONIFG_MPC837X)
+#define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000
+#endif
#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
-#if defined(CONFIG_MPC831X)
+#if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
@@ -489,8 +595,13 @@
/* RSR - Reset Status Register
*/
+#if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
+#define RSR_RSTSRC 0xF0000000 /* Reset source */
+#define RSR_RSTSRC_SHIFT 28
+#else
#define RSR_RSTSRC 0xE0000000 /* Reset source */
#define RSR_RSTSRC_SHIFT 29
+#endif
#define RSR_BSF 0x00010000 /* Boot seq. fail */
#define RSR_BSF_SHIFT 16
#define RSR_SWSR 0x00002000 /* software soft reset */
@@ -577,8 +688,8 @@
#define SCCR_PCICM 0x00010000
#define SCCR_PCICM_SHIFT 16
-/* SCCR bits - MPC8349 specific */
-#ifdef CONFIG_MPC834X
+#if defined(CONFIG_MPC834X)
+/* SCCR bits - MPC834x specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TSEC1CM_0 0x00000000
@@ -593,7 +704,19 @@
#define SCCR_TSEC2CM_2 0x20000000
#define SCCR_TSEC2CM_3 0x30000000
-#elif defined(CONFIG_MPC831X)
+/* The MPH must have the same clock ratio as DR, unless its clock disabled */
+#define SCCR_USBMPHCM 0x00c00000
+#define SCCR_USBMPHCM_SHIFT 22
+#define SCCR_USBDRCM 0x00300000
+#define SCCR_USBDRCM_SHIFT 20
+#define SCCR_USBCM 0x00f00000
+#define SCCR_USBCM_SHIFT 20
+#define SCCR_USBCM_0 0x00000000
+#define SCCR_USBCM_1 0x00500000
+#define SCCR_USBCM_2 0x00A00000
+#define SCCR_USBCM_3 0x00F00000
+
+#elif defined(CONFIG_MPC8313)
/* TSEC1 bits are for TSEC2 as well */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
@@ -606,17 +729,109 @@
#define SCCR_TSEC2ON 0x10000000
#define SCCR_TSEC2ON_SHIFT 28
-#endif
+#define SCCR_USBDRCM 0x00300000
+#define SCCR_USBDRCM_SHIFT 20
+#define SCCR_USBDRCM_0 0x00000000
+#define SCCR_USBDRCM_1 0x00100000
+#define SCCR_USBDRCM_2 0x00200000
+#define SCCR_USBDRCM_3 0x00300000
+
+#elif defined(CONFIG_MPC8315)
+/* SCCR bits - MPC8315 specific */
+#define SCCR_TSEC1CM 0xc0000000
+#define SCCR_TSEC1CM_SHIFT 30
+#define SCCR_TSEC1CM_0 0x00000000
+#define SCCR_TSEC1CM_1 0x40000000
+#define SCCR_TSEC1CM_2 0x80000000
+#define SCCR_TSEC1CM_3 0xC0000000
+
+#define SCCR_TSEC2CM 0x30000000
+#define SCCR_TSEC2CM_SHIFT 28
+#define SCCR_TSEC2CM_0 0x00000000
+#define SCCR_TSEC2CM_1 0x10000000
+#define SCCR_TSEC2CM_2 0x20000000
+#define SCCR_TSEC2CM_3 0x30000000
-#define SCCR_USBMPHCM 0x00c00000
-#define SCCR_USBMPHCM_SHIFT 22
#define SCCR_USBDRCM 0x00300000
#define SCCR_USBDRCM_SHIFT 20
+#define SCCR_USBDRCM_0 0x00000000
+#define SCCR_USBDRCM_1 0x00100000
+#define SCCR_USBDRCM_2 0x00200000
+#define SCCR_USBDRCM_3 0x00300000
+
+#define SCCR_PCIEXP1CM 0x00080000
+#define SCCR_PCIEXP2CM 0x00040000
+
+#define SCCR_SATA1CM 0x0000c000
+#define SCCR_SATA1CM_SHIFT 14
+#define SCCR_SATACM 0x0000f000
+#define SCCR_SATACM_SHIFT 8
+#define SCCR_SATACM_0 0x00000000
+#define SCCR_SATACM_1 0x00005000
+#define SCCR_SATACM_2 0x0000a000
+#define SCCR_SATACM_3 0x0000f000
+
+#define SCCR_TDMCM 0x000000c0
+#define SCCR_TDMCM_SHIFT 6
+#define SCCR_TDMCM_0 0x00000000
+#define SCCR_TDMCM_1 0x00000040
+#define SCCR_TDMCM_2 0x00000080
+#define SCCR_TDMCM_3 0x000000c0
+
+#elif defined(CONFIG_MPC837X)
+/* SCCR bits - MPC837x specific */
+#define SCCR_TSEC1CM 0xc0000000
+#define SCCR_TSEC1CM_SHIFT 30
+#define SCCR_TSEC1CM_0 0x00000000
+#define SCCR_TSEC1CM_1 0x40000000
+#define SCCR_TSEC1CM_2 0x80000000
+#define SCCR_TSEC1CM_3 0xC0000000
-#define SCCR_USBCM_0 0x00000000
-#define SCCR_USBCM_1 0x00500000
-#define SCCR_USBCM_2 0x00A00000
-#define SCCR_USBCM_3 0x00F00000
+#define SCCR_TSEC2CM 0x30000000
+#define SCCR_TSEC2CM_SHIFT 28
+#define SCCR_TSEC2CM_0 0x00000000
+#define SCCR_TSEC2CM_1 0x10000000
+#define SCCR_TSEC2CM_2 0x20000000
+#define SCCR_TSEC2CM_3 0x30000000
+
+#define SCCR_SDHCCM 0x0c000000
+#define SCCR_SDHCCM_SHIFT 26
+#define SCCR_SDHCCM_0 0x00000000
+#define SCCR_SDHCCM_1 0x04000000
+#define SCCR_SDHCCM_2 0x08000000
+#define SCCR_SDHCCM_3 0x0c000000
+
+#define SCCR_USBDRCM 0x00c00000
+#define SCCR_USBDRCM_SHIFT 22
+#define SCCR_USBDRCM_0 0x00000000
+#define SCCR_USBDRCM_1 0x00400000
+#define SCCR_USBDRCM_2 0x00800000
+#define SCCR_USBDRCM_3 0x00c00000
+
+#define SCCR_PCIEXP1CM 0x00300000
+#define SCCR_PCIEXP1CM_SHIFT 20
+#define SCCR_PCIEXP1CM_0 0x00000000
+#define SCCR_PCIEXP1CM_1 0x00100000
+#define SCCR_PCIEXP1CM_2 0x00200000
+#define SCCR_PCIEXP1CM_3 0x00300000
+
+#define SCCR_PCIEXP2CM 0x000c0000
+#define SCCR_PCIEXP2CM_SHIFT 18
+#define SCCR_PCIEXP2CM_0 0x00000000
+#define SCCR_PCIEXP2CM_1 0x00040000
+#define SCCR_PCIEXP2CM_2 0x00080000
+#define SCCR_PCIEXP2CM_3 0x000c0000
+
+/* All of the four SATA controllers must have the same clock ratio */
+#define SCCR_SATA1CM 0x000000c0
+#define SCCR_SATA1CM_SHIFT 6
+#define SCCR_SATACM 0x000000ff
+#define SCCR_SATACM_SHIFT 0
+#define SCCR_SATACM_0 0x00000000
+#define SCCR_SATACM_1 0x00000055
+#define SCCR_SATACM_2 0x000000aa
+#define SCCR_SATACM_3 0x000000ff
+#endif
/* CSn_BDNS - Chip Select memory Bounds Register
*/
@@ -860,7 +1075,7 @@
#define BR_MS_UPMA 0x00000080 /* UPMA */
#define BR_MS_UPMB 0x000000A0 /* UPMB */
#define BR_MS_UPMC 0x000000C0 /* UPMC */
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+#if !defined(CONFIG_MPC834X)
#define BR_ATOM 0x0000000C
#define BR_ATOM_SHIFT 2
#endif
@@ -869,7 +1084,7 @@
#if defined(CONFIG_MPC834X)
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
-#elif defined(CONFIG_MPC8360)
+#else
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
#endif
@@ -1255,7 +1470,7 @@
#define LTESR_CS 0x00080000
#define LTESR_CC 0x00000001
-/* DDR Control Driver Register
+/* DDRCDR - DDR Control Driver Register
*/
#define DDRCDR_EN 0x40000000
#define DDRCDR_PZ 0x3C000000
generated by cgit v1.1 at 2024-12-01 20:53:33 +0000