diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/cerf250.h | 14 | ||||
| -rw-r--r-- | include/configs/colibri_pxa270.h | 2 | ||||
| -rw-r--r-- | include/configs/cradle.h | 18 | ||||
| -rw-r--r-- | include/configs/csb226.h | 7 | ||||
| -rw-r--r-- | include/configs/delta.h | 267 | ||||
| -rw-r--r-- | include/configs/innokom.h | 8 | ||||
| -rw-r--r-- | include/configs/lubbock.h | 8 | ||||
| -rw-r--r-- | include/configs/palmld.h | 1 | ||||
| -rw-r--r-- | include/configs/palmtc.h | 1 | ||||
| -rw-r--r-- | include/configs/pleb2.h | 18 | ||||
| -rw-r--r-- | include/configs/pxa255_idp.h | 8 | ||||
| -rw-r--r-- | include/configs/trizepsiv.h | 1 | ||||
| -rw-r--r-- | include/configs/vpac270.h | 1 | ||||
| -rw-r--r-- | include/configs/wepep250.h | 199 | ||||
| -rw-r--r-- | include/configs/xaeniax.h | 9 | ||||
| -rw-r--r-- | include/configs/xm250.h | 9 | ||||
| -rw-r--r-- | include/configs/xsengine.h | 216 | ||||
| -rw-r--r-- | include/configs/zipitz2.h | 1 |
18 files changed, 69 insertions, 719 deletions
diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h index 98b69e3..a0726a9 100644 --- a/include/configs/cerf250.h +++ b/include/configs/cerf250.h @@ -38,6 +38,7 @@ #define CONFIG_CERF250 1 /* on Cerf PXA Board */ #define BOARD_LATE_INIT 1 #define CONFIG_BAUDRATE 38400 +#define CONFIG_SYS_TEXT_BASE 0x0 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ @@ -140,15 +141,9 @@ /* * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ #define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ @@ -187,6 +182,9 @@ #define CONFIG_SYS_PSSR_VAL 0x20 +#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 +#define CONFIG_SYS_CKEN 0x0 + /* * Memory settings */ @@ -196,6 +194,8 @@ #define CONFIG_SYS_MDCNFG_VAL 0x00001AC9 #define CONFIG_SYS_MDREFR_VAL 0x03CDC017 #define CONFIG_SYS_MDMRS_VAL 0x00000000 +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x00000000 /* * PCMCIA and CF Interfaces diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 5f457f8..afc1537 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -39,7 +39,7 @@ #define CONFIG_ENV_SIZE 0x4000 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) #define CONFIG_SYS_GBL_DATA_SIZE 128 - +#define CONFIG_SYS_TEXT_BASE 0x0 #define CONFIG_ENV_OVERWRITE /* override default environment */ #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/cradle.h b/include/configs/cradle.h index d1c1a48..3da3562 100644 --- a/include/configs/cradle.h +++ b/include/configs/cradle.h @@ -39,7 +39,7 @@ /* we will never enable dcache, because we have to setup MMU first */ #define CONFIG_SYS_NO_DCACHE - +#define CONFIG_SYS_TEXT_BASE 0x0 /* * Size of malloc() pool */ @@ -126,15 +126,9 @@ /* * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x01000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ #define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */ @@ -289,9 +283,9 @@ * Clocks, power control and interrupts */ #define CONFIG_SYS_PSSR_VAL 0x00000020 -#define CONFIG_SYS_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */ -#define CONFIG_SYS_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */ -#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */ +#define CONFIG_SYS_CCCR 0x00000141 /* 100 MHz memory, 200 MHz CPU */ +#define CONFIG_SYS_CKEN 0x00000060 /* FFUART and STUART enabled */ +#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */ /* FIXME * @@ -319,6 +313,8 @@ #define CONFIG_SYS_MDMRS_VAL 0x00000000 #define CONFIG_SYS_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */ #endif +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x00000000 /* * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init) diff --git a/include/configs/csb226.h b/include/configs/csb226.h index ae05734..72e47ce 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -45,7 +45,7 @@ /* we will never enable dcache, because we have to setup MMU first */ #define CONFIG_SYS_NO_DCACHE - +#define CONFIG_SYS_TEXT_BASE 0x0 /* * Hardware drivers */ @@ -458,6 +458,9 @@ #define CONFIG_SYS_PSSR_VAL 0x20 +#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 +#define CONFIG_SYS_CKEN 0x0 + /* * Memory settings */ @@ -468,6 +471,8 @@ #define CONFIG_SYS_MDCNFG_VAL 0x09a909a9 #define CONFIG_SYS_MDREFR_VAL 0x038ff030 #define CONFIG_SYS_MDMRS_VAL 0x00220022 +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x00000000 /* * PCMCIA and CF Interfaces diff --git a/include/configs/delta.h b/include/configs/delta.h deleted file mode 100644 index d53acbf..0000000 --- a/include/configs/delta.h +++ /dev/null @@ -1,267 +0,0 @@ -/* - * Configuation settings for the Delta board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */ -#define CONFIG_CPU_PXA320 -#define CONFIG_DELTA 1 /* Delta board */ - -/* #define CONFIG_LCD 1 */ -#ifdef CONFIG_LCD -#define CONFIG_SHARP_LM8V31 -#endif -#define BOARD_LATE_INIT 1 - -#undef CONFIG_SKIP_RELOCATE_UBOOT -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -#undef TURN_ON_ETHERNET -#ifdef TURN_ON_ETHERNET -# define CONFIG_DRIVER_SMC91111 1 -# define CONFIG_SMC91111_BASE 0x14000300 -# define CONFIG_SMC91111_EXT_PHY -# define CONFIG_SMC_USE_32_BIT -# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */ -#endif - -#define CONFIG_HARD_I2C 1 /* required for DA9030 access */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ -#define CONFIG_SYS_I2C_SLAVE 1 /* I2C controllers address */ -#define DA9030_I2C_ADDR 0x49 /* I2C address of DA9030 */ -#define CONFIG_SYS_DA9030_EXTON_DELAY 100000 /* wait x us after DA9030 reset via EXTON */ -#define CONFIG_SYS_I2C_INIT_BOARD 1 -/* #define CONFIG_HW_WATCHDOG 1 /\* Required for hitting the DA9030 WD *\/ */ - -#define DELTA_CHECK_KEYBD 1 /* check for keys pressed during boot */ -#define CONFIG_PREBOOT "\0" - -#ifdef DELTA_CHECK_KEYBD -# define KEYBD_DATALEN 4 /* we have four keys */ -# define KEYBD_KP_DKIN0 0x1 /* vol+ */ -# define KEYBD_KP_DKIN1 0x2 /* vol- */ -# define KEYBD_KP_DKIN2 0x3 /* multi */ -# define KEYBD_KP_DKIN5 0x4 /* SWKEY_GN */ -#endif /* DELTA_CHECK_KEYBD */ - -/* - * select serial console configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#ifdef TURN_ON_ETHERNET - -#define CONFIG_CMD_PING - -#else - -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_NAND -#define CONFIG_CMD_I2C - -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_IMLS - -#endif - -/* USB */ -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_DOS_PARTITION 1 - -#include <asm/arch/pxa-regs.h> /* for OHCI_REGS_BASE */ - -#undef CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE OHCI_REGS_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "delta" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 - -#define CONFIG_BOOTDELAY -1 -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_IPADDR 192.168.0.21 -#define CONFIG_SERVERIP 192.168.0.250 -#define CONFIG_BOOTCOMMAND "bootm 80000" -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" -#define CONFIG_CMDLINE_TAG -#define CONFIG_TIMESTAMP - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER 1 -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ -#else -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#endif -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -#define CONFIG_SYS_MEMTEST_START 0x80400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x80800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */ - -#define CONFIG_SYS_HZ 1000 - -/* Monahans Core Frequency */ -#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */ -#define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */ - - - /* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#ifdef CONFIG_MMC -#define CONFIG_PXA_MMC -#define CONFIG_CMD_MMC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#endif - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */ -#define PHYS_SDRAM_2 0x81000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */ -#define PHYS_SDRAM_3 0x82000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */ -#define PHYS_SDRAM_4 0x83000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */ - -#define CONFIG_SYS_DRAM_BASE 0x80000000 /* at CS0 */ -#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB Ram */ - -#undef CONFIG_SYS_SKIP_DRAM_SCRUB - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) - -/* - * NAND Flash - */ -#define CONFIG_SYS_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */ -#undef CONFIG_SYS_NAND1_BASE - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ - -/* nand timeout values */ -#define CONFIG_SYS_NAND_PROG_ERASE_TO 3000 -#define CONFIG_SYS_NAND_OTHER_TO 100 -#define CONFIG_SYS_NAND_SENDCMD_RETRY 3 -#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */ - -/* NAND Timing Parameters (in ns) */ -#define NAND_TIMING_tCH 10 -#define NAND_TIMING_tCS 0 -#define NAND_TIMING_tWH 20 -#define NAND_TIMING_tWP 40 - -#define NAND_TIMING_tRH 20 -#define NAND_TIMING_tRP 40 - -#define NAND_TIMING_tR 11123 -#define NAND_TIMING_tWHR 100 -#define NAND_TIMING_tAR 10 - -/* NAND debugging */ -#define CONFIG_SYS_DFC_DEBUG1 /* usefull */ -#undef CONFIG_SYS_DFC_DEBUG2 /* noisy */ -#undef CONFIG_SYS_DFC_DEBUG3 /* extremly noisy */ - -#define CONFIG_MTD_DEBUG -#define CONFIG_MTD_DEBUG_VERBOSE 1 - -#define CONFIG_SYS_NO_FLASH 1 - -#define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_OFFSET_REDUND 0x44000 -#define CONFIG_ENV_SIZE 0x4000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/innokom.h b/include/configs/innokom.h index 007cceb..01522cd 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -40,6 +40,8 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* for timer/console/ethernet */ +#define CONFIG_SYS_TEXT_BASE 0x0 + /* we will never enable dcache, because we have to setup MMU first */ #define CONFIG_SYS_NO_DCACHE @@ -347,6 +349,9 @@ */ #define CONFIG_SYS_PSSR_VAL 0x37 +#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 +#define CONFIG_SYS_CKEN 0x0 + /* * Memory settings * @@ -480,6 +485,9 @@ #define CONFIG_SYS_MCIO0_VAL 0x00000000 #define CONFIG_SYS_MCIO1_VAL 0x00000000 +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x00000000 + /* #define CSB226_USER_LED0 0x00000008 #define CSB226_USER_LED1 0x00000010 diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index 3a99ec2..62f9691 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -43,7 +43,7 @@ #define CONFIG_MMC #define BOARD_LATE_INIT 1 #define CONFIG_DOS_PARTITION - +#define CONFIG_SYS_TEXT_BASE 0x0 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* we will never enable dcache, because we have to setup MMU first */ @@ -202,6 +202,9 @@ #define CONFIG_SYS_PSSR_VAL 0x20 +#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 +#define CONFIG_SYS_CKEN 0x0 + /* * Memory settings */ @@ -212,6 +215,9 @@ #define CONFIG_SYS_MDREFR_VAL 0x00018018 #define CONFIG_SYS_MDMRS_VAL 0x00000000 +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x00000000 + /* * PCMCIA and CF Interfaces */ diff --git a/include/configs/palmld.h b/include/configs/palmld.h index 926728b..a2310a9 100644 --- a/include/configs/palmld.h +++ b/include/configs/palmld.h @@ -34,6 +34,7 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_MALLOC_LEN (128*1024) #define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_TEXT_BASE 0x0 #define CONFIG_BOOTCOMMAND \ "if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then " \ diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h index fe87648..40ab0bf 100644 --- a/include/configs/palmtc.h +++ b/include/configs/palmtc.h @@ -36,6 +36,7 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_MALLOC_LEN (128*1024) #define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_TEXT_BASE 0x0 #define CONFIG_BOOTCOMMAND \ "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \ diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h index 3b6e60a..b366f38 100644 --- a/include/configs/pleb2.h +++ b/include/configs/pleb2.h @@ -39,6 +39,7 @@ #undef CONFIG_LCD #undef CONFIG_MMC #define BOARD_LATE_INIT 1 +#define CONFIG_SYS_TEXT_BASE 0x0 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ @@ -155,15 +156,9 @@ /* * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ #define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ @@ -213,9 +208,9 @@ #define CONFIG_SYS_GAFR2_U_VAL 0x00000000 #define CONFIG_SYS_PSSR_VAL 0x20 -#define CONFIG_SYS_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */ -#define CONFIG_SYS_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */ -#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */ +#define CONFIG_SYS_CCCR 0x00000141 /* 100 MHz memory, 200 MHz CPU */ +#define CONFIG_SYS_CKEN 0x00000060 /* FFUART and STUART enabled */ +#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */ /* * Memory settings @@ -231,6 +226,9 @@ /* bits set in lowlevel_init.S */ #define CONFIG_SYS_MDMRS_VAL 0x00000000 +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x00000000 + /* * PCMCIA and CF Interfaces */ diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index 4581674..b4327c6 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -43,6 +43,7 @@ */ #undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */ #undef CONFIG_SKIP_RELOCATE_UBOOT /* define for developing */ +#define CONFIG_SYS_TEXT_BASE 0x0 /* * define the following to enable debug blinks. A debug blink function @@ -271,7 +272,7 @@ /* * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 1 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ @@ -317,6 +318,9 @@ #define CONFIG_SYS_PSSR_VAL 0x20 +#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 +#define CONFIG_SYS_CKEN 0x0 + /* * Memory settings */ @@ -326,6 +330,8 @@ #define CONFIG_SYS_MDCNFG_VAL 0x090009C9 #define CONFIG_SYS_MDREFR_VAL 0x0085C017 #define CONFIG_SYS_MDMRS_VAL 0x00220022 +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x00000000 /* * PCMCIA and CF Interfaces diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index 4743495..ac3566c 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -44,6 +44,7 @@ #define CONFIG_MMC 1 #define BOARD_LATE_INIT 1 +#define CONFIG_SYS_TEXT_BASE 0x0 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index c9d9c69..3107014 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -27,6 +27,7 @@ */ #define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ #define CONFIG_VPAC270 1 /* Voipac PXA270 board */ +#define CONFIG_SYS_TEXT_BASE 0x0 /* * Environment settings diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h deleted file mode 100644 index a961a27..0000000 --- a/include/configs/wepep250.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright (C) 2003 ETC s.r.o. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Written by Peter Figuli <peposh@etc.sk>, 2003. - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_PXA250 1 /* this is an PXA250 CPU */ -#define CONFIG_WEPEP250 1 /* config for wepep250 board */ -#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE - -/* - * Select serial console configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_BTUART 1 /* BTUART is default on WEP dev board */ -#define CONFIG_BAUDRATE 115200 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#undef CONFIG_CMD_CONSOLE -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_SOURCE - - -/* - * Boot options. Setting delay to -1 stops autostart count down. - * NOTE: Sending parameters to kernel depends on kernel version and - * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept - * parameters at all! Do not get confused by them so. - */ -#define CONFIG_BOOTDELAY -1 -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=32m console=ttyS01,115200n8" -#define CONFIG_BOOTCOMMAND "bootm 40000" - - -/* - * General options for u-boot. Modify to save memory foot print - */ -#define CONFIG_SYS_LONGHELP /* undef saves memory */ -#define CONFIG_SYS_PROMPT "WEP> " /* prompt string */ -#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */ -#define CONFIG_SYS_MAXARGS 16 /* max command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */ - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest test area */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 - -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Definitions related to passing arguments to kernel. - */ -#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ -#undef CONFIG_INITRD_TAG /* do not send initrd params */ -#undef CONFIG_VFD /* do not send framebuffer setup */ - - -/* - * Malloc pool need to host env + 128 Kb reserve for other allocations. - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) ) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -#define CONFIG_STACKSIZE (120<<10) /* stack size */ - -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */ -#endif - -/* - * SDRAM Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ -#define WEP_SDRAM_1 0xa0000000 /* SDRAM bank #1 */ -#define WEP_SDRAM_1_SIZE 0x02000000 /* 32 MB ( 2 chip ) */ -#define WEP_SDRAM_2 0xa2000000 /* SDRAM bank #2 */ -#define WEP_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define WEP_SDRAM_3 0xa8000000 /* SDRAM bank #3 */ -#define WEP_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define WEP_SDRAM_4 0xac000000 /* SDRAM bank #4 */ -#define WEP_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 -#define CONFIG_SYS_DRAM_SIZE 0x02000000 - -/* Uncomment used SDRAM chip */ -#define WEP_SDRAM_K4S281633 -/*#define WEP_SDRAM_K4S561633*/ - - -/* - * Configuration for FLASH memory - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ -#define WEP_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */ -#define WEP_FLASH_INTERLEAVE 2 /* ... made of 2 chips */ -#define WEP_FLASH_BANK_SIZE 0x2000000 /* size of one flash bank*/ -#define WEP_FLASH_SECT_SIZE 0x0040000 /* size of erase sector */ -#define WEP_FLASH_BASE 0x0000000 /* location of flash memory */ -#define WEP_FLASH_UNLOCK 1 /* perform hw unlock first */ - - -/* This should be defined if CFI FLASH device is present. Actually benefit - is not so clear to me. In other words we can provide more informations - to user, but this expects more complex flash handling we do not provide - now.*/ -#undef CONFIG_SYS_FLASH_CFI - -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Erase operation */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Write operation */ - -#define CONFIG_SYS_FLASH_BASE WEP_FLASH_BASE - -/* - * This is setting for JFFS2 support in u-boot. - * Right now there is no gain for user, but later on booting kernel might be - * possible. Consider using XIP kernel running from flash to save RAM - * footprint. - * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. - */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_FIRST_SECTOR 5 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -/* - * Environment setup. Definitions of monitor location and size with - * definition of environment setup ends up in 2 possibilities. - * 1. Embeded environment - in u-boot code is space for environment - * 2. Environment is read from predefined sector of flash - * Right now we support 2. possiblity, but expecting no env placed - * on mentioned address right now. This also needs to provide whole - * sector for it - for us 256Kb is really waste of memory. U-boot uses - * default env. and until kernel parameters could be sent to kernel - * env. has no sense to us. - */ - -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128kb ( 1 flash sector ) */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x20000 /* absolute address for now */ -#define CONFIG_ENV_SIZE 0x2000 - -#define PHYS_SDRAM_1 WEP_SDRAM_1 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) - -#undef CONFIG_ENV_OVERWRITE /* env is not writable now */ - -/* - * Well this has to be defined, but on the other hand it is used differently - * one may expect. For instance loadb command do not cares :-) - * So advice is - do not relay on this... - */ -#define CONFIG_SYS_LOAD_ADDR 0x40000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h index 67d4106..18b68fa 100644 --- a/include/configs/xaeniax.h +++ b/include/configs/xaeniax.h @@ -42,6 +42,7 @@ */ #define CONFIG_PXA250 1 /* This is an PXA255 CPU */ #define CONFIG_XAENIAX 1 /* on a xaeniax board */ +#define CONFIG_SYS_TEXT_BASE 0x0 #define BOARD_LATE_INIT 1 @@ -437,8 +438,9 @@ */ #define CONFIG_SYS_PSSR_VAL 0x00000030 -#define CONFIG_SYS_CKEN_VAL 0x00000080 /* */ -#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */ +#define CONFIG_SYS_CKEN 0x00000080 /* */ +#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */ +#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 /* @@ -562,6 +564,9 @@ */ #define CONFIG_SYS_MDMRS_VAL 0x00320032 +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x00000000 + /* * PCMCIA and CF Interfaces */ diff --git a/include/configs/xm250.h b/include/configs/xm250.h index 2ff9a28..ea52454 100644 --- a/include/configs/xm250.h +++ b/include/configs/xm250.h @@ -35,6 +35,7 @@ #define CONFIG_PXA250 1 /* This is an PXA250 CPU */ #define CONFIG_XM250 1 /* on a MicroSys XM250 Board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define CONFIG_SYS_TEXT_BASE 0x0 /* we will never enable dcache, because we have to setup MMU first */ #define CONFIG_SYS_NO_DCACHE @@ -322,9 +323,9 @@ * Clocks, power control and interrupts */ #define CONFIG_SYS_PSSR_VAL 0x00000030 -#define CONFIG_SYS_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */ -#define CONFIG_SYS_CKEN_VAL 0x000141ec /* FFUART and STUART enabled */ -#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */ +#define CONFIG_SYS_CCCR 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */ +#define CONFIG_SYS_CKEN 0x000141ec /* FFUART and STUART enabled */ +#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */ /* FIXME * @@ -343,6 +344,8 @@ #define CONFIG_SYS_MDCNFG_VAL 0x000009c9 #define CONFIG_SYS_MDMRS_VAL 0x00220022 #define CONFIG_SYS_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in lowlevel_init.S */ +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x00000000 /* * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init) diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h deleted file mode 100644 index 9606b53..0000000 --- a/include/configs/xsengine.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ -#define CONFIG_XSENGINE 1 -#define CONFIG_MMC 1 -#define CONFIG_DOS_PARTITION 1 -#define BOARD_LATE_INIT 1 -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE - -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ - -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ -#define CONFIG_SYS_DRAM_BASE 0xa0000000 -#define CONFIG_SYS_DRAM_SIZE 0x04000000 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) - -/* FLASH organization */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x00000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 127 KB sectors */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/* - * JFFS2 partitions - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=xsengine-0" -#define MTDPARTS_DEFAULT "mtdparts=xsengine-0:256k(uboot),1m(kernel1),8m(kernel2)" -*/ - -/* Environment settings */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector (after monitor)*/ -#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Size of the Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* 16kB Total Size of Environment Sector */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (75*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (50*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* Hardware drivers */ -#define CONFIG_NET_MULTI -#define CONFIG_SMC91111 -#define CONFIG_SMC91111_BASE 0x04000300 -#define CONFIG_SMC_USE_32_BIT 1 - -/* select serial console configuration */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_BAUDRATE 115200 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_FAT -#define CONFIG_CMD_PING -#define CONFIG_CMD_JFFS2 - - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.1.50 -#define CONFIG_SERVERIP 192.168.1.2 -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200" -#define CONFIG_CMDLINE_TAG - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_HUSH_PARSER 1 -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "XS-Engine u-boot> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_MEMTEST_START 0xA0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xA0800000 /* 4 ... 8 MB in DRAM */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */ -#define CONFIG_SYS_LOAD_ADDR 0xA0000000 /* load kernel to this address */ - -#ifdef CONFIG_MMC -#define CONFIG_PXA_MMC -#define CONFIG_CMD_MMC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#endif - -/* Stack sizes - The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* GP set register */ -#define CONFIG_SYS_GPSR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */ -#define CONFIG_SYS_GPSR1_VAL 0x00020000 /* nPWE */ -#define CONFIG_SYS_GPSR2_VAL 0x0000C000 /* CS2, CS3 */ - -/* GP clear register */ -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x00000000 -#define CONFIG_SYS_GPCR2_VAL 0x00000000 - -/* GP direction register */ -#define CONFIG_SYS_GPDR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */ -#define CONFIG_SYS_GPDR1_VAL 0x00022A80 /* nPWE, FFUART + BTUART pins */ -#define CONFIG_SYS_GPDR2_VAL 0x0000C000 /* CS2, CS3 */ - -/* GP rising edge detect register */ -#define CONFIG_SYS_GRER0_VAL 0x00000000 -#define CONFIG_SYS_GRER1_VAL 0x00000000 -#define CONFIG_SYS_GRER2_VAL 0x00000000 - -/* GP falling edge detect register */ -#define CONFIG_SYS_GFER0_VAL 0x00000000 -#define CONFIG_SYS_GFER1_VAL 0x00000000 -#define CONFIG_SYS_GFER2_VAL 0x00000000 - -/* GP alternate function register */ -#define CONFIG_SYS_GAFR0_L_VAL 0x80000000 /* CS1 */ -#define CONFIG_SYS_GAFR0_U_VAL 0x00000010 /* RDY */ -#define CONFIG_SYS_GAFR1_L_VAL 0x09988050 /* FFUART + BTUART pins */ -#define CONFIG_SYS_GAFR1_U_VAL 0x00000008 /* nPWE */ -#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 /* CS2, CS3 */ -#define CONFIG_SYS_GAFR2_U_VAL 0x00000000 - -#define CONFIG_SYS_PSSR_VAL 0x00000020 /* Power manager sleep status */ -#define CONFIG_SYS_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU */ -#define CONFIG_SYS_CKEN_VAL 0x000000C0 /* BTUART and FFUART enabled */ -#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */ - -/* Memory settings */ -#define CONFIG_SYS_MSC0_VAL 0x25F425F0 - -/* MDCNFG: SDRAM Configuration Register */ -#define CONFIG_SYS_MDCNFG_VAL 0x000009C9 - -/* MDREFR: SDRAM Refresh Control Register */ -#define CONFIG_SYS_MDREFR_VAL 0x00018018 - -/* MDMRS: Mode Register Set Configuration Register */ -#define CONFIG_SYS_MDMRS_VAL 0x00220022 - -#endif /* __CONFIG_H */ diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index ce65d1f..48537e3 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -27,6 +27,7 @@ */ #define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ #define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */ +#define CONFIG_SYS_TEXT_BASE 0x0 #undef BOARD_LATE_INIT #undef CONFIG_SKIP_RELOCATE_UBOOT |