diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/commproc.h | 55 | ||||
| -rw-r--r-- | include/configs/QS823.h | 571 | ||||
| -rw-r--r-- | include/configs/QS850.h | 571 | ||||
| -rw-r--r-- | include/configs/QS860T.h | 413 | ||||
| -rw-r--r-- | include/flash.h | 5 |
5 files changed, 1615 insertions, 0 deletions
diff --git a/include/commproc.h b/include/commproc.h index 63dcc4c..3da804f 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -1216,6 +1216,60 @@ typedef struct scc_enet { #endif /* CONFIG_NETVIA */ +/*** QS850/QS823 ***************************************************/ + +#if defined(CONFIG_QS850) || defined(CONFIG_QS823) +#undef FEC_ENET /* Don't use FEC for EThernet */ + +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 + +#define PA_ENET_RXD ((ushort)0x0004) /* RXD on PA13 (Pin D9) */ +#define PA_ENET_TXD ((ushort)0x0008) /* TXD on PA12 (Pin D7) */ +#define PC_ENET_RENA ((ushort)0x0080) /* RENA on PC8 (Pin D12) */ +#define PC_ENET_CLSN ((ushort)0x0040) /* CLSN on PC9 (Pin C12) */ +#define PA_ENET_TCLK ((ushort)0x0200) /* TCLK on PA6 (Pin D8) */ +#define PA_ENET_RCLK ((ushort)0x0800) /* RCLK on PA4 (Pin D10) */ +#define PB_ENET_TENA ((uint)0x00002000) /* TENA on PB18 (Pin D11) */ +#define PC_ENET_LBK ((ushort)0x0010) /* Loopback control on PC11 (Pin B14) */ +#define PC_ENET_LI ((ushort)0x0020) /* Link Integrity control PC10 (A15) */ +#define PC_ENET_SQE ((ushort)0x0100) /* SQE Disable control PC7 (B15) */ + +/* SCC2 TXCLK from CLK2 + * SCC2 RXCLK from CLK4 + * SCC2 Connected to NMSI */ +#define SICR_ENET_MASK ((uint)0x00007F00) +#define SICR_ENET_CLKRT ((uint)0x00003D00) + +#endif /* CONFIG_QS850/QS823 */ + +/*** QS860T ***************************************************/ + +#ifdef CONFIG_QS860T +#ifdef CONFIG_FEC_ENET +#define FEC_ENET /* use FEC for EThernet */ +#endif /* CONFIG_FEC_ETHERNET */ + +/* This ENET stuff is for GTH 10 Mbit ( SCC ) */ +#define PROFF_ENET PROFF_SCC1 +#define CPM_CR_ENET CPM_CR_CH_SCC1 +#define SCC_ENET 0 + +#define PA_ENET_RXD ((ushort)0x0001) /* PA15 */ +#define PA_ENET_TXD ((ushort)0x0002) /* PA14 */ +#define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */ +#define PA_ENET_RCLK ((ushort)0x0200) /* PA6 */ +#define PB_ENET_TENA ((uint)0x00001000) /* PB19 */ +#define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */ +#define PC_ENET_RENA ((ushort)0x0020) /* PC10 */ + +#define SICR_ENET_MASK ((uint)0x000000ff) +/* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */ +#define SICR_ENET_CLKRT ((uint)0x0000003D) + +#endif /* CONFIG_QS860T */ + /*** RPXCLASSIC *****************************************************/ #ifdef CONFIG_RPXCLASSIC @@ -1452,6 +1506,7 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00002e00) #endif /* CONFIG_V37 */ + /*********************************************************************/ /* SCC Event register as used by Ethernet. diff --git a/include/configs/QS823.h b/include/configs/QS823.h new file mode 100644 index 0000000..235bc48 --- /dev/null +++ b/include/configs/QS823.h @@ -0,0 +1,571 @@ +/* + * (C) Copyright 2003 + * MuLogic B.V. + * + * (C) Copyright 2002 + * Simple Network Magic Corporation + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* various debug settings */ +#undef CFG_DEVICE_NULLDEV /* null device */ +#undef CONFIG_SILENT_CONSOLE /* silent console */ +#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */ +#undef DEBUG /* debug output code */ +#undef DEBUG_FLASH /* debug flash code */ +#undef FLASH_DEBUG /* debug fash code */ +#undef DEBUG_ENV /* debug environment code */ + +#define CFG_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ +#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ +#define CONFIG_QS823 1 /* ...on a QS823 module */ +#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */ + +/* Select the target clock speed */ +#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */ +#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */ +#undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */ +#define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */ +#undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */ + +#ifdef CONFIG_CLOCK_16MHZ +#define CONFIG_CLOCK_MULT 512 +#endif + +#ifdef CONFIG_CLOCK_33MHZ +#define CONFIG_CLOCK_MULT 1024 +#endif + +#ifdef CONFIG_CLOCK_50MHZ +#define CONFIG_CLOCK_MULT 1525 +#endif + +#ifdef CONFIG_CLOCK_66MHZ +#define CONFIG_CLOCK_MULT 2048 +#endif + +#ifdef CONFIG_CLOCK_80MHZ +#define CONFIG_CLOCK_MULT 2441 +#endif + +/* choose flash size, 4Mb or 8Mb */ +#define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */ +#undef CONFIG_FLASH_8MB /* board has 8Mb flash */ + +#define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */ + +#undef CONFIG_8xx_CONS_SMC1 +#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ + +#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ + +/* Define default IP addresses */ +#define CONFIG_IPADDR 192.168.1.99 /* own ip address */ +#define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */ + +/* message to say directly after booting */ +#define CONFIG_PREBOOT "echo '';" \ + "echo 'type:';" \ + "echo 'run boot_nfs to boot to NFS';" \ + "echo 'run boot_flash to boot to flash';" \ + "echo '';" \ + "echo 'run flash_rootfs to install a new rootfs';" \ + "echo 'run flash_env to clear the env sector';" \ + "echo 'run flash_rw to clear the rw fs';" \ + "echo 'run flash_uboot to install a new u-boot';" \ + "echo 'run flash_kernel to install a new kernel';" + +/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTCOMMAND "run boot_nfs" + +#undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */ + +/* Our flash filesystem looks like this + * + * 4Mb board: + * ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb) + * ffec 0000 - ffed ffff read-write filesystem (ext2) + * ffee 0000 - ffef ffff environment + * fff0 0000 - fff1 ffff u-boot + * fff2 0000 - ffff ffff linux kernel + * + * 8Mb board: + * ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb) + * ffec 0000 - ffed ffff read-write filesystem (ext2) + * ffee 0000 - ffef ffff environment + * fff0 0000 - fff1 ffff u-boot + * fff2 0000 - ffff ffff linux kernel + * + */ + +/* environment for 4Mb board */ +#ifdef CONFIG_FLASH_4MB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "serial#=QS823\0" \ + "hostname=qs823\0" \ + "netdev=eth0\0" \ + "ethaddr=00:01:02:B4:36:56\0" \ + "rootpath=/exports/rootfs\0" \ + "mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ + /* fill in variables */ \ + "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ + "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ + "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ + /* commands */ \ + "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ + "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ + /* reinstall flash parts */ \ + "flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \ + "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ + "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ + "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \ + "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" +#endif /* CONFIG_FLASH_4MB */ + +/* environment for 8Mb board */ +#ifdef CONFIG_FLASH_8MB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "serial#=QS823\0" \ + "hostname=qs823\0" \ + "netdev=eth0\0" \ + "ethaddr=00:01:02:B4:36:56\0" \ + "rootpath=/exports/rootfs\0" \ + "mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ + /* fill in variables */ \ + "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ + "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ + "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ + /* commands */ \ + "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ + "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ + /* reinstall flash parts */ \ + "flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \ + "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ + "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ + "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \ + "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" +#endif /* CONFIG_FLASH_8MB */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_STATUS_LED /* Status LED disabled */ +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#undef CONFIG_MAC_PARTITION +#undef CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_BOOTD | \ + CFG_CMD_CONSOLE | \ + CFG_CMD_DATE | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IMMAP | \ + CFG_CMD_MEMORY | \ + CFG_CMD_NET | \ + CFG_CMD_RUN) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/*----------------------------------------------------------------------- + * Environment variable storage is in FLASH, one sector before U-boot + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */ +#define CFG_ENV_SIZE 0x2000 /* 8kb */ +#define CFG_ENV_ADDR 0xffee0000 /* address of env sector */ + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#define CFG_PROMPT_HUSH_PS2 "> " + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x400000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */ + +#define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */ +#define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */ + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MONITOR_BASE 0xFFF00000 /* U-boot location */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * TODO flash parameters + * FLASH organization for Intel Strataflash + */ +#undef CFG_FLASH_16BIT /* 32-bit wide flash memory */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ + +#ifdef CONFIG_WATCHDOG +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + */ +#define CFG_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + */ + +/* MF (Multiplication Factor of SPLL) */ +/* Sets the QS823 to specified clock from 32KHz clock at EXTAL. */ +#define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20) +#define CFG_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + */ +#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) +#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00) +#define CFG_BRGCLK_PRESCALE 1 +#endif + +#if defined(CONFIG_CLOCK_66MHZ) +#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01) +#define CFG_BRGCLK_PRESCALE 4 +#endif + +#if defined(CONFIG_CLOCK_80MHZ) +#define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01) +#define CFG_BRGCLK_PRESCALE 4 +#endif + +#define SCCR_MASK CFG_SCCR + +/*----------------------------------------------------------------------- + * Debug Enable Register + * 0x73E67C0F - All interrupts handled by BDM + * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM + *----------------------------------------------------------------------- +#define CFG_DER 0x73E67C0F +#define CFG_DER 0x0082400F + + #------------------------------------------------------------------------- + # Program the Debug Enable Register (DER). This register provides the user + # with the reason for entering into the debug mode. We want all conditions + # to end up as an exception. We don't want to enter into debug mode for + # any condition. See the back of of the Development Support section of the + # MPC860 User Manual for a description of this register. + #------------------------------------------------------------------------- +*/ +#define CFG_DER 0 + +/*----------------------------------------------------------------------- + * Memory Controller Initialization Constants + *----------------------------------------------------------------------- + */ + +/* + * BR0 and OR0 (AMD dual FLASH devices) + * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) + */ +#define CFG_PRELIM_OR_AM +#define CFG_OR_TIMING_FLASH + +/* + *----------------------------------------------------------------------- + * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32) + * flash that resides on the QS823. + *----------------------------------------------------------------------- + */ + +/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */ +/* represents a minumum 32K block size. */ +#define vBR0_BA ((0xFF80 << 16) + (0 << 15)) +#define CFG_BR0_PRELIM (vBR0_BA | BR_V) + +/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */ +/* which defines a 8 Mbyte memory block. */ +#define vOR0_AM ((0xFF80 << 16) + (0 << 15)) + +#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ) +/* 0101 = Add a 5 clock cycle wait state */ +#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK) +#endif + +#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ) +/* 0011 = Add a 3 clock cycle wait state */ +/* 29.8ns clock * (3 + 2) = 149ns cycle time */ +#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK) +#endif + +#if defined(CONFIG_CLOCK_16MHZ) +/* 0010 = Add a 2 clock cycle wait state */ +#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK) +#endif + +/* + * BR1 and OR1 (SDRAM) + * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) + * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation) + * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) + * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) + */ + +#define SDRAM_BASE 0x00000000 /* SDRAM bank */ +#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ + +/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which + * represents a 128 Mbyte block the DRAM in + * this address base. + */ +#define vOR1_AM ((0xF800 << 16) + (0 << 15)) +#define vBR1_BA ((0x0000 << 16) + (0 << 15)) +#define CFG_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI) +#define CFG_BR1 (vBR1_BA | BR_MS_UPMA | BR_V) + +/* Machine A Mode Register */ + +/* PTA Periodic Timer A */ + +#if defined(CONFIG_CLOCK_80MHZ) +#define vMAMR_PTA (19 << 24) +#endif + +#if defined(CONFIG_CLOCK_66MHZ) +#define vMAMR_PTA (16 << 24) +#endif + +#if defined(CONFIG_CLOCK_50MHZ) +#define vMAMR_PTA (195 << 24) +#endif + +#if defined(CONFIG_CLOCK_33MHZ) +#define vMAMR_PTA (131 << 24) +#endif + +#if defined(CONFIG_CLOCK_16MHZ) +#define vMAMR_PTA (65 << 24) +#endif + +/* For boards with 16M of SDRAM */ +#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ +#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ +MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* For boards with 32M of SDRAM */ +#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */ +#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ +MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* Memory Periodic Timer Prescaler Register */ + +#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ) +/* Divide by 32 */ +#define CFG_MPTPR 0x02 +#endif + +#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) +/* Divide by 16 */ +#define CFG_MPTPR 0x04 +#endif + +/* + * BR2 and OR2 (Unused) + * Base address = 0xF020_0000 - 0xF020_0FFF + * + */ +#define CFG_OR2_PRELIM 0xFFF00000 +#define CFG_BR2_PRELIM 0xF0200000 + +/* + * BR3 and OR3 (External Bus CS3) + * Base address = 0xF030_0000 - 0xF030_0FFF + * + */ +#define CFG_OR3_PRELIM 0xFFF00000 +#define CFG_BR3_PRELIM 0xF0300000 + +/* + * BR4 and OR4 (External Bus CS3) + * Base address = 0xF040_0000 - 0xF040_0FFF + * + */ +#define CFG_OR4_PRELIM 0xFFF00000 +#define CFG_BR4_PRELIM 0xF0400000 + + +/* + * BR4 and OR4 (External Bus CS3) + * Base address = 0xF050_0000 - 0xF050_0FFF + * + */ +#define CFG_OR5_PRELIM 0xFFF00000 +#define CFG_BR5_PRELIM 0xF0500000 + +/* + * BR6 and OR6 (Unused) + * Base address = 0xF060_0000 - 0xF060_0FFF + * + */ +#define CFG_OR6_PRELIM 0xFFF00000 +#define CFG_BR6_PRELIM 0xF0600000 + +/* + * BR7 and OR7 (Unused) + * Base address = 0xF070_0000 - 0xF070_0FFF + * + */ +#define CFG_OR7_PRELIM 0xFFF00000 +#define CFG_BR7_PRELIM 0xF0700000 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Sanity checks + */ +#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) +#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/QS850.h b/include/configs/QS850.h new file mode 100644 index 0000000..967582b --- /dev/null +++ b/include/configs/QS850.h @@ -0,0 +1,571 @@ +/* + * (C) Copyright 2003 + * MuLogic B.V. + * + * (C) Copyright 2002 + * Simple Network Magic Corporation + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* various debug settings */ +#undef CFG_DEVICE_NULLDEV /* null device */ +#undef CONFIG_SILENT_CONSOLE /* silent console */ +#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */ +#undef DEBUG /* debug output code */ +#undef DEBUG_FLASH /* debug flash code */ +#undef FLASH_DEBUG /* debug fash code */ +#undef DEBUG_ENV /* debug environment code */ + +#define CFG_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ +#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ +#define CONFIG_QS850 1 /* ...on a QS850 module */ +#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */ + +/* Select the target clock speed */ +#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */ +#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */ +#undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */ +#define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */ +#undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */ + +#ifdef CONFIG_CLOCK_16MHZ +#define CONFIG_CLOCK_MULT 512 +#endif + +#ifdef CONFIG_CLOCK_33MHZ +#define CONFIG_CLOCK_MULT 1024 +#endif + +#ifdef CONFIG_CLOCK_50MHZ +#define CONFIG_CLOCK_MULT 1525 +#endif + +#ifdef CONFIG_CLOCK_66MHZ +#define CONFIG_CLOCK_MULT 2048 +#endif + +#ifdef CONFIG_CLOCK_80MHZ +#define CONFIG_CLOCK_MULT 2441 +#endif + +/* choose flash size, 4Mb or 8Mb */ +#define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */ +#undef CONFIG_FLASH_8MB /* board has 8Mb flash */ + +#define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ + +#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ + +/* Define default IP addresses */ +#define CONFIG_IPADDR 192.168.1.99 /* own ip address */ +#define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */ + +/* message to say directly after booting */ +#define CONFIG_PREBOOT "echo '';" \ + "echo 'type:';" \ + "echo 'run boot_nfs to boot to NFS';" \ + "echo 'run boot_flash to boot to flash';" \ + "echo '';" \ + "echo 'run flash_rootfs to install a new rootfs';" \ + "echo 'run flash_env to clear the env sector';" \ + "echo 'run flash_rw to clear the rw fs';" \ + "echo 'run flash_uboot to install a new u-boot';" \ + "echo 'run flash_kernel to install a new kernel';" + +/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTCOMMAND "run boot_nfs" + +#undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */ + +/* Our flash filesystem looks like this + * + * 4Mb board: + * ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb) + * ffec 0000 - ffed ffff read-write filesystem (ext2) + * ffee 0000 - ffef ffff environment + * fff0 0000 - fff1 ffff u-boot + * fff2 0000 - ffff ffff linux kernel + * + * 8Mb board: + * ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb) + * ffec 0000 - ffed ffff read-write filesystem (ext2) + * ffee 0000 - ffef ffff environment + * fff0 0000 - fff1 ffff u-boot + * fff2 0000 - ffff ffff linux kernel + * + */ + +/* environment for 4Mb board */ +#ifdef CONFIG_FLASH_4MB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "serial#=QS850\0" \ + "hostname=qs850\0" \ + "netdev=eth0\0" \ + "ethaddr=00:01:02:B4:36:56\0" \ + "rootpath=/exports/rootfs\0" \ + "mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ + /* fill in variables */ \ + "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ + "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ + "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ + /* commands */ \ + "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ + "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ + /* reinstall flash parts */ \ + "flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \ + "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ + "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ + "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \ + "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" +#endif /* CONFIG_FLASH_4MB */ + +/* environment for 8Mb board */ +#ifdef CONFIG_FLASH_8MB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "serial#=QS850\0" \ + "hostname=qs850\0" \ + "netdev=eth0\0" \ + "ethaddr=00:01:02:B4:36:56\0" \ + "rootpath=/exports/rootfs\0" \ + "mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ + /* fill in variables */ \ + "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ + "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ + "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ + /* commands */ \ + "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ + "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ + /* reinstall flash parts */ \ + "flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \ + "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ + "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ + "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \ + "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" +#endif /* CONFIG_FLASH_8MB */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_STATUS_LED /* Status LED disabled */ +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#undef CONFIG_MAC_PARTITION +#undef CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_BOOTD | \ + CFG_CMD_CONSOLE | \ + CFG_CMD_DATE | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IMMAP | \ + CFG_CMD_MEMORY | \ + CFG_CMD_NET | \ + CFG_CMD_RUN) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/*----------------------------------------------------------------------- + * Environment variable storage is in FLASH, one sector before U-boot + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */ +#define CFG_ENV_SIZE 0x2000 /* 8kb */ +#define CFG_ENV_ADDR 0xffee0000 /* address of env sector */ + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#define CFG_PROMPT_HUSH_PS2 "> " + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x400000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */ + +#define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */ +#define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */ + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MONITOR_BASE 0xFFF00000 /* U-boot location */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * TODO flash parameters + * FLASH organization for Intel Strataflash + */ +#undef CFG_FLASH_16BIT /* 32-bit wide flash memory */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ + +#ifdef CONFIG_WATCHDOG +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + */ +#define CFG_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + */ + +/* MF (Multiplication Factor of SPLL) */ +/* Sets the QS850 to specified clock from 32KHz clock at EXTAL. */ +#define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20) +#define CFG_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + */ +#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) +#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00) +#define CFG_BRGCLK_PRESCALE 1 +#endif + +#if defined(CONFIG_CLOCK_66MHZ) +#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01) +#define CFG_BRGCLK_PRESCALE 4 +#endif + +#if defined(CONFIG_CLOCK_80MHZ) +#define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01) +#define CFG_BRGCLK_PRESCALE 4 +#endif + +#define SCCR_MASK CFG_SCCR + +/*----------------------------------------------------------------------- + * Debug Enable Register + * 0x73E67C0F - All interrupts handled by BDM + * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM + *----------------------------------------------------------------------- +#define CFG_DER 0x73E67C0F +#define CFG_DER 0x0082400F + + #------------------------------------------------------------------------- + # Program the Debug Enable Register (DER). This register provides the user + # with the reason for entering into the debug mode. We want all conditions + # to end up as an exception. We don't want to enter into debug mode for + # any condition. See the back of of the Development Support section of the + # MPC860 User Manual for a description of this register. + #------------------------------------------------------------------------- +*/ +#define CFG_DER 0 + +/*----------------------------------------------------------------------- + * Memory Controller Initialization Constants + *----------------------------------------------------------------------- + */ + +/* + * BR0 and OR0 (AMD dual FLASH devices) + * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) + */ +#define CFG_PRELIM_OR_AM +#define CFG_OR_TIMING_FLASH + +/* + *----------------------------------------------------------------------- + * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32) + * flash that resides on the QS850. + *----------------------------------------------------------------------- + */ + +/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */ +/* represents a minumum 32K block size. */ +#define vBR0_BA ((0xFF80 << 16) + (0 << 15)) +#define CFG_BR0_PRELIM (vBR0_BA | BR_V) + +/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */ +/* which defines a 8 Mbyte memory block. */ +#define vOR0_AM ((0xFF80 << 16) + (0 << 15)) + +#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ) +/* 0101 = Add a 5 clock cycle wait state */ +#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK) +#endif + +#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ) +/* 0011 = Add a 3 clock cycle wait state */ +/* 29.8ns clock * (3 + 2) = 149ns cycle time */ +#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK) +#endif + +#if defined(CONFIG_CLOCK_16MHZ) +/* 0010 = Add a 2 clock cycle wait state */ +#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK) +#endif + +/* + * BR1 and OR1 (SDRAM) + * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) + * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation) + * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) + * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) + */ + +#define SDRAM_BASE 0x00000000 /* SDRAM bank */ +#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ + +/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which + * represents a 128 Mbyte block the DRAM in + * this address base. + */ +#define vOR1_AM ((0xF800 << 16) + (0 << 15)) +#define vBR1_BA ((0x0000 << 16) + (0 << 15)) +#define CFG_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI) +#define CFG_BR1 (vBR1_BA | BR_MS_UPMA | BR_V) + +/* Machine A Mode Register */ + +/* PTA Periodic Timer A */ + +#if defined(CONFIG_CLOCK_80MHZ) +#define vMAMR_PTA (19 << 24) +#endif + +#if defined(CONFIG_CLOCK_66MHZ) +#define vMAMR_PTA (16 << 24) +#endif + +#if defined(CONFIG_CLOCK_50MHZ) +#define vMAMR_PTA (195 << 24) +#endif + +#if defined(CONFIG_CLOCK_33MHZ) +#define vMAMR_PTA (131 << 24) +#endif + +#if defined(CONFIG_CLOCK_16MHZ) +#define vMAMR_PTA (65 << 24) +#endif + +/* For boards with 16M of SDRAM */ +#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ +#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ +MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* For boards with 32M of SDRAM */ +#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */ +#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ +MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* Memory Periodic Timer Prescaler Register */ + +#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ) +/* Divide by 32 */ +#define CFG_MPTPR 0x02 +#endif + +#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) +/* Divide by 16 */ +#define CFG_MPTPR 0x04 +#endif + +/* + * BR2 and OR2 (Unused) + * Base address = 0xF020_0000 - 0xF020_0FFF + * + */ +#define CFG_OR2_PRELIM 0xFFF00000 +#define CFG_BR2_PRELIM 0xF0200000 + +/* + * BR3 and OR3 (External Bus CS3) + * Base address = 0xF030_0000 - 0xF030_0FFF + * + */ +#define CFG_OR3_PRELIM 0xFFF00000 +#define CFG_BR3_PRELIM 0xF0300000 + +/* + * BR4 and OR4 (External Bus CS3) + * Base address = 0xF040_0000 - 0xF040_0FFF + * + */ +#define CFG_OR4_PRELIM 0xFFF00000 +#define CFG_BR4_PRELIM 0xF0400000 + + +/* + * BR4 and OR4 (External Bus CS3) + * Base address = 0xF050_0000 - 0xF050_0FFF + * + */ +#define CFG_OR5_PRELIM 0xFFF00000 +#define CFG_BR5_PRELIM 0xF0500000 + +/* + * BR6 and OR6 (Unused) + * Base address = 0xF060_0000 - 0xF060_0FFF + * + */ +#define CFG_OR6_PRELIM 0xFFF00000 +#define CFG_BR6_PRELIM 0xF0600000 + +/* + * BR7 and OR7 (Unused) + * Base address = 0xF070_0000 - 0xF070_0FFF + * + */ +#define CFG_OR7_PRELIM 0xFFF00000 +#define CFG_BR7_PRELIM 0xF0700000 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Sanity checks + */ +#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) +#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/QS860T.h b/include/configs/QS860T.h new file mode 100644 index 0000000..92eccd3 --- /dev/null +++ b/include/configs/QS860T.h @@ -0,0 +1,413 @@ +/* + * (C) Copyright 2003 + * MuLogic B.V. + * + * (C) Copyright 2002 + * Simple Network Magic Corporation + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* various debug settings */ +#undef CFG_DEVICE_NULLDEV /* null device */ +#undef CONFIG_SILENT_CONSOLE /* silent console */ +#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */ +#undef DEBUG /* debug output code */ +#undef DEBUG_FLASH /* debug flash code */ +#undef FLASH_DEBUG /* debug fash code */ +#undef DEBUG_ENV /* debug environment code */ + +#define CFG_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ +#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ + + + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ +#define CONFIG_QS860T 1 /* ...on a QS860T module */ + +#define CONFIG_FEC_ENET 1 /* FEC 10/100BaseT ethernet */ +#define FEC_INTERRUPT SIU_LEVEL1 +#undef CONFIG_SCC1_ENET /* SCC1 10BaseT ethernet */ +#define CFG_DISCOVER_PHY + +#undef CONFIG_8xx_CONS_SMC1 +#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC */ +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +/* Pass clocks to Linux 2.4.18 in Hz */ +#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ + +#define CONFIG_PREBOOT "echo;" \ + "echo 'Type \"run flash_nfs\" to mount root filesystem over NFS';" \ + "echo" + +#undef CONFIG_BOOTARGS +/* TODO compare against CADM860 */ +#define CONFIG_BOOTCOMMAND "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "bootm" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#undef CONFIG_STATUS_LED /* Status LED disabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_REGINFO | \ + CFG_CMD_IMMAP | \ + CFG_CMD_ASKENV | \ + CFG_CMD_NET | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + + +/* TODO */ +#if 0 +/* Look at these */ +CONFIG_IPADDR +CONFIG_SERVERIP +CONFIG_I2C +CONFIG_SPI +#endif + +/* + * Environment variable storage is in NVRAM + */ +#define CFG_ENV_IS_IN_NVRAM 1 +#define CFG_ENV_SIZE 0x00001000 /* We use only the last 4K for PPCBoot */ +#define CFG_ENV_ADDR 0xD100E000 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#define CFG_PROMPT_HUSH_PS2 "> " + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/* TODO - size? */ +#define CFG_MEMTEST_START 0x0400000 /* memtest works */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF0000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFF00000 + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* TODO flash parameters */ +/*----------------------------------------------------------------------- + * FLASH organization for Intel Strataflash + */ +#define CFG_FLASH_16BIT 1 /* 16-bit wide flash memory */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#undef CFG_ENV_IS_IN_FLASH + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (0xFFFFFF88 | SYPCR_SWE | SYPCR_SWRI) +#else +#define CFG_SYPCR 0xFFFFFF88 +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + */ +#define CFG_SIUMCR 0x00620000 + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + */ +#define CFG_TBSCR 0x00C3 + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + */ +#define CFG_PISCR 0x0082 + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + */ +#define CFG_PLPRCR 0x0090D000 + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR 0x02000000 + + +/*----------------------------------------------------------------------- + * Debug Enable Register + * 0x73E67C0F - All interrupts handled by BDM + * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM + *----------------------------------------------------------------------- +#define CFG_DER 0x73E67C0F +*/ +#define CFG_DER 0x0082400F + + +/*----------------------------------------------------------------------- + * Memory Controller Initialization Constants + *----------------------------------------------------------------------- + */ + +/* + * BR0 and OR0 (AMD 512K Socketed FLASH) + * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) + */ +#define CFG_PRELIM_OR_AM +#define CFG_OR_TIMING_FLASH + +#define FLASH_BASE0_PRELIM 0xFFF00001 +#define CFG_OR0_PRELIM 0xFFF80D42 +#define CFG_BR0_PRELIM 0xFFF00401 + + +/* + * BR1 and OR1 (Intel 8M StrataFLASH) + * Base address = 0xD000_0000 - 0xD07F_FFFF + */ + +#define FLASH_BASE1_PRELIM 0xD0000000 +#define CFG_OR1_PRELIM 0xFF800D42 +#define CFG_BR1_PRELIM 0xD0000801 +/* #define CFG_OR1 0xFF800D42 */ +/* #define CFG_BR1 0xD0000801 */ + + +/* + * BR2 and OR2 (SDRAM) + * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) + * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) + * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) + * + */ +#define SDRAM_BASE 0x00000000 /* SDRAM bank */ +#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ + +/* SDRAM timing */ +#define SDRAM_TIMING 0x00000A00 + +/* For boards with 16M of SDRAM */ +#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ +#define CFG_16M_MBMR 0x18802114 /* Mem Periodic Timer Prescaler */ + +/* For boards with 64M of SDRAM */ +#define SDRAM_64M_MAX_SIZE 0x04000000 /* max 64MB SDRAM */ +/* TODO - determine real value */ +#define CFG_64M_MBMR 0x18802114 /* Mem Period Timer Prescaler */ + +#define CFG_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING) +#define CFG_BR2 (SDRAM_BASE | 0x000000C1) + + +/* + * BR3 and OR3 (NVRAM, Sipex, NAND Flash) + * Base address = 0xD100_0000 - 0xD100_FFFF (64K NVRAM) + * Base address = 0xD108_0000 - 0xD108_0000 (Sipex chip ctl register) + * Base address = 0xD110_0000 - 0xD110_0000 (NAND ctl register) + * Base address = 0xD138_0000 - 0xD138_0000 (LED ctl register) + * + */ + +#define CFG_OR3_PRELIM 0xFFC00DF6 +#define CFG_BR3_PRELIM 0xD1000401 +/* #define CFG_OR3 0xFFC00DF6 */ +/* #define CFG_BR3 0xD1000401 */ + + +/* + * BR4 and OR4 (Unused) + * Base address = 0xE000_0000 - 0xE3FF_FFFF + * + */ + +#define CFG_OR4_PRELIM 0xFF000000 +#define CFG_BR4_PRELIM 0xE0000000 +/* #define CFG_OR4 0xFF000000 */ +/* #define CFG_BR4 0xE0000000 */ + + +/* + * BR5 and OR5 (Expansion bus) + * Base address = 0xE400_0000 - 0xE7FF_FFFF + * + */ + +#define CFG_OR5_PRELIM 0xFF000000 +#define CFG_BR5_PRELIM 0xE4000000 +/* #define CFG_OR5 0xFF000000 */ +/* #define CFG_BR5 0xE4000000 */ + + + +/* + * BR6 and OR6 (Expansion bus) + * Base address = 0xE800_0000 - 0xEBFF_FFFF + * + */ + +#define CFG_OR6_PRELIM 0xFF000000 +#define CFG_BR6_PRELIM 0xE8000000 +/* #define CFG_OR6 0xFF000000 */ +/* #define CFG_BR6 0xE8000000 */ + + + +/* + * BR7 and OR7 (Expansion bus) + * Base address = 0xEC00_0000 - 0xEFFF_FFFF + * + */ + +#define CFG_OR7_PRELIM 0xFF000000 +#define CFG_BR7_PRELIM 0xE8000000 +/* #define CFG_OR7 0xFF000000 */ +/* #define CFG_BR7 0xE8000000 */ + + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Sanity checks + */ +#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) +#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured +#endif + +#endif /* __CONFIG_H */ diff --git a/include/flash.h b/include/flash.h index e93b86e..32f4f4a 100644 --- a/include/flash.h +++ b/include/flash.h @@ -148,6 +148,9 @@ extern int flash_real_protect(flash_info_t *info, long sector, int prot); #define AMD_ID_LV160T 0x22C422C4 /* 29LV160T ID (16 M, top boot sector) */ #define AMD_ID_LV160B 0x22492249 /* 29LV160B ID (16 M, bottom boot sect) */ +#define AMD_ID_DL163T 0x22282228 /* 29DL163T ID (16 M, top boot sector) */ +#define AMD_ID_DL163B 0x222B222B /* 29DL163B ID (16 M, bottom boot sect) */ + #define AMD_ID_LV320T 0x22F622F6 /* 29LV320T ID (32 M, top boot sector) */ #define AMD_ID_LV320B 0x22F922F9 /* 29LV320B ID (32 M, bottom boot sect) */ @@ -322,6 +325,8 @@ extern int flash_real_protect(flash_info_t *info, long sector, int prot); #define FLASH_AMLV128U 0x00A6 /* AMD 29LV128M ( 128M = 8M x 16 ) */ /* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */ #define FLASH_28F256L18T 0x00A8 +#define FLASH_AMDL163T 0x00A2 /* AMD AM29DL163T (2M x 16 ) */ +#define FLASH_AMDL163B 0x00A3 #define FLASH_UNKNOWN 0xFFFF /* unknown flash type */ |