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-rw-r--r--include/asm-ppc/fsl_lbc.h8
-rw-r--r--include/asm-ppc/immap_85xx.h3
-rw-r--r--include/configs/MPC8349EMDS.h1
-rw-r--r--include/configs/MPC8349ITX.h1
-rw-r--r--include/configs/MPC8536DS.h4
-rw-r--r--include/configs/MPC8540ADS.h1
-rw-r--r--include/configs/MPC8540EVAL.h1
-rw-r--r--include/configs/MPC8541CDS.h1
-rw-r--r--include/configs/MPC8544DS.h4
-rw-r--r--include/configs/MPC8548CDS.h3
-rw-r--r--include/configs/MPC8555CDS.h1
-rw-r--r--include/configs/MPC8560ADS.h1
-rw-r--r--include/configs/MPC8568MDS.h3
-rw-r--r--include/configs/MPC8572DS.h29
-rw-r--r--include/configs/MPC8610HPCD.h15
-rw-r--r--include/configs/MPC8641HPCN.h10
-rw-r--r--include/configs/MVBLM7.h1
-rw-r--r--include/configs/PM854.h1
-rw-r--r--include/configs/PM856.h1
-rw-r--r--include/configs/SBC8540.h1
-rw-r--r--include/configs/TQM834x.h1
-rw-r--r--include/configs/TQM85xx.h1
-rw-r--r--include/configs/sbc8349.h1
-rw-r--r--include/configs/sbc8548.h1
-rw-r--r--include/configs/sbc8560.h1
-rw-r--r--include/configs/sbc8641d.h15
-rw-r--r--include/configs/socrates.h1
-rw-r--r--include/configs/stxgp3.h1
-rw-r--r--include/configs/stxssa.h1
29 files changed, 55 insertions, 58 deletions
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index cac7bf6..51fc5c1 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -69,6 +69,14 @@
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
#endif
+/* Convert an address into the right format for the BR registers */
+#ifdef CONFIG_PHYS_64BIT
+#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
+ ((x & 0x300000000ULL) >> 19)))
+#else
+#define BR_PHYS_ADDR(x) (x & 0xffff8000)
+#endif
+
/* OR - Option Registers
*/
#define OR0 0x5004 /* Register offset to immr */
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 75b451d..e5046be 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1569,6 +1569,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
+#define MPC85xx_PORDEVSR_PCI1 0x00800000
#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
@@ -1647,8 +1648,6 @@ typedef struct ccsr_gur {
char res15[61648]; /* 0xe0f30 to 0xefffff */
} ccsr_gur_t;
-#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
-
#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000)
#define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000)
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index bbdc211..8e82aac 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -193,7 +193,6 @@
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */
#define CONFIG_SYS_OR1_PRELIM 0xFFFFE8F0 /* length 32K */
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index f633f24..14cbc45 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -266,7 +266,6 @@ boards, we say we have two, but don't display a message if we find only one. */
#undef CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index fff888ab..5a99d5f 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -99,7 +99,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_DDR_SPD
#undef CONFIG_DDR_DLL
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
@@ -231,8 +231,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 79a52d9..0b8fe6a 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -258,7 +258,6 @@
#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index 46a141a..21cf965 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -161,7 +161,6 @@
#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 7ada8a2..eaa737b 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -281,7 +281,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_BR3_PRELIM 0xf8000801
#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index cdbbea6..b31c2bb 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -97,7 +97,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
@@ -207,8 +207,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 083afba..7a7e5a1 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -100,7 +100,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_DDR_SPD
#define CONFIG_DDR_DLL /* possible DLL fix needed */
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
@@ -303,7 +303,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_BR3_PRELIM 0xf8000801
#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index f9419cc..40b40ed 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -279,7 +279,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_BR3_PRELIM 0xf8000801
#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index f67d489..2b5b2c1 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -254,7 +254,6 @@
#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index ab3e6d6..8bdec65 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -92,7 +92,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#define CONFIG_DDR_DLL /* possible DLL fix needed */
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
@@ -265,7 +265,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_BR5_PRELIM 0xf8010801
#define CONFIG_SYS_OR5_PRELIM 0xffff69f7
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index c3693b8..9a66ca8 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -99,6 +99,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_DDR_SPD
#undef CONFIG_DDR_DLL
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
@@ -114,22 +115,22 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
/* These are used when DDR doesn't use SPD. */
-#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1 0x00480432
+#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
+#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0 0x00260802
+#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
+#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
+#define CONFIG_SYS_DDR_MODE_1 0x00440462
#define CONFIG_SYS_DDR_MODE_2 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x06180100
+#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
+#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
+#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2 0x04400010
+#define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2 0x24400000
#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
@@ -248,8 +249,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
| PIXIS_VCFGEN1_TSEC3SER \
| PIXIS_VCFGEN1_TSEC4SER)
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index f2fe4a6..27517e5 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -81,6 +81,9 @@
#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
+
#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
@@ -206,7 +209,6 @@
#undef CONFIG_CLOCKS_IN_MHZ
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#ifndef CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
@@ -388,6 +390,17 @@
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
/*
* BAT4 32M Cache-inhibited, guarded
* 0xe200_0000 1M PCI-Express 2 I/O
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 69b4c44..5a83296 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -186,17 +186,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \
| CONFIG_SYS_PHYS_ADDR_HIGH)
-
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
-/* Convert an address into the right format for the BR registers */
-#ifdef CONFIG_PHYS_64BIT
-#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
- ((x & 0x300000000ULL) >> 19)))
-#else
-#define BR_PHYS_ADDR(x) (x & 0xffff8000)
-#endif
-
#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
| 0x00001001) /* port size 16bit */
#define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
@@ -268,7 +259,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#undef CONFIG_CLOCKS_IN_MHZ
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#ifndef CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index bc2d825..4ecf806 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -130,7 +130,6 @@
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
#undef CONFIG_SYS_RAMBOOT
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index c3a7f81..1cc80ad 100644
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -161,7 +161,6 @@
#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index b3bcf23..698ad2d 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -164,7 +164,6 @@
#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index 48c9339..2853fba 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -186,7 +186,6 @@
#define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 2961a1b..796030d 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -171,7 +171,6 @@ extern int tqm834x_num_flash_banks;
#undef CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index 2d4048a..300f490 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -234,7 +234,6 @@
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_CCSRBAR \
+ 0x04010000) /* Initial RAM address */
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 174149b..0603e3c 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -162,7 +162,6 @@
#undef CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index aefd30a..5ce4dac 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -280,7 +280,6 @@
| CONFIG_SYS_LBC_LSDMR_RFEN \
)
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index 4301275..e1d3a52 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -180,7 +180,6 @@
#define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 45d8179..0012945 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -104,6 +104,9 @@
#define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
+
#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
@@ -241,7 +244,6 @@
#undef CONFIG_CLOCKS_IN_MHZ
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#ifndef CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
@@ -433,6 +435,17 @@
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
/*
* BAT4 32M Cache-inhibited, guarded
* 0xe200_0000 16M PCI-Express 1 I/O
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index c67db8f..e89b5a3 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -167,7 +167,6 @@
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End used area in RAM */
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 2188e54..a0f2ed0 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -151,7 +151,6 @@
#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index b0bd050..f0990c6 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -164,7 +164,6 @@
#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */