diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-at91rm9200/AT91RM9200.h | 116 | ||||
| -rw-r--r-- | include/configs/NC650.h | 2 | ||||
| -rw-r--r-- | include/configs/at91rm9200dk.h | 19 | ||||
| -rw-r--r-- | include/configs/cmc_pu2.h | 69 | ||||
| -rw-r--r-- | include/flash.h | 3 |
5 files changed, 153 insertions, 56 deletions
diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h index 869c4e2..07ae112 100644 --- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h +++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h @@ -92,9 +92,52 @@ typedef struct _AT91S_USART { AT91_REG US_PTSR; /* PDC Transfer Status Register */ } AT91S_USART, *AT91PS_USART; -/* ***************************************************************************** */ +/************************************************************************/ +/* SOFTWARE API DEFINITION FOR Clock Generator Controler */ +/************************************************************************/ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; /* Main Oscillator Register */ + AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ + AT91_REG CKGR_PLLAR; /* PLL A Register */ + AT91_REG CKGR_PLLBR; /* PLL B Register */ +} AT91S_CKGR, *AT91PS_CKGR; + +/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) /* (CKGR) Oscillator Test */ +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) /* (CKGR) Main Oscillator Start-up Time */ +/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) /* (CKGR) Main Clock Ready */ +/* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- */ +#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL A Counter */ +#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) /* (CKGR) PLL A Output Frequency Range */ +#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLA datasheet */ +#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLA datasheet */ +#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLA datasheet */ +#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLA datasheet */ +#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) /* (CKGR) PLL A Multiplier */ +#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) /* (CKGR) PLL A Source */ +/* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- */ +#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL B Counter */ +#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) /* (CKGR) PLL B Output Frequency Range */ +#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLB datasheet */ +#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLB datasheet */ +#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLB datasheet */ +#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLB datasheet */ +#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) /* (CKGR) PLL B Multiplier */ +#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */ +#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */ + +/* ************************************************************************* */ /* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */ -/* ***************************************************************************** */ +/* ************************************************************************* */ typedef struct _AT91S_PIO { AT91_REG PIO_PER; /* PIO Enable Register */ AT91_REG PIO_PDR; /* PIO Disable Register */ @@ -198,6 +241,23 @@ typedef struct _AT91S_SMC2 { AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */ } AT91S_SMC2, *AT91PS_SMC2; +/* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */ +#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */ +#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ +#define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) /* (SMC2) Data Float Time */ +#define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */ +#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */ +#define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */ +#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ +#define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */ +#define AT91C_SMC2_ACSS ((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */ +#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ +#define AT91C_SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */ +#define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */ +#define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */ +#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */ +#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */ + /* ***************************************************************************** */ /* SOFTWARE API DEFINITION FOR Power Management Controler */ /* ******************************************************************************/ @@ -220,6 +280,58 @@ typedef struct _AT91S_PMC { } AT91S_PMC, *AT91PS_PMC; +/*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/ +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */ +#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) /* (PMC) USB Host Port Clock */ +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output */ +/*-------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ------*/ +/*-------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------*/ +/*-------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------*/ +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) /* (PMC) Clock from PLL A is selected */ +#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) /* (PMC) Clock from PLL B is selected */ +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) /* (PMC) Selected clock divided by 64 */ +#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) /* (PMC) Master Clock Division */ +#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) /* (PMC) The master clock and the processor clock are the same */ +#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) /* (PMC) The processor clock is twice as fast as the master clock */ +#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) /* (PMC) The processor clock is three times faster than the master clock */ +#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) /* (PMC) The processor clock is four times faster than the master clock */ +/*------ PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------*/ +/*------ PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------*/ +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) /* (PMC) PLL A Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) /* (PMC) PLL B Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */ +/*---- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------*/ +/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/ +/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/ + /* ***************************************************************************** */ /* SOFTWARE API DEFINITION FOR Ethernet MAC */ /* ***************************************************************************** */ diff --git a/include/configs/NC650.h b/include/configs/NC650.h index c62d879..8966909 100644 --- a/include/configs/NC650.h +++ b/include/configs/NC650.h @@ -347,8 +347,6 @@ #define CFG_OR5_PRELIM (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM) - - /* * 4096 Rows from SDRAM example configuration * 1000 factor s -> ms diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index fb8a610..58e2045 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -44,6 +44,9 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 +/* define this to include the functionality of boot.bin in u-boot */ +#undef CONFIG_BOOTBINFUNC + /* * Size of malloc() pool */ @@ -58,8 +61,9 @@ * Hardware drivers */ -/* define one of these to choose the DBGU or USART1 as console */ +/* define one of these to choose the DBGU, USART0 or USART1 as console */ #define CONFIG_DBGU +#undef CONFIG_USART0 #undef CONFIG_USART1 #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ @@ -145,16 +149,27 @@ #define CFG_ENV_SIZE 0x2000 /* 0x8000 */ #else #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* 0x10000 */ +#ifdef CONFIG_BOOTBINFUNC +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */ +#define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */ +#else +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */ #define CFG_ENV_SIZE 0x2000 /* 0x8000 */ #endif +#endif #define CFG_LOAD_ADDR 0x21000000 /* default load address */ +#ifdef CONFIG_BOOTBINFUNC +#define CFG_BOOT_SIZE 0x00 /* 0 KBytes */ +#define CFG_U_BOOT_BASE PHYS_FLASH_1 +#define CFG_U_BOOT_SIZE 0x60000 /* 384 KBytes */ +#else #define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */ #define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000) #define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */ +#endif #define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h index a08b791..e144a67 100644 --- a/include/configs/cmc_pu2.h +++ b/include/configs/cmc_pu2.h @@ -1,7 +1,7 @@ /* - * Rick Bronson <rick@efn.org> + * Gary Jennejohn <garyj@denx.de> * - * Configuation settings for the AT91RM9200DK board. + * Configuration settings for the CMC PU2 board. * * See file CREDITS for list of people who contributed to this * project. @@ -34,7 +34,6 @@ /* ARM asynchronous clock */ #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ #define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ -/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */ #define AT91_SLOW_CLOCK 32768 /* slow clock */ @@ -46,7 +45,12 @@ #define CONFIG_INITRD_TAG 1 /* define this to include the functionality of boot.bin in u-boot */ -#undef CONFIG_BOOTBINFUNC +#define CONFIG_BOOTBINFUNC + +/* just to make sure */ +#ifndef CONFIG_BOOTBINFUNC +#define CONFIG_BOOTBINFUNC +#endif /* * Size of malloc() pool @@ -64,14 +68,14 @@ /* define one of these to choose the DBGU, USART0 or USART1 as console */ #undef CONFIG_DBGU -#undef CONFIG_USART0 -#define CONFIG_USART1 +#define CONFIG_USART0 +#undef CONFIG_USART1 #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ -#undef CONFIG_HARD_I2C +#define CONFIG_HARD_I2C #ifdef CONFIG_HARD_I2C #define CFG_I2C_SPEED 0 /* not used */ @@ -114,38 +118,12 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ -#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) -#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) - -#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) -/* the following are NOP's in our implementation */ -#define NAND_CTL_CLRALE(nandptr) -#define NAND_CTL_SETALE(nandptr) -#define NAND_CTL_CLRCLE(nandptr) -#define NAND_CTL_SETCLE(nandptr) - #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ +#define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */ #define CFG_MEMTEST_START PHYS_SDRAM #define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 @@ -162,35 +140,26 @@ #define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ #define PHYS_FLASH_1 0x10000000 -#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */ +#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */ #define CFG_FLASH_BASE PHYS_FLASH_1 #define CFG_MAX_FLASH_BANKS 1 #define CFG_MAX_FLASH_SECT 256 #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ -#undef CFG_ENV_IS_IN_DATAFLASH - -#ifdef CFG_ENV_IS_IN_DATAFLASH -#define CFG_ENV_OFFSET 0x20000 -#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) -#define CFG_ENV_SIZE 0x2000 /* 0x8000 */ -#else #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* 0x10000 */ -#define CFG_ENV_SIZE 0x2000 /* 0x8000 */ -#endif - +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* after u-boot.bin */ +#define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */ #define CFG_LOAD_ADDR 0x21000000 /* default load address */ -#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */ -#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000) -#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */ +#define CFG_BOOT_SIZE 0x00 /* 0 KBytes */ +#define CFG_U_BOOT_BASE PHYS_FLASH_1 +#define CFG_U_BOOT_SIZE 0x20000 /* 128 KBytes */ #define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } -#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */ +#define CFG_PROMPT "cmc> " /* Monitor Command Prompt */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ diff --git a/include/flash.h b/include/flash.h index 0b28da7..a93c9b2 100644 --- a/include/flash.h +++ b/include/flash.h @@ -194,6 +194,8 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define AMD_ID_LV128U_3 0x22002200 /* 3rd ID word for AM29LV128M at 0x3c */ #define AMD_ID_LV256U_2 0x22122212 /* 2nd ID word for AM29LV256M at 0x38 */ #define AMD_ID_LV256U_3 0x22012201 /* 3rd ID word for AM29LV256M at 0x3c */ +#define AMD_ID_GL064M_2 0x22132213 /* 2nd ID word for S29GL064M-R6 */ +#define AMD_ID_GL064M_3 0x22012201 /* 3rd ID word for S29GL064M-R6 */ #define AMD_ID_LV320B_2 0x221A221A /* 2d ID word for AM29LV320MB at 0x38 */ #define AMD_ID_LV320B_3 0x22002200 /* 3d ID word for AM29LV320MB at 0x3c */ @@ -374,6 +376,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define FLASH_FUJLV650 0x00D0 /* Fujitsu MBM 29LV650UE/651UE */ #define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */ +#define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */ #define FLASH_UNKNOWN 0xFFFF /* unknown flash type */ |