diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/fsl_lbc.h | 130 | ||||
| -rw-r--r-- | include/asm-ppc/immap_83xx.h | 57 | ||||
| -rw-r--r-- | include/asm-ppc/immap_85xx.h | 1 | ||||
| -rw-r--r-- | include/configs/MPC8572DS.h | 56 | ||||
| -rw-r--r-- | include/linux/mtd/blktrans.h | 2 | ||||
| -rw-r--r-- | include/linux/mtd/doc2000.h | 2 | ||||
| -rw-r--r-- | include/linux/mtd/mtd.h | 32 | ||||
| -rw-r--r-- | include/linux/mtd/nand.h | 12 | ||||
| -rw-r--r-- | include/linux/mtd/nand_ecc.h | 2 | ||||
| -rw-r--r-- | include/linux/mtd/nftl.h | 7 | ||||
| -rw-r--r-- | include/linux/mtd/onenand.h | 1 | ||||
| -rw-r--r-- | include/linux/mtd/onenand_regs.h | 6 | ||||
| -rw-r--r-- | include/mpc83xx.h | 85 |
13 files changed, 240 insertions, 153 deletions
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index ea49ddc..cac7bf6 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -307,4 +307,134 @@ #define LTEDR_RAWA 0x00400000 /* Read-after-write-atomic error checking disable */ #define LTEDR_CSD 0x00080000 /* Chip select error checking disable */ +/* FMR - Flash Mode Register + */ +#define FMR_CWTO 0x0000F000 +#define FMR_CWTO_SHIFT 12 +#define FMR_BOOT 0x00000800 +#define FMR_ECCM 0x00000100 +#define FMR_AL 0x00000030 +#define FMR_AL_SHIFT 4 +#define FMR_OP 0x00000003 +#define FMR_OP_SHIFT 0 + +/* FIR - Flash Instruction Register + */ +#define FIR_OP0 0xF0000000 +#define FIR_OP0_SHIFT 28 +#define FIR_OP1 0x0F000000 +#define FIR_OP1_SHIFT 24 +#define FIR_OP2 0x00F00000 +#define FIR_OP2_SHIFT 20 +#define FIR_OP3 0x000F0000 +#define FIR_OP3_SHIFT 16 +#define FIR_OP4 0x0000F000 +#define FIR_OP4_SHIFT 12 +#define FIR_OP5 0x00000F00 +#define FIR_OP5_SHIFT 8 +#define FIR_OP6 0x000000F0 +#define FIR_OP6_SHIFT 4 +#define FIR_OP7 0x0000000F +#define FIR_OP7_SHIFT 0 +#define FIR_OP_NOP 0x0 /* No operation and end of sequence */ +#define FIR_OP_CA 0x1 /* Issue current column address */ +#define FIR_OP_PA 0x2 /* Issue current block+page address */ +#define FIR_OP_UA 0x3 /* Issue user defined address */ +#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ +#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ +#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ +#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ +#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ +#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ +#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ +#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ +#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ +#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ +#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ +#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */ + +/* FCR - Flash Command Register + */ +#define FCR_CMD0 0xFF000000 +#define FCR_CMD0_SHIFT 24 +#define FCR_CMD1 0x00FF0000 +#define FCR_CMD1_SHIFT 16 +#define FCR_CMD2 0x0000FF00 +#define FCR_CMD2_SHIFT 8 +#define FCR_CMD3 0x000000FF +#define FCR_CMD3_SHIFT 0 +/* FBAR - Flash Block Address Register + */ +#define FBAR_BLK 0x00FFFFFF + +/* FPAR - Flash Page Address Register + */ +#define FPAR_SP_PI 0x00007C00 +#define FPAR_SP_PI_SHIFT 10 +#define FPAR_SP_MS 0x00000200 +#define FPAR_SP_CI 0x000001FF +#define FPAR_SP_CI_SHIFT 0 +#define FPAR_LP_PI 0x0003F000 +#define FPAR_LP_PI_SHIFT 12 +#define FPAR_LP_MS 0x00000800 +#define FPAR_LP_CI 0x000007FF +#define FPAR_LP_CI_SHIFT 0 + +/* LTESR - Transfer Error Status Register + */ +#define LTESR_BM 0x80000000 +#define LTESR_FCT 0x40000000 +#define LTESR_PAR 0x20000000 +#define LTESR_WP 0x04000000 +#define LTESR_ATMW 0x00800000 +#define LTESR_ATMR 0x00400000 +#define LTESR_CS 0x00080000 +#define LTESR_CC 0x00000001 + +#ifndef __ASSEMBLY__ +/* + * Local Bus Controller Registers. + */ +typedef struct lbus_bank { + u32 br; /* Base Register */ + u32 or; /* Option Register */ +} lbus_bank_t; + +typedef struct fsl_lbus { + lbus_bank_t bank[8]; + u8 res0[0x28]; + u32 mar; /* UPM Address Register */ + u8 res1[0x4]; + u32 mamr; /* UPMA Mode Register */ + u32 mbmr; /* UPMB Mode Register */ + u32 mcmr; /* UPMC Mode Register */ + u8 res2[0x8]; + u32 mrtpr; /* Memory Refresh Timer Prescaler Register */ + u32 mdr; /* UPM Data Register */ + u8 res3[0x4]; + u32 lsor; /* Special Operation Initiation Register */ + u32 lsdmr; /* SDRAM Mode Register */ + u8 res4[0x8]; + u32 lurt; /* UPM Refresh Timer */ + u32 lsrt; /* SDRAM Refresh Timer */ + u8 res5[0x8]; + u32 ltesr; /* Transfer Error Status Register */ + u32 ltedr; /* Transfer Error Disable Register */ + u32 lteir; /* Transfer Error Interrupt Register */ + u32 lteatr; /* Transfer Error Attributes Register */ + u32 ltear; /* Transfer Error Address Register */ + u8 res6[0xC]; + u32 lbcr; /* Configuration Register */ + u32 lcrr; /* Clock Ratio Register */ + u8 res7[0x8]; + u32 fmr; /* Flash Mode Register */ + u32 fir; /* Flash Instruction Register */ + u32 fcr; /* Flash Command Register */ + u32 fbar; /* Flash Block Addr Register */ + u32 fpar; /* Flash Page Addr Register */ + u32 fbcr; /* Flash Byte Count Register */ + u8 res8[0xF08]; +} fsl_lbus_t; +#endif /* __ASSEMBLY__ */ + #endif /* __ASM_PPC_FSL_LBC_H */ diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index ff18303..df24a6e 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -31,6 +31,7 @@ #include <asm/types.h> #include <asm/fsl_i2c.h> #include <asm/mpc8xxx_spi.h> +#include <asm/fsl_lbc.h> /* * Local Access Window @@ -343,50 +344,6 @@ typedef struct duart83xx { } duart83xx_t; /* - * Local Bus Controller Registers - */ -typedef struct lbus_bank { - u32 br; /* Base Register */ - u32 or; /* Option Register */ -} lbus_bank_t; - -typedef struct lbus83xx { - lbus_bank_t bank[8]; - u8 res0[0x28]; - u32 mar; /* UPM Address Register */ - u8 res1[0x4]; - u32 mamr; /* UPMA Mode Register */ - u32 mbmr; /* UPMB Mode Register */ - u32 mcmr; /* UPMC Mode Register */ - u8 res2[0x8]; - u32 mrtpr; /* Memory Refresh Timer Prescaler Register */ - u32 mdr; /* UPM Data Register */ - u8 res3[0x4]; - u32 lsor; /* Special Operation Initiation Register */ - u32 lsdmr; /* SDRAM Mode Register */ - u8 res4[0x8]; - u32 lurt; /* UPM Refresh Timer */ - u32 lsrt; /* SDRAM Refresh Timer */ - u8 res5[0x8]; - u32 ltesr; /* Transfer Error Status Register */ - u32 ltedr; /* Transfer Error Disable Register */ - u32 lteir; /* Transfer Error Interrupt Register */ - u32 lteatr; /* Transfer Error Attributes Register */ - u32 ltear; /* Transfer Error Address Register */ - u8 res6[0xC]; - u32 lbcr; /* Configuration Register */ - u32 lcrr; /* Clock Ratio Register */ - u8 res7[0x8]; - u32 fmr; /* Flash Mode Register */ - u32 fir; /* Flash Instruction Register */ - u32 fcr; /* Flash Command Register */ - u32 fbar; /* Flash Block Addr Register */ - u32 fpar; /* Flash Page Addr Register */ - u32 fbcr; /* Flash Byte Count Register */ - u8 res8[0xF08]; -} lbus83xx_t; - -/* * DMA/Messaging Unit */ typedef struct dma83xx { @@ -614,7 +571,7 @@ typedef struct immap { u8 res2[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res3[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ + fsl_lbus_t lbus; /* Local Bus Controller Registers */ u8 res4[0x1000]; spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ @@ -648,7 +605,7 @@ typedef struct immap { u8 res1[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res2[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ + fsl_lbus_t lbus; /* Local Bus Controller Registers */ u8 res3[0x1000]; spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ @@ -683,7 +640,7 @@ typedef struct immap { u8 res1[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res2[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ + fsl_lbus_t lbus; /* Local Bus Controller Registers */ u8 res3[0x1000]; spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ @@ -728,7 +685,7 @@ typedef struct immap { u8 res1[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res2[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ + fsl_lbus_t lbus; /* Local Bus Controller Registers */ u8 res3[0x1000]; spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ @@ -778,7 +735,7 @@ typedef struct immap { u8 res4[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res5[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ + fsl_lbus_t lbus; /* Local Bus Controller Registers */ u8 res6[0x2000]; dma83xx_t dma; /* DMA */ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ @@ -817,7 +774,7 @@ typedef struct immap { u8 res3[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res4[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ + fsl_lbus_t lbus; /* Local Bus Controller Registers */ u8 res5[0x2000]; dma83xx_t dma; /* DMA */ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 4892d8b..75b451d 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -13,6 +13,7 @@ #include <asm/types.h> #include <asm/fsl_i2c.h> +#include <asm/fsl_lbc.h> /* * Local-Access Registers and ECM Registers(0x0000-0x2000) diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index eefb06c..f98e7fb 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -158,6 +158,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Localbus non-cacheable * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable + * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable @@ -260,6 +261,59 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_NAND_BASE 0xffa00000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ + CONFIG_SYS_NAND_BASE + 0x40000, \ + CONFIG_SYS_NAND_BASE + 0x80000,\ + CONFIG_SYS_NAND_BASE + 0xC0000} +#define CONFIG_SYS_MAX_NAND_DEVICE 4 +#define NAND_MAX_CHIPS 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* NAND flash config */ +#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ + | OR_FCM_PGS /* Large Page*/ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) + +#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ + +#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ + +#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ + + + /* Serial Port - controlled on board with jumper J8 * open - index 2 * shorted - index 1 @@ -455,7 +509,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 #define CONFIG_ENV_ADDR 0xfff80000 #else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) #endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ diff --git a/include/linux/mtd/blktrans.h b/include/linux/mtd/blktrans.h index d1ded51..32acb6c 100644 --- a/include/linux/mtd/blktrans.h +++ b/include/linux/mtd/blktrans.h @@ -1,6 +1,4 @@ /* - * $Id: blktrans.h,v 1.6 2005/11/07 11:14:54 gleixner Exp $ - * * (C) 2003 David Woodhouse <dwmw2@infradead.org> * * Interface to Linux block layer for MTD 'translation layers'. diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h index 12de284..ba29d53 100644 --- a/include/linux/mtd/doc2000.h +++ b/include/linux/mtd/doc2000.h @@ -6,8 +6,6 @@ * Copyright (C) 2002-2003 Greg Ungerer <gerg@snapgear.com> * Copyright (C) 2002-2003 SnapGear Inc * - * $Id: doc2000.h,v 1.25 2005/11/07 11:14:54 gleixner Exp $ - * * Released under GPL */ diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 55d33dd..354e3a0 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -1,6 +1,4 @@ /* - * $Id: mtd.h,v 1.61 2005/11/07 11:14:54 gleixner Exp $ - * * Copyright (C) 1999-2003 David Woodhouse <dwmw2@infradead.org> et al. * * Released under GPL @@ -132,7 +130,7 @@ struct mtd_info { u_int32_t oobavail; /* Available OOB bytes per block */ /* Kernel-only stuff starts here. */ - char *name; + const char *name; int index; /* ecc layout structure pointer - read only ! */ @@ -144,18 +142,36 @@ struct mtd_info { int numeraseregions; struct mtd_erase_region_info *eraseregions; + /* + * Erase is an asynchronous operation. Device drivers are supposed + * to call instr->callback() whenever the operation completes, even + * if it completes with a failure. + * Callers are supposed to pass a callback function and wait for it + * to be called before writing to the block. + */ int (*erase) (struct mtd_info *mtd, struct erase_info *instr); /* This stuff for eXecute-In-Place */ - int (*point) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char **mtdbuf); + /* phys is optional and may be set to NULL */ + int (*point) (struct mtd_info *mtd, loff_t from, size_t len, + size_t *retlen, void **virt, phys_addr_t *phys); /* We probably shouldn't allow XIP if the unpoint isn't a NULL */ - void (*unpoint) (struct mtd_info *mtd, u_char * addr, loff_t from, size_t len); + void (*unpoint) (struct mtd_info *mtd, loff_t from, size_t len); int (*read) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); int (*write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf); + /* In blackbox flight recorder like scenarios we want to make successful + writes in interrupt context. panic_write() is only intended to be + called when its known the kernel is about to panic and we need the + write to succeed. Since the kernel is not going to be running for much + longer, this function can break locks and delay to ensure the write + succeeds (but not sleep). */ + + int (*panic_write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf); + int (*read_oob) (struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops); int (*write_oob) (struct mtd_info *mtd, loff_t to, @@ -274,7 +290,11 @@ static inline void mtd_erase_callback(struct erase_info *instr) printk(KERN_INFO args); \ } while(0) #else /* CONFIG_MTD_DEBUG */ -#define MTDDEBUG(n, args...) do { } while(0) +#define MTDDEBUG(n, args...) \ + do { \ + if (0) \ + printk(KERN_INFO args); \ + } while(0) #endif /* CONFIG_MTD_DEBUG */ #endif /* __MTD_MTD_H__ */ diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 7ac72de..39f8aec 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -1,12 +1,10 @@ /* * linux/include/linux/mtd/nand.h * - * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com> + * Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org> * Steven J. Hill <sjhill@realitydiluted.com> * Thomas Gleixner <tglx@linutronix.de> * - * $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $ - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -190,6 +188,9 @@ typedef enum { #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) +/* Large page NAND with SOFT_ECC should support subpage reads */ +#define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \ + && (chip->page_shift > 9)) /* Mask to zero out the chip options, which come from the id table */ #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) @@ -278,6 +279,10 @@ struct nand_ecc_ctrl { int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf); + int (*read_subpage)(struct mtd_info *mtd, + struct nand_chip *chip, + uint32_t offs, uint32_t len, + uint8_t *buf); void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf); @@ -435,6 +440,7 @@ struct nand_chip { #define NAND_MFR_STMICRO 0x20 #define NAND_MFR_HYNIX 0xad #define NAND_MFR_MICRON 0x2c +#define NAND_MFR_AMD 0x01 /** * struct nand_flash_dev - NAND Flash Device ID Structure diff --git a/include/linux/mtd/nand_ecc.h b/include/linux/mtd/nand_ecc.h index 12c5bc3..090da50 100644 --- a/include/linux/mtd/nand_ecc.h +++ b/include/linux/mtd/nand_ecc.h @@ -3,8 +3,6 @@ * * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) * - * $Id: nand_ecc.h,v 1.4 2004/06/17 02:35:02 dbrown Exp $ - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. diff --git a/include/linux/mtd/nftl.h b/include/linux/mtd/nftl.h index 6731a16..fe22e0d 100644 --- a/include/linux/mtd/nftl.h +++ b/include/linux/mtd/nftl.h @@ -1,6 +1,4 @@ /* - * $Id: nftl.h,v 1.16 2004/06/30 14:49:00 dbrown Exp $ - * * (C) 1999-2003 David Woodhouse <dwmw2@infradead.org> */ @@ -43,6 +41,11 @@ struct NFTLrecord { int NFTL_mount(struct NFTLrecord *s); int NFTL_formatblock(struct NFTLrecord *s, int block); +int nftl_read_oob(struct mtd_info *mtd, loff_t offs, size_t len, + size_t *retlen, uint8_t *buf); +int nftl_write_oob(struct mtd_info *mtd, loff_t offs, size_t len, + size_t *retlen, uint8_t *buf); + #ifndef NFTL_MAJOR #define NFTL_MAJOR 93 #endif diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h index 420eb14..4467c2b 100644 --- a/include/linux/mtd/onenand.h +++ b/include/linux/mtd/onenand.h @@ -51,6 +51,7 @@ struct onenand_bufferram { * @param page_shift [INTERN] number of address bits in a page * @param ppb_shift [INTERN] number of address bits in a pages per block * @param page_mask [INTERN] a page per block mask + * @param writesize [INTERN] a real page size * @param bufferam_index [INTERN] BufferRAM index * @param bufferam [INTERN] BufferRAM info * @param readw [REPLACEABLE] hardware specific function for read short diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h index 6a8aa28..a245e14 100644 --- a/include/linux/mtd/onenand_regs.h +++ b/include/linux/mtd/onenand_regs.h @@ -67,12 +67,16 @@ /* * Device ID Register F001h (R) */ +#define ONENAND_DEVICE_DENSITY_MASK (0xf) #define ONENAND_DEVICE_DENSITY_SHIFT (4) #define ONENAND_DEVICE_IS_DDP (1 << 3) #define ONENAND_DEVICE_IS_DEMUX (1 << 2) #define ONENAND_DEVICE_VCC_MASK (0x3) #define ONENAND_DEVICE_DENSITY_512Mb (0x002) +#define ONENAND_DEVICE_DENSITY_1Gb (0x003) +#define ONENAND_DEVICE_DENSITY_2Gb (0x004) +#define ONENAND_DEVICE_DENSITY_4Gb (0x005) /* * Version ID Register F002h (R) @@ -110,6 +114,8 @@ #define ONENAND_CMD_READOOB (0x13) #define ONENAND_CMD_PROG (0x80) #define ONENAND_CMD_PROGOOB (0x1A) +#define ONENAND_CMD_2X_PROG (0x7D) +#define ONENAND_CMD_2X_CACHE_PROG (0x7F) #define ONENAND_CMD_UNLOCK (0x23) #define ONENAND_CMD_LOCK (0x2A) #define ONENAND_CMD_LOCK_TIGHT (0x2C) diff --git a/include/mpc83xx.h b/include/mpc83xx.h index ccf1077..a2c0ed9 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -1147,91 +1147,6 @@ */ #define PMCCR1_POWER_OFF 0x00000020 -/* FMR - Flash Mode Register - */ -#define FMR_CWTO 0x0000F000 -#define FMR_CWTO_SHIFT 12 -#define FMR_BOOT 0x00000800 -#define FMR_ECCM 0x00000100 -#define FMR_AL 0x00000030 -#define FMR_AL_SHIFT 4 -#define FMR_OP 0x00000003 -#define FMR_OP_SHIFT 0 - -/* FIR - Flash Instruction Register - */ -#define FIR_OP0 0xF0000000 -#define FIR_OP0_SHIFT 28 -#define FIR_OP1 0x0F000000 -#define FIR_OP1_SHIFT 24 -#define FIR_OP2 0x00F00000 -#define FIR_OP2_SHIFT 20 -#define FIR_OP3 0x000F0000 -#define FIR_OP3_SHIFT 16 -#define FIR_OP4 0x0000F000 -#define FIR_OP4_SHIFT 12 -#define FIR_OP5 0x00000F00 -#define FIR_OP5_SHIFT 8 -#define FIR_OP6 0x000000F0 -#define FIR_OP6_SHIFT 4 -#define FIR_OP7 0x0000000F -#define FIR_OP7_SHIFT 0 -#define FIR_OP_NOP 0x0 /* No operation and end of sequence */ -#define FIR_OP_CA 0x1 /* Issue current column address */ -#define FIR_OP_PA 0x2 /* Issue current block+page address */ -#define FIR_OP_UA 0x3 /* Issue user defined address */ -#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ -#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ -#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ -#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ -#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ -#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ -#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ -#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ -#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ -#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ -#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ -#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */ - -/* FCR - Flash Command Register - */ -#define FCR_CMD0 0xFF000000 -#define FCR_CMD0_SHIFT 24 -#define FCR_CMD1 0x00FF0000 -#define FCR_CMD1_SHIFT 16 -#define FCR_CMD2 0x0000FF00 -#define FCR_CMD2_SHIFT 8 -#define FCR_CMD3 0x000000FF -#define FCR_CMD3_SHIFT 0 - -/* FBAR - Flash Block Address Register - */ -#define FBAR_BLK 0x00FFFFFF - -/* FPAR - Flash Page Address Register - */ -#define FPAR_SP_PI 0x00007C00 -#define FPAR_SP_PI_SHIFT 10 -#define FPAR_SP_MS 0x00000200 -#define FPAR_SP_CI 0x000001FF -#define FPAR_SP_CI_SHIFT 0 -#define FPAR_LP_PI 0x0003F000 -#define FPAR_LP_PI_SHIFT 12 -#define FPAR_LP_MS 0x00000800 -#define FPAR_LP_CI 0x000007FF -#define FPAR_LP_CI_SHIFT 0 - -/* LTESR - Transfer Error Status Register - */ -#define LTESR_BM 0x80000000 -#define LTESR_FCT 0x40000000 -#define LTESR_PAR 0x20000000 -#define LTESR_WP 0x04000000 -#define LTESR_ATMW 0x00800000 -#define LTESR_ATMR 0x00400000 -#define LTESR_CS 0x00080000 -#define LTESR_CC 0x00000001 - /* DDRCDR - DDR Control Driver Register */ #define DDRCDR_DHC_EN 0x80000000 |