diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/fsl_ddr_dimm_params.h | 7 | ||||
| -rw-r--r-- | include/asm-ppc/fsl_ddr_sdram.h | 31 | ||||
| -rw-r--r-- | include/ddr_spd.h | 13 |
3 files changed, 49 insertions, 2 deletions
diff --git a/include/asm-ppc/fsl_ddr_dimm_params.h b/include/asm-ppc/fsl_ddr_dimm_params.h index c794eed..55923e0 100644 --- a/include/asm-ppc/fsl_ddr_dimm_params.h +++ b/include/asm-ppc/fsl_ddr_dimm_params.h @@ -33,9 +33,15 @@ typedef struct dimm_params_s { /* used in computing base address of DIMMs */ unsigned long long base_address; + /* mirrored DIMMs */ + unsigned int mirrored_dimm; /* only for ddr3 */ /* DIMM timing parameters */ + unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */ + unsigned int tAA_ps; /* minimum CAS latency time, only for ddr3 */ + unsigned int tFAW_ps; /* four active window delay, only for ddr3 */ + /* * SDRAM clock periods * The range for these are 1000-10000 so a short should be sufficient @@ -67,6 +73,7 @@ typedef struct dimm_params_s { unsigned int refresh_rate_ps; + /* DDR3 doesn't need these as below */ unsigned int tIS_ps; /* byte 32, spd->ca_setup */ unsigned int tIH_ps; /* byte 33, spd->ca_hold */ unsigned int tDS_ps; /* byte 34, spd->data_setup */ diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index 6e3b255..c2e5aee 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -19,6 +19,11 @@ #define SDRAM_TYPE_LPDDR1 6 #define SDRAM_TYPE_DDR3 7 +#define DDR_BL4 4 /* burst length 4 */ +#define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */ +#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ +#define DDR_BL8 8 /* burst length 8 */ + #if defined(CONFIG_FSL_DDR1) #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; @@ -68,6 +73,18 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define SDRAM_CFG_2T_EN 0x00008000 #define SDRAM_CFG_BI 0x00000001 +#if defined(CONFIG_P4080) +#define RD_TO_PRE_MASK 0xf +#define RD_TO_PRE_SHIFT 13 +#define WR_DATA_DELAY_MASK 0xf +#define WR_DATA_DELAY_SHIFT 9 +#else +#define RD_TO_PRE_MASK 0x7 +#define RD_TO_PRE_SHIFT 13 +#define WR_DATA_DELAY_MASK 0x7 +#define WR_DATA_DELAY_SHIFT 10 +#endif + /* Record of register values computed */ typedef struct fsl_ddr_cfg_regs_s { struct { @@ -145,7 +162,11 @@ typedef struct memctl_options_s { unsigned int dynamic_power; /* DYN_PWR */ /* memory data width to use (16-bit, 32-bit, 64-bit) */ unsigned int data_bus_width; - unsigned int burst_length; /* 4, 8 */ + unsigned int burst_length; /* BL4, OTF and BL8 */ + /* On-The-Fly Burst Chop enable */ + unsigned int OTF_burst_chop_en; + /* mirrior DIMMs for DDR3 */ + unsigned int mirrored_dimm; /* Global Timing Parameters */ unsigned int cas_latency_override; @@ -164,9 +185,17 @@ typedef struct memctl_options_s { unsigned int tCKE_clock_pulse_width_ps; /* tCKE */ unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */ + /* Rtt impedance */ + unsigned int rtt_override; /* rtt_override enable */ + unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ + /* Automatic self refresh */ unsigned int auto_self_refresh_en; unsigned int sr_it; + /* ZQ calibration */ + unsigned int zq_en; + /* Write leveling */ + unsigned int wrlvl_en; } memctl_options_t; extern phys_size_t fsl_ddr_sdram(void); diff --git a/include/ddr_spd.h b/include/ddr_spd.h index 6fdcef0..10402c5 100644 --- a/include/ddr_spd.h +++ b/include/ddr_spd.h @@ -184,7 +184,7 @@ typedef struct ddr3_spd_eeprom_s { unsigned char module_type; /* 3 Key Byte / Module Type */ unsigned char density_banks; /* 4 SDRAM Density and Banks */ unsigned char addressing; /* 5 SDRAM Addressing */ - unsigned char res_6; /* 6 Reserved */ + unsigned char module_vdd; /* 6 Module nominal voltage, VDD */ unsigned char organization; /* 7 Module Organization */ unsigned char bus_width; /* 8 Module Memory Bus Width */ unsigned char ftb_div; /* 9 Fine Timebase (FTB) @@ -273,6 +273,7 @@ extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd); extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd); extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd); extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd); +extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd); /* * Byte 2 Fundamental Memory Types. @@ -289,4 +290,14 @@ extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd); #define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A) #define SPD_MEMTYPE_DDR3 (0x0B) +/* + * Byte 3 Key Byte / Module Type for DDR3 SPD + */ +#define SPD_MODULETYPE_RDIMM (0x01) +#define SPD_MODULETYPE_UDIMM (0x02) +#define SPD_MODULETYPE_SODIMM (0x03) +#define SPD_MODULETYPE_MICRODIMM (0x04) +#define SPD_MODULETYPE_MINIRDIMM (0x05) +#define SPD_MODULETYPE_MINIUDIMM (0x06) + #endif /* _DDR_SPD_H_ */ |