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-rw-r--r--include/405gp_i2c.h64
-rw-r--r--include/440_i2c.h71
-rw-r--r--include/4xx_i2c.h122
-rw-r--r--include/asm-arm/io.h4
-rw-r--r--include/asm-avr32/io.h4
-rw-r--r--include/asm-blackfin/io.h5
-rw-r--r--include/asm-i386/io.h4
-rw-r--r--include/asm-m68k/io.h9
-rw-r--r--include/asm-microblaze/io.h4
-rw-r--r--include/asm-mips/io.h4
-rw-r--r--include/asm-nios/io.h4
-rw-r--r--include/asm-nios2/io.h5
-rw-r--r--include/asm-ppc/io.h11
-rw-r--r--include/asm-ppc/mmu.h208
-rw-r--r--include/common.h1
-rw-r--r--include/configs/katmai.h415
-rw-r--r--include/configs/mcc200.h1
-rw-r--r--include/configs/mecp5200.h58
-rw-r--r--include/configs/sequoia.h4
-rw-r--r--include/i2c.h10
-rw-r--r--include/ide.h6
-rw-r--r--include/part.h15
-rw-r--r--include/ppc405.h1
-rw-r--r--include/ppc440.h9
24 files changed, 821 insertions, 218 deletions
diff --git a/include/405gp_i2c.h b/include/405gp_i2c.h
deleted file mode 100644
index 5a9a497..0000000
--- a/include/405gp_i2c.h
+++ /dev/null
@@ -1,64 +0,0 @@
-#ifndef _405gp_i2c_h_
-#define _405gp_i2c_h_
-
-#define I2C_REGISTERS_BASE_ADDRESS 0xEF600500
-#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
-#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
-#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
-#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
-#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
-#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
-#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS)
-#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
-#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
-#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
-#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
-#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
-#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
-#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
-#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
-
-/* MDCNTL Register Bit definition */
-#define IIC_MDCNTL_HSCL 0x01
-#define IIC_MDCNTL_EUBS 0x02
-#define IIC_MDCNTL_EINT 0x04
-#define IIC_MDCNTL_ESM 0x08
-#define IIC_MDCNTL_FSM 0x10
-#define IIC_MDCNTL_EGC 0x20
-#define IIC_MDCNTL_FMDB 0x40
-#define IIC_MDCNTL_FSDB 0x80
-
-/* CNTL Register Bit definition */
-#define IIC_CNTL_PT 0x01
-#define IIC_CNTL_READ 0x02
-#define IIC_CNTL_CHT 0x04
-#define IIC_CNTL_RPST 0x08
-/* bit 2/3 for Transfer count*/
-#define IIC_CNTL_AMD 0x40
-#define IIC_CNTL_HMT 0x80
-
-/* STS Register Bit definition */
-#define IIC_STS_PT 0X01
-#define IIC_STS_IRQA 0x02
-#define IIC_STS_ERR 0X04
-#define IIC_STS_SCMP 0x08
-#define IIC_STS_MDBF 0x10
-#define IIC_STS_MDBS 0X20
-#define IIC_STS_SLPR 0x40
-#define IIC_STS_SSS 0x80
-
-/* EXTSTS Register Bit definition */
-#define IIC_EXTSTS_XFRA 0X01
-#define IIC_EXTSTS_ICT 0X02
-#define IIC_EXTSTS_LA 0X04
-
-/* XTCNTLSS Register Bit definition */
-#define IIC_XTCNTLSS_SRST 0x01
-#define IIC_XTCNTLSS_EPI 0x02
-#define IIC_XTCNTLSS_SDBF 0x04
-#define IIC_XTCNTLSS_SBDD 0x08
-#define IIC_XTCNTLSS_SWS 0x10
-#define IIC_XTCNTLSS_SWC 0x20
-#define IIC_XTCNTLSS_SRS 0x40
-#define IIC_XTCNTLSS_SRC 0x80
-#endif
diff --git a/include/440_i2c.h b/include/440_i2c.h
deleted file mode 100644
index 0c2bf36..0000000
--- a/include/440_i2c.h
+++ /dev/null
@@ -1,71 +0,0 @@
-#ifndef _440_i2c_h_
-#define _440_i2c_h_
-
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700)
-#else
-#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400)
-#endif /*CONFIG_440EP CONFIG_440GR*/
-
-#define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR
-#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
-#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
-#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
-#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
-#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
-#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
-#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS)
-#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
-#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
-#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
-#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
-#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
-#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
-#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
-#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
-
-/* MDCNTL Register Bit definition */
-#define IIC_MDCNTL_HSCL 0x01
-#define IIC_MDCNTL_EUBS 0x02
-#define IIC_MDCNTL_EINT 0x04
-#define IIC_MDCNTL_ESM 0x08
-#define IIC_MDCNTL_FSM 0x10
-#define IIC_MDCNTL_EGC 0x20
-#define IIC_MDCNTL_FMDB 0x40
-#define IIC_MDCNTL_FSDB 0x80
-
-/* CNTL Register Bit definition */
-#define IIC_CNTL_PT 0x01
-#define IIC_CNTL_READ 0x02
-#define IIC_CNTL_CHT 0x04
-#define IIC_CNTL_RPST 0x08
-/* bit 2/3 for Transfer count*/
-#define IIC_CNTL_AMD 0x40
-#define IIC_CNTL_HMT 0x80
-
-/* STS Register Bit definition */
-#define IIC_STS_PT 0X01
-#define IIC_STS_IRQA 0x02
-#define IIC_STS_ERR 0X04
-#define IIC_STS_SCMP 0x08
-#define IIC_STS_MDBF 0x10
-#define IIC_STS_MDBS 0X20
-#define IIC_STS_SLPR 0x40
-#define IIC_STS_SSS 0x80
-
-/* EXTSTS Register Bit definition */
-#define IIC_EXTSTS_XFRA 0X01
-#define IIC_EXTSTS_ICT 0X02
-#define IIC_EXTSTS_LA 0X04
-
-/* XTCNTLSS Register Bit definition */
-#define IIC_XTCNTLSS_SRST 0x01
-#define IIC_XTCNTLSS_EPI 0x02
-#define IIC_XTCNTLSS_SDBF 0x04
-#define IIC_XTCNTLSS_SBDD 0x08
-#define IIC_XTCNTLSS_SWS 0x10
-#define IIC_XTCNTLSS_SWC 0x20
-#define IIC_XTCNTLSS_SRS 0x40
-#define IIC_XTCNTLSS_SRC 0x80
-#endif
diff --git a/include/4xx_i2c.h b/include/4xx_i2c.h
new file mode 100644
index 0000000..66b7997
--- /dev/null
+++ b/include/4xx_i2c.h
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _4xx_i2c_h_
+#define _4xx_i2c_h_
+
+#define IIC_OK 0
+#define IIC_NOK 1
+#define IIC_NOK_LA 2 /* Lost arbitration */
+#define IIC_NOK_ICT 3 /* Incomplete transfer */
+#define IIC_NOK_XFRA 4 /* Transfer aborted */
+#define IIC_NOK_DATA 5 /* No data in buffer */
+#define IIC_NOK_TOUT 6 /* Transfer timeout */
+
+#define IIC_TIMEOUT 1 /* 1 second */
+
+#if defined(CONFIG_I2C_MULTI_BUS)
+#define I2C_BUS_OFFS (i2c_bus_num * 0x100)
+#else
+#define I2C_BUS_OFFS (0x000)
+#endif /* CONFIG_I2C_MULTI_BUS */
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS)
+#elif defined(CONFIG_440)
+/* all remaining 440 variants */
+#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400 + I2C_BUS_OFFS)
+#else
+/* all 405 variants */
+#define I2C_BASE_ADDR (0xEF600500 + I2C_BUS_OFFS)
+#endif
+
+#define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR
+#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
+#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
+#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
+#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
+#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
+#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
+#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS)
+#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
+#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
+#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
+#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
+#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
+#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
+#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
+#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
+
+/* MDCNTL Register Bit definition */
+#define IIC_MDCNTL_HSCL 0x01
+#define IIC_MDCNTL_EUBS 0x02
+#define IIC_MDCNTL_EINT 0x04
+#define IIC_MDCNTL_ESM 0x08
+#define IIC_MDCNTL_FSM 0x10
+#define IIC_MDCNTL_EGC 0x20
+#define IIC_MDCNTL_FMDB 0x40
+#define IIC_MDCNTL_FSDB 0x80
+
+/* CNTL Register Bit definition */
+#define IIC_CNTL_PT 0x01
+#define IIC_CNTL_READ 0x02
+#define IIC_CNTL_CHT 0x04
+#define IIC_CNTL_RPST 0x08
+/* bit 2/3 for Transfer count*/
+#define IIC_CNTL_AMD 0x40
+#define IIC_CNTL_HMT 0x80
+
+/* STS Register Bit definition */
+#define IIC_STS_PT 0x01
+#define IIC_STS_IRQA 0x02
+#define IIC_STS_ERR 0x04
+#define IIC_STS_SCMP 0x08
+#define IIC_STS_MDBF 0x10
+#define IIC_STS_MDBS 0x20
+#define IIC_STS_SLPR 0x40
+#define IIC_STS_SSS 0x80
+
+/* EXTSTS Register Bit definition */
+#define IIC_EXTSTS_XFRA 0x01
+#define IIC_EXTSTS_ICT 0x02
+#define IIC_EXTSTS_LA 0x04
+
+/* XTCNTLSS Register Bit definition */
+#define IIC_XTCNTLSS_SRST 0x01
+#define IIC_XTCNTLSS_EPI 0x02
+#define IIC_XTCNTLSS_SDBF 0x04
+#define IIC_XTCNTLSS_SBDD 0x08
+#define IIC_XTCNTLSS_SWS 0x10
+#define IIC_XTCNTLSS_SWC 0x20
+#define IIC_XTCNTLSS_SRS 0x40
+#define IIC_XTCNTLSS_SRC 0x80
+
+/* IICx_DIRECTCNTL register */
+#define IIC_DIRCNTL_SDAC 0x08
+#define IIC_DIRCNTL_SCC 0x04
+#define IIC_DIRCNTL_MSDA 0x02
+#define IIC_DIRCNTL_MSC 0x01
+
+#define DIRCTNL_FREE(v) (((v) & 0x0f) == 0x0f)
+#endif
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index 648a10d..47c18e7 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -29,6 +29,10 @@
#include <asm/arch/hardware.h>
#endif /* XXX###XXX */
+static inline void sync(void)
+{
+}
+
/*
* Generic virtual read/write. Note that we don't support half-word
* read/writes. We define __arch_*[bl] here, and leave __arch_*w
diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h
index e86c456..3c0d569 100644
--- a/include/asm-avr32/io.h
+++ b/include/asm-avr32/io.h
@@ -89,4 +89,8 @@ static __inline__ void * phys_to_virt(unsigned long address)
#endif /* __KERNEL__ */
+static inline void sync(void)
+{
+}
+
#endif /* __ASM_AVR32_IO_H */
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
index e5b388e..fc27194 100644
--- a/include/asm-blackfin/io.h
+++ b/include/asm-blackfin/io.h
@@ -25,6 +25,11 @@
#ifndef _BLACKFIN_IO_H
#define _BLACKFIN_IO_H
+static inline void sync(void)
+{
+ __asm__ __volatile__ asm("ssync" : : : "memory");
+}
+
#ifdef __KERNEL__
#include <linux/config.h>
diff --git a/include/asm-i386/io.h b/include/asm-i386/io.h
index 85d44aa..e64d788 100644
--- a/include/asm-i386/io.h
+++ b/include/asm-i386/io.h
@@ -201,4 +201,8 @@ __OUTS(b)
__OUTS(w)
__OUTS(l)
+static inline void sync(void)
+{
+}
+
#endif
diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h
index 79a9626..7bbdefb 100644
--- a/include/asm-m68k/io.h
+++ b/include/asm-m68k/io.h
@@ -1 +1,8 @@
-/* */
+#ifndef __ASM_M68K_IO_H_
+#define __ASM_M68K_IO_H_
+
+static inline void sync(void)
+{
+}
+
+#endif /* __ASM_M68K_IO_H_ */
diff --git a/include/asm-microblaze/io.h b/include/asm-microblaze/io.h
index 3359045..1c77ade 100644
--- a/include/asm-microblaze/io.h
+++ b/include/asm-microblaze/io.h
@@ -125,4 +125,8 @@ io_outsl (unsigned long port, const void *src, unsigned long count)
#define ioremap_writethrough(physaddr, size) (physaddr)
#define ioremap_fullcache(physaddr, size) (physaddr)
+static inline void sync(void)
+{
+}
+
#endif /* __MICROBLAZE_IO_H__ */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 857fb03..cd4d5dc 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -447,4 +447,8 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
#define dma_cache_wback(start,size) _dma_cache_wback(start,size)
#define dma_cache_inv(start,size) _dma_cache_inv(start,size)
+static inline void sync(void)
+{
+}
+
#endif /* _ASM_IO_H */
diff --git a/include/asm-nios/io.h b/include/asm-nios/io.h
index 07499d9..d77695a 100644
--- a/include/asm-nios/io.h
+++ b/include/asm-nios/io.h
@@ -97,4 +97,8 @@ static inline void outsl (unsigned long port, const void *src, unsigned long cou
while (count--) outl (*p++, port);
}
+static inline void sync(void)
+{
+}
+
#endif /* __ASM_NIOS_IO_H_ */
diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h
index 0fab53b..5bb5322 100644
--- a/include/asm-nios2/io.h
+++ b/include/asm-nios2/io.h
@@ -24,7 +24,10 @@
#ifndef __ASM_NIOS2_IO_H_
#define __ASM_NIOS2_IO_H_
-#define sync() asm volatile ("sync" : : : "memory");
+static inline void sync(void)
+{
+ __asm__ __volatile__ ("sync" : : : "memory");
+}
extern unsigned char inb (unsigned char *port);
extern unsigned short inw (unsigned short *port);
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index 8e5fe11..bbc9ba0 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -95,8 +95,15 @@ extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
* Acts as a barrier to ensure all previous I/O accesses have
* completed before any further ones are issued.
*/
-#define eieio() __asm__ __volatile__ ("eieio" : : : "memory");
-#define sync() __asm__ __volatile__ ("sync" : : : "memory");
+static inline void eieio(void)
+{
+ __asm__ __volatile__ ("eieio" : : : "memory");
+}
+
+static inline void sync(void)
+{
+ __asm__ __volatile__ ("sync" : : : "memory");
+}
/* Enforce in-order execution of data I/O.
* No distinction between read/write on PPC; use eieio for all three.
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 914f28b..b226825 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -335,41 +335,6 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
* instructions.
*/
-#define TLB_LO 1
-#define TLB_HI 0
-
-#define TLB_DATA TLB_LO
-#define TLB_TAG TLB_HI
-
-/* Tag portion */
-
-#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */
-#define TLB_PAGESZ_MASK 0x00000380
-#define TLB_PAGESZ(x) (((x) & 0x7) << 7)
-#define PAGESZ_1K 0
-#define PAGESZ_4K 1
-#define PAGESZ_16K 2
-#define PAGESZ_64K 3
-#define PAGESZ_256K 4
-#define PAGESZ_1M 5
-#define PAGESZ_4M 6
-#define PAGESZ_16M 7
-#define TLB_VALID 0x00000040 /* Entry is valid */
-
-/* Data portion */
-
-#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */
-#define TLB_PERM_MASK 0x00000300
-#define TLB_EX 0x00000200 /* Instruction execution allowed */
-#define TLB_WR 0x00000100 /* Writes permitted */
-#define TLB_ZSEL_MASK 0x000000F0
-#define TLB_ZSEL(x) (((x) & 0xF) << 4)
-#define TLB_ATTR_MASK 0x0000000F
-#define TLB_W 0x00000008 /* Caching is write-through */
-#define TLB_I 0x00000004 /* Caching is inhibited */
-#define TLB_M 0x00000002 /* Memory is coherent */
-#define TLB_G 0x00000001 /* Memory is guarded from prefetch */
-
/*
* e500 support
*/
@@ -482,7 +447,162 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23)
#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24)
-#ifdef CONFIG_440SPE
+#ifdef CONFIG_440
+/* General */
+#define TLB_VALID 0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K 0x00000000
+#define SZ_4K 0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K 0x00000040
+#define SZ_1M 0x00000050
+#define SZ_16M 0x00000070
+#define SZ_256M 0x00000090
+
+/* Storage attributes */
+#define SA_W 0x00000800 /* Write-through */
+#define SA_I 0x00000400 /* Caching inhibited */
+#define SA_M 0x00000200 /* Memory coherence */
+#define SA_G 0x00000100 /* Guarded */
+#define SA_E 0x00000080 /* Endian */
+
+/* Access control */
+#define AC_X 0x00000024 /* Execute */
+#define AC_W 0x00000012 /* Write */
+#define AC_R 0x00000009 /* Read */
+
+/* Some handy macros */
+
+#define EPN(e) ((e) & 0xfffffc00)
+#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID ))
+#define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn))
+#define TLB2(a) ((a) & 0x00000fbf)
+
+#define tlbtab_start\
+ mflr r1 ;\
+ bl 0f ;
+
+#define tlbtab_end\
+ .long 0, 0, 0 ;\
+0: mflr r0 ;\
+ mtlr r1 ;\
+ blr ;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+/*----------------------------------------------------------------------------+
+| TLB specific defines.
++----------------------------------------------------------------------------*/
+#define TLB_256MB_ALIGN_MASK 0xF0000000
+#define TLB_16MB_ALIGN_MASK 0xFF000000
+#define TLB_1MB_ALIGN_MASK 0xFFF00000
+#define TLB_256KB_ALIGN_MASK 0xFFFC0000
+#define TLB_64KB_ALIGN_MASK 0xFFFF0000
+#define TLB_16KB_ALIGN_MASK 0xFFFFC000
+#define TLB_4KB_ALIGN_MASK 0xFFFFF000
+#define TLB_1KB_ALIGN_MASK 0xFFFFFC00
+#define TLB_256MB_SIZE 0x10000000
+#define TLB_16MB_SIZE 0x01000000
+#define TLB_1MB_SIZE 0x00100000
+#define TLB_256KB_SIZE 0x00040000
+#define TLB_64KB_SIZE 0x00010000
+#define TLB_16KB_SIZE 0x00004000
+#define TLB_4KB_SIZE 0x00001000
+#define TLB_1KB_SIZE 0x00000400
+
+#define TLB_WORD0_EPN_MASK 0xFFFFFC00
+#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD0_V_MASK 0x00000200
+#define TLB_WORD0_V_ENABLE 0x00000200
+#define TLB_WORD0_V_DISABLE 0x00000000
+#define TLB_WORD0_TS_MASK 0x00000100
+#define TLB_WORD0_TS_1 0x00000100
+#define TLB_WORD0_TS_0 0x00000000
+#define TLB_WORD0_SIZE_MASK 0x000000F0
+#define TLB_WORD0_SIZE_1KB 0x00000000
+#define TLB_WORD0_SIZE_4KB 0x00000010
+#define TLB_WORD0_SIZE_16KB 0x00000020
+#define TLB_WORD0_SIZE_64KB 0x00000030
+#define TLB_WORD0_SIZE_256KB 0x00000040
+#define TLB_WORD0_SIZE_1MB 0x00000050
+#define TLB_WORD0_SIZE_16MB 0x00000070
+#define TLB_WORD0_SIZE_256MB 0x00000090
+#define TLB_WORD0_TPAR_MASK 0x0000000F
+#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
+#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
+
+#define TLB_WORD1_RPN_MASK 0xFFFFFC00
+#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD1_PAR1_MASK 0x00000300
+#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
+#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
+#define TLB_WORD1_PAR1_0 0x00000000
+#define TLB_WORD1_PAR1_1 0x00000100
+#define TLB_WORD1_PAR1_2 0x00000200
+#define TLB_WORD1_PAR1_3 0x00000300
+#define TLB_WORD1_ERPN_MASK 0x0000000F
+#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
+#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
+
+#define TLB_WORD2_PAR2_MASK 0xC0000000
+#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
+#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
+#define TLB_WORD2_PAR2_0 0x00000000
+#define TLB_WORD2_PAR2_1 0x40000000
+#define TLB_WORD2_PAR2_2 0x80000000
+#define TLB_WORD2_PAR2_3 0xC0000000
+#define TLB_WORD2_U0_MASK 0x00008000
+#define TLB_WORD2_U0_ENABLE 0x00008000
+#define TLB_WORD2_U0_DISABLE 0x00000000
+#define TLB_WORD2_U1_MASK 0x00004000
+#define TLB_WORD2_U1_ENABLE 0x00004000
+#define TLB_WORD2_U1_DISABLE 0x00000000
+#define TLB_WORD2_U2_MASK 0x00002000
+#define TLB_WORD2_U2_ENABLE 0x00002000
+#define TLB_WORD2_U2_DISABLE 0x00000000
+#define TLB_WORD2_U3_MASK 0x00001000
+#define TLB_WORD2_U3_ENABLE 0x00001000
+#define TLB_WORD2_U3_DISABLE 0x00000000
+#define TLB_WORD2_W_MASK 0x00000800
+#define TLB_WORD2_W_ENABLE 0x00000800
+#define TLB_WORD2_W_DISABLE 0x00000000
+#define TLB_WORD2_I_MASK 0x00000400
+#define TLB_WORD2_I_ENABLE 0x00000400
+#define TLB_WORD2_I_DISABLE 0x00000000
+#define TLB_WORD2_M_MASK 0x00000200
+#define TLB_WORD2_M_ENABLE 0x00000200
+#define TLB_WORD2_M_DISABLE 0x00000000
+#define TLB_WORD2_G_MASK 0x00000100
+#define TLB_WORD2_G_ENABLE 0x00000100
+#define TLB_WORD2_G_DISABLE 0x00000000
+#define TLB_WORD2_E_MASK 0x00000080
+#define TLB_WORD2_E_ENABLE 0x00000080
+#define TLB_WORD2_E_DISABLE 0x00000000
+#define TLB_WORD2_UX_MASK 0x00000020
+#define TLB_WORD2_UX_ENABLE 0x00000020
+#define TLB_WORD2_UX_DISABLE 0x00000000
+#define TLB_WORD2_UW_MASK 0x00000010
+#define TLB_WORD2_UW_ENABLE 0x00000010
+#define TLB_WORD2_UW_DISABLE 0x00000000
+#define TLB_WORD2_UR_MASK 0x00000008
+#define TLB_WORD2_UR_ENABLE 0x00000008
+#define TLB_WORD2_UR_DISABLE 0x00000000
+#define TLB_WORD2_SX_MASK 0x00000004
+#define TLB_WORD2_SX_ENABLE 0x00000004
+#define TLB_WORD2_SX_DISABLE 0x00000000
+#define TLB_WORD2_SW_MASK 0x00000002
+#define TLB_WORD2_SW_ENABLE 0x00000002
+#define TLB_WORD2_SW_DISABLE 0x00000000
+#define TLB_WORD2_SR_MASK 0x00000001
+#define TLB_WORD2_SR_ENABLE 0x00000001
+#define TLB_WORD2_SR_DISABLE 0x00000000
+
/*----------------------------------------------------------------------------+
| Following instructions are not available in Book E mode of the GNU assembler.
+----------------------------------------------------------------------------*/
@@ -516,11 +636,15 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define MBAR_INST .long 0x7c000000|\
(854<<1)
-/*----------------------------------------------------------------------------+
-| Following instruction is not available in PPC405 mode of the GNU assembler.
-+----------------------------------------------------------------------------*/
-#define TLBRE(rt,ra,ws) .long 0x7c000000|\
- (rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
+#ifndef __ASSEMBLY__
+/* Prototypes */
+void mttlb1(unsigned long index, unsigned long value);
+void mttlb2(unsigned long index, unsigned long value);
+void mttlb3(unsigned long index, unsigned long value);
+unsigned long mftlb1(unsigned long index);
+unsigned long mftlb2(unsigned long index);
+unsigned long mftlb3(unsigned long index);
+#endif /* __ASSEMBLY__ */
-#endif
+#endif /* CONFIG_440 */
#endif /* _PPC_MMU_H_ */
diff --git a/include/common.h b/include/common.h
index 982d6a8..b162dbd 100644
--- a/include/common.h
+++ b/include/common.h
@@ -187,6 +187,7 @@ void hang (void) __attribute__ ((noreturn));
long int initdram (int);
int display_options (void);
void print_size (ulong, const char *);
+int print_buffer (ulong addr, void* data, uint width, uint count, uint linelen);
/* common/main.c */
void main_loop (void);
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
new file mode 100644
index 0000000..c750e14
--- /dev/null
+++ b/include/configs/katmai.h
@@ -0,0 +1,415 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * katmai.h - configuration for AMCC Katmai (440SPe)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_KATMAI 1 /* Board is Katmai */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_440 1 /* ... PPC440 family */
+#define CONFIG_440SPE 1 /* Specifc SPe support */
+#undef CFG_DRAM_TEST /* Disable-takes long time */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
+#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
+
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xff000000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
+#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
+
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
+#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
+#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
+
+#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
+#define CFG_PCIE_MEMSIZE 0x01000000
+#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
+
+#define CFG_PCIE0_CFGBASE 0xc0000000
+#define CFG_PCIE0_XCFGBASE 0xc0000400
+#define CFG_PCIE1_CFGBASE 0xc0001000
+#define CFG_PCIE1_XCFGBASE 0xc0001400
+#define CFG_PCIE2_CFGBASE 0xc0002000
+#define CFG_PCIE2_XCFGBASE 0xc0002400
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
+
+#define CFG_ACE_BASE 0xe0000000 /* Xilinx ACE controller - Compact Flash */
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM 1
+#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_SERIAL_MULTI 1
+#undef CONFIG_UART1_CONSOLE
+#undef CFG_EXT_SERIAL_CLOCK
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
+#define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses */
+#define IIC0_DIMM0_ADDR 0x51
+#define IIC0_DIMM1_ADDR 0x52
+#undef CONFIG_STRESS
+#undef ENABLE_ECC
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CFG_SPD_BUS_NUM 0 /* The I2C bus for SPD */
+
+#define IIC0_BOOTPROM_ADDR 0x50
+#define IIC0_ALT_BOOTPROM_ADDR 0x54
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR (0x50)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11 1
+#define CFG_RTC_BUS_NUM 1 /* The I2C bus for RTC */
+#define CFG_I2C_RTC_ADDR 0x68
+#define CFG_M41T11_BASE_YEAR 1900 /* play along with linux */
+
+/* I2C DTT */
+#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
+#define CFG_DTT_BUS_NUM 1 /* The I2C bus for DTT */
+/*
+ * standard dtt sensor configuration - bottom bit will determine local or
+ * remote sensor of the ADM1021, the rest determines index into
+ * CFG_DTT_ADM1021 array below.
+ */
+#define CONFIG_DTT_SENSORS { 0, 1 }
+
+/*
+ * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
+ * there will be one entry in this array for each two (dummy) sensors in
+ * CONFIG_DTT_SENSORS.
+ *
+ * For Katmai board:
+ * - only one ADM1021
+ * - i2c addr 0x18
+ * - conversion rate 0x02 = 0.25 conversions/second
+ * - ALERT ouput disabled
+ * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
+ * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
+ */
+#define CFG_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=katmai\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=katmai/uImage\0" \
+ "kernel_addr=fff10000\0" \
+ "ramdisk_addr=fff20000\0" \
+ "initrd_high=30000000\0" \
+ "load=tftp 200000 katmai/u-boot.bin\0" \
+ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
+ "cp.b ${fileaddr} fffc0000 ${filesize};" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ "kozio=bootm ffc60000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_DTT | \
+ CFG_CMD_ELF | \
+ CFG_CMD_EXT2 | \
+ CFG_CMD_FAT | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
+#define CONFIG_HAS_ETH0
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_RESET_DELAY 1000
+#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* needed for NetConsole */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
+#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */
+#define CFG_PCI_TARGET_INIT /* let board init pci target */
+#undef CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+/* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */
+
+/*
+ * NETWORK Support (PCI):
+ */
+/* Support for Intel 82557/82559/82559ER chips. */
+#define CONFIG_EEPRO100
+
+/*-----------------------------------------------------------------------
+ * Xilinx System ACE support
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */
+#define CFG_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
+#define CFG_SYSTEMACE_BASE CFG_ACE_BASE
+#define CONFIG_DOS_PARTITION 1
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+
+/* Memory Bank 0 (Flash) initialization */
+#define CFG_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
+ EBC_BXAP_TWT_ENCODE(7) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(0) | \
+ EBC_BXAP_WBN_ENCODE(0) | \
+ EBC_BXAP_WBF_ENCODE(0) | \
+ EBC_BXAP_TH_ENCODE(0) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_DELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CFG_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | \
+ EBC_BXCR_BS_16MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 1 (Xilinx System ACE controller) initialization */
+#define CFG_EBC_PB1AP 0x7F8FFE80
+#define CFG_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CFG_ACE_BASE) | \
+ EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/*-------------------------------------------------------------------------
+ * Initialize EBC CONFIG -
+ * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
+ * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
+ *-------------------------------------------------------------------------*/
+#define CFG_EBC_CFG (EBC_CFG_LE_UNLOCK | \
+ EBC_CFG_PTD_ENABLE | \
+ EBC_CFG_RTC_16PERCLK | \
+ EBC_CFG_ATC_PREVIOUS | \
+ EBC_CFG_DTC_PREVIOUS | \
+ EBC_CFG_CTC_PREVIOUS | \
+ EBC_CFG_OEO_PREVIOUS | \
+ EBC_CFG_EMC_DEFAULT | \
+ EBC_CFG_PME_DISABLE | \
+ EBC_CFG_PR_16)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index f60973b..621a81c 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -265,6 +265,7 @@
*/
#if !defined(CONFIG_PRS200)
#define CONFIG_LCD 1
+#define CONFIG_PROGRESSBAR 1
#endif
#if defined(CONFIG_LCD)
diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h
index ccb0293..0c10294 100644
--- a/include/configs/mecp5200.h
+++ b/include/configs/mecp5200.h
@@ -88,10 +88,10 @@
/* USB */
#if 0
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
+#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
#else
-#define ADD_USB_CMD 0
+#define ADD_USB_CMD 0
#endif
/*
@@ -100,7 +100,7 @@
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_EEPROM | \
CFG_CMD_FAT | \
- CFG_CMD_EXT2 | \
+ CFG_CMD_EXT2 | \
CFG_CMD_I2C | \
CFG_CMD_IDE | \
CFG_CMD_BSP | \
@@ -110,11 +110,11 @@
#include <cmd_confdefs.h>
#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
-# define CFG_LOWBOOT 1
+# define CFG_LOWBOOT 1
# define CFG_LOWBOOT16 1
#endif
#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
-# define CFG_LOWBOOT 1
+# define CFG_LOWBOOT 1
# define CFG_LOWBOOT08 1
#endif
@@ -131,20 +131,20 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
- "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
- "net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
- "vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
- "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
- "loadaddr=01000000\0" \
- "serverip=192.168.2.99\0" \
- "gatewayip=10.0.0.79\0" \
- "user=mu\0" \
- "target=mecp5200.esd\0" \
- "script=mecp5200.bat\0" \
- "image=/tftpboot/vxWorks_mecp5200\0" \
- "ipaddr=10.0.13.196\0" \
- "netmask=255.255.0.0\0" \
+ "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
+ "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
+ "net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
+ "vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
+ "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
+ "loadaddr=01000000\0" \
+ "serverip=192.168.2.99\0" \
+ "gatewayip=10.0.0.79\0" \
+ "user=mu\0" \
+ "target=mecp5200.esd\0" \
+ "script=mecp5200.bat\0" \
+ "image=/tftpboot/vxWorks_mecp5200\0" \
+ "ipaddr=10.0.13.196\0" \
+ "netmask=255.255.0.0\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
@@ -171,12 +171,12 @@
#define CFG_I2C_EEPROM_ADDR_LEN 2
#define CFG_EEPROM_PAGE_WRITE_BITS 5
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CFG_I2C_MULTI_EEPROMS 1
+#define CFG_I2C_MULTI_EEPROMS 1
/*
* Flash configuration
*/
#define CFG_FLASH_BASE 0xFFC00000
-#define CFG_FLASH_SIZE 0x00400000
+#define CFG_FLASH_SIZE 0x00400000
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x003E0000)
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
#define CFG_MAX_FLASH_SECT 512
@@ -200,15 +200,15 @@
#define CONFIG_ENV_OVERWRITE 1
#endif
-#define CFG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
+#define CFG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
#if 0
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#endif
-#define CFG_FLASH_INCREMENT 0x00400000 /* size of flash bank */
+#define CFG_FLASH_INCREMENT 0x00400000 /* size of flash bank */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
-#define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */
+#define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */
/*
@@ -272,7 +272,7 @@
#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
@@ -339,7 +339,7 @@
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET (0x005C)
-/* Interval between registers */
-#define CFG_ATA_STRIDE 4
+/* Interval between registers */
+#define CFG_ATA_STRIDE 4
#endif /* __CONFIG_H */
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 098aa3f..29f3b40 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -391,7 +391,7 @@
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CFG_EBC_PB0AP 0x03017300
+#define CFG_EBC_PB0AP 0x03017200
#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000)
/* Memory Bank 3 (NAND-FLASH) initialization */
@@ -400,7 +400,7 @@
#else
#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
/* Memory Bank 3 (NOR-FLASH) initialization */
-#define CFG_EBC_PB3AP 0x03017300
+#define CFG_EBC_PB3AP 0x03017200
#define CFG_EBC_PB3CR (CFG_FLASH | 0xda000)
/* Memory Bank 0 (NAND-FLASH) initialization */
diff --git a/include/i2c.h b/include/i2c.h
index a8f729a..54c6f9f 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -46,6 +46,16 @@
*/
#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
+#if defined(CONFIG_I2C_MULTI_BUS)
+#define CFG_MAX_I2C_BUS 2
+#define I2C_GET_BUS() i2c_get_bus_num()
+#define I2C_SET_BUS(a) i2c_set_bus_num(a)
+#else
+#define CFG_MAX_I2C_BUS 1
+#define I2C_GET_BUS() 0
+#define I2C_SET_BUS(a)
+#endif
+
/*
* Initialization, must be called once on start up, may be called
* repeatedly to change the speed and slave addresses.
diff --git a/include/ide.h b/include/ide.h
index dfef32f..6976a6c 100644
--- a/include/ide.h
+++ b/include/ide.h
@@ -48,8 +48,8 @@ typedef ulong lbaint_t;
* Function Prototypes
*/
-void ide_init (void);
-ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer);
-ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer);
+void ide_init(void);
+ulong ide_read(int device, lbaint_t blknr, ulong blkcnt, void *buffer);
+ulong ide_write(int device, lbaint_t blknr, ulong blkcnt, void *buffer);
#endif /* _IDE_H */
diff --git a/include/part.h b/include/part.h
index 318aa3c..29c0320 100644
--- a/include/part.h
+++ b/include/part.h
@@ -22,6 +22,7 @@
*/
#ifndef _PART_H
#define _PART_H
+
#include <ide.h>
typedef struct block_dev_desc {
@@ -43,7 +44,11 @@ typedef struct block_dev_desc {
unsigned long (*block_read)(int dev,
unsigned long start,
lbaint_t blkcnt,
- unsigned long *buffer);
+ void *buffer);
+ unsigned long (*block_write)(int dev,
+ unsigned long start,
+ lbaint_t blkcnt,
+ const void *buffer);
}block_dev_desc_t;
/* Interface types: */
@@ -83,6 +88,14 @@ typedef struct disk_partition {
uchar type[32]; /* string type description */
} disk_partition_t;
+/* Misc _get_dev functions */
+block_dev_desc_t* get_dev(char* ifname, int dev);
+block_dev_desc_t* ide_get_dev(int dev);
+block_dev_desc_t* scsi_get_dev(int dev);
+block_dev_desc_t* usb_stor_get_dev(int dev);
+block_dev_desc_t* mmc_get_dev(int dev);
+block_dev_desc_t* systemace_get_dev(int dev);
+
/* disk/part.c */
int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
void print_part (block_dev_desc_t *dev_desc);
diff --git a/include/ppc405.h b/include/ppc405.h
index e475fa5..a49912c 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -240,6 +240,7 @@
#define pbesr0 0x21 /* periph bus error status reg 0 */
#define pbesr1 0x22 /* periph bus error status reg 1 */
#define epcr 0x23 /* external periph control reg */
+#define EBC0_CFG 0x23 /* external bus configuration reg */
#ifdef CONFIG_405EP
/******************************************************************************
diff --git a/include/ppc440.h b/include/ppc440.h
index 91cff41..c24f5b7 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -533,9 +533,12 @@
#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
-#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */
+#define SDRAM_MCSTAT_SRMS_MASK 0x40000000 /* Mem self refresh stat mask */
#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
-#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */
+#define SDRAM_MCSTAT_SRMS_SF 0x40000000 /* Mem in self refresh */
+#define SDRAM_MCSTAT_IDLE_MASK 0x20000000 /* Mem self refresh stat mask */
+#define SDRAM_MCSTAT_IDLE_NOT 0x00000000 /* Mem contr not idle */
+#define SDRAM_MCSTAT_IDLE 0x20000000 /* Mem contr idle */
/*-----------------------------------------------------------------------------+
| Memory Controller Options 1
@@ -730,6 +733,7 @@
#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
#define SDRAM_WRDTR_WTR_MASK 0x0E000000
#define SDRAM_WRDTR_WTR_0_DEG 0x06000000
+#define SDRAM_WRDTR_WTR_90_DEG_ADV 0x04000000
#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
@@ -847,6 +851,7 @@
#define pbear 0x20 /* periph bus error addr reg */
#define pbesr 0x21 /* periph bus error status reg */
#define xbcfg 0x23 /* external bus configuration reg */
+#define EBC0_CFG 0x23 /* external bus configuration reg */
#define xbcid 0x24 /* external bus core id reg */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
generated by cgit v1.1 at 2024-12-13 02:16:07 +0000