5 files changed, 55 insertions, 14 deletions
diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h
index 0174d62..a1ef029 100644
--- a/include/asm-ppc/ppc4xx-sdram.h
+++ b/include/asm-ppc/ppc4xx-sdram.h
@@ -29,6 +29,7 @@
 /*
  * SDRAM Controller
  */
+
 /*
  * XXX - ToDo: Revisit file to change all these lower case defines into
  * upper case. Also needs to be done in the controller setup code too
@@ -256,6 +257,7 @@
 #define SDRAM_DLYCAL_DLCV_ENCODE(x)	(((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
 #define SDRAM_DLYCAL_DLCV_DECODE(x)	(((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
 
+#if !defined(CONFIG_405EX)
 /*
  * Memory queue defines
  */
@@ -293,7 +295,6 @@
 
 #define SDRAM_PLBADDUHB		(SDRAMQ_DCR_BASE+0x10)  /* PLB base address upper 32 LL */
 
-#if !defined(CONFIG_405EX)
 /*
  * Memory Bank 0-7 configuration
  */
diff --git a/include/common.h b/include/common.h
index a394988..2516bfd 100644
--- a/include/common.h
+++ b/include/common.h
@@ -287,6 +287,27 @@ void	pciinfo	      (int, int);
 #endif
 #endif
 
+/*
+ * Prototypes
+ */
+#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
+void blank_string(int);
+inline void ppc4xx_ibm_ddr2_register_dump(void);
+#if defined(CONFIG_440)
+u32 mfdcr_any(u32);
+void mtdcr_any(u32, u32);
+#endif
+#if defined(CONFIG_SPD_EEPROM)
+u32 ddr_wrdtr(u32);
+u32 ddr_clktr(u32);
+void spd_ddr_init_hang(void);
+#endif
+#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) */
+
+#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
+u32 DQS_autocalibration(void);
+#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
+
 int	misc_init_f   (void);
 int	misc_init_r   (void);
 
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index a475f97..f9eaa77 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -223,6 +223,22 @@
  *----------------------------------------------------------------------*/
 #define CFG_MBYTES_SDRAM        (256)		/* 256MB			*/
 
+/*
+ * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
+ *
+ * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
+ *       SDRAM Controller DDR autocalibration values and takes a lot longer
+ *       to run than Method_B.
+ * (See the Method_A and Method_B algorithm discription in the file:
+ *	cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
+ * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
+ *
+ * DDR Autocalibration Method_B is the default.
+ */
+#define	CONFIG_PPC4xx_DDR_AUTOCALIBRATION	/* IBM DDR autocalibration */
+#define	DEBUG_PPC4xx_DDR_AUTOCALIBRATION	/* dynamic DDR autocal debug */
+#undef	CONFIG_PPC4xx_DDR_METHOD_A
+
 #define	CFG_SDRAM0_MB0CF_BASE	((  0 << 20) + CFG_SDRAM_BASE)
 
 /* DDR1/2 SDRAM Device Control Register Data Values */
@@ -386,6 +402,9 @@
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"   */
 #define CONFIG_PHY1_ADDR	2
 
+/* Debug messages for the DDR autocalibration */
+#define CONFIG_AUTOCALIB		"silent\0"  /* default is non-verbose */
+
 /*
  * Default environment variables
  */
diff --git a/include/ppc440.h b/include/ppc440.h
index 3584fd2..be8d3ff 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -2064,19 +2064,6 @@
 
 #ifndef __ASSEMBLY__
 
-static inline u32 get_mcsr(void)
-{
-	u32 val;
-
-	asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
-	return val;
-}
-
-static inline void set_mcsr(u32 val)
-{
-	asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
-}
-
 #endif	/* _ASMLANGUAGE */
 
 #endif	/* __PPC440_H__ */
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index 59a3b06..e216663 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -203,6 +203,19 @@ typedef struct
 	unsigned long pllPlbDiv;
 } PPC4xx_SYS_INFO;
 
+static inline u32 get_mcsr(void)
+{
+	u32 val;
+
+	asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
+	return val;
+}
+
+static inline void set_mcsr(u32 val)
+{
+	asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
+}
+
 #endif	/* __ASSEMBLY__ */
 
 #endif	/* __PPC4XX_H__ */