diff options
Diffstat (limited to 'include')
202 files changed, 5128 insertions, 1057 deletions
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 0abcbe4..a6d1d2a 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -55,20 +55,6 @@ typedef struct global_data { unsigned long relocaddr; /* Start address of U-Boot in RAM */ phys_size_t ram_size; /* RAM size */ -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE -#define MEM_RESERVE_SECURE_SECURED 0x1 -#define MEM_RESERVE_SECURE_MAINTAINED 0x2 -#define MEM_RESERVE_SECURE_ADDR_MASK (~0x3) - /* - * Secure memory addr - * This variable needs maintenance if the RAM base is not zero, - * or if RAM splits into non-consecutive banks. It also has a - * flag indicating the secure memory is marked as secure by MMU. - * Flags used: 0x1 secured - * 0x2 maintained - */ - phys_addr_t secure_ram; -#endif unsigned long mon_len; /* monitor len */ unsigned long irq_sp; /* irq stack pointer */ unsigned long start_addr_sp; /* start_addr_stackpointer */ diff --git a/include/clk.h b/include/clk.h index 2f31cf7..dc18b03 100644 --- a/include/clk.h +++ b/include/clk.h @@ -60,6 +60,10 @@ struct clk { }; #if CONFIG_IS_ENABLED(OF_CONTROL) +struct phandle_2_cell; +int clk_get_by_index_platdata(struct udevice *dev, int index, + struct phandle_2_cell *cells, struct clk *clk); + /** * clock_get_by_index - Get/request a clock by integer index. * @@ -100,7 +104,7 @@ static inline int clk_get_by_index(struct udevice *dev, int index, return -ENOSYS; } -static int clk_get_by_name(struct udevice *dev, const char *name, +static inline int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk) { return -ENOSYS; diff --git a/include/common.h b/include/common.h index 3feaae6..e9f0dea 100644 --- a/include/common.h +++ b/include/common.h @@ -101,6 +101,13 @@ typedef volatile unsigned char vu_char; #define _DEBUG 0 #endif +#ifdef CONFIG_SPL_BUILD +#define _SPL_BUILD 1 +#else +#define _SPL_BUILD 0 +#endif + +/* Define this at the top of a file to add a prefix to debug messages */ #ifndef pr_fmt #define pr_fmt(fmt) fmt #endif @@ -116,9 +123,14 @@ typedef volatile unsigned char vu_char; printf(pr_fmt(fmt), ##args); \ } while (0) +/* Show a message if DEBUG is defined in a file */ #define debug(fmt, args...) \ debug_cond(_DEBUG, fmt, ##args) +/* Show a message if not in SPL */ +#define warn_non_spl(fmt, args...) \ + debug_cond(!_SPL_BUILD, fmt, ##args) + /* * An assertion is run-time check done in debug mode only. If DEBUG is not * defined then it is skipped. If DEBUG is defined and the assertion fails, diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h index 9244680..b5efab5 100644 --- a/include/config_distro_defaults.h +++ b/include/config_distro_defaults.h @@ -20,9 +20,6 @@ #define CONFIG_BOOTP_PXE #define CONFIG_BOOTP_SUBNETMASK -#ifdef CONFIG_ARM64 -#define CONFIG_CMD_BOOTI -#endif #define CONFIG_CMD_PXE #define CONFIG_CMDLINE_EDITING diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index 566fd80..eb45e98 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -74,23 +74,27 @@ #ifdef CONFIG_BOOTSCRIPT_COPY_RAM #define CONFIG_BS_COPY_ENV \ "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ - "setenv bs_hdr_flash " __stringify(CONFIG_BS_HDR_ADDR_FLASH)";" \ + "setenv bs_hdr_device " __stringify(CONFIG_BS_HDR_ADDR_DEVICE)";" \ "setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \ "setenv bs_ram " __stringify(CONFIG_BS_ADDR_RAM)";" \ - "setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \ + "setenv bs_device " __stringify(CONFIG_BS_ADDR_DEVICE)";" \ "setenv bs_size " __stringify(CONFIG_BS_SIZE)";" /* For secure boot flow, default environment used will be used */ #if defined(CONFIG_SYS_RAMBOOT) #if defined(CONFIG_RAMBOOT_NAND) #define CONFIG_BS_COPY_CMD \ - "nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \ - "nand read $bs_ram $bs_flash $bs_size ;" + "nand read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \ + "nand read $bs_ram $bs_device $bs_size ;" #endif /* CONFIG_RAMBOOT_NAND */ -#else +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_BS_COPY_CMD \ + "mmc read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \ + "mmc read $bs_ram $bs_device $bs_size ;" +#else /* CONFIG_SD_BOOT */ #define CONFIG_BS_COPY_CMD \ - "cp.b $bs_hdr_flash $bs_hdr_ram $bs_hdr_size ;" \ - "cp.b $bs_flash $bs_ram $bs_size ;" + "cp.b $bs_hdr_device $bs_hdr_ram $bs_hdr_size ;" \ + "cp.b $bs_device $bs_ram $bs_size ;" #endif #endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 2c3c4ac..7d9619e 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -13,7 +13,6 @@ * B4860 QDS board configuration file */ #define CONFIG_B4860QDS -#define CONFIG_PHYS_64BIT #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg @@ -830,7 +829,7 @@ unsigned long get_board_ddr_clk(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=b4860qds/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=b4860qds/b4860qds.dtb\0" \ "bdev=sda3\0" @@ -868,7 +867,7 @@ unsigned long get_board_ddr_clk(void); "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ + "setenv fdtaddr 0x01e00000;" \ "setenv loadaddr 0x1000000;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 0a9d8a6..f2a7c69 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -403,7 +403,7 @@ extern unsigned long get_sdram_size(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=bsc9131rdb.dtb\0" \ "bdev=sda1\0" \ "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 756beec..4744f08 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -647,7 +647,7 @@ combinations. this should be removed later "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=bsc9132qds.dtb\0" \ "bdev=sda1\0" \ CONFIG_DEF_HWCONFIG\ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 69a9798..f75919d 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -11,7 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_PHYS_64BIT #define CONFIG_DISPLAY_BOARDINFO #ifdef CONFIG_C29XPCIE @@ -530,7 +529,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=name/of/device-tree.dtb\0" \ "othbootargs=ramdisk_size=600000\0" \ diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 578325c..5b80464 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -203,7 +203,7 @@ */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* @@ -452,6 +452,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Core HID Setup diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 5613a4a..1c4e082 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -241,7 +241,7 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* @@ -268,7 +268,7 @@ #define CONFIG_CMD_MTDPARTS #define MTDIDS_DEFAULT "nand0=e2800000.flash" #define MTDPARTS_DEFAULT \ - "mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" + "mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_CMD_NAND 1 @@ -502,6 +502,7 @@ */ /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 7ce5f59..23a2e34 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -169,7 +169,7 @@ /* * The reserved memory */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* @@ -241,7 +241,7 @@ #define CONFIG_CMD_MTDPARTS #define MTDIDS_DEFAULT "nand0=e0600000.flash" #define MTDPARTS_DEFAULT \ - "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" + "mtdparts=e0600000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_CMD_NAND 1 @@ -489,6 +489,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Core HID Setup diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 13f954d..095c0d8 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -156,7 +156,7 @@ #endif /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* @@ -359,6 +359,7 @@ */ /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Core HID Setup diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index fd48260..18418e3 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -168,7 +168,7 @@ #endif /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* @@ -441,6 +441,7 @@ */ /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Core HID Setup diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 288b126..a2fa783 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -225,7 +225,7 @@ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* @@ -508,6 +508,7 @@ */ /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 2721255..c11c0cf 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -330,7 +330,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* @@ -544,6 +544,7 @@ boards, we say we have two, but don't display a message if we find only one. */ */ /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #define CONFIG_SYS_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 921d5f3..b2dc189 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -200,7 +200,7 @@ #endif /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* @@ -522,6 +522,7 @@ extern int board_pci_host_broken(void); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Core HID Setup diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index bb06e89..8eb87eb 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -225,7 +225,7 @@ #undef CONFIG_SYS_RAMBOOT #endif -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* @@ -533,6 +533,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Core HID Setup diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 7c19ff8..b536f67 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -14,10 +14,6 @@ #define CONFIG_DISPLAY_BOARDINFO #include "../board/freescale/common/ics307_clk.h" -#ifdef CONFIG_36BIT -#define CONFIG_PHYS_64BIT 1 -#endif - #ifdef CONFIG_SDCARD #define CONFIG_RAMBOOT_SDCARD 1 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 @@ -727,7 +723,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=8536ds/ramdisk.uboot\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "fdtfile=8536ds/mpc8536ds.dtb\0" \ "bdev=sda3\0" \ "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index b9d97c1..cd10432 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -209,7 +209,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 @@ -462,7 +462,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=8544ds/ramdisk.uboot\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "fdtfile=8544ds/mpc8544ds.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index e73be48..789c62b 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -15,10 +15,6 @@ #define CONFIG_DISPLAY_BOARDINFO -#ifdef CONFIG_36BIT -#define CONFIG_PHYS_64BIT -#endif - /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -562,7 +558,7 @@ extern unsigned long get_clock_freq(void); "consoledev=ttyS1\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=mpc8548cds.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 2e6989f..26cf8d6 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -15,10 +15,6 @@ #include "../board/freescale/common/ics307_clk.h" -#ifdef CONFIG_36BIT -#define CONFIG_PHYS_64BIT -#endif - #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif @@ -668,7 +664,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=8572ds/ramdisk.uboot\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "fdtfile=8572ds/mpc8572ds.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 8159493..c1b9b6e 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -477,7 +477,8 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ @@ -498,7 +499,7 @@ #define CONFIG_NETMASK 255.255.255.0 /* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 +#define CONFIG_LOADADDR 0x10000000 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ @@ -566,9 +567,9 @@ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ " $filesize\0" \ "consoledev=ttyS0\0" \ -"ramdiskaddr=2000000\0" \ +"ramdiskaddr=0x18000000\0" \ "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=0x17c00000\0" \ "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ "bdev=sda3\0" \ "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ @@ -604,9 +605,9 @@ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ + "ramdiskaddr=0x18000000\0" \ "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=0x17c00000\0" \ "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ "bdev=sda3\0" #endif diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index f90f7f2..1885124 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -23,7 +23,6 @@ #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ #define CONFIG_MP 1 /* support multiple processors */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ -/*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */ #define CONFIG_ADDR_MAP 1 /* Use addr map */ /* @@ -637,7 +636,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ @@ -664,7 +664,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_NETMASK 255.255.255.0 /* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 +#define CONFIG_LOADADDR 0x10000000 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ @@ -685,9 +685,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ " $filesize\0" \ "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ + "ramdiskaddr=0x18000000\0" \ "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=0x17c00000\0" \ "fdtfile=mpc8641_hpcn.dtb\0" \ "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 5384584..5ab6602 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -11,9 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifdef CONFIG_36BIT -#define CONFIG_PHYS_64BIT -#endif #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_P1010 @@ -862,7 +859,7 @@ extern unsigned long get_sdram_size(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=p1010rdb.dtb\0" \ "bdev=sda1\0" \ "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index bdf0323..5d572b4 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -13,10 +13,6 @@ #define CONFIG_DISPLAY_BOARDINFO -#ifdef CONFIG_36BIT -#define CONFIG_PHYS_64BIT -#endif - #ifdef CONFIG_SDCARD #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT #define CONFIG_SPL_ENV_SUPPORT @@ -731,7 +727,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=p1022ds.dtb\0" \ "bdev=sda3\0" \ "hwconfig=esdhc;audclk:12\0" diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index 07a594d..d044c7b 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -375,7 +375,7 @@ extern unsigned long get_clock_freq(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=p1023rdb.dtb\0" \ "othbootargs=ramdisk_size=600000\0" \ "bdev=sda1\0" \ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 24e5431..e6057f9 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -12,7 +12,6 @@ #define __CONFIG_H #define CONFIG_P2041RDB -#define CONFIG_PHYS_64BIT #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_PPC_P2041 @@ -698,7 +697,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); "usb_dr_mode=host\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=p2041rdb/p2041rdb.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index e05dd75..c901fe2 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -9,7 +9,6 @@ * */ #define CONFIG_P3041DS -#define CONFIG_PHYS_64BIT #define CONFIG_PPC_P3041 #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 2f89008..0d44c00 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -9,7 +9,6 @@ * Also supports P4040 DS */ #define CONFIG_P4080DS -#define CONFIG_PHYS_64BIT #define CONFIG_PPC_P4080 #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index 588df80..d2cedfe 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -9,7 +9,6 @@ * Also supports P5010 DS */ #define CONFIG_P5020DS -#define CONFIG_PHYS_64BIT #define CONFIG_PPC_P5020 #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h index e4a031a..dc82721 100644 --- a/include/configs/P5040DS.h +++ b/include/configs/P5040DS.h @@ -9,7 +9,6 @@ * */ #define CONFIG_P5040DS -#define CONFIG_PHYS_64BIT #define CONFIG_PPC_P5040 #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index b151963..2f18f52 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -18,7 +18,6 @@ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */ -#define CONFIG_PHYS_64BIT #define CONFIG_ENABLE_36BIT_PHYS #ifdef CONFIG_PHYS_64BIT diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 06d1d0f..8029ca8 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -18,7 +18,6 @@ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */ -#define CONFIG_PHYS_64BIT #define CONFIG_ENABLE_36BIT_PHYS #ifdef CONFIG_PHYS_64BIT @@ -897,7 +896,7 @@ unsigned long get_board_ddr_clk(void); "cmp.b $loadaddr $ubootaddr $filesize\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "bdev=sda3\0" #define CONFIG_LINUX \ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 9f5063c..b8c6e89 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -27,7 +27,6 @@ * T1040 QDS board configuration file */ #define CONFIG_T1040QDS -#define CONFIG_PHYS_64BIT #define CONFIG_DISPLAY_BOARDINFO #ifdef CONFIG_RAMBOOT_PBL @@ -770,7 +769,7 @@ unsigned long get_board_ddr_clk(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=t1040qds/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=t1040qds/t1040qds.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index a8f4f74..e583def 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -11,14 +11,20 @@ * T104x RDB board configuration file */ #define CONFIG_T104xRDB -#define CONFIG_PHYS_64BIT #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_E500 /* BOOKE e500 family */ #include <asm/config_mpc85xx.h> #ifdef CONFIG_RAMBOOT_PBL + +#ifndef CONFIG_SECURE_BOOT #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg +#else +#define CONFIG_SYS_FSL_PBL_PBI \ + $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg +#endif + #ifdef CONFIG_T1040RDB #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg #endif @@ -62,7 +68,17 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #ifdef CONFIG_NAND #define CONFIG_SPL_NAND_SUPPORT +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. + */ +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ + CONFIG_U_BOOT_HDR_SIZE) +#else #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#endif #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) @@ -161,6 +177,10 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (512 * 0x800) #elif defined(CONFIG_NAND) +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_RAMBOOT_NAND +#define CONFIG_BOOTSCRIPT_COPY_RAM +#endif #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE 0x2000 @@ -202,8 +222,14 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg * Config the L3 Cache as L3 SRAM */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +/* + * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence + * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address + * (CONFIG_SYS_INIT_L3_VADDR) will be different. + */ +#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 #define CONFIG_SYS_L3_SIZE 256 << 10 -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) #endif @@ -873,7 +899,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=" __stringify(FDTFILE) "\0" \ "bdev=sda3\0" diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 1f07a83..3f28549 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -26,7 +26,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_PHYS_64BIT #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ @@ -840,7 +839,7 @@ unsigned long get_board_ddr_clk(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=t2080qds/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=t2080qds/t2080qds.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 0ded41e..37d16ae 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -19,7 +19,6 @@ #define CONFIG_FSL_SATA_V2 /* High Level Configuration Options */ -#define CONFIG_PHYS_64BIT #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ @@ -792,7 +791,7 @@ unsigned long get_board_ddr_clk(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=t2080rdb/t2080rdb.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index f075dfb..8fffffe 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -11,7 +11,6 @@ #define __CONFIG_H #define CONFIG_T4240QDS -#define CONFIG_PHYS_64BIT #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE4 @@ -577,7 +576,7 @@ unsigned long get_board_ddr_clk(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=t4240qds/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=t4240qds/t4240qds.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 9ba69a1..15b8219 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -11,7 +11,6 @@ #define __CONFIG_H #define CONFIG_T4240RDB -#define CONFIG_PHYS_64BIT #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_FSL_SATA_V2 @@ -770,7 +769,7 @@ unsigned long get_board_ddr_clk(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=t4240rdb/t4240rdb.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h index 8f17dd1..ab2477c 100644 --- a/include/configs/a3m071.h +++ b/include/configs/a3m071.h @@ -334,6 +334,7 @@ #define CONFIG_SYS_OS_BASE 0xfc200000 #define CONFIG_SYS_FDT_BASE 0xfc1e0000 +#define CONFIG_SYS_FDT_SIZE (16<<10) #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 361704b..0467953 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -98,7 +98,6 @@ #if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD) #define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 -#define CONFIG_USB_HOST #define CONFIG_USB_XHCI_OMAP #define CONFIG_USB_STORAGE #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 2db199d..46e8d4c 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -63,7 +63,6 @@ #define CONFIG_SUPPORT_EMMC_BOOT /* USB xHCI HOST */ -#define CONFIG_USB_HOST #define CONFIG_USB_XHCI_OMAP #define CONFIG_USB_STORAGE #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 @@ -86,4 +85,40 @@ #define CONFIG_EEPROM_CHIP_ADDRESS 0x50 #define CONFIG_EEPROM_BUS_ADDRESS 0 +/* + * Default to using SPI for environment, etc. + * 0x000000 - 0x040000 : QSPI.SPL (256KiB) + * 0x040000 - 0x140000 : QSPI.u-boot (1MiB) + * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB) + * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB) + * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB) + * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) + * 0x9E0000 - 0x2000000 : USERLAND + */ +#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 +#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 +#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH +#undef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_MAX_SIZE (256 << 10) /* 256 KiB */ +#endif + +/* SPI SPL */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_DMA_SUPPORT +#define CONFIG_TI_EDMA3 +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 + +/* SPI */ +#undef CONFIG_OMAP3_SPI +#define CONFIG_TI_SPI_MMAP +#define CONFIG_SF_DEFAULT_SPEED 76800000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_QSPI_QUAD_SUPPORT + #endif /* __CONFIG_AM57XX_EVM_H */ diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index d87d40c..640227b 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -17,7 +17,6 @@ #define CONFIG_MACH_TYPE 4501 #define CONFIG_MMCROOT "/dev/mmcblk0p1" -#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M) diff --git a/include/configs/arndale.h b/include/configs/arndale.h index b08f341..18e59fc 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -45,6 +45,7 @@ #define CONFIG_S5P_PA_SYSRAM 0x02020000 #define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM +#define CONFIG_ARMV7_PSCI_NR_CPUS 4 /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ #define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000 diff --git a/include/configs/axs101.h b/include/configs/axs10x.h index c0b68e2..b99248e 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs10x.h @@ -1,12 +1,13 @@ /* - * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * Copyright (C) 2013-2016 Synopsys, Inc. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _CONFIG_AXS101_H_ -#define _CONFIG_AXS101_H_ +#ifndef _CONFIG_AXS10X_H_ +#define _CONFIG_AXS10X_H_ +#include <linux/sizes.h> /* * CPU configuration */ @@ -24,13 +25,13 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 /* 512 Mb */ +#define CONFIG_SYS_SDRAM_SIZE SZ_512M #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */ -#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ +#define CONFIG_SYS_MALLOC_LEN SZ_2M +#define CONFIG_SYS_BOOTM_LEN SZ_32M #define CONFIG_SYS_LOAD_ADDR 0x82000000 /* @@ -113,7 +114,7 @@ * Environment settings */ #define CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */ +#define CONFIG_ENV_SIZE SZ_512 #define CONFIG_ENV_OFFSET 0 /* @@ -127,7 +128,7 @@ * Console configuration */ #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_CBSIZE SZ_256 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) @@ -137,4 +138,4 @@ */ #define CONFIG_BOUNCE_BUFFER -#endif /* _CONFIG_AXS101_H_ */ +#endif /* _CONFIG_AXS10X_H_ */ diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h index 8d041ed..770dd87 100644 --- a/include/configs/bcm23550_w1d.h +++ b/include/configs/bcm23550_w1d.h @@ -127,17 +127,9 @@ /* Commands */ #define CONFIG_FAT_WRITE -/* Fastboot and USB OTG */ -#define CONFIG_USB_FUNCTION_FASTBOOT -#define CONFIG_CMD_FASTBOOT -#define CONFIG_FASTBOOT_FLASH -#define CONFIG_FASTBOOT_FLASH_MMC_DEV 0 #define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_FASTBOOT_BUF_SIZE 0x1d000000 -#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_SDRAM_BASE #undef CONFIG_USB_GADGET_VBUS_DRAW #define CONFIG_USB_GADGET_VBUS_DRAW 0 -#define CONFIG_USB_GADGET_BCM_UDC_OTG_PHY #define CONFIG_USBID_ADDR 0x34052c46 #define CONFIG_SYS_ICACHE_OFF diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h index 889e5db..df0b2ba 100644 --- a/include/configs/bcm28155_ap.h +++ b/include/configs/bcm28155_ap.h @@ -126,15 +126,7 @@ /* Commands */ #define CONFIG_FAT_WRITE -/* Fastboot and USB OTG */ -#define CONFIG_USB_FUNCTION_FASTBOOT -#define CONFIG_CMD_FASTBOOT -#define CONFIG_FASTBOOT_FLASH -#define CONFIG_FASTBOOT_FLASH_MMC_DEV 0 #define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_FASTBOOT_BUF_SIZE (CONFIG_SYS_SDRAM_SIZE - SZ_1M) -#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_USB_GADGET_BCM_UDC_OTG_PHY #define CONFIG_USBID_ADDR 0x34052c46 #endif /* __BCM28155_AP_H */ diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h index d5888e8..50cd743 100644 --- a/include/configs/bcm_ep_board.h +++ b/include/configs/bcm_ep_board.h @@ -93,5 +93,6 @@ /* Misc utility code */ #define CONFIG_BOUNCE_BUFFER #define CONFIG_CRC32_VERIFY +#define CONFIG_ARMV7_PSCI_NR_CPUS 4 #endif /* __BCM_EP_BOARD_H */ diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index dd03936..127a28a 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -251,7 +251,6 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 1f20ec3..c839b03 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -18,6 +18,7 @@ #define CONFIG_MACH_TYPE 4273 /* CMD */ +#define CONFIG_CMD_MTDPARTS /* MMC */ #define CONFIG_SYS_FSL_USDHC_NUM 3 @@ -53,6 +54,20 @@ #define CONFIG_SF_DEFAULT_SPEED 25000000 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +/* MTD support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_FDT_FIXUP_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_SPI_FLASH_MTD +#endif + +#define MTDIDS_DEFAULT "nor0=spi0.0" +#define MTDPARTS_DEFAULT "mtdparts=spi0.0:" \ + "768k(uboot)," \ + "256k(uboot-environment)," \ + "-(reserved)" + /* Environment */ #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED @@ -69,6 +84,8 @@ "stderr=serial,vga\0" \ "panel=HDMI\0" \ "autoload=no\0" \ + "uImage=uImage-cm-fx6\0" \ + "zImage=zImage-cm-fx6\0" \ "kernel=uImage-cm-fx6\0" \ "script=boot.scr\0" \ "dtb=cm-fx6.dtb\0" \ @@ -81,10 +98,12 @@ "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \ "doboot=bootm ${loadaddr}\0" \ "doloadfdt=false\0" \ - "setboottypez=setenv kernel zImage-cm-fx6;" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "setboottypez=setenv kernel ${zImage};" \ "setenv doboot bootz ${loadaddr} - ${fdtaddr};" \ "setenv doloadfdt true;\0" \ - "setboottypem=setenv kernel uImage-cm-fx6;" \ + "setboottypem=setenv kernel ${uImage};" \ "setenv doboot bootm ${loadaddr};" \ "setenv doloadfdt false;\0"\ "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ @@ -92,13 +111,13 @@ "nandroot=/dev/mtdblock4 rw\0" \ "nandrootfstype=ubifs\0" \ "mmcargs=setenv bootargs console=${console} root=${mmcroot} " \ - "${video}\0" \ + "${video} ${extrabootargs}\0" \ "sataargs=setenv bootargs console=${console} root=${sataroot} " \ - "${video}\0" \ + "${video} ${extrabootargs}\0" \ "nandargs=setenv bootargs console=${console} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype} " \ - "${video}\0" \ + "${video} ${extrabootargs}\0" \ "nandboot=if run nandloadkernel; then " \ "run nandloadfdt;" \ "run setboottypem;" \ @@ -155,7 +174,7 @@ "run setupnandboot;" \ "run nandboot;" -#define CONFIG_PREBOOT "usb start" +#define CONFIG_PREBOOT "usb start;sf probe" /* SPI */ #define CONFIG_SPI diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 9bb975a..5d94f13 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -60,7 +60,6 @@ #define CONFIG_SYS_RX_ETH_BUFFER 64 /* USB support */ -#define CONFIG_USB_HOST #define CONFIG_USB_XHCI_OMAP #define CONFIG_USB_STORAGE #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h index 68851ee..8e9444e 100644 --- a/include/configs/cm_t54.h +++ b/include/configs/cm_t54.h @@ -69,7 +69,6 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) /* USB UHH support options */ -#define CONFIG_USB_HOST #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP #define CONFIG_USB_STORAGE diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h new file mode 100644 index 0000000..9da219c --- /dev/null +++ b/include/configs/colibri_imx7.h @@ -0,0 +1,247 @@ +/* + * Copyright 2016 Toradex AG + * + * Configuration settings for the Colibri iMX7 module. + * + * based on mx7dsabresd.h: + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __COLIBRI_IMX7_CONFIG_H +#define __COLIBRI_IMX7_CONFIG_H + +#include "mx7_common.h" + +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_USE_ARCH_MEMCPY +#define CONFIG_USE_ARCH_MEMSET + +/*#define CONFIG_DBG_MONITOR*/ +#define PHYS_SDRAM_SIZE SZ_512M + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_DISPLAY_BOARDINFO_LATE + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +/* Uncomment to enable secure boot support */ +/* #define CONFIG_SECURE_BOOT */ +#define CONFIG_CSF_SIZE 0x4000 + +#define CONFIG_CMD_BMODE + +/* Network */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_TFTP_TSIZE +#define CONFIG_IP_DEFRAG +#define CONFIG_TFTP_BLOCKSIZE 16384 + +/* ENET1 */ +#define IMX_FEC_BASE ENET_IPS_BASE_ADDR + +/* MMC Config*/ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +#undef CONFIG_BOOTM_PLAN9 +#undef CONFIG_BOOTM_RTEMS + +/* I2C configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.10.1 + +#define MEM_LAYOUT_ENV_SETTINGS \ + "fdt_addr_r=0x82000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_addr_r=0x81000000\0" \ + "ramdisk_addr_r=0x82100000\0" + +#define SD_BOOTCMD \ + "sdargs=root=/dev/mmcblk0p2 rw rootwait\0" \ + "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} " \ + "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \ + "run m4boot && " \ + "load mmc 0:1 ${kernel_addr_r} ${kernel_file} && " \ + "load mmc 0:1 ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +#define NFS_BOOTCMD \ + "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ + "nfsboot=run setup; " \ + "setenv bootargs ${defargs} ${nfsargs} " \ + "${setupargs} ${vidargs}; echo Booting from NFS...;" \ + "dhcp ${kernel_addr_r} && " \ + "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +#define UBI_BOOTCMD \ + "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ + "ubi.fm_autoconvert=1\0" \ + "ubiboot=run setup; " \ + "setenv bootargs ${defargs} ${ubiargs} " \ + "${setupargs} ${vidargs}; echo Booting from NAND...; " \ + "ubi part ubi && run m4boot && " \ + "ubi read ${kernel_addr_r} kernel && " \ + "ubi read ${fdt_addr_r} dtb && " \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + NFS_BOOTCMD \ + SD_BOOTCMD \ + UBI_BOOTCMD \ + "console=ttymxc0\0" \ + "defargs=\0" \ + "fdt_board=eval-v3\0" \ + "fdt_fixup=;\0" \ + "m4boot=;\0" \ + "ip_dyn=yes\0" \ + "kernel_file=zImage\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ + "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ + "${board}/flash_eth.img && source ${loadaddr}\0" \ + "setsdupdate=mmc rescan && setenv interface mmc && " \ + "fatload ${interface} 0:1 ${loadaddr} " \ + "${board}/flash_blk.img && source ${loadaddr}\0" \ + "setup=setenv setupargs " \ + "console=tty1 console=${console}" \ + ",${baudrate}n8 ${memargs} consoleblank=0 ${mtdparts}\0" \ + "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ + "setusbupdate=usb start && setenv interface usb && " \ + "fatload ${interface} 0:1 ${loadaddr} " \ + "${board}/flash_blk.img && source ${loadaddr}\0" \ + "splashpos=m,m\0" \ + "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \ + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x0c000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_NAND + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ +#define CONFIG_ENV_OFFSET (8 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_NAND) +#define CONFIG_ENV_OFFSET (4 * 1024 * 1024) +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +#define CONFIG_NAND_MXS +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES +#define CONFIG_CMD_NAND_TORTURE + +/* UBI stuff */ +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_UBI +#define CONFIG_MTD_UBI_FASTMAP +#define CONFIG_CMD_UBIFS /* increases size by almost 60 KB */ + +/* Dynamic MTD partition support */ +#define CONFIG_CMD_MTDPARTS /* Enable 'mtdparts' command line support */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define MTDIDS_DEFAULT "nand0=gpmi-nand" +#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:" \ + "512k(mx7-bcb)," \ + "3584k(u-boot)ro," \ + "512k(u-boot-env)," \ + "-(ubi)" + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 + +/* USB Configs */ +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#define CONFIG_IMX_THERMAL + +#define CONFIG_USBD_HS + +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +/* USB Device Firmware Update support */ +#define CONFIG_USB_FUNCTION_DFU +#define CONFIG_DFU_MMC +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +#define CONFIG_VIDEO +#ifdef CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif + +#endif diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h index 4c37d5e..652e073 100644 --- a/include/configs/conga-qeval20-qa3-e3845.h +++ b/include/configs/conga-qeval20-qa3-e3845.h @@ -15,6 +15,7 @@ #define CONFIG_SYS_MONITOR_LEN (1 << 20) #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT #define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_ARCH_MISC_INIT @@ -41,23 +42,24 @@ #define CONFIG_CMD_BMP #define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0x007fe000 +#define CONFIG_ENV_OFFSET 0x006ef000 #undef CONFIG_BOOTARGS #undef CONFIG_BOOTCOMMAND #define CONFIG_BOOTARGS \ - "root=/dev/sda1 ro quiet" + "root=/dev/sda2 ro quiet" #define CONFIG_BOOTCOMMAND \ - "load scsi 0:1 03000000 /boot/vmlinuz-4.2.0-26-generic;" \ - "load scsi 0:1 04000000 /boot/initrd.img-4.2.0-26-generic;" \ + "load scsi 0:2 03000000 /boot/vmlinuz-${kernel-ver}-generic;" \ + "load scsi 0:2 04000000 /boot/initrd.img-${kernel-ver}-generic;" \ "run boot" #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel-ver=4.4.0-22\0" \ "boot=zboot 03000000 0 04000000 ${filesize}\0" \ "upd_uboot=tftp 100000 conga/u-boot.rom;" \ - "sf probe;sf update 100000 0 7fe000\0" + "sf probe;sf update 100000 0 800000;saveenv\0" #define CONFIG_PREBOOT diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 30c2831..1a63d03 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -26,10 +26,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifdef CONFIG_36BIT -#define CONFIG_PHYS_64BIT -#endif - #ifdef CONFIG_SDCARD #define CONFIG_RAMBOOT_SDCARD #endif @@ -447,7 +443,7 @@ "consoledev=ttyS1\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=controlcenterd.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 4a770b0..0c99e9f 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -708,7 +708,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=p4080ds/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=p4080ds/p4080ds.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/corvus.h b/include/configs/corvus.h index e6a811a..28ea15b 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -95,6 +95,7 @@ /* Ethernet */ #define CONFIG_MACB +#define CONFIG_PHYLIB #define CONFIG_RMII #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_AT91_WANTS_COMMON_PHY diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 708d5f7..8e0ed06 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -11,8 +11,6 @@ #define CONFIG_CYRUS -#define CONFIG_PHYS_64BIT - #if !defined(CONFIG_PPC_P5020) && !defined(CONFIG_PPC_P5040) #error Must call Cyrus CONFIG with a specific CPU enabled. #endif @@ -520,7 +518,7 @@ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "bdev=sda3\0" #define CONFIG_HDBOOT \ diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h new file mode 100644 index 0000000..23d8a0a --- /dev/null +++ b/include/configs/dfi-bt700.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_BOARD_EARLY_INIT_F + +#ifndef CONFIG_INTERNAL_UART +/* Use BayTrail internal HS UART which is memory-mapped */ +#undef CONFIG_SYS_NS16550_PORT_MAPPED +#endif + +#define CONFIG_PCI_PNP + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT} + +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SDMA + +#undef CONFIG_USB_MAX_CONTROLLER_COUNT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_RTL8152 + +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO +#define CONFIG_CMD_BMP + +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x006ef000 + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_BOOTARGS \ + "root=/dev/sda1 ro quiet" +#define CONFIG_BOOTCOMMAND \ + "load scsi 0:1 03000000 /boot/vmlinuz-${kernel-ver}-generic;" \ + "load scsi 0:1 04000000 /boot/initrd.img-${kernel-ver}-generic;" \ + "run boot" + +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel-ver=4.4.0-24\0" \ + "boot=zboot 03000000 0 04000000 ${filesize}\0" \ + "upd_uboot=usb reset;tftp 100000 dfi/u-boot.rom;" \ + "sf probe;sf update 100000 0 800000;saveenv\0" + +#define CONFIG_PREBOOT + +#endif /* __CONFIG_H */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 0d51aeb..b66949f 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -20,7 +20,6 @@ #endif #define CONFIG_VERY_BIG_RAM -#define CONFIG_PHYS_64BIT #define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_MAX_MEM_MAPPED 0x80000000 @@ -157,7 +156,7 @@ /* SPI */ #undef CONFIG_OMAP3_SPI #define CONFIG_TI_SPI_MMAP -#define CONFIG_SF_DEFAULT_SPEED 64000000 +#define CONFIG_SF_DEFAULT_SPEED 76800000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_QSPI_QUAD_SUPPORT @@ -210,7 +209,6 @@ #define CONFIG_SUPPORT_EMMC_BOOT /* USB xHCI HOST */ -#define CONFIG_USB_HOST #define CONFIG_USB_XHCI_OMAP #define CONFIG_USB_STORAGE #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index 4b00922..1dbe219 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -84,8 +84,8 @@ #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) \ - func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> @@ -126,6 +126,8 @@ REFLASH(dragonboard/u-boot.img, 8)\ "fdtfile=apq8016-sbc.dtb\0" \ "fdt_addr_r=0x83000000\0"\ "ramdisk_addr_r=0x84000000\0"\ + "scriptaddr=0x90000000\0"\ + "pxefile_addr_r=0x90100000\0"\ BOOTENV #define CONFIG_ENV_IS_NOWHERE diff --git a/include/configs/duovero.h b/include/configs/duovero.h index 98afe27..299c0d5 100644 --- a/include/configs/duovero.h +++ b/include/configs/duovero.h @@ -29,7 +29,6 @@ #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS /* USB UHH support options */ -#define CONFIG_USB_HOST #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP #define CONFIG_USB_STORAGE diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h new file mode 100644 index 0000000..55ef612 --- /dev/null +++ b/include/configs/el6x_common.h @@ -0,0 +1,139 @@ +/* + * Copyright (C) Stefano Babic <sbabic@denx.de> + * + * Configuration settings for the E+L i.MX6Q DO82 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __EL6Q_COMMON_CONFIG_H +#define __EL6Q_COMMON_CONFIG_H + +#define CONFIG_BOARD_NAME EL6Q + +#include <config_distro_defaults.h> +#include "mx6_common.h" + +#define CONFIG_IMX_THERMAL + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_MXC_UART + +#ifdef CONFIG_SPL +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) +#define CONFIG_SPL_SPI_LOAD +#include "imx6_spl.h" +#endif + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* I2C config */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +/* Commands */ +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 3 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ + +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_BOOTZ +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOARD_NAME EL6Q + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_EXTRA_ENV_SETTINGS \ + "board="__stringify(CONFIG_BOARD_NAME)"\0" \ + "cma_size="__stringify(EL6Q_CMA_SIZE)"\0" \ + "chp_size="__stringify(EL6Q_COHERENT_POOL_SIZE)"\0" \ + "console=" CONFIG_CONSOLE_DEV "\0" \ + "fdtfile=undefined\0" \ + "fdt_high=0xffffffff\0" \ + "fdt_addr_r=0x18000000\0" \ + "fdt_addr=0x18000000\0" \ + "findfdt=setenv fdtfile " CONFIG_DEFAULT_FDT_FILE "\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(PXE, PXE, na) \ + func(DHCP, dhcp, na) + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run distro_bootcmd" + +#include <config_distro_bootcmd.h> + +#define CONFIG_ARP_TIMEOUT 200UL + +#define CONFIG_CMD_MEMTEST + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10800000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 + +#define CONFIG_STACKSIZE (128 * 1024) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_ENV_IS_IN_MMC + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET 0x0 +#endif + +#endif /* __EL6Q_COMMON_CONFIG_H */ diff --git a/include/configs/evb_rk3288.h b/include/configs/evb_rk3288.h new file mode 100644 index 0000000..342557f --- /dev/null +++ b/include/configs/evb_rk3288.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS +#include <configs/rk3288_common.h> + +#define CONFIG_SPL_MMC_SUPPORT + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +/* SPL @ 32k for ~36k + * ENV @ 96k + * u-boot @ 128K + */ +#define CONFIG_ENV_OFFSET (96 * 1024) + +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h new file mode 100644 index 0000000..047850a --- /dev/null +++ b/include/configs/evb_rk3399.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __EVB_RK3399_H +#define __EVB_RK3399_H + +#include <configs/rk3399_common.h> + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +/* + * SPL @ 32k for ~36k + * ENV @ 96k + * u-boot @ 128K + */ +#define CONFIG_ENV_OFFSET (96 * 1024) + +#define SDRAM_BANK_SIZE (2UL << 30) + +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/include/configs/fennec_rk3288.h b/include/configs/fennec_rk3288.h new file mode 100644 index 0000000..342557f --- /dev/null +++ b/include/configs/fennec_rk3288.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS +#include <configs/rk3288_common.h> + +#define CONFIG_SPL_MMC_SUPPORT + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +/* SPL @ 32k for ~36k + * ENV @ 96k + * u-boot @ 128K + */ +#define CONFIG_ENV_OFFSET (96 * 1024) + +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 4de2460..7a54546 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -32,8 +32,6 @@ #define CONFIG_MXC_UART_BASE UART3_BASE #define CONFIG_CONSOLE_DEV "ttymxc2" -#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024) - #define CONFIG_SUPPORT_EMMC_BOOT diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 982ddba..1bd13fe 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -33,6 +33,8 @@ #include "imx6_spl.h" /* common IMX6 SPL configuration */ #include "mx6_common.h" #undef CONFIG_SPL_EXT_SUPPORT +#undef CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DISPLAY_BOARDINFO_LATE #define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */ @@ -269,15 +271,13 @@ /* Environment */ #define CONFIG_IPADDR 192.168.1.1 #define CONFIG_SERVERIP 192.168.1.146 -#define HWCONFIG_DEFAULT \ - "hwconfig=rs232;" \ - "dio0:mode=gpio;dio1:mode=gpio;dio2:mode=gpio;dio3:mode=gpio\0" \ #define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "pcidisable=1\0" \ "usb_pgood_delay=2000\0" \ "console=ttymxc1\0" \ "bootdevs=usb mmc sata flash\0" \ - HWCONFIG_DEFAULT \ + "hwconfig=_UNKNOWN_\0" \ "video=\0" \ \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 953c088..2b172a5 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -61,6 +61,7 @@ #include "tegra-common-post.h" #define CONFIG_ARMV7_PSCI 1 +#define CONFIG_ARMV7_PSCI_NR_CPUS 4 /* Reserve top 1M for secure RAM */ #define CONFIG_ARMV7_SECURE_BASE 0xfff00000 #define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000 diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index f8bba67..71b0037 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -73,4 +73,10 @@ #define CONFIG_SF_DEFAULT_BUS 1 #define CONFIG_SF_DEFAULT_CS 0 +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CADENCE_QSPI +#define CONFIG_CQSPI_REF_CLK 384000000 +#define CONFIG_CQSPI_DECODER 0x0 +#endif + #endif /* __CONFIG_K2G_EVM_H */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 9513c6d..e3fede5 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -29,7 +29,6 @@ /* * Enable this board for more than 2GB of SDRAM */ -#define CONFIG_PHYS_64BIT #define CONFIG_VERY_BIG_RAM /* diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 5bdda22..8166c86 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -8,7 +8,6 @@ #ifndef _CONFIG_KMP204X_H #define _CONFIG_KMP204X_H -#define CONFIG_PHYS_64BIT #define CONFIG_PPC_P2041 #define CONFIG_SYS_TEXT_BASE 0xfff40000 diff --git a/include/configs/kylin_rk3036.h b/include/configs/kylin_rk3036.h index b16c03f..e8ca76d 100644 --- a/include/configs/kylin_rk3036.h +++ b/include/configs/kylin_rk3036.h @@ -26,7 +26,6 @@ /* Enable gpt partition table */ #define CONFIG_CMD_GPT #define CONFIG_RANDOM_UUID -#define CONFIG_EFI_PARTITION #define PARTS_DEFAULT \ "uuid_disk=${uuid_gpt_disk};" \ "name=loader,start=32K,size=4000K,uuid=${uuid_gpt_loader};" \ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index fcf402c..6e31ca0 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -28,11 +28,11 @@ #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_BRDCFG_REG 0x04 #define QIXIS_LBMAP_SWITCH 6 -#define QIXIS_LBMAP_MASK 0xf7 +#define QIXIS_LBMAP_MASK 0x08 #define QIXIS_LBMAP_SHIFT 0 #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x08 -#define QIXIS_RST_CTL_RESET 0x41 +#define QIXIS_RST_CTL_RESET 0x31 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index db684d2..47180f9 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -10,6 +10,10 @@ #define CONFIG_LS102XA #define CONFIG_ARMV7_PSCI +#define CONFIG_ARMV7_PSCI_1_0 +#define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS + +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR #define CONFIG_SYS_FSL_CLK @@ -279,6 +283,8 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_SHIFT 0 #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_PWR_CTL 0x21 +#define QIXIS_PWR_CTL_POWEROFF 0x80 #define QIXIS_RST_CTL_RESET 0x44 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 0fb28ef..2f19950 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -10,6 +10,10 @@ #define CONFIG_LS102XA #define CONFIG_ARMV7_PSCI +#define CONFIG_ARMV7_PSCI_1_0 +#define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS + +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR #define CONFIG_SYS_FSL_CLK @@ -123,7 +127,18 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. + */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \ + (CONFIG_U_BOOT_HDR_SIZE / 512) +#else #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 +#endif /* ifdef CONFIG_SECURE_BOOT */ #define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_MAX_SIZE 0x1a000 @@ -136,7 +151,18 @@ #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#ifdef CONFIG_U_BOOT_HDR_SIZE +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. Here u-boot max. size is 512K. So if binary + * size increases then increase this size in case of secure boot as + * it uses raw u-boot image instead of fit image. + */ +#define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE) +#else #define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ #endif #ifdef CONFIG_QSPI_BOOT diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index b0d4a8d..e55fcb2 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -175,6 +175,8 @@ /* Command line configuration */ #define CONFIG_CMD_ENV +#define CONFIG_MENU +#define CONFIG_CMD_PXE /* MMC */ #define CONFIG_MMC @@ -241,22 +243,37 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ + "5m(kernel),1m(dtb),9m(file_system)" +#else +#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ + "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ + "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ + "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ + "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ + "40m(nor_bank4_fit);7e800000.flash:" \ + "1m(nand_uboot),1m(nand_uboot_env)," \ + "20m(nand_fit);spi0.0:1m(uboot)," \ + "5m(kernel),1m(dtb),9m(file_system)" +#endif + /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ - "kernel_addr=0x100000\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_start=0x61100000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ - "console=ttyAMA0,38400n8\0" + "console=ttyS0,115200\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ - "earlycon=uart8250,mmio,0x21c0500" + "earlycon=uart8250,mmio,0x21c0500 " \ + MTDPARTS_DEFAULT + #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ "e0000 f00000 && bootm $kernel_load" diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 94ddfb1..857ad7b 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -9,6 +9,17 @@ #include "ls1043a_common.h" +#if defined(CONFIG_FSL_LS_PPA) +#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#define SEC_FIRMWARE_ERET_ADDR_REVERT +#define CONFIG_ARMV8_PSCI + +#define CONFIG_SYS_LS_PPA_FW_IN_XIP +#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP +#define CONFIG_SYS_LS_PPA_FW_ADDR 0x60500000 +#endif +#endif + #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 93fb166..e5bf700 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -175,10 +175,6 @@ #define CONFIG_CMD_IRQ #define CONFIG_CMD_MFSL -#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE) -#else -#endif - #if defined(FLASH) # define CONFIG_CMD_JFFS2 # define CONFIG_CMD_UBI @@ -309,6 +305,7 @@ 0x60000) #define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ 0x40000) +#define CONFIG_SYS_FDT_SIZE (16<<10) #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \ 0x1000000) diff --git a/include/configs/miniarm_rk3288.h b/include/configs/miniarm_rk3288.h new file mode 100644 index 0000000..342557f --- /dev/null +++ b/include/configs/miniarm_rk3288.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS +#include <configs/rk3288_common.h> + +#define CONFIG_SPL_MMC_SUPPORT + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +/* SPL @ 32k for ~36k + * ENV @ 96k + * u-boot @ 128K + */ +#define CONFIG_ENV_OFFSET (96 * 1024) + +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index 6039fc4..200e468 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -13,7 +13,6 @@ #define CONFIG_MXC_UART_BASE UART4_BASE #define CONFIG_CONSOLE_DEV "ttymxc3" #define CONFIG_MMCROOT "/dev/mmcblk0p2" -#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024) /* USB Configs */ #define CONFIG_USB_EHCI diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index d53e416..375aa0e 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -137,7 +137,6 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE SZ_1G #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index d771f9d..439579d 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -103,7 +103,6 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE SZ_2G #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 183a759..9281fee 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -132,7 +132,6 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE SZ_1G #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index fbc6de6..7295fa6 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -21,6 +21,7 @@ #define CONFIG_MXC_GPT_HCLK #define CONFIG_SYSCOUNTER_TIMER #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ +#define CONFIG_TIMER_CLK_FREQ CONFIG_SC_TIMER_CLK #define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_BOOTM_LEN 0x1000000 @@ -28,8 +29,9 @@ /* Enable iomux-lpsr support */ #define CONFIG_IOMUX_LPSR +#define CONFIG_ARCH_MISC_INIT + #define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_LOADADDR 0x80800000 #define CONFIG_SYS_TEXT_BASE 0x87800000 @@ -70,15 +72,8 @@ #define CONFIG_CMD_FUSE #define CONFIG_MXC_OCOTP -/* - * Default boot linux kernel in no secure mode. - * If want to boot kernel in secure mode, please define CONFIG_MX7_SEC - */ -#ifndef CONFIG_MX7_SEC -#define CONFIG_ARMV7_NONSEC #define CONFIG_ARMV7_PSCI #define CONFIG_ARMV7_PSCI_NR_CPUS 2 #define CONFIG_ARMV7_SECURE_BASE 0x00900000 -#endif #endif diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index ece8a03..822d81f 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -22,6 +22,8 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT +#define CONFIG_DISPLAY_BOARDINFO + /* Uncomment to enable secure boot support */ /* #define CONFIG_SECURE_BOOT */ #define CONFIG_CSF_SIZE 0x4000 @@ -237,8 +239,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ /* USB Configs */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX7 #define CONFIG_USB_STORAGE #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_HOST_ETHER diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 0882d5d..238b16d 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -120,7 +120,7 @@ #define CONFIG_PL011_CLOCK 24000000 #define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } #define CONFIG_CONS_INDEX 0 -/* Default baudrate can be overriden by board! */ +/* Default baudrate can be overridden by board! */ #ifndef CONFIG_BAUDRATE #define CONFIG_BAUDRATE 115200 #endif diff --git a/include/configs/novena.h b/include/configs/novena.h index 2382951..57d8c3e 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -57,7 +57,6 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE 0xF0000000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR diff --git a/include/configs/arcangel4.h b/include/configs/nsim.h index d608104..1edc560 100644 --- a/include/configs/arcangel4.h +++ b/include/configs/nsim.h @@ -1,11 +1,13 @@ /* - * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * Copyright (C) 2013-2016 Synopsys, Inc. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _CONFIG_ARCANGEL4_H_ -#define _CONFIG_ARCANGEL4_H_ +#ifndef _CONFIG_NSIM_H_ +#define _CONFIG_NSIM_H_ + +#include <linux/sizes.h> /* * CPU configuration @@ -19,13 +21,13 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */ +#define CONFIG_SYS_SDRAM_SIZE SZ_256M #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */ -#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ +#define CONFIG_SYS_MALLOC_LEN SZ_2M +#define CONFIG_SYS_BOOTM_LEN SZ_32M #define CONFIG_SYS_LOAD_ADDR 0x82000000 #define CONFIG_SYS_NO_FLASH @@ -48,7 +50,7 @@ * Environment settings */ #define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */ +#define CONFIG_ENV_SIZE SZ_512 #define CONFIG_ENV_OFFSET 0 /* @@ -62,9 +64,9 @@ * Console configuration */ #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_CBSIZE SZ_256 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -#endif /* _CONFIG_ARCANGEL4_H_ */ +#endif /* _CONFIG_NSIM_H_ */ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 1726a3e..52a24d3 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -96,11 +96,279 @@ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +/* + * High level configuration options + */ +#define CONFIG_OMAP /* This is TI OMAP core */ +#define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 + +#define CONFIG_SDRC /* The chip has SDRC controller */ + +#define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */ +#define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */ + +/* + * Clock related definitions + */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +/* Size of environment - 128KB */ +#define CONFIG_ENV_SIZE (128 << 10) + +/* Size of malloc pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) + +/* + * Physical Memory Map + * Note 1: CS1 may or may not be populated + * Note 2: SDRAM size is expected to be at least 32MB + */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* Limits for memtest */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +/* Default load address */ +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) + /* ----------------------------------------------------------------------------- - * Include common board configuration + * Hardware drivers * ----------------------------------------------------------------------------- */ -#include "omap3_evm_common.h" + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ +#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX + +/* + * PISMO support + */ +/* Monitor at start of flash - Reserve 2 sectors */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) + +/* Start location & size of environment */ +#define ONENAND_ENV_OFFSET 0x260000 +#define SMNAND_ENV_OFFSET 0x260000 + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ + +/* + * NAND + */ +/* Physical address to access NAND */ +#define CONFIG_SYS_NAND_ADDR NAND_BASE + +/* Physical address to access NAND at CS0 */ +#define CONFIG_SYS_NAND_BASE NAND_BASE + +/* Max number of NAND devices */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT +/* Timeout values (in ticks) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) + +#define CONFIG_SYS_JFFS2_MEM_NAND +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* Start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +/* Size of jffs2 partition */ +#define CONFIG_JFFS2_PART_SIZE 0xf980000 + +/* + * USB + */ +#ifdef CONFIG_USB_OMAP3 + +#ifdef CONFIG_USB_MUSB_HCD + +#define CONFIG_USB_STORAGE +#define CONGIG_CMD_STORAGE + +#ifdef CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL +#define CONFIG_PREBOOT "usb start" +#endif /* CONFIG_USB_KEYBOARD */ + +#endif /* CONFIG_USB_MUSB_HCD */ + +#ifdef CONFIG_USB_MUSB_UDC +/* USB device configuration */ +#define CONFIG_USB_DEVICE +#define CONFIG_USB_TTY +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* Change these to suit your needs */ +#define CONFIG_USBD_VENDORID 0x0451 +#define CONFIG_USBD_PRODUCTID 0x5678 +#define CONFIG_USBD_MANUFACTURER "Texas Instruments" +#define CONFIG_USBD_PRODUCT_NAME "EVM" +#endif /* CONFIG_USB_MUSB_UDC */ + +#endif /* CONFIG_USB_OMAP3 */ + +/* ---------------------------------------------------------------------------- + * U-Boot features + * ---------------------------------------------------------------------------- + */ +#define CONFIG_SYS_MAXARGS 16 /* max args for a command */ + +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of Console IO buffer */ +#define CONFIG_SYS_CBSIZE 512 + +/* Size of print buffer */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Size of bootarg buffer */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_BOOTFILE "uImage" + +/* + * NAND / OneNAND + */ +#if defined(CONFIG_CMD_NAND) +#define CONFIG_SYS_FLASH_BASE NAND_BASE + +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#elif defined(CONFIG_CMD_ONENAND) +#define CONFIG_SYS_FLASH_BASE ONENAND_MAP +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP +#endif + +#if !defined(CONFIG_ENV_IS_NOWHERE) +#if defined(CONFIG_CMD_NAND) +#define CONFIG_ENV_IS_IN_NAND +#elif defined(CONFIG_CMD_ONENAND) +#define CONFIG_ENV_IS_IN_ONENAND +#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET +#endif +#endif /* CONFIG_ENV_IS_NOWHERE */ + +#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET + +#if defined(CONFIG_CMD_NET) + +/* Ethernet (SMSC9115 from SMSC9118 family) */ +#define CONFIG_SMC911X +#define CONFIG_SMC911X_32_BIT +#define CONFIG_SMC911X_BASE 0x2C000000 + +/* BOOTP fields */ +#define CONFIG_BOOTP_SUBNETMASK 0x00000001 +#define CONFIG_BOOTP_GATEWAY 0x00000002 +#define CONFIG_BOOTP_HOSTNAME 0x00000004 +#define CONFIG_BOOTP_BOOTPATH 0x00000010 + +#endif /* CONFIG_CMD_NET */ + +/* Support for relocation */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* ----------------------------------------------------------------------------- + * Board specific + * ----------------------------------------------------------------------------- + */ +#define CONFIG_SYS_NO_FLASH + +/* Uncomment to define the board revision statically */ +/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */ + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_OMAP3_ID_NAND +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* ----------------------------------------------------------------------------- * Default environment diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h deleted file mode 100644 index 01336ff..0000000 --- a/include/configs/omap3_evm_common.h +++ /dev/null @@ -1,286 +0,0 @@ -/* - * Common configuration settings for the TI OMAP3 EVM board. - * - * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __OMAP3_EVM_COMMON_H -#define __OMAP3_EVM_COMMON_H - -/* - * High level configuration options - */ -#define CONFIG_OMAP /* This is TI OMAP core */ -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 - -#define CONFIG_SDRC /* The chip has SDRC controller */ - -#define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */ -#define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */ - -/* - * Clock related definitions - */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/* Size of environment - 128KB */ -#define CONFIG_ENV_SIZE (128 << 10) - -/* Size of malloc pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - -/* - * Physical Memory Map - * Note 1: CS1 may or may not be populated - * Note 2: SDRAM size is expected to be at least 32MB - */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/* Limits for memtest */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ - -/* Default load address */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) - -/* ----------------------------------------------------------------------------- - * Hardware drivers - * ----------------------------------------------------------------------------- - */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ -#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_OMAP34XX - -/* - * PISMO support - */ -/* Monitor at start of flash - Reserve 2 sectors */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) - -/* Start location & size of environment */ -#define ONENAND_ENV_OFFSET 0x260000 -#define SMNAND_ENV_OFFSET 0x260000 - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ - -/* - * NAND - */ -/* Physical address to access NAND */ -#define CONFIG_SYS_NAND_ADDR NAND_BASE - -/* Physical address to access NAND at CS0 */ -#define CONFIG_SYS_NAND_BASE NAND_BASE - -/* Max number of NAND devices */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BUSWIDTH_16BIT -/* Timeout values (in ticks) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) - -/* Flash banks JFFS2 should use */ -#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ - CONFIG_SYS_MAX_NAND_DEVICE) - -#define CONFIG_SYS_JFFS2_MEM_NAND -#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#define CONFIG_JFFS2_NAND -/* nand device jffs2 lives on */ -#define CONFIG_JFFS2_DEV "nand0" -/* Start of jffs2 partition */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 -/* Size of jffs2 partition */ -#define CONFIG_JFFS2_PART_SIZE 0xf980000 - -/* - * USB - */ -#ifdef CONFIG_USB_OMAP3 - -#ifdef CONFIG_USB_MUSB_HCD - -#define CONFIG_USB_STORAGE -#define CONGIG_CMD_STORAGE - -#ifdef CONFIG_USB_KEYBOARD -#define CONFIG_SYS_USB_EVENT_POLL -#define CONFIG_PREBOOT "usb start" -#endif /* CONFIG_USB_KEYBOARD */ - -#endif /* CONFIG_USB_MUSB_HCD */ - -#ifdef CONFIG_USB_MUSB_UDC -/* USB device configuration */ -#define CONFIG_USB_DEVICE -#define CONFIG_USB_TTY -#define CONFIG_SYS_CONSOLE_IS_IN_ENV - -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "EVM" -#endif /* CONFIG_USB_MUSB_UDC */ - -#endif /* CONFIG_USB_OMAP3 */ - -/* ---------------------------------------------------------------------------- - * U-Boot features - * ---------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MAXARGS 16 /* max args for a command */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Size of Console IO buffer */ -#define CONFIG_SYS_CBSIZE 512 - -/* Size of print buffer */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Size of bootarg buffer */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -#define CONFIG_BOOTFILE "uImage" - -/* - * NAND / OneNAND - */ -#if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE - -#define CONFIG_NAND_OMAP_GPMC -#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET -#elif defined(CONFIG_CMD_ONENAND) -#define CONFIG_SYS_FLASH_BASE ONENAND_MAP -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP -#endif - -#if !defined(CONFIG_ENV_IS_NOWHERE) -#if defined(CONFIG_CMD_NAND) -#define CONFIG_ENV_IS_IN_NAND -#elif defined(CONFIG_CMD_ONENAND) -#define CONFIG_ENV_IS_IN_ONENAND -#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET -#endif -#endif /* CONFIG_ENV_IS_NOWHERE */ - -#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET - -#if defined(CONFIG_CMD_NET) - -/* Ethernet (SMSC9115 from SMSC9118 family) */ -#define CONFIG_SMC911X -#define CONFIG_SMC911X_32_BIT -#define CONFIG_SMC911X_BASE 0x2C000000 - -/* BOOTP fields */ -#define CONFIG_BOOTP_SUBNETMASK 0x00000001 -#define CONFIG_BOOTP_GATEWAY 0x00000002 -#define CONFIG_BOOTP_HOSTNAME 0x00000004 -#define CONFIG_BOOTP_BOOTPATH 0x00000010 - -#endif /* CONFIG_CMD_NET */ - -/* Support for relocation */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* ----------------------------------------------------------------------------- - * Board specific - * ----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_NO_FLASH - -/* Uncomment to define the board revision statically */ -/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */ - -#define CONFIG_SYS_CACHELINE_SIZE 64 - -/* Defines for SPL */ -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_TEXT_BASE 0x40200800 -#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ - -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_POWER_SUPPORT -#define CONFIG_SPL_OMAP3_ID_NAND -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" - -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. - */ -#define CONFIG_SYS_TEXT_BASE 0x80100000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - -#endif /* __OMAP3_EVM_COMMON_H */ diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h deleted file mode 100644 index b7d8765..0000000 --- a/include/configs/omap3_evm_quick_mmc.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Configuration settings for quick boot from MMC on OMAP3 EVM. - * - * Copyright (C) 2006-2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * Author : - * Sanjeev Premi <premi@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __OMAP3_EVM_QUICK_MMC_H -#define __OMAP3_EVM_QUICK_MMC_H - -#include <asm/arch/cpu.h> -#include <asm/arch/omap.h> - -/* ---------------------------------------------------------------------------- - * Supported U-Boot commands - * ---------------------------------------------------------------------------- - */ - -/* - * Board revision is detected by probing the Ethernet chip. - * - * When revision is statically configured via CONFIG_STATIC_BOARD_REV, - * this option can be removed. Generated binary is leaner by ~16Kbytes. - */ - -/* ---------------------------------------------------------------------------- - * Supported U-Boot features - * ---------------------------------------------------------------------------- - */ -#define CONFIG_SILENT_CONSOLE -#define CONFIG_ENV_IS_NOWHERE - -/* ---------------------------------------------------------------------------- - * Supported hardware - * ---------------------------------------------------------------------------- - */ - -/* MMC */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_OMAP_HSMMC -#define CONFIG_DOS_PARTITION - -/* ----------------------------------------------------------------------------- - * Include common board configuration - * ----------------------------------------------------------------------------- - */ -#include "omap3_evm_common.h" - -/* ----------------------------------------------------------------------------- - * Default environment - * ----------------------------------------------------------------------------- - */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=no\0" \ - "silent=1" - -#define CONFIG_BOOTCOMMAND \ - "mmc rescan 0; " \ - "fatload mmc 0 0x82000000 uImage; " \ - "bootm 0x82000000;" - -/* - * Update the bootargs as necessary e.g. size of memory, partition and fstype - */ -#define CONFIG_BOOTARGS \ - "quiet " \ - "console=ttyO0,115200n8 " \ - "mem=128M " \ - "noinitrd " \ - "root=/dev/mmcblk0p2 rw " \ - "rootfstype=ext3 rootwait" - -/* - * SPL - */ -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#endif /* __OMAP3_EVM_QUICK_MMC_H */ diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h deleted file mode 100644 index da5d325..0000000 --- a/include/configs/omap3_evm_quick_nand.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Configuration settings for quick boot from NAND on OMAP3 EVM. - * - * Copyright (C) 2006-2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * Author : - * Sanjeev Premi <premi@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __OMAP3_EVM_QUICK_NAND_H -#define __OMAP3_EVM_QUICK_NAND_H - -#include <asm/arch/cpu.h> -#include <asm/arch/omap.h> - -/* ---------------------------------------------------------------------------- - * Supported U-Boot commands - * ---------------------------------------------------------------------------- - */ -#define CONFIG_CMD_NAND - -/* - * Board revision is detected by probing the Ethernet chip. - * - * When revision is statically configured via CONFIG_STATIC_BOARD_REV, - * this option can be removed. Generated binary is leaner by ~16Kbytes. - */ - -/* ---------------------------------------------------------------------------- - * Supported U-Boot features - * ---------------------------------------------------------------------------- - */ -#define CONFIG_SILENT_CONSOLE -#define CONFIG_ENV_IS_NOWHERE - -/* ----------------------------------------------------------------------------- - * Include common board configuration - * ----------------------------------------------------------------------------- - */ -#include "omap3_evm_common.h" - -/* ----------------------------------------------------------------------------- - * Default environment - * ----------------------------------------------------------------------------- - */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=no\0" \ - "silent=1" - -#define CONFIG_BOOTCOMMAND \ - "nandecc hw; " \ - "nand read.i 0x80000000 280000 300000; " \ - "bootm 0x80000000;" - -/* - * Update the bootargs as necessary e.g. size of memory, partition and fstype - */ -#define CONFIG_BOOTARGS \ - "quiet " \ - "console=ttyO0,115200n8 " \ - "mem=128M " \ - "noinitrd " \ - "root=/dev/mtdblock4 rw " \ - "rootfstype=jffs2 " - -/* - * SPL - */ -#define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 - -#endif /* __OMAP3_EVM_QUICK_NAND_H */ diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 9bd8915..e0d2593 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -10,11 +10,8 @@ #ifndef __IGEP00X0_H #define __IGEP00X0_H -#ifdef CONFIG_BOOT_NAND -#define CONFIG_NAND -#endif - #define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_NAND #include <configs/ti_omap3_common.h> #include <asm/mach-types.h> @@ -76,9 +73,9 @@ #define CONFIG_USBD_MANUFACTURER "Texas Instruments" #define CONFIG_USBD_PRODUCT_NAME "IGEP" -#ifdef CONFIG_BOOT_ONENAND -#define CONFIG_CMD_ONENAND /* ONENAND support */ -#endif +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_ONENAND +#define CONFIG_CMD_UBI #ifndef CONFIG_SPL_BUILD @@ -106,27 +103,6 @@ #endif /* - * FLASH and environment organization - */ - -#ifdef CONFIG_BOOT_ONENAND -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ - -#define CONFIG_ENV_IS_IN_ONENAND 1 -#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ -#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET -#endif - -#ifdef CONFIG_NAND -#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ -#define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ -#define CONFIG_ENV_ADDR NAND_ENV_OFFSET -#endif - -/* * SMSC911x Ethernet */ #if defined(CONFIG_CMD_NET) @@ -135,19 +111,19 @@ #define CONFIG_SMC911X_BASE 0x2C000000 #endif /* (CONFIG_CMD_NET) */ -/* OneNAND boot config */ -#ifdef CONFIG_BOOT_ONENAND -#define CONFIG_SPL_ONENAND_SUPPORT -#define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x80000 -#define CONFIG_SYS_ONENAND_PAGE_SIZE 2048 -#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x80000 -#define CONFIG_SPL_ONENAND_LOAD_SIZE \ - (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR) +#define CONFIG_RBTREE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_SYS_MTDPARTS_RUNTIME -#endif +/* OneNAND config */ +#define CONFIG_SPL_ONENAND_SUPPORT +#define CONFIG_USE_ONENAND_BOARD_INIT +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP +#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) -/* NAND boot config */ -#ifdef CONFIG_NAND +/* NAND config */ +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_OMAP3_ID_NAND #define CONFIG_SYS_NAND_BUSWIDTH_16BIT #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 @@ -168,13 +144,29 @@ #define CONFIG_NAND_OMAP_GPMC #define CONFIG_BCH -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_CMD_SPL_NAND_OFS 0x240000 -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 -#endif -#endif +/* UBI configuration */ +#define CONFIG_SPL_UBI 1 +#define CONFIG_SPL_UBI_MAX_VOL_LEBS 256 +#define CONFIG_SPL_UBI_MAX_PEB_SIZE (256*1024) +#define CONFIG_SPL_UBI_MAX_PEBS 4096 +#define CONFIG_SPL_UBI_VOL_IDS 8 +#define CONFIG_SPL_UBI_LOAD_MONITOR_ID 0 +#define CONFIG_SPL_UBI_LOAD_KERNEL_ID 3 +#define CONFIG_SPL_UBI_LOAD_ARGS_ID 4 +#define CONFIG_SPL_UBI_PEB_OFFSET 4 +#define CONFIG_SPL_UBI_VID_OFFSET 512 +#define CONFIG_SPL_UBI_LEB_START 2048 +#define CONFIG_SPL_UBI_INFO_ADDR 0x88080000 + +/* environment organization */ +#define CONFIG_ENV_IS_IN_UBI 1 +#define CONFIG_ENV_UBI_PART "UBI" +#define CONFIG_ENV_UBI_VOLUME "config" +#define CONFIG_ENV_UBI_VOLUME_REDUND "config_r" +#define CONFIG_UBI_SILENCE_MSG 1 +#define CONFIG_UBIFS_SILENCE_MSG 1 +#define CONFIG_ENV_SIZE (32*1024) + +#undef CONFIG_SPL_EXT_SUPPORT #endif /* __IGEP00X0_H */ diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index 0d62ccd..ffa22c3 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -17,7 +17,6 @@ */ /* USB UHH support options */ -#define CONFIG_USB_HOST #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP #define CONFIG_USB_STORAGE diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 4ddc492..2bf955a 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -88,7 +88,6 @@ #define CONFIG_SYS_I2C_TCA642X_ADDR 0x22 /* USB UHH support options */ -#define CONFIG_USB_HOST #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP #define CONFIG_USB_STORAGE diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 1f36d36..d00cf50 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -203,7 +203,7 @@ #define CONFIG_REVISION_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTARGS "console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootwait ip=off" -#define CONFIG_BOOTCOMMAND "if mmc rescan 0; then if fatload mmc 0 0xc0600000 boot.scr; then source 0xc0600000; else fatload mmc 0 0xc0700000 uImage; bootm c0700000; fi; else sf probe 0; sf read 0xc0700000 0x80000 0x220000; bootm 0xc0700000; fi" +#define CONFIG_BOOTCOMMAND "if mmc rescan; then if fatload mmc 0 0xc0600000 boot.scr; then source 0xc0600000; else fatload mmc 0 0xc0700000 uImage; bootm c0700000; fi; else sf probe 0; sf read 0xc0700000 0x80000 0x220000; bootm 0xc0700000; fi" /* * U-Boot commands diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h index 913256a..227c0ca 100644 --- a/include/configs/openrisc-generic.h +++ b/include/configs/openrisc-generic.h @@ -44,7 +44,6 @@ /* * Ethernet */ -#define CONFIG_ETHOC #define CONFIG_SYS_ETHOC_BASE 0x92000000 #define CONFIG_BOOTFILE "boot.img" diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 4f22d12..5d0a570 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -12,10 +12,6 @@ #define CONFIG_DISPLAY_BOARDINFO -#ifdef CONFIG_36BIT -#define CONFIG_PHYS_64BIT -#endif - #if defined(CONFIG_P1020MBG) #define CONFIG_BOARDNAME "P1020MBG-PC" #define CONFIG_P1020 @@ -989,7 +985,7 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "bdev=sda1\0" \ "jffs2nor=mtdblock3\0" \ "norbootaddr=ef080000\0" \ diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index 30bfbf4..79e4991 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -513,7 +513,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "bdev=sda1\0" \ "norbootaddr=ef080000\0" \ "norfdtaddr=ef040000\0" \ diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h index 257283f..1f64405 100644 --- a/include/configs/p2771-0000.h +++ b/include/configs/p2771-0000.h @@ -14,6 +14,9 @@ /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000" +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA + /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC @@ -25,6 +28,11 @@ #define CONFIG_SYS_MMC_ENV_PART 2 #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +/* PCI host support */ +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_CMD_PCI + #include "tegra-common-post.h" /* Crystal is 38.4MHz. clk_m runs at half that rate */ diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h new file mode 100644 index 0000000..97cbeba --- /dev/null +++ b/include/configs/pcm058.h @@ -0,0 +1,140 @@ +/* + * Copyright (C) Stefano Babic <sbabic@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#ifndef __PCM058_CONFIG_H +#define __PCM058_CONFIG_H + +#include <config_distro_defaults.h> + +#ifdef CONFIG_SPL +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_DMA_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) +#include "imx6_spl.h" +#endif + +#include "mx6_common.h" + +/* Thermal */ +#define CONFIG_IMX_THERMAL + +/* Serial */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CONSOLE_DEV "ttymxc1" + +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +/* Early setup */ +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_DISPLAY_BOARDINFO_LATE + + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) + +/* Ethernet */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 3 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_KSZ9031 + +/* SPI Flash */ +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_NAND +/* Enable NAND support */ +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 + +/* Filesystem support */ +#define CONFIG_LZO +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:16m(uboot),1m(env),-(rootfs)" + +/* Various command support */ +#define CONFIG_CMD_BMODE /* set eFUSE shadow for a boot dev and reset */ +#define CONFIG_CMD_HDMIDETECT /* detect HDMI output device */ +#define CONFIG_CMD_GSC +#define CONFIG_CMD_EECONFIG /* Gateworks EEPROM config cmd */ +#define CONFIG_CMD_UBI +#define CONFIG_RBTREE + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +/* Environment organization */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_ENV_OFFSET (1024 * SZ_1K) +#define CONFIG_ENV_SECT_SIZE (64 * SZ_1K) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (0x1E0000) +#define CONFIG_ENV_SECT_SIZE (128 * SZ_1K) +#endif + +#endif diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index d848ead..ca3c30b 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -17,8 +17,18 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +/* Network support */ + +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL + /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) +#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */ #define CONFIG_BOARD_EARLY_INIT_F @@ -42,24 +52,17 @@ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG1 port enabled */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_CI_UDC #define CONFIG_USBD_HS -#define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_GADGET #define CONFIG_USB_FUNCTION_MASS_STORAGE -#define CONFIG_USB_GADGET_DOWNLOAD #define CONFIG_USB_GADGET_VBUS_DRAW 2 -#define CONFIG_G_DNL_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 -#define CONFIG_G_DNL_MANUFACTURER "FSL" - -#define CONFIG_G_DNL_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 -#define CONFIG_G_DNL_MANUFACTURER "FSL" +#define CONFIG_USB_FUNCTION_DFU +#define CONFIG_DFU_MMC +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M +#define DFU_DEFAULT_POLL_TIMEOUT 300 #define CONFIG_DEFAULT_FDT_FILE "imx6ul-pico-hobbit.dtb" @@ -76,6 +79,7 @@ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcautodetect=yes\0" \ + "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ @@ -86,7 +90,31 @@ "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "echo WARN: Cannot load the DT; " \ - "fi;\0" + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ #define CONFIG_BOOTCOMMAND \ "if mmc rescan; then " \ @@ -118,6 +146,18 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) +/* I2C configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 + /* FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/popmetal_rk3288.h b/include/configs/popmetal_rk3288.h new file mode 100644 index 0000000..342557f --- /dev/null +++ b/include/configs/popmetal_rk3288.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS +#include <configs/rk3288_common.h> + +#define CONFIG_SPL_MMC_SUPPORT + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +/* SPL @ 32k for ~36k + * ENV @ 96k + * u-boot @ 128K + */ +#define CONFIG_ENV_OFFSET (96 * 1024) + +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 0b86402..072859e 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -56,8 +56,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #endif -#define CONFIG_PHYS_64BIT - /* Virtual address range for PCI region maps */ #define CONFIG_SYS_PCI_MAP_START 0x80000000 #define CONFIG_SYS_PCI_MAP_END 0xe8000000 diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 89cde20..f9e5f59 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -12,7 +12,6 @@ #include <asm/arch/rmobile.h> -#define CONFIG_CMD_BOOTI #define CONFIG_CMD_DFL #define CONFIG_CMD_SDRAM #define CONFIG_CMD_FAT diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 1bdcf9d..21d4683 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_RK3036_COMMON_H #define __CONFIG_RK3036_COMMON_H -#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_CACHELINE_SIZE 64 #include <asm/arch/hardware.h> @@ -40,16 +40,12 @@ #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10) #define CONFIG_ROCKCHIP_CHIP_TAG "RK30" -#define CONFIG_ROCKCHIP_COMMON - /* MMC/SD IP block */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_SDHCI #define CONFIG_DWMMC #define CONFIG_BOUNCE_BUFFER -#define CONFIG_DOS_PARTITION #define CONFIG_FAT_WRITE #define CONFIG_PARTITION_UUIDS #define CONFIG_CMD_PART @@ -64,6 +60,25 @@ #define CONFIG_SF_DEFAULT_SPEED 20000000 #ifndef CONFIG_SPL_BUILD +/* usb otg */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_DWC2_OTG +#define CONFIG_USB_GADGET_VBUS_DRAW 0 + +/* fastboot */ +#define CONFIG_CMD_FASTBOOT +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_FASTBOOT_FLASH +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 0 +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x08000000 + +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_G_DNL_MANUFACTURER "Rockchip" +#define CONFIG_G_DNL_VENDOR_NUM 0x2207 +#define CONFIG_G_DNL_PRODUCT_NUM 0x310a + #include <config_distro_defaults.h> #define ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 9d50d83..d3d4c68 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -33,15 +33,17 @@ #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SPL_BOARD_INIT +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +/* Bootrom will load u-boot binary to 0x0 once return from SPL */ +#define CONFIG_SYS_TEXT_BASE 0x00000000 +#else #define CONFIG_SYS_TEXT_BASE 0x00100000 +#endif #define CONFIG_SYS_INIT_SP_ADDR 0x00100000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0xff718000 #define CONFIG_SPL_TEXT_BASE 0xff704004 -#define CONFIG_ROCKCHIP_COMMON -#define CONFIG_SPL_ROCKCHIP_COMMON - #define CONFIG_SILENT_CONSOLE #ifndef CONFIG_SPL_BUILD # define CONFIG_SYS_CONSOLE_IS_IN_ENV @@ -51,11 +53,9 @@ /* MMC/SD IP block */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_SDHCI #define CONFIG_DWMMC #define CONFIG_BOUNCE_BUFFER -#define CONFIG_DOS_PARTITION #define CONFIG_FAT_WRITE #define CONFIG_PARTITION_UUIDS #define CONFIG_CMD_PART @@ -81,6 +81,33 @@ #define CONFIG_SF_DEFAULT_SPEED 20000000 #ifndef CONFIG_SPL_BUILD +/* usb otg */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_DWC2_OTG +#define CONFIG_ROCKCHIP_USB2_PHY +#define CONFIG_USB_GADGET_VBUS_DRAW 0 + +/* fastboot */ +#define CONFIG_CMD_FASTBOOT +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_FASTBOOT_FLASH +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 /* eMMC */ +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x08000000 + +/* usb mass storage */ +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#define CONFIG_CMD_USB_MASS_STORAGE + +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_G_DNL_MANUFACTURER "Rockchip" +#define CONFIG_G_DNL_VENDOR_NUM 0x2207 +#define CONFIG_G_DNL_PRODUCT_NUM 0x320a + +/* Enable gpt partition table */ +#define CONFIG_CMD_GPT + #include <config_distro_defaults.h> #define ENV_MEM_LAYOUT_SETTINGS \ @@ -90,6 +117,12 @@ "kernel_addr_r=0x02000000\0" \ "ramdisk_addr_r=0x04000000\0" +#define CONFIG_RANDOM_UUID +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=boot,start=8M,size=64M,bootable,uuid=${uuid_gpt_boot};" \ + "name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \ + /* First try to boot from SD (index 0), then eMMC (index 1 */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ @@ -102,6 +135,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x1fffffff\0" \ "initrd_high=0x1fffffff\0" \ + "partitions=" PARTS_DEFAULT \ ENV_MEM_LAYOUT_SETTINGS \ ROCKCHIP_DEVICE_SETTINGS \ BOOTENV diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h new file mode 100644 index 0000000..6875308 --- /dev/null +++ b/include/configs/rk3399_common.h @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RK3399_COMMON_H +#define __CONFIG_RK3399_COMMON_H + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 1500000 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_TEXT_BASE 0x00200000 +#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 +#define CONFIG_SYS_LOAD_ADDR 0x00800800 + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +/* MMC/SD IP block */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DWMMC +#define CONFIG_SDHCI +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000 + +#define CONFIG_SUPPORT_VFAT +#define CONFIG_FS_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_FS_EXT4 +#define CONFIG_CMD_PART + +/* RAW SD card / eMMC locations. */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256 +#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) + +/* FAT sd card locations. */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI +#define CONFIG_SF_DEFAULT_SPEED 20000000 + +#ifndef CONFIG_SPL_BUILD +#include <config_distro_defaults.h> + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00000000\0" \ + "pxefile_addr_r=0x00100000\0" \ + "fdt_addr_r=0x01f00000\0" \ + "kernel_addr_r=0x02000000\0" \ + "ramdisk_addr_r=0x04000000\0" + +#define CONFIG_CMD_GPT +#define CONFIG_RANDOM_UUID +#define CONFIG_PARTITION_UUIDS +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=boot,start=16M,size=32M,bootable;" \ + "name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \ + +/* First try to boot from SD (index 0), then eMMC (index 1) */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#include <config_distro_bootcmd.h> +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "partitions=" PARTS_DEFAULT \ + BOOTENV + +#endif + +#endif diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 23a0c40..94e024b 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -16,8 +16,10 @@ #endif +#ifndef CONFIG_SPL_BUILD #define CONFIG_IO_TRACE #define CONFIG_CMD_IOTRACE +#endif #ifndef CONFIG_TIMER #define CONFIG_SYS_TIMER_RATE 1000000 @@ -25,7 +27,10 @@ #define CONFIG_SYS_STDIO_DEREGISTER -/* Number of bits in a C 'long' on this architecture */ +/* + * Number of bits in a C 'long' on this architecture. Set this to 32 when + * building on a 32-bit machine. + */ #define CONFIG_SANDBOX_BITS_PER_LONG 64 #define CONFIG_LMB @@ -80,7 +85,6 @@ #define CONFIG_CMD_SF_TEST #define CONFIG_I2C_EDID -#define CONFIG_I2C_EEPROM /* Memory things - we don't really want a memory test */ #define CONFIG_SYS_LOAD_ADDR 0x00000000 @@ -192,6 +196,7 @@ #define CONFIG_CMD_LZMADEC #define CONFIG_CMD_DATE +#ifndef CONFIG_SPL_BUILD #define CONFIG_CMD_IDE #define CONFIG_SYS_IDE_MAXBUS 1 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 @@ -201,6 +206,7 @@ #define CONFIG_SYS_ATA_REG_OFFSET 1 #define CONFIG_SYS_ATA_ALT_OFFSET 2 #define CONFIG_SYS_ATA_STRIDE 4 +#endif #define CONFIG_SCSI #define CONFIG_SCSI_AHCI_PLAT diff --git a/include/configs/sandbox_spl.h b/include/configs/sandbox_spl.h new file mode 100644 index 0000000..ffc3098 --- /dev/null +++ b/include/configs/sandbox_spl.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2016 Google, Inc + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SANDBOX_SPL_CONFIG_H +#define __SANDBOX_SPL_CONFIG_H + +#include <configs/sandbox.h> + +#define CONFIG_SPL_BOARD_INIT + +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#endif diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 46766a6..ec9ad45 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -595,7 +595,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=uRamdisk\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "fdtfile=sbc8548.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 6add391..076a5ce 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -122,6 +122,7 @@ * */ #define CONFIG_MACB +#define CONFIG_PHYLIB #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX #define CONFIG_USB_ETHER_MCS7830 diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index fd6c70e..c91ab71 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -56,6 +56,7 @@ /* Ethernet */ #define CONFIG_MACB +#define CONFIG_PHYLIB #define CONFIG_RMII #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_RESET_PHY_R diff --git a/include/configs/som-db5800-som-6867.h b/include/configs/som-db5800-som-6867.h new file mode 100644 index 0000000..a4b343e --- /dev/null +++ b/include/configs/som-db5800-som-6867.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_ARCH_MISC_INIT + +#define CONFIG_PCI_PNP +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd,vga\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT} + +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO + +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x006ef000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index e544a21..4391bff 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -24,13 +24,13 @@ * Configuration of the external SDRAM memory */ #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_RAM_SIZE ((64 + 192) << 10) +#define CONFIG_SYS_RAM_SIZE (8 * 1024 * 1024) #define CONFIG_SYS_RAM_CS 1 #define CONFIG_SYS_RAM_FREQ_DIV 2 -#define CONFIG_SYS_RAM_BASE 0x20000000 +#define CONFIG_SYS_RAM_BASE 0xC0000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE -#define CONFIG_SYS_LOAD_ADDR 0x20000000 -#define CONFIG_LOADADDR 0x20000000 +#define CONFIG_SYS_LOAD_ADDR 0xC0400000 +#define CONFIG_LOADADDR 0xC0400000 #define CONFIG_SYS_MAX_FLASH_SECT 8 #define CONFIG_SYS_MAX_FLASH_BANKS 1 @@ -42,7 +42,8 @@ #define CONFIG_STM32_FLASH #define CONFIG_STM32X7_SERIAL -#define CONFIG_SYS_CLK_FREQ 16*1000*1000 /* 180 MHz */ +#define CONFIG_STM32_HSE_HZ 25000000 +#define CONFIG_SYS_CLK_FREQ 200000000 /* 200 MHz */ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define CONFIG_CMDLINE_TAG diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h index 95ccc35..0625502 100644 --- a/include/configs/sun6i.h +++ b/include/configs/sun6i.h @@ -25,6 +25,7 @@ #define CONFIG_ARMV7_PSCI 1 #define CONFIG_ARMV7_PSCI_NR_CPUS 4 #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE +#define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */ /* * Include common sunxi configuration where most the settings are diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index 0dd2902..e9074d5 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -21,7 +21,9 @@ #define CONFIG_SUNXI_USB_PHYS 3 #define CONFIG_ARMV7_PSCI 1 +#define CONFIG_ARMV7_PSCI_NR_CPUS 2 #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE +#define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */ /* * Include common sunxi configuration where most the settings are diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 94275a7..b9aa62b 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -134,7 +134,15 @@ #define CONFIG_SERIAL_TAG #ifdef CONFIG_NAND_SUNXI +#define CONFIG_SYS_NAND_MAX_ECCPOS 1664 #define CONFIG_SPL_NAND_SUPPORT 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_MAX_NAND_DEVICE 8 +#endif + +#ifdef CONFIG_SPL_SPI_SUNXI +#define CONFIG_SPL_SPI_FLASH_SUPPORT 1 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 #endif /* mmc config */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 882a4e5..2d091db 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -99,6 +99,7 @@ /* Ethernet */ #define CONFIG_MACB +#define CONFIG_PHYLIB #define CONFIG_RMII #define CONFIG_AT91_WANTS_COMMON_PHY diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index ba7cf15..9f947ee 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -108,9 +108,25 @@ /* Timer information. */ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +/* + * Disable DM_* for SPL build and can be re-enabled after adding + * DM support in SPL + */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_I2C +#endif + /* I2C IP block */ #define CONFIG_I2C +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#else +/* + * Enable CONFIG_DM_I2C_COMPAT temporarily until all the i2c client + * devices are adopted to DM + */ +#define CONFIG_DM_I2C_COMPAT +#endif /* MMC/SD IP block */ #define CONFIG_MMC diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 2ee26c4..4aa262e 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -89,6 +89,10 @@ #define CONFIG_SYS_SPI2 #define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE #define CONFIG_SYS_SPI2_NUM_CS 4 +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH +#endif /* Network Configuration */ #define CONFIG_PHYLIB diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index b761640..9d49f63 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -37,7 +37,8 @@ #define CONFIG_ENV_SPI_MAX_HZ 48000000 #define CONFIG_ENV_SPI_MODE SPI_MODE_0 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -#define CONFIG_ENV_OFFSET (512 * 1024) +/* 1MiB flash, environment located as high as possible */ +#define CONFIG_ENV_OFFSET (SZ_1M - CONFIG_ENV_SIZE) /* USB Host support */ #define CONFIG_USB_EHCI diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 4ebaf84..0f5b20f 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -1,5 +1,7 @@ /* - * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2012-2015 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,7 +11,9 @@ #ifndef __CONFIG_UNIPHIER_COMMON_H__ #define __CONFIG_UNIPHIER_COMMON_H__ -#define CONFIG_I2C_EEPROM +#define CONFIG_ARMV7_PSCI +#define CONFIG_ARMV7_PSCI_NR_CPUS 4 + #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 #define CONFIG_SMC911X @@ -26,10 +30,11 @@ /* #define CONFIG_SYS_ICACHE_OFF */ /* #define CONFIG_SYS_DCACHE_OFF */ +#ifdef CONFIG_CACHE_UNIPHIER +#define CONFIG_SYS_CACHELINE_SIZE 128 +#else #define CONFIG_SYS_CACHELINE_SIZE 32 - -/* Comment out the following to disable L2 cache */ -#define CONFIG_UNIPHIER_L2CACHE_ON +#endif #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -184,7 +189,6 @@ "__nfsboot=run tftpboot\0" #else #ifdef CONFIG_ARM64 -#define CONFIG_CMD_BOOTI #define CONFIG_BOOTFILE "Image" #define LINUXBOOT_CMD "booti" #define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0" @@ -226,7 +230,6 @@ "run boot_common\0" \ "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \ "tftpboot $fdt_addr_r $fdt_file &&" \ - "tftpboot $fdt_addr_r $fdt_file &&" \ "setenv ramdisk_addr_r - &&" \ "run boot_common\0" #endif diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 8568663..5484204 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -17,16 +17,13 @@ #define CONFIG_SYS_FSL_CLK #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MXC_GPIO +#define CONFIG_SYS_NO_FLASH #include <asm/arch/imx-regs.h> #include <config_distro_defaults.h> -/* U-Boot commands */ - /* U-Boot environment */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_NO_FLASH #define CONFIG_ENV_OFFSET (6 * 64 * 1024) #define CONFIG_ENV_SIZE (8 * 1024) #define CONFIG_ENV_IS_IN_MMC @@ -69,17 +66,19 @@ #define CONFIG_CMD_FUSE #define CONFIG_FSL_IIM -/* Linux boot */ +/* U-Boot memory offsets */ #define CONFIG_LOADADDR 0x72000000 #define CONFIG_SYS_TEXT_BASE 0x77800000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Linux boot */ #define CONFIG_HOSTNAME usbarmory #define CONFIG_BOOTCOMMAND \ "run distro_bootcmd; " \ "setenv bootargs console=${console} ${bootargs_default}; " \ - "ext2load mmc 0:1 ${kernel_addr_r} /boot/uImage; " \ + "ext2load mmc 0:1 ${kernel_addr_r} /boot/zImage; " \ "ext2load mmc 0:1 ${fdt_addr_r} /boot/${fdtfile}; " \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}" + "bootz ${kernel_addr_r} - ${fdt_addr_r}" #define BOOT_TARGET_DEVICES(func) func(MMC, mmc, 0) @@ -99,6 +98,12 @@ "console=ttymxc0,115200\0" \ BOOTENV +#ifndef CONFIG_CMDLINE +#define CONFIG_BOOTARGS "console=ttymxc0,115200 root=/dev/mmcblk0p1 rootwait rw" +#define USBARMORY_FIT_PATH "/boot/usbarmory.itb" +#define USBARMORY_FIT_ADDR "0x70800000" +#endif + /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM CSD0_BASE_ADDR diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 28c748d..5ebdf5b 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -55,7 +55,7 @@ #define SDRAM_TAPDELAY 0x10000000 /* - * PCI - no suport + * PCI - no support */ #undef CONFIG_PCI diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 46cf83b..9aca393 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -133,7 +133,6 @@ /* Command line configuration */ #define CONFIG_MENU /*#define CONFIG_MENU_SHOW*/ -#define CONFIG_CMD_BOOTI #define CONFIG_CMD_UNZIP #define CONFIG_CMD_PXE #define CONFIG_CMD_ENV diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h index b509a9c..9583e8c 100644 --- a/include/configs/vexpress_ca15_tc2.h +++ b/include/configs/vexpress_ca15_tc2.h @@ -16,5 +16,6 @@ #define CONFIG_SYSFLAGS_ADDR 0x1c010030 #define CONFIG_SMP_PEN_ADDR CONFIG_SYSFLAGS_ADDR +#define CONFIG_ARMV7_PSCI_NR_CPUS 4 #endif diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 99f5c0c..2a00ff4 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -28,6 +28,18 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE +/* SATA Configs */ + +#define CONFIG_CMD_SATA +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + /* Command definition */ #define CONFIG_CMD_BMODE @@ -181,7 +193,7 @@ #define CONFIG_ENV_SIZE (8 * 1024) #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_OFFSET (768 * 1024) #define CONFIG_SYS_MMC_ENV_DEV 0 #endif /* __CONFIG_H * */ diff --git a/include/configs/warp.h b/include/configs/warp.h index 4a8e270..12c7c38 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -43,7 +43,6 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE SZ_512M #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR diff --git a/include/configs/warp7.h b/include/configs/warp7.h index fc0e51a..e59b16c 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -21,6 +21,8 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT +#define CONFIG_DISPLAY_BOARDINFO + /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR #define CONFIG_SUPPORT_EMMC_BOOT @@ -114,8 +116,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USB Configs */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX7 #define CONFIG_USB_STORAGE #define CONFIG_EHCI_HCD_INIT_AFTER_RESET @@ -125,18 +125,9 @@ #define CONFIG_IMX_THERMAL -#define CONFIG_CI_UDC #define CONFIG_USBD_HS -#define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_GADGET #define CONFIG_USB_FUNCTION_MASS_STORAGE -#define CONFIG_USB_GADGET_DOWNLOAD -#define CONFIG_USB_GADGET_VBUS_DRAW 2 - -#define CONFIG_G_DNL_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 -#define CONFIG_G_DNL_MANUFACTURER "FSL" /* USB Device Firmware Update support */ #define CONFIG_USB_FUNCTION_DFU diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index e776e32..ca60e5d 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -41,7 +41,7 @@ # define CONFIG_IDENT_STRING " Xilinx ZynqMP" #endif -#define CONFIG_SYS_INIT_SP_ADDR 0xfffffffc +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ #if !defined(COUNTER_FREQUENCY) @@ -117,7 +117,6 @@ #if defined(CONFIG_ZYNQMP_USB) #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE #define CONFIG_USB_XHCI_ZYNQMP #define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000 @@ -206,7 +205,6 @@ #define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) -#define CONFIG_CMD_BOOTI #define CONFIG_CMD_UNZIP #define CONFIG_BOARD_EARLY_INIT_R @@ -257,6 +255,7 @@ #endif #define CONFIG_SPL_TEXT_BASE 0xfffc0000 +#define CONFIG_SPL_STACK 0xfffffffc #define CONFIG_SPL_MAX_SIZE 0x20000 /* Just random location in OCM */ diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index c5bd5da..44434aa 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -17,6 +17,7 @@ #define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9) #define CONFIG_ZYNQ_EEPROM #define CONFIG_AHCI +#define CONFIG_SATA_CEVA #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ ZYNQMP_USB1_XHCI_BASEADDR} diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h index 73c8d5b..bc91714 100644 --- a/include/configs/xpedite1000.h +++ b/include/configs/xpedite1000.h @@ -304,7 +304,7 @@ extern void out32(unsigned int, unsigned long); "osfile=/home/user/board.uImage\0" \ "fdtfile=/home/user/board.dtb\0" \ "ubootfile=/home/user/u-boot.bin\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=0x1e00000\0" \ "osaddr=0x1000000\0" \ "loadaddr=0x1000000\0" \ "prog_uboot="CONFIG_PROG_UBOOT"\0" \ diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 9f3158d..eaea33b 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -699,7 +699,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "osfile=/home/user/board.uImage\0" \ "fdtfile=/home/user/board.dtb\0" \ "ubootfile=/home/user/u-boot.bin\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=0x1e00000\0" \ "osaddr=0x1000000\0" \ "loadaddr=0x1000000\0" \ "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index a418fc5..f7cfc9e 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -483,7 +483,7 @@ "osfile=/home/user/board.uImage\0" \ "fdtfile=/home/user/board.dtb\0" \ "ubootfile=/home/user/u-boot.bin\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=0x1e00000\0" \ "osaddr=0x1000000\0" \ "loadaddr=0x1000000\0" \ "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 36df668..3306e44a 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -554,7 +554,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); "osfile=/home/user/board.uImage\0" \ "fdtfile=/home/user/board.dtb\0" \ "ubootfile=/home/user/u-boot.bin\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=0x1e00000\0" \ "osaddr=0x1000000\0" \ "loadaddr=0x1000000\0" \ "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 1794ba1..276dde7 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -538,7 +538,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); "osfile=/home/user/board.uImage\0" \ "fdtfile=/home/user/board.dtb\0" \ "ubootfile=/home/user/u-boot.bin\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=0x1e00000\0" \ "osaddr=0x1000000\0" \ "loadaddr=0x1000000\0" \ "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h new file mode 100644 index 0000000..c5b06e3 --- /dev/null +++ b/include/configs/xtfpga.h @@ -0,0 +1,268 @@ +/* + * Copyright (C) 2007-2013 Tensilica, Inc. + * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/core.h> +#include <asm/addrspace.h> +#include <asm/config.h> + +/* + * The 'xtfpga' board describes a set of very similar boards with only minimal + * differences. + */ + +/*=====================*/ +/* Board and Processor */ +/*=====================*/ + +#define CONFIG_XTFPGA + +/* FPGA CPU freq after init */ +#define CONFIG_SYS_CLK_FREQ (gd->cpu_clk) + +/*===================*/ +/* RAM Layout */ +/*===================*/ + +#if XCHAL_HAVE_PTP_MMU +#define CONFIG_SYS_MEMORY_BASE \ + (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR) +#define CONFIG_SYS_IO_BASE 0xf0000000 +#else +#define CONFIG_SYS_MEMORY_BASE 0x60000000 +#define CONFIG_SYS_IO_BASE 0x90000000 +#define CONFIG_MAX_MEM_MAPPED 0x10000000 +#endif + +/* Onboard RAM sizes: + * + * LX60 0x04000000 64 MB + * LX110 0x03000000 48 MB + * LX200 0x06000000 96 MB + * ML605 0x18000000 384 MB + * KC705 0x38000000 896 MB + * + * noMMU configurations can only see first 256MB of onboard memory. + */ + +#if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000 +#define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE +#else +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#endif + +#define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000) + +/* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */ +#ifdef CONFIG_XTFPGA_LX60 +# define CONFIG_SYS_MONITOR_LEN 0x00020000 /* 128KB */ +#else +# define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */ +#endif + +#define CONFIG_SYS_STACKSIZE (512 << 10) /* stack 512KB */ +#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* heap 256KB */ + +/* Linux boot param area in RAM (used only when booting linux) */ +#define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10) + +/* Memory test is destructive so default must not overlap vectors or U-Boot*/ +#define CONFIG_SYS_MEMTEST_START MEMADDR(0x01000000) +#define CONFIG_SYS_MEMTEST_END MEMADDR(0x02000000) + +/* Load address for stand-alone applications. + * MEMADDR cannot be used here, because the definition needs to be + * a plain number as it's used as -Ttext argument for ld in standalone + * example makefile. + * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually. + */ +#if XCHAL_HAVE_PTP_MMU +#if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR +#define CONFIG_STANDALONE_LOAD_ADDR 0x00800000 +#else +#define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000 +#endif +#else +#define CONFIG_STANDALONE_LOAD_ADDR 0x60800000 +#endif + +#if defined(CONFIG_MAX_MEM_MAPPED) && \ + CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE +#define CONFIG_SYS_MEMORY_SIZE CONFIG_MAX_MEM_MAPPED +#else +#define CONFIG_SYS_MEMORY_SIZE CONFIG_SYS_SDRAM_SIZE +#endif + +#define CONFIG_SYS_MEMORY_TOP MEMADDR(CONFIG_SYS_MEMORY_SIZE) +#define CONFIG_SYS_TEXT_ADDR \ + (CONFIG_SYS_MEMORY_TOP - CONFIG_SYS_MONITOR_LEN) + +/* Used by tftpboot; env var 'loadaddr' */ +#define CONFIG_SYS_LOAD_ADDR MEMADDR(0x02000000) + +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ + +#undef CONFIG_USE_IRQ /* Keep it simple, poll only */ +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_MISC_INIT_R + +#define CONFIG_BOOTFILE "uImage" + /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 + /* Prt buf */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + /* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + /* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/*=================*/ +/* U-Boot commands */ +/*=================*/ + +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_SAVES + +/*==============================*/ +/* U-Boot autoboot configuration */ +/*==============================*/ + +#define CONFIG_BOOT_RETRY_TIME 60 /* retry after 60 secs */ + +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE /* Support tab autocompletion */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +#define CONFIG_SHOW_BOOT_PROGRESS + +#ifdef DEBUG +#define CONFIG_PANIC_HANG 1 /* Require manual reboot */ +#endif + + +/*=========================================*/ +/* FPGA Registers (board info and control) */ +/*=========================================*/ + +/* + * These assume FPGA bitstreams from Tensilica release RB and up. Earlier + * releases may not provide any/all of these registers or at these offsets. + * Some of the FPGA registers are broken down into bitfields described by + * SHIFT left amount and field WIDTH (bits), and also by a bitMASK. + */ + +/* Date of FPGA bitstream build in binary coded decimal (BCD) */ +#define CONFIG_SYS_FPGAREG_DATE IOADDR(0x0D020000) +#define FPGAREG_MTH_SHIFT 24 /* BCD month 1..12 */ +#define FPGAREG_MTH_WIDTH 8 +#define FPGAREG_MTH_MASK 0xFF000000 +#define FPGAREG_DAY_SHIFT 16 /* BCD day 1..31 */ +#define FPGAREG_DAY_WIDTH 8 +#define FPGAREG_DAY_MASK 0x00FF0000 +#define FPGAREG_YEAR_SHIFT 0 /* BCD year 2001..9999*/ +#define FPGAREG_YEAR_WIDTH 16 +#define FPGAREG_YEAR_MASK 0x0000FFFF + +/* FPGA core clock frequency in Hz (also input to UART) */ +#define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ + +/* + * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): + * Bits 0..5 set the lower 6 bits of the default ethernet MAC. + * Bit 6 is reserved for future use by Tensilica. + * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to + * the base of flash * (when on/1) or to the base of RAM (when off/0). + */ +#define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) +#define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */ +#define FPGAREG_MAC_WIDTH 6 +#define FPGAREG_MAC_MASK 0x3f +#define FPGAREG_BOOT_SHIFT 7 /* Boot ROM addr mapping */ +#define FPGAREG_BOOT_WIDTH 1 +#define FPGAREG_BOOT_MASK 0x80 +#define FPGAREG_BOOT_RAM 0 +#define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT) + +/* Force hard reset of board by writing a code to this register */ +#define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */ +#define CONFIG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */ + +/*====================*/ +/* Serial Driver Info */ +/*====================*/ + +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */ + +/* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*======================*/ +/* Ethernet Driver Info */ +/*======================*/ + +#define CONFIG_ETHBASE 00:50:C2:13:6f:00 +#define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000) +#define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000) + +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER /* use generic CFI driver */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#ifdef CONFIG_XTFPGA_LX60 +# define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */ +# define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* block size 64KB */ +# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */ +# define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) +# define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#elif defined(CONFIG_XTFPGA_KC705) +# define CONFIG_SYS_FLASH_SIZE 0x8000000 /* 128MB */ +# define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */ +# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ +# define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000) +# define CONFIG_SYS_MONITOR_BASE IOADDR(0x06000000) +#else +# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* 16MB */ +# define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */ +# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ +# define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) +# define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#endif +#define CONFIG_SYS_MAX_FLASH_SECT \ + (CONFIG_SYS_FLASH_SECT_SZ/CONFIG_SYS_FLASH_PARMSECT_SZ + \ + CONFIG_SYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ - 1) +#define CONFIG_SYS_FLASH_PROTECTION /* hw flash protection */ + +/* + * Put environment in top block (64kB) + * Another option would be to put env. in 2nd param block offs 8KB, size 8KB + */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SIZE - CONFIG_SYS_FLASH_SECT_SZ) +#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SZ + +/* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_EMPTY_INFO + +#endif /* __CONFIG_H */ diff --git a/include/configs/zc5202.h b/include/configs/zc5202.h new file mode 100644 index 0000000..073a42c --- /dev/null +++ b/include/configs/zc5202.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) Stefano Babic <sbabic@denx.de> + * + * Configuration settings for the E+L i.MX6Q DO82 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __EL_ZC5202_H +#define __EL_ZC5202_H + +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CONSOLE_DEV "ttymxc1" +#define CONFIG_MMCROOT "/dev/mmcblk0p2" + +#define CONFIG_DEFAULT_FDT_FILE "imx6q-zc5202.dtb" + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#include "el6x_common.h" + +/* Ethernet */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE MII100 +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_MV88E6352_SWITCH + +#define CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX + +#endif /*__EL6Q_CONFIG_H */ diff --git a/include/configs/zc5601.h b/include/configs/zc5601.h new file mode 100644 index 0000000..28b9c6b --- /dev/null +++ b/include/configs/zc5601.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) Stefano Babic <sbabic@denx.de> + * + * Configuration settings for the E+L i.MX6Q DO82 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __EL_ZC5601_H +#define __EL_ZC5601_H + + +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CONSOLE_DEV "ttymxc1" +#define CONFIG_MMCROOT "/dev/mmcblk0p1" + +#define CONFIG_DEFAULT_FDT_FILE "imx6q-zc5601.dtb" + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#include "el6x_common.h" + +/* Ethernet */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0x10 +#define CONFIG_PHYLIB +#define CONFIG_FEC_FIXED_SPEED 1000 /* No autoneg, fix Gb */ + +#endif /*__EL6Q_CONFIG_H */ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 8dbac87..e59e412 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -86,10 +86,7 @@ # define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 #endif -#ifdef CONFIG_ZYNQ_USB -# define CONFIG_USB_EHCI -# define CONFIG_USB_STORAGE -# define CONFIG_USB_EHCI_ZYNQ +#ifdef CONFIG_USB_EHCI_ZYNQ # define CONFIG_EHCI_IS_TDI # define CONFIG_USB_MAX_CONTROLLER_COUNT 2 diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h deleted file mode 100644 index ec7bb1c..0000000 --- a/include/configs/zynq_microzed.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * (C) Copyright 2013 Xilinx, Inc. - * - * Configuration for Micro Zynq Evaluation and Development Board - MicroZedBoard - * See zynq-common.h for Zynq common configs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_ZYNQ_MICROZED_H -#define __CONFIG_ZYNQ_MICROZED_H - -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_ZYNQ_USB - -#include <configs/zynq-common.h> - -#endif /* __CONFIG_ZYNQ_MICROZED_H */ diff --git a/include/configs/zynq_picozed.h b/include/configs/zynq_picozed.h deleted file mode 100644 index adc4d0f..0000000 --- a/include/configs/zynq_picozed.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * (C) Copyright 2015 Xilinx, Inc. - * - * Configuration for PicoZed - * See zynq-common.h for Zynq common configs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_ZYNQ_PICOZED_H -#define __CONFIG_ZYNQ_PICOZED_H - -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_ZYNQ_USB - -#include <configs/zynq-common.h> - -#endif /* __CONFIG_ZYNQ_PICOZED_H */ diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h index 8a04590..fc46fec 100644 --- a/include/configs/zynq_zc70x.h +++ b/include/configs/zynq_zc70x.h @@ -10,9 +10,6 @@ #ifndef __CONFIG_ZYNQ_ZC70X_H #define __CONFIG_ZYNQ_ZC70X_H -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_ZYNQ_USB #define CONFIG_ZYNQ_I2C0 #define CONFIG_ZYNQ_EEPROM diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h deleted file mode 100644 index 35622ae..0000000 --- a/include/configs/zynq_zc770.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2013 Xilinx, Inc. - * - * Configuration settings for the Xilinx Zynq ZC770 board. - * See zynq-common.h for Zynq common configs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_ZYNQ_ZC770_H -#define __CONFIG_ZYNQ_ZC770_H - -#define CONFIG_SYS_NO_FLASH - -#if defined(CONFIG_ZC770_XM012) -# undef CONFIG_SYS_NO_FLASH - -#endif - -#include <configs/zynq-common.h> - -#endif /* __CONFIG_ZYNQ_ZC770_H */ diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h deleted file mode 100644 index 150cb4a..0000000 --- a/include/configs/zynq_zed.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * (C) Copyright 2013 Xilinx, Inc. - * - * Configuration for Zynq Evaluation and Development Board - ZedBoard - * See zynq-common.h for Zynq common configs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_ZYNQ_ZED_H -#define __CONFIG_ZYNQ_ZED_H - -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_ZYNQ_USB - -#include <configs/zynq-common.h> - -#endif /* __CONFIG_ZYNQ_ZED_H */ diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h index 637b1c5..b9ff391 100644 --- a/include/configs/zynq_zybo.h +++ b/include/configs/zynq_zybo.h @@ -11,9 +11,6 @@ #ifndef __CONFIG_ZYNQ_ZYBO_H #define __CONFIG_ZYNQ_ZYBO_H -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_ZYNQ_USB #define CONFIG_ZYNQ_I2C0 #define CONFIG_ZYNQ_I2C1 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 diff --git a/include/dm/device.h b/include/dm/device.h index f03bcd3..babf8ac 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -42,7 +42,9 @@ struct driver_info; #define DM_FLAG_BOUND (1 << 6) /* Device name is allocated and should be freed on unbind() */ -#define DM_NAME_ALLOCED (1 << 7) +#define DM_FLAG_NAME_ALLOCED (1 << 7) + +#define DM_FLAG_OF_PLATDATA (1 << 8) /** * struct udevice - An instance of a driver @@ -205,6 +207,10 @@ struct driver { #define U_BOOT_DRIVER(__name) \ ll_entry_declare(struct driver, __name, driver) +/* Get a pointer to a given driver */ +#define DM_GET_DRIVER(__name) \ + ll_entry_get(struct driver, __name, driver) + /** * dev_get_platdata() - Get the platform data for a device * @@ -467,6 +473,19 @@ fdt_addr_t dev_get_addr(struct udevice *dev); void *dev_get_addr_ptr(struct udevice *dev); /** + * dev_map_physmem() - Read device address from reg property of the + * device node and map the address into CPU address + * space. + * + * @dev: Pointer to device + * @size: size of the memory to map + * + * @return mapped address, or NULL if the device does not have reg + * property. + */ +void *dev_map_physmem(struct udevice *dev, unsigned long size); + +/** * dev_get_addr_index() - Get the indexed reg property of a device * * @dev: Pointer to a device @@ -540,7 +559,7 @@ int device_set_name(struct udevice *dev, const char *name); /** * device_set_name_alloced() - note that a device name is allocated * - * This sets the DM_NAME_ALLOCED flag for the device, so that when it is + * This sets the DM_FLAG_NAME_ALLOCED flag for the device, so that when it is * unbound the name will be freed. This avoids memory leaks. * * @dev: Device to update @@ -593,6 +612,22 @@ static inline bool device_is_on_pci_bus(struct udevice *dev) #define device_foreach_child_safe(pos, next, parent) \ list_for_each_entry_safe(pos, next, &parent->child_head, sibling_node) +/** + * dm_scan_fdt_dev() - Bind child device in a the device tree + * + * This handles device which have sub-nodes in the device tree. It scans all + * sub-nodes and binds drivers for each node where a driver can be found. + * + * If this is called prior to relocation, only pre-relocation devices will be + * bound (those marked with u-boot,dm-pre-reloc in the device tree, or where + * the driver has the DM_FLAG_PRE_RELOC flag set). Otherwise, all devices will + * be bound. + * + * @dev: Device to scan + * @return 0 if OK, -ve on error + */ +int dm_scan_fdt_dev(struct udevice *dev); + /* device resource management */ typedef void (*dr_release_t)(struct udevice *dev, void *res); typedef int (*dr_match_t)(struct udevice *dev, void *res, void *match_data); diff --git a/include/dm/platdata.h b/include/dm/platdata.h index 6f4f001..488b2ab 100644 --- a/include/dm/platdata.h +++ b/include/dm/platdata.h @@ -22,10 +22,15 @@ * * @name: Driver name * @platdata: Driver-specific platform data + * @platdata_size: Size of platform data structure + * @flags: Platform data flags (DM_FLAG_...) */ struct driver_info { const char *name; const void *platdata; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + uint platdata_size; +#endif }; /** diff --git a/include/dm/platform_data/net_ethoc.h b/include/dm/platform_data/net_ethoc.h new file mode 100644 index 0000000..3f94bde --- /dev/null +++ b/include/dm/platform_data/net_ethoc.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ETHOC_H +#define _ETHOC_H + +#include <net.h> + +#ifdef CONFIG_DM_ETH + +struct ethoc_eth_pdata { + struct eth_pdata eth_pdata; + phys_addr_t packet_base; +}; + +#endif + +#endif /* _ETHOC_H */ diff --git a/include/dm/platform_data/serial_mxc.h b/include/dm/platform_data/serial_mxc.h index 7d3ace2..7bcd280 100644 --- a/include/dm/platform_data/serial_mxc.h +++ b/include/dm/platform_data/serial_mxc.h @@ -9,6 +9,7 @@ /* Information about a serial port */ struct mxc_serial_platdata { struct mxc_uart *reg; /* address of registers in physical memory */ + bool use_dte; }; #endif diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index b768660..eb78c4d 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -33,7 +33,6 @@ enum uclass_id { UCLASS_CROS_EC, /* Chrome OS EC */ UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */ UCLASS_DMA, /* Direct Memory Access */ - UCLASS_RAM, /* RAM controller */ UCLASS_ETH, /* Ethernet device */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ UCLASS_I2C, /* I2C bus */ @@ -56,11 +55,13 @@ enum uclass_id { UCLASS_PCH, /* x86 platform controller hub */ UCLASS_PCI, /* PCI bus */ UCLASS_PCI_GENERIC, /* Generic PCI bus device */ - UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */ UCLASS_PINCONFIG, /* Pin configuration node device */ + UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */ UCLASS_PMIC, /* PMIC I/O device */ UCLASS_PWM, /* Pulse-width modulator */ + UCLASS_POWER_DOMAIN, /* (SoC) Power domains */ UCLASS_PWRSEQ, /* Power sequence device */ + UCLASS_RAM, /* RAM controller */ UCLASS_REGULATOR, /* Regulator device */ UCLASS_REMOTEPROC, /* Remote Processor device */ UCLASS_RESET, /* Reset controller device */ diff --git a/include/dm/uclass.h b/include/dm/uclass.h index fd368b6..84f05bc 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -38,6 +38,7 @@ struct uclass { struct list_head sibling_node; }; +struct driver; struct udevice; /* Members of this uclass sequence themselves with aliases */ @@ -194,6 +195,23 @@ int uclass_get_device_by_phandle(enum uclass_id id, struct udevice *parent, const char *name, struct udevice **devp); /** + * uclass_get_device_by_driver() - Get a uclass device for a driver + * + * This searches the devices in the uclass for one that uses the given + * driver. Use DM_GET_DRIVER(name) for the @drv argument, where 'name' is + * the driver name - as used in U_BOOT_DRIVER(name). + * + * The device is probed to activate it ready for use. + * + * @id: ID to look up + * @drv: Driver to look for + * @devp: Returns pointer to the first device with that driver + * @return 0 if OK, -ve on error + */ +int uclass_get_device_by_driver(enum uclass_id id, const struct driver *drv, + struct udevice **devp); + +/** * uclass_first_device() - Get the first device in a uclass * * The device returned is probed if necessary, and ready for use diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h new file mode 100644 index 0000000..0a86aec --- /dev/null +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -0,0 +1,746 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H + +/* core clocks */ +#define PLL_APLLL 1 +#define PLL_APLLB 2 +#define PLL_DPLL 3 +#define PLL_CPLL 4 +#define PLL_GPLL 5 +#define PLL_NPLL 6 +#define PLL_VPLL 7 +#define ARMCLKL 8 +#define ARMCLKB 9 + +/* sclk gates (special clocks) */ +#define SCLK_I2C1 65 +#define SCLK_I2C2 66 +#define SCLK_I2C3 67 +#define SCLK_I2C5 68 +#define SCLK_I2C6 69 +#define SCLK_I2C7 70 +#define SCLK_SPI0 71 +#define SCLK_SPI1 72 +#define SCLK_SPI2 73 +#define SCLK_SPI4 74 +#define SCLK_SPI5 75 +#define SCLK_SDMMC 76 +#define SCLK_SDIO 77 +#define SCLK_EMMC 78 +#define SCLK_TSADC 79 +#define SCLK_SARADC 80 +#define SCLK_UART0 81 +#define SCLK_UART1 82 +#define SCLK_UART2 83 +#define SCLK_UART3 84 +#define SCLK_SPDIF_8CH 85 +#define SCLK_I2S0_8CH 86 +#define SCLK_I2S1_8CH 87 +#define SCLK_I2S2_8CH 88 +#define SCLK_I2S_8CH_OUT 89 +#define SCLK_TIMER00 90 +#define SCLK_TIMER01 91 +#define SCLK_TIMER02 92 +#define SCLK_TIMER03 93 +#define SCLK_TIMER04 94 +#define SCLK_TIMER05 95 +#define SCLK_TIMER06 96 +#define SCLK_TIMER07 97 +#define SCLK_TIMER08 98 +#define SCLK_TIMER09 99 +#define SCLK_TIMER10 100 +#define SCLK_TIMER11 101 +#define SCLK_MACREF 102 +#define SCLK_MAC_RX 103 +#define SCLK_MAC_TX 104 +#define SCLK_MAC 105 +#define SCLK_MACREF_OUT 106 +#define SCLK_VOP0_PWM 107 +#define SCLK_VOP1_PWM 108 +#define SCLK_RGA_CORE 109 +#define SCLK_ISP0 110 +#define SCLK_ISP1 111 +#define SCLK_HDMI_CEC 112 +#define SCLK_HDMI_SFR 113 +#define SCLK_DP_CORE 114 +#define SCLK_PVTM_CORE_L 115 +#define SCLK_PVTM_CORE_B 116 +#define SCLK_PVTM_GPU 117 +#define SCLK_PVTM_DDR 118 +#define SCLK_MIPIDPHY_REF 119 +#define SCLK_MIPIDPHY_CFG 120 +#define SCLK_HSICPHY 121 +#define SCLK_USBPHY480M 122 +#define SCLK_USB2PHY0_REF 123 +#define SCLK_USB2PHY1_REF 124 +#define SCLK_UPHY0_TCPDPHY_REF 125 +#define SCLK_UPHY0_TCPDCORE 126 +#define SCLK_UPHY1_TCPDPHY_REF 127 +#define SCLK_UPHY1_TCPDCORE 128 +#define SCLK_USB3OTG0_REF 129 +#define SCLK_USB3OTG1_REF 130 +#define SCLK_USB3OTG0_SUSPEND 131 +#define SCLK_USB3OTG1_SUSPEND 132 +#define SCLK_CRYPTO0 133 +#define SCLK_CRYPTO1 134 +#define SCLK_CCI_TRACE 135 +#define SCLK_CS 136 +#define SCLK_CIF_OUT 137 +#define SCLK_PCIEPHY_REF 138 +#define SCLK_PCIE_CORE 139 +#define SCLK_M0_PERILP 140 +#define SCLK_M0_PERILP_DEC 141 +#define SCLK_CM0S 142 +#define SCLK_DBG_NOC 143 +#define SCLK_DBG_PD_CORE_B 144 +#define SCLK_DBG_PD_CORE_L 145 +#define SCLK_DFIMON0_TIMER 146 +#define SCLK_DFIMON1_TIMER 147 +#define SCLK_INTMEM0 148 +#define SCLK_INTMEM1 149 +#define SCLK_INTMEM2 150 +#define SCLK_INTMEM3 151 +#define SCLK_INTMEM4 152 +#define SCLK_INTMEM5 153 +#define SCLK_SDMMC_DRV 154 +#define SCLK_SDMMC_SAMPLE 155 +#define SCLK_SDIO_DRV 156 +#define SCLK_SDIO_SAMPLE 157 +#define SCLK_VDU_CORE 158 +#define SCLK_VDU_CA 159 +#define SCLK_PCIE_PM 160 +#define SCLK_SPDIF_REC_DPTX 161 +#define SCLK_DPHY_PLL 162 +#define SCLK_DPHY_TX0_CFG 163 +#define SCLK_DPHY_TX1RX1_CFG 164 +#define SCLK_DPHY_RX0_CFG 165 +#define SCLK_RMII_SRC 166 +#define SCLK_PCIEPHY_REF100M 167 + +#define DCLK_VOP0 180 +#define DCLK_VOP1 181 +#define DCLK_VOP0_DIV 182 +#define DCLK_VOP1_DIV 183 +#define DCLK_M0_PERILP 184 + +#define FCLK_CM0S 190 + +/* aclk gates */ +#define ACLK_PERIHP 192 +#define ACLK_PERIHP_NOC 193 +#define ACLK_PERILP0 194 +#define ACLK_PERILP0_NOC 195 +#define ACLK_PERF_PCIE 196 +#define ACLK_PCIE 197 +#define ACLK_INTMEM 198 +#define ACLK_TZMA 199 +#define ACLK_DCF 200 +#define ACLK_CCI 201 +#define ACLK_CCI_NOC0 202 +#define ACLK_CCI_NOC1 203 +#define ACLK_CCI_GRF 204 +#define ACLK_CENTER 205 +#define ACLK_CENTER_MAIN_NOC 206 +#define ACLK_CENTER_PERI_NOC 207 +#define ACLK_GPU 208 +#define ACLK_PERF_GPU 209 +#define ACLK_GPU_GRF 210 +#define ACLK_DMAC0_PERILP 211 +#define ACLK_DMAC1_PERILP 212 +#define ACLK_GMAC 213 +#define ACLK_GMAC_NOC 214 +#define ACLK_PERF_GMAC 215 +#define ACLK_VOP0_NOC 216 +#define ACLK_VOP0 217 +#define ACLK_VOP1_NOC 218 +#define ACLK_VOP1 219 +#define ACLK_RGA 220 +#define ACLK_RGA_NOC 221 +#define ACLK_HDCP 222 +#define ACLK_HDCP_NOC 223 +#define ACLK_HDCP22 224 +#define ACLK_IEP 225 +#define ACLK_IEP_NOC 226 +#define ACLK_VIO 227 +#define ACLK_VIO_NOC 228 +#define ACLK_ISP0 229 +#define ACLK_ISP1 230 +#define ACLK_ISP0_NOC 231 +#define ACLK_ISP1_NOC 232 +#define ACLK_ISP0_WRAPPER 233 +#define ACLK_ISP1_WRAPPER 234 +#define ACLK_VCODEC 235 +#define ACLK_VCODEC_NOC 236 +#define ACLK_VDU 237 +#define ACLK_VDU_NOC 238 +#define ACLK_PERI 239 +#define ACLK_EMMC 240 +#define ACLK_EMMC_CORE 241 +#define ACLK_EMMC_NOC 242 +#define ACLK_EMMC_GRF 243 +#define ACLK_USB3 244 +#define ACLK_USB3_NOC 245 +#define ACLK_USB3OTG0 246 +#define ACLK_USB3OTG1 247 +#define ACLK_USB3_RKSOC_AXI_PERF 248 +#define ACLK_USB3_GRF 249 +#define ACLK_GIC 250 +#define ACLK_GIC_NOC 251 +#define ACLK_GIC_ADB400_CORE_L_2_GIC 252 +#define ACLK_GIC_ADB400_CORE_B_2_GIC 253 +#define ACLK_GIC_ADB400_GIC_2_CORE_L 254 +#define ACLK_GIC_ADB400_GIC_2_CORE_B 255 +#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 +#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 +#define ACLK_ADB400M_PD_CORE_L 258 +#define ACLK_ADB400M_PD_CORE_B 259 +#define ACLK_PERF_CORE_L 260 +#define ACLK_PERF_CORE_B 261 +#define ACLK_GIC_PRE 262 +#define ACLK_VOP0_PRE 263 +#define ACLK_VOP1_PRE 264 + +/* pclk gates */ +#define PCLK_PERIHP 320 +#define PCLK_PERIHP_NOC 321 +#define PCLK_PERILP0 322 +#define PCLK_PERILP1 323 +#define PCLK_PERILP1_NOC 324 +#define PCLK_PERILP_SGRF 325 +#define PCLK_PERIHP_GRF 326 +#define PCLK_PCIE 327 +#define PCLK_SGRF 328 +#define PCLK_INTR_ARB 329 +#define PCLK_CENTER_MAIN_NOC 330 +#define PCLK_CIC 331 +#define PCLK_COREDBG_B 332 +#define PCLK_COREDBG_L 333 +#define PCLK_DBG_CXCS_PD_CORE_B 334 +#define PCLK_DCF 335 +#define PCLK_GPIO2 336 +#define PCLK_GPIO3 337 +#define PCLK_GPIO4 338 +#define PCLK_GRF 339 +#define PCLK_HSICPHY 340 +#define PCLK_I2C1 341 +#define PCLK_I2C2 342 +#define PCLK_I2C3 343 +#define PCLK_I2C5 344 +#define PCLK_I2C6 345 +#define PCLK_I2C7 346 +#define PCLK_SPI0 347 +#define PCLK_SPI1 348 +#define PCLK_SPI2 349 +#define PCLK_SPI4 350 +#define PCLK_SPI5 351 +#define PCLK_UART0 352 +#define PCLK_UART1 353 +#define PCLK_UART2 354 +#define PCLK_UART3 355 +#define PCLK_TSADC 356 +#define PCLK_SARADC 357 +#define PCLK_GMAC 358 +#define PCLK_GMAC_NOC 359 +#define PCLK_TIMER0 360 +#define PCLK_TIMER1 361 +#define PCLK_EDP 362 +#define PCLK_EDP_NOC 363 +#define PCLK_EDP_CTRL 364 +#define PCLK_VIO 365 +#define PCLK_VIO_NOC 366 +#define PCLK_VIO_GRF 367 +#define PCLK_MIPI_DSI0 368 +#define PCLK_MIPI_DSI1 369 +#define PCLK_HDCP 370 +#define PCLK_HDCP_NOC 371 +#define PCLK_HDMI_CTRL 372 +#define PCLK_DP_CTRL 373 +#define PCLK_HDCP22 374 +#define PCLK_GASKET 375 +#define PCLK_DDR 376 +#define PCLK_DDR_MON 377 +#define PCLK_DDR_SGRF 378 +#define PCLK_ISP1_WRAPPER 379 +#define PCLK_WDT 380 +#define PCLK_EFUSE1024NS 381 +#define PCLK_EFUSE1024S 382 +#define PCLK_PMU_INTR_ARB 383 +#define PCLK_MAILBOX0 384 +#define PCLK_USBPHY_MUX_G 385 +#define PCLK_UPHY0_TCPHY_G 386 +#define PCLK_UPHY0_TCPD_G 387 +#define PCLK_UPHY1_TCPHY_G 388 +#define PCLK_UPHY1_TCPD_G 389 +#define PCLK_ALIVE 390 + +/* hclk gates */ +#define HCLK_PERIHP 448 +#define HCLK_PERILP0 449 +#define HCLK_PERILP1 450 +#define HCLK_PERILP0_NOC 451 +#define HCLK_PERILP1_NOC 452 +#define HCLK_M0_PERILP 453 +#define HCLK_M0_PERILP_NOC 454 +#define HCLK_AHB1TOM 455 +#define HCLK_HOST0 456 +#define HCLK_HOST0_ARB 457 +#define HCLK_HOST1 458 +#define HCLK_HOST1_ARB 459 +#define HCLK_HSIC 460 +#define HCLK_SD 461 +#define HCLK_SDMMC 462 +#define HCLK_SDMMC_NOC 463 +#define HCLK_M_CRYPTO0 464 +#define HCLK_M_CRYPTO1 465 +#define HCLK_S_CRYPTO0 466 +#define HCLK_S_CRYPTO1 467 +#define HCLK_I2S0_8CH 468 +#define HCLK_I2S1_8CH 469 +#define HCLK_I2S2_8CH 470 +#define HCLK_SPDIF 471 +#define HCLK_VOP0_NOC 472 +#define HCLK_VOP0 473 +#define HCLK_VOP1_NOC 474 +#define HCLK_VOP1 475 +#define HCLK_ROM 476 +#define HCLK_IEP 477 +#define HCLK_IEP_NOC 478 +#define HCLK_ISP0 479 +#define HCLK_ISP1 480 +#define HCLK_ISP0_NOC 481 +#define HCLK_ISP1_NOC 482 +#define HCLK_ISP0_WRAPPER 483 +#define HCLK_ISP1_WRAPPER 484 +#define HCLK_RGA 485 +#define HCLK_RGA_NOC 486 +#define HCLK_HDCP 487 +#define HCLK_HDCP_NOC 488 +#define HCLK_HDCP22 489 +#define HCLK_VCODEC 490 +#define HCLK_VCODEC_NOC 491 +#define HCLK_VDU 492 +#define HCLK_VDU_NOC 493 +#define HCLK_SDIO 494 +#define HCLK_SDIO_NOC 495 +#define HCLK_SDIOAUDIO_NOC 496 + +#define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) + +/* pmu-clocks indices */ + +#define PLL_PPLL 1 + +#define SCLK_32K_SUSPEND_PMU 2 +#define SCLK_SPI3_PMU 3 +#define SCLK_TIMER12_PMU 4 +#define SCLK_TIMER13_PMU 5 +#define SCLK_UART4_PMU 6 +#define SCLK_PVTM_PMU 7 +#define SCLK_WIFI_PMU 8 +#define SCLK_I2C0_PMU 9 +#define SCLK_I2C4_PMU 10 +#define SCLK_I2C8_PMU 11 + +#define PCLK_SRC_PMU 19 +#define PCLK_PMU 20 +#define PCLK_PMUGRF_PMU 21 +#define PCLK_INTMEM1_PMU 22 +#define PCLK_GPIO0_PMU 23 +#define PCLK_GPIO1_PMU 24 +#define PCLK_SGRF_PMU 25 +#define PCLK_NOC_PMU 26 +#define PCLK_I2C0_PMU 27 +#define PCLK_I2C4_PMU 28 +#define PCLK_I2C8_PMU 29 +#define PCLK_RKPWM_PMU 30 +#define PCLK_SPI3_PMU 31 +#define PCLK_TIMER_PMU 32 +#define PCLK_MAILBOX_PMU 33 +#define PCLK_UART4_PMU 34 +#define PCLK_WDT_M0_PMU 35 + +#define FCLK_CM0S_SRC_PMU 44 +#define FCLK_CM0S_PMU 45 +#define SCLK_CM0S_PMU 46 +#define HCLK_CM0S_PMU 47 +#define DCLK_CM0S_PMU 48 +#define PCLK_INTR_ARB_PMU 49 +#define HCLK_NOC_PMU 50 + +#define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1) + +/* soft-reset indices */ + +/* cru_softrst_con0 */ +#define SRST_CORE_L0 0 +#define SRST_CORE_B0 1 +#define SRST_CORE_PO_L0 2 +#define SRST_CORE_PO_B0 3 +#define SRST_L2_L 4 +#define SRST_L2_B 5 +#define SRST_ADB_L 6 +#define SRST_ADB_B 7 +#define SRST_A_CCI 8 +#define SRST_A_CCIM0_NOC 9 +#define SRST_A_CCIM1_NOC 10 +#define SRST_DBG_NOC 11 + +/* cru_softrst_con1 */ +#define SRST_CORE_L0_T 16 +#define SRST_CORE_L1 17 +#define SRST_CORE_L2 18 +#define SRST_CORE_L3 19 +#define SRST_CORE_PO_L0_T 20 +#define SRST_CORE_PO_L1 21 +#define SRST_CORE_PO_L2 22 +#define SRST_CORE_PO_L3 23 +#define SRST_A_ADB400_GIC2COREL 24 +#define SRST_A_ADB400_COREL2GIC 25 +#define SRST_P_DBG_L 26 +#define SRST_L2_L_T 28 +#define SRST_ADB_L_T 29 +#define SRST_A_RKPERF_L 30 +#define SRST_PVTM_CORE_L 31 + +/* cru_softrst_con2 */ +#define SRST_CORE_B0_T 32 +#define SRST_CORE_B1 33 +#define SRST_CORE_PO_B0_T 36 +#define SRST_CORE_PO_B1 37 +#define SRST_A_ADB400_GIC2COREB 40 +#define SRST_A_ADB400_COREB2GIC 41 +#define SRST_P_DBG_B 42 +#define SRST_L2_B_T 43 +#define SRST_ADB_B_T 45 +#define SRST_A_RKPERF_B 46 +#define SRST_PVTM_CORE_B 47 + +/* cru_softrst_con3 */ +#define SRST_A_CCI_T 50 +#define SRST_A_CCIM0_NOC_T 51 +#define SRST_A_CCIM1_NOC_T 52 +#define SRST_A_ADB400M_PD_CORE_B_T 53 +#define SRST_A_ADB400M_PD_CORE_L_T 54 +#define SRST_DBG_NOC_T 55 +#define SRST_DBG_CXCS 56 +#define SRST_CCI_TRACE 57 +#define SRST_P_CCI_GRF 58 + +/* cru_softrst_con4 */ +#define SRST_A_CENTER_MAIN_NOC 64 +#define SRST_A_CENTER_PERI_NOC 65 +#define SRST_P_CENTER_MAIN 66 +#define SRST_P_DDRMON 67 +#define SRST_P_CIC 68 +#define SRST_P_CENTER_SGRF 69 +#define SRST_DDR0_MSCH 70 +#define SRST_DDRCFG0_MSCH 71 +#define SRST_DDR0 72 +#define SRST_DDRPHY0 73 +#define SRST_DDR1_MSCH 74 +#define SRST_DDRCFG1_MSCH 75 +#define SRST_DDR1 76 +#define SRST_DDRPHY1 77 +#define SRST_DDR_CIC 78 +#define SRST_PVTM_DDR 79 + +/* cru_softrst_con5 */ +#define SRST_A_VCODEC_NOC 80 +#define SRST_A_VCODEC 81 +#define SRST_H_VCODEC_NOC 82 +#define SRST_H_VCODEC 83 +#define SRST_A_VDU_NOC 88 +#define SRST_A_VDU 89 +#define SRST_H_VDU_NOC 90 +#define SRST_H_VDU 91 +#define SRST_VDU_CORE 92 +#define SRST_VDU_CA 93 + +/* cru_softrst_con6 */ +#define SRST_A_IEP_NOC 96 +#define SRST_A_VOP_IEP 97 +#define SRST_A_IEP 98 +#define SRST_H_IEP_NOC 99 +#define SRST_H_IEP 100 +#define SRST_A_RGA_NOC 102 +#define SRST_A_RGA 103 +#define SRST_H_RGA_NOC 104 +#define SRST_H_RGA 105 +#define SRST_RGA_CORE 106 +#define SRST_EMMC_NOC 108 +#define SRST_EMMC 109 +#define SRST_EMMC_GRF 110 + +/* cru_softrst_con7 */ +#define SRST_A_PERIHP_NOC 112 +#define SRST_P_PERIHP_GRF 113 +#define SRST_H_PERIHP_NOC 114 +#define SRST_USBHOST0 115 +#define SRST_HOSTC0_AUX 116 +#define SRST_HOST0_ARB 117 +#define SRST_USBHOST1 118 +#define SRST_HOSTC1_AUX 119 +#define SRST_HOST1_ARB 120 +#define SRST_SDIO0 121 +#define SRST_SDMMC 122 +#define SRST_HSIC 123 +#define SRST_HSIC_AUX 124 +#define SRST_AHB1TOM 125 +#define SRST_P_PERIHP_NOC 126 +#define SRST_HSICPHY 127 + +/* cru_softrst_con8 */ +#define SRST_A_PCIE 128 +#define SRST_P_PCIE 129 +#define SRST_PCIE_CORE 130 +#define SRST_PCIE_MGMT 131 +#define SRST_PCIE_MGMT_STICKY 132 +#define SRST_PCIE_PIPE 133 +#define SRST_PCIE_PM 134 +#define SRST_PCIEPHY 135 +#define SRST_A_GMAC_NOC 136 +#define SRST_A_GMAC 137 +#define SRST_P_GMAC_NOC 138 +#define SRST_P_GMAC_GRF 140 +#define SRST_HSICPHY_POR 142 +#define SRST_HSICPHY_UTMI 143 + +/* cru_softrst_con9 */ +#define SRST_USB2PHY0_POR 144 +#define SRST_USB2PHY0_UTMI_PORT0 145 +#define SRST_USB2PHY0_UTMI_PORT1 146 +#define SRST_USB2PHY0_EHCIPHY 147 +#define SRST_UPHY0_PIPE_L00 148 +#define SRST_UPHY0 149 +#define SRST_UPHY0_TCPDPWRUP 150 +#define SRST_USB2PHY1_POR 152 +#define SRST_USB2PHY1_UTMI_PORT0 153 +#define SRST_USB2PHY1_UTMI_PORT1 154 +#define SRST_USB2PHY1_EHCIPHY 155 +#define SRST_UPHY1_PIPE_L00 156 +#define SRST_UPHY1 157 +#define SRST_UPHY1_TCPDPWRUP 158 + +/* cru_softrst_con10 */ +#define SRST_A_PERILP0_NOC 160 +#define SRST_A_DCF 161 +#define SRST_GIC500 162 +#define SRST_DMAC0_PERILP0 163 +#define SRST_DMAC1_PERILP0 164 +#define SRST_TZMA 165 +#define SRST_INTMEM 166 +#define SRST_ADB400_MST0 167 +#define SRST_ADB400_MST1 168 +#define SRST_ADB400_SLV0 169 +#define SRST_ADB400_SLV1 170 +#define SRST_H_PERILP0 171 +#define SRST_H_PERILP0_NOC 172 +#define SRST_ROM 173 +#define SRST_CRYPTO_S 174 +#define SRST_CRYPTO_M 175 + +/* cru_softrst_con11 */ +#define SRST_P_DCF 176 +#define SRST_CM0S_NOC 177 +#define SRST_CM0S 178 +#define SRST_CM0S_DBG 179 +#define SRST_CM0S_PO 180 +#define SRST_CRYPTO 181 +#define SRST_P_PERILP1_SGRF 182 +#define SRST_P_PERILP1_GRF 183 +#define SRST_CRYPTO1_S 184 +#define SRST_CRYPTO1_M 185 +#define SRST_CRYPTO1 186 +#define SRST_GIC_NOC 188 +#define SRST_SD_NOC 189 +#define SRST_SDIOAUDIO_BRG 190 + +/* cru_softrst_con12 */ +#define SRST_H_PERILP1 192 +#define SRST_H_PERILP1_NOC 193 +#define SRST_H_I2S0_8CH 194 +#define SRST_H_I2S1_8CH 195 +#define SRST_H_I2S2_8CH 196 +#define SRST_H_SPDIF_8CH 197 +#define SRST_P_PERILP1_NOC 198 +#define SRST_P_EFUSE_1024 199 +#define SRST_P_EFUSE_1024S 200 +#define SRST_P_I2C0 201 +#define SRST_P_I2C1 202 +#define SRST_P_I2C2 203 +#define SRST_P_I2C3 204 +#define SRST_P_I2C4 205 +#define SRST_P_I2C5 206 +#define SRST_P_MAILBOX0 207 + +/* cru_softrst_con13 */ +#define SRST_P_UART0 208 +#define SRST_P_UART1 209 +#define SRST_P_UART2 210 +#define SRST_P_UART3 211 +#define SRST_P_SARADC 212 +#define SRST_P_TSADC 213 +#define SRST_P_SPI0 214 +#define SRST_P_SPI1 215 +#define SRST_P_SPI2 216 +#define SRST_P_SPI3 217 +#define SRST_P_SPI4 218 +#define SRST_SPI0 219 +#define SRST_SPI1 220 +#define SRST_SPI2 221 +#define SRST_SPI3 222 +#define SRST_SPI4 223 + +/* cru_softrst_con14 */ +#define SRST_I2S0_8CH 224 +#define SRST_I2S1_8CH 225 +#define SRST_I2S2_8CH 226 +#define SRST_SPDIF_8CH 227 +#define SRST_UART0 228 +#define SRST_UART1 229 +#define SRST_UART2 230 +#define SRST_UART3 231 +#define SRST_TSADC 232 +#define SRST_I2C0 233 +#define SRST_I2C1 234 +#define SRST_I2C2 235 +#define SRST_I2C3 236 +#define SRST_I2C4 237 +#define SRST_I2C5 238 +#define SRST_SDIOAUDIO_NOC 239 + +/* cru_softrst_con15 */ +#define SRST_A_VIO_NOC 240 +#define SRST_A_HDCP_NOC 241 +#define SRST_A_HDCP 242 +#define SRST_H_HDCP_NOC 243 +#define SRST_H_HDCP 244 +#define SRST_P_HDCP_NOC 245 +#define SRST_P_HDCP 246 +#define SRST_P_HDMI_CTRL 247 +#define SRST_P_DP_CTRL 248 +#define SRST_S_DP_CTRL 249 +#define SRST_C_DP_CTRL 250 +#define SRST_P_MIPI_DSI0 251 +#define SRST_P_MIPI_DSI1 252 +#define SRST_DP_CORE 253 +#define SRST_DP_I2S 254 + +/* cru_softrst_con16 */ +#define SRST_GASKET 256 +#define SRST_VIO_GRF 258 +#define SRST_DPTX_SPDIF_REC 259 +#define SRST_HDMI_CTRL 260 +#define SRST_HDCP_CTRL 261 +#define SRST_A_ISP0_NOC 262 +#define SRST_A_ISP1_NOC 263 +#define SRST_H_ISP0_NOC 266 +#define SRST_H_ISP1_NOC 267 +#define SRST_H_ISP0 268 +#define SRST_H_ISP1 269 +#define SRST_ISP0 270 +#define SRST_ISP1 271 + +/* cru_softrst_con17 */ +#define SRST_A_VOP0_NOC 272 +#define SRST_A_VOP1_NOC 273 +#define SRST_A_VOP0 274 +#define SRST_A_VOP1 275 +#define SRST_H_VOP0_NOC 276 +#define SRST_H_VOP1_NOC 277 +#define SRST_H_VOP0 278 +#define SRST_H_VOP1 279 +#define SRST_D_VOP0 280 +#define SRST_D_VOP1 281 +#define SRST_VOP0_PWM 282 +#define SRST_VOP1_PWM 283 +#define SRST_P_EDP_NOC 284 +#define SRST_P_EDP_CTRL 285 + +/* cru_softrst_con18 */ +#define SRST_A_GPU 288 +#define SRST_A_GPU_NOC 289 +#define SRST_A_GPU_GRF 290 +#define SRST_PVTM_GPU 291 +#define SRST_A_USB3_NOC 292 +#define SRST_A_USB3_OTG0 293 +#define SRST_A_USB3_OTG1 294 +#define SRST_A_USB3_GRF 295 +#define SRST_PMU 296 + +/* cru_softrst_con19 */ +#define SRST_P_TIMER0_5 304 +#define SRST_TIMER0 305 +#define SRST_TIMER1 306 +#define SRST_TIMER2 307 +#define SRST_TIMER3 308 +#define SRST_TIMER4 309 +#define SRST_TIMER5 310 +#define SRST_P_TIMER6_11 311 +#define SRST_TIMER6 312 +#define SRST_TIMER7 313 +#define SRST_TIMER8 314 +#define SRST_TIMER9 315 +#define SRST_TIMER10 316 +#define SRST_TIMER11 317 +#define SRST_P_INTR_ARB_PMU 318 +#define SRST_P_ALIVE_SGRF 319 + +/* cru_softrst_con20 */ +#define SRST_P_GPIO2 320 +#define SRST_P_GPIO3 321 +#define SRST_P_GPIO4 322 +#define SRST_P_GRF 323 +#define SRST_P_ALIVE_NOC 324 +#define SRST_P_WDT0 325 +#define SRST_P_WDT1 326 +#define SRST_P_INTR_ARB 327 +#define SRST_P_UPHY0_DPTX 328 +#define SRST_P_UPHY0_APB 330 +#define SRST_P_UPHY0_TCPHY 332 +#define SRST_P_UPHY1_TCPHY 333 +#define SRST_P_UPHY0_TCPDCTRL 334 +#define SRST_P_UPHY1_TCPDCTRL 335 + +/* pmu soft-reset indices */ + +/* pmu_cru_softrst_con0 */ +#define SRST_P_NOC 0 +#define SRST_P_INTMEM 1 +#define SRST_H_CM0S 2 +#define SRST_H_CM0S_NOC 3 +#define SRST_DBG_CM0S 4 +#define SRST_PO_CM0S 5 +#define SRST_P_SPI6 6 +#define SRST_SPI6 7 +#define SRST_P_TIMER_0_1 8 +#define SRST_P_TIMER_0 9 +#define SRST_P_TIMER_1 10 +#define SRST_P_UART4 11 +#define SRST_UART4 12 +#define SRST_P_WDT 13 + +/* pmu_cru_softrst_con1 */ +#define SRST_P_I2C6 16 +#define SRST_P_I2C7 17 +#define SRST_P_I2C8 18 +#define SRST_P_MAILBOX 19 +#define SRST_P_RKPWM 20 +#define SRST_P_PMUGRF 21 +#define SRST_P_SGRF 22 +#define SRST_P_GPIO0 23 +#define SRST_P_GPIO1 24 +#define SRST_P_CRU 25 +#define SRST_P_INTR 26 +#define SRST_PVTM 27 +#define SRST_I2C6 28 +#define SRST_I2C7 29 +#define SRST_I2C8 30 + +#endif diff --git a/include/dt-bindings/clock/tegra186-clock.h b/include/dt-bindings/clock/tegra186-clock.h new file mode 100644 index 0000000..f73d320 --- /dev/null +++ b/include/dt-bindings/clock/tegra186-clock.h @@ -0,0 +1,940 @@ +/** @file */ + +#ifndef _MACH_T186_CLK_T186_H +#define _MACH_T186_CLK_T186_H + +/** + * @defgroup clock_ids Clock Identifiers + * @{ + * @defgroup extern_input external input clocks + * @{ + * @def TEGRA186_CLK_OSC + * @def TEGRA186_CLK_CLK_32K + * @def TEGRA186_CLK_DTV_INPUT + * @def TEGRA186_CLK_SOR0_PAD_CLKOUT + * @def TEGRA186_CLK_SOR1_PAD_CLKOUT + * @def TEGRA186_CLK_I2S1_SYNC_INPUT + * @def TEGRA186_CLK_I2S2_SYNC_INPUT + * @def TEGRA186_CLK_I2S3_SYNC_INPUT + * @def TEGRA186_CLK_I2S4_SYNC_INPUT + * @def TEGRA186_CLK_I2S5_SYNC_INPUT + * @def TEGRA186_CLK_I2S6_SYNC_INPUT + * @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT + * @} + * + * @defgroup extern_output external output clocks + * @{ + * @def TEGRA186_CLK_EXTPERIPH1 + * @def TEGRA186_CLK_EXTPERIPH2 + * @def TEGRA186_CLK_EXTPERIPH3 + * @def TEGRA186_CLK_EXTPERIPH4 + * @} + * + * @defgroup display_clks display related clocks + * @{ + * @def TEGRA186_CLK_CEC + * @def TEGRA186_CLK_DSIC + * @def TEGRA186_CLK_DSIC_LP + * @def TEGRA186_CLK_DSID + * @def TEGRA186_CLK_DSID_LP + * @def TEGRA186_CLK_DPAUX1 + * @def TEGRA186_CLK_DPAUX + * @def TEGRA186_CLK_HDA2HDMICODEC + * @def TEGRA186_CLK_NVDISPLAY_DISP + * @def TEGRA186_CLK_NVDISPLAY_DSC + * @def TEGRA186_CLK_NVDISPLAY_P0 + * @def TEGRA186_CLK_NVDISPLAY_P1 + * @def TEGRA186_CLK_NVDISPLAY_P2 + * @def TEGRA186_CLK_NVDISPLAYHUB + * @def TEGRA186_CLK_SOR_SAFE + * @def TEGRA186_CLK_SOR0 + * @def TEGRA186_CLK_SOR0_OUT + * @def TEGRA186_CLK_SOR1 + * @def TEGRA186_CLK_SOR1_OUT + * @def TEGRA186_CLK_DSI + * @def TEGRA186_CLK_MIPI_CAL + * @def TEGRA186_CLK_DSIA_LP + * @def TEGRA186_CLK_DSIB + * @def TEGRA186_CLK_DSIB_LP + * @} + * + * @defgroup camera_clks camera related clocks + * @{ + * @def TEGRA186_CLK_NVCSI + * @def TEGRA186_CLK_NVCSILP + * @def TEGRA186_CLK_VI + * @} + * + * @defgroup audio_clks audio related clocks + * @{ + * @def TEGRA186_CLK_ACLK + * @def TEGRA186_CLK_ADSP + * @def TEGRA186_CLK_ADSPNEON + * @def TEGRA186_CLK_AHUB + * @def TEGRA186_CLK_APE + * @def TEGRA186_CLK_APB2APE + * @def TEGRA186_CLK_AUD_MCLK + * @def TEGRA186_CLK_DMIC1 + * @def TEGRA186_CLK_DMIC2 + * @def TEGRA186_CLK_DMIC3 + * @def TEGRA186_CLK_DMIC4 + * @def TEGRA186_CLK_DSPK1 + * @def TEGRA186_CLK_DSPK2 + * @def TEGRA186_CLK_HDA + * @def TEGRA186_CLK_HDA2CODEC_2X + * @def TEGRA186_CLK_I2S1 + * @def TEGRA186_CLK_I2S2 + * @def TEGRA186_CLK_I2S3 + * @def TEGRA186_CLK_I2S4 + * @def TEGRA186_CLK_I2S5 + * @def TEGRA186_CLK_I2S6 + * @def TEGRA186_CLK_MAUD + * @def TEGRA186_CLK_PLL_A_OUT0 + * @def TEGRA186_CLK_SPDIF_DOUBLER + * @def TEGRA186_CLK_SPDIF_IN + * @def TEGRA186_CLK_SPDIF_OUT + * @def TEGRA186_CLK_SYNC_DMIC1 + * @def TEGRA186_CLK_SYNC_DMIC2 + * @def TEGRA186_CLK_SYNC_DMIC3 + * @def TEGRA186_CLK_SYNC_DMIC4 + * @def TEGRA186_CLK_SYNC_DMIC5 + * @def TEGRA186_CLK_SYNC_DSPK1 + * @def TEGRA186_CLK_SYNC_DSPK2 + * @def TEGRA186_CLK_SYNC_I2S1 + * @def TEGRA186_CLK_SYNC_I2S2 + * @def TEGRA186_CLK_SYNC_I2S3 + * @def TEGRA186_CLK_SYNC_I2S4 + * @def TEGRA186_CLK_SYNC_I2S5 + * @def TEGRA186_CLK_SYNC_I2S6 + * @def TEGRA186_CLK_SYNC_SPDIF + * @} + * + * @defgroup uart_clks UART clocks + * @{ + * @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL + * @def TEGRA186_CLK_UARTA + * @def TEGRA186_CLK_UARTB + * @def TEGRA186_CLK_UARTC + * @def TEGRA186_CLK_UARTD + * @def TEGRA186_CLK_UARTE + * @def TEGRA186_CLK_UARTF + * @def TEGRA186_CLK_UARTG + * @def TEGRA186_CLK_UART_FST_MIPI_CAL + * @} + * + * @defgroup i2c_clks I2C clocks + * @{ + * @def TEGRA186_CLK_AON_I2C_SLOW + * @def TEGRA186_CLK_I2C1 + * @def TEGRA186_CLK_I2C2 + * @def TEGRA186_CLK_I2C3 + * @def TEGRA186_CLK_I2C4 + * @def TEGRA186_CLK_I2C5 + * @def TEGRA186_CLK_I2C6 + * @def TEGRA186_CLK_I2C8 + * @def TEGRA186_CLK_I2C9 + * @def TEGRA186_CLK_I2C1 + * @def TEGRA186_CLK_I2C12 + * @def TEGRA186_CLK_I2C13 + * @def TEGRA186_CLK_I2C14 + * @def TEGRA186_CLK_I2C_SLOW + * @def TEGRA186_CLK_VI_I2C + * @} + * + * @defgroup spi_clks SPI clocks + * @{ + * @def TEGRA186_CLK_SPI1 + * @def TEGRA186_CLK_SPI2 + * @def TEGRA186_CLK_SPI3 + * @def TEGRA186_CLK_SPI4 + * @} + * + * @defgroup storage storage related clocks + * @{ + * @def TEGRA186_CLK_SATA + * @def TEGRA186_CLK_SATA_OOB + * @def TEGRA186_CLK_SATA_IOBIST + * @def TEGRA186_CLK_SDMMC_LEGACY_TM + * @def TEGRA186_CLK_SDMMC1 + * @def TEGRA186_CLK_SDMMC2 + * @def TEGRA186_CLK_SDMMC3 + * @def TEGRA186_CLK_SDMMC4 + * @def TEGRA186_CLK_QSPI + * @def TEGRA186_CLK_QSPI_OUT + * @def TEGRA186_CLK_UFSDEV_REF + * @def TEGRA186_CLK_UFSHC + * @} + * + * @defgroup pwm_clks PWM clocks + * @{ + * @def TEGRA186_CLK_PWM1 + * @def TEGRA186_CLK_PWM2 + * @def TEGRA186_CLK_PWM3 + * @def TEGRA186_CLK_PWM4 + * @def TEGRA186_CLK_PWM5 + * @def TEGRA186_CLK_PWM6 + * @def TEGRA186_CLK_PWM7 + * @def TEGRA186_CLK_PWM8 + * @} + * + * @defgroup plls PLLs and related clocks + * @{ + * @def TEGRA186_CLK_PLLREFE_OUT_GATED + * @def TEGRA186_CLK_PLLREFE_OUT1 + * @def TEGRA186_CLK_PLLD_OUT1 + * @def TEGRA186_CLK_PLLP_OUT0 + * @def TEGRA186_CLK_PLLP_OUT5 + * @def TEGRA186_CLK_PLLA + * @def TEGRA186_CLK_PLLE_PWRSEQ + * @def TEGRA186_CLK_PLLA_OUT1 + * @def TEGRA186_CLK_PLLREFE_REF + * @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ + * @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ + * @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH + * @def TEGRA186_CLK_PLLREFE_PEX + * @def TEGRA186_CLK_PLLREFE_IDDQ + * @def TEGRA186_CLK_PLLC_OUT_AON + * @def TEGRA186_CLK_PLLC_OUT_ISP + * @def TEGRA186_CLK_PLLC_OUT_VE + * @def TEGRA186_CLK_PLLC4_OUT + * @def TEGRA186_CLK_PLLREFE_OUT + * @def TEGRA186_CLK_PLLREFE_PLL_REF + * @def TEGRA186_CLK_PLLE + * @def TEGRA186_CLK_PLLC + * @def TEGRA186_CLK_PLLP + * @def TEGRA186_CLK_PLLD + * @def TEGRA186_CLK_PLLD2 + * @def TEGRA186_CLK_PLLREFE_VCO + * @def TEGRA186_CLK_PLLC2 + * @def TEGRA186_CLK_PLLC3 + * @def TEGRA186_CLK_PLLDP + * @def TEGRA186_CLK_PLLC4_VCO + * @def TEGRA186_CLK_PLLA1 + * @def TEGRA186_CLK_PLLNVCSI + * @def TEGRA186_CLK_PLLDISPHUB + * @def TEGRA186_CLK_PLLD3 + * @def TEGRA186_CLK_PLLBPMPCAM + * @def TEGRA186_CLK_PLLAON + * @def TEGRA186_CLK_PLLU + * @def TEGRA186_CLK_PLLC4_VCO_DIV2 + * @def TEGRA186_CLK_PLL_REF + * @def TEGRA186_CLK_PLLREFE_OUT1_DIV5 + * @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ + * @def TEGRA186_CLK_PLL_U_48M + * @def TEGRA186_CLK_PLL_U_480M + * @def TEGRA186_CLK_PLLC4_OUT0 + * @def TEGRA186_CLK_PLLC4_OUT1 + * @def TEGRA186_CLK_PLLC4_OUT2 + * @def TEGRA186_CLK_PLLC4_OUT_MUX + * @def TEGRA186_CLK_DFLLDISP_DIV + * @def TEGRA186_CLK_PLLDISPHUB_DIV + * @def TEGRA186_CLK_PLLP_DIV8 + * @} + * + * @defgroup nafll_clks NAFLL clock sources + * @{ + * @def TEGRA186_CLK_NAFLL_AXI_CBB + * @def TEGRA186_CLK_NAFLL_BCPU + * @def TEGRA186_CLK_NAFLL_BPMP + * @def TEGRA186_CLK_NAFLL_DISP + * @def TEGRA186_CLK_NAFLL_GPU + * @def TEGRA186_CLK_NAFLL_ISP + * @def TEGRA186_CLK_NAFLL_MCPU + * @def TEGRA186_CLK_NAFLL_NVDEC + * @def TEGRA186_CLK_NAFLL_NVENC + * @def TEGRA186_CLK_NAFLL_NVJPG + * @def TEGRA186_CLK_NAFLL_SCE + * @def TEGRA186_CLK_NAFLL_SE + * @def TEGRA186_CLK_NAFLL_TSEC + * @def TEGRA186_CLK_NAFLL_TSECB + * @def TEGRA186_CLK_NAFLL_VI + * @def TEGRA186_CLK_NAFLL_VIC + * @} + * + * @defgroup mphy MPHY related clocks + * @{ + * @def TEGRA186_CLK_MPHY_L0_RX_SYMB + * @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT + * @def TEGRA186_CLK_MPHY_L0_TX_SYMB + * @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT + * @def TEGRA186_CLK_MPHY_L0_RX_ANA + * @def TEGRA186_CLK_MPHY_L1_RX_ANA + * @def TEGRA186_CLK_MPHY_IOBIST + * @def TEGRA186_CLK_MPHY_TX_1MHZ_REF + * @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED + * @} + * + * @defgroup eavb EAVB related clocks + * @{ + * @def TEGRA186_CLK_EQOS_AXI + * @def TEGRA186_CLK_EQOS_PTP_REF + * @def TEGRA186_CLK_EQOS_RX + * @def TEGRA186_CLK_EQOS_RX_INPUT + * @def TEGRA186_CLK_EQOS_TX + * @} + * + * @defgroup usb USB related clocks + * @{ + * @def TEGRA186_CLK_PEX_USB_PAD0_MGMT + * @def TEGRA186_CLK_PEX_USB_PAD1_MGMT + * @def TEGRA186_CLK_HSIC_TRK + * @def TEGRA186_CLK_USB2_TRK + * @def TEGRA186_CLK_USB2_HSIC_TRK + * @def TEGRA186_CLK_XUSB_CORE_SS + * @def TEGRA186_CLK_XUSB_CORE_DEV + * @def TEGRA186_CLK_XUSB_FALCON + * @def TEGRA186_CLK_XUSB_FS + * @def TEGRA186_CLK_XUSB + * @def TEGRA186_CLK_XUSB_DEV + * @def TEGRA186_CLK_XUSB_HOST + * @def TEGRA186_CLK_XUSB_SS + * @} + * + * @defgroup bigblock compute block related clocks + * @{ + * @def TEGRA186_CLK_GPCCLK + * @def TEGRA186_CLK_GPC2CLK + * @def TEGRA186_CLK_GPU + * @def TEGRA186_CLK_HOST1X + * @def TEGRA186_CLK_ISP + * @def TEGRA186_CLK_NVDEC + * @def TEGRA186_CLK_NVENC + * @def TEGRA186_CLK_NVJPG + * @def TEGRA186_CLK_SE + * @def TEGRA186_CLK_TSEC + * @def TEGRA186_CLK_TSECB + * @def TEGRA186_CLK_VIC + * @} + * + * @defgroup can CAN bus related clocks + * @{ + * @def TEGRA186_CLK_CAN1 + * @def TEGRA186_CLK_CAN1_HOST + * @def TEGRA186_CLK_CAN2 + * @def TEGRA186_CLK_CAN2_HOST + * @} + * + * @defgroup system basic system clocks + * @{ + * @def TEGRA186_CLK_ACTMON + * @def TEGRA186_CLK_AON_APB + * @def TEGRA186_CLK_AON_CPU_NIC + * @def TEGRA186_CLK_AON_NIC + * @def TEGRA186_CLK_AXI_CBB + * @def TEGRA186_CLK_BPMP_APB + * @def TEGRA186_CLK_BPMP_CPU_NIC + * @def TEGRA186_CLK_BPMP_NIC_RATE + * @def TEGRA186_CLK_CLK_M + * @def TEGRA186_CLK_EMC + * @def TEGRA186_CLK_MSS_ENCRYPT + * @def TEGRA186_CLK_SCE_APB + * @def TEGRA186_CLK_SCE_CPU_NIC + * @def TEGRA186_CLK_SCE_NIC + * @def TEGRA186_CLK_TSC + * @} + * + * @defgroup pcie_clks PCIe related clocks + * @{ + * @def TEGRA186_CLK_AFI + * @def TEGRA186_CLK_PCIE + * @def TEGRA186_CLK_PCIE2_IOBIST + * @def TEGRA186_CLK_PCIERX0 + * @def TEGRA186_CLK_PCIERX1 + * @def TEGRA186_CLK_PCIERX2 + * @def TEGRA186_CLK_PCIERX3 + * @def TEGRA186_CLK_PCIERX4 + * @} + */ + +/** @brief output of gate CLK_ENB_FUSE */ +#define TEGRA186_CLK_FUSE 0 +/** + * @brief It's not what you think + * @details output of gate CLK_ENB_GPU. This output connects to the GPU + * pwrclk. @warning: This is almost certainly not the clock you think + * it is. If you're looking for the clock of the graphics engine, see + * TEGRA186_GPCCLK + */ +#define TEGRA186_CLK_GPU 1 +/** @brief output of gate CLK_ENB_PCIE */ +#define TEGRA186_CLK_PCIE 3 +/** @brief output of the divider IPFS_CLK_DIVISOR */ +#define TEGRA186_CLK_AFI 4 +/** @brief output of gate CLK_ENB_PCIE2_IOBIST */ +#define TEGRA186_CLK_PCIE2_IOBIST 5 +/** @brief output of gate CLK_ENB_PCIERX0*/ +#define TEGRA186_CLK_PCIERX0 6 +/** @brief output of gate CLK_ENB_PCIERX1*/ +#define TEGRA186_CLK_PCIERX1 7 +/** @brief output of gate CLK_ENB_PCIERX2*/ +#define TEGRA186_CLK_PCIERX2 8 +/** @brief output of gate CLK_ENB_PCIERX3*/ +#define TEGRA186_CLK_PCIERX3 9 +/** @brief output of gate CLK_ENB_PCIERX4*/ +#define TEGRA186_CLK_PCIERX4 10 +/** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */ +#define TEGRA186_CLK_PLLC_OUT_ISP 11 +/** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */ +#define TEGRA186_CLK_PLLC_OUT_VE 12 +/** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */ +#define TEGRA186_CLK_PLLC_OUT_AON 13 +/** @brief output of gate CLK_ENB_SOR_SAFE */ +#define TEGRA186_CLK_SOR_SAFE 39 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ +#define TEGRA186_CLK_I2S2 42 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ +#define TEGRA186_CLK_I2S3 43 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */ +#define TEGRA186_CLK_SPDIF_IN 44 +/** @brief output of gate CLK_ENB_SPDIF_DOUBLER */ +#define TEGRA186_CLK_SPDIF_DOUBLER 45 +/** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */ +#define TEGRA186_CLK_SPI3 46 +/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */ +#define TEGRA186_CLK_I2C1 47 +/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */ +#define TEGRA186_CLK_I2C5 48 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */ +#define TEGRA186_CLK_SPI1 49 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */ +#define TEGRA186_CLK_ISP 50 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */ +#define TEGRA186_CLK_VI 51 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */ +#define TEGRA186_CLK_SDMMC1 52 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */ +#define TEGRA186_CLK_SDMMC2 53 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ +#define TEGRA186_CLK_SDMMC4 54 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ +#define TEGRA186_CLK_UARTA 55 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */ +#define TEGRA186_CLK_UARTB 56 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ +#define TEGRA186_CLK_HOST1X 57 +/** + * @brief controls the EMC clock frequency. + * @details Doing a clk_set_rate on this clock will select the + * appropriate clock source, program the source rate and execute a + * specific sequence to switch to the new clock source for both memory + * controllers. This can be used to control the balance between memory + * throughput and memory controller power. + */ +#define TEGRA186_CLK_EMC 58 +/* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */ +#define TEGRA186_CLK_EXTPERIPH4 73 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */ +#define TEGRA186_CLK_SPI4 74 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ +#define TEGRA186_CLK_I2C3 75 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */ +#define TEGRA186_CLK_SDMMC3 76 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */ +#define TEGRA186_CLK_UARTD 77 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ +#define TEGRA186_CLK_I2S1 79 +/** output of gate CLK_ENB_DTV */ +#define TEGRA186_CLK_DTV 80 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */ +#define TEGRA186_CLK_TSEC 81 +/** @brief output of gate CLK_ENB_DP2 */ +#define TEGRA186_CLK_DP2 82 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ +#define TEGRA186_CLK_I2S4 84 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ +#define TEGRA186_CLK_I2S5 85 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ +#define TEGRA186_CLK_I2C4 86 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ +#define TEGRA186_CLK_AHUB 87 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */ +#define TEGRA186_CLK_HDA2CODEC_2X 88 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */ +#define TEGRA186_CLK_EXTPERIPH1 89 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */ +#define TEGRA186_CLK_EXTPERIPH2 90 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */ +#define TEGRA186_CLK_EXTPERIPH3 91 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */ +#define TEGRA186_CLK_I2C_SLOW 92 +/** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ +#define TEGRA186_CLK_SOR1 93 +/** @brief output of gate CLK_ENB_CEC */ +#define TEGRA186_CLK_CEC 94 +/** @brief output of gate CLK_ENB_DPAUX1 */ +#define TEGRA186_CLK_DPAUX1 95 +/** @brief output of gate CLK_ENB_DPAUX */ +#define TEGRA186_CLK_DPAUX 96 +/** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ +#define TEGRA186_CLK_SOR0 97 +/** @brief output of gate CLK_ENB_HDA2HDMICODEC */ +#define TEGRA186_CLK_HDA2HDMICODEC 98 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */ +#define TEGRA186_CLK_SATA 99 +/** @brief output of gate CLK_ENB_SATA_OOB */ +#define TEGRA186_CLK_SATA_OOB 100 +/** @brief output of gate CLK_ENB_SATA_IOBIST */ +#define TEGRA186_CLK_SATA_IOBIST 101 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */ +#define TEGRA186_CLK_HDA 102 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */ +#define TEGRA186_CLK_SE 103 +/** @brief output of gate CLK_ENB_APB2APE */ +#define TEGRA186_CLK_APB2APE 104 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ +#define TEGRA186_CLK_APE 105 +/** @brief output of gate CLK_ENB_IQC1 */ +#define TEGRA186_CLK_IQC1 106 +/** @brief output of gate CLK_ENB_IQC2 */ +#define TEGRA186_CLK_IQC2 107 +/** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */ +#define TEGRA186_CLK_PLLREFE_OUT 108 +/** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */ +#define TEGRA186_CLK_PLLREFE_PLL_REF 109 +/** @brief output of gate CLK_ENB_PLLC4_OUT */ +#define TEGRA186_CLK_PLLC4_OUT 110 +/** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB 111 +/** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_DEV 112 +/** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_HOST 113 +/** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_SS 114 +/** @brief output of gate CLK_ENB_DSI */ +#define TEGRA186_CLK_DSI 115 +/** @brief output of gate CLK_ENB_MIPI_CAL */ +#define TEGRA186_CLK_MIPI_CAL 116 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */ +#define TEGRA186_CLK_DSIA_LP 117 +/** @brief output of gate CLK_ENB_DSIB */ +#define TEGRA186_CLK_DSIB 118 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */ +#define TEGRA186_CLK_DSIB_LP 119 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ +#define TEGRA186_CLK_DMIC1 122 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ +#define TEGRA186_CLK_DMIC2 123 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ +#define TEGRA186_CLK_AUD_MCLK 124 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ +#define TEGRA186_CLK_I2C6 125 +/**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */ +#define TEGRA186_CLK_UART_FST_MIPI_CAL 126 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ +#define TEGRA186_CLK_VIC 127 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */ +#define TEGRA186_CLK_SDMMC_LEGACY_TM 128 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */ +#define TEGRA186_CLK_NVDEC 129 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */ +#define TEGRA186_CLK_NVJPG 130 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */ +#define TEGRA186_CLK_NVENC 131 +/** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ +#define TEGRA186_CLK_QSPI 132 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */ +#define TEGRA186_CLK_VI_I2C 133 +/** @brief output of gate CLK_ENB_HSIC_TRK */ +#define TEGRA186_CLK_HSIC_TRK 134 +/** @brief output of gate CLK_ENB_USB2_TRK */ +#define TEGRA186_CLK_USB2_TRK 135 +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */ +#define TEGRA186_CLK_MAUD 136 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */ +#define TEGRA186_CLK_TSECB 137 +/** @brief output of gate CLK_ENB_ADSP */ +#define TEGRA186_CLK_ADSP 138 +/** @brief output of gate CLK_ENB_ADSPNEON */ +#define TEGRA186_CLK_ADSPNEON 139 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */ +#define TEGRA186_CLK_MPHY_L0_RX_SYMB 140 +/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */ +#define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */ +#define TEGRA186_CLK_MPHY_L0_TX_SYMB 142 +/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */ +#define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143 +/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */ +#define TEGRA186_CLK_MPHY_L0_RX_ANA 144 +/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */ +#define TEGRA186_CLK_MPHY_L1_RX_ANA 145 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */ +#define TEGRA186_CLK_MPHY_IOBIST 146 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */ +#define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */ +#define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */ +#define TEGRA186_CLK_AXI_CBB 149 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ +#define TEGRA186_CLK_DMIC3 150 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ +#define TEGRA186_CLK_DMIC4 151 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ +#define TEGRA186_CLK_DSPK1 152 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ +#define TEGRA186_CLK_DSPK2 153 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ +#define TEGRA186_CLK_I2S6 154 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */ +#define TEGRA186_CLK_NVDISPLAY_P0 155 +/** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */ +#define TEGRA186_CLK_NVDISPLAY_DISP 156 +/** @brief output of gate CLK_ENB_NVDISPLAY_DSC */ +#define TEGRA186_CLK_NVDISPLAY_DSC 157 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */ +#define TEGRA186_CLK_NVDISPLAYHUB 158 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */ +#define TEGRA186_CLK_NVDISPLAY_P1 159 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */ +#define TEGRA186_CLK_NVDISPLAY_P2 160 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */ +#define TEGRA186_CLK_TACH 166 +/** @brief output of gate CLK_ENB_EQOS */ +#define TEGRA186_CLK_EQOS_AXI 167 +/** @brief output of gate CLK_ENB_EQOS_RX */ +#define TEGRA186_CLK_EQOS_RX 168 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */ +#define TEGRA186_CLK_UFSHC 178 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */ +#define TEGRA186_CLK_UFSDEV_REF 179 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */ +#define TEGRA186_CLK_NVCSI 180 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */ +#define TEGRA186_CLK_NVCSILP 181 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ +#define TEGRA186_CLK_I2C7 182 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ +#define TEGRA186_CLK_I2C9 183 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */ +#define TEGRA186_CLK_I2C12 184 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */ +#define TEGRA186_CLK_I2C13 185 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */ +#define TEGRA186_CLK_I2C14 186 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ +#define TEGRA186_CLK_PWM1 187 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ +#define TEGRA186_CLK_PWM2 188 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ +#define TEGRA186_CLK_PWM3 189 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ +#define TEGRA186_CLK_PWM5 190 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ +#define TEGRA186_CLK_PWM6 191 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ +#define TEGRA186_CLK_PWM7 192 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ +#define TEGRA186_CLK_PWM8 193 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */ +#define TEGRA186_CLK_UARTE 194 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */ +#define TEGRA186_CLK_UARTF 195 +/** @deprecated */ +#define TEGRA186_CLK_DBGAPB 196 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */ +#define TEGRA186_CLK_BPMP_CPU_NIC 197 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */ +#define TEGRA186_CLK_BPMP_APB 199 +/** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */ +#define TEGRA186_CLK_ACTMON 201 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */ +#define TEGRA186_CLK_AON_CPU_NIC 208 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */ +#define TEGRA186_CLK_CAN1 210 +/** @brief output of gate CLK_ENB_CAN1_HOST */ +#define TEGRA186_CLK_CAN1_HOST 211 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */ +#define TEGRA186_CLK_CAN2 212 +/** @brief output of gate CLK_ENB_CAN2_HOST */ +#define TEGRA186_CLK_CAN2_HOST 213 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */ +#define TEGRA186_CLK_AON_APB 214 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */ +#define TEGRA186_CLK_UARTC 215 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */ +#define TEGRA186_CLK_UARTG 216 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */ +#define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ +#define TEGRA186_CLK_I2C2 218 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ +#define TEGRA186_CLK_I2C8 219 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */ +#define TEGRA186_CLK_I2C10 220 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */ +#define TEGRA186_CLK_AON_I2C_SLOW 221 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */ +#define TEGRA186_CLK_SPI2 222 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */ +#define TEGRA186_CLK_DMIC5 223 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */ +#define TEGRA186_CLK_AON_TOUCH 224 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ +#define TEGRA186_CLK_PWM4 225 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */ +#define TEGRA186_CLK_TSC 226 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */ +#define TEGRA186_CLK_MSS_ENCRYPT 227 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */ +#define TEGRA186_CLK_SCE_CPU_NIC 228 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */ +#define TEGRA186_CLK_SCE_APB 230 +/** @brief output of gate CLK_ENB_DSIC */ +#define TEGRA186_CLK_DSIC 231 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */ +#define TEGRA186_CLK_DSIC_LP 232 +/** @brief output of gate CLK_ENB_DSID */ +#define TEGRA186_CLK_DSID 233 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */ +#define TEGRA186_CLK_DSID_LP 234 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */ +#define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */ +#define TEGRA186_CLK_SPDIF_OUT 238 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */ +#define TEGRA186_CLK_EQOS_PTP_REF 239 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */ +#define TEGRA186_CLK_EQOS_TX 240 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */ +#define TEGRA186_CLK_USB2_HSIC_TRK 241 +/** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_CORE_SS 242 +/** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_CORE_DEV 243 +/** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_FALCON 244 +/** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */ +#define TEGRA186_CLK_XUSB_FS 245 +/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ +#define TEGRA186_CLK_PLL_A_OUT0 246 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ +#define TEGRA186_CLK_SYNC_I2S1 247 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ +#define TEGRA186_CLK_SYNC_I2S2 248 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ +#define TEGRA186_CLK_SYNC_I2S3 249 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ +#define TEGRA186_CLK_SYNC_I2S4 250 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ +#define TEGRA186_CLK_SYNC_I2S5 251 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ +#define TEGRA186_CLK_SYNC_I2S6 252 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ +#define TEGRA186_CLK_SYNC_DSPK1 253 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ +#define TEGRA186_CLK_SYNC_DSPK2 254 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ +#define TEGRA186_CLK_SYNC_DMIC1 255 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ +#define TEGRA186_CLK_SYNC_DMIC2 256 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ +#define TEGRA186_CLK_SYNC_DMIC3 257 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ +#define TEGRA186_CLK_SYNC_DMIC4 259 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */ +#define TEGRA186_CLK_SYNC_SPDIF 260 +/** @brief output of gate CLK_ENB_PLLREFE_OUT */ +#define TEGRA186_CLK_PLLREFE_OUT_GATED 261 +/** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs: + * * VCO/pdiv defined by this clock object + * * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT + */ +#define TEGRA186_CLK_PLLREFE_OUT1 262 +#define TEGRA186_CLK_PLLD_OUT1 267 +/** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */ +#define TEGRA186_CLK_PLLP_OUT0 269 +/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */ +#define TEGRA186_CLK_PLLP_OUT5 270 +/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ +#define TEGRA186_CLK_PLLA 271 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */ +#define TEGRA186_CLK_ACLK 273 +/** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */ +#define TEGRA186_CLK_PLL_U_48M 274 +/** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */ +#define TEGRA186_CLK_PLL_U_480M 275 +/** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */ +#define TEGRA186_CLK_PLLC4_OUT0 276 +/** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */ +#define TEGRA186_CLK_PLLC4_OUT1 277 +/** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */ +#define TEGRA186_CLK_PLLC4_OUT2 278 +/** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */ +#define TEGRA186_CLK_PLLC4_OUT_MUX 279 +/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ +#define TEGRA186_CLK_DFLLDISP_DIV 284 +/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ +#define TEGRA186_CLK_PLLDISPHUB_DIV 285 +/** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */ +#define TEGRA186_CLK_PLLP_DIV8 286 +/** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */ +#define TEGRA186_CLK_BPMP_NIC 287 +/** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */ +#define TEGRA186_CLK_PLL_A_OUT1 288 +/** @deprecated */ +#define TEGRA186_CLK_GPC2CLK 289 +/** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */ +#define TEGRA186_CLK_KFUSE 293 +/** + * @brief controls the PLLE hardware sequencer. + * @details This clock only has enable and disable methods. When the + * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by + * hw based on the control signals from the PCIe, SATA and XUSB + * clocks. When the PLLE hw sequencer is disabled, the state of PLLE + * is controlled by sw using clk_enable/clk_disable on + * TEGRA186_CLK_PLLE. + */ +#define TEGRA186_CLK_PLLE_PWRSEQ 294 +/** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */ +#define TEGRA186_CLK_PLLREFE_REF 295 +/** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ +#define TEGRA186_CLK_SOR0_OUT 296 +/** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ +#define TEGRA186_CLK_SOR1_OUT 297 +/** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */ +#define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298 +/** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */ +#define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */ +#define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302 +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */ +#define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303 +/** @brief controls the UPHY_PLL0 hardware sqeuencer */ +#define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304 +/** @brief controls the UPHY_PLL1 hardware sqeuencer */ +#define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305 +/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */ +#define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306 +/** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */ +#define TEGRA186_CLK_PLLREFE_PEX 307 +/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */ +#define TEGRA186_CLK_PLLREFE_IDDQ 308 +/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ +#define TEGRA186_CLK_QSPI_OUT 309 +/** + * @brief GPC2CLK-div-2 + * @details fixed /2 divider. Output frequency is + * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the + * frequency at which the GPU graphics engine runs. */ +#define TEGRA186_CLK_GPCCLK 310 +/** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */ +#define TEGRA186_CLK_AON_NIC 450 +/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */ +#define TEGRA186_CLK_SCE_NIC 451 +/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */ +#define TEGRA186_CLK_PLLE 512 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */ +#define TEGRA186_CLK_PLLC 513 +/** Fixed 408MHz PLL for use by peripheral clocks */ +#define TEGRA186_CLK_PLLP 516 +/** @deprecated */ +#define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */ +#define TEGRA186_CLK_PLLD 518 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */ +#define TEGRA186_CLK_PLLD2 519 +/** + * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE. + * @details Note that this clock only controls the VCO output, before + * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more + * information. + */ +#define TEGRA186_CLK_PLLREFE_VCO 520 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */ +#define TEGRA186_CLK_PLLC2 521 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */ +#define TEGRA186_CLK_PLLC3 522 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */ +#define TEGRA186_CLK_PLLDP 523 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ +#define TEGRA186_CLK_PLLC4_VCO 524 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */ +#define TEGRA186_CLK_PLLA1 525 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */ +#define TEGRA186_CLK_PLLNVCSI 526 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */ +#define TEGRA186_CLK_PLLDISPHUB 527 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */ +#define TEGRA186_CLK_PLLD3 528 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */ +#define TEGRA186_CLK_PLLBPMPCAM 531 +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */ +#define TEGRA186_CLK_PLLAON 532 +/** Fixed frequency 960MHz PLL for USB and EAVB */ +#define TEGRA186_CLK_PLLU 533 +/** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */ +#define TEGRA186_CLK_PLLC4_VCO_DIV2 535 +/** @brief NAFLL clock source for AXI_CBB */ +#define TEGRA186_CLK_NAFLL_AXI_CBB 564 +/** @brief NAFLL clock source for BPMP */ +#define TEGRA186_CLK_NAFLL_BPMP 565 +/** @brief NAFLL clock source for ISP */ +#define TEGRA186_CLK_NAFLL_ISP 566 +/** @brief NAFLL clock source for NVDEC */ +#define TEGRA186_CLK_NAFLL_NVDEC 567 +/** @brief NAFLL clock source for NVENC */ +#define TEGRA186_CLK_NAFLL_NVENC 568 +/** @brief NAFLL clock source for NVJPG */ +#define TEGRA186_CLK_NAFLL_NVJPG 569 +/** @brief NAFLL clock source for SCE */ +#define TEGRA186_CLK_NAFLL_SCE 570 +/** @brief NAFLL clock source for SE */ +#define TEGRA186_CLK_NAFLL_SE 571 +/** @brief NAFLL clock source for TSEC */ +#define TEGRA186_CLK_NAFLL_TSEC 572 +/** @brief NAFLL clock source for TSECB */ +#define TEGRA186_CLK_NAFLL_TSECB 573 +/** @brief NAFLL clock source for VI */ +#define TEGRA186_CLK_NAFLL_VI 574 +/** @brief NAFLL clock source for VIC */ +#define TEGRA186_CLK_NAFLL_VIC 575 +/** @brief NAFLL clock source for DISP */ +#define TEGRA186_CLK_NAFLL_DISP 576 +/** @brief NAFLL clock source for GPU */ +#define TEGRA186_CLK_NAFLL_GPU 577 +/** @brief NAFLL clock source for M-CPU cluster */ +#define TEGRA186_CLK_NAFLL_MCPU 578 +/** @brief NAFLL clock source for B-CPU cluster */ +#define TEGRA186_CLK_NAFLL_BCPU 579 +/** @brief input from Tegra's CLK_32K_IN pad */ +#define TEGRA186_CLK_CLK_32K 608 +/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */ +#define TEGRA186_CLK_CLK_M 609 +/** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */ +#define TEGRA186_CLK_PLL_REF 610 +/** @brief input from Tegra's XTAL_IN */ +#define TEGRA186_CLK_OSC 612 +/** @brief clock recovered from EAVB input */ +#define TEGRA186_CLK_EQOS_RX_INPUT 613 +/** @brief clock recovered from DTV input */ +#define TEGRA186_CLK_DTV_INPUT 614 +/** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/ +#define TEGRA186_CLK_SOR0_PAD_CLKOUT 615 +/** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/ +#define TEGRA186_CLK_SOR1_PAD_CLKOUT 616 +/** @brief clock recovered from I2S1 input */ +#define TEGRA186_CLK_I2S1_SYNC_INPUT 617 +/** @brief clock recovered from I2S2 input */ +#define TEGRA186_CLK_I2S2_SYNC_INPUT 618 +/** @brief clock recovered from I2S3 input */ +#define TEGRA186_CLK_I2S3_SYNC_INPUT 619 +/** @brief clock recovered from I2S4 input */ +#define TEGRA186_CLK_I2S4_SYNC_INPUT 620 +/** @brief clock recovered from I2S5 input */ +#define TEGRA186_CLK_I2S5_SYNC_INPUT 621 +/** @brief clock recovered from I2S6 input */ +#define TEGRA186_CLK_I2S6_SYNC_INPUT 622 +/** @brief clock recovered from SPDIFIN input */ +#define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623 + +/** + * @brief subject to change + * @details maximum clock identifier value plus one. + */ +#define TEGRA186_CLK_CLK_MAX 624 + +/** @} */ + +#endif diff --git a/include/dt-bindings/mailbox/tegra-hsp.h b/include/dt-bindings/mailbox/tegra-hsp.h deleted file mode 100644 index e8c23fa..0000000 --- a/include/dt-bindings/mailbox/tegra-hsp.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra186-hsp. - * - * The number with TEGRA_HSP_MASTER prefix indicates the bit that is - * associated with a master ID in the doorbell registers. - */ - -#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H -#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H - -#define TEGRA_HSP_MASTER_CCPLEX 17 -#define TEGRA_HSP_MASTER_BPMP 19 - -#endif diff --git a/include/dt-bindings/mailbox/tegra186-hsp.h b/include/dt-bindings/mailbox/tegra186-hsp.h new file mode 100644 index 0000000..b486432 --- /dev/null +++ b/include/dt-bindings/mailbox/tegra186-hsp.h @@ -0,0 +1,19 @@ +/* + * This header provides constants for binding nvidia,tegra186-hsp. + * + * The number with HSP_DB_MASTER prefix indicates the bit that is + * associated with a master ID in the doorbell registers. + */ + +#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H +#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H + +#define HSP_MBOX_TYPE_DB 0x0 +#define HSP_MBOX_TYPE_SM 0x1 +#define HSP_MBOX_TYPE_SS 0x2 +#define HSP_MBOX_TYPE_AS 0x3 + +#define HSP_DB_MASTER_CCPLEX 17 +#define HSP_DB_MASTER_BPMP 19 + +#endif diff --git a/include/dt-bindings/power/tegra186-powergate.h b/include/dt-bindings/power/tegra186-powergate.h new file mode 100644 index 0000000..70630c6 --- /dev/null +++ b/include/dt-bindings/power/tegra186-powergate.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2015-2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H +#define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H + +#define TEGRA186_POWER_DOMAIN_AUD 0 +#define TEGRA186_POWER_DOMAIN_DFD 1 +#define TEGRA186_POWER_DOMAIN_DISP 2 +#define TEGRA186_POWER_DOMAIN_DISPB 3 +#define TEGRA186_POWER_DOMAIN_DISPC 4 +#define TEGRA186_POWER_DOMAIN_ISPA 5 +#define TEGRA186_POWER_DOMAIN_NVDEC 6 +#define TEGRA186_POWER_DOMAIN_NVJPG 7 +#define TEGRA186_POWER_DOMAIN_MPE 8 +#define TEGRA186_POWER_DOMAIN_PCX 9 +#define TEGRA186_POWER_DOMAIN_SAX 10 +#define TEGRA186_POWER_DOMAIN_VE 11 +#define TEGRA186_POWER_DOMAIN_VIC 12 +#define TEGRA186_POWER_DOMAIN_XUSBA 13 +#define TEGRA186_POWER_DOMAIN_XUSBB 14 +#define TEGRA186_POWER_DOMAIN_XUSBC 15 +#define TEGRA186_POWER_DOMAIN_GPU 43 +#define TEGRA186_POWER_DOMAIN_MAX 44 + +#endif diff --git a/include/dt-bindings/reset/tegra186-reset.h b/include/dt-bindings/reset/tegra186-reset.h new file mode 100644 index 0000000..26b4ba9 --- /dev/null +++ b/include/dt-bindings/reset/tegra186-reset.h @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ABI_MACH_T186_RESET_T186_H_ +#define _ABI_MACH_T186_RESET_T186_H_ + +#define TEGRA186_RESET_ACTMON 0 +#define TEGRA186_RESET_AFI 1 +#define TEGRA186_RESET_CEC 2 +#define TEGRA186_RESET_CSITE 3 +#define TEGRA186_RESET_DP2 4 +#define TEGRA186_RESET_DPAUX 5 +#define TEGRA186_RESET_DSI 6 +#define TEGRA186_RESET_DSIB 7 +#define TEGRA186_RESET_DTV 8 +#define TEGRA186_RESET_DVFS 9 +#define TEGRA186_RESET_ENTROPY 10 +#define TEGRA186_RESET_EXTPERIPH1 11 +#define TEGRA186_RESET_EXTPERIPH2 12 +#define TEGRA186_RESET_EXTPERIPH3 13 +#define TEGRA186_RESET_GPU 14 +#define TEGRA186_RESET_HDA 15 +#define TEGRA186_RESET_HDA2CODEC_2X 16 +#define TEGRA186_RESET_HDA2HDMICODEC 17 +#define TEGRA186_RESET_HOST1X 18 +#define TEGRA186_RESET_I2C1 19 +#define TEGRA186_RESET_I2C2 20 +#define TEGRA186_RESET_I2C3 21 +#define TEGRA186_RESET_I2C4 22 +#define TEGRA186_RESET_I2C5 23 +#define TEGRA186_RESET_I2C6 24 +#define TEGRA186_RESET_ISP 25 +#define TEGRA186_RESET_KFUSE 26 +#define TEGRA186_RESET_LA 27 +#define TEGRA186_RESET_MIPI_CAL 28 +#define TEGRA186_RESET_PCIE 29 +#define TEGRA186_RESET_PCIEXCLK 30 +#define TEGRA186_RESET_SATA 31 +#define TEGRA186_RESET_SATACOLD 32 +#define TEGRA186_RESET_SDMMC1 33 +#define TEGRA186_RESET_SDMMC2 34 +#define TEGRA186_RESET_SDMMC3 35 +#define TEGRA186_RESET_SDMMC4 36 +#define TEGRA186_RESET_SE 37 +#define TEGRA186_RESET_SOC_THERM 38 +#define TEGRA186_RESET_SOR0 39 +#define TEGRA186_RESET_SPI1 40 +#define TEGRA186_RESET_SPI2 41 +#define TEGRA186_RESET_SPI3 42 +#define TEGRA186_RESET_SPI4 43 +#define TEGRA186_RESET_TMR 44 +#define TEGRA186_RESET_TRIG_SYS 45 +#define TEGRA186_RESET_TSEC 46 +#define TEGRA186_RESET_UARTA 47 +#define TEGRA186_RESET_UARTB 48 +#define TEGRA186_RESET_UARTC 49 +#define TEGRA186_RESET_UARTD 50 +#define TEGRA186_RESET_VI 51 +#define TEGRA186_RESET_VIC 52 +#define TEGRA186_RESET_XUSB_DEV 53 +#define TEGRA186_RESET_XUSB_HOST 54 +#define TEGRA186_RESET_XUSB_PADCTL 55 +#define TEGRA186_RESET_XUSB_SS 56 +#define TEGRA186_RESET_AON_APB 57 +#define TEGRA186_RESET_AXI_CBB 58 +#define TEGRA186_RESET_BPMP_APB 59 +#define TEGRA186_RESET_CAN1 60 +#define TEGRA186_RESET_CAN2 61 +#define TEGRA186_RESET_DMIC5 62 +#define TEGRA186_RESET_DSIC 63 +#define TEGRA186_RESET_DSID 64 +#define TEGRA186_RESET_EMC_EMC 65 +#define TEGRA186_RESET_EMC_MEM 66 +#define TEGRA186_RESET_EMCSB_EMC 67 +#define TEGRA186_RESET_EMCSB_MEM 68 +#define TEGRA186_RESET_EQOS 69 +#define TEGRA186_RESET_GPCDMA 70 +#define TEGRA186_RESET_GPIO_CTL0 71 +#define TEGRA186_RESET_GPIO_CTL1 72 +#define TEGRA186_RESET_GPIO_CTL2 73 +#define TEGRA186_RESET_GPIO_CTL3 74 +#define TEGRA186_RESET_GPIO_CTL4 75 +#define TEGRA186_RESET_GPIO_CTL5 76 +#define TEGRA186_RESET_I2C10 77 +#define TEGRA186_RESET_I2C12 78 +#define TEGRA186_RESET_I2C13 79 +#define TEGRA186_RESET_I2C14 80 +#define TEGRA186_RESET_I2C7 81 +#define TEGRA186_RESET_I2C8 82 +#define TEGRA186_RESET_I2C9 83 +#define TEGRA186_RESET_JTAG2AXI 84 +#define TEGRA186_RESET_MPHY_IOBIST 85 +#define TEGRA186_RESET_MPHY_L0_RX 86 +#define TEGRA186_RESET_MPHY_L0_TX 87 +#define TEGRA186_RESET_NVCSI 88 +#define TEGRA186_RESET_NVDISPLAY0_HEAD0 89 +#define TEGRA186_RESET_NVDISPLAY0_HEAD1 90 +#define TEGRA186_RESET_NVDISPLAY0_HEAD2 91 +#define TEGRA186_RESET_NVDISPLAY0_MISC 92 +#define TEGRA186_RESET_NVDISPLAY0_WGRP0 93 +#define TEGRA186_RESET_NVDISPLAY0_WGRP1 94 +#define TEGRA186_RESET_NVDISPLAY0_WGRP2 95 +#define TEGRA186_RESET_NVDISPLAY0_WGRP3 96 +#define TEGRA186_RESET_NVDISPLAY0_WGRP4 97 +#define TEGRA186_RESET_NVDISPLAY0_WGRP5 98 +#define TEGRA186_RESET_PWM1 99 +#define TEGRA186_RESET_PWM2 100 +#define TEGRA186_RESET_PWM3 101 +#define TEGRA186_RESET_PWM4 102 +#define TEGRA186_RESET_PWM5 103 +#define TEGRA186_RESET_PWM6 104 +#define TEGRA186_RESET_PWM7 105 +#define TEGRA186_RESET_PWM8 106 +#define TEGRA186_RESET_SCE_APB 107 +#define TEGRA186_RESET_SOR1 108 +#define TEGRA186_RESET_TACH 109 +#define TEGRA186_RESET_TSC 110 +#define TEGRA186_RESET_UARTF 111 +#define TEGRA186_RESET_UARTG 112 +#define TEGRA186_RESET_UFSHC 113 +#define TEGRA186_RESET_UFSHC_AXI_M 114 +#define TEGRA186_RESET_UPHY 115 +#define TEGRA186_RESET_ADSP 116 +#define TEGRA186_RESET_ADSPDBG 117 +#define TEGRA186_RESET_ADSPINTF 118 +#define TEGRA186_RESET_ADSPNEON 119 +#define TEGRA186_RESET_ADSPPERIPH 120 +#define TEGRA186_RESET_ADSPSCU 121 +#define TEGRA186_RESET_ADSPWDT 122 +#define TEGRA186_RESET_APE 123 +#define TEGRA186_RESET_DPAUX1 124 +#define TEGRA186_RESET_NVDEC 125 +#define TEGRA186_RESET_NVENC 126 +#define TEGRA186_RESET_NVJPG 127 +#define TEGRA186_RESET_PEX_USB_UPHY 128 +#define TEGRA186_RESET_QSPI 129 +#define TEGRA186_RESET_TSECB 130 +#define TEGRA186_RESET_VI_I2C 131 +#define TEGRA186_RESET_UARTE 132 +#define TEGRA186_RESET_TOP_GTE 133 +#define TEGRA186_RESET_SHSP 134 +#define TEGRA186_RESET_PEX_USB_UPHY_L5 135 +#define TEGRA186_RESET_PEX_USB_UPHY_L4 136 +#define TEGRA186_RESET_PEX_USB_UPHY_L3 137 +#define TEGRA186_RESET_PEX_USB_UPHY_L2 138 +#define TEGRA186_RESET_PEX_USB_UPHY_L1 139 +#define TEGRA186_RESET_PEX_USB_UPHY_L0 140 +#define TEGRA186_RESET_PEX_USB_UPHY_PLL1 141 +#define TEGRA186_RESET_PEX_USB_UPHY_PLL0 142 +#define TEGRA186_RESET_TSCTNVI 143 +#define TEGRA186_RESET_EXTPERIPH4 144 +#define TEGRA186_RESET_DSIPADCTL 145 +#define TEGRA186_RESET_AUD_MCLK 146 +#define TEGRA186_RESET_MPHY_CLK_CTL 147 +#define TEGRA186_RESET_MPHY_L1_RX 148 +#define TEGRA186_RESET_MPHY_L1_TX 149 +#define TEGRA186_RESET_UFSHC_LP 150 +#define TEGRA186_RESET_BPMP_NIC 151 +#define TEGRA186_RESET_BPMP_NSYSPORESET 152 +#define TEGRA186_RESET_BPMP_NRESET 153 +#define TEGRA186_RESET_BPMP_DBGRESETN 154 +#define TEGRA186_RESET_BPMP_PRESETDBGN 155 +#define TEGRA186_RESET_BPMP_PM 156 +#define TEGRA186_RESET_BPMP_CVC 157 +#define TEGRA186_RESET_BPMP_DMA 158 +#define TEGRA186_RESET_BPMP_HSP 159 +#define TEGRA186_RESET_TSCTNBPMP 160 +#define TEGRA186_RESET_BPMP_TKE 161 +#define TEGRA186_RESET_BPMP_GTE 162 +#define TEGRA186_RESET_BPMP_PM_ACTMON 163 +#define TEGRA186_RESET_AON_NIC 164 +#define TEGRA186_RESET_AON_NSYSPORESET 165 +#define TEGRA186_RESET_AON_NRESET 166 +#define TEGRA186_RESET_AON_DBGRESETN 167 +#define TEGRA186_RESET_AON_PRESETDBGN 168 +#define TEGRA186_RESET_AON_ACTMON 169 +#define TEGRA186_RESET_AOPM 170 +#define TEGRA186_RESET_AOVC 171 +#define TEGRA186_RESET_AON_DMA 172 +#define TEGRA186_RESET_AON_GPIO 173 +#define TEGRA186_RESET_AON_HSP 174 +#define TEGRA186_RESET_TSCTNAON 175 +#define TEGRA186_RESET_AON_TKE 176 +#define TEGRA186_RESET_AON_GTE 177 +#define TEGRA186_RESET_SCE_NIC 178 +#define TEGRA186_RESET_SCE_NSYSPORESET 179 +#define TEGRA186_RESET_SCE_NRESET 180 +#define TEGRA186_RESET_SCE_DBGRESETN 181 +#define TEGRA186_RESET_SCE_PRESETDBGN 182 +#define TEGRA186_RESET_SCE_ACTMON 183 +#define TEGRA186_RESET_SCE_PM 184 +#define TEGRA186_RESET_SCE_DMA 185 +#define TEGRA186_RESET_SCE_HSP 186 +#define TEGRA186_RESET_TSCTNSCE 187 +#define TEGRA186_RESET_SCE_TKE 188 +#define TEGRA186_RESET_SCE_GTE 189 +#define TEGRA186_RESET_SCE_CFG 190 +#define TEGRA186_RESET_ADSP_ALL 191 +/** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */ +#define TEGRA186_RESET_UFSHC_LP_SEQ 192 +#define TEGRA186_RESET_SIZE 193 + +#endif diff --git a/include/dt-structs.h b/include/dt-structs.h new file mode 100644 index 0000000..e13afa6 --- /dev/null +++ b/include/dt-structs.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2016 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_STTUCTS +#define __DT_STTUCTS + +/* These structures may only be used in SPL */ +#if CONFIG_IS_ENABLED(OF_PLATDATA) +struct phandle_2_cell { + const void *node; + int id; +}; +#include <generated/dt-structs.h> +#endif + +#endif diff --git a/include/dwmmc.h b/include/dwmmc.h index 335af51..5b9602c 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -105,7 +105,7 @@ /* Status Register */ #define DWMCI_BUSY (1 << 9) -#define DWMCI_FIFO_MASK 0x1ff +#define DWMCI_FIFO_MASK 0x1fff #define DWMCI_FIFO_SHIFT 17 /* FIFOTH Register */ @@ -224,9 +224,79 @@ static inline u8 dwmci_readb(struct dwmci_host *host, int reg) return readb(host->ioaddr + reg); } +#ifdef CONFIG_BLK +/** + * dwmci_setup_cfg() - Set up the configuration for DWMMC + * + * This is used to set up a DWMMC device when you are using CONFIG_BLK. + * + * This should be called from your MMC driver's probe() method once you have + * the information required. + * + * Generally your driver will have a platform data structure which holds both + * the configuration (struct mmc_config) and the MMC device info (struct mmc). + * For example: + * + * struct rockchip_mmc_plat { + * struct mmc_config cfg; + * struct mmc mmc; + * }; + * + * ... + * + * Inside U_BOOT_DRIVER(): + * .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat), + * + * To access platform data: + * struct rockchip_mmc_plat *plat = dev_get_platdata(dev); + * + * See rockchip_dw_mmc.c for an example. + * + * @cfg: Configuration structure to fill in (generally &plat->mmc) + * @name: Device name (normally dev->name) + * @buswidth: Bus width (in bits, such as 4 or 8) + * @caps: Host capabilities (MMC_MODE_...) + * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000) + * @min_clk: Minimum supported clock speed in HZ (e.g. 400000) + */ void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, uint caps, u32 max_clk, u32 min_clk); + +/** + * dwmci_bind() - Set up a new MMC block device + * + * This is used to set up a DWMMC block device when you are using CONFIG_BLK. + * It should be called from your driver's bind() method. + * + * See rockchip_dw_mmc.c for an example. + * + * @dev: Device to set up + * @mmc: Pointer to mmc structure (normally &plat->mmc) + * @cfg: Empty configuration structure (generally &plat->cfg). This is + * normally all zeroes at this point. The only purpose of passing + * this in is to set mmc->cfg to it. + * @return 0 if OK, -ve if the block device could not be created + */ int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); +#else +/** + * add_dwmci() - Add a new DWMMC interface + * + * This is used when you are not using CONFIG_BLK. Convert your driver over! + * + * @host: DWMMC host structure + * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000) + * @min_clk: Minimum supported clock speed in HZ (e.g. 400000) + * @return 0 if OK, -ve on error + */ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk); +#endif /* !CONFIG_BLK */ + +#ifdef CONFIG_DM_MMC_OPS +/* Export the operations to drivers */ +int dwmci_probe(struct udevice *dev); +extern const struct dm_mmc_ops dm_dwmci_ops; +#endif + #endif /* __DWMMC_HW_H */ diff --git a/include/ext4fs.h b/include/ext4fs.h index cc765ae..13d2c56 100644 --- a/include/ext4fs.h +++ b/include/ext4fs.h @@ -32,6 +32,7 @@ #define EXT4_EXT_MAGIC 0xf30a #define EXT4_FEATURE_RO_COMPAT_GDT_CSUM 0x0010 #define EXT4_FEATURE_INCOMPAT_EXTENTS 0x0040 +#define EXT4_FEATURE_INCOMPAT_64BIT 0x0080 #define EXT4_INDIRECT_BLOCKS 12 #define EXT4_BG_INODE_UNINIT 0x0001 diff --git a/include/fdt_support.h b/include/fdt_support.h index d34e959..e9f3497 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -172,9 +172,16 @@ int fdt_increase_size(void *fdt, int add_len); int fdt_fixup_nor_flash_size(void *blob); +#if defined(CONFIG_FDT_FIXUP_PARTITIONS) void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size); +#else +static inline void fdt_fixup_mtdparts(void *fdt, void *node_info, + int node_info_size) {} +#endif + void fdt_del_node_and_alias(void *blob, const char *alias); -u64 fdt_translate_address(void *blob, int node_offset, const __be32 *in_addr); +u64 fdt_translate_address(const void *blob, int node_offset, + const __be32 *in_addr); int fdt_node_offset_by_compat_reg(void *blob, const char *compat, phys_addr_t compat_off); int fdt_alloc_phandle(void *blob); @@ -233,7 +240,7 @@ static inline u64 of_read_number(const fdt32_t *cell, int size) return r; } -void of_bus_default_count_cells(void *blob, int parentoffset, +void of_bus_default_count_cells(const void *blob, int parentoffset, int *addrc, int *sizec); int ft_verify_fdt(void *fdt); int arch_fixup_memory_node(void *blob); diff --git a/include/fdtdec.h b/include/fdtdec.h index 05d70c4..aeb6bab 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -134,13 +134,10 @@ enum fdt_compat_id { COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */ COMPAT_SAMSUNG_EXYNOS5_SOUND, /* Exynos Sound */ COMPAT_WOLFSON_WM8994_CODEC, /* Wolfson WM8994 Sound Codec */ - COMPAT_GOOGLE_CROS_EC_KEYB, /* Google CROS_EC Keyboard */ COMPAT_SAMSUNG_EXYNOS_USB_PHY, /* Exynos phy controller for usb2.0 */ COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */ COMPAT_SAMSUNG_EXYNOS_TMU, /* Exynos TMU */ - COMPAT_SAMSUNG_EXYNOS_FIMD, /* Exynos Display controller */ COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */ - COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */ COMPAT_SAMSUNG_EXYNOS_DWMMC, /* Exynos DWMMC controller */ COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */ COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */ @@ -149,20 +146,16 @@ enum fdt_compat_id { COMPAT_SAMSUNG_EXYNOS5_I2C, /* Exynos5 High Speed I2C Controller */ COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */ COMPAT_INTEL_MICROCODE, /* Intel microcode update */ - COMPAT_INTEL_PANTHERPOINT_AHCI, /* Intel Pantherpoint AHCI */ - COMPAT_INTEL_MODEL_206AX, /* Intel Model 206AX CPU */ - COMPAT_INTEL_GMA, /* Intel Graphics Media Accelerator */ COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */ - COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */ COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */ - COMPAT_INTEL_PCH, /* Intel PCH */ COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */ COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */ COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */ COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */ COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */ COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */ + COMPAT_SUNXI_NAND, /* SUNXI NAND controller */ COMPAT_COUNT, }; @@ -304,11 +297,13 @@ int fdtdec_next_compatible_subnode(const void *blob, int node, * @param na the number of cells used to represent an address * @param ns the number of cells used to represent a size * @param sizep a pointer to store the size into. Use NULL if not required + * @param translate Indicates whether to translate the returned value + * using the parent node's ranges property. * @return address, if found, or FDT_ADDR_T_NONE if not */ fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node, const char *prop_name, int index, int na, int ns, - fdt_size_t *sizep); + fdt_size_t *sizep, bool translate); /* * Look up an address property in a node and return the parsed address, and @@ -324,10 +319,13 @@ fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node, * @param prop_name name of property to find * @param index which address to retrieve from a list of addresses. Often 0. * @param sizep a pointer to store the size into. Use NULL if not required + * @param translate Indicates whether to translate the returned value + * using the parent node's ranges property. * @return address, if found, or FDT_ADDR_T_NONE if not */ fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent, - int node, const char *prop_name, int index, fdt_size_t *sizep); + int node, const char *prop_name, int index, fdt_size_t *sizep, + bool translate); /* * Look up an address property in a node and return the parsed address, and @@ -347,10 +345,13 @@ fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent, * @param prop_name name of property to find * @param index which address to retrieve from a list of addresses. Often 0. * @param sizep a pointer to store the size into. Use NULL if not required + * @param translate Indicates whether to translate the returned value + * using the parent node's ranges property. * @return address, if found, or FDT_ADDR_T_NONE if not */ fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node, - const char *prop_name, int index, fdt_size_t *sizep); + const char *prop_name, int index, fdt_size_t *sizep, + bool translate); /* * Look up an address property in a node and return the parsed address. diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h index 281a819..a939d89 100644 --- a/include/fsl_mmdc.h +++ b/include/fsl_mmdc.h @@ -12,7 +12,7 @@ #define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1 0xff328f64 #define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2 0x01ff00db -#define CONFIG_SYS_MMDC_CORE_MISC 0x00000680 +#define CONFIG_SYS_MMDC_CORE_MISC 0x00001680 #define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT 0x00000800 #define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY 0x00002000 #define CONFIG_SYS_MMDC_PHY_ODT_CTRL 0x0000022a @@ -43,7 +43,7 @@ #define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT 0x00001067 -#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x103e8000 +#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x0f3c8000 #define START_REFRESH 0x00000001 diff --git a/include/fsl_validate.h b/include/fsl_validate.h index a71e1ce..c350938 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -254,4 +254,11 @@ int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc, int fsl_check_boot_mode_secure(void); int fsl_setenv_chain_of_trust(void); + +/* + * This function is used to validate the main U-boot binary from + * SPL just before passing control to it using QorIQ Trust + * Architecture header (appended to U-boot image). + */ +void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr); #endif diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index e1b9c64..bb8e144 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -17,7 +17,6 @@ enum { }; int get_fpga_state(unsigned dev); -void print_fpga_state(unsigned dev); int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data); int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data); diff --git a/include/i2c_eeprom.h b/include/i2c_eeprom.h index ea6c962..0452892 100644 --- a/include/i2c_eeprom.h +++ b/include/i2c_eeprom.h @@ -14,6 +14,10 @@ struct i2c_eeprom_ops { }; struct i2c_eeprom { + /* The EEPROM's page size in byte */ + unsigned long pagesize; + /* The EEPROM's page width in bits (pagesize = 2^pagewidth) */ + unsigned pagewidth; }; #endif diff --git a/include/image.h b/include/image.h index d788c26..64da722 100644 --- a/include/image.h +++ b/include/image.h @@ -123,62 +123,87 @@ struct lmb; # define IMAGE_OF_SYSTEM_SETUP 0 #endif +enum ih_category { + IH_ARCH, + IH_COMP, + IH_OS, + IH_TYPE, + + IH_COUNT, +}; + /* * Operating System Codes + * + * The following are exposed to uImage header. + * Do not change values for backward compatibility. */ -#define IH_OS_INVALID 0 /* Invalid OS */ -#define IH_OS_OPENBSD 1 /* OpenBSD */ -#define IH_OS_NETBSD 2 /* NetBSD */ -#define IH_OS_FREEBSD 3 /* FreeBSD */ -#define IH_OS_4_4BSD 4 /* 4.4BSD */ -#define IH_OS_LINUX 5 /* Linux */ -#define IH_OS_SVR4 6 /* SVR4 */ -#define IH_OS_ESIX 7 /* Esix */ -#define IH_OS_SOLARIS 8 /* Solaris */ -#define IH_OS_IRIX 9 /* Irix */ -#define IH_OS_SCO 10 /* SCO */ -#define IH_OS_DELL 11 /* Dell */ -#define IH_OS_NCR 12 /* NCR */ -#define IH_OS_LYNXOS 13 /* LynxOS */ -#define IH_OS_VXWORKS 14 /* VxWorks */ -#define IH_OS_PSOS 15 /* pSOS */ -#define IH_OS_QNX 16 /* QNX */ -#define IH_OS_U_BOOT 17 /* Firmware */ -#define IH_OS_RTEMS 18 /* RTEMS */ -#define IH_OS_ARTOS 19 /* ARTOS */ -#define IH_OS_UNITY 20 /* Unity OS */ -#define IH_OS_INTEGRITY 21 /* INTEGRITY */ -#define IH_OS_OSE 22 /* OSE */ -#define IH_OS_PLAN9 23 /* Plan 9 */ -#define IH_OS_OPENRTOS 24 /* OpenRTOS */ +enum { + IH_OS_INVALID = 0, /* Invalid OS */ + IH_OS_OPENBSD, /* OpenBSD */ + IH_OS_NETBSD, /* NetBSD */ + IH_OS_FREEBSD, /* FreeBSD */ + IH_OS_4_4BSD, /* 4.4BSD */ + IH_OS_LINUX, /* Linux */ + IH_OS_SVR4, /* SVR4 */ + IH_OS_ESIX, /* Esix */ + IH_OS_SOLARIS, /* Solaris */ + IH_OS_IRIX, /* Irix */ + IH_OS_SCO, /* SCO */ + IH_OS_DELL, /* Dell */ + IH_OS_NCR, /* NCR */ + IH_OS_LYNXOS, /* LynxOS */ + IH_OS_VXWORKS, /* VxWorks */ + IH_OS_PSOS, /* pSOS */ + IH_OS_QNX, /* QNX */ + IH_OS_U_BOOT, /* Firmware */ + IH_OS_RTEMS, /* RTEMS */ + IH_OS_ARTOS, /* ARTOS */ + IH_OS_UNITY, /* Unity OS */ + IH_OS_INTEGRITY, /* INTEGRITY */ + IH_OS_OSE, /* OSE */ + IH_OS_PLAN9, /* Plan 9 */ + IH_OS_OPENRTOS, /* OpenRTOS */ + + IH_OS_COUNT, +}; /* * CPU Architecture Codes (supported by Linux) + * + * The following are exposed to uImage header. + * Do not change values for backward compatibility. */ -#define IH_ARCH_INVALID 0 /* Invalid CPU */ -#define IH_ARCH_ALPHA 1 /* Alpha */ -#define IH_ARCH_ARM 2 /* ARM */ -#define IH_ARCH_I386 3 /* Intel x86 */ -#define IH_ARCH_IA64 4 /* IA64 */ -#define IH_ARCH_MIPS 5 /* MIPS */ -#define IH_ARCH_MIPS64 6 /* MIPS 64 Bit */ -#define IH_ARCH_PPC 7 /* PowerPC */ -#define IH_ARCH_S390 8 /* IBM S390 */ -#define IH_ARCH_SH 9 /* SuperH */ -#define IH_ARCH_SPARC 10 /* Sparc */ -#define IH_ARCH_SPARC64 11 /* Sparc 64 Bit */ -#define IH_ARCH_M68K 12 /* M68K */ -#define IH_ARCH_MICROBLAZE 14 /* MicroBlaze */ -#define IH_ARCH_NIOS2 15 /* Nios-II */ -#define IH_ARCH_BLACKFIN 16 /* Blackfin */ -#define IH_ARCH_AVR32 17 /* AVR32 */ -#define IH_ARCH_ST200 18 /* STMicroelectronics ST200 */ -#define IH_ARCH_SANDBOX 19 /* Sandbox architecture (test only) */ -#define IH_ARCH_NDS32 20 /* ANDES Technology - NDS32 */ -#define IH_ARCH_OPENRISC 21 /* OpenRISC 1000 */ -#define IH_ARCH_ARM64 22 /* ARM64 */ -#define IH_ARCH_ARC 23 /* Synopsys DesignWare ARC */ -#define IH_ARCH_X86_64 24 /* AMD x86_64, Intel and Via */ +enum { + IH_ARCH_INVALID = 0, /* Invalid CPU */ + IH_ARCH_ALPHA, /* Alpha */ + IH_ARCH_ARM, /* ARM */ + IH_ARCH_I386, /* Intel x86 */ + IH_ARCH_IA64, /* IA64 */ + IH_ARCH_MIPS, /* MIPS */ + IH_ARCH_MIPS64, /* MIPS 64 Bit */ + IH_ARCH_PPC, /* PowerPC */ + IH_ARCH_S390, /* IBM S390 */ + IH_ARCH_SH, /* SuperH */ + IH_ARCH_SPARC, /* Sparc */ + IH_ARCH_SPARC64, /* Sparc 64 Bit */ + IH_ARCH_M68K, /* M68K */ + IH_ARCH_NIOS, /* Nios-32 */ + IH_ARCH_MICROBLAZE, /* MicroBlaze */ + IH_ARCH_NIOS2, /* Nios-II */ + IH_ARCH_BLACKFIN, /* Blackfin */ + IH_ARCH_AVR32, /* AVR32 */ + IH_ARCH_ST200, /* STMicroelectronics ST200 */ + IH_ARCH_SANDBOX, /* Sandbox architecture (test only) */ + IH_ARCH_NDS32, /* ANDES Technology - NDS32 */ + IH_ARCH_OPENRISC, /* OpenRISC 1000 */ + IH_ARCH_ARM64, /* ARM64 */ + IH_ARCH_ARC, /* Synopsys DesignWare ARC */ + IH_ARCH_X86_64, /* AMD x86_64, Intel and Via */ + IH_ARCH_XTENSA, /* Xtensa */ + + IH_ARCH_COUNT, +}; /* * Image Types @@ -217,49 +242,62 @@ struct lmb; * U-Boot's command interpreter; this feature is especially * useful when you configure U-Boot to use a real shell (hush) * as command interpreter (=> Shell Scripts). + * + * The following are exposed to uImage header. + * Do not change values for backward compatibility. */ -#define IH_TYPE_INVALID 0 /* Invalid Image */ -#define IH_TYPE_STANDALONE 1 /* Standalone Program */ -#define IH_TYPE_KERNEL 2 /* OS Kernel Image */ -#define IH_TYPE_RAMDISK 3 /* RAMDisk Image */ -#define IH_TYPE_MULTI 4 /* Multi-File Image */ -#define IH_TYPE_FIRMWARE 5 /* Firmware Image */ -#define IH_TYPE_SCRIPT 6 /* Script file */ -#define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */ -#define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ -#define IH_TYPE_KWBIMAGE 9 /* Kirkwood Boot Image */ -#define IH_TYPE_IMXIMAGE 10 /* Freescale IMXBoot Image */ -#define IH_TYPE_UBLIMAGE 11 /* Davinci UBL Image */ -#define IH_TYPE_OMAPIMAGE 12 /* TI OMAP Config Header Image */ -#define IH_TYPE_AISIMAGE 13 /* TI Davinci AIS Image */ -#define IH_TYPE_KERNEL_NOLOAD 14 /* OS Kernel Image, can run from any load address */ -#define IH_TYPE_PBLIMAGE 15 /* Freescale PBL Boot Image */ -#define IH_TYPE_MXSIMAGE 16 /* Freescale MXSBoot Image */ -#define IH_TYPE_GPIMAGE 17 /* TI Keystone GPHeader Image */ -#define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */ -#define IH_TYPE_SOCFPGAIMAGE 19 /* Altera SOCFPGA Preloader */ -#define IH_TYPE_X86_SETUP 20 /* x86 setup.bin Image */ -#define IH_TYPE_LPC32XXIMAGE 21 /* x86 setup.bin Image */ -#define IH_TYPE_LOADABLE 22 /* A list of typeless images */ -#define IH_TYPE_RKIMAGE 23 /* Rockchip Boot Image */ -#define IH_TYPE_RKSD 24 /* Rockchip SD card */ -#define IH_TYPE_RKSPI 25 /* Rockchip SPI image */ -#define IH_TYPE_ZYNQIMAGE 26 /* Xilinx Zynq Boot Image */ -#define IH_TYPE_ZYNQMPIMAGE 27 /* Xilinx ZynqMP Boot Image */ -#define IH_TYPE_FPGA 28 /* FPGA Image */ - -#define IH_TYPE_COUNT 29 /* Number of image types */ +enum { + IH_TYPE_INVALID = 0, /* Invalid Image */ + IH_TYPE_STANDALONE, /* Standalone Program */ + IH_TYPE_KERNEL, /* OS Kernel Image */ + IH_TYPE_RAMDISK, /* RAMDisk Image */ + IH_TYPE_MULTI, /* Multi-File Image */ + IH_TYPE_FIRMWARE, /* Firmware Image */ + IH_TYPE_SCRIPT, /* Script file */ + IH_TYPE_FILESYSTEM, /* Filesystem Image (any type) */ + IH_TYPE_FLATDT, /* Binary Flat Device Tree Blob */ + IH_TYPE_KWBIMAGE, /* Kirkwood Boot Image */ + IH_TYPE_IMXIMAGE, /* Freescale IMXBoot Image */ + IH_TYPE_UBLIMAGE, /* Davinci UBL Image */ + IH_TYPE_OMAPIMAGE, /* TI OMAP Config Header Image */ + IH_TYPE_AISIMAGE, /* TI Davinci AIS Image */ + /* OS Kernel Image, can run from any load address */ + IH_TYPE_KERNEL_NOLOAD, + IH_TYPE_PBLIMAGE, /* Freescale PBL Boot Image */ + IH_TYPE_MXSIMAGE, /* Freescale MXSBoot Image */ + IH_TYPE_GPIMAGE, /* TI Keystone GPHeader Image */ + IH_TYPE_ATMELIMAGE, /* ATMEL ROM bootable Image */ + IH_TYPE_SOCFPGAIMAGE, /* Altera SOCFPGA Preloader */ + IH_TYPE_X86_SETUP, /* x86 setup.bin Image */ + IH_TYPE_LPC32XXIMAGE, /* x86 setup.bin Image */ + IH_TYPE_LOADABLE, /* A list of typeless images */ + IH_TYPE_RKIMAGE, /* Rockchip Boot Image */ + IH_TYPE_RKSD, /* Rockchip SD card */ + IH_TYPE_RKSPI, /* Rockchip SPI image */ + IH_TYPE_ZYNQIMAGE, /* Xilinx Zynq Boot Image */ + IH_TYPE_ZYNQMPIMAGE, /* Xilinx ZynqMP Boot Image */ + IH_TYPE_FPGA, /* FPGA Image */ + + IH_TYPE_COUNT, /* Number of image types */ +}; /* * Compression Types + * + * The following are exposed to uImage header. + * Do not change values for backward compatibility. */ -#define IH_COMP_NONE 0 /* No Compression Used */ -#define IH_COMP_GZIP 1 /* gzip Compression Used */ -#define IH_COMP_BZIP2 2 /* bzip2 Compression Used */ -#define IH_COMP_LZMA 3 /* lzma Compression Used */ -#define IH_COMP_LZO 4 /* lzo Compression Used */ -#define IH_COMP_LZ4 5 /* lz4 Compression Used */ +enum { + IH_COMP_NONE = 0, /* No Compression Used */ + IH_COMP_GZIP, /* gzip Compression Used */ + IH_COMP_BZIP2, /* bzip2 Compression Used */ + IH_COMP_LZMA, /* lzma Compression Used */ + IH_COMP_LZO, /* lzo Compression Used */ + IH_COMP_LZ4, /* lz4 Compression Used */ + + IH_COMP_COUNT, +}; #define IH_MAGIC 0x27051956 /* Image Magic Number */ #define IH_NMLEN 32 /* Image Name Length */ @@ -454,6 +492,40 @@ const char *genimg_get_comp_name(uint8_t comp); */ const char *genimg_get_comp_short_name(uint8_t comp); +/** + * genimg_get_cat_name() - Get the name of an item in a category + * + * @category: Category of item + * @id: Item ID + * @return name of item, or "Unknown ..." if unknown + */ +const char *genimg_get_cat_name(enum ih_category category, uint id); + +/** + * genimg_get_cat_short_name() - Get the short name of an item in a category + * + * @category: Category of item + * @id: Item ID + * @return short name of item, or "Unknown ..." if unknown + */ +const char *genimg_get_cat_short_name(enum ih_category category, uint id); + +/** + * genimg_get_cat_count() - Get the number of items in a category + * + * @category: Category to check + * @return the number of items in the category (IH_xxx_COUNT) + */ +int genimg_get_cat_count(enum ih_category category); + +/** + * genimg_get_cat_desc() - Get the description of a category + * + * @return the description of a category, e.g. "architecture". This + * effectively converts the enum to a string. + */ +const char *genimg_get_cat_desc(enum ih_category category); + int genimg_get_os_id(const char *name); int genimg_get_arch_id(const char *name); int genimg_get_type_id(const char *name); @@ -1173,4 +1245,21 @@ void android_print_contents(const struct andr_img_hdr *hdr); */ int board_fit_config_name_match(const char *name); +#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS +/** + * board_fit_image_post_process() - Do any post-process on FIT binary data + * + * This is used to do any sort of image manipulation, verification, decryption + * etc. in a platform or board specific way. Obviously, anything done here would + * need to be comprehended in how the images were prepared before being injected + * into the FIT creation (i.e. the binary blobs would have been pre-processed + * before being added to the FIT image). + * + * @image: pointer to the image start pointer + * @size: pointer to the image size + * @return no return value (failure should be handled internally) + */ +void board_fit_image_post_process(void **p_image, size_t *p_size); +#endif /* CONFIG_SPL_FIT_IMAGE_POST_PROCESS */ + #endif /* __IMAGE_H__ */ diff --git a/include/libfdt.h b/include/libfdt.h index 74b1d14..b6a400a 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -284,6 +284,19 @@ int fdt_move(const void *fdt, void *buf, int bufsize); const char *fdt_string(const void *fdt, int stroffset); /** + * fdt_get_max_phandle - retrieves the highest phandle in a tree + * @fdt: pointer to the device tree blob + * + * fdt_get_max_phandle retrieves the highest phandle in the given + * device tree + * + * returns: + * the highest phandle on success + * 0, if an error occurred + */ +uint32_t fdt_get_max_phandle(const void *fdt); + +/** * fdt_num_mem_rsv - retrieve the number of memory reserve map entries * @fdt: pointer to the device tree blob * @@ -353,6 +366,17 @@ int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); /** + * fdt_path_offset_namelen - find a tree node based on substring + * @fdt: pointer to the device tree blob + * @path: full path of the node to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_path_offset(), but only examine the first + * namelen characters of path for matching the node path. + */ +int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen); + +/** * fdt_path_offset - find a tree node by its full path * @fdt: pointer to the device tree blob * @path: full path of the node to locate @@ -374,7 +398,10 @@ int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); * -FDT_ERR_BADSTRUCTURE, * -FDT_ERR_TRUNCATED, standard meanings. */ -int fdt_path_offset(const void *fdt, const char *path); +static inline int fdt_path_offset(const void *fdt, const char *path) +{ + return fdt_path_offset_namelen(fdt, path, strlen(path)); +} /** * fdt_get_name - retrieve the name of a given node @@ -441,6 +468,30 @@ int fdt_first_property_offset(const void *fdt, int nodeoffset); int fdt_next_property_offset(const void *fdt, int offset); /** + * fdt_for_each_property - iterate over all properties of a node + * @property_offset: property offset (int) + * @fdt: FDT blob (const void *) + * @node: node offset (int) + * + * This is actually a wrapper around a for loop and would be used like so: + * + * fdt_for_each_property(fdt, node, property) { + * ... + * use property + * ... + * } + * + * Note that this is implemented as a macro and property is used as + * iterator in the loop. It should therefore be a locally allocated + * variable. The node variable on the other hand is never modified, so + * it can be constant or even a literal. + */ +#define fdt_for_each_property_offset(property, fdt, node) \ + for (property = fdt_first_property_offset(fdt, node); \ + property >= 0; \ + property = fdt_next_property_offset(fdt, property)) + +/** * fdt_get_property_by_offset - retrieve the property at a given offset * @fdt: pointer to the device tree blob * @offset: offset of the property to retrieve @@ -568,6 +619,13 @@ const void *fdt_getprop_by_offset(const void *fdt, int offset, */ const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, const char *name, int namelen, int *lenp); +static inline void *fdt_getprop_namelen_w(void *fdt, int nodeoffset, + const char *name, int namelen, + int *lenp) +{ + return (void *)(uintptr_t)fdt_getprop_namelen(fdt, nodeoffset, name, + namelen, lenp); +} /** * fdt_getprop - retrieve the value of a given property @@ -996,6 +1054,27 @@ int fdt_size_cells(const void *fdt, int nodeoffset); /**********************************************************************/ /** + * fdt_setprop_inplace_namelen_partial - change a property's value, + * but not its size + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @namelen: number of characters of name to consider + * @index: index of the property to change in the array + * @val: pointer to data to replace the property value with + * @len: length of the property value + * + * Identical to fdt_setprop_inplace(), but modifies the given property + * starting from the given index, and using only the first characters + * of the name. It is useful when you want to manipulate only one value of + * an array and you have a string that doesn't end with \0. + */ +int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset, + const char *name, int namelen, + uint32_t index, const void *val, + int len); + +/** * fdt_setprop_inplace - change a property's value, but not its size * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node whose property to change @@ -1661,6 +1740,36 @@ int fdt_add_subnode(void *fdt, int parentoffset, const char *name); */ int fdt_del_node(void *fdt, int nodeoffset); +/** + * fdt_overlay_apply - Applies a DT overlay on a base DT + * @fdt: pointer to the base device tree blob + * @fdto: pointer to the device tree overlay blob + * + * fdt_overlay_apply() will apply the given device tree overlay on the + * given base device tree. + * + * Expect the base device tree to be modified, even if the function + * returns an error. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there's not enough space in the base device tree + * -FDT_ERR_NOTFOUND, the overlay points to some inexistant nodes or + * properties in the base DT + * -FDT_ERR_BADPHANDLE, the phandles in the overlay do not have the right + * magic + * -FDT_ERR_INTERNAL, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADOFFSET, + * -FDT_ERR_BADPATH, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_overlay_apply(void *fdt, void *fdto); + /**********************************************************************/ /* Debugging / informational functions */ /**********************************************************************/ diff --git a/include/libfdt_env.h b/include/libfdt_env.h index 273b5d3..6c6845f 100644 --- a/include/libfdt_env.h +++ b/include/libfdt_env.h @@ -23,6 +23,12 @@ typedef __be64 fdt64_t; #define fdt64_to_cpu(x) be64_to_cpu(x) #define cpu_to_fdt64(x) cpu_to_be64(x) +#ifdef __UBOOT__ +#include <vsprintf.h> + +#define strtoul(cp, endp, base) simple_strtoul(cp, endp, base) +#endif + /* adding a ramdisk needs 0x44 bytes in version 2008.10 */ #define FDT_RAMDISK_OVERHEAD 0x80 diff --git a/include/linux/io.h b/include/linux/io.h index 1b36a22..a104b7e 100644 --- a/include/linux/io.h +++ b/include/linux/io.h @@ -5,6 +5,22 @@ #ifndef _LINUX_IO_H #define _LINUX_IO_H +#include <linux/compiler.h> +#include <linux/types.h> #include <asm/io.h> +#ifndef CONFIG_HAVE_ARCH_IOREMAP +static inline void __iomem *ioremap(resource_size_t offset, + resource_size_t size) +{ + return (void __iomem *)(unsigned long)offset; +} + +static inline void iounmap(void __iomem *addr) +{ +} + +#define devm_ioremap(dev, offset, size) ioremap(offset, size) +#endif + #endif /* _LINUX_IO_H */ diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index cf20674..779eea0 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -500,5 +500,10 @@ int mtd_arg_off(const char *arg, int *idx, loff_t *off, loff_t *size, int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off, loff_t *size, loff_t *maxsize, int devtype, uint64_t chipsize); + +/* drivers/mtd/mtdcore.c */ +void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset, + const uint64_t length, uint64_t *len_incl_bad, + int *truncated); #endif #endif /* __MTD_MTD_H__ */ diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index b5a02c3..87d72db 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -48,7 +48,7 @@ extern void nand_wait_ready(struct mtd_info *mtd); * is supported now. If you add a chip with bigger oobsize/page * adjust this accordingly. */ -#define NAND_MAX_OOBSIZE 1216 +#define NAND_MAX_OOBSIZE 1664 #define NAND_MAX_PAGESIZE 16384 /* @@ -590,6 +590,7 @@ struct nand_buffers { * flash device * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the * flash device. + * @flash_node: [BOARDSPECIFIC] device node describing this instance * @read_byte: [REPLACEABLE] read one byte from the chip * @read_word: [REPLACEABLE] read one word from the chip * @write_byte: [REPLACEABLE] write a single byte to the chip on the @@ -689,6 +690,8 @@ struct nand_chip { void __iomem *IO_ADDR_R; void __iomem *IO_ADDR_W; + int flash_node; + uint8_t (*read_byte)(struct mtd_info *mtd); u16 (*read_word)(struct mtd_info *mtd); void (*write_byte)(struct mtd_info *mtd, uint8_t byte); diff --git a/include/linux/mtd/omap_gpmc.h b/include/linux/mtd/omap_gpmc.h index 3a75674..be3ce9d 100644 --- a/include/linux/mtd/omap_gpmc.h +++ b/include/linux/mtd/omap_gpmc.h @@ -92,6 +92,7 @@ struct gpmc { }; /* Used for board specific gpmc initialization */ -extern struct gpmc *gpmc_cfg; +extern const struct gpmc *gpmc_cfg; +extern char gpmc_cs0_flash; #endif /* __ASM_OMAP_GPMC_H */ diff --git a/include/linux/stat.h b/include/linux/stat.h index cef6369..1af0876 100644 --- a/include/linux/stat.h +++ b/include/linux/stat.h @@ -126,7 +126,7 @@ struct stat { #endif /* __MIPS__ */ -#if defined(__AVR32__) || defined(__SH__) +#if defined(__AVR32__) || defined(__SH__) || defined(__XTENSA__) struct stat { unsigned long st_dev; @@ -149,7 +149,7 @@ struct stat { unsigned long __unused5; }; -#endif /* __AVR32__ || __SH__ */ +#endif /* __AVR32__ || __SH__ || __XTENSA__ */ #ifdef __cplusplus } diff --git a/include/linux/types.h b/include/linux/types.h index 6f75be4..416fa66 100644 --- a/include/linux/types.h +++ b/include/linux/types.h @@ -124,6 +124,10 @@ typedef __UINT64_TYPE__ u_int64_t; typedef __INT64_TYPE__ int64_t; #endif +#ifdef __KERNEL__ +typedef phys_addr_t resource_size_t; +#endif + /* * Below are truly Linux-specific types that should never collide with * any application/library that wants linux/types.h. diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index 253eddf..199f366 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -51,22 +51,18 @@ struct fsl_xhci { struct dwc3 *dwc3_reg; }; -#if defined(CONFIG_LS102XA) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR +#if defined(CONFIG_LS102XA) || defined(CONFIG_LS1012A) +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 #elif defined(CONFIG_LS2080A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR -#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 -#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR -#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR -#elif defined(CONFIG_LS1012A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR +#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 +#elif defined(CONFIG_LS1043A) +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR +#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR +#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR #endif #define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \ diff --git a/include/miiphy.h b/include/miiphy.h index af12274..83141b4 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -21,13 +21,6 @@ #include <net.h> #include <phy.h> -struct legacy_mii_dev { - int (*read)(const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); - int (*write)(const char *devname, unsigned char addr, - unsigned char reg, unsigned short value); -}; - int miiphy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value); int miiphy_write(const char *devname, unsigned char addr, unsigned char reg, @@ -44,12 +37,6 @@ int miiphy_link(const char *devname, unsigned char addr); void miiphy_init(void); -void miiphy_register(const char *devname, - int (*read)(const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value), - int (*write)(const char *devname, unsigned char addr, - unsigned char reg, unsigned short value)); - int miiphy_set_current_dev(const char *devname); const char *miiphy_get_current_dev(void); struct mii_dev *mdio_get_current_dev(void); @@ -86,10 +73,9 @@ extern struct bb_miiphy_bus bb_miiphy_buses[]; extern int bb_miiphy_buses_num; void bb_miiphy_init(void); -int bb_miiphy_read(const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -int bb_miiphy_write(const char *devname, unsigned char addr, - unsigned char reg, unsigned short value); +int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg); +int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg, + u16 value); #endif /* phy seed setup */ diff --git a/include/misc.h b/include/misc.h index 2b78814..03ef55c 100644 --- a/include/misc.h +++ b/include/misc.h @@ -38,6 +38,27 @@ int misc_write(struct udevice *dev, int offset, void *buf, int size); int misc_ioctl(struct udevice *dev, unsigned long request, void *buf); /* + * Send a message to the device and wait for a response. + * + * The caller provides the message type/ID and payload to be sent. + * The callee constructs any message header required, transmits it to the + * target, waits for a response, checks any error code in the response, + * strips any message header from the response, and returns the error code + * (or a parsed version of it) and the response message payload. + * + * @dev: the device. + * @msgid: the message ID/number to send. + * tx_msg: the request/transmit message payload. + * tx_size: the size of the buffer pointed at by tx_msg. + * rx_msg: the buffer to receive the response message payload. May be NULL if + * the caller only cares about the error code. + * rx_size: the size of the buffer pointed at by rx_msg. + * @return the response message size if OK, -ve on error + */ +int misc_call(struct udevice *dev, int msgid, void *tx_msg, int tx_size, + void *rx_msg, int rx_size); + +/* * struct misc_ops - Driver model Misc operations * * The uclass interface is implemented by all miscellaneous devices which @@ -74,6 +95,20 @@ struct misc_ops { * @return: 0 if OK, -ve on error */ int (*ioctl)(struct udevice *dev, unsigned long request, void *buf); + /* + * Send a message to the device and wait for a response. + * + * @dev: the device + * @msgid: the message ID/number to send + * tx_msg: the request/transmit message payload + * tx_size: the size of the buffer pointed at by tx_msg + * rx_msg: the buffer to receive the response message payload. May be + * NULL if the caller only cares about the error code. + * rx_size: the size of the buffer pointed at by rx_msg + * @return the response message size if OK, -ve on error + */ + int (*call)(struct udevice *dev, int msgid, void *tx_msg, int tx_size, + void *rx_msg, int rx_size); }; #endif /* _MISC_H_ */ diff --git a/include/mmc.h b/include/mmc.h index f383925..aa6d5d1 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -66,12 +66,6 @@ #define MMC_DATA_READ 1 #define MMC_DATA_WRITE 2 -#define NO_CARD_ERR -16 /* No SD/MMC card inserted */ -#define UNUSABLE_ERR -17 /* Unusable Card */ -#define COMM_ERR -18 /* Communications Error */ -#define TIMEOUT -19 -#define SWITCH_ERR -20 /* Card reports failure to switch mode */ - #define MMC_CMD_GO_IDLE_STATE 0 #define MMC_CMD_SEND_OP_COND 1 #define MMC_CMD_ALL_SEND_CID 2 @@ -323,6 +317,58 @@ struct mmc_data { /* forward decl. */ struct mmc; +#ifdef CONFIG_DM_MMC_OPS +struct dm_mmc_ops { + /** + * send_cmd() - Send a command to the MMC device + * + * @dev: Device to receive the command + * @cmd: Command to send + * @data: Additional data to send/receive + * @return 0 if OK, -ve on error + */ + int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data); + + /** + * set_ios() - Set the I/O speed/width for an MMC device + * + * @dev: Device to update + * @return 0 if OK, -ve on error + */ + int (*set_ios)(struct udevice *dev); + + /** + * get_cd() - See whether a card is present + * + * @dev: Device to check + * @return 0 if not present, 1 if present, -ve on error + */ + int (*get_cd)(struct udevice *dev); + + /** + * get_wp() - See whether a card has write-protect enabled + * + * @dev: Device to check + * @return 0 if write-enabled, 1 if write-protected, -ve on error + */ + int (*get_wp)(struct udevice *dev); +}; + +#define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops) + +int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data); +int dm_mmc_set_ios(struct udevice *dev); +int dm_mmc_get_cd(struct udevice *dev); +int dm_mmc_get_wp(struct udevice *dev); + +/* Transition functions for compatibility */ +int mmc_set_ios(struct mmc *mmc); +int mmc_getcd(struct mmc *mmc); +int mmc_getwp(struct mmc *mmc); + +#else struct mmc_ops { int (*send_cmd)(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data); @@ -331,10 +377,13 @@ struct mmc_ops { int (*getcd)(struct mmc *mmc); int (*getwp)(struct mmc *mmc); }; +#endif struct mmc_config { const char *name; +#ifndef CONFIG_DM_MMC_OPS const struct mmc_ops *ops; +#endif uint host_caps; uint voltages; uint f_min; @@ -343,7 +392,12 @@ struct mmc_config { unsigned char part_type; }; -/* TODO struct mmc should be in mmc_private but it's hard to fix right now */ +/* + * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device + * with mmc_get_mmc_dev(). + * + * TODO struct mmc should be in mmc_private but it's hard to fix right now + */ struct mmc { #ifndef CONFIG_BLK struct list_head link; @@ -443,13 +497,23 @@ void mmc_set_clock(struct mmc *mmc, uint clock); struct mmc *find_mmc_device(int dev_num); int mmc_set_dev(int dev_num); void print_mmc_devices(char separator); + +/** + * get_mmc_num() - get the total MMC device number + * + * @return 0 if there is no MMC device, else the number of devices + */ int get_mmc_num(void); int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf, enum mmc_hwpart_conf_mode mode); + +#ifndef CONFIG_DM_MMC_OPS int mmc_getcd(struct mmc *mmc); int board_mmc_getcd(struct mmc *mmc); int mmc_getwp(struct mmc *mmc); int board_mmc_getwp(struct mmc *mmc); +#endif + int mmc_set_dsr(struct mmc *mmc, u16 val); /* Function to change the size of boot partition and rpmb partitions */ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, diff --git a/include/nand.h b/include/nand.h index a4f0f92..b6eb223 100644 --- a/include/nand.h +++ b/include/nand.h @@ -122,6 +122,7 @@ int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length, int nand_get_lock_status(struct mtd_info *mtd, loff_t offset); int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst); +int nand_spl_read_block(int block, int offset, int len, void *dst); void nand_deselect(void); #ifdef CONFIG_SYS_NAND_SELECT_DEVICE @@ -141,3 +142,6 @@ __attribute__((noreturn)) void nand_boot(void); int get_nand_env_oob(struct mtd_info *mtd, unsigned long *result); #endif int spl_nand_erase_one(int block, int page); + +/* platform specific init functions */ +void sunxi_nand_init(void); diff --git a/include/net.h b/include/net.h index 5ee5929..06320c6 100644 --- a/include/net.h +++ b/include/net.h @@ -238,7 +238,7 @@ int eth_getenv_enetaddr(const char *name, uchar *enetaddr); int eth_setenv_enetaddr(const char *name, const uchar *enetaddr); /** - * eth_setenv_enetaddr_by_index() - set the MAC address envrionment variable + * eth_setenv_enetaddr_by_index() - set the MAC address environment variable * * This sets up an environment variable with the given MAC address (@enetaddr). * The environment variable to be set is defined by <@base_name><@index>addr. diff --git a/include/nuvoton_nct6102d.h b/include/nuvoton_nct6102d.h new file mode 100644 index 0000000..a122550 --- /dev/null +++ b/include/nuvoton_nct6102d.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _NUVOTON_NCT6102D_H_ +#define _NUVOTON_NCT6102D_H_ + +/* I/O address of Nuvoton Super IO chip */ +#define NCT6102D_IO_PORT 0x4e + +/* Extended Function Enable Registers */ +#define NCT_EFER (NCT6102D_IO_PORT + 0) +/* Extended Function Index Register (same as EFER) */ +#define NCT_EFIR (NCT6102D_IO_PORT + 0) +/* Extended Function Data Register */ +#define NCT_EFDR (NCT_EFIR + 1) + +#define NCT_LD_SELECT_REG 0x07 + +/* Logical device number */ +#define NCT6102D_LD_UARTA 0x02 +#define NCT6102D_LD_WDT 0x08 + +#define NCT6102D_UARTA_ENABLE 0x30 +#define NCT6102D_WDT_TIMEOUT 0xf1 + +#define NCT_ENTRY_KEY 0x87 +#define NCT_EXIT_KEY 0xaa + +int nct6102d_wdt_disable(void); + +#endif /* _NUVOTON_NCT6102D_H_ */ diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h index fd01040..995f0aa 100644 --- a/include/onenand_uboot.h +++ b/include/onenand_uboot.h @@ -26,7 +26,7 @@ extern struct mtd_info onenand_mtd; extern struct onenand_chip onenand_chip; /* board */ -extern void onenand_board_init(struct mtd_info *); +extern int onenand_board_init(struct mtd_info *); /* Functions */ extern void onenand_init(void); @@ -49,6 +49,7 @@ extern int flexonenand_set_boundary(struct mtd_info *mtd, int die, int boundary, int lock); /* SPL */ +int onenand_spl_read_block(int block, int offset, int len, void *dst); void onenand_spl_load_image(uint32_t offs, uint32_t size, void *dst); #endif /* __UBOOT_ONENAND_H */ diff --git a/include/os.h b/include/os.h index 954a48c..1782e50 100644 --- a/include/os.h +++ b/include/os.h @@ -287,6 +287,31 @@ int os_read_ram_buf(const char *fname); int os_jump_to_image(const void *dest, int size); /** + * os_find_u_boot() - Determine the path to U-Boot proper + * + * This function is intended to be called from within sandbox SPL. It uses + * a few heuristics to find U-Boot proper. Normally it is either in the same + * directory, or the directory above (since u-boot-spl is normally in an + * spl/ subdirectory when built). + * + * @fname: Place to put full path to U-Boot + * @maxlen: Maximum size of @fname + * @return 0 if OK, -NOSPC if the filename is too large, -ENOENT if not found + */ +int os_find_u_boot(char *fname, int maxlen); + +/** + * os_spl_to_uboot() - Run U-Boot proper + * + * When called from SPL, this runs U-Boot proper. The filename is obtained by + * calling os_find_u_boot(). + * + * @fname: Full pathname to U-Boot executable + * @return 0 if OK, -ve on error + */ +int os_spl_to_uboot(const char *fname); + +/** * Read the current system time * * This reads the current Local Time and places it into the provided diff --git a/include/power-domain-uclass.h b/include/power-domain-uclass.h new file mode 100644 index 0000000..5878021 --- /dev/null +++ b/include/power-domain-uclass.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _POWER_DOMAIN_UCLASS_H +#define _POWER_DOMAIN_UCLASS_H + +/* See power-domain.h for background documentation. */ + +#include <power-domain.h> + +struct udevice; + +/** + * struct power_domain_ops - The functions that a power domain controller driver + * must implement. + */ +struct power_domain_ops { + /** + * of_xlate - Translate a client's device-tree (OF) power domain + * specifier. + * + * The power domain core calls this function as the first step in + * implementing a client's power_domain_get() call. + * + * If this function pointer is set to NULL, the power domain core will + * use a default implementation, which assumes #power-domain-cells = + * <1>, and that the DT cell contains a simple integer power domain ID. + * + * At present, the power domain API solely supports device-tree. If + * this changes, other xxx_xlate() functions may be added to support + * those other mechanisms. + * + * @power_domain: The power domain struct to hold the + * translation result. + * @args: The power domain specifier values from device + * tree. + * @return 0 if OK, or a negative error code. + */ + int (*of_xlate)(struct power_domain *power_domain, + struct fdtdec_phandle_args *args); + /** + * request - Request a translated power domain. + * + * The power domain core calls this function as the second step in + * implementing a client's power_domain_get() call, following a + * successful xxx_xlate() call. + * + * @power_domain: The power domain to request; this has been + * filled in by a previous xxx_xlate() function + * call. + * @return 0 if OK, or a negative error code. + */ + int (*request)(struct power_domain *power_domain); + /** + * free - Free a previously requested power domain. + * + * This is the implementation of the client power_domain_free() API. + * + * @power_domain: The power domain to free. + * @return 0 if OK, or a negative error code. + */ + int (*free)(struct power_domain *power_domain); + /** + * on - Power on a power domain. + * + * @power_domain: The power domain to turn on. + * @return 0 if OK, or a negative error code. + */ + int (*on)(struct power_domain *power_domain); + /** + * off - Power off a power domain. + * + * @power_domain: The power domain to turn off. + * @return 0 if OK, or a negative error code. + */ + int (*off)(struct power_domain *power_domain); +}; + +#endif diff --git a/include/power-domain.h b/include/power-domain.h new file mode 100644 index 0000000..1099979 --- /dev/null +++ b/include/power-domain.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _POWER_DOMAIN_H +#define _POWER_DOMAIN_H + +/** + * A power domain is a portion of an SoC or chip that is powered by a + * switchable source of power. In many cases, software has control over the + * power domain, and can turn the power source on or off. This is typically + * done to save power by powering off unused devices, or to enable software + * sequencing of initial powerup at boot. This API provides a means for + * drivers to turn power domains on and off. + * + * A driver that implements UCLASS_POWER_DOMAIN is a power domain controller or + * provider. A controller will often implement multiple separate power domains, + * since the hardware it manages often has this capability. + * power-domain-uclass.h describes the interface which power domain controllers + * must implement. + * + * Depending on the power domain controller hardware, changing the state of a + * power domain may require performing related operations on other resources. + * For example, some power domains may require certain clocks to be enabled + * whenever the power domain is powered on, or during the time when the power + * domain is transitioning state. These details are implementation-specific + * and should ideally be encapsulated entirely within the provider driver, or + * configured through mechanisms (e.g. device tree) that do not require client + * drivers to provide extra configuration information. + * + * Power domain consumers/clients are the drivers for HW modules within the + * power domain. This header file describes the API used by those drivers. + * + * In many cases, a single complex IO controller (e.g. a PCIe controller) will + * be the sole logic contained within a power domain. In such cases, it is + * logical for the relevant device driver to directly control that power + * domain. In other cases, multiple controllers, each with their own driver, + * may be contained in a single power domain. Any logic require to co-ordinate + * between drivers for these multiple controllers is beyond the scope of this + * API at present. Equally, this API does not define or implement any policy + * by which power domains are managed. + */ + +struct udevice; + +/** + * struct power_domain - A handle to (allowing control of) a single power domain. + * + * Clients provide storage for power domain handles. The content of the + * structure is managed solely by the power domain API and power domain + * drivers. A power domain struct is initialized by "get"ing the power domain + * struct. The power domain struct is passed to all other power domain APIs to + * identify which power domain to operate upon. + * + * @dev: The device which implements the power domain. + * @id: The power domain ID within the provider. + * + * Currently, the power domain API assumes that a single integer ID is enough + * to identify and configure any power domain for any power domain provider. If + * this assumption becomes invalid in the future, the struct could be expanded + * to either (a) add more fields to allow power domain providers to store + * additional information, or (b) replace the id field with an opaque pointer, + * which the provider would dynamically allocate during its .of_xlate op, and + * process during is .request op. This may require the addition of an extra op + * to clean up the allocation. + */ +struct power_domain { + struct udevice *dev; + /* + * Written by of_xlate. We assume a single id is enough for now. In the + * future, we might add more fields here. + */ + unsigned long id; +}; + +/** + * power_domain_get - Get/request the power domain for a device. + * + * This looks up and requests a power domain. Each device is assumed to have + * a single (or, at least one) power domain associated with it somehow, and + * that domain, or the first/default domain. The mapping of client device to + * provider power domain may be via device-tree properties, board-provided + * mapping tables, or some other mechanism. + * + * @dev: The client device. + * @power_domain A pointer to a power domain struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int power_domain_get(struct udevice *dev, struct power_domain *power_domain); + +/** + * power_domain_free - Free a previously requested power domain. + * + * @power_domain: A power domain struct that was previously successfully + * requested by power_domain_get(). + * @return 0 if OK, or a negative error code. + */ +int power_domain_free(struct power_domain *power_domain); + +/** + * power_domain_on - Enable power to a power domain. + * + * @power_domain: A power domain struct that was previously successfully + * requested by power_domain_get(). + * @return 0 if OK, or a negative error code. + */ +int power_domain_on(struct power_domain *power_domain); + +/** + * power_domain_off - Disable power ot a power domain. + * + * @power_domain: A power domain struct that was previously successfully + * requested by power_domain_get(). + * @return 0 if OK, or a negative error code. + */ +int power_domain_off(struct power_domain *power_domain); + +#endif diff --git a/include/power/regulator.h b/include/power/regulator.h index 63c0814..9bcd728 100644 --- a/include/power/regulator.h +++ b/include/power/regulator.h @@ -54,7 +54,7 @@ * which does the scan on the device node, for the 'regulator-name' constraint. * If the parent is not a PMIC device, and the child is not bind by function: * 'pmic_bind_childs()', then it's recommended to bind the device by call to - * dm_scan_fdt_node() - this is usually done automatically for bus devices, + * dm_scan_fdt_dev() - this is usually done automatically for bus devices, * as a post bind method. * * Regulator get: diff --git a/include/regmap.h b/include/regmap.h index eccf770..1eed94e 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -57,6 +57,22 @@ int regmap_read(struct regmap *map, uint offset, uint *valp); int regmap_init_mem(struct udevice *dev, struct regmap **mapp); /** + * regmap_init_mem_platdata() - Set up a new memory register map for of-platdata + * + * This creates a new regmap with a list of regions passed in, rather than + * using the device tree. It only supports 32-bit machines. + * + * Use regmap_uninit() to free it. + * + * @dev: Device that uses this map + * @reg: List of address, size pairs + * @count: Number of pairs (e.g. 1 if the regmap has a single entry) + * @mapp: Returns allocated map + */ +int regmap_init_mem_platdata(struct udevice *dev, u32 *reg, int count, + struct regmap **mapp); + +/** * regmap_get_range() - Obtain the base memory address of a regmap range * * @map: Regmap to query diff --git a/include/sdhci.h b/include/sdhci.h index e0f6667..6844c73 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -166,6 +166,8 @@ #define SDHCI_CAN_64BIT 0x10000000 #define SDHCI_CAPABILITIES_1 0x44 +#define SDHCI_CLOCK_MUL_MASK 0x00FF0000 +#define SDHCI_CLOCK_MUL_SHIFT 16 #define SDHCI_MAX_CURRENT 0x48 @@ -338,5 +340,78 @@ static inline u8 sdhci_readb(struct sdhci_host *host, int reg) } #endif +#ifdef CONFIG_BLK +/** + * sdhci_setup_cfg() - Set up the configuration for DWMMC + * + * This is used to set up an SDHCI device when you are using CONFIG_BLK. + * + * This should be called from your MMC driver's probe() method once you have + * the information required. + * + * Generally your driver will have a platform data structure which holds both + * the configuration (struct mmc_config) and the MMC device info (struct mmc). + * For example: + * + * struct msm_sdhc_plat { + * struct mmc_config cfg; + * struct mmc mmc; + * }; + * + * ... + * + * Inside U_BOOT_DRIVER(): + * .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat), + * + * To access platform data: + * struct msm_sdhc_plat *plat = dev_get_platdata(dev); + * + * See msm_sdhci.c for an example. + * + * @cfg: Configuration structure to fill in (generally &plat->mmc) + * @host: SDHCI host structure + * @max_clk: Maximum supported clock speed in HZ (0 for default) + * @min_clk: Minimum supported clock speed in HZ (0 for default) + */ +int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, + u32 max_clk, u32 min_clk); + +/** + * sdhci_bind() - Set up a new MMC block device + * + * This is used to set up an SDHCI block device when you are using CONFIG_BLK. + * It should be called from your driver's bind() method. + * + * See msm_sdhci.c for an example. + * + * @dev: Device to set up + * @mmc: Pointer to mmc structure (normally &plat->mmc) + * @cfg: Empty configuration structure (generally &plat->cfg). This is + * normally all zeroes at this point. The only purpose of passing + * this in is to set mmc->cfg to it. + * @return 0 if OK, -ve if the block device could not be created + */ +int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); +#else + +/** + * add_sdhci() - Add a new SDHCI interface + * + * This is used when you are not using CONFIG_BLK. Convert your driver over! + * + * @host: SDHCI host structure + * @max_clk: Maximum supported clock speed in HZ (0 for default) + * @min_clk: Minimum supported clock speed in HZ (0 for default) + * @return 0 if OK, -ve on error + */ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk); +#endif /* !CONFIG_BLK */ + +#ifdef CONFIG_DM_MMC_OPS +/* Export the operations to drivers */ +int sdhci_probe(struct udevice *dev); +extern const struct dm_mmc_ops sdhci_ops; +#else +#endif + #endif /* __SDHCI_HW_H */ diff --git a/include/spl.h b/include/spl.h index 2360466..8afa085 100644 --- a/include/spl.h +++ b/include/spl.h @@ -71,6 +71,7 @@ void spl_set_header_raw_uboot(void); int spl_parse_image_header(const struct image_header *header); void spl_board_prepare_for_linux(void); void spl_board_prepare_for_boot(void); +int spl_board_ubi_load_image(u32 boot_device); void __noreturn jump_to_image_linux(void *arg); int spl_start_uboot(void); void spl_display_print(void); @@ -84,6 +85,9 @@ int spl_onenand_load_image(void); /* NOR SPL functions */ int spl_nor_load_image(void); +/* UBI SPL functions */ +int spl_ubi_load_image(u32 boot_device); + /* MMC SPL functions */ int spl_mmc_load_image(u32 boot_device); diff --git a/include/splash.h b/include/splash.h index 25df1cf..136eac7 100644 --- a/include/splash.h +++ b/include/splash.h @@ -47,7 +47,16 @@ struct splash_location { char *ubivol; /* UBI volume-name for ubifsmount */ }; +#ifdef CONFIG_SPLASH_SOURCE int splash_source_load(struct splash_location *locations, uint size); +#else +static inline int splash_source_load(struct splash_location *locations, + uint size) +{ + return 0; +} +#endif + int splash_screen_prepare(void); #ifdef CONFIG_SPLASH_SCREEN_ALIGN diff --git a/include/syscon.h b/include/syscon.h index 4593b6e..34842aa 100644 --- a/include/syscon.h +++ b/include/syscon.h @@ -23,6 +23,17 @@ struct syscon_ops { #define syscon_get_ops(dev) ((struct syscon_ops *)(dev)->driver->ops) +#if CONFIG_IS_ENABLED(OF_PLATDATA) +/* + * We don't support 64-bit machines. If they are so resource-contrained that + * they need to use OF_PLATDATA, something is horribly wrong with the + * education of our hardware engineers. + */ +struct syscon_base_platdata { + u32 reg[2]; +}; +#endif + /** * syscon_get_regmap() - Get access to a register map * diff --git a/include/test/overlay.h b/include/test/overlay.h new file mode 100644 index 0000000..392f28f --- /dev/null +++ b/include/test/overlay.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2016 NextThing Co + * Copyright (c) 2016 Free Electrons + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TEST_OVERLAY_H__ +#define __TEST_OVERLAY_H__ + +#include <test/test.h> + +/* Declare a new environment test */ +#define OVERLAY_TEST(_name, _flags) UNIT_TEST(_name, _flags, overlay_test) + +#endif /* __TEST_OVERLAY_H__ */ diff --git a/include/test/suites.h b/include/test/suites.h index f579033..0e94feb 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -10,6 +10,7 @@ int do_ut_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_env(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); #endif /* __TEST_SUITES_H__ */ diff --git a/include/ubispl.h b/include/ubispl.h new file mode 100644 index 0000000..944653e --- /dev/null +++ b/include/ubispl.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) Thomas Gleixner <tglx@linutronix.de> + * + * SPDX-License-Identifier: GPL 2.0+ BSD-3-Clause + */ +#ifndef __UBOOT_UBISPL_H +#define __UBOOT_UBISPL_H + +/* + * The following CONFIG options are relevant for UBISPL + * + * #define CONFIG_SPL_UBI_MAX_VOL_LEBS 256 + * + * Defines the maximum number of logical erase blocks per loadable + * (static) volume to size the ubispl internal arrays. + * + * #define CONFIG_SPL_UBI_MAX_PEB_SIZE (256*1024) + * + * Defines the maximum physical erase block size to size the fastmap + * buffer for ubispl. + * + * #define CONFIG_SPL_UBI_MAX_PEBS 4096 + * + * Define the maximum number of physical erase blocks to size the + * ubispl internal arrays. + * + * #define CONFIG_SPL_UBI_VOL_IDS 8 + * + * Defines the maximum number of volumes in which UBISPL is + * interested. Limits the amount of memory for the scan data and + * speeds up the scan process as we simply ignore stuff which we dont + * want to load from the SPL anyway. So the volumes which can be + * loaded in the above example are ids 0 - 7 + */ + +/* + * The struct definition is in drivers/mtd/ubispl/ubispl.h. It does + * not fit into the BSS due to the large buffer requirement of the + * upstream fastmap code. So the caller of ubispl_load_volumes needs + * to hand in a pointer to a free memory area where ubispl will place + * its data. The area is not required to be initialized. + */ +struct ubi_scan_info; + +typedef int (*ubispl_read_flash)(int pnum, int offset, int len, void *dst); + +/** + * struct ubispl_info - description structure for fast ubi scan + * @ubi: Pointer to memory space for ubi scan info structure + * @peb_size: Physical erase block size + * @vid_offset: Offset of the VID header + * @leb_start: Start of the logical erase block, i.e. offset of data + * @peb_count: Number of physical erase blocks in the UBI FLASH area + * aka MTD partition. + * @peb_offset: Offset of PEB0 in the UBI FLASH area (aka MTD partition) + * to the real start of the FLASH in erase blocks. + * @fastmap: Enable fastmap attachment + * @read: Read function to access the flash + */ +struct ubispl_info { + struct ubi_scan_info *ubi; + u32 peb_size; + u32 vid_offset; + u32 leb_start; + u32 peb_count; + u32 peb_offset; + int fastmap; + ubispl_read_flash read; +}; + +/** + * struct ubispl_load - structure to describe a volume to load + * @vol_id: Volume id + * @load_addr: Load address of the volume + */ +struct ubispl_load { + int vol_id; + void *load_addr; +}; + +/** + * ubispl_load_volumes - Scan flash and load volumes + * @info: Pointer to the ubi scan info structure + * @lovls: Pointer to array of volumes to load + * @nrvols: Array size of @lovls + */ +int ubispl_load_volumes(struct ubispl_info *info, + struct ubispl_load *lvols, int nrvols); + +#endif diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h index 302e9a3..7324d8a 100644 --- a/include/usb/dwc2_udc.h +++ b/include/usb/dwc2_udc.h @@ -12,12 +12,17 @@ #define PHY0_SLEEP (1 << 5) struct dwc2_plat_otg_data { + void *priv; + int phy_of_node; int (*phy_control)(int on); unsigned int regs_phy; unsigned int regs_otg; unsigned int usb_phy_ctrl; unsigned int usb_flags; unsigned int usb_gusbcfg; + unsigned int rx_fifo_sz; + unsigned int np_tx_fifo_sz; + unsigned int tx_fifo_sz; }; int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata); diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index 586d32a..882aed4 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -160,7 +160,7 @@ #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR 0 #elif defined(CONFIG_LS102XA) -#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR +#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR 0 #endif diff --git a/include/vsprintf.h b/include/vsprintf.h index 376f5dd..60e91d1 100644 --- a/include/vsprintf.h +++ b/include/vsprintf.h @@ -8,6 +8,8 @@ #ifndef __VSPRINTF_H #define __VSPRINTF_H +#include <stdarg.h> + ulong simple_strtoul(const char *cp, char **endp, unsigned int base); /** |