diff options
Diffstat (limited to 'include')
46 files changed, 393 insertions, 77 deletions
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 4407b45..ad4cbd8 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -329,6 +329,7 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index d5e6c4b..823cba6 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -32,11 +32,15 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_I2C_MULTI_EEPROMS +/* Power */ +#define CONFIG_POWER_TPS65218 + /* SPL defines. */ #define CONFIG_SPL_TEXT_BASE 0x40300350 #define CONFIG_SPL_MAX_SIZE (220 << 10) /* 220KB */ #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ (128 << 20)) +#define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_YMODEM_SUPPORT /* Enabling L2 Cache */ @@ -48,15 +52,24 @@ * Since SPL did pll and ddr initialization for us, * we don't need to do it twice. */ -#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_QSPI_BOOT) #define CONFIG_SKIP_LOWLEVEL_INIT #endif +/* + * When building U-Boot such that there is no previous loader + * we need to call board_early_init_f. This is taken care of in + * s_init when we have SPL used. + */ +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL) +#define CONFIG_BOARD_EARLY_INIT_F +#endif + /* Now bring in the rest of the common code. */ #include <configs/ti_armv7_common.h> -/* Always 128 KiB env size */ -#define CONFIG_ENV_SIZE (128 << 10) +/* Always 64 KiB env size */ +#define CONFIG_ENV_SIZE (64 << 10) #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG @@ -86,6 +99,30 @@ #define CONFIG_OMAP_USB_PHY #define CONFIG_AM437X_USB2PHY2_HOST +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_TEXT_BASE 0x30000000 +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */ +#define CONFIG_ENV_OFFSET 0x110000 +#define CONFIG_ENV_OFFSET_REDUND 0x120000 +#ifdef MTDIDS_DEFAULT +#undef MTDIDS_DEFAULT +#endif +#ifdef MTDPARTS_DEFAULT +#undef MTDPARTS_DEFAULT +#endif +#define MTDPARTS_DEFAULT "mtdparts=qspi.0:512k(QSPI.u-boot)," \ + "512k(QSPI.u-boot.backup)," \ + "512k(QSPI.u-boot-spl-os)," \ + "64k(QSPI.u-boot-env)," \ + "64k(QSPI.u-boot-env.backup)," \ + "8m(QSPI.kernel)," \ + "-(QSPI.file-system)" +#endif + /* SPI */ #undef CONFIG_OMAP3_SPI #define CONFIG_TI_QSPI @@ -94,6 +131,7 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_SPI #define CONFIG_TI_SPI_MMAP +#define CONFIG_SPI_FLASH_BAR #define CONFIG_QSPI_SEL_GPIO 48 #define CONFIG_SF_DEFAULT_SPEED 48000000 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 @@ -145,6 +183,7 @@ "loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ "mmcboot=mmc dev ${mmcdev}; " \ "setenv devnum ${mmcdev}; " \ + "setenv devtype mmc; " \ "if mmc rescan; then " \ "echo SD/MMC found on device ${devnum};" \ "if run loadbootenv; then " \ diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 515facf..30ecd45 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -224,8 +224,8 @@ /* PMIC */ #define CONFIG_PMIC -#define CONFIG_PMIC_I2C -#define CONFIG_PMIC_MAX77686 +#define CONFIG_POWER_I2C +#define CONFIG_POWER_MAX77686 #define CONFIG_DEFAULT_DEVICE_TREE exynos5250-arndale diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 9ff089e..ae83112 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -76,6 +76,7 @@ /* USB Host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB @@ -87,6 +88,7 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP +#include "tegra-common-ums.h" #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 7adc8c0..5a37536 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -12,6 +12,8 @@ #ifndef __BUR_AM335X_COMMON_H__ #define __BUR_AM335X_COMMON_H__ /* ------------------------------------------------------------------------- */ +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_AM33XX #define CONFIG_OMAP #define CONFIG_OMAP_COMMON @@ -94,7 +96,7 @@ #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 #define CONFIG_SYS_I2C_OMAP24XX - +#define CONFIG_CMD_I2C /* GPIO */ #define CONFIG_OMAP_GPIO #define CONFIG_CMD_GPIO diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index 26b615b..4d1dd28 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -141,7 +141,6 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 #define CONFIG_CMD_NAND -#define GPMC_NAND_ECC_LP_x8_LAYOUT #define MTDIDS_DEFAULT "nand0=nand" #define MTDPARTS_DEFAULT "mtdparts=nand:2m(spl)," \ "1m(u-boot),1m(u-boot-env)," \ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index aae05e0..8c60e22 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -158,7 +158,6 @@ /* CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -#define GPMC_NAND_ECC_LP_x8_LAYOUT /* Environment information */ #define CONFIG_BOOTDELAY 3 diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 16a00eb..5308790 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -314,6 +314,7 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/dig297.h b/include/configs/dig297.h index af6f56b..ce205e9 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -138,6 +138,7 @@ * Board NAND Info. */ #define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ diff --git a/include/configs/exynos4-dt.h b/include/configs/exynos4-dt.h index cbd2d20..44e6ab4 100644 --- a/include/configs/exynos4-dt.h +++ b/include/configs/exynos4-dt.h @@ -20,6 +20,7 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_COMMON +#define CONFIG_SYS_GENERIC_BOARD /* Enable fdt support */ #define CONFIG_OF_CONTROL @@ -44,6 +45,9 @@ #define CONFIG_S5P_SDHCI #define CONFIG_SDHCI #define CONFIG_MMC_SDMA +#define CONFIG_DWMMC +#define CONFIG_EXYNOS_DWMMC +#define CONFIG_BOUNCE_BUFFER #define CONFIG_MMC_DEFAULT_DEV 0 /* PWM */ diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h index 5a9b1b4..b830495 100644 --- a/include/configs/exynos5-dt.h +++ b/include/configs/exynos5-dt.h @@ -259,6 +259,7 @@ /* PMIC */ #define CONFIG_POWER #define CONFIG_POWER_I2C +#define CONFIG_POWER_TPS65090 /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index b7ff472..9d1d56a 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -45,7 +45,7 @@ #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK /* PMIC */ -#define CONFIG_PMIC_MAX77686 +#define CONFIG_POWER_MAX77686 /* Sound */ #define CONFIG_CMD_SOUND diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 6255750..0b9e5b6 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -63,6 +63,7 @@ /* USB Host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB @@ -74,6 +75,7 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP +#include "tegra-common-ums.h" #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index dde7329..6ba7e62 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -71,7 +71,8 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 K2HK_UART0_BASE +#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE +#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE #define CONFIG_SYS_NS16550_CLK clk_get_rate(K2HK_CLK1_6) #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 @@ -130,6 +131,7 @@ /* NAND Configuration */ #define CONFIG_NAND_DAVINCI +#define CONFIG_CMD_NAND_ECCLAYOUT #define CONFIG_SYS_NAND_CS 2 #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index aff2419..d464ad9 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -107,7 +107,7 @@ #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_POWER_FSL -#define CONFIG_PMIC_FSL_MC34704 +#define CONFIG_POWER_FSL_MC34704 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x54 #define CONFIG_DOS_PARTITION diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 0a46f4c..ab48144 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -52,7 +52,7 @@ #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_POWER_FSL -#define CONFIG_PMIC_FSL_MC13892 +#define CONFIG_POWER_FSL_MC13892 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08 #define CONFIG_RTC_MC13XXX diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 5bbae8c..fb2072d 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -47,7 +47,7 @@ #define CONFIG_POWER_I2C #define CONFIG_POWER_FSL #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8 -#define CONFIG_PMIC_FSL_MC13892 +#define CONFIG_POWER_FSL_MC13892 #define CONFIG_RTC_MC13XXX /* MMC Configs */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 12d79b4..a74508c 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -82,7 +82,7 @@ #define CONFIG_POWER_I2C #define CONFIG_DIALOG_POWER #define CONFIG_POWER_FSL -#define CONFIG_PMIC_FSL_MC13892 +#define CONFIG_POWER_FSL_MC13892 #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 0a7df60..c023483 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -295,6 +295,7 @@ #define CONFIG_SPL_OMAP3_ID_NAND /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 7f3424b..ae4ce63 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -120,7 +120,7 @@ /* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 - +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 /* Timeout values (in ticks) */ #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index d56d5b0..79daabd 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -187,6 +187,7 @@ /* NAND boot config */ #ifdef CONFIG_NAND +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 0d03c75..8dcbba3 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -141,6 +141,7 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ /* NAND devices */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ #define CONFIG_JFFS2_DEV "nand0" diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 7b97be9..1a13633 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -206,6 +206,7 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 7c5540f..3efe4cf 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -98,6 +98,7 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 /* Environment information */ diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index fc25966..8510405 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -149,7 +149,6 @@ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -#define GPMC_NAND_ECC_LP_x8_LAYOUT 1 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ "128k(SPL.backup1)," \ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 799d4fe..fce1716 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -17,6 +17,7 @@ #define CONFIG_S5PC110 1 /* which is in a S5PC110 */ #define CONFIG_MACH_GONI 1 /* working with Goni */ +#include <linux/sizes.h> #include <asm/arch/cpu.h> /* get chip and board defs */ #define CONFIG_ARCH_CPU_INIT @@ -38,11 +39,9 @@ #define CONFIG_INITRD_TAG #define CONFIG_CMDLINE_EDITING -/* - * Size of malloc() pool - * 1MB = 0x100000, 0x100000 = 1024 * 1024 - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) +/* Size of malloc() pool.*/ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 80 * SZ_1M) + /* * select serial console configuration */ @@ -72,14 +71,19 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_REGINFO #define CONFIG_CMD_ONENAND -#define CONFIG_CMD_MTDPARTS #define CONFIG_CMD_MMC +#define CONFIG_CMD_DFU +#define CONFIG_CMD_GPT -#define CONFIG_BOOTDELAY 1 -#define CONFIG_ZERO_BOOTDELAY_CHECK +/* USB Composite download gadget - g_dnl */ +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS +/* USB Samsung's IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x04E8 +#define CONFIG_G_DNL_PRODUCT_NUM 0x6601 +#define CONFIG_G_DNL_MANUFACTURER "Samsung" /* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */ #define MTDIDS_DEFAULT "onenand0=samsung-onenand" @@ -90,30 +94,52 @@ ",7m(kernel)"\ ",1m(log)"\ ",12m(modem)"\ - ",60m(qboot)"\ - ",-(UBI)\0" + ",60m(qboot)\0" -#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT +#define CONFIG_BOOTDELAY 1 +#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_BOOTCOMMAND "run ubifsboot" +/* partitions definitions */ +#define PARTS_CSA "csa-mmc" +#define PARTS_BOOTLOADER "u-boot" +#define PARTS_BOOT "boot" +#define PARTS_ROOT "platform" +#define PARTS_DATA "data" +#define PARTS_CSC "csc" +#define PARTS_UMS "ums" + +#define CONFIG_DFU_ALT \ + "u-boot raw 0x80 0x400;" \ + "uImage ext4 0 2;" \ + "exynos3-goni.dtb ext4 0 2;" \ + ""PARTS_ROOT" part 0 5\0" + +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ + "name="PARTS_BOOTLOADER",size=60MiB," \ + "uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \ + "name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ + "name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ + "name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ + "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ + "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ + +#define CONFIG_BOOTCOMMAND "run mmcboot" #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" -#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext2" \ +#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext4" \ " ${console} ${meminfo}" #define CONFIG_COMMON_BOOT "${console} ${meminfo} ${mtdparts}" -#define CONFIG_BOOTARGS "root=/dev/mtdblock8 ubi.mtd=8 ubi.mtd=3 ubi.mtd=6" \ - " rootfstype=cramfs " CONFIG_COMMON_BOOT +#define CONFIG_BOOTARGS "root=/dev/mtdblock8 rootfstype=ext4 " \ + CONFIG_COMMON_BOOT #define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x100000;" \ " onenand write 0x32008000 0x0 0x100000\0" -#define CONFIG_UBI_MTD " ubi.mtd=${ubiblock} ubi.mtd=3 ubi.mtd=6" - -#define CONFIG_UBIFS_OPTION "rootflags=bulk_read,no_chk_data_crc" - #define CONFIG_MISC_COMMON #define CONFIG_MISC_INIT_R @@ -130,42 +156,44 @@ "onenand erase 0x01560000 0x1eaa0000;" \ "onenand write 0x32000000 0x1260000 0x8C0000\0" \ "bootk=" \ - "onenand read 0x30007FC0 0xc00000 0x600000;" \ + "run loaduimage;" \ "bootm 0x30007FC0\0" \ "flashboot=" \ "set bootargs root=/dev/mtdblock${bootblock} " \ - "rootfstype=${rootfstype}" CONFIG_UBI_MTD " ${opts} " \ + "rootfstype=${rootfstype} ${opts} " \ "${lcdinfo} " CONFIG_COMMON_BOOT "; run bootk\0" \ "ubifsboot=" \ "set bootargs root=ubi0!rootfs rootfstype=ubifs " \ - CONFIG_UBIFS_OPTION CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \ + "${opts} ${lcdinfo} " \ CONFIG_COMMON_BOOT "; run bootk\0" \ "tftpboot=" \ "set bootargs root=ubi0!rootfs rootfstype=ubifs " \ - CONFIG_UBIFS_OPTION CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \ - CONFIG_COMMON_BOOT "; tftp 0x30007FC0 uImage; " \ - "bootm 0x30007FC0\0" \ + "${opts} ${lcdinfo} " CONFIG_COMMON_BOOT \ + "; tftp 0x30007FC0 uImage; bootm 0x30007FC0\0" \ "ramboot=" \ "set bootargs " CONFIG_RAMDISK_BOOT \ - " initrd=0x33000000,8M ramdisk=8192\0" \ + "initrd=0x33000000,8M ramdisk=8192\0" \ "mmcboot=" \ - "set bootargs root=${mmcblk} rootfstype=${rootfstype}" \ - CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \ + "set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ + "rootfstype=${rootfstype} ${opts} ${lcdinfo} " \ CONFIG_COMMON_BOOT "; run bootk\0" \ "boottrace=setenv opts initcall_debug; run bootcmd\0" \ "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ "verify=n\0" \ - "rootfstype=cramfs\0" \ + "rootfstype=ext4\0" \ "console=" CONFIG_DEFAULT_CONSOLE \ - "mtdparts=" MTDPARTS_DEFAULT \ "meminfo=mem=80M mem=256M@0x40000000 mem=128M@0x50000000\0" \ - "mmcblk=/dev/mmcblk1p1\0" \ + "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x30007FC0 uImage\0" \ + "mmcdev=0\0" \ + "mmcbootpart=2\0" \ + "mmcrootpart=5\0" \ + "partitions=" PARTS_DEFAULT \ "bootblock=9\0" \ "ubiblock=8\0" \ "ubi=enabled\0" \ - "opts=always_resume=1" + "opts=always_resume=1\0" \ + "dfu_alt_info=" CONFIG_DFU_ALT "\0" -/* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT "Goni # " @@ -202,6 +230,18 @@ #define CONFIG_DOS_PARTITION 1 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE + +/* write support for filesystems */ +#define CONFIG_FAT_WRITE +#define CONFIG_EXT4_WRITE + +/* GPT */ +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) #define CONFIG_SYS_CACHELINE_SIZE 64 @@ -226,5 +266,8 @@ #define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_S3C_UDC_OTG #define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE #endif /* __CONFIG_H */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 3522c1a..0c2f0f1 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -185,6 +185,7 @@ /* Configure the PISMO */ #define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC #define CONFIG_ENV_IS_IN_NAND #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ @@ -249,6 +250,7 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 9c04c23..1b0fee9 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -137,10 +137,10 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 /* Environment information */ #define CONFIG_BOOTDELAY 3 diff --git a/include/configs/tegra-common-ums.h b/include/configs/tegra-common-ums.h new file mode 100644 index 0000000..7bd8960 --- /dev/null +++ b/include/configs/tegra-common-ums.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _TEGRA_COMMON_UMS_H_ +#define _TEGRA_COMMON_UMS_H + +#ifndef CONFIG_SPL_BUILD +/* USB gadget, and mass storage protocol */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_CI_UDC +#define CONFIG_CI_UDC_HAS_HOSTPC +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_G_DNL_VENDOR_NUM 0x0955 +#define CONFIG_G_DNL_PRODUCT_NUM 0x701A +#define CONFIG_G_DNL_MANUFACTURER "NVIDIA" +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_CMD_USB_MASS_STORAGE +#endif + +#endif /* _TEGRA_COMMON_UMS_H */ diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 128b66e..80976e7 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -75,6 +75,15 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #endif +/* + * When building U-Boot such that there is no previous loader + * we need to call board_early_init_f. This is taken care of in + * s_init when we have SPL used. + */ +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL) +#define CONFIG_BOARD_EARLY_INIT_F +#endif + #ifdef CONFIG_NAND #define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ #endif diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 4854272..6982918 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -196,7 +196,8 @@ * under common/spl/. Given our generally common memory map, we set a * number of related defaults and sizes here. */ -#ifndef CONFIG_NOR_BOOT +#if !defined(CONFIG_NOR_BOOT) && \ + !(defined(CONFIG_QSPI_BOOT) && defined(CONFIG_AM43XX)) #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_OS_BOOT diff --git a/include/configs/tseries.h b/include/configs/tseries.h index e550afa..1fd6e32 100644 --- a/include/configs/tseries.h +++ b/include/configs/tseries.h @@ -157,7 +157,6 @@ /* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */ #define CONFIG_NAND_OMAP_ELM #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/venice2.h b/include/configs/venice2.h index 2d75f50..c4a1b94 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -63,6 +63,7 @@ /* USB Host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB @@ -74,6 +75,7 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP +#include "tegra-common-ums.h" #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index 695bc23..259205e 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -55,7 +55,7 @@ #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_POWER_FSL -#define CONFIG_PMIC_FSL_MC13892 +#define CONFIG_POWER_FSL_MC13892 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 #define CONFIG_RTC_MC13XXX diff --git a/include/dwmmc.h b/include/dwmmc.h index c9bdf51..b67f11b 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -123,6 +123,9 @@ #define DWMCI_BMOD_IDMAC_FB (1 << 1) #define DWMCI_BMOD_IDMAC_EN (1 << 7) +/* UHS register */ +#define DWMCI_DDR_MODE (1 << 16) + /* quirks */ #define DWMCI_QUIRK_DISABLE_SMU (1 << 0) @@ -134,7 +137,9 @@ struct dwmci_host { unsigned int version; unsigned int clock; unsigned int bus_hz; + unsigned int div; int dev_index; + int dev_id; int buswidth; u32 clksel_val; u32 fifoth_val; diff --git a/include/fdtdec.h b/include/fdtdec.h index 3196cf6..a7e6ee7 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -81,7 +81,7 @@ enum fdt_compat_id { COMPAT_SAMSUNG_EXYNOS_FIMD, /* Exynos Display controller */ COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */ COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */ - COMPAT_SAMSUNG_EXYNOS5_DWMMC, /* Exynos5 DWMMC controller */ + COMPAT_SAMSUNG_EXYNOS_DWMMC, /* Exynos DWMMC controller */ COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */ COMPAT_SAMSUNG_EXYNOS_SERIAL, /* Exynos UART */ COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */ @@ -92,6 +92,8 @@ enum fdt_compat_id { COMPAT_SAMSUNG_EXYNOS5_I2C, /* Exynos5 High Speed I2C Controller */ COMPAT_SANDBOX_HOST_EMULATION, /* Sandbox emulation of a function */ COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */ + COMPAT_TI_TPS65090, /* Texas Instrument TPS65090 */ + COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */ COMPAT_COUNT, }; diff --git a/include/initcall.h b/include/initcall.h index 2378077..65f67dc 100644 --- a/include/initcall.h +++ b/include/initcall.h @@ -6,4 +6,4 @@ typedef int (*init_fnc_t)(void); -int initcall_run_list(init_fnc_t init_sequence[]); +int initcall_run_list(const init_fnc_t init_sequence[]); diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 0546565..991bd8e 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -719,4 +719,23 @@ static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) } #endif +/** + * Check if the opcode's address should be sent only on the lower 8 bits + * @command: opcode to check + */ +static inline int nand_opcode_8bits(unsigned int command) +{ + switch (command) { + case NAND_CMD_READID: + case NAND_CMD_PARAM: + case NAND_CMD_GET_FEATURES: + case NAND_CMD_SET_FEATURES: + return 1; + default: + break; + } + return 0; +} + + #endif /* __LINUX_MTD_NAND_H */ diff --git a/include/linux/mtd/omap_elm.h b/include/linux/mtd/omap_elm.h index 45454ea..b8096b0 100644 --- a/include/linux/mtd/omap_elm.h +++ b/include/linux/mtd/omap_elm.h @@ -24,6 +24,9 @@ #define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100) #define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F) +#define ELM_MAX_CHANNELS 8 +#define ELM_MAX_ERROR_COUNT 16 + #ifndef __ASSEMBLY__ enum bch_level { @@ -43,7 +46,7 @@ struct syndrome { struct location { u32 location_status; /* 0x800 */ u8 res1[124]; /* 0x804 */ - u32 error_location_x[16]; /* 0x880.... */ + u32 error_location_x[ELM_MAX_ERROR_COUNT]; /* 0x880, 0x980, .. */ u8 res2[64]; /* 0x8c0 */ }; @@ -63,12 +66,12 @@ struct elm { u8 res2[92]; /* 0x024 */ u32 page_ctrl; /* 0x080 */ u8 res3[892]; /* 0x084 */ - struct syndrome syndrome_fragments[8]; /* 0x400 */ + struct syndrome syndrome_fragments[ELM_MAX_CHANNELS]; /* 0x400,0x420 */ u8 res4[512]; /* 0x600 */ - struct location error_location[8]; /* 0x800 */ + struct location error_location[ELM_MAX_CHANNELS]; /* 0x800,0x900 ... */ }; -int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, +int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count, u32 *error_locations); int elm_config(enum bch_level level); void elm_reset(void); diff --git a/include/linux/mtd/omap_gpmc.h b/include/linux/mtd/omap_gpmc.h index 22f6573..9a86582 100644 --- a/include/linux/mtd/omap_gpmc.h +++ b/include/linux/mtd/omap_gpmc.h @@ -11,6 +11,7 @@ #define GPMC_BUF_EMPTY 0 #define GPMC_BUF_FULL 1 +#define GPMC_MAX_SECTORS 8 enum omap_ecc { /* 1-bit ECC calculation by Software, Error detection by Software */ @@ -26,6 +27,8 @@ enum omap_ecc { OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, /* 8-bit ECC calculation by GPMC, Error detection by ELM */ OMAP_ECC_BCH8_CODE_HW, + /* 16-bit ECC calculation by GPMC, Error detection by ELM */ + OMAP_ECC_BCH16_CODE_HW, }; struct gpmc_cs { @@ -46,6 +49,10 @@ struct bch_res_0_3 { u32 bch_result_x[4]; }; +struct bch_res_4_6 { + u32 bch_result_x[3]; +}; + struct gpmc { u8 res1[0x10]; u32 sysconfig; /* 0x10 */ @@ -75,7 +82,9 @@ struct gpmc { u8 res7[12]; /* 0x224 */ u32 testmomde_ctrl; /* 0x230 */ u8 res8[12]; /* 0x234 */ - struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */ + struct bch_res_0_3 bch_result_0_3[GPMC_MAX_SECTORS]; /* 0x240,0x250, */ + u8 res9[16 * 4]; /* 0x2C0 - 0x2FF */ + struct bch_res_4_6 bch_result_4_6[GPMC_MAX_SECTORS]; /* 0x300,0x310, */ }; /* Used for board specific gpmc initialization */ diff --git a/include/mmc.h b/include/mmc.h index a3a100b..f46572e 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -32,15 +32,13 @@ #define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429) #define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405) -#define MMC_MODE_HS 0x001 -#define MMC_MODE_HS_52MHz 0x010 -#define MMC_MODE_4BIT 0x100 -#define MMC_MODE_8BIT 0x200 -#define MMC_MODE_SPI 0x400 -#define MMC_MODE_HC 0x800 - -#define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT) -#define MMC_MODE_WIDTH_BITS_SHIFT 8 +#define MMC_MODE_HS (1 << 0) +#define MMC_MODE_HS_52MHz (1 << 1) +#define MMC_MODE_4BIT (1 << 2) +#define MMC_MODE_8BIT (1 << 3) +#define MMC_MODE_SPI (1 << 4) +#define MMC_MODE_HC (1 << 5) +#define MMC_MODE_DDR_52MHz (1 << 6) #define SD_DATA_4BIT 0x00040000 @@ -100,9 +98,6 @@ #define SD_HIGHSPEED_BUSY 0x00020000 #define SD_HIGHSPEED_SUPPORTED 0x00020000 -#define MMC_HS_TIMING 0x00000100 -#define MMC_HS_52MHZ 0x2 - #define OCR_BUSY 0x80000000 #define OCR_HCS 0x40000000 #define OCR_VOLTAGE_MASK 0x007FFF80 @@ -178,10 +173,16 @@ #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2) +#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3) +#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ + | EXT_CSD_CARD_TYPE_DDR_1_2V) #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ +#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ +#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) diff --git a/include/power/max77693_pmic.h b/include/power/max77693_pmic.h index 616d051..3d59e59 100644 --- a/include/power/max77693_pmic.h +++ b/include/power/max77693_pmic.h @@ -10,8 +10,6 @@ #include <power/power_chrg.h> -enum {CHARGER_ENABLE, CHARGER_DISABLE}; - #define CHARGER_MIN_CURRENT 200 #define CHARGER_MAX_CURRENT 2000 diff --git a/include/power/max8997_pmic.h b/include/power/max8997_pmic.h index 74c5d54..728d60a 100644 --- a/include/power/max8997_pmic.h +++ b/include/power/max8997_pmic.h @@ -170,7 +170,6 @@ enum { #define SAFEOUT_3_30V 0x03 /* Charger */ -enum {CHARGER_ENABLE, CHARGER_DISABLE}; #define DETBAT (1 << 2) #define MBCICHFCSET (1 << 4) #define MBCHOSTEN (1 << 6) diff --git a/include/power/pmic.h b/include/power/pmic.h index 8f282dd..a62e6c9 100644 --- a/include/power/pmic.h +++ b/include/power/pmic.h @@ -17,6 +17,11 @@ enum { I2C_PMIC, I2C_NUM, }; enum { PMIC_READ, PMIC_WRITE, }; enum { PMIC_SENSOR_BYTE_ORDER_LITTLE, PMIC_SENSOR_BYTE_ORDER_BIG, }; +enum { + PMIC_CHARGER_DISABLE, + PMIC_CHARGER_ENABLE, +}; + struct p_i2c { unsigned char addr; unsigned char *buf; diff --git a/include/power/tps65090_pmic.h b/include/power/tps65090_pmic.h new file mode 100644 index 0000000..dcf99c9 --- /dev/null +++ b/include/power/tps65090_pmic.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TPS65090_PMIC_H_ +#define __TPS65090_PMIC_H_ + +/* I2C device address for TPS65090 PMU */ +#define TPS65090_I2C_ADDR 0x48 + +enum { + /* Status register fields */ + TPS65090_ST1_OTC = 1 << 0, + TPS65090_ST1_OCC = 1 << 1, + TPS65090_ST1_STATE_SHIFT = 4, + TPS65090_ST1_STATE_MASK = 0xf << TPS65090_ST1_STATE_SHIFT, +}; + +/** + * Enable FET + * + * @param fet_id FET ID, value between 1 and 7 + * @return 0 on success, non-0 on failure + */ +int tps65090_fet_enable(unsigned int fet_id); + +/** + * Disable FET + * + * @param fet_id FET ID, value between 1 and 7 + * @return 0 on success, non-0 on failure + */ +int tps65090_fet_disable(unsigned int fet_id); + +/** + * Is FET enabled? + * + * @param fet_id FET ID, value between 1 and 7 + * @return 1 enabled, 0 disabled, negative value on failure + */ +int tps65090_fet_is_enabled(unsigned int fet_id); + +/** + * Enable / disable the battery charger + * + * @param enable 0 to disable charging, non-zero to enable + */ +int tps65090_set_charge_enable(int enable); + +/** + * Check whether we have enabled battery charging + * + * @return 1 if enabled, 0 if disabled + */ +int tps65090_get_charging(void); + +/** + * Return the value of the status register + * + * @return status register value, or -1 on error + */ +int tps65090_get_status(void); + +/** + * Initialize the TPS65090 PMU. + * + * @return 0 on success, non-0 on failure + */ +int tps65090_init(void); + +#endif /* __TPS65090_PMIC_H_ */ diff --git a/include/power/tps65218.h b/include/power/tps65218.h new file mode 100644 index 0000000..67aa2f8 --- /dev/null +++ b/include/power/tps65218.h @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2014 + * Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __POWER_TPS65218_H__ +#define __POWER_TPS65218_H__ + +/* I2C chip address */ +#define TPS65218_CHIP_PM 0x24 + +/* Registers */ +enum { + TPS65218_CHIPID = 0x00, + TPS65218_INT1, + TPS65218_INT2, + TPS65218_INT_MASK1, + TPS65218_INT_MASK2, + TPS65218_STATUS, + TPS65218_CONTROL, + TPS65218_FLAG, + TPS65218_PASSWORD = 0x10, + TPS65218_ENABLE1, + TPS65218_ENABLE2, + TPS65218_CONFIG1, + TPS65218_CONFIG2, + TPS65218_CONFIG3, + TPS65218_DCDC1, + TPS65218_DCDC2, + TPS65218_DCDC3, + TPS65218_DCDC4, + TPS65218_SLEW, + TPS65218_LDO1, + TPS65218_SEQ1 = 0x20, + TPS65218_SEQ2, + TPS65218_SEQ3, + TPS65218_SEQ4, + TPS65218_SEQ5, + TPS65218_SEQ6, + TPS65218_SEQ7, + TPS65218_PMIC_NUM_OF_REGS, +}; + +#define TPS65218_PROT_LEVEL_NONE 0x00 +#define TPS65218_PROT_LEVEL_1 0x01 +#define TPS65218_PROT_LEVEL_2 0x02 + +#define TPS65218_PASSWORD_LOCK_FOR_WRITE 0x00 +#define TPS65218_PASSWORD_UNLOCK 0x7D + +#define TPS65218_DCDC_GO 0x80 + +#define TPS65218_MASK_ALL_BITS 0xFF + +#define TPS65218_DCDC_VOLT_SEL_1100MV 0x19 +#define TPS65218_DCDC_VOLT_SEL_1330MV 0x30 + +int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, + uchar mask); +int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel); +#endif /* __POWER_TPS65218_H__ */ |