diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-blackfin/blackfin-config-post.h | 5 | ||||
| -rw-r--r-- | include/asm-blackfin/blackfin-config-pre.h | 22 | ||||
| -rw-r--r-- | include/asm-blackfin/blackfin_local.h | 20 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf548/ports.h | 20 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-common/bits/ebiu.h | 4 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-common/bits/pata.h | 220 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-common/bits/sdh.h | 122 | ||||
| -rw-r--r-- | include/asm-blackfin/mmc.h | 1 | ||||
| -rw-r--r-- | include/asm-blackfin/posix_types.h | 20 |
9 files changed, 410 insertions, 24 deletions
diff --git a/include/asm-blackfin/blackfin-config-post.h b/include/asm-blackfin/blackfin-config-post.h index 21abd72..fea4737 100644 --- a/include/asm-blackfin/blackfin-config-post.h +++ b/include/asm-blackfin/blackfin-config-post.h @@ -67,6 +67,11 @@ # define CONFIG_LINUX_CMDLINE_SIZE L1_SRAM_SCRATCH_SIZE #endif +/* Set default SPI flash CS to the one we boot from */ +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_SPI_CS) +# define CONFIG_ENV_SPI_CS BFIN_BOOT_SPI_SSEL +#endif + /* Default/common Blackfin memory layout */ #ifndef CONFIG_SYS_SDRAM_BASE # define CONFIG_SYS_SDRAM_BASE 0 diff --git a/include/asm-blackfin/blackfin-config-pre.h b/include/asm-blackfin/blackfin-config-pre.h index 714352b..a1fae5c 100644 --- a/include/asm-blackfin/blackfin-config-pre.h +++ b/include/asm-blackfin/blackfin-config-pre.h @@ -38,4 +38,26 @@ #define BFIN_BOOT_8HOST_DMA 12 /* boot ldr from 8-bit host dma */ #define BFIN_BOOT_NAND 13 /* boot ldr from nand flash */ +#ifndef __ASSEMBLY__ +static inline const char *get_bfin_boot_mode(int bfin_boot) +{ + switch (bfin_boot) { + case BFIN_BOOT_BYPASS: return "bypass"; + case BFIN_BOOT_PARA: return "parallel flash"; + case BFIN_BOOT_SPI_MASTER: return "spi flash"; + case BFIN_BOOT_SPI_SLAVE: return "spi slave"; + case BFIN_BOOT_TWI_MASTER: return "i2c flash"; + case BFIN_BOOT_TWI_SLAVE: return "i2c slave"; + case BFIN_BOOT_UART: return "uart"; + case BFIN_BOOT_IDLE: return "idle"; + case BFIN_BOOT_FIFO: return "fifo"; + case BFIN_BOOT_MEM: return "memory"; + case BFIN_BOOT_16HOST_DMA: return "16bit dma"; + case BFIN_BOOT_8HOST_DMA: return "8bit dma"; + case BFIN_BOOT_NAND: return "nand flash"; + default: return "INVALID"; + } +} +#endif + #endif diff --git a/include/asm-blackfin/blackfin_local.h b/include/asm-blackfin/blackfin_local.h index c9ee91a..e17d8a2 100644 --- a/include/asm-blackfin/blackfin_local.h +++ b/include/asm-blackfin/blackfin_local.h @@ -43,6 +43,9 @@ #define SCLK_TO_MSEC(sclk) ((MSEC_PER_SEC * ((sclk) / USEC_PER_MSEC)) / (BFIN_SCLK / USEC_PER_MSEC)) #define MSEC_TO_SCLK(msec) ((((BFIN_SCLK / USEC_PER_MSEC) * (msec)) / MSEC_PER_SEC) * USEC_PER_MSEC) +#define L1_CACHE_SHIFT 5 +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + #include <asm/linkage.h> #ifndef __ASSEMBLY__ @@ -52,25 +55,22 @@ # include <linux/types.h> +extern u_long get_vco(void); +extern u_long get_cclk(void); extern u_long get_sclk(void); # define bfin_revid() (*pCHIPID >> 28) extern void blackfin_icache_flush_range(const void *, const void *); extern void blackfin_dcache_flush_range(const void *, const void *); +extern void blackfin_icache_dcache_flush_range(const void *, const void *); extern void blackfin_dcache_flush_invalidate_range(const void *, const void *); -/* Use DMA to move data from on chip to external memory. While this is - * required for only L1 instruction (it is not directly readable by the - * core via data loads), it isn't a huge performance issue for other - * regions (it's probably even faster than core load/stores). However, - * the DMA engine does not have access to the L1 scratchpad, and we - * cannot use DMA inside of the MMR space. +/* Use DMA to move data from on chip to external memory. The L1 instruction + * regions can only be accessed via DMA, so if the address in question is in + * that region, make sure we attempt to DMA indirectly. */ -# define addr_bfin_on_chip_mem(addr) \ - (((unsigned long)(addr) >= 0xef000000 && (unsigned long)addr < SYSMMR_BASE) && \ - !((unsigned long)(addr) >= L1_SRAM_SCRATCH && \ - (unsigned long)(addr) < L1_SRAM_SCRATCH_END)) +# define addr_bfin_on_chip_mem(addr) (((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000) # include <asm/system.h> diff --git a/include/asm-blackfin/mach-bf548/ports.h b/include/asm-blackfin/mach-bf548/ports.h index c828516..5f0e45e 100644 --- a/include/asm-blackfin/mach-bf548/ports.h +++ b/include/asm-blackfin/mach-bf548/ports.h @@ -236,7 +236,25 @@ #define PH14 0x4000 #define PH15 0x8000 -/* Port J Masks */ +/* Port I Masks */ +#define PI0 0x0001 +#define PI1 0x0002 +#define PI2 0x0004 +#define PI3 0x0008 +#define PI4 0x0010 +#define PI5 0x0020 +#define PI6 0x0040 +#define PI7 0x0080 +#define PI8 0x0100 +#define PI9 0x0200 +#define PI10 0x0400 +#define PI11 0x0800 +#define PI12 0x1000 +#define PI13 0x2000 +#define PI14 0x4000 +#define PI15 0x8000 + +/* Port I Masks */ #define PJ0 0x0001 #define PJ1 0x0002 #define PJ2 0x0004 diff --git a/include/asm-blackfin/mach-common/bits/ebiu.h b/include/asm-blackfin/mach-common/bits/ebiu.h index af456fb..7c0c569 100644 --- a/include/asm-blackfin/mach-common/bits/ebiu.h +++ b/include/asm-blackfin/mach-common/bits/ebiu.h @@ -357,8 +357,8 @@ #define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ #define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ #define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ -#define EBSZ_256 0x0007 /* SDRAM External Bank Size = 256MB */ -#define EBSZ_512 0x0008 /* SDRAM External Bank Size = 512MB */ +#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */ +#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */ #define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ #define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ #define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ diff --git a/include/asm-blackfin/mach-common/bits/pata.h b/include/asm-blackfin/mach-common/bits/pata.h new file mode 100644 index 0000000..9b61824 --- /dev/null +++ b/include/asm-blackfin/mach-common/bits/pata.h @@ -0,0 +1,220 @@ +/* + * ATAPI Masks + */ + +#ifndef __BFIN_PERIPHERAL_PATA__ +#define __BFIN_PERIPHERAL_PATA__ + +/* Bit masks for ATAPI_CONTROL */ +#define PIO_START 0x1 /* Start PIO/Reg Op */ +#define MULTI_START 0x2 /* Start Multi-DMA Op */ +#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ +#define XFER_DIR 0x8 /* Transfer Direction */ +#define IORDY_EN 0x10 /* IORDY Enable */ +#define FIFO_FLUSH 0x20 /* Flush FIFOs */ +#define SOFT_RST 0x40 /* Soft Reset */ +#define DEV_RST 0x80 /* Device Reset */ +#define TFRCNT_RST 0x100 /* Trans Count Reset */ +#define END_ON_TERM 0x200 /* End/Terminate Select */ +#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ +#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ + +/* Bit masks for ATAPI_STATUS */ +#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ +#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ +#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ +#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ + +/* Bit masks for ATAPI_DEV_ADDR */ +#define DEV_ADDR 0x1f /* Device Address */ + +/* Bit masks for ATAPI_INT_MASK */ +#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ +#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ +#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ +#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ +#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ +#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ +#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ +#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ +#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ + +/* Bit masks for ATAPI_INT_STATUS */ +#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ +#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ +#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ +#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ +#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ +#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ +#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ +#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ +#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ + +/* Bit masks for ATAPI_LINE_STATUS */ +#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ +#define ATAPI_DASP 0x2 /* Device dasp to host line status */ +#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ +#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ +#define ATAPI_ADDR 0x70 /* ATAPI address line status */ +#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ +#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ +#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ +#define ATAPI_DIORN 0x400 /* ATAPI read line status */ +#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_SM_STATE */ +#define PIO_CSTATE 0xf /* PIO mode state machine current state */ +#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ +#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ +#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_TERMINATE */ +#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ + +/* Bit masks for ATAPI_REG_TIM_0 */ +#define T2_REG 0xff /* End of cycle time for register access transfers */ +#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ + +/* Bit masks for ATAPI_PIO_TIM_0 */ +#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ +#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ +#define T4_REG 0xf000 /* DIOW data hold */ + +/* Bit masks for ATAPI_PIO_TIM_1 */ +#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ + +/* Bit masks for ATAPI_MULTI_TIM_0 */ +#define TD 0xff /* DIOR/DIOW asserted pulsewidth */ +#define TM 0xff00 /* Time from address valid to DIOR/DIOW */ + +/* Bit masks for ATAPI_MULTI_TIM_1 */ +#define TKW 0xff /* Selects DIOW negated pulsewidth */ +#define TKR 0xff00 /* Selects DIOR negated pulsewidth */ + +/* Bit masks for ATAPI_MULTI_TIM_2 */ +#define TH 0xff /* Selects DIOW data hold */ +#define TEOC 0xff00 /* Selects end of cycle for DMA */ + +/* Bit masks for ATAPI_ULTRA_TIM_0 */ +#define TACK 0xff /* Selects setup and hold times for TACK */ +#define TENV 0xff00 /* Selects envelope time */ + +/* Bit masks for ATAPI_ULTRA_TIM_1 */ +#define TDVS 0xff /* Selects data valid setup time */ +#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ + +/* Bit masks for ATAPI_ULTRA_TIM_2 */ +#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ +#define TMLI 0xff00 /* Selects interlock time */ + +/* Bit masks for ATAPI_ULTRA_TIM_3 */ +#define TZAH 0xff /* Selects minimum delay required for output */ +#define READY_PAUSE 0xff00 /* Selects ready to pause */ + +/* Bit masks for ATAPI_CONTROL */ +#define PIO_START 0x1 /* Start PIO/Reg Op */ +#define MULTI_START 0x2 /* Start Multi-DMA Op */ +#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ +#define XFER_DIR 0x8 /* Transfer Direction */ +#define IORDY_EN 0x10 /* IORDY Enable */ +#define FIFO_FLUSH 0x20 /* Flush FIFOs */ +#define SOFT_RST 0x40 /* Soft Reset */ +#define DEV_RST 0x80 /* Device Reset */ +#define TFRCNT_RST 0x100 /* Trans Count Reset */ +#define END_ON_TERM 0x200 /* End/Terminate Select */ +#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ +#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ + +/* Bit masks for ATAPI_STATUS */ +#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ +#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ +#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ +#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ + +/* Bit masks for ATAPI_DEV_ADDR */ +#define DEV_ADDR 0x1f /* Device Address */ + +/* Bit masks for ATAPI_INT_MASK */ +#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ +#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ +#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ +#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ +#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ +#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ +#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ +#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ +#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ + +/* Bit masks for ATAPI_INT_STATUS */ +#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ +#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ +#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ +#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ +#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ +#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ +#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ +#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ +#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ + +/* Bit masks for ATAPI_LINE_STATUS */ +#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ +#define ATAPI_DASP 0x2 /* Device dasp to host line status */ +#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ +#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ +#define ATAPI_ADDR 0x70 /* ATAPI address line status */ +#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ +#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ +#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ +#define ATAPI_DIORN 0x400 /* ATAPI read line status */ +#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_SM_STATE */ +#define PIO_CSTATE 0xf /* PIO mode state machine current state */ +#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ +#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ +#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_TERMINATE */ +#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ + +/* Bit masks for ATAPI_REG_TIM_0 */ +#define T2_REG 0xff /* End of cycle time for register access transfers */ +#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ + +/* Bit masks for ATAPI_PIO_TIM_0 */ +#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ +#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ +#define T4_REG 0xf000 /* DIOW data hold */ + +/* Bit masks for ATAPI_PIO_TIM_1 */ +#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ + +/* Bit masks for ATAPI_MULTI_TIM_0 */ +#define TD 0xff /* DIOR/DIOW asserted pulsewidth */ +#define TM 0xff00 /* Time from address valid to DIOR/DIOW */ + +/* Bit masks for ATAPI_MULTI_TIM_1 */ +#define TKW 0xff /* Selects DIOW negated pulsewidth */ +#define TKR 0xff00 /* Selects DIOR negated pulsewidth */ + +/* Bit masks for ATAPI_MULTI_TIM_2 */ +#define TH 0xff /* Selects DIOW data hold */ +#define TEOC 0xff00 /* Selects end of cycle for DMA */ + +/* Bit masks for ATAPI_ULTRA_TIM_0 */ +#define TACK 0xff /* Selects setup and hold times for TACK */ +#define TENV 0xff00 /* Selects envelope time */ + +/* Bit masks for ATAPI_ULTRA_TIM_1 */ +#define TDVS 0xff /* Selects data valid setup time */ +#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ + +/* Bit masks for ATAPI_ULTRA_TIM_2 */ +#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ +#define TMLI 0xff00 /* Selects interlock time */ + +/* Bit masks for ATAPI_ULTRA_TIM_3 */ +#define TZAH 0xff /* Selects minimum delay required for output */ +#define READY_PAUSE 0xff00 /* Selects ready to pause */ + +#endif /* __BFIN_PERIPHERAL_PATA__ */ diff --git a/include/asm-blackfin/mach-common/bits/sdh.h b/include/asm-blackfin/mach-common/bits/sdh.h new file mode 100644 index 0000000..8c5dd33 --- /dev/null +++ b/include/asm-blackfin/mach-common/bits/sdh.h @@ -0,0 +1,122 @@ +/* + * SDH Masks + */ + +#ifndef __BFIN_PERIPHERAL_SDH__ +#define __BFIN_PERIPHERAL_SDH__ + +/* Bit masks for SDH_COMMAND */ +#define CMD_IDX 0x3f /* Command Index */ +#define CMD_RSP 0x40 /* Response */ +#define CMD_L_RSP 0x80 /* Long Response */ +#define CMD_INT_E 0x100 /* Command Interrupt */ +#define CMD_PEND_E 0x200 /* Command Pending */ +#define CMD_E 0x400 /* Command Enable */ + +/* Bit masks for SDH_PWR_CTL */ +#define PWR_ON 0x3 /* Power On */ +#define SD_CMD_OD 0x40 /* Open Drain Output */ +#define ROD_CTL 0x80 /* Rod Control */ + +/* Bit masks for SDH_CLK_CTL */ +#define CLKDIV 0xff /* MC_CLK Divisor */ +#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ +#define PWR_SV_E 0x200 /* Power Save Enable */ +#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ +#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ + +/* Bit masks for SDH_RESP_CMD */ +#define RESP_CMD 0x3f /* Response Command */ + +/* Bit masks for SDH_DATA_CTL */ +#define DTX_E 0x1 /* Data Transfer Enable */ +#define DTX_DIR 0x2 /* Data Transfer Direction */ +#define DTX_MODE 0x4 /* Data Transfer Mode */ +#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ +#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ + +/* Bit masks for SDH_STATUS */ +#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ +#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ +#define TX_UNDERRUN 0x10 /* Transmit Underrun */ +#define RX_OVERRUN 0x20 /* Receive Overrun */ +#define CMD_RESP_END 0x40 /* CMD Response End */ +#define CMD_SENT 0x80 /* CMD Sent */ +#define DAT_END 0x100 /* Data End */ +#define START_BIT_ERR 0x200 /* Start Bit Error */ +#define DAT_BLK_END 0x400 /* Data Block End */ +#define CMD_ACT 0x800 /* CMD Active */ +#define TX_ACT 0x1000 /* Transmit Active */ +#define RX_ACT 0x2000 /* Receive Active */ +#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ +#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ +#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ +#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ +#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ +#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ +#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ +#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ + +/* Bit masks for SDH_STATUS_CLR */ +#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ +#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ +#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ +#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ +#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ +#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ +#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ +#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ +#define DAT_END_STAT 0x100 /* Data End Status */ +#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ +#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ + +/* Bit masks for SDH_MASK0 */ +#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ +#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ +#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ +#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ +#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ +#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ +#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ +#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ +#define DAT_END_MASK 0x100 /* Data End Mask */ +#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ +#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ +#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ +#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ +#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ +#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ +#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ +#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ +#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ +#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ +#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ +#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ +#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ + +/* Bit masks for SDH_FIFO_CNT */ +#define FIFO_COUNT 0x7fff /* FIFO Count */ + +/* Bit masks for SDH_E_STATUS */ +#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ +#define SD_CARD_DET 0x10 /* SD Card Detect */ + +/* Bit masks for SDH_E_MASK */ +#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ +#define SCD_MSK 0x40 /* Mask Card Detect */ + +/* Bit masks for SDH_CFG */ +#define CLKS_EN 0x1 /* Clocks Enable */ +#define SD4E 0x4 /* SDIO 4-Bit Enable */ +#define MWE 0x8 /* Moving Window Enable */ +#define SD_RST 0x10 /* SDMMC Reset */ +#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ +#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ +#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ + +/* Bit masks for SDH_RD_WAIT_EN */ +#define RWR 0x1 /* Read Wait Request */ + +#endif diff --git a/include/asm-blackfin/mmc.h b/include/asm-blackfin/mmc.h new file mode 100644 index 0000000..aa2ac95 --- /dev/null +++ b/include/asm-blackfin/mmc.h @@ -0,0 +1 @@ +#include <asm-avr32/arch-at32ap700x/mmc.h> diff --git a/include/asm-blackfin/posix_types.h b/include/asm-blackfin/posix_types.h index 39651d2..000ffe5 100644 --- a/include/asm-blackfin/posix_types.h +++ b/include/asm-blackfin/posix_types.h @@ -40,15 +40,17 @@ typedef unsigned short __kernel_mode_t; typedef unsigned short __kernel_nlink_t; typedef long __kernel_off_t; typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; +typedef unsigned int __kernel_ipc_pid_t; +typedef unsigned int __kernel_uid_t; +typedef unsigned int __kernel_gid_t; +typedef unsigned long __kernel_size_t; +typedef long __kernel_ssize_t; typedef int __kernel_ptrdiff_t; typedef long __kernel_time_t; typedef long __kernel_suseconds_t; typedef long __kernel_clock_t; +typedef int __kernel_timer_t; +typedef int __kernel_clockid_t; typedef int __kernel_daddr_t; typedef char *__kernel_caddr_t; typedef unsigned short __kernel_uid16_t; @@ -67,14 +69,10 @@ typedef long long __kernel_loff_t; #endif typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ } __kernel_fsid_t; -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) +#if defined(__KERNEL__) #undef __FD_SET #define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) @@ -88,6 +86,6 @@ typedef struct { #undef __FD_ZERO #define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ +#endif /* defined(__KERNEL__) */ #endif |