diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/MPC8349EMDS.h | 2 | ||||
| -rw-r--r-- | include/configs/MPC8349ITX.h | 6 | ||||
| -rw-r--r-- | include/configs/MPC8360ERDK.h | 2 | ||||
| -rw-r--r-- | include/configs/MVBC_P.h | 2 | ||||
| -rw-r--r-- | include/configs/MVBLM7.h | 49 |
5 files changed, 26 insertions, 35 deletions
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 1d736f3..9b2d25a 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -732,7 +732,7 @@ "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ "upd=run load update\0" \ "fdtaddr=780000\0" \ - "fdtfile=mpc8349emds.dtb\0" \ + "fdtfile=mpc834x_mds.dtb\0" \ "" #define CONFIG_NFSBOOTCOMMAND \ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index fd5ad70..3b4e344 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -515,7 +515,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ #ifdef CONFIG_MPC8349ITX #define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ @@ -708,7 +708,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_FDTFILE mpc8349emitxgp.dtb #endif -#define CONFIG_BOOTDELAY 0 +#define CONFIG_BOOTDELAY 6 #define XMK_STR(x) #x #define MK_STR(x) XMK_STR(x) @@ -731,7 +731,7 @@ boards, we say we have two, but don't display a message if we find only one. */ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ - "fdtaddr=400000\0" \ + "fdtaddr=780000\0" \ "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" #define CONFIG_NFSBOOTCOMMAND \ diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index 68d68bb..cb0535c 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -530,7 +530,7 @@ "consoledev=ttyS0\0"\ "loadaddr=a00000\0"\ "fdtaddr=900000\0"\ - "fdtfile=dtb\0"\ + "fdtfile=mpc836x_rdk.dtb\0"\ "fsfile=fs\0"\ "ubootfile=u-boot.bin\0"\ "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\ diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h index 867e8e0..0c228cb 100644 --- a/include/configs/MVBC_P.h +++ b/include/configs/MVBC_P.h @@ -67,7 +67,7 @@ #define MV_CI mvBlueCOUGAR-P #define MV_VCI mvBlueCOUGAR-P #define MV_FPGA_DATA 0xff860000 -#define MV_FPGA_SIZE 0x0003c886 +#define MV_FPGA_SIZE 0 #define MV_KERNEL_ADDR 0xffd00000 #define MV_INITRD_ADDR 0xff900000 #define MV_INITRD_LENGTH 0x00400000 diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index aa91805..80334bd 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -46,10 +46,9 @@ #define CONFIG_MPC8XXX_SPI #define CONFIG_HARD_SPI #define MVBLM7_MMC_CS 0x04000000 +#define CONFIG_MISC_INIT_R /* I2C */ -#undef CONFIG_SOFT_I2C - #define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_I2C_OFFSET 0x3000 @@ -61,44 +60,36 @@ /* * DDR Setup */ +#undef CONFIG_SPD_EEPROM + #define CONFIG_SYS_DDR_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_83XX_DDR_USES_CS0 1 #define CONFIG_SYS_MEMTEST_START (60<<20) #define CONFIG_SYS_MEMTEST_END (70<<20) +#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 - -#define CONFIG_SYS_DDR_SIZE 256 +#define CONFIG_SYS_DDRCDR 0x22000001 +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -/* HC, 75Ohm, DDR-II, DRQ */ -#define CONFIG_SYS_DDRCDR 0x80000001 -/* EN, ODT_WR, 3BA, 14row, 10col */ -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014102 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x0 -#define CONFIG_SYS_DDR_CS2_CONFIG 0x0 -#define CONFIG_SYS_DDR_CS3_CONFIG 0x0 +#define CONFIG_SYS_DDR_SIZE 512 -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS1_BNDS 0x0 -#define CONFIG_SYS_DDR_CS2_BNDS 0x0 -#define CONFIG_SYS_DDR_CS3_BNDS 0x0 +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x2625b221 -#define CONFIG_SYS_DDR_TIMING_2 0x1f9820c7 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 0x00260802 +#define CONFIG_SYS_DDR_TIMING_1 0x3837c322 +#define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6 +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -/* ~MEM_EN, SREN, DDR-II, 32_BE */ -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080000 +#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 +#define CONFIG_SYS_DDR_INTERVAL 0x02000100 -#define CONFIG_SYS_DDR_MODE 0x078e0232 +#define CONFIG_SYS_DDR_MODE 0x04040242 +#define CONFIG_SYS_DDR_MODE2 0x00800000 /* Flash */ #define CONFIG_SYS_FLASH_CFI @@ -404,8 +395,8 @@ #define MV_CI mvBL-M7 #define MV_VCI mvBL-M7 -#define MV_FPGA_DATA 0xfff80000 -#define MV_FPGA_SIZE 0x00076ca2 +#define MV_FPGA_DATA 0xfff40000 +#define MV_FPGA_SIZE 0 #define MV_KERNEL_ADDR 0xff810000 #define MV_INITRD_ADDR 0xffb00000 #define MV_SOURCE_ADDR 0xff804000 @@ -452,7 +443,7 @@ "static_ipaddr=192.168.90.10\0" \ "static_netmask=255.255.255.0\0" \ "static_gateway=0.0.0.0\0" \ - "initrd_name=uInitrd.mvblm7-xenorfs\0" \ + "initrd_name=uInitrd.mvBL-M7-rfs\0" \ "zcip=no\0" \ "netboot=yes\0" \ "mvtest=Ff\0" \ |