diff options
Diffstat (limited to 'include')
52 files changed, 2460 insertions, 643 deletions
diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h new file mode 100755 index 0000000..f10f89c --- /dev/null +++ b/include/asm-microblaze/asm.h @@ -0,0 +1,98 @@ +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK <monstr@monstr.eu> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* FSL macros */ +#define NGET(val, fslnum) \ + __asm__ __volatile__ ("nget %0, rfsl" #fslnum :"=r" (val)); + +#define GET(val, fslnum) \ + __asm__ __volatile__ ("get %0, rfsl" #fslnum :"=r" (val)); + +#define NCGET(val, fslnum) \ + __asm__ __volatile__ ("ncget %0, rfsl" #fslnum :"=r" (val)); + +#define CGET(val, fslnum) \ + __asm__ __volatile__ ("cget %0, rfsl" #fslnum :"=r" (val)); + +#define NPUT(val, fslnum) \ + __asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val)); + +#define PUT(val, fslnum) \ + __asm__ __volatile__ ("put %0, rfsl" #fslnum ::"r" (val)); + +#define NCPUT(val, fslnum) \ + __asm__ __volatile__ ("ncput %0, rfsl" #fslnum ::"r" (val)); + +#define CPUT(val, fslnum) \ + __asm__ __volatile__ ("cput %0, rfsl" #fslnum ::"r" (val)); + +/* CPU dependent */ +/* machine status register */ +#define MFS(val, reg) \ + __asm__ __volatile__ ("mfs %0," #reg :"=r" (val)); + +#define MTS(val, reg) \ + __asm__ __volatile__ ("mts " #reg ", %0"::"r" (val)); + +/* get return address from interrupt */ +#define R14(val) \ + __asm__ __volatile__ ("addi %0, r14, 0":"=r" (val)); + +#define NOP __asm__ __volatile__ ("nop"); + +/* use machine status registe USE_MSR_REG */ +#ifdef XILINX_USE_MSR_INSTR +#define MSRSET(val) \ + __asm__ __volatile__ ("msrset r0," #val ); + +#define MSRCLR(val) \ + __asm__ __volatile__ ("msrclr r0," #val ); + +#else +#define MSRSET(val) \ +{ \ + register unsigned tmp; \ + __asm__ __volatile__ (" \ + mfs %0, rmsr; \ + ori %0, %0, "#val"; \ + mts rmsr, %0; \ + nop;" \ + : "=r" (tmp) \ + : "d" (val) \ + : "memory"); \ +} + +#define MSRCLR(val) \ +{ \ + register unsigned tmp; \ + __asm__ __volatile__ (" \ + mfs %0, rmsr; \ + andi %0, %0, ~"#val"; \ + mts rmsr, %0; \ + nop;" \ + : "=r" (tmp) \ + : "d" (val) \ + : "memory"); \ +} +#endif diff --git a/include/asm-microblaze/microblaze_intc.h b/include/asm-microblaze/microblaze_intc.h index 6635aea..4c385aa 100644 --- a/include/asm-microblaze/microblaze_intc.h +++ b/include/asm-microblaze/microblaze_intc.h @@ -38,3 +38,6 @@ struct irq_action { void *arg; int count; /* number of interrupt */ }; + +void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, + void *arg); diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h index ff9512f..d1bb159 100644 --- a/include/asm-ppc/e300.h +++ b/include/asm-ppc/e300.h @@ -6,19 +6,9 @@ #ifndef __E300_H__ #define __E300_H__ -/* - * e300 Processor Version & Revision Numbers - */ -#define PVR_83xx 0x80830000 -#define PVR_8349_REV10 (PVR_83xx | 0x0010) -#define PVR_8349_REV11 (PVR_83xx | 0x0011) -#define PVR_8360_REV10 (PVR_83xx | 0x0020) -#define PVR_8360_REV11 (PVR_83xx | 0x0020) - -#if defined(CONFIG_MPC832X) -#undef PVR_83xx -#define PVR_83xx 0x80840000 -#endif +#define PVR_E300C1 0x80830000 +#define PVR_E300C2 0x80840000 +#define PVR_E300C3 0x80850000 /* * Hardware Implementation-Dependent Register 0 (HID0) diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 26bc875..cd24636 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -55,11 +55,13 @@ typedef struct global_data { #if defined(CONFIG_MPC83XX) /* There are other clocks in the MPC83XX */ u32 csb_clk; -#if defined (CONFIG_MPC834X) +#if defined (CONFIG_MPC834X) || defined(CONFIG_MPC831X) u32 tsec1_clk; u32 tsec2_clk; - u32 usbmph_clk; u32 usbdr_clk; +#endif +#if defined (CONFIG_MPC834X) + u32 usbmph_clk; #endif /* CONFIG_MPC834X */ u32 core_clk; u32 i2c1_clk; diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 5e088d6..0de9338 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -206,7 +206,9 @@ typedef struct pmc83xx { u32 pmccr; /* PMC Configuration Register */ u32 pmcer; /* PMC Event Register */ u32 pmcmr; /* PMC Mask Register */ - u8 res0[0xF4]; + u32 pmccr1; /* PMC Configuration Register 1 */ + u32 pmccr2; /* PMC Configuration Register 2 */ + u8 res0[0xEC]; } pmc83xx_t; /* @@ -355,7 +357,8 @@ typedef struct lbus83xx { u8 res2[0x8]; u32 mrtpr; /* Memory Refresh Timer Prescaler Register */ u32 mdr; /* UPM Data Register */ - u8 res3[0x8]; + u8 res3[0x4]; + u32 lsor; /* Special Operation Initiation Register */ u32 lsdmr; /* SDRAM Mode Register */ u8 res4[0x8]; u32 lurt; /* UPM Refresh Timer */ @@ -369,8 +372,14 @@ typedef struct lbus83xx { u8 res6[0xC]; u32 lbcr; /* Configuration Register */ u32 lcrr; /* Clock Ratio Register */ - u8 res7[0x28]; - u8 res8[0xF00]; + u8 res7[0x8]; + u32 fmr; /* Flash Mode Register */ + u32 fir; /* Flash Instruction Register */ + u32 fcr; /* Flash Command Register */ + u32 fbar; /* Flash Block Addr Register */ + u32 fpar; /* Flash Page Addr Register */ + u32 fbcr; /* Flash Byte Count Register */ + u8 res8[0xF08]; } lbus83xx_t; /* @@ -527,7 +536,7 @@ typedef struct pcictrl83xx { * USB */ typedef struct usb83xx { - u8 fixme[0x2000]; + u8 fixme[0x1000]; } usb83xx_t; /* @@ -574,7 +583,42 @@ typedef struct immap { ios83xx_t ios; /* Sequencer */ pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ u8 res5[0x19900]; - usb83xx_t usb; + usb83xx_t usb[2]; + tsec83xx_t tsec[2]; + u8 res6[0xA000]; + security83xx_t security; + u8 res7[0xC0000]; +} immap_t; + +#elif defined(CONFIG_MPC831X) +typedef struct immap { + sysconf83xx_t sysconf; /* System configuration */ + wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk83xx_t rtc; /* Real Time Clock Module Registers */ + rtclk83xx_t pit; /* Periodic Interval Timer */ + gtm83xx_t gtm[2]; /* Global Timers Module */ + ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter83xx_t arbiter; /* System Arbiter Registers */ + reset83xx_t reset; /* Reset Module */ + clk83xx_t clk; /* System Clock Module */ + pmc83xx_t pmc; /* Power Management Control Module */ + gpio83xx_t gpio[1]; /* General purpose I/O module */ + u8 res0[0x1300]; + ddr83xx_t ddr; /* DDR Memory Controller Memory */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ + u8 res1[0x1300]; + duart83xx_t duart[2]; /* DUART */ + u8 res2[0x900]; + lbus83xx_t lbus; /* Local Bus Controller Registers */ + u8 res3[0x1000]; + spi83xx_t spi; /* Serial Peripheral Interface */ + dma83xx_t dma; /* DMA */ + pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ + u8 res4[0x80]; + ios83xx_t ios; /* Sequencer */ + pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ + u8 res5[0x1aa00]; + usb83xx_t usb[1]; tsec83xx_t tsec[2]; u8 res6[0xA000]; security83xx_t security; diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index b226825..48fd982 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -396,8 +396,8 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define BOOKE_PAGESZ_16M 7 #define BOOKE_PAGESZ_64M 8 #define BOOKE_PAGESZ_256M 9 -#define BOOKE_PAGESZ_1GB 10 -#define BOOKE_PAGESZ_4GB 11 +#define BOOKE_PAGESZ_1G 10 +#define BOOKE_PAGESZ_4G 11 #if defined(CONFIG_MPC86xx) #define LAWBAR_BASE_ADDR 0x00FFFFFF @@ -413,6 +413,7 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000 #define LAWAR_TRGT_IF_PCI2 0x00100000 +#define LAWAR_TRGT_IF_PEX 0x00200000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 0585962..5efc3ee 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -232,6 +232,9 @@ #define HID0_BHTE (1<<2) /* Branch History Table Enable */ #define HID0_BTCD (1<<1) /* Branch target cache disable */ #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ +#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ +#define HID1_ASTME (1<<13) /* Address bus streaming mode */ +#define HID1_ABE (1<<12) /* Address broadcast enable */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #ifndef CONFIG_BOOKE #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ @@ -415,10 +418,12 @@ #define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ /* e500 definitions */ -#define SPRN_L1CSR0 0x3f2 /* L1 Cache Control and Status Register 0 */ +#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ +#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ -#define SPRN_L1CSR1 0x3f3 /* L1 Cache Control and Status Register 1 */ +#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ +#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ @@ -701,8 +706,6 @@ #define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ #define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ -/* System-On-Chip Version Numbers (version field only) */ -#define SVR_MPC5200 0x8011 /* Processor Version Register */ @@ -813,6 +816,12 @@ #define PVR_8260_HIP7R1 0x80822013 #define PVR_8260_HIP7RA 0x80822014 +/* + * MPC 52xx + */ +#define PVR_5200 0x80822011 +#define PVR_5200B 0x80822014 + /* * System Version Register @@ -840,9 +849,12 @@ #define SVR_8560 0x8070 #define SVR_8555 0x8079 #define SVR_8541 0x807A +#define SVR_8544 0x8034 +#define SVR_8544_E 0x803C #define SVR_8548 0x8031 #define SVR_8548_E 0x8039 #define SVR_8641 0x8090 +#define SVR_8568_E 0x807D /* I am just adding a single entry for 8260 boards. I think we may be diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h index cf36583..b3ccdce 100644 --- a/include/cmd_confdefs.h +++ b/include/cmd_confdefs.h @@ -94,6 +94,7 @@ #define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */ #define CFG_CMD_SNTP 0x2000000000000000ULL /* SNTP support */ #define CFG_CMD_DISPLAY 0x4000000000000000ULL /* Display support */ +#define CFG_CMD_MFSL 0x8000000000000000ULL /* FSL support for Microblaze */ #define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFULL /* ALL commands */ @@ -125,6 +126,7 @@ CFG_CMD_IRQ | \ CFG_CMD_JFFS2 | \ CFG_CMD_KGDB | \ + CFG_CMD_MFSL | \ CFG_CMD_MII | \ CFG_CMD_MMC | \ CFG_CMD_NAND | \ diff --git a/include/common.h b/include/common.h index b162dbd..3c4b37b 100644 --- a/include/common.h +++ b/include/common.h @@ -402,6 +402,10 @@ void ppcDcbi(unsigned long value); void ppcSync(void); void ppcDcbz(unsigned long value); #endif +#if defined (CONFIG_MICROBLAZE) +unsigned short in16(unsigned int); +void out16(unsigned int, unsigned short value); +#endif #if defined (CONFIG_MPC83XX) void ppcDWload(unsigned int *addr, unsigned int *ret); @@ -440,8 +444,6 @@ int sdram_adjust_866 (void); int adjust_sdram_tbs_8xx (void); #if defined(CONFIG_8260) int prt_8260_clks (void); -#elif defined(CONFIG_MPC83XX) -int print_clock_conf(void); #elif defined(CONFIG_MPC5xxx) int prt_mpc5xxx_clks (void); #endif diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 5b54f30..bc30977 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -282,17 +282,17 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ +#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ /* * PCI Bus clocking configuration * * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet - * hasn't been tested with a IPB Bus Clock of 66 MHz. + * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock + * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. */ -#if defined(CFG_IPBSPEED_133) -# define CFG_PCISPEED_66 /* define for 66MHz speed */ +#if defined(CFG_IPBCLK_EQUALS_XLBCLK) +# define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ #endif /* @@ -488,7 +488,7 @@ #define CFG_BOOTCS_START CFG_FLASH_BASE #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCISPEED_66 +#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2 # define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ #else # define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 5988112..73be069 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -167,9 +167,9 @@ * IPB Bus clocking configuration. */ #if defined(CONFIG_LITE5200B) -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ +#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #else -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #endif #endif /* CONFIG_MPC5200 */ diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h new file mode 100644 index 0000000..6976313 --- /dev/null +++ b/include/configs/MPC8313ERDB.h @@ -0,0 +1,561 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * mpc8313epb board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 +#define CONFIG_MPC83XX 1 +#define CONFIG_MPC831X 1 +#define CONFIG_MPC8313 1 +#define CONFIG_MPC8313ERDB 1 + +#define CONFIG_PCI +#define CONFIG_83XX_GENERIC_PCI + +#ifdef CFG_66MHZ +#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ +#elif defined(CFG_33MHZ) +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ +#else +#error Unknown oscillator frequency. +#endif + +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ + +#define CFG_IMMR 0xE0000000 + +#define CFG_MEMTEST_START 0x00001000 +#define CFG_MEMTEST_END 0x07f00000 + +/* Early revs of this board will lock up hard when attempting + * to access the PMC registers, unless a JTAG debugger is + * connected, or some resistor modifications are made. + */ +#define CFG_8313ERDB_BROKEN_PMC 1 + +#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE + +/* + * Manually set up DDR parameters, as this board does not + * seem to have the SPD connected to I2C. + */ +#define CFG_DDR_SIZE 128 /* MB */ +#define CFG_DDR_CONFIG ( CSCONFIG_EN | CSCONFIG_AP \ + | 0x00040000 /* TODO */ \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) + /* 0x80840102 */ + +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ + | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ + | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) + /* 0x00220802 */ +#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ + | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ + | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ + | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ + | (13 << TIMING_CFG1_REFREC_SHIFT ) \ + | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ + | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ + | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) + /* 0x3935d322 */ +#define CFG_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \ + | (31 << TIMING_CFG2_CPO_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ + | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ + | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ + | (10 << TIMING_CFG2_FOUR_ACT_SHIFT) ) + /* 0x0f9048ca */ /* P9-45,may need tuning */ +#define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \ + | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) + /* 0x03200064 */ +#if defined(CONFIG_DDR_2T_TIMING) +#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ + | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ + | SDRAM_CFG_2T_EN \ + | SDRAM_CFG_DBW_32 ) +#else +#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ + | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ + | SDRAM_CFG_32_BE ) + /* 0x43080000 */ +#endif +#define CFG_SDRAM_CFG2 0x00401000; +/* set burst length to 8 for 32-bit data path */ +#define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \ + | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) + /* 0x44400232 */ +#define CFG_DDR_MODE_2 0x8000C000; + +#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + /*0x02000000*/ +#define CFG_DDRCDR_VALUE ( DDRCDR_EN \ + | DDRCDR_PZ_NOMZ \ + | DDRCDR_NZ_NOMZ \ + | DDRCDR_M_ODR ) + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CFG_FLASH_SIZE 8 /* flash size in MB */ +#define CFG_FLASH_EMPTY_INFO /* display empty sectors */ +#define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) /* valid */ +#define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_9 \ + | OR_GPCM_EHTR \ + | OR_GPCM_EAD ) + /* 0xFF006FF7 TODO SLOW 16 MB flash size */ +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 135 /* sectors per device */ + +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#endif + +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + */ +#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */ +#define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \ + | (0xFF << LBCR_BMT_SHIFT) \ + | 0xF ) /* 0x0004ff0f */ + +#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ + +/* drivers/nand/nand.c */ +#define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE + +#define CFG_BR1_PRELIM ( CFG_NAND_BASE \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V ) /* valid */ +#define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR ) + /* 0xFFFF8396 */ +#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE +#define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ + +#define CFG_VSC7385_BASE 0xF0000000 + +#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ +#define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ +#define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ +#define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */ +#define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ + +/* local bus read write buffer mapping */ +#define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ +#define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ +#define CFG_LBLAWBAR3_PRELIM 0xFA000000 +#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8313@0" +#define OF_SOC "soc8313@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc8313@e0000000/serial@4500" + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#define CONFIG_FSL_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 + +/* TSEC */ +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) +#define CONFIG_NET_MULTI + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_MMIO_BASE 0x90000000 +#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE +#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xE2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +/* + * TSEC configuration + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_GMII 1 /* MII PHY management */ +#define CONFIG_MPC83XX_TSEC1 1 + +#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC83XX_TSEC2 1 +#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 0x1c +#define TSEC2_PHY_ADDR 4 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC1" + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_DS1337 +#define CFG_I2C_RTC_ADDR 0x68 + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 + +/* Address and size of Redundant Environment Sector */ +#else + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CFG_BASE_COMMANDS ( CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_DHCP \ + | CFG_CMD_I2C \ + | CFG_CMD_MII \ + | CFG_CMD_DATE \ + | CFG_CMD_PCI) + +#define CONFIG_CMDLINE_EDITING 1 + +#define CFG_RAMBOOT_COMMANDS (CFG_BASE_COMMANDS & \ + ~(CFG_CMD_ENV | CFG_CMD_LOADS)) + +#if defined(CFG_RAMBOOT) +#define CONFIG_COMMANDS CFG_RAMBOOT_COMMANDS +#else +#define CONFIG_COMMANDS CFG_BASE_COMMANDS +#endif + +#include <cmd_confdefs.h> + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 32 +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ + +#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#ifdef CFG_66MHZ + +/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ +/* 0x62040000 */ +#define CFG_HRCW_LOW (\ + 0x20000000 /* reserved, must be set */ |\ + HRCWL_DDRCM |\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_CORE_TO_CSB_2X1) + +#elif defined(CFG_33MHZ) + +/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ +/* 0x65040000 */ +#define CFG_HRCW_LOW (\ + 0x20000000 /* reserved, must be set */ |\ + HRCWL_DDRCM |\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_CSB_TO_CLKIN_5X1 |\ + HRCWL_CORE_TO_CSB_2X1) + +#endif + +/* 0xa0606c00 */ +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) + +/* System IO Config */ +#define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ +#define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */ + +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) + +#define CFG_HID2 HID2_HBE + +/* DDR @ 0x00000000 */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI @ 0x80000000 */ +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10) +#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI2 not supported on 8313 */ +#define CFG_IBAT3L (0) +#define CFG_IBAT3U (0) +#define CFG_IBAT4L (0) +#define CFG_IBAT4U (0) + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ +#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) + +/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CFG_IBAT6L (0xF0000000 | BATL_PP_10) +#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT7L (0) +#define CFG_IBAT7U (0) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ETHADDR 00:E0:0C:00:95:01 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 + +#define CONFIG_IPADDR 10.0.0.2 +#define CONFIG_SERVERIP 10.0.0.1 +#define CONFIG_GATEWAYIP 10.0.0.1 +#define CONFIG_NETMASK 255.0.0.0 +#define CONFIG_NETDEV eth1 + +#define CONFIG_HOSTNAME mpc8313erdb +#define CONFIG_ROOTPATH /nfs/root/path +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ +#define CONFIG_FDTFILE mpc8313erdb.dtb + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ +#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ +#define CONFIG_BAUDRATE 115200 + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "ethprime=TSEC1\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "fdtaddr=400000\0" \ + "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ + "console=ttyS0\0" \ + "setbootargs=setenv bootargs " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ + "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv rootdev /dev/nfs;" \ + "run setbootargs;" \ + "run setipargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv rootdev /dev/ram;" \ + "run setbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#undef MK_STR +#undef XMK_STR + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 37bbfb3..906339e 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -154,6 +154,9 @@ #define CFG_MEMTEST_START 0x1000 /* memtest region */ #define CFG_MEMTEST_END 0x2000 +#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + #ifdef CONFIG_HARD_I2C #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ #endif diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 74a84f4..5aeea58 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -330,13 +330,12 @@ /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ - -#define CFG_PCI1_IO_BASE 0x0 +#define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe2000000 #define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index db389cf..fb360d2 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -334,7 +334,7 @@ extern unsigned long get_clock_freq(void); /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h new file mode 100644 index 0000000..4c34308 --- /dev/null +++ b/include/configs/MPC8544DS.h @@ -0,0 +1,591 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8544ds board configuration file + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ +#define CONFIG_MPC8544 1 +#define CONFIG_MPC8544DS 1 + +#undef CONFIG_PCI /* Enable PCI/PCIE */ +#undef CONFIG_PCI1 /* PCI controller 1 */ +#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#undef CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ +#undef CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ +#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#undef CONFIG_DDR_DLL +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CONFIG_DDR_ECC_CMD + +/* + * When initializing flash, if we cannot find the manufacturer ID, + * assume this is the AMD flash associated with the CDS board. + * This allows booting from a promjet. + */ +#define CONFIG_ASSUME_AMD_FLASH + +#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ + +#ifndef __ASSEMBLY__ +extern unsigned long get_board_sys_clk(unsigned long dummy); +#endif +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ +#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00400000 +#define CFG_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) +#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) +#define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) +#define CFG_PCIE3_ADDR (CFG_CCSRBAR+0xb000) + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +/* + * Make sure required options are set + */ +#ifndef CONFIG_SPD_EEPROM +#error ("CONFIG_SPD_EEPROM is required") +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +/* + * Memory map + * + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * + * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable + * + * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable + * + * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable + * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable + * + * Localbus cacheable + * + * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable + * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 + * + * Localbus non-cacheable + * + * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable + * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable + * + */ + +/* + * Local Bus Definitions + */ +#define CFG_BOOT_BLOCK 0xfc000000 /* boot TLB */ + +#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ + +#define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ + +#define CFG_BR0_PRELIM 0xff801001 +#define CFG_BR1_PRELIM 0xfe801001 + +#define CFG_OR0_PRELIM 0xff806e65 +#define CFG_OR1_PRELIM 0xff806e65 + +#define CFG_FLASH_BANKS_LIST {0xfe800000,CFG_FLASH_BASE} + +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + +#define CFG_LBC_NONCACHE_BASE 0xf8000000 + +#define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ +#define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ + +#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ +#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ + +#define PIXIS_BASE 0xf8100000 /* PIXIS registers */ +#define PIXIS_ID 0x0 /* Board ID at offset 0 */ +#define PIXIS_VER 0x1 /* Board version at offset 1 */ +#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ +#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ +#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch + * register */ +#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ +#define PIXIS_VCTL 0x10 /* VELA Control Register */ +#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ +#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ +#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ +#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ +#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ +#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ +#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ + + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM 1 +#define CFG_INIT_L1_LOCK 1 +#define CFG_INIT_L1_ADDR 0xf4010000 /* Initial L1 address */ +#define CFG_INIT_L1_END 0x00004000 /* End of used area in RAM */ + +/* define to use L2SRAM as initial stack */ +#undef CONFIG_L2_INIT_RAM +#define CFG_INIT_L2_ADDR 0xf8fc0000 +#define CFG_INIT_L2_END 0x00040000 /* End of used area in RAM */ + +#ifdef CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_ADDR CFG_INIT_L1_ADDR +#define CFG_INIT_RAM_END CFG_INIT_L1_END +#else +#define CFG_INIT_RAM_ADDR CFG_INIT_L2_ADDR +#define CFG_INIT_RAM_END CFG_INIT_L2_END +#endif + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8544@0" +#define OF_SOC "soc8544@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8544@e0000000/serial@4500" + +/* I2C */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3100 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CFG_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ +#define CFG_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ + +#define CFG_PCI1_MEM_BASE 0xc0000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe1000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +/* controller 2, Slot 1, tgtid 1, Base address 9000 */ +#define CFG_PCIE2_MEM_BASE 0x80000000 +#define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE +#define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCIE2_IO_BASE 0x00000000 +#define CFG_PCIE2_IO_PHYS 0xe2000000 +#define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */ + +/* controller 1, Slot 2,tgtid 2, Base address a000 */ +#define CFG_PCIE1_MEM_BASE 0xa0000000 +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE +#define CFG_PCIE1_MEM_SIZE 0x08000000 /* 128M */ +#define CFG_PCIE1_MEM_BASE2 0xa8000000 +#define CFG_PCIE1_MEM_PHYS2 CFG_PCIE1_MEM_BASE2 +#define CFG_PCIE1_MEM_SIZE2 0x04000000 /* 64M */ +#define CFG_PCIE1_IO_BASE 0x00000000 /* reuse mem LAW */ +#define CFG_PCIE1_IO_PHYS 0xaf000000 +#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ + +/* controller 3, direct to uli, tgtid 3, Base address b000 */ +#define CFG_PCIE3_MEM_BASE 0xb0000000 +#define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE +#define CFG_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCIE3_IO_BASE 0x00000000 +#define CFG_PCIE3_IO_PHYS 0xe3000000 +#define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */ + +#if defined(CONFIG_PCI) + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP +#define CONFIG_RTL8139 + +#ifdef CONFIG_RTL8139 +/* This macro is used by RTL8139 but not defined in PPC architecture */ +#define KSEG1ADDR(x) (x) +#define _IO_BASE 0x00000000 +#endif + +#ifndef CONFIG_PCI_PNP + #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE + #define PCI_ENET0_MEMADDR CFG_PCI1_IO_BASE + #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#define CONFIG_SCSI_AHCI + +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_SATA_ULI5288 +#define CFG_SCSI_MAX_SCSI_ID 4 +#define CFG_SCSI_MAX_LUN 1 +#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) +#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE +#endif /* SCSCI */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC1" +#define CONFIG_MPC85XX_TSEC3 1 +#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC3" +#undef CONFIG_MPC85XX_FEC + +#define TSEC1_PHY_ADDR 0 +#define TSEC3_PHY_ADDR 1 + +#define TSEC1_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#if CFG_MONITOR_BASE > 0xfff80000 +#define CFG_ENV_ADDR 0xfff80000 +#else +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#endif +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII \ + | CFG_CMD_BEDBUG \ + | CFG_CMD_NET) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) +#endif +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:E0:0C:02:00:FD +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD +#endif + +#define CONFIG_IPADDR 192.168.1.251 + +#define CONFIG_HOSTNAME 8544ds_unknown +#define CONFIG_ROOTPATH /nfs/mpc85xx +#define CONFIG_BOOTFILE 8544ds_tmt/uImage.uboot + +#define CONFIG_SERVERIP 192.168.0.1 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_NETMASK 255.255.0.0 + +#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ + +#define CONFIG_BAUDRATE 115200 + +#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3) +#define PCIE_ENV \ + "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ + "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ + "pcie1regs=setenv a e000a; run pciereg\0" \ + "pcie2regs=setenv a e0009; run pciereg\0" \ + "pcie3regs=setenv a e000b; run pciereg\0" \ + "pcieerr=md ${a}020 1; md ${a}e00;" \ + "pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ + "pci d.w $b.0 56 1;" \ + "pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \ + "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff;" \ + "pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff;" \ + "pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \ + "pci w $b.0 130 ffffffff\0" \ + "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ + "pcie1err=setenv a e000a; run pcieerr\0" \ + "pcie2err=setenv a e0009; run pcieerr\0" \ + "pcie3err=setenv a e000b; run pcieerr\0" \ + "pcie1errc=setenv a e000a; run pcieerrc\0" \ + "pcie2errc=setenv a e0009; run pcieerrc\0" \ + "pcie3errc=setenv a e000b; run pcieerrc\0" +#else +#define PCIE_ENV "" +#endif + +#if defined(CONFIG_PCI1) +#define PCI_ENV \ + "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ + "echo e;md ${a}e00 9\0" \ + "pci1regs=setenv a e0008; run pcireg\0" \ + "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ + "pci d.w $b.0 56 1\0" \ + "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ + "pci w.w $b.0 56 ffff\0" \ + "pci1err=setenv a e0008; run pcierr\0" \ + "pci1errc=setenv a e0008; run pcierrc\0" +#else +#define PCI_ENV "" +#endif + +#if defined(CONFIG_TSEC_ENET) +#define ENET_ENV \ + "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \ + "md ${a}098 2\0" \ + "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \ + "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \ + "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \ + "echo mib;md ${a}680 31\0" \ + "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \ + "enet1regs=setenv a e0024; run enetreg\0" \ + "enet3regs=setenv a e0026; run enetreg\0" +#else +#define ENET_ENV "" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=8544ds_tmt/ramdisk.uboot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=8544ds_tmt/mpc8544ds.dtb\0" \ + "eoi=mw e00400b0 0\0" \ + "iack=md e00400a0 1\0" \ + "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ + "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \ + "ddrregs=setenv a e0002; run ddrreg\0" \ + "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \ + "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \ + "guregs=setenv a e00e0; run gureg\0" \ + "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \ + "ecmregs=setenv a e0001; run ecmreg\0" \ + PCIE_ENV \ + PCI_ENV \ + ENET_ENV + + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs root=/dev/sda3 rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 7c4849f..680009d 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -36,12 +36,12 @@ #define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ -#undef CONFIG_PCI +#define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ +#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ @@ -340,22 +340,34 @@ extern unsigned long get_clock_freq(void); /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ #define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ -#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_BASE 0x90000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ #define CFG_PCI2_IO_BASE 0x00000000 -#define CFG_PCI2_IO_PHYS 0xe2100000 -#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCI2_IO_PHYS 0xe2800000 +#define CFG_PCI2_IO_SIZE 0x00800000 /* 8M */ +#define CFG_PEX_MEM_BASE 0xa0000000 +#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE +#define CFG_PEX_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PEX_IO_BASE 0x00000000 +#define CFG_PEX_IO_PHYS 0xe3000000 +#define CFG_PEX_IO_SIZE 0x01000000 /* 16M */ + +/* + * RapidIO MMU + */ +#define CFG_RIO_MEM_BASE 0xC0000000 +#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ #if defined(CONFIG_PCI) diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 835bf5c..21e6637 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -320,14 +320,14 @@ /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI) diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h new file mode 100644 index 0000000..3f65644 --- /dev/null +++ b/include/configs/MPC8568MDS.h @@ -0,0 +1,505 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8568mds board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ +#define CONFIG_MPC8568 1 /* MPC8568 specific */ +#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ + +#undef CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +/*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */ + +/*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */ +/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + + +/* + * When initializing flash, if we cannot find the manufacturer ID, + * assume this is the AMD flash associated with the MDS board. + * This allows booting from a promjet. + */ +#define CONFIG_ASSUME_AMD_FLASH + +#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ + +#ifndef __ASSEMBLY__ +extern unsigned long get_clock_freq(void); +#endif /*Replace a call to get_clock_freq (after it is implemented)*/ +#define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +/*#define CONFIG_L2_CACHE*/ /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00400000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +/* + * Make sure required options are set + */ +#ifndef CONFIG_SPD_EEPROM +#error ("CONFIG_SPD_EEPROM is required") +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + + +/* + * Local Bus Definitions + */ + +/* + * FLASH on the Local Bus + * Two banks, 8M each, using the CFI driver. + * Boot from BR0/OR0 bank at 0xff00_0000 + * Alternate BR1/OR1 bank at 0xff80_0000 + * + * BR0, BR1: + * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 + * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 + * Port Size = 16 bits = BRx[19:20] = 10 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 + * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 + * + * OR0, OR1: + * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 + * Reserved ORx[17:18] = 11, confusion here? + * CSNT = ORx[20] = 1 + * ACS = half cycle delay = ORx[21:22] = 11 + * SCY = 6 = ORx[24:27] = 0110 + * TRLX = use relaxed timing = ORx[29] = 1 + * EAD = use external address latch delay = OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx + */ +#define CFG_BCSR_BASE 0xf8000000 + +#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ + +/*Chip select 0 - Flash*/ +#define CFG_BR0_PRELIM 0xfe001001 +#define CFG_OR0_PRELIM 0xfe006ff7 + +/*Chip slelect 1 - BCSR*/ +#define CFG_BR1_PRELIM 0xf8000801 +#define CFG_OR1_PRELIM 0xffffe9f7 + +/*#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} */ +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 512 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + + +/* + * SDRAM on the LocalBus + */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + + +/*Chip select 2 - SDRAM*/ +#define CFG_BR2_PRELIM 0xf0001861 +#define CFG_OR2_PRELIM 0xfc006901 + +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +/* + * Common settings for all Local Bus SDRAM commands. + * At run time, either BSMA1516 (for CPU 1.1) + * or BSMA1617 (for CPU 1.0) (old) + * is OR'ed in too. + */ +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ + | CFG_LBC_LSDMR_PRETOACT7 \ + | CFG_LBC_LSDMR_ACTTORW7 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC4 \ + | CFG_LBC_LSDMR_CL3 \ + | CFG_LBC_LSDMR_RFEN \ + ) + +/* + * The bcsr registers are connected to CS3 on MDS. + * The new memory map places bcsr at 0xf8000000. + * + * For BR3, need: + * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 + * port-size = 8-bits = BR[19:20] = 01 + * no parity checking = BR[21:22] = 00 + * GPMC for MSEL = BR[24:26] = 000 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 + * + * For OR3, need: + * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 + * disable buffer ctrl OR[19] = 0 + * CSNT OR[20] = 1 + * ACS OR[21:22] = 11 + * XACS OR[23] = 1 + * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe + * SETA OR[28] = 0 + * TRLX OR[29] = 1 + * EHTR OR[30] = 1 + * EAD extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 + */ +#define CFG_BCSR (0xf8000000) + +/*Chip slelect 4 - PIB*/ +#define CFG_BR4_PRELIM 0xf8008801 +#define CFG_OR4_PRELIM 0xffffe9f7 + +/*Chip select 5 - PIB*/ +#define CFG_BR5_PRELIM 0xf8010801 +#define CFG_OR5_PRELIM 0xffff69f7 + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser*/ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8568@0" +#define OF_SOC "soc8568@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600" + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 + +/* + * General PCI + * Memory Addresses are mapped 1-1. I/O is mapped from 0 + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ + +#define CFG_PEX_MEM_BASE 0xa0000000 +#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE +#define CFG_PEX_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PEX_IO_BASE 0x00000000 +#define CFG_PEX_IO_PHYS 0xe2800000 +#define CFG_PEX_IO_SIZE 0x00800000 /* 8M */ + +#define CFG_SRIO_MEM_BASE 0xc0000000 + +#if defined(CONFIG_PCI) + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" +#undef CONFIG_MPC85XX_TSEC3 +#undef CONFIG_MPC85XX_TSEC4 +#undef CONFIG_MPC85XX_FEC + +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 3 + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +/* Options are: eTSEC[0-3] */ +#define CONFIG_ETHPRIME "eTSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#define CFG_ENV_SIZE 0x2000 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) +#endif +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#endif + +#define CONFIG_IPADDR 192.168.1.253 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /nfsroot +#define CONFIG_BOOTFILE your.uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs\0" \ + "ramargs=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs\0" \ + + +#define CONFIG_NFSBOOTCOMMAND \ + "run nfsargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + + +#define CONFIG_RAMBOOTCOMMAND \ + "run ramargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/PM520.h b/include/configs/PM520.h index 9c241e6..7d91a01 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -160,7 +160,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #endif /* * I2C configuration diff --git a/include/configs/SBC8560.h b/include/configs/SBC8560.h deleted file mode 100644 index 8b46a17..0000000 --- a/include/configs/SBC8560.h +++ /dev/null @@ -1,410 +0,0 @@ -/* - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao <X.Xiao@motorola.com> - * - * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>. - * Added support for Wind River SBC8560 board - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* mpc8560ads board configuration file */ -/* please refer to doc/README.mpc85xx for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#if XXX -#define DEBUG /* General debug */ -#define ET_DEBUG -#endif -#define TSEC_DEBUG - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ - - -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */ - -#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */ - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_PCI /* pci ethernet support */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ - - -#define CONFIG_ENV_OVERWRITE - -/* Using Localbus SDRAM to emulate flash before we can program the flash, - * normally you need a flash-boot image(u-boot.bin), if so undef this. - */ -#undef CONFIG_RAM_AS_FLASH - -#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ - #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */ -#else - #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */ -#endif - -/* below can be toggled for performance analysis. otherwise use default */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#undef CONFIG_BTB /* toggle branch predition */ -#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 - -#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ - defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ - defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) -#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." -#endif - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ - -#if XXX - #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -#else - #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ -#endif -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ -#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */ - -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ - -#if defined(CONFIG_MPC85xx_REV1) - #define CONFIG_DDR_DLL /* possible DLL fix needed */ -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -#if defined(CONFIG_RAM_AS_FLASH) - #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ - #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ - #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */ - #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ -#else /* Boot from real Flash */ - #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ - #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ - #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */ - #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ -#endif -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* local bus definitions */ -#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ -#define CFG_OR1_PRELIM 0xfc000ff7 - -#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */ -#define CFG_OR2_PRELIM 0x00000000 - -#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ -#define CFG_OR3_PRELIM 0xfc000cc1 - -#if defined(CONFIG_RAM_AS_FLASH) - #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ -#else - #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ -#endif -#define CFG_OR4_PRELIM 0xfc000cc1 - -#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ -#if 1 - #define CFG_OR5_PRELIM 0xff000ff7 -#else - #define CFG_OR5_PRELIM 0xff0000f0 -#endif - -#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ -#define CFG_OR6_PRELIM 0xfc000ff7 -#define CFG_LBC_LCRR 0x00030002 /* local bus freq */ -#define CFG_LBC_LBCR 0x00000000 -#define CFG_LBC_LSRT 0x20000000 -#define CFG_LBC_MRTPR 0x20000000 -#define CFG_LBC_LSDMR_1 0x2861b723 -#define CFG_LBC_LSDMR_2 0x0861b723 -#define CFG_LBC_LSDMR_3 0x0861b723 -#define CFG_LBC_LSDMR_4 0x1861b723 -#define CFG_LBC_LSDMR_5 0x4061b723 - -/* just hijack the MOT BCSR def for SBC8560 misc devices */ -#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000) -/* the size of CS5 needs to be >= 16M for TLB and LAW setups */ - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ - -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */ -#define CONFIG_BAUDRATE 9600 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000) -#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -#define CFG_PCI_MEM_BASE 0xC0000000 -#define CFG_PCI_MEM_PHYS 0xC0000000 -#define CFG_PCI_MEM_SIZE 0x10000000 - -#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ - -# define CONFIG_NET_MULTI 1 -# define CONFIG_MII 1 /* MII PHY management */ -# define CONFIG_MPC85xx_TSEC1 -# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0" -# define TSEC1_PHY_ADDR 25 -# define TSEC1_PHYIDX 0 -/* Options are: TSEC0 */ -# define CONFIG_ETHPRIME "TSEC0" - - -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ - - #undef CONFIG_ETHER_NONE /* define if ether on something else */ - #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ - #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - - #if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CFG_CPMFCR_RAMTYPE 0 - #define CFG_FCC_PSMR (FCC_PSMR_FDE) - - #elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #endif /* CONFIG_ETHER_INDEX */ - - #define CONFIG_MII /* MII PHY management */ - #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - /* - * GPIO pins used for bit-banged MII communications - */ - #define MDIO_PORT 2 /* Port C */ - #define MDIO_ACTIVE (iop->pdir |= 0x00400000) - #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) - #define MDIO_READ ((iop->pdat & 0x00400000) != 0) - - #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - - #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - - #define MIIDELAY udelay(1) - -#endif - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#if 0 -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_PROTECTION /* use hardware protection */ -#endif -#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if 0 -/* XXX This doesn't work and I don't want to fix it */ -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) - #define CFG_RAMBOOT -#else - #undef CFG_RAMBOOT -#endif -#endif - -/* Environment */ -#if !defined(CFG_RAMBOOT) - #if defined(CONFIG_RAM_AS_FLASH) - #define CFG_ENV_IS_NOWHERE - #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) - #define CFG_ENV_SIZE 0x2000 - #else - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) - #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */ - #endif -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600" -/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ -#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" -#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV | \ - CFG_CMD_LOADS )) - #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) - #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) - #endif -#endif - -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x1000000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ - #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/*Note: change below for your network setting!!! */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a -# define CONFIG_HAS_ETH1 -# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b -# define CONFIG_HAS_ETH2 -# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c -#endif - -#define CONFIG_SERVERIP YourServerIP -#define CONFIG_IPADDR YourTargetIP -#define CONFIG_GATEWAYIP YourGatewayIP -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME SBC8560 -#define CONFIG_ROOTPATH YourRootPath -#define CONFIG_BOOTFILE YourImageName - -#endif /* __CONFIG_H */ diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index 8a6e5a6..b42cfb6 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -200,17 +200,17 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ +#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#if defined(CFG_IPBSPEED_133) +#if defined(CFG_IPBCLK_EQUALS_XLBCLK) /* * PCI Bus clocking configuration * * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't - * been tested with a IPB Bus Clock of 66 MHz. + * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock + * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. */ -#define CFG_PCISPEED_66 /* define for 66MHz speed */ +#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ #endif /* @@ -432,7 +432,7 @@ #define CFG_BOOTCS_START CFG_FLASH_BASE #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCISPEED_66 +#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2 #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ #else #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h index f41dbd0..1cc9ce9 100644 --- a/include/configs/TOP5200.h +++ b/include/configs/TOP5200.h @@ -186,7 +186,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ /* * I2C configuration diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 7069b35..7935593 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -269,17 +269,17 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ +#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#if defined(CFG_IPBSPEED_133) && !defined(CONFIG_CAM5200) +#if defined(CFG_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200) /* * PCI Bus clocking configuration * * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't - * been tested with a IPB Bus Clock of 66 MHz. + * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of + * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. */ -#define CFG_PCISPEED_66 /* define for 66MHz speed */ +#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ #endif /* @@ -594,7 +594,7 @@ #define CFG_BOOTCS_START CFG_FLASH_BASE #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCISPEED_66 +#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2 #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ #else #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index 8175703..d8686dd 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -183,7 +183,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #endif /* diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 35b6a51..c72d933 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -34,7 +34,9 @@ #define CONFIG_ACADIA 1 /* Board is Acadia */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EZ 1 /* Specifc 405EZ support*/ -#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ +/* Detect Acadia PLL input clock automatically via CPLD bit */ +#define CONFIG_SYS_CLK_FREQ ((in8(CFG_CPLD_BASE + 0) == 0x0c) ? \ + 66666666 : 33333000) #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */ @@ -224,16 +226,6 @@ #define CONFIG_USB_OHCI #define CONFIG_USB_STORAGE -#if 0 /* test-only */ -#define TEST_ONLY_NAND -#endif - -#ifdef TEST_ONLY_NAND -#define CMD_NAND CFG_CMD_NAND -#else -#define CMD_NAND 0 -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -252,7 +244,7 @@ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ - CMD_NAND | \ + CFG_CMD_NAND | \ CFG_CMD_NET | \ CFG_CMD_NFS | \ CFG_CMD_PCI | \ @@ -300,7 +292,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -#ifdef TEST_ONLY_NAND /*----------------------------------------------------------------------- * NAND FLASH *----------------------------------------------------------------------*/ @@ -308,7 +299,6 @@ #define NAND_MAX_CHIPS 1 #define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ -#endif /*----------------------------------------------------------------------- * Cache Configuration @@ -322,7 +312,7 @@ /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ -#define CFG_NAND_CS 0 /* NAND chip connected to CSx */ +#define CFG_NAND_CS 3 /* NAND chip connected to CSx */ /* Memory Bank 0 (Flash) initialization */ #define CFG_EBC_PB0AP 0x03337200 @@ -358,7 +348,8 @@ /*----------------------------------------------------------------------- * Definitions for GPIO_0 setup (PPC405EZ specific) * - * GPIO0[0-3] - External Bus Controller CS_4 - CS_7 Outputs + * GPIO0[0-2] - External Bus Controller CS_4 - CS_6 Outputs + * GPIO0[3] - NAND FLASH Controller CE3 (NFCE3) Output * GPIO0[4] - External Bus Controller Hold Input * GPIO0[5] - External Bus Controller Priority Input * GPIO0[6] - External Bus Controller HLDA Output @@ -376,10 +367,10 @@ */ #define CFG_GPIO0_TCR 0xC0000000 #define CFG_GPIO0_OSRL 0x50000000 -#define CFG_GPIO0_OSRH 0x00000055 +#define CFG_GPIO0_OSRH 0x02000055 #define CFG_GPIO0_ISR1L 0x00000000 #define CFG_GPIO0_ISR1H 0x00000055 -#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TSRL 0x02000000 #define CFG_GPIO0_TSRH 0x00000055 /*----------------------------------------------------------------------- diff --git a/include/configs/aev.h b/include/configs/aev.h index 8d9f0a1..6c2a360 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -166,17 +166,17 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ +#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#if defined(CFG_IPBSPEED_133) +#if defined(CFG_IPBCLK_EQUALS_XLBCLK) /* * PCI Bus clocking configuration * * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't - * been tested with a IPB Bus Clock of 66 MHz. + * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock + * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. */ -#define CFG_PCISPEED_66 /* define for 66MHz speed */ +#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ #endif /* @@ -362,7 +362,7 @@ #define CFG_BOOTCS_START CFG_FLASH_BASE #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCISPEED_66 +#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2 #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ #else #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index bcc736c..db58a9f 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005-2006 + * (C) Copyright 2005-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this @@ -43,7 +43,6 @@ * 2nd ethernet port you have to "undef" the following define. */ #define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */ -#define CFG_NAND_LEGACY /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the @@ -143,65 +142,13 @@ #endif /* CFG_ENV_IS_IN_FLASH */ /*----------------------------------------------------------------------- - * NAND-FLASH related + * NAND FLASH *----------------------------------------------------------------------*/ -#define NAND_CMD_REG (0x00) /* NandFlash Command Register */ -#define NAND_ADDR_REG (0x04) /* NandFlash Address Register */ -#define NAND_DATA_REG (0x08) /* NandFlash Data Register */ -#define NAND_ECC0_REG (0x10) /* NandFlash ECC Register0 */ -#define NAND_ECC1_REG (0x14) /* NandFlash ECC Register1 */ -#define NAND_ECC2_REG (0x18) /* NandFlash ECC Register2 */ -#define NAND_ECC3_REG (0x1C) /* NandFlash ECC Register3 */ -#define NAND_ECC4_REG (0x20) /* NandFlash ECC Register4 */ -#define NAND_ECC5_REG (0x24) /* NandFlash ECC Register5 */ -#define NAND_ECC6_REG (0x28) /* NandFlash ECC Register6 */ -#define NAND_ECC7_REG (0x2C) /* NandFlash ECC Register7 */ -#define NAND_CR0_REG (0x30) /* NandFlash Device Bank0 Config Register */ -#define NAND_CR1_REG (0x34) /* NandFlash Device Bank1 Config Register */ -#define NAND_CR2_REG (0x38) /* NandFlash Device Bank2 Config Register */ -#define NAND_CR3_REG (0x3C) /* NandFlash Device Bank3 Config Register */ -#define NAND_CCR_REG (0x40) /* NandFlash Core Configuration Register */ -#define NAND_STAT_REG (0x44) /* NandFlash Device Status Register */ -#define NAND_HWCTL_REG (0x48) /* NandFlash Direct Hwd Control Register */ -#define NAND_REVID_REG (0x50) /* NandFlash Core Revision Id Register */ - -/* Nand Flash K9F1208U0A Command Set => Nand Flash 0 */ -#define NAND0_CMD_READ1_HALF1 0x00 /* Starting addr for 1rst half of registers */ -#define NAND0_CMD_READ1_HALF2 0x01 /* Starting addr for 2nd half of registers */ -#define NAND0_CMD_READ2 0x50 -#define NAND0_CMD_READ_ID 0x90 -#define NAND0_CMD_READ_STATUS 0x70 -#define NAND0_CMD_RESET 0xFF -#define NAND0_CMD_PAGE_PROG 0x80 -#define NAND0_CMD_PAGE_PROG_TRUE 0x10 -#define NAND0_CMD_PAGE_PROG_DUMMY 0x11 -#define NAND0_CMD_BLOCK_ERASE 0x60 -#define NAND0_CMD_BLOCK_ERASE_END 0xD0 - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_CMD_REG) = d;} while(0) -#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_ADDR_REG) = d;} while(0) -#define WRITE_NAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_DATA_REG) = d;} while(0) -#define READ_NAND(adr) (*(volatile u8 *)((ulong)adr+NAND_DATA_REG)) -#define NAND_WAIT_READY(nand) while (!(*(volatile u8 *)((ulong)nand->IO_ADDR+NAND_STAT_REG) & 0x01)) - -/* not needed with 440EP NAND controller */ -#define NAND_CTL_CLRALE(nandptr) -#define NAND_CTL_SETALE(nandptr) -#define NAND_CTL_CLRCLE(nandptr) -#define NAND_CTL_SETCLE(nandptr) -#define NAND_DISABLE_CE(nand) -#define NAND_ENABLE_CE(nand) +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_CS 1 +#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ /*----------------------------------------------------------------------- * DDR SDRAM diff --git a/include/configs/canmb.h b/include/configs/canmb.h index 2c160a4..ec6d57e 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -111,7 +111,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ /* * Flash configuration, expect one 16 Megabyte Bank at most diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h index f9586fb..f5efcd9 100644 --- a/include/configs/cpci5200.h +++ b/include/configs/cpci5200.h @@ -179,7 +179,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #endif /* * I2C configuration diff --git a/include/configs/delta.h b/include/configs/delta.h index 91284fd..1568120 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -188,7 +188,6 @@ /* * NAND Flash */ -/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */ #undef CFG_NAND_LEGACY #define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */ diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index 095b5f6..4d813d8 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -110,7 +110,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ /* * I2C configuration diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index 773d5d2..ad3cf06 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -147,7 +147,7 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ +#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ /* * Flash configuration diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 7f55366..cc47a16 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -360,7 +360,19 @@ EBC_BXCR_BW_16BIT) /* Memory Bank 1 (Xilinx System ACE controller) initialization */ -#define CFG_EBC_PB1AP 0x7F8FFE80 +#define CFG_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(4) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(0) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_NONDELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) #define CFG_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CFG_ACE_BASE) | \ EBC_BXCR_BS_1MB | \ EBC_BXCR_BU_RW | \ diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index 621a81c..c2324a0 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -169,7 +169,7 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ +#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ /* * I2C configuration diff --git a/include/configs/ml401.h b/include/configs/ml401.h index cb159e7..3db2877 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -28,6 +28,7 @@ #include "../board/xilinx/ml401/xparameters.h" #define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */ +#define MICROBLAZE_V5 1 #define CONFIG_ML401 1 /* ML401 Board */ /* uart */ @@ -36,11 +37,11 @@ #define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE } /* setting reset address */ -#define CFG_RESET_ADDRESS TEXT_BASE +/*#define CFG_RESET_ADDRESS TEXT_BASE*/ /* ethernet */ #define CONFIG_EMACLITE 1 -#define XPAR_EMAC_0_DEVICE_ID XPAR_XEMAC_NUM_INSTANCES +#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID /* gpio */ #define CFG_GPIO_0 1 @@ -58,6 +59,10 @@ #define FREQUENCE XILINX_CLOCK_FREQ #define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 ) +/* FSL */ +#define CFG_FSL_2 +#define FSL_INTR_2 1 + /* * memory layout - Example * TEXT_BASE = 0x1200_0000; @@ -93,7 +98,8 @@ /* global pointer */ #define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */ -#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */ +/* start of global data */ +#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* monitor code */ #define SIZE 0x40000 @@ -117,6 +123,7 @@ #define CFG_FLASH_EMPTY_INFO 1 /* ?empty sector */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + #define CFG_FLASH_PROTECTION /* hardware flash protection */ #ifdef RAMENV #define CFG_ENV_IS_NOWHERE 1 @@ -135,6 +142,7 @@ #define CFG_ENV_IS_NOWHERE 1 #define CFG_ENV_SIZE 0x1000 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE) + #define CFG_FLASH_PROTECTION /* hardware flash protection */ #endif /* !FLASH */ #ifdef FLASH @@ -152,8 +160,13 @@ CFG_CMD_IMI |\ CFG_CMD_NET |\ CFG_CMD_CACHE |\ + CFG_CMD_FAT |\ + CFG_CMD_EXT2 |\ + CFG_CMD_JFFS2 |\ + CFG_CMD_ECHO |\ CFG_CMD_IMLS |\ CFG_CMD_FLASH |\ + CFG_CMD_MFSL |\ CFG_CMD_PING \ ) #else /* !RAMENV */ @@ -174,6 +187,11 @@ CFG_CMD_FLASH |\ CFG_CMD_PING |\ CFG_CMD_ENV |\ + CFG_CMD_FAT |\ + CFG_CMD_EXT2 |\ + CFG_CMD_JFFS2 |\ + CFG_CMD_ECHO |\ + CFG_CMD_MFSL |\ CFG_CMD_SAVES \ ) @@ -189,16 +207,30 @@ CFG_CMD_BDI |\ CFG_CMD_RUN |\ CFG_CMD_LOADS |\ + CFG_CMD_FAT |\ + CFG_CMD_EXT2 |\ CFG_CMD_LOADB |\ CFG_CMD_IMI |\ CFG_CMD_NET |\ CFG_CMD_CACHE |\ + CFG_CMD_MFSL |\ CFG_CMD_PING \ ) #endif /* !FLASH */ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +/* JFFS2 partitions */ +#define CONFIG_JFFS2_CMDLINE /* mtdparts command line support */ +#define MTDIDS_DEFAULT "nor0=ml401-0" + +/* default mtd partition table */ +#define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\ + "256k(env),3m(kernel),1m(romfs),"\ + "1m(cramfs),-(jffs2)" +#endif + /* Miscellaneous configurable options */ #define CFG_PROMPT "U-Boot-mONStR> " #define CFG_CBSIZE 512 /* size of console buffer */ @@ -207,7 +239,7 @@ #define CFG_LONGHELP #define CFG_LOAD_ADDR 0x12000000 /* default load address */ -#define CONFIG_BOOTDELAY 30 +#define CONFIG_BOOTDELAY 30 #define CONFIG_BOOTARGS "root=romfs" #define CONFIG_HOSTNAME "ml401" #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" @@ -221,10 +253,19 @@ #define CFG_HZ 1000 /* system ace */ -/*#define CONFIG_SYSTEMACE -#define DEBUG_SYSTEMACE -#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR -#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH -#define CONFIG_DOS_PARTITION -*/ +#define CONFIG_SYSTEMACE +/* #define DEBUG_SYSTEMACE */ +#define SYSTEMACE_CONFIG_FPGA +#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR +#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH +#define CONFIG_DOS_PARTITION + +#define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo" + +#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\ + "nor0=ml401-0\0"\ + "mtdparts=mtdparts=ml401-0:"\ + "256k(u-boot),256k(env),3m(kernel),"\ + "1m(romfs),1m(cramfs),-(jffs2)\0" + #endif /* __CONFIG_H */ diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 5328e8d..e3899a5 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -26,12 +26,10 @@ #ifndef __CONFIG_H #define __CONFIG_H - /* * High Level Configuration Options */ - /* CPU and board */ #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ @@ -50,7 +48,14 @@ CFG_CMD_MII | \ CFG_CMD_BEDBUG | \ CFG_CMD_NET | \ - CFG_CMD_PING) + CFG_CMD_PING | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_I2C | \ + CFG_CMD_DATE | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DTT) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -71,7 +76,7 @@ #define CONFIG_MPC5xxx_FEC 1 #define CONFIG_PHY_ADDR 0x2 #define CONFIG_PHY_TYPE 0x79c874 - +#define CONFIG_RESET_PHY_R 1 /* * Autobooting @@ -94,42 +99,51 @@ * Default environment settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "sdram_test=0\0" \ "netdev=eth0\0" \ "hostname=motionpro\0" \ "netmask=255.255.0.0\0" \ "ipaddr=192.168.160.22\0" \ "serverip=192.168.1.1\0" \ "gatewayip=192.168.1.1\0" \ - "kernel_addr=200000\0" \ + "console=ttyPSC0,115200\0" \ "u-boot_addr=100000\0" \ - "kernel_sector=20\0" \ - "kernel_size=1000\0" \ - "console=ttyS0,115200\0" \ + "kernel_addr=200000\0" \ + "fdt_addr=400000\0" \ + "ramdisk_addr=500000\0" \ + "multi_image_addr=800000\0" \ "rootpath=/opt/eldk-4.1/ppc_6xx\0" \ - "bootfile=/tftpboot/motionpro/uImage\0" \ "u-boot=/tftpboot/motionpro/u-boot.bin\0" \ - "load=tftp $(u-boot_addr) $(u-boot)\0" \ + "bootfile=/tftpboot/motionpro/uImage\0" \ + "fdt_file=/tftpboot/motionpro/motionpro.dtb\0" \ + "ramdisk_file=/tftpboot/motionpro/uRamdisk\0" \ + "multi_image_file=kernel+initrd+dtb.img\0" \ + "load=tftp ${u-boot_addr} ${u-boot}\0" \ "update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; " \ - "cp.b $(u-boot_addr) fff00000 $(filesize);" \ + "cp.b ${u-boot_addr} fff00000 ${filesize};" \ "prot on fff00000 fff3ffff\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) console=$(console) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):" \ - "$(netmask):$(hostname):$(netdev):off panic=1\0" \ - "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip;bootm $(kernel_addr) " \ - "$(ramdisk_addr)\0" \ - "net_nfs=tftp $(kernel_addr) $(bootfile); run nfsargs addip; " \ - "bootm $(kernel_addr)\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "fstype=ext3\0" \ - "fatargs=setenv bootargs init=/linuxrc rw\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ + "fat_args=setenv bootargs rw\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off panic=1 " \ + "console=${console}\0" \ + "net_nfs=tftp ${kernel_addr} ${bootfile}; " \ + "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip; " \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "net_self=tftp ${kernel_addr} ${bootfile}; " \ + "tftp ${fdt_addr} ${fdt_file}; " \ + "tftp ${ramdisk_addr} ${ramdisk_file}; " \ + "run ramargs addip; " \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "fat_multi=run fat_args addip; fatload ide 0:1 " \ + "${multi_image_addr} ${multi_image_file}; " \ + "bootm ${multi_image_addr}\0" \ "" #define CONFIG_BOOTCOMMAND "run net_nfs" - /* * do board-specific init */ @@ -148,6 +162,12 @@ /* + * Set IPB speed to 100MHz + */ +#define CFG_IPBCLK_EQUALS_XLBCLK + + +/* * Memory map */ /* @@ -243,6 +263,84 @@ #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ #define CONFIG_FLASH_16BIT /* Flash is 16-bit */ +/* + * MTD configuration + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=motionpro-0" +#define MTDPARTS_DEFAULT "mtdparts=motionpro-0:" \ + "13m(fs),2m(kernel),256k(uboot)," \ + "64k(env),64k(redund_env),64k(dtb)," \ + "-(user_data)" + +/* + * IDE/ATA configuration + */ +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA +#define CFG_IDE_MAXBUS 1 +#define CFG_IDE_MAXDEVICE 1 +#define CONFIG_IDE_PREINIT + +#define CFG_ATA_DATA_OFFSET 0x0060 +#define CFG_ATA_REG_OFFSET CFG_ATA_DATA_OFFSET +#define CFG_ATA_STRIDE 4 +#define CONFIG_DOS_PARTITION + + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* select I2C module #2 */ +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* DTT driver needs this */ +#define CFG_EEPROM_PAGE_WRITE_BITS 1 /* 2 bytes per write cycle */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 5 /* 2ms/cycle + 3ms extra */ +#define CFG_I2C_MULTI_EEPROMS 1 /* 2 EEPROMs (addr:50,52) */ + + +/* + * RTC configuration + */ +#define CONFIG_RTC_DS1337 1 +#define CFG_I2C_RTC_ADDR 0x68 + + +/* + * Status LED configuration + */ +#define CONFIG_STATUS_LED /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED + +#define ENABLE_GPIO_OUT 0x00000024 +#define LED_ON 0x00000010 + +#ifndef __ASSEMBLY__ +/* + * In case of Motion-PRO, a LED is identified by its corresponding + * GPT Enable and Mode Select Register. + */ +typedef volatile unsigned long * led_id_t; + +extern void __led_init(led_id_t id, int state); +extern void __led_toggle(led_id_t id); +extern void __led_set(led_id_t id, int state); +#endif /* __ASSEMBLY__ */ + + +/* + * Temperature sensor + */ +#define CONFIG_DTT_LM75 1 +#define CONFIG_DTT_SENSORS { 0x49 } + /* * Environment settings @@ -253,6 +351,9 @@ #define CFG_ENV_SIZE 0x1000 #define CFG_ENV_SECT_SIZE 0x10000 +/* Configuration of redundant environment */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) /* * Pin multiplexing configuration @@ -270,11 +371,17 @@ /* + * Motion-PRO's CPLD revision control register + */ +#define CPLD_REV_REGISTER (CFG_CS2_START + 0x06) + + +/* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ @@ -302,4 +409,15 @@ /* Not needed for MPC 5xxx U-Boot, but used by tools/updater */ #define CFG_RESET_ADDRESS 0xfff00100 +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 +#define OF_CPU "PowerPC,5200@0" +#define OF_SOC "soc5200@f0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" + #endif /* __CONFIG_H */ diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h index 5c05a74..63d0da7 100644 --- a/include/configs/o2dnt.h +++ b/include/configs/o2dnt.h @@ -137,17 +137,17 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ +#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#if defined(CFG_IPBSPEED_133) +#if defined(CFG_IPBCLK_EQUALS_XLBCLK) /* * PCI Bus clocking configuration * * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't - * been tested with a IPB Bus Clock of 66 MHz. + * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock + * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. */ -#define CFG_PCISPEED_66 /* define for 66MHz speed */ +#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ #endif #endif @@ -276,7 +276,7 @@ #define CFG_BOOTCS_START CFG_FLASH_BASE #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCISPEED_66 +#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash). */ diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h index fefdb3c..7151a9e 100644 --- a/include/configs/pf5200.h +++ b/include/configs/pf5200.h @@ -171,7 +171,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #endif /* * I2C configuration diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 1f19621..e1572ba 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -38,7 +38,9 @@ #define CONFIG_440GRX 1 /* Specific PPC440GRx */ #endif #define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_SYS_CLK_FREQ 33000000 /* external freq to pll */ +/* Detect Sequoia PLL input clock automatically via CPLD bit */ +#define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \ + 33333333 : 33000000) #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h index e106b3b..185c2d4 100644 --- a/include/configs/smmaco4.h +++ b/include/configs/smmaco4.h @@ -138,17 +138,17 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ +#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#if defined(CFG_IPBSPEED_133) +#if defined(CFG_IPBCLK_EQUALS_XLBCLK) /* * PCI Bus clocking configuration * * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't - * been tested with a IPB Bus Clock of 66 MHz. + * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock + * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. */ -#define CFG_PCISPEED_66 /* define for 66MHz speed */ +#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ #endif /* @@ -357,7 +357,7 @@ #define CFG_BOOTCS_START CFG_FLASH_BASE #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCISPEED_66 +#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2 #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ #else #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ diff --git a/include/configs/spieval.h b/include/configs/spieval.h index f40dde2..fd138a5 100644 --- a/include/configs/spieval.h +++ b/include/configs/spieval.h @@ -219,17 +219,17 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ +#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#if defined(CFG_IPBSPEED_133) +#if defined(CFG_IPBCLK_EQUALS_XLBCLK) /* * PCI Bus clocking configuration * * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't - * been tested with a IPB Bus Clock of 66 MHz. + * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock + * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. */ -#define CFG_PCISPEED_66 /* define for 66MHz speed */ +#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ #endif /* @@ -444,7 +444,7 @@ #define CFG_BOOTCS_START CFG_FLASH_BASE #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCISPEED_66 +#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2 #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ #else #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ diff --git a/include/configs/uc101.h b/include/configs/uc101.h index 8cd8e9b..ff061ee 100644 --- a/include/configs/uc101.h +++ b/include/configs/uc101.h @@ -114,7 +114,7 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ +#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ /* * I2C configuration diff --git a/include/configs/v38b.h b/include/configs/v38b.h index e19591d..0b7b19e 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -167,7 +167,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #endif /* diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h index a2f4810..b4c720d 100644 --- a/include/configs/xupv2p.h +++ b/include/configs/xupv2p.h @@ -132,6 +132,8 @@ CFG_CMD_LOADS |\ CFG_CMD_LOADB |\ CFG_CMD_MISC |\ + CFG_CMD_FAT |\ + CFG_CMD_EXT2 |\ CFG_CMD_PING \ ) @@ -163,12 +165,12 @@ "base 0;" \ "echo" - /* system ace */ -/*#define CONFIG_SYSTEMACE -#define DEBUG_SYSTEMACE -#define CFG_SYSTEMACE_BASE 0xCF000000 -#define CFG_SYSTEMACE_WIDTH 16 -#define CONFIG_DOS_PARTITION*/ +#define CONFIG_SYSTEMACE +/* #define DEBUG_SYSTEMACE */ +#define SYSTEMACE_CONFIG_FPGA +#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR +#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH +#define CONFIG_DOS_PARTITION #endif /* __CONFIG_H */ diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index c6aa8ec..1e8ed7a 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -174,7 +174,6 @@ /* * NAND Flash */ -/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */ #define CONFIG_NEW_NAND_CODE #define CFG_NAND0_BASE 0x0 #undef CFG_NAND1_BASE diff --git a/include/linux/stat.h b/include/linux/stat.h index 43fd53f..37f2924 100644 --- a/include/linux/stat.h +++ b/include/linux/stat.h @@ -67,7 +67,8 @@ struct stat { #endif /* __PPC__ */ -#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__) +#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__) ||\ + defined (__microblaze__) struct stat { unsigned short st_dev; diff --git a/include/mpc83xx.h b/include/mpc83xx.h index c2a4ff5..60fc214 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -95,6 +95,11 @@ #define SPR_8321E_REV11 0x80660011 #define SPR_8321_REV11 0x80670011 +#define SPR_8311_REV10 0x80B30010 +#define SPR_8311E_REV10 0x80B20010 +#define SPR_8313_REV10 0x80B10010 +#define SPR_8313E_REV10 0x80B00010 + /* SPCR - System Priority Configuration Register */ #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ @@ -121,6 +126,15 @@ #define SPCR_TSEC2BDP_SHIFT (31-29) #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ #define SPCR_TSEC2EP_SHIFT (31-31) + +#elif defined(CONFIG_MPC831X) +/* SPCR bits - MPC831x specific */ +#define SPCR_TSECDP 0x00003000 /* TSEC data priority */ +#define SPCR_TSECDP_SHIFT (31-19) +#define SPCR_TSECEP 0x00000C00 /* TSEC emergency priority */ +#define SPCR_TSECEP_SHIFT (31-21) +#define SPCR_TSECBDP 0x00000300 /* TSEC buffer descriptor priority */ +#define SPCR_TSECBDP_SHIFT (31-23) #endif /* SICRL/H - System I/O Configuration Register Low/High @@ -195,6 +209,36 @@ #define SICRL_PCI_MSRC 0x10000000 #define SICRL_URT_CTPR 0x06000000 #define SICRL_IRQ_CTPR 0x00C00000 + +#elif defined(CONFIG_MPC831X) +/* SICRL bits - MPC831x specific */ +#define SICRL_LBC 0x30000000 +#define SICRL_UART 0x0C000000 +#define SICRL_SPI_A 0x03000000 +#define SICRL_SPI_B 0x00C00000 +#define SICRL_SPI_C 0x00300000 +#define SICRL_SPI_D 0x000C0000 +#define SICRL_USBDR 0x00000C00 +#define SICRL_ETSEC1_A 0x0000000C +#define SICRL_ETSEC2_A 0x00000003 + +/* SICRH bits - MPC831x specific */ +#define SICRH_INTR_A 0x02000000 +#define SICRH_INTR_B 0x00C00000 +#define SICRH_IIC 0x00300000 +#define SICRH_ETSEC2_B 0x000C0000 +#define SICRH_ETSEC2_C 0x00030000 +#define SICRH_ETSEC2_D 0x0000C000 +#define SICRH_ETSEC2_E 0x00003000 +#define SICRH_ETSEC2_F 0x00000C00 +#define SICRH_ETSEC2_G 0x00000300 +#define SICRH_ETSEC1_B 0x00000080 +#define SICRH_ETSEC1_C 0x00000060 +#define SICRH_GTX1_DLY 0x00000008 +#define SICRH_GTX2_DLY 0x00000004 +#define SICRH_TSOBI1 0x00000002 +#define SICRH_TSOBI2 0x00000001 + #endif /* SWCRR - System Watchdog Control Register @@ -393,6 +437,28 @@ #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 +#if defined(CONFIG_MPC831X) +#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 +#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 +#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 +#define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 + +#define HRCWH_RL_EXT_LEGACY 0x00000000 +#define HRCWH_RL_EXT_NAND 0x00040000 + +#define HRCWH_TSEC1M_IN_MII 0x00000000 +#define HRCWH_TSEC1M_IN_RMII 0x00002000 +#define HRCWH_TSEC1M_IN_RGMII 0x00006000 +#define HRCWH_TSEC1M_IN_RTBI 0x0000A000 +#define HRCWH_TSEC1M_IN_SGMII 0x0000C000 + +#define HRCWH_TSEC2M_IN_MII 0x00000000 +#define HRCWH_TSEC2M_IN_RMII 0x00000400 +#define HRCWH_TSEC2M_IN_RGMII 0x00000C00 +#define HRCWH_TSEC2M_IN_RTBI 0x00001400 +#define HRCWH_TSEC2M_IN_SGMII 0x00001800 +#endif + #if defined(CONFIG_MPC834X) #define HRCWH_TSEC1M_IN_RGMII 0x00000000 #define HRCWH_TSEC1M_IN_RTBI 0x00004000 @@ -523,6 +589,18 @@ #define SCCR_TSEC2CM_1 0x10000000 #define SCCR_TSEC2CM_2 0x20000000 #define SCCR_TSEC2CM_3 0x30000000 + +#elif defined(CONFIG_MPC831X) +/* TSEC1 bits are for TSEC2 as well */ +#define SCCR_TSEC1CM 0xc0000000 +#define SCCR_TSEC1CM_SHIFT 30 +#define SCCR_TSEC1CM_1 0x40000000 +#define SCCR_TSEC1CM_2 0x80000000 +#define SCCR_TSEC1CM_3 0xC0000000 + +#define SCCR_TSEC1ON 0x20000000 +#define SCCR_TSEC2ON 0x10000000 + #endif #define SCCR_USBMPHCM 0x00c00000 @@ -556,6 +634,25 @@ #define CSCONFIG_COL_BIT_10 0x00000002 #define CSCONFIG_COL_BIT_11 0x00000003 +/* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 + */ +#define TIMING_CFG0_RWT 0xC0000000 +#define TIMING_CFG0_RWT_SHIFT 30 +#define TIMING_CFG0_WRT 0x30000000 +#define TIMING_CFG0_WRT_SHIFT 28 +#define TIMING_CFG0_RRT 0x0C000000 +#define TIMING_CFG0_RRT_SHIFT 26 +#define TIMING_CFG0_WWT 0x03000000 +#define TIMING_CFG0_WWT_SHIFT 24 +#define TIMING_CFG0_ACT_PD_EXIT 0x00700000 +#define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20 +#define TIMING_CFG0_PRE_PD_EXIT 0x00070000 +#define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 +#define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 +#define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 +#define TIMING_CFG0_MRS_CYC 0x00000F00 +#define TIMING_CFG0_MRS_CYC_SHIFT 0 + /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 */ #define TIMING_CFG1_PRETOACT 0x70000000 @@ -586,6 +683,17 @@ #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ +#define TIMING_CFG2_ADD_LAT 0x70000000 +#define TIMING_CFG2_ADD_LAT_SHIFT 28 +#define TIMING_CFG2_WR_LAT_DELAY 0x00380000 +#define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19 +#define TIMING_CFG2_RD_TO_PRE 0x0000E000 +#define TIMING_CFG2_RD_TO_PRE_SHIFT 13 +#define TIMING_CFG2_CKE_PLS 0x000001C0 +#define TIMING_CFG2_CKE_PLS_SHIFT 6 +#define TIMING_CFG2_FOUR_ACT 0x0000003F +#define TIMING_CFG2_FOUR_ACT_SHIFT 0 + /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration */ #define SDRAM_CFG_MEM_EN 0x80000000 @@ -593,13 +701,14 @@ #define SDRAM_CFG_ECC_EN 0x20000000 #define SDRAM_CFG_RD_EN 0x10000000 #define SDRAM_CFG_SDRAM_TYPE 0x03000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 #define SDRAM_CFG_32_BE 0x00080000 #define SDRAM_CFG_8_BE 0x00040000 #define SDRAM_CFG_NCAP 0x00020000 #define SDRAM_CFG_2T_EN 0x00008000 -#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 +#define SDRAM_CFG_BI 0x00000001 /* DDR_SDRAM_MODE - DDR SDRAM Mode Register */ @@ -732,11 +841,15 @@ #define BR_PS_32 0x00001800 /* Port Size 32 bit */ #define BR_DECC 0x00000600 #define BR_DECC_SHIFT 9 +#define BR_DECC_OFF 0x00000000 +#define BR_DECC_CHK 0x00000200 +#define BR_DECC_CHK_GEN 0x00000400 #define BR_WP 0x00000100 #define BR_WP_SHIFT 8 #define BR_MSEL 0x000000E0 #define BR_MSEL_SHIFT 5 #define BR_MS_GPCM 0x00000000 /* GPCM */ +#define BR_MS_FCM 0x00000020 /* FCM */ #define BR_MS_SDRAM 0x00000060 /* SDRAM */ #define BR_MS_UPMA 0x00000080 /* UPMA */ #define BR_MS_UPMB 0x000000A0 /* UPMB */ @@ -803,6 +916,34 @@ #define OR_GPCM_EAD 0x00000001 #define OR_GPCM_EAD_SHIFT 0 +#define OR_FCM_AM 0xFFFF8000 +#define OR_FCM_AM_SHIFT 15 +#define OR_FCM_BCTLD 0x00001000 +#define OR_FCM_BCTLD_SHIFT 12 +#define OR_FCM_PGS 0x00000400 +#define OR_FCM_PGS_SHIFT 10 +#define OR_FCM_CSCT 0x00000200 +#define OR_FCM_CSCT_SHIFT 9 +#define OR_FCM_CST 0x00000100 +#define OR_FCM_CST_SHIFT 8 +#define OR_FCM_CHT 0x00000080 +#define OR_FCM_CHT_SHIFT 7 +#define OR_FCM_SCY 0x00000070 +#define OR_FCM_SCY_SHIFT 4 +#define OR_FCM_SCY_1 0x00000010 +#define OR_FCM_SCY_2 0x00000020 +#define OR_FCM_SCY_3 0x00000030 +#define OR_FCM_SCY_4 0x00000040 +#define OR_FCM_SCY_5 0x00000050 +#define OR_FCM_SCY_6 0x00000060 +#define OR_FCM_SCY_7 0x00000070 +#define OR_FCM_RST 0x00000008 +#define OR_FCM_RST_SHIFT 3 +#define OR_FCM_TRLX 0x00000004 +#define OR_FCM_TRLX_SHIFT 2 +#define OR_FCM_EHTR 0x00000002 +#define OR_FCM_EHTR_SHIFT 1 + #define OR_UPM_AM 0xFFFF8000 #define OR_UPM_AM_SHIFT 15 #define OR_UPM_XAM 0x00006000 @@ -1019,4 +1160,118 @@ #define PIWAR_IWS_1G 0x0000001D #define PIWAR_IWS_2G 0x0000001E +/* PMCCR1 - PCI Configuration Register 1 + */ +#define PMCCR1_POWER_OFF 0x00000020 + +/* FMR - Flash Mode Register + */ +#define FMR_CWTO 0x0000F000 +#define FMR_CWTO_SHIFT 12 +#define FMR_BOOT 0x00000800 +#define FMR_ECCM 0x00000100 +#define FMR_AL 0x00000030 +#define FMR_AL_SHIFT 4 +#define FMR_OP 0x00000003 +#define FMR_OP_SHIFT 0 + +/* FIR - Flash Instruction Register + */ +#define FIR_OP0 0xF0000000 +#define FIR_OP0_SHIFT 28 +#define FIR_OP1 0x0F000000 +#define FIR_OP1_SHIFT 24 +#define FIR_OP2 0x00F00000 +#define FIR_OP2_SHIFT 20 +#define FIR_OP3 0x000F0000 +#define FIR_OP3_SHIFT 16 +#define FIR_OP4 0x0000F000 +#define FIR_OP4_SHIFT 12 +#define FIR_OP5 0x00000F00 +#define FIR_OP5_SHIFT 8 +#define FIR_OP6 0x000000F0 +#define FIR_OP6_SHIFT 4 +#define FIR_OP7 0x0000000F +#define FIR_OP7_SHIFT 0 +#define FIR_OP_NOP 0x0 /* No operation and end of sequence */ +#define FIR_OP_CA 0x1 /* Issue current column address */ +#define FIR_OP_PA 0x2 /* Issue current block+page address */ +#define FIR_OP_UA 0x3 /* Issue user defined address */ +#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ +#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ +#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ +#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ +#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ +#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ +#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ +#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ +#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ +#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ +#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ +#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */ + +/* FCR - Flash Command Register + */ +#define FCR_CMD0 0xFF000000 +#define FCR_CMD0_SHIFT 24 +#define FCR_CMD1 0x00FF0000 +#define FCR_CMD1_SHIFT 16 +#define FCR_CMD2 0x0000FF00 +#define FCR_CMD2_SHIFT 8 +#define FCR_CMD3 0x000000FF +#define FCR_CMD3_SHIFT 0 + +/* FBAR - Flash Block Address Register + */ +#define FBAR_BLK 0x00FFFFFF + +/* FPAR - Flash Page Address Register + */ +#define FPAR_SP_PI 0x00007C00 +#define FPAR_SP_PI_SHIFT 10 +#define FPAR_SP_MS 0x00000200 +#define FPAR_SP_CI 0x000001FF +#define FPAR_SP_CI_SHIFT 0 +#define FPAR_LP_PI 0x0003F000 +#define FPAR_LP_PI_SHIFT 12 +#define FPAR_LP_MS 0x00000800 +#define FPAR_LP_CI 0x000007FF +#define FPAR_LP_CI_SHIFT 0 + +/* LTESR - Transfer Error Status Register + */ +#define LTESR_BM 0x80000000 +#define LTESR_FCT 0x40000000 +#define LTESR_PAR 0x20000000 +#define LTESR_WP 0x04000000 +#define LTESR_ATMW 0x00800000 +#define LTESR_ATMR 0x00400000 +#define LTESR_CS 0x00080000 +#define LTESR_CC 0x00000001 + +/* DDR Control Driver Register + */ +#define DDRCDR_EN 0x40000000 +#define DDRCDR_PZ 0x3C000000 +#define DDRCDR_PZ_MAXZ 0x00000000 +#define DDRCDR_PZ_HIZ 0x20000000 +#define DDRCDR_PZ_NOMZ 0x30000000 +#define DDRCDR_PZ_LOZ 0x38000000 +#define DDRCDR_PZ_MINZ 0x3C000000 +#define DDRCDR_NZ 0x3C000000 +#define DDRCDR_NZ_MAXZ 0x00000000 +#define DDRCDR_NZ_HIZ 0x02000000 +#define DDRCDR_NZ_NOMZ 0x03000000 +#define DDRCDR_NZ_LOZ 0x03800000 +#define DDRCDR_NZ_MINZ 0x03C00000 +#define DDRCDR_ODT 0x00080000 +#define DDRCDR_DDR_CFG 0x00040000 +#define DDRCDR_M_ODR 0x00000002 +#define DDRCDR_Q_DRN 0x00000001 + +#ifndef __ASSEMBLY__ +struct pci_region; +void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot); +#endif + #endif /* __MPC83XX_H__ */ diff --git a/include/mpc86xx.h b/include/mpc86xx.h index bc8ba3f..673bfed 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -9,6 +9,15 @@ #define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ + +/* + * platform register addresses + */ + +#define GUTS_SVR (CFG_CCSRBAR + 0xE00A4) +#define MCM_ABCR (CFG_CCSRBAR + 0x01000) +#define MCM_DBCR (CFG_CCSRBAR + 0x01008) + /* * l2cr values. Look in config_<BOARD>.h for the actual setup */ diff --git a/include/ppc405.h b/include/ppc405.h index a2503a9..fffae4d 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -547,8 +547,8 @@ #define sdrcfga (SDR_DCR_BASE+0x0) /* ADDR */ #define sdrcfgd (SDR_DCR_BASE+0x1) /* Data */ -#define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data) -#define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd) +#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0) +#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0) #define sdrnand0 0x4000 #define sdrultra0 0x4040 @@ -593,8 +593,8 @@ /* * Macro for accessing the indirect CPR register */ -#define mtcpr(reg, data) mtdcr(cprcfga,reg);mtdcr(cprcfgd,data) -#define mfcpr(reg, data) mtdcr(cprcfga,reg);data = mfdcr(cprcfgd) +#define mtcpr(reg, data) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,data); } while (0) +#define mfcpr(reg, data) do { mtdcr(cprcfga,reg);data = mfdcr(cprcfgd); } while (0) #define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ #define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ diff --git a/include/ppc440.h b/include/ppc440.h index bc1d7aa..07f75de 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1425,9 +1425,6 @@ /*----------------------------------------------------------------------------+ | Clock / Power-on-reset DCR's. +----------------------------------------------------------------------------*/ -#define CPR0_CFGADDR 0x00C -#define CPR0_CFGDATA 0x00D - #define CPR0_CLKUPD 0x20 #define CPR0_CLKUPD_BSY_MASK 0x80000000 #define CPR0_CLKUPD_BSY_COMPLETED 0x00000000 @@ -3314,6 +3311,23 @@ #define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0) #define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0) +/* + * All 44x except 440GP have CPR registers (indirect DCR) + */ +#if !defined(CONFIG_440GP) +#define CPR0_CFGADDR 0x00C +#define CPR0_CFGDATA 0x00D + +#define mtcpr(reg, data) do { \ + mtdcr(CPR0_CFGADDR, reg); \ + mtdcr(CPR0_CFGDATA, data); \ + } while (0) + +#define mfcpr(reg, data) do { \ + mtdcr(CPR0_CFGADDR, reg); \ + data = mfdcr(CPR0_CFGDATA); \ + } while (0) +#endif #ifndef __ASSEMBLY__ diff --git a/include/status_led.h b/include/status_led.h index db4c60f..71a202f 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -355,6 +355,18 @@ void status_led_set (int led, int state); # define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ # define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ +#elif defined(CONFIG_MOTIONPRO) + +#define STATUS_LED_BIT ((vu_long *) MPC5XXX_GPT6_ENABLE) +#define STATUS_LED_PERIOD (CFG_HZ / 10) +#define STATUS_LED_STATE STATUS_LED_BLINKING + +#define STATUS_LED_BIT1 ((vu_long *) MPC5XXX_GPT7_ENABLE) +#define STATUS_LED_PERIOD1 (CFG_HZ / 10) +#define STATUS_LED_STATE1 STATUS_LED_OFF + +#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + #else # error Status LED configuration missing #endif |