25 files changed, 1551 insertions, 302 deletions
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index be2ce24..c09b07d 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -70,9 +70,6 @@ typedef	struct	global_data {
 #if defined(CONFIG_MPC8315)
 	u32 tdm_clk;
 #endif
-#if defined(CONFIG_MPC837X)
-	u32 sdhc_clk;
-#endif
 	u32 core_clk;
 	u32 enc_clk;
 	u32 lbiu_clk;
@@ -89,6 +86,9 @@ typedef	struct	global_data {
 	u32  mem_sec_clk;
 #endif /* CONFIG_MPC8360 */
 #endif
+#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8536)
+	u32 sdhc_clk;
+#endif
 #if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
 	u32 i2c1_clk;
 	u32 i2c2_clk;
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 113ba48..559d6ea 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1560,6 +1560,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_SGMII2_DIS	0x10000000
 #define MPC85xx_PORDEVSR_SGMII3_DIS	0x08000000
 #define MPC85xx_PORDEVSR_SGMII4_DIS	0x04000000
+#define MPC85xx_PORDEVSR_SRDS2_IO_SEL   0x38000000
 #define MPC85xx_PORDEVSR_IO_SEL		0x00380000
 #define MPC85xx_PORDEVSR_PCI2_ARB	0x00040000
 #define MPC85xx_PORDEVSR_PCI1_ARB	0x00020000
@@ -1653,13 +1654,23 @@ typedef struct ccsr_gur {
 #define CFG_MPC85xx_PCIX_ADDR	(CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET)
 #define CFG_MPC85xx_PCIX2_OFFSET	(0x9000)
 #define CFG_MPC85xx_PCIX2_ADDR	(CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET)
+#define CFG_MPC85xx_SATA1_OFFSET	(0x18000)
+#define CFG_MPC85xx_SATA1_ADDR	(CFG_IMMR + CFG_MPC85xx_SATA1_OFFSET)
+#define CFG_MPC85xx_SATA2_OFFSET	(0x19000)
+#define CFG_MPC85xx_SATA2_ADDR	(CFG_IMMR + CFG_MPC85xx_SATA2_OFFSET)
 #define CFG_MPC85xx_L2_OFFSET	(0x20000)
 #define CFG_MPC85xx_L2_ADDR	(CFG_IMMR + CFG_MPC85xx_L2_OFFSET)
 #define CFG_MPC85xx_DMA_OFFSET	(0x21000)
 #define CFG_MPC85xx_DMA_ADDR	(CFG_IMMR + CFG_MPC85xx_DMA_OFFSET)
+#define CFG_MPC85xx_ESDHC_OFFSET	(0x2e000)
+#define CFG_MPC85xx_ESDHC_ADDR	(CFG_IMMR + CFG_MPC85xx_ESDHC_OFFSET)
 #define CFG_MPC85xx_PIC_OFFSET	(0x40000)
 #define CFG_MPC85xx_PIC_ADDR	(CFG_IMMR + CFG_MPC85xx_PIC_OFFSET)
 #define CFG_MPC85xx_CPM_OFFSET	(0x80000)
 #define CFG_MPC85xx_CPM_ADDR	(CFG_IMMR + CFG_MPC85xx_CPM_OFFSET)
+#define CFG_MPC85xx_SERDES1_OFFSET	(0xE3000)
+#define CFG_MPC85xx_SERDES1_ADDR	(CFG_IMMR + CFG_MPC85xx_SERDES2_OFFSET)
+#define CFG_MPC85xx_SERDES2_OFFSET	(0xE3100)
+#define CFG_MPC85xx_SERDES2_ADDR	(CFG_IMMR + CFG_MPC85xx_SERDES2_OFFSET)
 
 #endif /*__IMMAP_85xx__*/
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 050a7b6..8975e6c 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -431,6 +431,7 @@ extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
 extern void disable_tlb(u8 esel);
 extern void invalidate_tlb(u8 tlb);
 extern void init_tlbs(void);
+extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
 
 #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
 	{ .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index dce4717..e07e5d3 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -926,6 +926,8 @@
 
 #define SVR_8533	0x803400
 #define SVR_8533_E	0x803C00
+#define SVR_8536	0x803700
+#define SVR_8536_E	0x803F00
 #define SVR_8540	0x803000
 #define SVR_8541	0x807200
 #define SVR_8541_E	0x807A00
diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
index 6aa881c..5bc28f1 100644
--- a/include/configs/ATUM8548.h
+++ b/include/configs/ATUM8548.h
@@ -55,18 +55,11 @@
 
 #define CONFIG_TSEC_ENET	1	/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for DDR setup*/
-#undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
-#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
-
 #define CONFIG_SYS_CLK_FREQ	33000000
 
 /*
@@ -104,33 +97,38 @@
 #define CFG_PCI2_ADDR	(CFG_CCSRBAR+0x9000)
 #define CFG_PCIE1_ADDR	(CFG_CCSRBAR+0xa000)
 
-/*
- * DDR Setup
- */
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
 
-#if defined(CONFIG_SPD_EEPROM)
-    /*
-     * Determine DDR configuration from I2C interface.
-     */
-    #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#else
-    /*
-     * Manually set up DDR parameters
-     */
-    #define CFG_SDRAM_SIZE	1024		/* DDR is 1024MB */
-    #define CFG_DDR_CS0_BNDS	0x0000000f	/* 0-1024 */
-    #define CFG_DDR_CS0_CONFIG	0x80000102
-    #define CFG_DDR_TIMING_0	0x00260802
-    #define CFG_DDR_TIMING_1	0x38355322
-    #define CFG_DDR_TIMING_2	0x039048c7
-    #define CFG_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
-    #define CFG_DDR_MODE	0x00000432
-    #define CFG_DDR_INTERVAL	0x05150100
-    #define DDR_SDRAM_CFG	0x43000000
-#endif
+#define CFG_DDR_SDRAM_BASE	0x00000000
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* Manually set up DDR parameters */
+#define CFG_SDRAM_SIZE	1024		/* DDR is 1024MB */
+#define CFG_DDR_CS0_BNDS	0x0000000f	/* 0-1024 */
+#define CFG_DDR_CS0_CONFIG	0x80000102
+#define CFG_DDR_TIMING_0	0x00260802
+#define CFG_DDR_TIMING_1	0x38355322
+#define CFG_DDR_TIMING_2	0x039048c7
+#define CFG_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
+#define CFG_DDR_MODE	0x00000432
+#define CFG_DDR_INTERVAL	0x05150100
+#define DDR_SDRAM_CFG	0x43000000
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
new file mode 100644
index 0000000..17cc934
--- /dev/null
+++ b/include/configs/MPC8536DS.h
@@ -0,0 +1,594 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8536ds board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8536		1
+#define CONFIG_MPC8536DS	1
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCI1		1	/* Enable PCI controller 1 */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash associated with the CDS board.
+ * This allows booting from a promjet.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+extern unsigned long get_board_ddr_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
+/* #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /\* ddrclk for MPC85xx *\/ FIXME-8536*/
+#define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
+#define CONFIG_GET_CLK_FROM_ICS307	  /* decode sysclk and ddrclk freq
+					     from ICS307 instead of switches */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
+
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#define CFG_MEMTEST_START	0x00000000	/* memtest works on */
+#define CFG_MEMTEST_END		0x7fffffff
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+
+#define CFG_PCI1_ADDR		(CFG_CCSRBAR+0x8000)
+#define CFG_PCIE1_ADDR		(CFG_CCSRBAR+0xa000)
+#define CFG_PCIE2_ADDR		(CFG_CCSRBAR+0x9000)
+#define CFG_PCIE3_ADDR		(CFG_CCSRBAR+0xb000)
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#undef CONFIG_DDR_DLL
+
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+#define CFG_SPD_BUS_NUM		1
+
+/* These are used when DDR doesn't use SPD. */
+#define CFG_SDRAM_SIZE		256		/* DDR is 256MB */
+#define CFG_DDR_CS0_BNDS	0x0000001F
+#define CFG_DDR_CS0_CONFIG	0x80010102	/* Enable, no interleaving */
+#define CFG_DDR_TIMING_3	0x00000000
+#define CFG_DDR_TIMING_0	0x00260802
+#define CFG_DDR_TIMING_1	0x3935d322
+#define CFG_DDR_TIMING_2	0x14904cc8
+#define CFG_DDR_MODE_1		0x00480432
+#define CFG_DDR_MODE_2		0x00000000
+#define CFG_DDR_INTERVAL	0x06180100
+#define CFG_DDR_DATA_INIT	0xdeadbeef
+#define CFG_DDR_CLK_CTRL	0x03800000
+#define CFG_DDR_OCD_CTRL	0x00000000
+#define CFG_DDR_OCD_STATUS	0x00000000
+#define CFG_DDR_CONTROL		0xC3008000	/* Type = DDR2 */
+#define CFG_DDR_CONTROL2	0x04400010
+
+#define CFG_DDR_ERR_INT_EN	0x0000000d
+#define CFG_DDR_ERR_DIS		0x00000000
+#define CFG_DDR_SBE		0x00010000
+
+/* FIXME: Not used in fixed_sdram function */
+#define CFG_DDR_MODE		0x00000022
+#define CFG_DDR_CS1_BNDS	0x00000000
+#define CFG_DDR_CS2_BNDS	0x00000FFF	/* Not done */
+#define CFG_DDR_CS3_BNDS	0x00000FFF	/* Not done */
+#define CFG_DDR_CS4_BNDS	0x00000FFF	/* Not done */
+#define CFG_DDR_CS5_BNDS	0x00000FFF	/* Not done */
+
+/* Make sure required options are set */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
+/*
+ * Memory map -- xxx -this is wrong, needs updating
+ *
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
+ * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
+ * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
+ *
+ * Localbus cacheable (TBD)
+ * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
+ *
+ * Localbus non-cacheable
+ * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
+ * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
+ * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CFG_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
+
+#define CFG_BR0_PRELIM		0xe8001001
+#define CFG_OR0_PRELIM		0xf8000ff7
+
+#define CFG_BR1_PRELIM		0xe0001001
+#define CFG_OR1_PRELIM		0xf8000ff7
+
+#define CFG_FLASH_BANKS_LIST	{CFG_FLASH_BASE + 0x8000000, CFG_FLASH_BASE}
+#define CFG_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
+#define CFG_MAX_FLASH_SECT	1024		/* sectors per device */
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_AMD_CHECK_DQ7
+
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+
+#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
+#define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
+
+#define CFG_BR3_PRELIM	(PIXIS_BASE | 0x0801)	/* port size 8bit */
+#define CFG_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
+
+#define PIXIS_ID		0x0	/* Board ID at offset 0 */
+#define PIXIS_VER		0x1	/* Board version at offset 1 */
+#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
+#define PIXIS_CSR   		0x3	/* PIXIS General control/status register */
+#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
+#define PIXIS_PWR		0x5	/* PIXIS Power status register */
+#define PIXIS_AUX		0x6	/* Auxiliary 1 register */
+#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
+#define PIXIS_AUX2		0x8	/* Auxiliary 2 register */
+#define PIXIS_VCTL		0x10	/* VELA Control Register */
+#define PIXIS_VSTAT		0x11	/* VELA Status Register */
+#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
+#define PIXIS_VCORE0	 	0x14	/* VELA VCORE0 Register */
+#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
+#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
+#define PIXIS_VSPEED2		0x19	/* VELA VSpeed 2 */
+#define PIXIS_VSYSCLK0		0x1A	/* VELA SYSCLK0 Register */
+#define PIXIS_VSYSCLK1		0x1B	/* VELA SYSCLK1 Register */
+#define PIXIS_VSYSCLK2		0x1C	/* VELA SYSCLK2 Register */
+#define PIXIS_VDDRCLK0		0x1D	/* VELA DDRCLK0 Register */
+#define PIXIS_VDDRCLK1		0x1E	/* VELA DDRCLK1 Register */
+#define PIXIS_VDDRCLK2		0x1F	/* VELA DDRCLK2 Register */
+#define PIXIS_VWATCH		0x24    /* Watchdog Register */
+#define PIXIS_LED		0x25    /* LED Register */
+
+/* old pixis referenced names */
+#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
+#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+#define CFG_PIXIS_VBOOT_MASK	0xc0
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#define CFG_INIT_RAM_END	0x00004000	/* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE	128	/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+#define CFG_64BIT_STRTOUL		1
+#define CFG_64BIT_VSPRINTF		1
+
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{{0, 0x29}}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
+#define CFG_I2C2_OFFSET		0x3100
+
+/*
+ * I2C2 EEPROM
+ */
+#define CFG_ID_EEPROM
+#ifdef CFG_ID_EEPROM
+#define CONFIG_ID_EEPROM
+#define CFG_I2C_EEPROM_NXID
+#endif
+#define CFG_I2C_EEPROM_ADDR	0x57
+#define CFG_I2C_EEPROM_ADDR_LEN	1
+#define CFG_EEPROM_BUS_NUM	1
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS	0x00000000
+#define CFG_PCI_MEMORY_PHYS	0x00000000
+#define CFG_PCI_MEMORY_SIZE	0x80000000
+
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xffc00000
+#define CFG_PCI1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CFG_PCIE1_MEM_BASE	0x90000000
+#define CFG_PCIE1_MEM_PHYS	CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE	0x08000000	/* 128M */
+#define CFG_PCIE1_IO_BASE	0x00000000
+#define CFG_PCIE1_IO_PHYS	0xffc10000
+#define CFG_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#define CFG_PCIE2_MEM_BASE	0x98000000
+#define CFG_PCIE2_MEM_PHYS	CFG_PCIE2_MEM_BASE
+#define CFG_PCIE2_MEM_SIZE	0x08000000	/* 128M */
+#define CFG_PCIE2_IO_BASE	0x00000000
+#define CFG_PCIE2_IO_PHYS	0xffc20000
+#define CFG_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, direct to uli, tgtid 3, Base address 8000 */
+#define CFG_PCIE3_MEM_BASE	0xa0000000
+#define CFG_PCIE3_MEM_PHYS	CFG_PCIE3_MEM_BASE
+#define CFG_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCIE3_IO_BASE	0x00000000
+#define CFG_PCIE3_IO_PHYS	0xffc30000
+#define CFG_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET		CFG_PCIE3_IO_PHYS
+
+/*PCI video card used*/
+/*#define VIDEO_IO_OFFSET	CFG_PCI1_IO_PHYS*/
+
+/* video */
+#define CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_BIOSEMU
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+/*#define CONFIG_CONSOLE_CURSOR*/
+#define CFG_ISA_IO_BASE_ADDRESS CFG_PCIE3_IO_PHYS
+#endif
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#undef CONFIG_RTL8139
+
+#ifdef CONFIG_RTL8139
+/* This macro is used by RTL8139 but not defined in PPC architecture */
+#define KSEG1ADDR(x)		({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
+#define _IO_BASE	0x00000000
+#endif
+
+#ifndef CONFIG_PCI_PNP
+	#define PCI_ENET0_IOADDR	CFG_PCI1_IO_BASE
+	#define PCI_ENET0_MEMADDR	CFG_PCI1_IO_BASE
+	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CFG_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CFG_SATA1		CFG_MPC85xx_SATA1_ADDR
+#define CFG_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CFG_SATA2		CFG_MPC85xx_SATA2_ADDR
+#define CFG_SATA2_FLAGS		FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI	1
+#endif
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define TSEC1_PHY_ADDR		1	/* TSEC1 -> PHY1 */
+#define TSEC3_PHY_ADDR		0	/* TSEC3 -> PHY0 */
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC3_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#if CFG_MONITOR_BASE > 0xfff80000
+#define CFG_ENV_ADDR		0xfff80000
+#else
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x60000)
+#endif
+#define CFG_ENV_SIZE		0x2000
+#define CFG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_NET
+#endif
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR	00:E0:0C:02:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR	00:E0:0C:02:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR	00:E0:0C:02:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR	00:E0:0C:02:03:FD
+#endif
+
+#define CONFIG_IPADDR		192.168.1.254
+
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		/opt/nfsroot
+#define CONFIG_BOOTFILE		uImage
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
+
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+ "netdev=eth0\0"						\
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
+ "tftpflash=tftpboot $loadaddr $uboot; "			\
+	"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
+	"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
+	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
+	"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
+	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
+ "consoledev=ttyS0\0"				\
+ "ramdiskaddr=2000000\0"			\
+ "ramdiskfile=8536ds/ramdisk.uboot\0"		\
+ "fdtaddr=c00000\0"				\
+ "fdtfile=8536ds/mpc8536ds.dtb\0"		\
+ "bdev=sda3\0"
+
+#define CONFIG_HDBOOT				\
+ "setenv bootargs root=/dev/$bdev rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"			\
+ "tftp $fdtaddr $fdtfile;"			\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND		\
+ "setenv bootargs root=/dev/nfs rw "	\
+ "nfsroot=$serverip:$rootpath "		\
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND		\
+ "setenv bootargs root=/dev/ram rw "	\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $ramdiskaddr $ramdiskfile;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 6351925..74f8605 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -48,13 +48,6 @@
 #define CONFIG_PCI
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
-
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
-
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
 /*
@@ -100,33 +93,33 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#undef CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 
-/*
- * DDR Setup
- */
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 
-#if defined(CONFIG_SPD_EEPROM)
-    /*
-     * Determine DDR configuration from I2C interface.
-     */
-    #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
-
-#else
-    /*
-     * Manually set up DDR parameters
-     */
-    #define CFG_SDRAM_SIZE	128		/* DDR is 128MB */
-    #define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
-    #define CFG_DDR_CS0_CONFIG	0x80000002
-    #define CFG_DDR_TIMING_1	0x37344321
-    #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
-    #define CFG_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
-    #define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
-    #define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
-#endif
-
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD. */
+#define CFG_SDRAM_SIZE	128		/* DDR is 128MB */
+#define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
+#define CFG_DDR_CS0_CONFIG	0x80000002
+#define CFG_DDR_TIMING_1	0x37344321
+#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CFG_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
+#define CFG_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
+#define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
 
 /*
  * SDRAM on the Local Bus
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index b13c81c..1073e23 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -39,9 +39,6 @@
 #undef  CONFIG_PCI			    /* pci ethernet support	*/
 #define CONFIG_TSEC_ENET		    /* tsec ethernet support  */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM                   /* Use SPD EEPROM for DDR setup */
-#undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
-#define CONFIG_DDR_DLL                      /* possible DLL fix needed */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
@@ -86,8 +83,6 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 #define CFG_SDRAM_SIZE		256             /* DDR is now 256MB     */
 
 #if defined(CONFIG_RAM_AS_FLASH)
@@ -121,10 +116,27 @@
 #undef  CFG_RAMBOOT
 #endif
 
-#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_DLL                      /* possible DLL fix needed */
+
+#undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
 
-/* Here some DDR setting should be added */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
 
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index d948d76..29dff32 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -40,12 +40,6 @@
 #define CONFIG_PCI
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
-
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
@@ -59,8 +53,6 @@
  */
 #define CONFIG_ASSUME_AMD_FLASH
 
-#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_clock_freq(void);
 #endif
@@ -85,13 +77,23 @@ extern unsigned long get_clock_freq(void);
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
-/*
- * DDR Setup
- */
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#undef CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 
-#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
 
 /*
  * Make sure required options are set
@@ -102,7 +104,6 @@ extern unsigned long get_clock_freq(void);
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-
 /*
  * Local Bus Definitions
  */
@@ -317,6 +318,9 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
+#define CFG_64BIT_VSPRINTF	1
+#define CFG_64BIT_STRTOUL	1
+
 /*
  * I2C
  */
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 9a77b7b..5738192 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -46,15 +46,6 @@
 
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
-#undef CONFIG_DDR_DLL
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
-
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
-
-#define CONFIG_DDR_ECC_CMD
 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
 
 /*
@@ -64,8 +55,6 @@
  */
 #define CONFIG_ASSUME_AMD_FLASH
 
-#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
@@ -101,17 +90,27 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CFG_PCIE2_ADDR		(CFG_CCSRBAR+0x9000)
 #define CFG_PCIE3_ADDR		(CFG_CCSRBAR+0xb000)
 
-/*
- * DDR Setup
- */
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
 
+/* I2C addresses of SPD EEPROMs */
 #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
 
-/*
- * Make sure required options are set
- */
+/* Make sure required options are set */
 #ifndef CONFIG_SPD_EEPROM
 #error ("CONFIG_SPD_EEPROM is required")
 #endif
@@ -242,6 +241,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
+#define CFG_64BIT_STRTOUL		1
+#define CFG_64BIT_VSPRINTF		1
+
 /* I2C */
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 33c5c93..ec0b4ff 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -46,15 +46,7 @@
 
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
-
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
-
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
 #define CONFIG_FSL_VIA
@@ -67,8 +59,6 @@
  */
 #define CONFIG_ASSUME_AMD_FLASH
 
-#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_clock_freq(void);
 #endif
@@ -103,17 +93,27 @@ extern unsigned long get_clock_freq(void);
 #define CFG_PCI2_ADDR	(CFG_CCSRBAR+0x9000)
 #define CFG_PCIE1_ADDR	(CFG_CCSRBAR+0xa000)
 
-/*
- * DDR Setup
- */
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_DLL			/* possible DLL fix needed */
+
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 
-#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
-/*
- * Make sure required options are set
- */
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* Make sure required options are set */
 #ifndef CONFIG_SPD_EEPROM
 #error ("CONFIG_SPD_EEPROM is required")
 #endif
@@ -342,6 +342,9 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
+#define CFG_64BIT_VSPRINTF	1
+#define CFG_64BIT_STRTOUL	1
+
 /*
  * I2C
  */
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 85c235c..c07a725 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -40,13 +40,6 @@
 #define CONFIG_PCI
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
-
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
-
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
 #define CONFIG_FSL_VIA
@@ -59,8 +52,6 @@
  */
 #define CONFIG_ASSUME_AMD_FLASH
 
-#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_clock_freq(void);
 #endif
@@ -85,24 +76,31 @@ extern unsigned long get_clock_freq(void);
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
-/*
- * DDR Setup
- */
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#undef CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 
-#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
-/*
- * Make sure required options are set
- */
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* Make sure required options are set */
 #ifndef CONFIG_SPD_EEPROM
 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
 #endif
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-
 /*
  * Local Bus Definitions
  */
@@ -317,6 +315,9 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
+#define CFG_64BIT_VSPRINTF	1
+#define CFG_64BIT_STRTOUL	1
+
 /*
  * I2C
  */
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 3567d1ce..a8e7c0a 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -46,13 +46,6 @@
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
-
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
-
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
 /*
@@ -96,33 +89,33 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#undef CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 
-/*
- * DDR Setup
- */
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 
-#if defined(CONFIG_SPD_EEPROM)
-    /*
-     * Determine DDR configuration from I2C interface.
-     */
-    #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
-#else
-    /*
-     * Manually set up DDR parameters
-     */
-    #define CFG_SDRAM_SIZE	128		/* DDR is 128MB */
-    #define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
-    #define CFG_DDR_CS0_CONFIG	0x80000002
-    #define CFG_DDR_TIMING_1	0x37344321
-    #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
-    #define CFG_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
-    #define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
-    #define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
-#endif
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
 
+/* These are used when DDR doesn't use SPD.  */
+#define CFG_SDRAM_SIZE	128		/* DDR is 128MB */
+#define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
+#define CFG_DDR_CS0_CONFIG	0x80000002
+#define CFG_DDR_TIMING_1	0x37344321
+#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CFG_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
+#define CFG_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
+#define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
 
 /*
  * SDRAM on the Local Bus
@@ -293,6 +286,9 @@
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
+#define CFG_64BIT_VSPRINTF	1
+#define CFG_64BIT_STRTOUL	1
+
 /*
  * I2C
  */
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index a82d528..8aeaa29 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -41,14 +41,6 @@
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_QE			/* Enable QE */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_DLL			/* possible DLL fix needed */
-/*#define CONFIG_DDR_2T_TIMING		 Sets the 2T timing bit */
-
-/*#define CONFIG_DDR_ECC*/			/* only for ECC DDR module */
-/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/	/* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
-
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
 /*
@@ -58,8 +50,6 @@
  */
 #define CONFIG_ASSUME_AMD_FLASH
 
-#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_clock_freq(void);
 #endif						  /*Replace a call to get_clock_freq (after it is implemented)*/
@@ -95,24 +85,33 @@ extern unsigned long get_clock_freq(void);
 #define CFG_PCI1_ADDR           (CFG_CCSRBAR+0x8000)
 #define CFG_PCIE1_ADDR          (CFG_CCSRBAR+0xa000)
 
-/*
- * DDR Setup
- */
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_DLL			/* possible DLL fix needed */
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 
-#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
-/*
- * Make sure required options are set
- */
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* Make sure required options are set */
 #ifndef CONFIG_SPD_EEPROM
 #error ("CONFIG_SPD_EEPROM is required")
 #endif
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-
 /*
  * Local Bus Definitions
  */
@@ -302,6 +301,9 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
+#define CFG_64BIT_VSPRINTF	1
+#define CFG_64BIT_STRTOUL	1
+
 /*
  * I2C
  */
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
new file mode 100644
index 0000000..b0094f3
--- /dev/null
+++ b/include/configs/MPC8572DS.h
@@ -0,0 +1,576 @@
+/*
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8572ds board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8572		1
+#define CONFIG_MPC8572DS	1
+#define CONFIG_MP		1	/* support multiple processors */
+#define CONFIG_NUM_CPUS		2	/* Number of CPUs in the system */
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash associated with the CDS board.
+ * This allows booting from a promjet.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+extern unsigned long get_board_ddr_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */
+#define CONFIG_ICS307_REFCLK_HZ	33333333  /* ICS307 clock chip ref freq */
+#define CONFIG_GET_CLK_FROM_ICS307	  /* decode sysclk and ddrclk freq
+					     from ICS307 instead of switches */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
+
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#define CFG_MEMTEST_START	0x00000000	/* memtest works on */
+#define CFG_MEMTEST_END		0x7fffffff
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+
+#define CFG_PCIE3_ADDR		(CFG_CCSRBAR+0x8000)
+#define CFG_PCIE2_ADDR		(CFG_CCSRBAR+0x9000)
+#define CFG_PCIE1_ADDR		(CFG_CCSRBAR+0xa000)
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#undef CONFIG_DDR_DLL
+
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
+#define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 1 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD.  */
+#define CFG_SDRAM_SIZE		256		/* DDR is 256MB */
+#define CFG_DDR_CS0_BNDS	0x0000001F
+#define CFG_DDR_CS0_CONFIG	0x80010102	/* Enable, no interleaving */
+#define CFG_DDR_TIMING_3	0x00000000
+#define CFG_DDR_TIMING_0	0x00260802
+#define CFG_DDR_TIMING_1	0x3935d322
+#define CFG_DDR_TIMING_2	0x14904cc8
+#define CFG_DDR_MODE_1		0x00480432
+#define CFG_DDR_MODE_2		0x00000000
+#define CFG_DDR_INTERVAL	0x06180100
+#define CFG_DDR_DATA_INIT	0xdeadbeef
+#define CFG_DDR_CLK_CTRL	0x03800000
+#define CFG_DDR_OCD_CTRL	0x00000000
+#define CFG_DDR_OCD_STATUS	0x00000000
+#define CFG_DDR_CONTROL		0xC3008000	/* Type = DDR2 */
+#define CFG_DDR_CONTROL2	0x04400010
+
+#define CFG_DDR_ERR_INT_EN	0x0000000d
+#define CFG_DDR_ERR_DIS		0x00000000
+#define CFG_DDR_SBE		0x00010000
+
+/*
+ * FIXME: Not used in fixed_sdram function
+ */
+#define CFG_DDR_MODE		0x00000022
+#define CFG_DDR_CS1_BNDS	0x00000000
+#define CFG_DDR_CS2_BNDS	0x00000FFF	/* Not done */
+#define CFG_DDR_CS3_BNDS	0x00000FFF	/* Not done */
+#define CFG_DDR_CS4_BNDS	0x00000FFF	/* Not done */
+#define CFG_DDR_CS5_BNDS	0x00000FFF	/* Not done */
+
+/*
+ * Make sure required options are set
+ */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
+ * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
+ * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
+ *
+ * Localbus cacheable (TBD)
+ * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
+ *
+ * Localbus non-cacheable
+ * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
+ * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
+ * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CFG_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
+
+#define CFG_BR0_PRELIM		0xe8001001
+#define CFG_OR0_PRELIM		0xf8000ff7
+
+#define CFG_BR1_PRELIM		0xe0001001
+#define CFG_OR1_PRELIM		0xf8000ff7
+
+#define CFG_FLASH_BANKS_LIST	{CFG_FLASH_BASE + 0x8000000, CFG_FLASH_BASE}
+#define CFG_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
+#define CFG_MAX_FLASH_SECT	1024		/* sectors per device */
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_AMD_CHECK_DQ7
+
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+
+#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
+#define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
+
+#define CFG_BR3_PRELIM	(PIXIS_BASE | 0x0801)	/* port size 8bit */
+#define CFG_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
+
+#define PIXIS_ID		0x0	/* Board ID at offset 0 */
+#define PIXIS_VER		0x1	/* Board version at offset 1 */
+#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
+#define PIXIS_CSR   		0x3	/* PIXIS General control/status register */
+#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
+#define PIXIS_PWR		0x5	/* PIXIS Power status register */
+#define PIXIS_AUX		0x6	/* Auxiliary 1 register */
+#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
+#define PIXIS_AUX2		0x8	/* Auxiliary 2 register */
+#define PIXIS_VCTL		0x10	/* VELA Control Register */
+#define PIXIS_VSTAT		0x11	/* VELA Status Register */
+#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
+#define PIXIS_VCORE0	 	0x14	/* VELA VCORE0 Register */
+#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
+#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
+#define PIXIS_VSPEED2		0x19	/* VELA VSpeed 2 */
+#define PIXIS_VSYSCLK0		0x1C	/* VELA SYSCLK0 Register */
+#define PIXIS_VSYSCLK1		0x1D	/* VELA SYSCLK1 Register */
+#define PIXIS_VSYSCLK2		0x1E	/* VELA SYSCLK2 Register */
+#define PIXIS_VDDRCLK0		0x1F	/* VELA DDRCLK0 Register */
+#define PIXIS_VDDRCLK1		0x20	/* VELA DDRCLK1 Register */
+#define PIXIS_VDDRCLK2		0x21	/* VELA DDRCLK2 Register */
+#define PIXIS_VWATCH		0x24    /* Watchdog Register */
+#define PIXIS_LED		0x25    /* LED Register */
+
+/* old pixis referenced names */
+#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
+#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+#define CFG_PIXIS_VBOOT_MASK	0xc0
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#define CFG_INIT_RAM_END	0x00004000	/* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE	128	/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+#define CFG_64BIT_VSPRINTF	1
+#define CFG_64BIT_STRTOUL	1
+
+/* new uImage format support */
+#define CONFIG_FIT		1
+#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_EEPROM_ADDR	0x57
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3100
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS	0x00000000
+#define CFG_PCI_MEMORY_PHYS	0x00000000
+#define CFG_PCI_MEMORY_SIZE	0x80000000
+
+/* controller 3, direct to uli, tgtid 3, Base address 8000 */
+#define CFG_PCIE3_MEM_BASE	0x80000000
+#define CFG_PCIE3_MEM_PHYS	CFG_PCIE3_MEM_BASE
+#define CFG_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCIE3_IO_BASE	0x00000000
+#define CFG_PCIE3_IO_PHYS	0xffc00000
+#define CFG_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#define CFG_PCIE2_MEM_BASE	0xa0000000
+#define CFG_PCIE2_MEM_PHYS	CFG_PCIE2_MEM_BASE
+#define CFG_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCIE2_IO_BASE	0x00000000
+#define CFG_PCIE2_IO_PHYS	0xffc10000
+#define CFG_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CFG_PCIE1_MEM_BASE	0xc0000000
+#define CFG_PCIE1_MEM_PHYS	CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCIE1_IO_BASE	0x00000000
+#define CFG_PCIE1_IO_PHYS	0xffc20000
+#define CFG_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+#if defined(CONFIG_PCI)
+
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET		CFG_PCIE1_IO_PHYS
+
+/* video */
+#define CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_BIOSEMU
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+/*#define CONFIG_CONSOLE_CURSOR*/
+#define CFG_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
+#endif
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#undef CONFIG_RTL8139
+
+#ifdef CONFIG_RTL8139
+/* This macro is used by RTL8139 but not defined in PPC architecture */
+#define KSEG1ADDR(x)		(x)
+#define _IO_BASE	0x00000000
+#endif
+
+#ifndef CONFIG_PCI_PNP
+	#define PCI_ENET0_IOADDR	CFG_PCIE3_IO_BASE
+	#define PCI_ENET0_MEMADDR	CFG_PCIE3_IO_BASE
+	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CFG_SCSI_MAX_SCSI_ID	4
+#define CFG_SCSI_MAX_LUN	1
+#define CFG_SCSI_MAX_DEVICE	(CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAXDEVICE	CFG_SCSI_MAX_DEVICE
+#endif /* SCSI */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI	1
+#endif
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+#define CONFIG_TSEC4	1
+#define CONFIG_TSEC4_NAME	"eTSEC4"
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC3_PHY_ADDR		2
+#define TSEC4_PHY_ADDR		3
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+#define TSEC4_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#if CFG_MONITOR_BASE > 0xfff80000
+#define CFG_ENV_ADDR		0xfff80000
+#else
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x70000)
+#endif
+#define CFG_ENV_SIZE		0x2000
+#define CFG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_EXT2
+#endif
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR	00:E0:0C:02:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR	00:E0:0C:02:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR	00:E0:0C:02:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR	00:E0:0C:02:03:FD
+#endif
+
+#define CONFIG_IPADDR		192.168.1.254
+
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		/opt/nfsroot
+#define CONFIG_BOOTFILE		uImage
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
+
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+ "netdev=eth0\0"						\
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
+ "tftpflash=tftpboot $loadaddr $uboot; "			\
+	"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
+	"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
+	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
+	"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
+	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
+ "consoledev=ttyS0\0"				\
+ "ramdiskaddr=2000000\0"			\
+ "ramdiskfile=8572ds/ramdisk.uboot\0"		\
+ "fdtaddr=c00000\0"				\
+ "fdtfile=8572ds/mpc8572ds.dtb\0"		\
+ "bdev=sda3\0"
+
+#define CONFIG_HDBOOT				\
+ "setenv bootargs root=/dev/$bdev rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"			\
+ "tftp $fdtaddr $fdtfile;"			\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND		\
+ "setenv bootargs root=/dev/nfs rw "	\
+ "nfsroot=$serverip:$rootpath "		\
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND		\
+ "setenv bootargs root=/dev/ram rw "	\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $ramdiskaddr $ramdiskfile;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index f2c11b0..aa6095f 100644
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -44,12 +44,6 @@
 #define CONFIG_PCI
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#undef	CONFIG_SPD_EEPROM		/* do not use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
-
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_MEM_INIT_VALUE		0xDEADBEEF
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
@@ -96,32 +90,36 @@
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 
-/*
- * DDR Setup
- */
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
-
-#if defined(CONFIG_SPD_EEPROM)
-    /*
-     * Determine DDR configuration from I2C interface.
-     */
-    #define SPD_EEPROM_ADDRESS	0x58		/* DDR DIMM */
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#undef CONFIG_DDR_SPD
+#define CONFIG_DDR_DLL                      /* possible DLL fix needed */
+#define CONFIG_DDR_ECC			    /* only for ECC DDR module */
 
-#else
-    /*
-     * Manually set up DDR parameters
-     */
-    #define CFG_SDRAM_SIZE	256		/* DDR is 256 MB */
-    #define CFG_DDR_CS0_BNDS	0x0000000f	/* 0-256MB */
-    #define CFG_DDR_CS0_CONFIG	0x80000102
-    #define CFG_DDR_TIMING_1	0x47444321
-    #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
-    #define CFG_DDR_CONTROL	0xc2008000	/* unbuffered,no DYN_PWR */
-    #define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
-    #define CFG_DDR_INTERVAL	0x045b0100	/* autocharge,no open page */
-#endif
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
+#define CFG_DDR_SDRAM_BASE	0x00000000
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x58	/* CTLR 0 DIMM 0 */
+
+/* Manually set up DDR parameters */
+#define CFG_SDRAM_SIZE	256		/* DDR is 256 MB */
+#define CFG_DDR_CS0_BNDS	0x0000000f	/* 0-256MB */
+#define CFG_DDR_CS0_CONFIG	0x80000102
+#define CFG_DDR_TIMING_1	0x47444321
+#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CFG_DDR_CONTROL	0xc2008000	/* unbuffered,no DYN_PWR */
+#define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
+#define CFG_DDR_INTERVAL	0x045b0100	/* autocharge,no open page */
 
 /*
  * SDRAM on the Local Bus
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index b2cf060..244f09a 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -45,11 +45,6 @@
 #define CONFIG_PCI
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#undef  CONFIG_SPD_EEPROM		/* do not use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
-#define CONFIG_MEM_INIT_VALUE		0xDEADBEEF
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
@@ -97,33 +92,36 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#undef CONFIG_DDR_SPD
+#define CONFIG_DDR_DLL                      /* possible DLL fix needed */
+#define CONFIG_DDR_ECC			    /* only for ECC DDR module */
 
-/*
- * DDR Setup
- */
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
-
-#if defined(CONFIG_SPD_EEPROM)
-    /*
-     * Determine DDR configuration from I2C interface.
-     */
-    #define SPD_EEPROM_ADDRESS	0x58		/* DDR DIMM */
-
-#else
-    /*
-     * Manually set up DDR parameters
-     */
-    #define CFG_SDRAM_SIZE	256		/* DDR is 256 MB */
-    #define CFG_DDR_CS0_BNDS	0x0000000f	/* 0-256MB */
-    #define CFG_DDR_CS0_CONFIG	0x80000102
-    #define CFG_DDR_TIMING_1	0x47444321
-    #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
-    #define CFG_DDR_CONTROL	0xc2008000	/* unbuffered,no DYN_PWR */
-    #define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
-    #define CFG_DDR_INTERVAL	0x045b0100	/* autocharge,no open page */
-#endif
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
+#define CFG_DDR_SDRAM_BASE	0x00000000
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x58	/* CTLR 0 DIMM 0 */
+
+/* Manually set up DDR parameters */
+#define CFG_SDRAM_SIZE	256		/* DDR is 256 MB */
+#define CFG_DDR_CS0_BNDS	0x0000000f	/* 0-256MB */
+#define CFG_DDR_CS0_CONFIG	0x80000102
+#define CFG_DDR_TIMING_1	0x47444321
+#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CFG_DDR_CONTROL	0xc2008000	/* unbuffered,no DYN_PWR */
+#define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
+#define CFG_DDR_INTERVAL	0x045b0100	/* autocharge,no open page */
 
 /*
  * SDRAM on the Local Bus
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index 6033d93..93509ee 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -103,18 +103,34 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 #define CFG_SDRAM_SIZE		512		/* DDR is 512MB */
-#define SPD_EEPROM_ADDRESS	0x55		/*  DDR DIMM */
 
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#undef CONFIG_FSL_DDR_INTERACTIVE
 #undef  CONFIG_DDR_ECC				/* only for ECC DDR module	*/
 #undef  CONFIG_SPD_EEPROM			/* Use SPD EEPROM for DDR setup */
+#undef  CONFIG_DDR_SPD
 
 #if defined(CONFIG_MPC85xx_REV1)
   #define CONFIG_DDR_DLL			/* possible DLL fix needed	*/
 #endif
 
+#undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x55	/* CTLR 0 DIMM 0 */
+
 #undef CONFIG_CLOCKS_IN_MHZ
 
 #if defined(CONFIG_RAM_AS_FLASH)
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index d84554e..5e1cf95 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -137,6 +137,10 @@
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
 #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
 /* TQM8540 & 8560 need DLL-override */
 #define CONFIG_DDR_DLL				/* DLL fix needed	*/
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index b4238e5..9ef0bfd 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -47,19 +47,11 @@
 
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
-#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
-#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
-
 #define CONFIG_SYS_CLK_FREQ	66000000 /* SBC8548 default SYSCLK */
 
 /*
@@ -94,13 +86,26 @@
 #define CFG_PCI2_ADDR	(CFG_CCSRBAR+0x9000)
 #define CFG_PCIE1_ADDR	(CFG_CCSRBAR+0xa000)
 
-/*
- * DDR Setup
- */
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#undef CONFIG_DDR_SPD
+#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
 
-#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
 
 /*
  * Make sure required options are set
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index b244eef..99d328c 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -97,18 +97,34 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 #define CFG_SDRAM_SIZE		512		/* DDR is 512MB */
-#define SPD_EEPROM_ADDRESS	0x55		/*  DDR DIMM */
 
-#undef  CONFIG_DDR_ECC			/* only for ECC DDR module	*/
-#undef  CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#undef  CONFIG_DDR_ECC				/* only for ECC DDR module	*/
+#undef  CONFIG_SPD_EEPROM			/* Use SPD EEPROM for DDR setup */
+#undef  CONFIG_DDR_SPD
 
 #if defined(CONFIG_MPC85xx_REV1)
-  #define CONFIG_DDR_DLL		/* possible DLL fix needed	*/
+  #define CONFIG_DDR_DLL			/* possible DLL fix needed	*/
 #endif
 
+#undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x55	/* CTLR 0 DIMM 0 */
+
 #undef CONFIG_CLOCKS_IN_MHZ
 
 #if defined(CONFIG_RAM_AS_FLASH)
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 8a64942..15abec1 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -93,11 +93,25 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
-/*
- * DDR Setup
- */
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	*/
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
 
 #define CONFIG_DDR_DEFAULT_CL	30		/* CAS latency 3	*/
 
@@ -114,13 +128,6 @@
 #define CFG_DDR_CLK_CONTROL		0x03800000
 #define CFG_SDRAM_SIZE			256 /* in Megs */
 
-#define CONFIG_SPD_EEPROM	1 	/* Use SPD EEPROM for DDR setup*/
-#define SPD_EEPROM_ADDRESS	0x50		/* DDR DIMM */
-#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
-
-/*
- * Flash on the Local Bus
- */
 /*
  * Flash on the LocalBus
  */
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 6e8213d..ea79de7 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -47,10 +47,6 @@
 #define CONFIG_TSEC_ENET		/* tsec ethernet support*/
 #undef  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
-#undef  CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_DDR_DLL                  /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
@@ -118,19 +114,27 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#undef CONFIG_FSL_DDR_INTERACTIVE
 
-/*
- * DDR Setup
- */
+#undef  CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_DDR_DLL                  /* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 
-#define SPD_EEPROM_ADDRESS	0x54		/*  DDR DIMM */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x54	/* CTLR 0 DIMM 0 */
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index 4f1c156..ac349df 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -47,10 +47,6 @@
 #define CONFIG_TSEC_ENET		/* tsec ethernet support*/
 #undef CONFIG_ETHER_ON_FCC		/* cpm FCC ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
-#undef	CONFIG_DDR_ECC			/* only for ECC DDR module */
-#undef CONFIG_DDR_DLL			/* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
@@ -131,19 +127,27 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#undef CONFIG_FSL_DDR_INTERACTIVE
 
-/*
- * DDR Setup
- */
+#undef	CONFIG_DDR_ECC			/* only for ECC DDR module */
+#undef CONFIG_DDR_DLL			/* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 
-#define SPD_EEPROM_ADDRESS	0x54		/*  DDR DIMM */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x54	/* CTLR 0 DIMM 0 */
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
diff --git a/include/pci_ids.h b/include/pci_ids.h
index 165456b..ae642b1 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -2057,6 +2057,8 @@
 #define PCI_DEVICE_ID_MICROGATE_SCA	0x0030
 
 #define PCI_VENDOR_ID_FREESCALE		0x1957
+#define PCI_DEVICE_ID_MPC8536E		0x0050
+#define PCI_DEVICE_ID_MPC8536		0x0051
 #define PCI_DEVICE_ID_MPC8548E		0x0012
 #define PCI_DEVICE_ID_MPC8548		0x0013
 #define PCI_DEVICE_ID_MPC8543E		0x0014