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-rw-r--r--include/arm925t.h11
-rw-r--r--include/common.h2
-rw-r--r--include/configs/am335x_evm.h28
-rw-r--r--include/configs/apf27.h388
-rw-r--r--include/configs/dra7xx_evm.h8
-rw-r--r--include/configs/mx35pdk.h1
-rw-r--r--include/configs/mx6sabresd.h4
-rw-r--r--include/configs/mx6slevk.h14
-rw-r--r--include/configs/omap1510inn.h166
-rw-r--r--include/configs/pcm051.h1
-rw-r--r--include/configs/sansa_fuze_plus.h70
-rw-r--r--include/configs/socfpga_cyclone5.h1
-rw-r--r--include/configs/vexpress_ca15_tc2.h5
-rw-r--r--include/configs/wandboard.h4
-rw-r--r--include/configs/xfi3.h69
-rw-r--r--include/power/tps65217.h83
-rw-r--r--include/power/tps65910.h77
17 files changed, 738 insertions, 194 deletions
diff --git a/include/arm925t.h b/include/arm925t.h
deleted file mode 100644
index 3d767b3..0000000
--- a/include/arm925t.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/************************************************
- * NAME : arm925t.h
- * Version : 23 June 2003 *
- ************************************************/
-
-#ifndef __ARM925T_H__
-#define __ARM925T_H__
-
-void archflashwp(void *archdata, int wp);
-
-#endif /*__ARM925T_H__*/
diff --git a/include/common.h b/include/common.h
index 8addf43..4d2a56d 100644
--- a/include/common.h
+++ b/include/common.h
@@ -627,6 +627,8 @@ void ft_pci_setup(void *blob, bd_t *bd);
#endif
#endif
+void smp_set_core_boot_addr(unsigned long addr, int corenr);
+void smp_kick_all_cpus(void);
/* $(CPU)/serial.c */
int serial_init (void);
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 3de30fc..2f06ca2 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -46,7 +46,7 @@
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \
- "bootm ${loadaddr}\0" \
+ "bootz ${loadaddr}\0" \
"nandimgsize=0x500000\0"
#else
#define NANDARGS ""
@@ -61,8 +61,9 @@
"fdt_high=0xffffffff\0" \
"boot_fdt=try\0" \
"rdaddr=0x81000000\0" \
+ "bootpart=0:2\0" \
"bootdir=/boot\0" \
- "bootfile=uImage\0" \
+ "bootfile=zImage\0" \
"fdtfile=undefined\0" \
"console=ttyO0,115200n8\0" \
"optargs=\0" \
@@ -71,7 +72,6 @@
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 ro\0" \
"mmcrootfstype=ext4 rootwait\0" \
- "bootpart=0:2\0" \
"rootpath=/export/rootfs\0" \
"nfsopts=nolock\0" \
"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
@@ -105,21 +105,21 @@
"root=${ramroot} " \
"rootfstype=${ramrootfstype}\0" \
"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
- "loaduimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+ "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
"mmcloados=run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
- "bootm ${loadaddr} - ${fdtaddr}; " \
+ "bootz ${loadaddr} - ${fdtaddr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
- "bootm; " \
+ "bootz; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
- "bootm; " \
+ "bootz; " \
"fi;\0" \
"mmcboot=mmc dev ${mmcdev}; " \
"if mmc rescan; then " \
@@ -132,7 +132,7 @@
"echo Running uenvcmd ...;" \
"run uenvcmd;" \
"fi;" \
- "if run loaduimage; then " \
+ "if run loadimage; then " \
"run mmcloados;" \
"fi;" \
"fi;\0" \
@@ -140,17 +140,17 @@
"run spiargs; " \
"sf probe ${spibusno}:0; " \
"sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \
- "bootm ${loadaddr}\0" \
+ "bootz ${loadaddr}\0" \
"netboot=echo Booting from network ...; " \
"setenv autoload no; " \
"dhcp; " \
"tftp ${loadaddr} ${bootfile}; " \
"tftp ${fdtaddr} ${fdtfile}; " \
"run netargs; " \
- "bootm ${loadaddr} - ${fdtaddr}\0" \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
"ramboot=echo Booting from ramdisk ...; " \
"run ramargs; " \
- "bootm ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
+ "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
"findfdt="\
"if test $board_name = A335BONE; then " \
"setenv fdtfile am335x-bone.dtb; fi; " \
@@ -170,6 +170,7 @@
"run mmcboot;" \
"setenv mmcdev 1; " \
"setenv bootpart 1:2; " \
+ "setenv mmcroot /dev/mmcblk1p2 ro; " \
"run mmcboot;" \
"run nandboot;"
@@ -189,8 +190,13 @@
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_MULTI_EEPROMS
+/* PMIC support */
+#define CONFIG_POWER_TPS65217
+#define CONFIG_POWER_TPS65910
+
/* SPL */
#ifndef CONFIG_NOR_BOOT
+#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_YMODEM_SUPPORT
/* CPSW support */
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
new file mode 100644
index 0000000..e7e258f
--- /dev/null
+++ b/include/configs/apf27.h
@@ -0,0 +1,388 @@
+/*
+ *
+ * Configuration settings for the Armadeus Project motherboard APF27
+ *
+ * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_ENV_VERSION 10
+#define CONFIG_IDENT_STRING " apf27 patch 3.10"
+#define CONFIG_BOARD_NAME apf27
+
+/*
+ * SoC configurations
+ */
+#define CONFIG_ARM926EJS /* this is an ARM926EJS CPU */
+#define CONFIG_MX27 /* in a Freescale i.MX27 Chip */
+#define CONFIG_MACH_TYPE 1698 /* APF27 */
+#define CONFIG_SYS_GENERIC_BOARD
+
+/*
+ * Enable the call to miscellaneous platform dependent initialization.
+ */
+#define CONFIG_SYS_NO_FLASH /* to be define before <config_cmd_default.h> */
+
+/*
+ * Board display option
+ */
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_CPUINFO
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_MAX_SIZE 2048
+#define CONFIG_SPL_TEXT_BASE 0xA0000000
+
+/* NAND boot config */
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+
+#define CONFIG_HOSTNAME CONFIG_BOARD_NAME
+#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV /* ask for env variable */
+#define CONFIG_CMD_BSP /* Board Specific functions */
+#define CONFIG_CMD_CACHE /* icache, dcache */
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP /* DHCP Support */
+#define CONFIG_CMD_DNS
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_IMX_FUSE /* imx iim fuse */
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII /* MII support */
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_MTDPARTS /* MTD partition support */
+#define CONFIG_CMD_NAND /* NAND support */
+#define CONFIG_CMD_NAND_LOCK_UNLOCK
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_PING /* ping support */
+#define CONFIG_CMD_SETEXPR /* setexpr support */
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_POPULATED 1
+#define CONFIG_NR_DRAM_BANKS 2
+
+#define ACFG_SDRAM_MBYTE_SYZE 64
+
+#define PHYS_SDRAM_1 0xA0000000
+#define PHYS_SDRAM_2 0xB0000000
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10))
+#define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */
+#define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
+ + PHYS_SDRAM_1_SIZE - 0x0100000)
+
+#define CONFIG_SYS_TEXT_BASE 0xA0000800
+
+/*
+ * FLASH organization
+ */
+#define ACFG_MONITOR_OFFSET 0x00000000
+#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */
+#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
+#define CONFIG_ENV_RANGE 0X00080000 /* 512kB */
+#define CONFIG_ENV_OFFSET_REDUND \
+ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */
+#define CONFIG_FIRMWARE_OFFSET 0x00200000
+#define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */
+#define CONFIG_KERNEL_OFFSET 0x00300000
+#define CONFIG_ROOTFS_OFFSET 0x00800000
+
+#define CONFIG_MTDMAP "mxc_nand.0"
+#define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP
+#define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \
+ ":1M(u-boot)ro," \
+ "512K(env)," \
+ "512K(env2)," \
+ "512K(firmware)," \
+ "512K(dtb)," \
+ "5M(kernel)," \
+ "-(rootfs)"
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "BIOS> " /* prompt string */
+#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+ /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 16 /* max command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER /* enable the "hush" shell */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* secondary prompt string */
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_PREBOOT "run check_flash check_env;"
+
+
+/*
+ * Boot Linux
+ */
+#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
+#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
+#define CONFIG_INITRD_TAG /* send initrd params */
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin"
+#define CONFIG_BOOTARGS "console=" __stringify(ACFG_CONSOLE_DEV) "," \
+ __stringify(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \
+ " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs "
+
+#define ACFG_CONSOLE_DEV ttySMX0
+#define CONFIG_BOOTCOMMAND "run ubifsboot"
+#define CONFIG_SYS_AUTOLOAD "no"
+/*
+ * Default load address for user programs and kernel
+ */
+#define CONFIG_LOADADDR 0xA0000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/*
+ * Extra Environments
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \
+ "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "partition=nand0,6\0" \
+ "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \
+ "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \
+ "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \
+ "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \
+ "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \
+ "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \
+ "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \
+ "kernel_addr_r=A0000000\0" \
+ "check_env=if test -n ${flash_env_version}; " \
+ "then env default env_version; " \
+ "else env set flash_env_version ${env_version}; env save; "\
+ "fi; " \
+ "if itest ${flash_env_version} < ${env_version}; then " \
+ "echo \"*** Warning - Environment version" \
+ " change suggests: run flash_reset_env; reset\"; "\
+ "env default flash_reset_env; "\
+ "fi; \0" \
+ "check_flash=nand lock; nand unlock ${env_addr}; \0" \
+ "flash_reset_env=env default -f -a; saveenv; run update_env;" \
+ "echo Flash environment variables erased!\0" \
+ "download_uboot=tftpboot ${loadaddr} ${board_name}" \
+ "-u-boot-with-spl.bin\0" \
+ "flash_uboot=nand unlock ${u-boot_addr} ;" \
+ "nand erase.part u-boot;" \
+ "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
+ "then nand lock; nand unlock ${env_addr};" \
+ "echo Flashing of uboot succeed;" \
+ "else echo Flashing of uboot failed;" \
+ "fi; \0" \
+ "update_uboot=run download_uboot flash_uboot\0" \
+ "download_env=tftpboot ${loadaddr} ${board_name}" \
+ "-u-boot-env.txt\0" \
+ "flash_env=env import -t ${loadaddr}; env save; \0" \
+ "update_env=run download_env flash_env\0" \
+ "update_all=run update_env update_uboot\0" \
+ "unlock_regs=mw 10000008 0; mw 10020008 0\0" \
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/*
+ * GPIO
+ */
+#define CONFIG_MXC_GPIO
+
+/*
+ * NOR
+ */
+
+/*
+ * NAND
+ */
+#define CONFIG_NAND_MXC
+
+#define CONFIG_MXC_NAND_REGS_BASE 0xD8000000
+#define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE
+#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 11
+#define NAND_MAX_CHIPS 1
+
+#define CONFIG_FLASH_SHOW_PROGRESS 45
+#define CONFIG_SYS_NAND_QUIET 1
+
+/*
+ * Partitions & Filsystems
+ */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+
+/*
+ * UBIFS
+ */
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+
+/*
+ * Ethernet (on SOC imx FEC)
+ */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR 0x1f
+#define CONFIG_MII /* MII PHY management */
+
+/*
+ * FPGA
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_FPGA
+#endif
+#define CONFIG_FPGA_COUNT 1
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_SPARTAN3
+#define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_CHECK_CTRLC
+#define CONFIG_SYS_FPGA_CHECK_ERROR
+
+/*
+ * Fuses - IIM
+ */
+#ifdef CONFIG_CMD_IMX_FUSE
+#define IIM_MAC_BANK 0
+#define IIM_MAC_ROW 5
+#define IIM0_SCC_KEY 11
+#define IIM1_SUID 1
+#endif
+
+/*
+ * I2C
+ */
+
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE IMX_I2C1_BASE
+#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_NOPROBES { }
+
+#ifdef CONFIG_CMD_EEPROM
+# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */
+#endif /* CONFIG_CMD_EEPROM */
+#endif /* CONFIG_CMD_I2C */
+
+/*
+ * SD/MMC
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXC_MMC
+#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
+#endif
+
+/*
+ * RTC
+ */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_DS1374
+#define CONFIG_SYS_RTC_BUS_NUM 0
+#endif /* CONFIG_CMD_DATE */
+
+/*
+ * Clocks
+ */
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+
+/*
+ * PLL
+ *
+ * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
+ * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
+ */
+#define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */
+
+#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
+/* micron 64MB */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
+#endif
+
+#if (ACFG_SDRAM_MBYTE_SYZE == 128)
+/* micron 128MB */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
+#endif
+
+#if (ACFG_SDRAM_MBYTE_SYZE == 256)
+/* micron 256MB */
+#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
+#define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 4fbe768..7b120de 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -14,7 +14,13 @@
#define CONFIG_DRA7XX
-#define CONFIG_ENV_IS_NOWHERE /* For now. */
+/* MMC ENV related defines */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
+#define CONFIG_ENV_OFFSET 0xE0000
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_CMD_SAVEENV
#define CONSOLEDEV "ttyO0"
#define CONFIG_CONS_INDEX 1
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index 68b225a..a25b20e 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -23,7 +23,6 @@
/* Set TEXT at the beginning of the NOR flash */
#define CONFIG_SYS_TEXT_BASE 0xA0000000
-#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index a3dd74a..3229bc7 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -16,7 +16,11 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_CONSOLE_DEV "ttymxc0"
#define CONFIG_MMCROOT "/dev/mmcblk1p2"
+#if defined(CONFIG_MX6Q)
#define CONFIG_DEFAULT_FDT_FILE "imx6q-sabresd.dtb"
+#elif defined(CONFIG_MX6DL)
+#define CONFIG_DEFAULT_FDT_FILE "imx6dl-sabresd.dtb"
+#endif
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#include "mx6sabre_common.h"
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index ca8f2f6..792f17c 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -44,6 +44,20 @@
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 0
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
diff --git a/include/configs/omap1510inn.h b/include/configs/omap1510inn.h
deleted file mode 100644
index 1a7e5c7..0000000
--- a/include/configs/omap1510inn.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments.
- * Kshitij Gupta <kshitij@ti.com>
- * Configuation settings for the TI OMAP Innovator board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM925T 1 /* This is an arm925t CPU */
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP1510 1 /* which is in a 1510 (helen) */
-#define CONFIG_INNOVATOROMAP1510 1 /* a Innovator Board */
-
-/* input clock of PLL */
-#define CONFIG_SYS_CLK_FREQ 12000000 /* the OMAP1510 Innovator has 12MHz input clock */
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-/*
-#define CONFIG_DRIVER_SMC9196
-#define CONFIG_SMC9196_BASE 0x08000300
-#define CONFIG_SMC9196_EXT_PHY
-*/
-#define CONFIG_LAN91C96
-#define CONFIG_LAN91C96_BASE 0x08000300
-#define CONFIG_LAN91C96_EXT_PHY
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK (CONFIG_SYS_CLK_FREQ) /* can be 12M/32Khz or 48Mhz */
-#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1510 Innovator */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-
-
-#include <configs/omap1510.h>
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=bootp"
-#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
-#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-/* what's this ? it's not used anywhere */
-#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "OMAP1510 Innovator # " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
-
-/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
- * This time is further subdivided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE /* use timer 1 */
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-#define PHYS_SRAM 0x20000000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
-#define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */
-#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SECT_SIZE)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
-#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE }
-
-/*-----------------------------------------------------------------------
- * FLASH driver setup
- */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index e2b4de7..2fff0be 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -201,6 +201,7 @@
/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
/*
* Place the image at the start of the ROM defined image space.
* We limit our size to the ROM-defined downloaded image area, and use the
diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h
new file mode 100644
index 0000000..a85eb1c
--- /dev/null
+++ b/include/configs/sansa_fuze_plus.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIGS_SANSA_FUZE_PLUS_H__
+#define __CONFIGS_SANSA_FUZE_PLUS_H__
+
+/* System configurations */
+#define CONFIG_MX23 /* i.MX23 SoC */
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_VIDEO
+#define CONFIG_CMD_MEMTEST
+
+/* Memory configuration */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x40000000 /* Base address */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_SIZE (16 * 1024)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_OVERWRITE
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 "
+#define CONFIG_LOADADDR 0x42000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* LCD */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_FONT_4X6
+#define CONFIG_VIDEO_MXS_MODE_SYSTEM
+#define CONFIG_SYS_BLACK_IN_WRITE
+#define LCD_BPP LCD_COLOR16
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_MXS_PORT0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */
+#define CONFIG_USB_GADGET_DUALSPEED
+
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_CDC
+#define CONFIG_NETCONSOLE
+#endif
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_SANSA_FUZE_PLUS_H__ */
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 06aeba6..346ca72 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -7,6 +7,7 @@
#define __CONFIG_H
#include <asm/arch/socfpga_base_addrs.h>
+#include "../../board/altera/socfpga/pinmux_config.h"
/*
* High level configuration
diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h
index d1431e5..0806034 100644
--- a/include/configs/vexpress_ca15_tc2.h
+++ b/include/configs/vexpress_ca15_tc2.h
@@ -15,6 +15,9 @@
#include "vexpress_common.h"
#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.vexpress_ca15x2_tc2"
-#define CONFIG_SYS_CLK_FREQ 24000000
+#define CONFIG_SYSFLAGS_ADDR 0x1c010030
+#define CONFIG_SMP_PEN_ADDR CONFIG_SYSFLAGS_ADDR
+
+#define CONFIG_ARMV7_VIRT
#endif
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 665cfc3..442a984 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -99,12 +99,10 @@
#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
-#if defined(CONFIG_MX6DL)
+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#define CONFIG_DEFAULT_FDT_FILE "imx6dl-wandboard.dtb"
#elif defined(CONFIG_MX6Q)
#define CONFIG_DEFAULT_FDT_FILE "imx6q-wandboard.dtb"
-#elif defined(CONFIG_MX6S)
-#define CONFIG_DEFAULT_FDT_FILE "imx6s-wandboard.dtb"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h
new file mode 100644
index 0000000..022bc95
--- /dev/null
+++ b/include/configs/xfi3.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIGS_XFI3_H__
+#define __CONFIGS_XFI3_H__
+
+/* System configurations */
+#define CONFIG_MX23 /* i.MX23 SoC */
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_VIDEO
+
+/* Memory configuration */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x40000000 /* Base address */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_SIZE (16 * 1024)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_OVERWRITE
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 "
+#define CONFIG_LOADADDR 0x42000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* LCD */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_FONT_4X6
+#define CONFIG_VIDEO_MXS_MODE_SYSTEM
+#define CONFIG_SYS_BLACK_IN_WRITE
+#define LCD_BPP LCD_COLOR16
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_MXS_PORT0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */
+#define CONFIG_USB_GADGET_DUALSPEED
+
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_CDC
+#define CONFIG_NETCONSOLE
+#endif
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_XFI3_H__ */
diff --git a/include/power/tps65217.h b/include/power/tps65217.h
new file mode 100644
index 0000000..297c4cb
--- /dev/null
+++ b/include/power/tps65217.h
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * For more details, please see the TRM at http://www.ti.com/product/tps65217a
+ */
+
+#ifndef __POWER_TPS65217_H__
+#define __POWER_TPS65217_H__
+
+/* I2C chip address */
+#define TPS65217_CHIP_PM 0x24
+
+/* Registers */
+enum {
+ TPS65217_CHIPID = 0x00,
+ TPS65217_POWER_PATH,
+ TPS65217_INTERRUPT,
+ TPS65217_CHGCONFIG0,
+ TPS65217_CHGCONFIG1,
+ TPS65217_CHGCONFIG2,
+ TPS65217_CHGCONFIG3,
+ TPS65217_WLEDCTRL1,
+ TPS65217_WLEDCTRL2,
+ TPS65217_MUXCTRL,
+ TPS65217_STATUS,
+ TPS65217_PASSWORD,
+ TPS65217_PGOOD,
+ TPS65217_DEFPG,
+ TPS65217_DEFDCDC1,
+ TPS65217_DEFDCDC2,
+ TPS65217_DEFDCDC3,
+ TPS65217_DEFSLEW,
+ TPS65217_DEFLDO1,
+ TPS65217_DEFLDO2,
+ TPS65217_DEFLS1,
+ TPS65217_DEFLS2,
+ TPS65217_ENABLE,
+ TPS65217_DEFUVLO,
+ TPS65217_SEQ1,
+ TPS65217_SEQ2,
+ TPS65217_SEQ3,
+ TPS65217_SEQ4,
+ TPS65217_SEQ5,
+ TPS65217_SEQ6,
+ TPS65217_PMIC_NUM_OF_REGS,
+};
+
+#define TPS65217_PROT_LEVEL_NONE 0x00
+#define TPS65217_PROT_LEVEL_1 0x01
+#define TPS65217_PROT_LEVEL_2 0x02
+
+#define TPS65217_PASSWORD_LOCK_FOR_WRITE 0x00
+#define TPS65217_PASSWORD_UNLOCK 0x7D
+
+#define TPS65217_DCDC_GO 0x80
+
+#define TPS65217_MASK_ALL_BITS 0xFF
+
+#define TPS65217_USB_INPUT_CUR_LIMIT_MASK 0x03
+#define TPS65217_USB_INPUT_CUR_LIMIT_100MA 0x00
+#define TPS65217_USB_INPUT_CUR_LIMIT_500MA 0x01
+#define TPS65217_USB_INPUT_CUR_LIMIT_1300MA 0x02
+#define TPS65217_USB_INPUT_CUR_LIMIT_1800MA 0x03
+
+#define TPS65217_DCDC_VOLT_SEL_1125MV 0x09
+#define TPS65217_DCDC_VOLT_SEL_1275MV 0x0F
+#define TPS65217_DCDC_VOLT_SEL_1325MV 0x11
+
+#define TPS65217_LDO_MASK 0x1F
+#define TPS65217_LDO_VOLTAGE_OUT_1_8 0x06
+#define TPS65217_LDO_VOLTAGE_OUT_3_3 0x1F
+
+#define TPS65217_PWR_SRC_USB_BITMASK 0x4
+#define TPS65217_PWR_SRC_AC_BITMASK 0x8
+
+int tps65217_reg_read(uchar src_reg, uchar *src_val);
+int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
+ uchar mask);
+int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel);
+#endif /* __POWER_TPS65217_H__ */
diff --git a/include/power/tps65910.h b/include/power/tps65910.h
new file mode 100644
index 0000000..ca84301
--- /dev/null
+++ b/include/power/tps65910.h
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * For more details, please see the TRM at http://www.ti.com/product/tps65910
+ */
+#ifndef __POWER_TPS65910_H__
+#define __POWER_TPS65910_H__
+
+#define MPU 0
+#define CORE 1
+
+#define TPS65910_SR_I2C_ADDR 0x12
+#define TPS65910_CTRL_I2C_ADDR 0x2D
+
+/* PMIC Register offsets */
+enum {
+ TPS65910_VDD1_REG = 0x21,
+ TPS65910_VDD1_OP_REG = 0x22,
+ TPS65910_VDD2_REG = 0x24,
+ TPS65910_VDD2_OP_REG = 0x25,
+ TPS65910_DEVCTRL_REG = 0x3F,
+};
+
+/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */
+#define TPS65910_VGAIN_SEL_MASK (0x3 << 6)
+#define TPS65910_ILMAX_MASK (0x1 << 5)
+#define TPS65910_TSTEP_MASK (0x7 << 2)
+#define TPS65910_ST_MASK (0x3)
+
+#define TPS65910_REG_VGAIN_SEL_X1 (0x0 << 6)
+#define TPS65910_REG_VGAIN_SEL_X1_0 (0x1 << 6)
+#define TPS65910_REG_VGAIN_SEL_X3 (0x2 << 6)
+#define TPS65910_REG_VGAIN_SEL_X4 (0x3 << 6)
+
+#define TPS65910_REG_ILMAX_1_0_A (0x0 << 5)
+#define TPS65910_REG_ILMAX_1_5_A (0x1 << 5)
+
+#define TPS65910_REG_TSTEP_ (0x0 << 2)
+#define TPS65910_REG_TSTEP_12_5 (0x1 << 2)
+#define TPS65910_REG_TSTEP_9_4 (0x2 << 2)
+#define TPS65910_REG_TSTEP_7_5 (0x3 << 2)
+#define TPS65910_REG_TSTEP_6_25 (0x4 << 2)
+#define TPS65910_REG_TSTEP_4_7 (0x5 << 2)
+#define TPS65910_REG_TSTEP_3_12 (0x6 << 2)
+#define TPS65910_REG_TSTEP_2_5 (0x7 << 2)
+
+#define TPS65910_REG_ST_OFF (0x0)
+#define TPS65910_REG_ST_ON_HI_POW (0x1)
+#define TPS65910_REG_ST_OFF_1 (0x2)
+#define TPS65910_REG_ST_ON_LOW_POW (0x3)
+
+
+/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
+#define TPS65910_OP_REG_SEL (0x7F)
+
+#define TPS65910_OP_REG_CMD_MASK (0x1 << 7)
+#define TPS65910_OP_REG_CMD_OP (0x0 << 7)
+#define TPS65910_OP_REG_CMD_SR (0x1 << 7)
+
+#define TPS65910_OP_REG_SEL_MASK (0x7F)
+#define TPS65910_OP_REG_SEL_0_9_5 (0x1F) /* 0.9500 V */
+#define TPS65910_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */
+#define TPS65910_OP_REG_SEL_1_2_0 (0x33) /* 1.2000 V */
+#define TPS65910_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */
+#define TPS65910_OP_REG_SEL_1_3_2_5 (0x3D) /* 1.3250 V */
+
+/* Device control register . (DEVCTRL_REG) */
+#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4)
+#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4)
+#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4)
+
+int tps65910_set_i2c_control(void);
+int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel);
+#endif /* __POWER_TPS65910_H__ */