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-rw-r--r--include/asm-arm/arch-mx50/mx50.h1
-rw-r--r--include/configs/mx50_arm2.h10
-rw-r--r--include/configs/mx50_arm2_ddr2.h10
-rw-r--r--include/configs/mx50_arm2_lpddr2.h10
-rw-r--r--include/configs/mx50_rd3.h10
-rw-r--r--include/configs/mx50_rdp.h10
-rw-r--r--include/configs/mx50_rdp_android.h10
-rw-r--r--include/fsl_esdhc.h4
8 files changed, 58 insertions, 7 deletions
diff --git a/include/asm-arm/arch-mx50/mx50.h b/include/asm-arm/arch-mx50/mx50.h
index 9c905e5..c004951 100644
--- a/include/asm-arm/arch-mx50/mx50.h
+++ b/include/asm-arm/arch-mx50/mx50.h
@@ -44,6 +44,7 @@
#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
#define ABPHDMA_BASE_ADDR (DEBUG_BASE_ADDR + 0x01000000)
#define OCOTP_CTRL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01002000)
+#define DIGCTL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01004000)
#define GPMI_BASE_ADDR (DEBUG_BASE_ADDR + 0x01006000)
#define BCH_BASE_ADDR (DEBUG_BASE_ADDR + 0x01008000)
#define EPDC_BASE_ADDR (DEBUG_BASE_ADDR + 0x01010000)
diff --git a/include/configs/mx50_arm2.h b/include/configs/mx50_arm2.h
index d6a56e0..d0266cc 100644
--- a/include/configs/mx50_arm2.h
+++ b/include/configs/mx50_arm2.h
@@ -251,7 +251,15 @@
#define CONFIG_EMMC_DDR_MODE
/* Indicate to esdhc driver which ports support 8-bit data */
- #define CONFIG_MMC_8BIT_PORTS 0x6 /* ports 1 and 2 */
+ #define CONFIG_MMC_8BIT_PORTS 0x6 /* SD2 and SD3 */
+
+ /* Uncomment the following define to enable uSDHC instead
+ * of eSDHC on SD3 port for SDR mode since eSDHC timing on MX50
+ * is borderline for SDR mode. DDR mode will be disabled when this
+ * define is enabled since the uSDHC timing on MX50 is borderline
+ * for DDR mode. */
+
+ /*#define CONFIG_MX50_ENABLE_USDHC_SDR 1*/
#endif
/*
diff --git a/include/configs/mx50_arm2_ddr2.h b/include/configs/mx50_arm2_ddr2.h
index e2eac01..c5e8bce 100644
--- a/include/configs/mx50_arm2_ddr2.h
+++ b/include/configs/mx50_arm2_ddr2.h
@@ -242,7 +242,15 @@
#define CONFIG_EMMC_DDR_MODE
/* Indicate to esdhc driver which ports support 8-bit data */
- #define CONFIG_MMC_8BIT_PORTS 0x6 /* ports 1 & 2 */
+ #define CONFIG_MMC_8BIT_PORTS 0x6 /* SD2 and SD3 */
+
+ /* Uncomment the following define to enable uSDHC instead
+ * of eSDHC on SD3 port for SDR mode since eSDHC timing on MX50
+ * is borderline for SDR mode. DDR mode will be disabled when this
+ * define is enabled since the uSDHC timing on MX50 is borderline
+ * for DDR mode. */
+
+ /*#define CONFIG_MX50_ENABLE_USDHC_SDR 1*/
#endif
diff --git a/include/configs/mx50_arm2_lpddr2.h b/include/configs/mx50_arm2_lpddr2.h
index d7e3aea..d1751df 100644
--- a/include/configs/mx50_arm2_lpddr2.h
+++ b/include/configs/mx50_arm2_lpddr2.h
@@ -243,7 +243,15 @@
#define CONFIG_EMMC_DDR_MODE
/* Indicate to esdhc driver which ports support 8-bit data */
- #define CONFIG_MMC_8BIT_PORTS 0x6 /* ports 1 and 2 */
+ #define CONFIG_MMC_8BIT_PORTS 0x6 /* SD2 and SD3 */
+
+ /* Uncomment the following define to enable uSDHC instead
+ * of eSDHC on SD3 port for SDR mode since eSDHC timing on MX50
+ * is borderline for SDR mode. DDR mode will be disabled when this
+ * define is enabled since the uSDHC timing on MX50 is borderline
+ * for DDR mode. */
+
+ /*#define CONFIG_MX50_ENABLE_USDHC_SDR 1*/
#endif
/*
diff --git a/include/configs/mx50_rd3.h b/include/configs/mx50_rd3.h
index 98d299d..58229a1 100644
--- a/include/configs/mx50_rd3.h
+++ b/include/configs/mx50_rd3.h
@@ -220,7 +220,15 @@
#define CONFIG_EMMC_DDR_MODE
/* Indicate to esdhc driver which ports support 8-bit data */
- #define CONFIG_MMC_8BIT_PORTS 0x6 /* ports 1 and 2 */
+ #define CONFIG_MMC_8BIT_PORTS 0x6 /* SD2 and SD3 */
+
+ /* Uncomment the following define to enable uSDHC instead
+ * of eSDHC on SD3 port for SDR mode since eSDHC timing on MX50
+ * is borderline for SDR mode. DDR mode will be disabled when this
+ * define is enabled since the uSDHC timing on MX50 is borderline
+ * for DDR mode. */
+
+ /*#define CONFIG_MX50_ENABLE_USDHC_SDR 1*/
#endif
/*
diff --git a/include/configs/mx50_rdp.h b/include/configs/mx50_rdp.h
index 8fb1189..fff16a9 100644
--- a/include/configs/mx50_rdp.h
+++ b/include/configs/mx50_rdp.h
@@ -220,7 +220,15 @@
#define CONFIG_EMMC_DDR_MODE
/* Indicate to esdhc driver which ports support 8-bit data */
- #define CONFIG_MMC_8BIT_PORTS 0x6 /* ports 1 and 2 */
+ #define CONFIG_MMC_8BIT_PORTS 0x6 /* SD2 and SD3 */
+
+ /* Uncomment the following define to enable uSDHC instead
+ * of eSDHC on SD3 port for SDR mode since eSDHC timing on MX50
+ * is borderline for SDR mode. DDR mode will be disabled when this
+ * define is enabled since the uSDHC timing on MX50 is borderline
+ * for DDR mode. */
+
+ /*#define CONFIG_MX50_ENABLE_USDHC_SDR 1*/
#endif
/*
diff --git a/include/configs/mx50_rdp_android.h b/include/configs/mx50_rdp_android.h
index 0b6eb8d..f3675dd 100644
--- a/include/configs/mx50_rdp_android.h
+++ b/include/configs/mx50_rdp_android.h
@@ -220,7 +220,15 @@
#define CONFIG_EMMC_DDR_MODE
/* Indicate to esdhc driver which ports support 8-bit data */
- #define CONFIG_MMC_8BIT_PORTS 0x2 /* ports 1 and 2 */
+ #define CONFIG_MMC_8BIT_PORTS 0x6 /* SD2 and SD3 */
+
+ /* Uncomment the following define to enable uSDHC instead
+ * of eSDHC on SD3 port for SDR mode since eSDHC timing on MX50
+ * is borderline for SDR mode. DDR mode will be disabled when this
+ * define is enabled since the uSDHC timing on MX50 is borderline
+ * for DDR mode. */
+
+ /*#define CONFIG_MX50_ENABLE_USDHC_SDR 1*/
#endif
/*
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index e32d7d2..1787407 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -2,7 +2,7 @@
* FSL SD/MMC Defines
*-------------------------------------------------------------------
*
- * Copyright (C) 2007-2008, 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2007-2008, 2010-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -34,6 +34,8 @@
#define SYSCTL_TIMEOUT_MASK 0x000f0000
#define SYSCTL_CLOCK_MASK 0x0000fff0
#define SYSCTL_RSTA 0x01000000
+#define SYSCTL_RSTC 0x02000000
+#define SYSCTL_RSTD 0x04000000
#define SYSCTL_SDCLKEN 0x00000008
#define SYSCTL_PEREN 0x00000004
#define SYSCTL_HCKEN 0x00000002
generated by cgit v1.1 at 2024-12-25 00:47:19 +0000