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-rw-r--r--include/asm-ppc/immap_83xx.h4
-rw-r--r--include/configs/MPC8315ERDB.h2
-rw-r--r--include/configs/MPC8349EMDS.h26
-rw-r--r--include/configs/MVBLM7.h56
-rw-r--r--include/mpc83xx.h7
5 files changed, 65 insertions, 30 deletions
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 5b21539..ff18303 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -61,7 +61,9 @@ typedef struct sysconf83xx {
u32 spcr; /* System Priority Configuration Register */
u32 sicrl; /* System I/O Configuration Register Low */
u32 sicrh; /* System I/O Configuration Register High */
- u8 res6[0x0C];
+ u8 res6[0x04];
+ u32 sidcr0; /* System I/O Delay Configuration Register 0 */
+ u32 sidcr1; /* System I/O Delay Configuration Register 1 */
u32 ddrcdr; /* DDR Control Driver Register */
u32 ddrdsr; /* DDR Debug Status Register */
u32 obir; /* Output Buffer Impedance Register */
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index b0cc36d..006b93a 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -321,6 +321,8 @@
#define CONFIG_NET_MULTI 1
#endif
+#define CONFIG_HAS_FSL_DR_USB
+
/*
* TSEC
*/
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index a53f5cd..c8870b5 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -48,6 +48,11 @@
#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
#endif
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_PCI
+#define CONFIG_83XX_PCICLK 66666666 /* in Hz */
+#endif /* CONFIG_PCISLAVE */
+
#ifndef CONFIG_SYS_CLK_FREQ
#ifdef PCI_66M
#define CONFIG_SYS_CLK_FREQ 66000000
@@ -406,6 +411,8 @@
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_83XX_GENERIC_PCI
+#define CONFIG_83XX_PCI_STREAMING
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -417,7 +424,7 @@
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#endif /* CONFIG_PCI */
@@ -573,6 +580,20 @@
HRCWL_CORE_TO_CSB_1X1)
#endif
+#ifdef CONFIG_PCISLAVE
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_AGENT |\
+ HRCWH_64_BIT_PCI |\
+ HRCWH_PCI1_ARBITER_DISABLE |\
+ HRCWH_PCI2_ARBITER_DISABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_TSEC1M_IN_GMII |\
+ HRCWH_TSEC2M_IN_GMII )
+#else
#if defined(PCI_64BIT)
#define CFG_HRCW_HIGH (\
HRCWH_PCI_HOST |\
@@ -599,7 +620,8 @@
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
HRCWH_TSEC2M_IN_GMII )
-#endif
+#endif /* PCI_64BIT */
+#endif /* CONFIG_PCISLAVE */
/*
* System performance
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index 0dce9b4..849350f 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -406,22 +406,22 @@
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_RESET_TO_RETRY 1000
-#define MV_CI "mvBL-M7"
-#define MV_VCI "mvBL-M7"
-#define MV_FPGA_DATA "0xfff80000"
-#define MV_FPGA_SIZE "0x76ca2"
-#define MV_KERNEL_ADDR "0xff810000"
-#define MV_INITRD_ADDR "0xffc00000"
-#define MV_AUTOSCR_ADDR "0xff804000"
-#define MV_AUTOSCR_ADDR2 "0xff806000"
-#define MV_DTB_ADDR "0xff808000"
-#define MV_INITRD_LENGTH "0x00300000"
+#define MV_CI mvBL-M7
+#define MV_VCI mvBL-M7
+#define MV_FPGA_DATA 0xfff80000
+#define MV_FPGA_SIZE 0x00076ca2
+#define MV_KERNEL_ADDR 0xff810000
+#define MV_INITRD_ADDR 0xffb00000
+#define MV_AUTOSCR_ADDR 0xff804000
+#define MV_AUTOSCR_ADDR2 0xff806000
+#define MV_DTB_ADDR 0xff808000
+#define MV_INITRD_LENGTH 0x00400000
#define CONFIG_SHOW_BOOT_PROGRESS 1
-#define MV_KERNEL_ADDR_RAM "0x00100000"
-#define MV_DTB_ADDR_RAM "0x00600000"
-#define MV_INITRD_ADDR_RAM "0x01000000"
+#define MV_KERNEL_ADDR_RAM 0x00100000
+#define MV_DTB_ADDR_RAM 0x00600000
+#define MV_INITRD_ADDR_RAM 0x01000000
#define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \
then autoscr ${autoscr_addr}; \
@@ -431,25 +431,26 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"console_nr=0\0" \
+ "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0" \
"fpga=0\0" \
- "fpgadata=" MV_FPGA_DATA "\0" \
- "fpgadatasize=" MV_FPGA_SIZE "\0" \
- "autoscr_addr=" MV_AUTOSCR_ADDR "\0" \
- "autoscr_addr2=" MV_AUTOSCR_ADDR2 "\0" \
- "mv_kernel_addr=" MV_KERNEL_ADDR "\0" \
- "mv_kernel_addr_ram=" MV_KERNEL_ADDR_RAM "\0" \
- "mv_initrd_addr=" MV_INITRD_ADDR "\0" \
- "mv_initrd_addr_ram=" MV_INITRD_ADDR_RAM "\0" \
- "mv_initrd_length=" MV_INITRD_LENGTH "\0" \
- "mv_dtb_addr=" MV_DTB_ADDR "\0" \
- "mv_dtb_addr_ram=" MV_DTB_ADDR_RAM "\0" \
- "dtb_name=" MV_DTB_NAME "\0" \
+ "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
+ "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
+ "autoscr_addr=" MK_STR(MV_AUTOSCR_ADDR) "\0" \
+ "autoscr_addr2=" MK_STR(MV_AUTOSCR_ADDR2) "\0" \
+ "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
+ "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
+ "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
+ "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
+ "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
+ "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
+ "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
+ "dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
"mv_version=" U_BOOT_VERSION "\0" \
- "dhcp_client_id=" MV_CI "\0" \
- "dhcp_vendor-class-identifier=" MV_VCI "\0" \
+ "dhcp_client_id=" MK_STR(MV_CI) "\0" \
+ "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
"netretry=no\0" \
"use_static_ipaddr=no\0" \
"static_ipaddr=192.168.90.10\0" \
@@ -470,6 +471,7 @@
"gevss_debug=0\0" \
"watchdog=0\0" \
"usb_dr_mode=host\0" \
+ "sensor_cnt=2\0" \
""
#define CONFIG_FPGA_COUNT 1
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 70a4de7..5d82bb4 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -350,7 +350,9 @@
/* ATR - Arbiter Timers Register
*/
#define ATR_DTO 0x00FF0000 /* Data time out */
+#define ATR_DTO_SHIFT 16
#define ATR_ATO 0x000000FF /* Address time out */
+#define ATR_ATO_SHIFT 0
/* AER - Arbiter Event Register
*/
@@ -364,10 +366,15 @@
/* AEATR - Arbiter Event Address Register
*/
#define AEATR_EVENT 0x07000000 /* Event type */
+#define AEATR_EVENT_SHIFT 24
#define AEATR_MSTR_ID 0x001F0000 /* Master Id */
+#define AEATR_MSTR_ID_SHIFT 16
#define AEATR_TBST 0x00000800 /* Transfer burst */
+#define AEATR_TBST_SHIFT 11
#define AEATR_TSIZE 0x00000700 /* Transfer Size */
+#define AEATR_TSIZE_SHIFT 8
#define AEATR_TTYPE 0x0000001F /* Transfer Type */
+#define AEATR_TTYPE_SHIFT 0
/* HRCWL - Hard Reset Configuration Word Low
*/
generated by cgit v1.1 at 2024-12-03 22:44:26 +0000