diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/crownbay.h | 2 | ||||
| -rw-r--r-- | include/configs/galileo.h | 3 | ||||
| -rw-r--r-- | include/configs/minnowmax.h | 6 | ||||
| -rw-r--r-- | include/configs/qemu-x86.h | 77 | ||||
| -rw-r--r-- | include/configs/x86-chromebook.h | 1 | ||||
| -rw-r--r-- | include/configs/x86-common.h | 7 | ||||
| -rw-r--r-- | include/dt-bindings/gpio/x86-gpio.h | 31 | ||||
| -rw-r--r-- | include/dt-bindings/interrupt-router/intel-irq.h | 31 | ||||
| -rw-r--r-- | include/fdtdec.h | 2 | ||||
| -rw-r--r-- | include/pci_ids.h | 1 |
10 files changed, 147 insertions, 14 deletions
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index 4fef433..0e1f046 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -17,8 +17,6 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_MISC_INIT -#define CONFIG_NR_DRAM_BANKS 1 - #define CONFIG_X86_SERIAL #define CONFIG_SMSC_LPC47M diff --git a/include/configs/galileo.h b/include/configs/galileo.h index f780b8f..fd89bf3 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -15,8 +15,7 @@ #define CONFIG_SYS_MONITOR_LEN (1 << 20) #define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ARCH_MISC_INIT #define CONFIG_X86_SERIAL diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 2a1915d..547765d 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -15,8 +15,7 @@ #define CONFIG_SYS_MONITOR_LEN (1 << 20) #define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_X86_SERIAL #define CONFIG_SMSC_LPC47M @@ -56,9 +55,6 @@ #define CONFIG_X86_OPTION_ROM_FILE vga.bin #define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 -#ifndef CONFIG_SYS_COREBOOT -#define CONFIG_VIDEO_VESA -#endif #define VIDEO_IO_OFFSET 0 #define CONFIG_X86EMU_RAW_IO #define CONFIG_VGA_AS_SINGLE_DEVICE diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h new file mode 100644 index 0000000..78c296f --- /dev/null +++ b/include/configs/qemu-x86.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_ARCH_MISC_INIT + +#define CONFIG_X86_SERIAL + +#define CONFIG_PCI_MEM_BUS 0xc0000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_PREF_BUS 0xd0000000 +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS +#define CONFIG_PCI_PREF_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x2000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0xe000 + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_PCI_PNP +#define CONFIG_E1000 + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" + +/* + * ATA/SATA support for QEMU x86 targets + * - Only legacy IDE controller is supported for QEMU '-M pc' target + * - AHCI controller is supported for QEMU '-M q35' target + * + * Default configuraion is to support the QEMU default x86 target + * Undefine CONFIG_CMD_IDE to support q35 target + */ +#define CONFIG_CMD_IDE +#ifdef CONFIG_CMD_IDE +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE 4 +#define CONFIG_SYS_ATA_BASE_ADDR 0 +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_REG_OFFSET 0 +#define CONFIG_SYS_ATA_ALT_OFFSET 0 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 +#define CONFIG_ATAPI + +#undef CONFIG_SCSI_AHCI +#undef CONFIG_CMD_SCSI +#else +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_AHCI} +#endif + +/* GPIO is not supported */ +#undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_CMD_GPIO + +/* SPI is not supported */ +#undef CONFIG_ICH_SPI +#undef CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_IS_NOWHERE + +#endif /* __CONFIG_H */ diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index b6a76fe..e0e7fca 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -14,7 +14,6 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MISC_INIT_R -#define CONFIG_NR_DRAM_BANKS 8 #define CONFIG_X86_MRC_ADDR 0xfffa0000 #define CONFIG_CACHE_MRC_SIZE_KB 512 diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index bf4758e..1917d87 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -21,6 +21,7 @@ #define CONFIG_DISPLAY_BOARDINFO_LATE #define CONFIG_DISPLAY_CPUINFO #define CONFIG_LAST_STAGE_INIT +#define CONFIG_NR_DRAM_BANKS 8 #define CONFIG_LMB #define CONFIG_OF_LIBFDT @@ -36,6 +37,7 @@ #define CONFIG_SCSI_AHCI #ifdef CONFIG_SCSI_AHCI #define CONFIG_LIBATA +#define CONFIG_LBA48 #define CONFIG_SYS_64BIT_LBA #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 @@ -75,10 +77,6 @@ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SUPPORT_VFAT -/************************************************************ - * ATAPI support (experimental) - ************************************************************/ -#define CONFIG_ATAPI /************************************************************ * DISK Partition support @@ -246,6 +244,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_STD_DEVICES_SETTINGS \ + "pciconfighost=1\0" \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ "othbootargs=acpi=off\0" \ diff --git a/include/dt-bindings/gpio/x86-gpio.h b/include/dt-bindings/gpio/x86-gpio.h new file mode 100644 index 0000000..7f1de30 --- /dev/null +++ b/include/dt-bindings/gpio/x86-gpio.h @@ -0,0 +1,31 @@ +/* + * This header provides constants for binding intel,x86-pinctrl. + */ + +#ifndef _DT_BINDINGS_GPIO_X86_GPIO_H +#define _DT_BINDINGS_GPIO_X86_GPIO_H + +#include <dt-bindings/gpio/gpio.h> + +#define GPIO_MODE_NATIVE 0 +#define GPIO_MODE_GPIO 1 + +#define GPIO_MODE_FUNC0 0 +#define GPIO_MODE_FUNC1 1 +#define GPIO_MODE_FUNC2 2 +#define GPIO_MODE_FUNC3 3 +#define GPIO_MODE_FUNC4 4 +#define GPIO_MODE_FUNC5 5 +#define GPIO_MODE_FUNC6 6 + +#define PIN_INPUT 0 +#define PIN_OUTPUT 1 + +#define PIN_INPUT_NOPULL 0 +#define PIN_INPUT_PULLUP 1 +#define PIN_INPUT_PULLDOWN 2 + +#define PULL_STR_2K 0 +#define PULL_STR_20K 2 + +#endif diff --git a/include/dt-bindings/interrupt-router/intel-irq.h b/include/dt-bindings/interrupt-router/intel-irq.h new file mode 100644 index 0000000..5092f33 --- /dev/null +++ b/include/dt-bindings/interrupt-router/intel-irq.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_INTEL_IRQ_H_ +#define _DT_BINDINGS_INTEL_IRQ_H_ + +/* PCI interrupt pin */ +#define INTA 1 +#define INTB 2 +#define INTC 3 +#define INTD 4 + +/* PIRQs */ +#define PIRQA 0 +#define PIRQB 1 +#define PIRQC 2 +#define PIRQD 3 +#define PIRQE 4 +#define PIRQF 5 +#define PIRQG 6 +#define PIRQH 7 + +/* PCI bdf encoding */ +#ifndef PCI_BDF +#define PCI_BDF(b, d, f) ((b) << 16 | (d) << 11 | (f) << 8) +#endif + +#endif /* _DT_BINDINGS_INTEL_IRQ_H_ */ diff --git a/include/fdtdec.h b/include/fdtdec.h index 6bf5f61..4fb8a2a 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -176,8 +176,10 @@ enum fdt_compat_id { COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */ COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */ COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ + COMPAT_INTEL_X86_PINCTRL, /* Intel ICH7/9 pin control */ COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */ COMPAT_INTEL_PCH, /* Intel PCH */ + COMPAT_INTEL_IRQ_ROUTER, /* Intel Interrupt Router */ COMPAT_COUNT, }; diff --git a/include/pci_ids.h b/include/pci_ids.h index 2e66851..5771e12 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2838,6 +2838,7 @@ #define PCI_DEVICE_ID_INTEL_ICH9_6 0x2930 #define PCI_DEVICE_ID_INTEL_ICH9_7 0x2916 #define PCI_DEVICE_ID_INTEL_ICH9_8 0x2918 +#define PCI_DEVICE_ID_INTEL_ICH9_AHCI 0x2922 #define PCI_DEVICE_ID_INTEL_I7_MCR 0x2c18 #define PCI_DEVICE_ID_INTEL_I7_MC_TAD 0x2c19 #define PCI_DEVICE_ID_INTEL_I7_MC_RAS 0x2c1a |