diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/ethsw.h | 6 | ||||
| -rw-r--r-- | include/fsl_mdio.h | 7 | ||||
| -rw-r--r-- | include/net.h | 2 | ||||
| -rw-r--r-- | include/phy.h | 25 | ||||
| -rw-r--r-- | include/tsec.h | 69 | ||||
| -rw-r--r-- | include/vsc9953.h | 24 |
6 files changed, 93 insertions, 40 deletions
diff --git a/include/ethsw.h b/include/ethsw.h index 2d3c12a..25f358d 100644 --- a/include/ethsw.h +++ b/include/ethsw.h @@ -12,6 +12,7 @@ #define ETHSW_MAX_CMD_PARAMS 20 #define ETHSW_CMD_PORT_ALL -1 #define ETHSW_CMD_VLAN_ALL -1 +#define ETHSW_CMD_AGGR_GRP_NONE -1 /* IDs used to track keywords in a command */ enum ethsw_keyword_id { @@ -41,6 +42,7 @@ enum ethsw_keyword_id { ethsw_id_private, ethsw_id_ingress, ethsw_id_filtering, + ethsw_id_aggr, ethsw_id_count, /* keep last */ }; @@ -50,6 +52,7 @@ enum ethsw_keyword_opt_id { ethsw_id_pvid_no, ethsw_id_add_del_no, ethsw_id_add_del_mac, + ethsw_id_aggr_no, ethsw_id_count_all, /* keep last */ }; @@ -58,6 +61,7 @@ struct ethsw_command_def { int cmd_keywords_nr; int port; int vid; + int aggr_grp; uchar ethaddr[6]; int (*cmd_function)(struct ethsw_command_def *parsed_cmd); }; @@ -88,6 +92,8 @@ struct ethsw_command_func { int (*vlan_learn_set)(struct ethsw_command_def *parsed_cmd); int (*port_ingr_filt_show)(struct ethsw_command_def *parsed_cmd); int (*port_ingr_filt_set)(struct ethsw_command_def *parsed_cmd); + int (*port_aggr_show)(struct ethsw_command_def *parsed_cmd); + int (*port_aggr_set)(struct ethsw_command_def *parsed_cmd); }; int ethsw_define_functions(const struct ethsw_command_func *cmd_func); diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h index 2137282..25678a9 100644 --- a/include/fsl_mdio.h +++ b/include/fsl_mdio.h @@ -5,6 +5,7 @@ * * SPDX-License-Identifier: GPL-2.0+ */ + #ifndef __FSL_PHY_H__ #define __FSL_PHY_H__ @@ -27,9 +28,9 @@ int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc); #define PHY_EXT_PAGE_ACCESS 0x1f /* MII Management Configuration Register */ -#define MIIMCFG_RESET_MGMT 0x80000000 -#define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007 -#define MIIMCFG_INIT_VALUE 0x00000003 +#define MIIMCFG_RESET_MGMT 0x80000000 +#define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007 +#define MIIMCFG_INIT_VALUE 0x00000003 /* MII Management Command Register */ #define MIIMCOM_READ_CYCLE 0x00000001 diff --git a/include/net.h b/include/net.h index ac44d61..a739f45 100644 --- a/include/net.h +++ b/include/net.h @@ -86,11 +86,13 @@ enum eth_state_t { * @iobase: The base address of the hardware registers * @enetaddr: The Ethernet MAC address that is loaded from EEPROM or env * @phy_interface: PHY interface to use - see PHY_INTERFACE_MODE_... + * @max_speed: Maximum speed of Ethernet connection supported by MAC */ struct eth_pdata { phys_addr_t iobase; unsigned char enetaddr[6]; int phy_interface; + int max_speed; }; enum eth_recv_flags { diff --git a/include/phy.h b/include/phy.h index 66cf61b..09bbe48 100644 --- a/include/phy.h +++ b/include/phy.h @@ -17,18 +17,28 @@ #define PHY_MAX_ADDR 32 -#define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \ - SUPPORTED_10baseT_Full | \ - SUPPORTED_100baseT_Half | \ - SUPPORTED_100baseT_Full | \ - SUPPORTED_Autoneg | \ +#define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */ + +#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \ SUPPORTED_TP | \ SUPPORTED_MII) -#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ - SUPPORTED_1000baseT_Half | \ +#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \ + SUPPORTED_10baseT_Full) + +#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \ + SUPPORTED_100baseT_Full) + +#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \ SUPPORTED_1000baseT_Full) +#define PHY_BASIC_FEATURES (PHY_10BT_FEATURES | \ + PHY_100BT_FEATURES | \ + PHY_DEFAULT_FEATURES) + +#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ + PHY_1000BT_FEATURES) + #define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \ SUPPORTED_10000baseT_Full) @@ -226,6 +236,7 @@ int phy_startup(struct phy_device *phydev); int phy_config(struct phy_device *phydev); int phy_shutdown(struct phy_device *phydev); int phy_register(struct phy_driver *drv); +int phy_set_supported(struct phy_device *phydev, u32 max_speed); int genphy_config_aneg(struct phy_device *phydev); int genphy_restart_aneg(struct phy_device *phydev); int genphy_update_link(struct phy_device *phydev); diff --git a/include/tsec.h b/include/tsec.h index 1119d2c..fb27edf 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -3,15 +3,12 @@ * * Driver for the Motorola Triple Speed Ethernet Controller * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * maintained by Xianghua Xiao (x.xiao@motorola.com) * author Andy Fleming * + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __TSEC_H @@ -21,6 +18,8 @@ #include <config.h> #include <phy.h> +#ifndef CONFIG_DM_ETH + #ifdef CONFIG_LS102XA #define TSEC_SIZE 0x40000 #define TSEC_MDIO_OFFSET 0x40000 @@ -67,11 +66,13 @@ x.mii_devname = DEFAULT_MII_NAME;\ } -#define MAC_ADDR_LEN 6 +#endif /* CONFIG_DM_ETH */ + +#define MAC_ADDR_LEN 6 /* #define TSEC_TIMEOUT 1000000 */ -#define TSEC_TIMEOUT 1000 -#define TOUT_LOOP 1000000 +#define TSEC_TIMEOUT 1000 +#define TOUT_LOOP 1000000 /* TBI register addresses */ #define TBI_CR 0x00 @@ -83,8 +84,8 @@ /* TBI MDIO register bit fields*/ #define TBICON_CLK_SELECT 0x0020 -#define TBIANA_ASYMMETRIC_PAUSE 0x0100 -#define TBIANA_SYMMETRIC_PAUSE 0x0080 +#define TBIANA_ASYMMETRIC_PAUSE 0x0100 +#define TBIANA_SYMMETRIC_PAUSE 0x0080 #define TBIANA_HALF_DUPLEX 0x0040 #define TBIANA_FULL_DUPLEX 0x0020 #define TBICR_PHY_RESET 0x8000 @@ -93,13 +94,12 @@ #define TBICR_FULL_DUPLEX 0x0100 #define TBICR_SPEED1_SET 0x0040 - /* MAC register bits */ #define MACCFG1_SOFT_RESET 0x80000000 #define MACCFG1_RESET_RX_MC 0x00080000 #define MACCFG1_RESET_TX_MC 0x00040000 #define MACCFG1_RESET_RX_FUN 0x00020000 -#define MACCFG1_RESET_TX_FUN 0x00010000 +#define MACCFG1_RESET_TX_FUN 0x00010000 #define MACCFG1_LOOPBACK 0x00000100 #define MACCFG1_RX_FLOW 0x00000020 #define MACCFG1_TX_FLOW 0x00000010 @@ -122,7 +122,7 @@ #define ECNTRL_SGMII_MODE 0x00000002 #ifndef CONFIG_SYS_TBIPA_VALUE - #define CONFIG_SYS_TBIPA_VALUE 0x1f +# define CONFIG_SYS_TBIPA_VALUE 0x1f #endif #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN @@ -137,7 +137,6 @@ #define TSTAT_CLEAR_THALT 0x80000000 #define RSTAT_CLEAR_RHALT 0x00800000 - #define IEVENT_INIT_CLEAR 0xffffffff #define IEVENT_BABR 0x80000000 #define IEVENT_RXC 0x40000000 @@ -164,11 +163,9 @@ #define IMASK_TXFEN 0x00100000 #define IMASK_RXFEN0 0x00000080 - /* Default Attribute fields */ -#define ATTR_INIT_SETTINGS 0x000000c0 -#define ATTRELI_INIT_SETTINGS 0x00000000 - +#define ATTR_INIT_SETTINGS 0x000000c0 +#define ATTRELI_INIT_SETTINGS 0x00000000 /* TxBD status field bits */ #define TXBD_READY 0x8000 @@ -181,7 +178,7 @@ #define TXBD_HUGEFRAME 0x0080 #define TXBD_LATECOLLISION 0x0080 #define TXBD_RETRYLIMIT 0x0040 -#define TXBD_RETRYCOUNTMASK 0x003c +#define TXBD_RETRYCOUNTMASK 0x003c #define TXBD_UNDERRUN 0x0002 #define TXBD_STATS 0x03ff @@ -204,15 +201,15 @@ #define RXBD_STATS 0x003f struct txbd8 { - uint16_t status; /* Status Fields */ - uint16_t length; /* Buffer length */ - uint32_t bufptr; /* Buffer Pointer */ + uint16_t status; /* Status Fields */ + uint16_t length; /* Buffer length */ + uint32_t bufptr; /* Buffer Pointer */ }; struct rxbd8 { - uint16_t status; /* Status Fields */ - uint16_t length; /* Buffer Length */ - uint32_t bufptr; /* Buffer Pointer */ + uint16_t status; /* Status Fields */ + uint16_t length; /* Buffer Length */ + uint32_t bufptr; /* Buffer Pointer */ }; struct tsec_rmon_mib { @@ -336,15 +333,15 @@ struct tsec { u32 rbdlen; /* RxBD Data Length */ u32 res310[4]; u32 res320; - u32 crbptr; /* Current Receive Buffer Pointer */ + u32 crbptr; /* Current Receive Buffer Pointer */ u32 res328[6]; - u32 mrblr; /* Maximum Receive Buffer Length */ + u32 mrblr; /* Maximum Receive Buffer Length */ u32 res344[16]; - u32 rbptr; /* RxBD Pointer */ + u32 rbptr; /* RxBD Pointer */ u32 res388[30]; /* (0x2_n400) */ u32 res400; - u32 rbase; /* RxBD Base Address */ + u32 rbase; /* RxBD Base Address */ u32 res408[62]; /* MAC Registers (0x2_n500) */ @@ -388,21 +385,33 @@ struct tsec { u32 resc00[256]; }; -#define TSEC_GIGABIT (1 << 0) +#define TSEC_GIGABIT (1 << 0) /* These flags currently only have meaning if we're using the eTSEC */ #define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */ #define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */ +#define TX_BUF_CNT 2 + struct tsec_private { + struct txbd8 __iomem txbd[TX_BUF_CNT]; + struct rxbd8 __iomem rxbd[PKTBUFSRX]; struct tsec __iomem *regs; struct tsec_mii_mng __iomem *phyregs_sgmii; struct phy_device *phydev; phy_interface_t interface; struct mii_dev *bus; uint phyaddr; + uint tbiaddr; char mii_devname[16]; u32 flags; + uint rx_idx; /* index of the current RX buffer */ + uint tx_idx; /* index of the current TX buffer */ +#ifndef CONFIG_DM_ETH + struct eth_device *dev; +#else + struct udevice *dev; +#endif }; struct tsec_info_struct { @@ -415,7 +424,9 @@ struct tsec_info_struct { u32 flags; }; +#ifndef CONFIG_DM_ETH int tsec_standard_init(bd_t *bis); int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num); +#endif #endif /* __TSEC_H */ diff --git a/include/vsc9953.h b/include/vsc9953.h index cd5cfc7..a2d4554 100644 --- a/include/vsc9953.h +++ b/include/vsc9953.h @@ -126,6 +126,7 @@ #define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100 #define VSC9953_PORT_CFG_LEARN_CPU 0x00000200 #define VSC9953_PORT_CFG_LEARN_DROP 0x00000400 +#define VSC9953_PORT_CFG_PORTID_MASK 0x0000003c /* Macros for vsc9953_qsys_sys.switch_port_mode register */ #define VSC9953_PORT_ENA 0x00002000 @@ -136,6 +137,9 @@ /* Macros for vsc9953_ana_ana.adv_learn register */ #define VSC9953_VLAN_CHK 0x00000400 +/* Macros for vsc9953_ana_ana.auto_age register */ +#define VSC9953_AUTOAGE_PERIOD_MASK 0x001ffffe + /* Macros for vsc9953_rew_port.port_tag_cfg register */ #define VSC9953_TAG_CFG_MASK 0x00000180 #define VSC9953_TAG_CFG_NONE 0x00000000 @@ -153,6 +157,19 @@ /* Macros for vsc9953_ana_ana_tables.mach_data register */ #define VSC9953_MACHDATA_VID_MASK 0x1fff0000 +/* Macros for vsc9953_ana_common.aggr_cfg register */ +#define VSC9953_AC_RND_ENA 0x00000080 +#define VSC9953_AC_DMAC_ENA 0x00000040 +#define VSC9953_AC_SMAC_ENA 0x00000020 +#define VSC9953_AC_IP6_LBL_ENA 0x00000010 +#define VSC9953_AC_IP6_TCPUDP_ENA 0x00000008 +#define VSC9953_AC_IP4_SIPDIP_ENA 0x00000004 +#define VSC9953_AC_IP4_TCPUDP_ENA 0x00000002 +#define VSC9953_AC_MASK 0x000000fe + +/* Macros for vsc9953_ana_pgid.port_grp_id[] registers */ +#define VSC9953_PGID_PORT_MASK 0x000003ff + #define VSC9953_MAX_PORTS 10 #define VSC9953_PORT_CHECK(port) \ (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) @@ -164,6 +181,7 @@ #define VSC9953_MAX_VLAN 4096 #define VSC9953_VLAN_CHECK(vid) \ (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1) +#define VSC9953_DEFAULT_AGE_TIME 300 #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0" @@ -235,6 +253,10 @@ struct vsc9953_ana_ana { u32 port_mode[12]; }; +#define PGID_DST_START 0 +#define PGID_AGGR_START 64 +#define PGID_SRC_START 80 + struct vsc9953_ana_pgid { u32 port_grp_id[91]; }; @@ -269,7 +291,7 @@ struct vsc9953_analyzer { struct vsc9953_ana_ana_tables ana_tables; u32 reserved2[14]; struct vsc9953_ana_ana ana; - u32 reserved3[22]; + u32 reserved3[21]; struct vsc9953_ana_pgid port_id_tbl; u32 reserved4[549]; struct vsc9953_ana_pfc pfc[10]; |