diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/chromebook_jerry.h | 16 | ||||
| -rw-r--r-- | include/configs/firefly-rk3288.h | 14 | ||||
| -rw-r--r-- | include/configs/rk3288_common.h | 118 | ||||
| -rw-r--r-- | include/dm/pinctrl.h | 60 | ||||
| -rw-r--r-- | include/dt-bindings/clock/rk3288-cru.h | 370 | ||||
| -rw-r--r-- | include/dt-bindings/clock/rockchip,rk808.h | 11 | ||||
| -rw-r--r-- | include/dt-bindings/pinctrl/rockchip.h | 26 | ||||
| -rw-r--r-- | include/dt-bindings/power-domain/rk3288.h | 11 | ||||
| -rw-r--r-- | include/dwmmc.h | 16 | ||||
| -rw-r--r-- | include/image.h | 5 | ||||
| -rw-r--r-- | include/power/act8846_pmic.h | 37 |
11 files changed, 682 insertions, 2 deletions
diff --git a/include/configs/chromebook_jerry.h b/include/configs/chromebook_jerry.h new file mode 100644 index 0000000..a22b123 --- /dev/null +++ b/include/configs/chromebook_jerry.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/rk3288_common.h> + +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD + +#endif diff --git a/include/configs/firefly-rk3288.h b/include/configs/firefly-rk3288.h new file mode 100644 index 0000000..a82adc8 --- /dev/null +++ b/include/configs/firefly-rk3288.h @@ -0,0 +1,14 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/rk3288_common.h> + +#define CONFIG_SPL_MMC_SUPPORT + +#endif diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h new file mode 100644 index 0000000..e8aec28 --- /dev/null +++ b/include/configs/rk3288_common.h @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RK3288_COMMON_H +#define __CONFIG_RK3288_COMMON_H + +#include <asm/arch/hardware.h> + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_OF_LIBFDT +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +#define CONFIG_SYS_TIMER_COUNTER (TIMER7_BASE + 8) + +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SPL_BOARD_INIT + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SYS_TEXT_BASE 0x00100000 +#define CONFIG_SYS_INIT_SP_ADDR 0x00100000 +#define CONFIG_SYS_LOAD_ADDR 0x00800800 +#define CONFIG_SPL_STACK 0xff718000 +#define CONFIG_SPL_TEXT_BASE 0xff704004 + +/* MMC/SD IP block */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_MMC +#define CONFIG_SDHCI +#define CONFIG_DWMMC +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + +/* RAW SD card / eMMC locations. */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256 +#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) + +/* FAT sd card locations. */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_PINCTRL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_RAM_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_TIME + +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_NR_DRAM_BANKS 1 +#define SDRAM_BANK_SIZE (2UL << 30) + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SF_DEFAULT_SPEED 20000000 + +#define CONFIG_CMD_I2C + +#ifndef CONFIG_SPL_BUILD +#include <config_distro_defaults.h> + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00000000\0" \ + "pxefile_addr_r=0x00100000\0" \ + "fdt_addr_r=0x01f00000\0" \ + "kernel_addr_r=0x02000000\0" \ + "ramdisk_addr_r=0x04000000\0" + +/* First try to boot from SD (index 0), then eMMC (index 1 */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#include <config_distro_bootcmd.h> + +/* Linux fails to load the fdt if it's loaded above 512M on a Rock 2 board, so + * limit the fdt reallocation to that */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x1fffffff\0" \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV +#endif + +#endif diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h index bc6fdb4..f6025f6 100644 --- a/include/dm/pinctrl.h +++ b/include/dm/pinctrl.h @@ -87,7 +87,33 @@ struct pinctrl_ops { int (*pinconf_group_set)(struct udevice *dev, unsigned group_selector, unsigned param, unsigned argument); int (*set_state)(struct udevice *dev, struct udevice *config); + + /* for pinctrl-simple */ int (*set_state_simple)(struct udevice *dev, struct udevice *periph); + /** + * request() - Request a particular pinctrl function + * + * This activates the selected function. + * + * @dev: Device to adjust (UCLASS_PINCTRL) + * @func: Function number (driver-specific) + * @return 0 if OK, -ve on error + */ + int (*request)(struct udevice *dev, int func, int flags); + + /** + * get_periph_id() - get the peripheral ID for a device + * + * This generally looks at the peripheral's device tree node to work + * out the peripheral ID. The return value is normally interpreted as + * enum periph_id. so long as this is defined by the platform (which it + * should be). + * + * @dev: Pinctrl device to use for decoding + * @periph: Device to check + * @return peripheral ID of @periph, or -ENOENT on error + */ + int (*get_periph_id)(struct udevice *dev, struct udevice *periph); }; #define pinctrl_get_ops(dev) ((struct pinctrl_ops *)(dev)->driver->ops) @@ -224,4 +250,38 @@ static inline int pinctrl_select_state(struct udevice *dev, } #endif +/** + * pinctrl_request() - Request a particular pinctrl function + * + * @dev: Device to check (UCLASS_PINCTRL) + * @func: Function number (driver-specific) + * @flags: Flags (driver-specific) + * @return 0 if OK, -ve on error + */ +int pinctrl_request(struct udevice *dev, int func, int flags); + +/** + * pinctrl_request_noflags() - Request a particular pinctrl function + * + * This is similar to pinctrl_request() but uses 0 for @flags. + * + * @dev: Device to check (UCLASS_PINCTRL) + * @func: Function number (driver-specific) + * @return 0 if OK, -ve on error + */ +int pinctrl_request_noflags(struct udevice *dev, int func); + +/** + * pinctrl_get_periph_id() - get the peripheral ID for a device + * + * This generally looks at the peripheral's device tree node to work out the + * peripheral ID. The return value is normally interpreted as enum periph_id. + * so long as this is defined by the platform (which it should be). + * + * @dev: Pinctrl device to use for decoding + * @periph: Device to check + * @return peripheral ID of @periph, or -ENOENT on error + */ +int pinctrl_get_periph_id(struct udevice *dev, struct udevice *periph); + #endif /* __PINCTRL_H */ diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h new file mode 100644 index 0000000..216eee5 --- /dev/null +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_NPLL 5 +#define ARMCLK 6 + +/* sclk gates (special clocks) */ +#define SCLK_GPU 64 +#define SCLK_SPI0 65 +#define SCLK_SPI1 66 +#define SCLK_SPI2 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO0 69 +#define SCLK_SDIO1 70 +#define SCLK_EMMC 71 +#define SCLK_TSADC 72 +#define SCLK_SARADC 73 +#define SCLK_PS2C 74 +#define SCLK_NANDC0 75 +#define SCLK_NANDC1 76 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_UART3 80 +#define SCLK_UART4 81 +#define SCLK_I2S0 82 +#define SCLK_SPDIF 83 +#define SCLK_SPDIF8CH 84 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_TIMER4 89 +#define SCLK_TIMER5 90 +#define SCLK_TIMER6 91 +#define SCLK_HSADC 92 +#define SCLK_OTGPHY0 93 +#define SCLK_OTGPHY1 94 +#define SCLK_OTGPHY2 95 +#define SCLK_OTG_ADP 96 +#define SCLK_HSICPHY480M 97 +#define SCLK_HSICPHY12M 98 +#define SCLK_MACREF 99 +#define SCLK_LCDC_PWM0 100 +#define SCLK_LCDC_PWM1 101 +#define SCLK_MAC_RX 102 +#define SCLK_MAC_TX 103 +#define SCLK_EDP_24M 104 +#define SCLK_EDP 105 +#define SCLK_RGA 106 +#define SCLK_ISP 107 +#define SCLK_ISP_JPE 108 +#define SCLK_HDMI_HDCP 109 +#define SCLK_HDMI_CEC 110 +#define SCLK_HEVC_CABAC 111 +#define SCLK_HEVC_CORE 112 +#define SCLK_I2S0_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO0_DRV 115 +#define SCLK_SDIO1_DRV 116 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO0_SAMPLE 119 +#define SCLK_SDIO1_SAMPLE 120 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_USBPHY480M_SRC 122 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 + +#define SCLK_MAC 151 +#define SCLK_MACREF_OUT 152 + +#define DCLK_VOP0 190 +#define DCLK_VOP1 191 + +/* aclk gates */ +#define ACLK_GPU 192 +#define ACLK_DMAC1 193 +#define ACLK_DMAC2 194 +#define ACLK_MMU 195 +#define ACLK_GMAC 196 +#define ACLK_VOP0 197 +#define ACLK_VOP1 198 +#define ACLK_CRYPTO 199 +#define ACLK_RGA 200 +#define ACLK_RGA_NIU 201 +#define ACLK_IEP 202 +#define ACLK_VIO0_NIU 203 +#define ACLK_VIP 204 +#define ACLK_ISP 205 +#define ACLK_VIO1_NIU 206 +#define ACLK_HEVC 207 +#define ACLK_VCODEC 208 +#define ACLK_CPU 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_GPIO4 324 +#define PCLK_GPIO5 325 +#define PCLK_GPIO6 326 +#define PCLK_GPIO7 327 +#define PCLK_GPIO8 328 +#define PCLK_GRF 329 +#define PCLK_SGRF 330 +#define PCLK_PMU 331 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_I2C4 336 +#define PCLK_I2C5 337 +#define PCLK_SPI0 338 +#define PCLK_SPI1 339 +#define PCLK_SPI2 340 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_UART3 344 +#define PCLK_UART4 345 +#define PCLK_TSADC 346 +#define PCLK_SARADC 347 +#define PCLK_SIM 348 +#define PCLK_GMAC 349 +#define PCLK_PWM 350 +#define PCLK_RKPWM 351 +#define PCLK_PS2C 352 +#define PCLK_TIMER 353 +#define PCLK_TZPC 354 +#define PCLK_EDP_CTRL 355 +#define PCLK_MIPI_DSI0 356 +#define PCLK_MIPI_DSI1 357 +#define PCLK_MIPI_CSI 358 +#define PCLK_LVDS_PHY 359 +#define PCLK_HDMI_CTRL 360 +#define PCLK_VIO2_H2P 361 +#define PCLK_CPU 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL0 364 +#define PCLK_PUBL0 365 +#define PCLK_DDRUPCTL1 366 +#define PCLK_PUBL1 367 +#define PCLK_WDT 368 + +/* hclk gates */ +#define HCLK_GPS 448 +#define HCLK_OTG0 449 +#define HCLK_USBHOST0 450 +#define HCLK_USBHOST1 451 +#define HCLK_HSIC 452 +#define HCLK_NANDC0 453 +#define HCLK_NANDC1 454 +#define HCLK_TSP 455 +#define HCLK_SDMMC 456 +#define HCLK_SDIO0 457 +#define HCLK_SDIO1 458 +#define HCLK_EMMC 459 +#define HCLK_HSADC 460 +#define HCLK_CRYPTO 461 +#define HCLK_I2S0 462 +#define HCLK_SPDIF 463 +#define HCLK_SPDIF8CH 464 +#define HCLK_VOP0 465 +#define HCLK_VOP1 466 +#define HCLK_ROM 467 +#define HCLK_IEP 468 +#define HCLK_ISP 469 +#define HCLK_RGA 470 +#define HCLK_VIO_AHB_ARBI 471 +#define HCLK_VIO_NIU 472 +#define HCLK_VIP 473 +#define HCLK_VIO2_H2P 474 +#define HCLK_HEVC 475 +#define HCLK_VCODEC 476 +#define HCLK_CPU 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE2 2 +#define SRST_CORE3 3 +#define SRST_CORE0_PO 4 +#define SRST_CORE1_PO 5 +#define SRST_CORE2_PO 6 +#define SRST_CORE3_PO 7 +#define SRST_PDCORE_STRSYS 8 +#define SRST_PDBUS_STRSYS 9 +#define SRST_L2C 10 +#define SRST_TOPDBG 11 +#define SRST_CORE0_DBG 12 +#define SRST_CORE1_DBG 13 +#define SRST_CORE2_DBG 14 +#define SRST_CORE3_DBG 15 + +#define SRST_PDBUG_AHB_ARBITOR 16 +#define SRST_EFUSE256 17 +#define SRST_DMAC1 18 +#define SRST_INTMEM 19 +#define SRST_ROM 20 +#define SRST_SPDIF8CH 21 +#define SRST_TIMER 22 +#define SRST_I2S0 23 +#define SRST_SPDIF 24 +#define SRST_TIMER0 25 +#define SRST_TIMER1 26 +#define SRST_TIMER2 27 +#define SRST_TIMER3 28 +#define SRST_TIMER4 29 +#define SRST_TIMER5 30 +#define SRST_EFUSE 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_GPIO4 36 +#define SRST_GPIO5 37 +#define SRST_GPIO6 38 +#define SRST_GPIO7 39 +#define SRST_GPIO8 40 +#define SRST_I2C0 42 +#define SRST_I2C1 43 +#define SRST_I2C2 44 +#define SRST_I2C3 45 +#define SRST_I2C4 46 +#define SRST_I2C5 47 + +#define SRST_DWPWM 48 +#define SRST_MMC_PERI 49 +#define SRST_PERIPH_MMU 50 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_TPIU 53 +#define SRST_PMU_APB 54 +#define SRST_GRF 55 +#define SRST_PMU 56 +#define SRST_PERIPH_AXI 57 +#define SRST_PERIPH_AHB 58 +#define SRST_PERIPH_APB 59 +#define SRST_PERIPH_NIU 60 +#define SRST_PDPERI_AHB_ARBI 61 +#define SRST_EMEM 62 +#define SRST_USB_PERI 63 + +#define SRST_DMAC2 64 +#define SRST_MAC 66 +#define SRST_GPS 67 +#define SRST_RKPWM 69 +#define SRST_CCP 71 +#define SRST_USBHOST0 72 +#define SRST_HSIC 73 +#define SRST_HSIC_AUX 74 +#define SRST_HSIC_PHY 75 +#define SRST_HSADC 76 +#define SRST_NANDC0 77 +#define SRST_NANDC1 78 + +#define SRST_TZPC 80 +#define SRST_SPI0 83 +#define SRST_SPI1 84 +#define SRST_SPI2 85 +#define SRST_SARADC 87 +#define SRST_PDALIVE_NIU 88 +#define SRST_PDPMU_INTMEM 89 +#define SRST_PDPMU_NIU 90 +#define SRST_SGRF 91 + +#define SRST_VIO_ARBI 96 +#define SRST_RGA_NIU 97 +#define SRST_VIO0_NIU_AXI 98 +#define SRST_VIO_NIU_AHB 99 +#define SRST_LCDC0_AXI 100 +#define SRST_LCDC0_AHB 101 +#define SRST_LCDC0_DCLK 102 +#define SRST_VIO1_NIU_AXI 103 +#define SRST_VIP 104 +#define SRST_RGA_CORE 105 +#define SRST_IEP_AXI 106 +#define SRST_IEP_AHB 107 +#define SRST_RGA_AXI 108 +#define SRST_RGA_AHB 109 +#define SRST_ISP 110 +#define SRST_EDP 111 + +#define SRST_VCODEC_AXI 112 +#define SRST_VCODEC_AHB 113 +#define SRST_VIO_H2P 114 +#define SRST_MIPIDSI0 115 +#define SRST_MIPIDSI1 116 +#define SRST_MIPICSI 117 +#define SRST_LVDS_PHY 118 +#define SRST_LVDS_CON 119 +#define SRST_GPU 120 +#define SRST_HDMI 121 +#define SRST_CORE_PVTM 124 +#define SRST_GPU_PVTM 125 + +#define SRST_MMC0 128 +#define SRST_SDIO0 129 +#define SRST_SDIO1 130 +#define SRST_EMMC 131 +#define SRST_USBOTG_AHB 132 +#define SRST_USBOTG_PHY 133 +#define SRST_USBOTG_CON 134 +#define SRST_USBHOST0_AHB 135 +#define SRST_USBHOST0_PHY 136 +#define SRST_USBHOST0_CON 137 +#define SRST_USBHOST1_AHB 138 +#define SRST_USBHOST1_PHY 139 +#define SRST_USBHOST1_CON 140 +#define SRST_USB_ADP 141 +#define SRST_ACC_EFUSE 142 + +#define SRST_CORESIGHT 144 +#define SRST_PD_CORE_AHB_NOC 145 +#define SRST_PD_CORE_APB_NOC 146 +#define SRST_PD_CORE_MP_AXI 147 +#define SRST_GIC 148 +#define SRST_LCDC_PWM0 149 +#define SRST_LCDC_PWM1 150 +#define SRST_VIO0_H2P_BRG 151 +#define SRST_VIO1_H2P_BRG 152 +#define SRST_RGA_H2P_BRG 153 +#define SRST_HEVC 154 +#define SRST_TSADC 159 + +#define SRST_DDRPHY0 160 +#define SRST_DDRPHY0_APB 161 +#define SRST_DDRCTRL0 162 +#define SRST_DDRCTRL0_APB 163 +#define SRST_DDRPHY0_CTRL 164 +#define SRST_DDRPHY1 165 +#define SRST_DDRPHY1_APB 166 +#define SRST_DDRCTRL1 167 +#define SRST_DDRCTRL1_APB 168 +#define SRST_DDRPHY1_CTRL 169 +#define SRST_DDRMSCH0 170 +#define SRST_DDRMSCH1 171 +#define SRST_CRYPTO 174 +#define SRST_C2C_HOST 175 + +#define SRST_LCDC1_AXI 176 +#define SRST_LCDC1_AHB 177 +#define SRST_LCDC1_DCLK 178 +#define SRST_UART0 179 +#define SRST_UART1 180 +#define SRST_UART2 181 +#define SRST_UART3 182 +#define SRST_UART4 183 +#define SRST_SIMC 186 +#define SRST_PS2C 187 +#define SRST_TSP 188 +#define SRST_TSP_CLKIN0 189 +#define SRST_TSP_CLKIN1 190 +#define SRST_TSP_27M 191 diff --git a/include/dt-bindings/clock/rockchip,rk808.h b/include/dt-bindings/clock/rockchip,rk808.h new file mode 100644 index 0000000..1a87343 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk808.h @@ -0,0 +1,11 @@ +/* + * This header provides constants clk index RK808 pmic clkout + */ +#ifndef _CLK_ROCKCHIP_RK808 +#define _CLK_ROCKCHIP_RK808 + +/* CLOCKOUT index */ +#define RK808_CLKOUT0 0 +#define RK808_CLKOUT1 1 + +#endif diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h new file mode 100644 index 0000000..56887e1 --- /dev/null +++ b/include/dt-bindings/pinctrl/rockchip.h @@ -0,0 +1,26 @@ +/* + * Header providing constants for Rockchip pinctrl bindings. + * + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ +#define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ + +#define RK_GPIO0 0 +#define RK_GPIO1 1 +#define RK_GPIO2 2 +#define RK_GPIO3 3 +#define RK_GPIO4 4 +#define RK_GPIO6 6 + +#define RK_FUNC_GPIO 0 +#define RK_FUNC_1 1 +#define RK_FUNC_2 2 +#define RK_FUNC_3 3 +#define RK_FUNC_4 4 + +#endif diff --git a/include/dt-bindings/power-domain/rk3288.h b/include/dt-bindings/power-domain/rk3288.h new file mode 100644 index 0000000..ca68c11 --- /dev/null +++ b/include/dt-bindings/power-domain/rk3288.h @@ -0,0 +1,11 @@ +#ifndef __DT_BINDINGS_POWER_DOMAIN_RK3288_H__ +#define __DT_BINDINGS_POWER_DOMAIN_RK3288_H__ + +/* RK3288 power domain index */ +#define RK3288_PD_GPU 0 +#define RK3288_PD_VIO 1 +#define RK3288_PD_VIDEO 2 +#define RK3288_PD_HEVC 3 +#define RK3288_PD_PERI 4 + +#endif diff --git a/include/dwmmc.h b/include/dwmmc.h index 7a7555a..25cf42c 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -163,7 +163,21 @@ struct dwmci_host { void (*clksel)(struct dwmci_host *host); void (*board_init)(struct dwmci_host *host); - unsigned int (*get_mmc_clk)(struct dwmci_host *host); + + /** + * Get / set a particular MMC clock frequency + * + * This is used to request the current clock frequency of the clock + * that drives the DWMMC peripheral. The caller will then use this + * information to work out the divider it needs to achieve the + * required MMC bus clock frequency. If you want to handle the + * clock external to DWMMC, use @freq to select the frequency and + * return that value too. Then DWMMC will put itself in bypass mode. + * + * @host: DWMMC host + * @freq: Frequency the host is trying to achieve + */ + unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq); struct mmc_config cfg; }; diff --git a/include/image.h b/include/image.h index 63c3d37..8a864ae 100644 --- a/include/image.h +++ b/include/image.h @@ -245,8 +245,11 @@ struct lmb; #define IH_TYPE_X86_SETUP 20 /* x86 setup.bin Image */ #define IH_TYPE_LPC32XXIMAGE 21 /* x86 setup.bin Image */ #define IH_TYPE_LOADABLE 22 /* A list of typeless images */ +#define IH_TYPE_RKIMAGE 23 /* Rockchip Boot Image */ +#define IH_TYPE_RKSD 24 /* Rockchip SD card */ +#define IH_TYPE_RKSPI 25 /* Rockchip SPI image */ -#define IH_TYPE_COUNT 23 /* Number of image types */ +#define IH_TYPE_COUNT 26 /* Number of image types */ /* * Compression Types diff --git a/include/power/act8846_pmic.h b/include/power/act8846_pmic.h new file mode 100644 index 0000000..a811f28 --- /dev/null +++ b/include/power/act8846_pmic.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PMIC_ACT8846_H_ +#define _PMIC_ACT8846_H_ + +#include <asm/gpio.h> + +#define ACT8846_NUM_OF_REGS 12 + +#define BUCK_VOL_MASK 0x3f +#define LDO_VOL_MASK 0x3f + +#define BUCK_EN_MASK 0x80 +#define LDO_EN_MASK 0x80 + +#define VOL_MIN_IDX 0x00 +#define VOL_MAX_IDX 0x3f + +struct act8846_reg_table { + char *name; + char reg_ctl; + char reg_vol; +}; + +struct pmic_act8846 { + struct pmic *pmic; + int node; /*device tree node*/ + struct gpio_desc pwr_hold; + struct udevice *dev; +}; + +#endif |