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-rwxr-xr-xinclude/asm-microblaze/asm.h98
-rw-r--r--include/asm-microblaze/microblaze_intc.h3
-rw-r--r--include/asm-ppc/mmu.h5
-rw-r--r--include/asm-ppc/processor.h20
-rw-r--r--include/cmd_confdefs.h2
-rw-r--r--include/common.h4
-rw-r--r--include/configs/MPC8540ADS.h5
-rw-r--r--include/configs/MPC8541CDS.h2
-rw-r--r--include/configs/MPC8544DS.h591
-rw-r--r--include/configs/MPC8548CDS.h30
-rw-r--r--include/configs/MPC8560ADS.h8
-rw-r--r--include/configs/MPC8568MDS.h505
-rw-r--r--include/configs/SBC8560.h410
-rw-r--r--include/configs/bamboo.h67
-rw-r--r--include/configs/delta.h1
-rw-r--r--include/configs/katmai.h14
-rw-r--r--include/configs/ml401.h61
-rw-r--r--include/configs/motionpro.h116
-rw-r--r--include/configs/sequoia.h4
-rw-r--r--include/configs/stxssa.h465
-rw-r--r--include/configs/xupv2p.h14
-rw-r--r--include/configs/zylonite.h1
-rw-r--r--include/linux/stat.h3
-rw-r--r--include/mpc86xx.h9
24 files changed, 1904 insertions, 534 deletions
diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h
new file mode 100755
index 0000000..f10f89c
--- /dev/null
+++ b/include/asm-microblaze/asm.h
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* FSL macros */
+#define NGET(val, fslnum) \
+ __asm__ __volatile__ ("nget %0, rfsl" #fslnum :"=r" (val));
+
+#define GET(val, fslnum) \
+ __asm__ __volatile__ ("get %0, rfsl" #fslnum :"=r" (val));
+
+#define NCGET(val, fslnum) \
+ __asm__ __volatile__ ("ncget %0, rfsl" #fslnum :"=r" (val));
+
+#define CGET(val, fslnum) \
+ __asm__ __volatile__ ("cget %0, rfsl" #fslnum :"=r" (val));
+
+#define NPUT(val, fslnum) \
+ __asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val));
+
+#define PUT(val, fslnum) \
+ __asm__ __volatile__ ("put %0, rfsl" #fslnum ::"r" (val));
+
+#define NCPUT(val, fslnum) \
+ __asm__ __volatile__ ("ncput %0, rfsl" #fslnum ::"r" (val));
+
+#define CPUT(val, fslnum) \
+ __asm__ __volatile__ ("cput %0, rfsl" #fslnum ::"r" (val));
+
+/* CPU dependent */
+/* machine status register */
+#define MFS(val, reg) \
+ __asm__ __volatile__ ("mfs %0," #reg :"=r" (val));
+
+#define MTS(val, reg) \
+ __asm__ __volatile__ ("mts " #reg ", %0"::"r" (val));
+
+/* get return address from interrupt */
+#define R14(val) \
+ __asm__ __volatile__ ("addi %0, r14, 0":"=r" (val));
+
+#define NOP __asm__ __volatile__ ("nop");
+
+/* use machine status registe USE_MSR_REG */
+#ifdef XILINX_USE_MSR_INSTR
+#define MSRSET(val) \
+ __asm__ __volatile__ ("msrset r0," #val );
+
+#define MSRCLR(val) \
+ __asm__ __volatile__ ("msrclr r0," #val );
+
+#else
+#define MSRSET(val) \
+{ \
+ register unsigned tmp; \
+ __asm__ __volatile__ (" \
+ mfs %0, rmsr; \
+ ori %0, %0, "#val"; \
+ mts rmsr, %0; \
+ nop;" \
+ : "=r" (tmp) \
+ : "d" (val) \
+ : "memory"); \
+}
+
+#define MSRCLR(val) \
+{ \
+ register unsigned tmp; \
+ __asm__ __volatile__ (" \
+ mfs %0, rmsr; \
+ andi %0, %0, ~"#val"; \
+ mts rmsr, %0; \
+ nop;" \
+ : "=r" (tmp) \
+ : "d" (val) \
+ : "memory"); \
+}
+#endif
diff --git a/include/asm-microblaze/microblaze_intc.h b/include/asm-microblaze/microblaze_intc.h
index 6635aea..4c385aa 100644
--- a/include/asm-microblaze/microblaze_intc.h
+++ b/include/asm-microblaze/microblaze_intc.h
@@ -38,3 +38,6 @@ struct irq_action {
void *arg;
int count; /* number of interrupt */
};
+
+void install_interrupt_handler (int irq, interrupt_handler_t * hdlr,
+ void *arg);
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index b226825..48fd982 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -396,8 +396,8 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define BOOKE_PAGESZ_16M 7
#define BOOKE_PAGESZ_64M 8
#define BOOKE_PAGESZ_256M 9
-#define BOOKE_PAGESZ_1GB 10
-#define BOOKE_PAGESZ_4GB 11
+#define BOOKE_PAGESZ_1G 10
+#define BOOKE_PAGESZ_4G 11
#if defined(CONFIG_MPC86xx)
#define LAWBAR_BASE_ADDR 0x00FFFFFF
@@ -413,6 +413,7 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define LAWAR_TRGT_IF_PCI1 0x00000000
#define LAWAR_TRGT_IF_PCIX 0x00000000
#define LAWAR_TRGT_IF_PCI2 0x00100000
+#define LAWAR_TRGT_IF_PEX 0x00200000
#define LAWAR_TRGT_IF_LBC 0x00400000
#define LAWAR_TRGT_IF_CCSR 0x00800000
#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 0585962..5efc3ee 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -232,6 +232,9 @@
#define HID0_BHTE (1<<2) /* Branch History Table Enable */
#define HID0_BTCD (1<<1) /* Branch target cache disable */
#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
+#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */
+#define HID1_ASTME (1<<13) /* Address bus streaming mode */
+#define HID1_ABE (1<<12) /* Address broadcast enable */
#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
#ifndef CONFIG_BOOKE
#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
@@ -415,10 +418,12 @@
#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
/* e500 definitions */
-#define SPRN_L1CSR0 0x3f2 /* L1 Cache Control and Status Register 0 */
+#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
+#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
-#define SPRN_L1CSR1 0x3f3 /* L1 Cache Control and Status Register 1 */
+#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
+#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
@@ -701,8 +706,6 @@
#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */
#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */
-/* System-On-Chip Version Numbers (version field only) */
-#define SVR_MPC5200 0x8011
/* Processor Version Register */
@@ -813,6 +816,12 @@
#define PVR_8260_HIP7R1 0x80822013
#define PVR_8260_HIP7RA 0x80822014
+/*
+ * MPC 52xx
+ */
+#define PVR_5200 0x80822011
+#define PVR_5200B 0x80822014
+
/*
* System Version Register
@@ -840,9 +849,12 @@
#define SVR_8560 0x8070
#define SVR_8555 0x8079
#define SVR_8541 0x807A
+#define SVR_8544 0x8034
+#define SVR_8544_E 0x803C
#define SVR_8548 0x8031
#define SVR_8548_E 0x8039
#define SVR_8641 0x8090
+#define SVR_8568_E 0x807D
/* I am just adding a single entry for 8260 boards. I think we may be
diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h
index cf36583..b3ccdce 100644
--- a/include/cmd_confdefs.h
+++ b/include/cmd_confdefs.h
@@ -94,6 +94,7 @@
#define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */
#define CFG_CMD_SNTP 0x2000000000000000ULL /* SNTP support */
#define CFG_CMD_DISPLAY 0x4000000000000000ULL /* Display support */
+#define CFG_CMD_MFSL 0x8000000000000000ULL /* FSL support for Microblaze */
#define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFULL /* ALL commands */
@@ -125,6 +126,7 @@
CFG_CMD_IRQ | \
CFG_CMD_JFFS2 | \
CFG_CMD_KGDB | \
+ CFG_CMD_MFSL | \
CFG_CMD_MII | \
CFG_CMD_MMC | \
CFG_CMD_NAND | \
diff --git a/include/common.h b/include/common.h
index c4fc2b3..3c4b37b 100644
--- a/include/common.h
+++ b/include/common.h
@@ -402,6 +402,10 @@ void ppcDcbi(unsigned long value);
void ppcSync(void);
void ppcDcbz(unsigned long value);
#endif
+#if defined (CONFIG_MICROBLAZE)
+unsigned short in16(unsigned int);
+void out16(unsigned int, unsigned short value);
+#endif
#if defined (CONFIG_MPC83XX)
void ppcDWload(unsigned int *addr, unsigned int *ret);
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 74a84f4..5aeea58 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -330,13 +330,12 @@
/*
* General PCI
- * Addresses are mapped 1-1.
+ * Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
-
-#define CFG_PCI1_IO_BASE 0x0
+#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index db389cf..fb360d2 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -334,7 +334,7 @@ extern unsigned long get_clock_freq(void);
/*
* General PCI
- * Addresses are mapped 1-1.
+ * Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
new file mode 100644
index 0000000..4c34308
--- /dev/null
+++ b/include/configs/MPC8544DS.h
@@ -0,0 +1,591 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8544ds board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8544 1
+#define CONFIG_MPC8544DS 1
+
+#undef CONFIG_PCI /* Enable PCI/PCIE */
+#undef CONFIG_PCI1 /* PCI controller 1 */
+#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
+#undef CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
+#undef CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
+#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#undef CONFIG_DDR_DLL
+#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
+#define CONFIG_DDR_ECC_CMD
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash associated with the CDS board.
+ * This allows booting from a promjet.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00400000
+#define CFG_ALT_MEMTEST
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+
+#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
+#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
+#define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000)
+#define CFG_PCIE3_ADDR (CFG_CCSRBAR+0xb000)
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+
+#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
+
+/*
+ * Make sure required options are set
+ */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
+ *
+ * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
+ *
+ * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
+ *
+ * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
+ * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
+ *
+ * Localbus cacheable
+ *
+ * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
+ * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
+ *
+ * Localbus non-cacheable
+ *
+ * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
+ * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
+ * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
+ *
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CFG_BOOT_BLOCK 0xfc000000 /* boot TLB */
+
+#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
+
+#define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
+
+#define CFG_BR0_PRELIM 0xff801001
+#define CFG_BR1_PRELIM 0xfe801001
+
+#define CFG_OR0_PRELIM 0xff806e65
+#define CFG_OR1_PRELIM 0xff806e65
+
+#define CFG_FLASH_BANKS_LIST {0xfe800000,CFG_FLASH_BASE}
+
+#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
+#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+#define CFG_LBC_NONCACHE_BASE 0xf8000000
+
+#define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */
+#define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
+
+#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */
+#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
+
+#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
+#define PIXIS_ID 0x0 /* Board ID at offset 0 */
+#define PIXIS_VER 0x1 /* Board version at offset 1 */
+#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
+#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
+#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
+ * register */
+#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
+#define PIXIS_VCTL 0x10 /* VELA Control Register */
+#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
+#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
+#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
+#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
+#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
+#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
+
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM 1
+#define CFG_INIT_L1_LOCK 1
+#define CFG_INIT_L1_ADDR 0xf4010000 /* Initial L1 address */
+#define CFG_INIT_L1_END 0x00004000 /* End of used area in RAM */
+
+/* define to use L2SRAM as initial stack */
+#undef CONFIG_L2_INIT_RAM
+#define CFG_INIT_L2_ADDR 0xf8fc0000
+#define CFG_INIT_L2_END 0x00040000 /* End of used area in RAM */
+
+#ifdef CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_ADDR CFG_INIT_L1_ADDR
+#define CFG_INIT_RAM_END CFG_INIT_L1_END
+#else
+#define CFG_INIT_RAM_ADDR CFG_INIT_L2_ADDR
+#define CFG_INIT_RAM_END CFG_INIT_L2_END
+#endif
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,8544@0"
+#define OF_SOC "soc8544@e0000000"
+#define OF_TBCLK (bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH "/soc8544@e0000000/serial@4500"
+
+/* I2C */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_EEPROM_ADDR 0x57
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3100
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CFG_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
+#define CFG_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
+
+#define CFG_PCI1_MEM_BASE 0xc0000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xe1000000
+#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
+
+/* controller 2, Slot 1, tgtid 1, Base address 9000 */
+#define CFG_PCIE2_MEM_BASE 0x80000000
+#define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE
+#define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCIE2_IO_BASE 0x00000000
+#define CFG_PCIE2_IO_PHYS 0xe2000000
+#define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */
+
+/* controller 1, Slot 2,tgtid 2, Base address a000 */
+#define CFG_PCIE1_MEM_BASE 0xa0000000
+#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE 0x08000000 /* 128M */
+#define CFG_PCIE1_MEM_BASE2 0xa8000000
+#define CFG_PCIE1_MEM_PHYS2 CFG_PCIE1_MEM_BASE2
+#define CFG_PCIE1_MEM_SIZE2 0x04000000 /* 64M */
+#define CFG_PCIE1_IO_BASE 0x00000000 /* reuse mem LAW */
+#define CFG_PCIE1_IO_PHYS 0xaf000000
+#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
+
+/* controller 3, direct to uli, tgtid 3, Base address b000 */
+#define CFG_PCIE3_MEM_BASE 0xb0000000
+#define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE
+#define CFG_PCIE3_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCIE3_IO_BASE 0x00000000
+#define CFG_PCIE3_IO_PHYS 0xe3000000
+#define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#define CONFIG_RTL8139
+
+#ifdef CONFIG_RTL8139
+/* This macro is used by RTL8139 but not defined in PPC architecture */
+#define KSEG1ADDR(x) (x)
+#define _IO_BASE 0x00000000
+#endif
+
+#ifndef CONFIG_PCI_PNP
+ #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE
+ #define PCI_ENET0_MEMADDR CFG_PCI1_IO_BASE
+ #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CFG_SCSI_MAX_SCSI_ID 4
+#define CFG_SCSI_MAX_LUN 1
+#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
+#endif /* SCSCI */
+
+#endif /* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+#define CONFIG_MPC85XX_TSEC1 1
+#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC1"
+#define CONFIG_MPC85XX_TSEC3 1
+#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC3"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR 0
+#define TSEC3_PHY_ADDR 1
+
+#define TSEC1_PHYIDX 0
+#define TSEC3_PHYIDX 0
+
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#if CFG_MONITOR_BASE > 0xfff80000
+#define CFG_ENV_ADDR 0xfff80000
+#else
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+#endif
+#define CFG_ENV_SIZE 0x2000
+#define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_PCI \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C \
+ | CFG_CMD_MII \
+ | CFG_CMD_BEDBUG \
+ | CFG_CMD_NET)
+#else
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C \
+ | CFG_CMD_MII)
+#endif
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
+#endif
+
+#define CONFIG_IPADDR 192.168.1.251
+
+#define CONFIG_HOSTNAME 8544ds_unknown
+#define CONFIG_ROOTPATH /nfs/mpc85xx
+#define CONFIG_BOOTFILE 8544ds_tmt/uImage.uboot
+
+#define CONFIG_SERVERIP 192.168.0.1
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_NETMASK 255.255.0.0
+
+#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE 115200
+
+#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
+#define PCIE_ENV \
+ "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
+ "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
+ "pcie1regs=setenv a e000a; run pciereg\0" \
+ "pcie2regs=setenv a e0009; run pciereg\0" \
+ "pcie3regs=setenv a e000b; run pciereg\0" \
+ "pcieerr=md ${a}020 1; md ${a}e00;" \
+ "pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
+ "pci d.w $b.0 56 1;" \
+ "pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \
+ "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff;" \
+ "pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff;" \
+ "pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \
+ "pci w $b.0 130 ffffffff\0" \
+ "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
+ "pcie1err=setenv a e000a; run pcieerr\0" \
+ "pcie2err=setenv a e0009; run pcieerr\0" \
+ "pcie3err=setenv a e000b; run pcieerr\0" \
+ "pcie1errc=setenv a e000a; run pcieerrc\0" \
+ "pcie2errc=setenv a e0009; run pcieerrc\0" \
+ "pcie3errc=setenv a e000b; run pcieerrc\0"
+#else
+#define PCIE_ENV ""
+#endif
+
+#if defined(CONFIG_PCI1)
+#define PCI_ENV \
+ "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
+ "echo e;md ${a}e00 9\0" \
+ "pci1regs=setenv a e0008; run pcireg\0" \
+ "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
+ "pci d.w $b.0 56 1\0" \
+ "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
+ "pci w.w $b.0 56 ffff\0" \
+ "pci1err=setenv a e0008; run pcierr\0" \
+ "pci1errc=setenv a e0008; run pcierrc\0"
+#else
+#define PCI_ENV ""
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+#define ENET_ENV \
+ "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \
+ "md ${a}098 2\0" \
+ "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \
+ "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \
+ "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \
+ "echo mib;md ${a}680 31\0" \
+ "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \
+ "enet1regs=setenv a e0024; run enetreg\0" \
+ "enet3regs=setenv a e0026; run enetreg\0"
+#else
+#define ENET_ENV ""
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=8544ds_tmt/ramdisk.uboot\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=8544ds_tmt/mpc8544ds.dtb\0" \
+ "eoi=mw e00400b0 0\0" \
+ "iack=md e00400a0 1\0" \
+ "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
+ "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
+ "ddrregs=setenv a e0002; run ddrreg\0" \
+ "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
+ "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
+ "guregs=setenv a e00e0; run gureg\0" \
+ "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
+ "ecmregs=setenv a e0001; run ecmreg\0" \
+ PCIE_ENV \
+ PCI_ENV \
+ ENET_ENV
+
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs root=/dev/sda3 rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 7c4849f..680009d 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -36,12 +36,12 @@
#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
-#undef CONFIG_PCI
+#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
@@ -340,22 +340,34 @@ extern unsigned long get_clock_freq(void);
/*
* General PCI
- * Addresses are mapped 1-1.
+ * Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
-#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
+#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
-#define CFG_PCI2_MEM_BASE 0xa0000000
+#define CFG_PCI2_MEM_BASE 0x90000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
#define CFG_PCI2_IO_BASE 0x00000000
-#define CFG_PCI2_IO_PHYS 0xe2100000
-#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
+#define CFG_PCI2_IO_PHYS 0xe2800000
+#define CFG_PCI2_IO_SIZE 0x00800000 /* 8M */
+#define CFG_PEX_MEM_BASE 0xa0000000
+#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE
+#define CFG_PEX_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PEX_IO_BASE 0x00000000
+#define CFG_PEX_IO_PHYS 0xe3000000
+#define CFG_PEX_IO_SIZE 0x01000000 /* 16M */
+
+/*
+ * RapidIO MMU
+ */
+#define CFG_RIO_MEM_BASE 0xC0000000
+#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */
#if defined(CONFIG_PCI)
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 835bf5c..21e6637 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -320,14 +320,14 @@
/*
* General PCI
- * Addresses are mapped 1-1.
+ * Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI1_IO_BASE 0xe2000000
-#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xe2000000
+#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
#if defined(CONFIG_PCI)
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
new file mode 100644
index 0000000..3f65644
--- /dev/null
+++ b/include/configs/MPC8568MDS.h
@@ -0,0 +1,505 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8568mds board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
+#define CONFIG_MPC8568 1 /* MPC8568 specific */
+#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
+
+#undef CONFIG_PCI
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_DLL /* possible DLL fix needed */
+/*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */
+
+/*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */
+/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash associated with the MDS board.
+ * This allows booting from a promjet.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif /*Replace a call to get_clock_freq (after it is implemented)*/
+#define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+/*#define CONFIG_L2_CACHE*/ /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+
+#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
+
+/*
+ * Make sure required options are set
+ */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ * Port Size = 16 bits = BRx[19:20] = 10
+ * Use GPCM = BRx[24:26] = 000
+ * Valid = BRx[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
+ *
+ * OR0, OR1:
+ * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ * Reserved ORx[17:18] = 11, confusion here?
+ * CSNT = ORx[20] = 1
+ * ACS = half cycle delay = ORx[21:22] = 11
+ * SCY = 6 = ORx[24:27] = 0110
+ * TRLX = use relaxed timing = ORx[29] = 1
+ * EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
+ */
+#define CFG_BCSR_BASE 0xf8000000
+
+#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
+
+/*Chip select 0 - Flash*/
+#define CFG_BR0_PRELIM 0xfe001001
+#define CFG_OR0_PRELIM 0xfe006ff7
+
+/*Chip slelect 1 - BCSR*/
+#define CFG_BR1_PRELIM 0xf8000801
+#define CFG_OR1_PRELIM 0xffffe9f7
+
+/*#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} */
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 512 /* sectors per device */
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+
+/*
+ * SDRAM on the LocalBus
+ */
+#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+
+
+/*Chip select 2 - SDRAM*/
+#define CFG_BR2_PRELIM 0xf0001861
+#define CFG_OR2_PRELIM 0xfc006901
+
+#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
+#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
+#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
+#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
+#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
+
+/*
+ * Common settings for all Local Bus SDRAM commands.
+ * At run time, either BSMA1516 (for CPU 1.1)
+ * or BSMA1617 (for CPU 1.0) (old)
+ * is OR'ed in too.
+ */
+#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
+ | CFG_LBC_LSDMR_PRETOACT7 \
+ | CFG_LBC_LSDMR_ACTTORW7 \
+ | CFG_LBC_LSDMR_BL8 \
+ | CFG_LBC_LSDMR_WRC4 \
+ | CFG_LBC_LSDMR_CL3 \
+ | CFG_LBC_LSDMR_RFEN \
+ )
+
+/*
+ * The bcsr registers are connected to CS3 on MDS.
+ * The new memory map places bcsr at 0xf8000000.
+ *
+ * For BR3, need:
+ * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
+ * port-size = 8-bits = BR[19:20] = 01
+ * no parity checking = BR[21:22] = 00
+ * GPMC for MSEL = BR[24:26] = 000
+ * Valid = BR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
+ *
+ * For OR3, need:
+ * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
+ * disable buffer ctrl OR[19] = 0
+ * CSNT OR[20] = 1
+ * ACS OR[21:22] = 11
+ * XACS OR[23] = 1
+ * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
+ * SETA OR[28] = 0
+ * TRLX OR[29] = 1
+ * EHTR OR[30] = 1
+ * EAD extra time OR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
+ */
+#define CFG_BCSR (0xf8000000)
+
+/*Chip slelect 4 - PIB*/
+#define CFG_BR4_PRELIM 0xf8008801
+#define CFG_OR4_PRELIM 0xffffe9f7
+
+/*Chip select 5 - PIB*/
+#define CFG_BR5_PRELIM 0xf8010801
+#define CFG_OR5_PRELIM 0xffff69f7
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser*/
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,8568@0"
+#define OF_SOC "soc8568@e0000000"
+#define OF_TBCLK (bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600"
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_EEPROM_ADDR 0x57
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
+
+/*
+ * General PCI
+ * Memory Addresses are mapped 1-1. I/O is mapped from 0
+ */
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xe2000000
+#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
+
+#define CFG_PEX_MEM_BASE 0xa0000000
+#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE
+#define CFG_PEX_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PEX_IO_BASE 0x00000000
+#define CFG_PEX_IO_PHYS 0xe2800000
+#define CFG_PEX_IO_SIZE 0x00800000 /* 8M */
+
+#define CFG_SRIO_MEM_BASE 0xc0000000
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+#endif /* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_MPC85XX_TSEC1 1
+#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0"
+#define CONFIG_MPC85XX_TSEC2 1
+#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
+#undef CONFIG_MPC85XX_TSEC3
+#undef CONFIG_MPC85XX_TSEC4
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR 2
+#define TSEC2_PHY_ADDR 3
+
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+
+/* Options are: eTSEC[0-3] */
+#define CONFIG_ETHPRIME "eTSEC0"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+#define CFG_ENV_SIZE 0x2000
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_PCI \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C \
+ | CFG_CMD_MII)
+#else
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C \
+ | CFG_CMD_MII)
+#endif
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
+#endif
+
+#define CONFIG_IPADDR 192.168.1.253
+
+#define CONFIG_HOSTNAME unknown
+#define CONFIG_ROOTPATH /nfsroot
+#define CONFIG_BOOTFILE your.uImage
+
+#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK 255.255.255.0
+
+#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=600000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=your.fdt.dtb\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs\0" \
+
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "run nfsargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "run ramargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/SBC8560.h b/include/configs/SBC8560.h
deleted file mode 100644
index 8b46a17..0000000
--- a/include/configs/SBC8560.h
+++ /dev/null
@@ -1,410 +0,0 @@
-/*
- * (C) Copyright 2002,2003 Motorola,Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
- * Added support for Wind River SBC8560 board
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* mpc8560ads board configuration file */
-/* please refer to doc/README.mpc85xx for more info */
-/* make sure you change the MAC address and other network params first,
- * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#if XXX
-#define DEBUG /* General debug */
-#define ET_DEBUG
-#endif
-#define TSEC_DEBUG
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
-#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
-
-
-#define CONFIG_CPM2 1 /* has CPM2 */
-#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
-
-#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */
-
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#undef CONFIG_PCI /* pci ethernet support */
-#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
-
-
-#define CONFIG_ENV_OVERWRITE
-
-/* Using Localbus SDRAM to emulate flash before we can program the flash,
- * normally you need a flash-boot image(u-boot.bin), if so undef this.
- */
-#undef CONFIG_RAM_AS_FLASH
-
-#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
- #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */
-#else
- #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */
-#endif
-
-/* below can be toggled for performance analysis. otherwise use default */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#undef CONFIG_BTB /* toggle branch predition */
-#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-
-#undef CFG_DRAM_TEST /* memory test, takes time */
-#define CFG_MEMTEST_START 0x00200000 /* memtest region */
-#define CFG_MEMTEST_END 0x00400000
-
-#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
- defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
- defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
-#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
-#endif
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
-
-#if XXX
- #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
-#else
- #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */
-#endif
-#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
-
-#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
-#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
-#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */
-#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */
-
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-
-#if defined(CONFIG_MPC85xx_REV1)
- #define CONFIG_DDR_DLL /* possible DLL fix needed */
-#endif
-
-#undef CONFIG_CLOCKS_IN_MHZ
-
-#if defined(CONFIG_RAM_AS_FLASH)
- #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
- #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
- #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */
- #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
-#else /* Boot from real Flash */
- #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
- #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
- #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */
- #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
-#endif
-#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-/* local bus definitions */
-#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
-#define CFG_OR1_PRELIM 0xfc000ff7
-
-#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */
-#define CFG_OR2_PRELIM 0x00000000
-
-#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
-#define CFG_OR3_PRELIM 0xfc000cc1
-
-#if defined(CONFIG_RAM_AS_FLASH)
- #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
-#else
- #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
-#endif
-#define CFG_OR4_PRELIM 0xfc000cc1
-
-#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
-#if 1
- #define CFG_OR5_PRELIM 0xff000ff7
-#else
- #define CFG_OR5_PRELIM 0xff0000f0
-#endif
-
-#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
-#define CFG_OR6_PRELIM 0xfc000ff7
-#define CFG_LBC_LCRR 0x00030002 /* local bus freq */
-#define CFG_LBC_LBCR 0x00000000
-#define CFG_LBC_LSRT 0x20000000
-#define CFG_LBC_MRTPR 0x20000000
-#define CFG_LBC_LSDMR_1 0x2861b723
-#define CFG_LBC_LSDMR_2 0x0861b723
-#define CFG_LBC_LSDMR_3 0x0861b723
-#define CFG_LBC_LSDMR_4 0x1861b723
-#define CFG_LBC_LSDMR_5 0x4061b723
-
-/* just hijack the MOT BCSR def for SBC8560 misc devices */
-#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000)
-/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
-
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
-#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
-
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else */
-
-#define CONFIG_CONS_INDEX 1
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE 1
-#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */
-#define CONFIG_BAUDRATE 9600
-
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000)
-#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000)
-
-/* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
-#endif
-
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-
-#define CFG_PCI_MEM_BASE 0xC0000000
-#define CFG_PCI_MEM_PHYS 0xC0000000
-#define CFG_PCI_MEM_SIZE 0x10000000
-
-#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
-
-# define CONFIG_NET_MULTI 1
-# define CONFIG_MII 1 /* MII PHY management */
-# define CONFIG_MPC85xx_TSEC1
-# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0"
-# define TSEC1_PHY_ADDR 25
-# define TSEC1_PHYIDX 0
-/* Options are: TSEC0 */
-# define CONFIG_ETHPRIME "TSEC0"
-
-
-#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
-
- #undef CONFIG_ETHER_NONE /* define if ether on something else */
- #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
- #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
-
- #if (CONFIG_ETHER_INDEX == 2)
- /*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers
- * - Full duplex
- */
- #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
- #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
- #define CFG_CPMFCR_RAMTYPE 0
- #define CFG_FCC_PSMR (FCC_PSMR_FDE)
-
- #elif (CONFIG_ETHER_INDEX == 3)
- /* need more definitions here for FE3 */
- #endif /* CONFIG_ETHER_INDEX */
-
- #define CONFIG_MII /* MII PHY management */
- #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
- /*
- * GPIO pins used for bit-banged MII communications
- */
- #define MDIO_PORT 2 /* Port C */
- #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
- #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
- #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
-
- #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
- else iop->pdat &= ~0x00400000
-
- #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
- else iop->pdat &= ~0x00200000
-
- #define MIIDELAY udelay(1)
-
-#endif
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#if 0
-#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CFG_FLASH_PROTECTION /* use hardware protection */
-#endif
-#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-
-#undef CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
-
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-
-#if 0
-/* XXX This doesn't work and I don't want to fix it */
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
- #define CFG_RAMBOOT
-#else
- #undef CFG_RAMBOOT
-#endif
-#endif
-
-/* Environment */
-#if !defined(CFG_RAMBOOT)
- #if defined(CONFIG_RAM_AS_FLASH)
- #define CFG_ENV_IS_NOWHERE
- #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
- #define CFG_ENV_SIZE 0x2000
- #else
- #define CFG_ENV_IS_IN_FLASH 1
- #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
- #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
- #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */
- #endif
-#else
- #define CFG_NO_FLASH 1 /* Flash is not usable now */
- #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
- #define CFG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
-/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
-#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
-#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV | \
- CFG_CMD_LOADS ))
- #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV))
- #endif
-#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_PING | CFG_CMD_I2C)
- #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_PING | CFG_CMD_I2C)
- #endif
-#endif
-
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
- #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_LOAD_ADDR 0x1000000 /* default load address */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
- #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
- #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
- #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*Note: change below for your network setting!!! */
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
-# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a
-# define CONFIG_HAS_ETH1
-# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b
-# define CONFIG_HAS_ETH2
-# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c
-#endif
-
-#define CONFIG_SERVERIP YourServerIP
-#define CONFIG_IPADDR YourTargetIP
-#define CONFIG_GATEWAYIP YourGatewayIP
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_HOSTNAME SBC8560
-#define CONFIG_ROOTPATH YourRootPath
-#define CONFIG_BOOTFILE YourImageName
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index bcc736c..db58a9f 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2005-2006
+ * (C) Copyright 2005-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -43,7 +43,6 @@
* 2nd ethernet port you have to "undef" the following define.
*/
#define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */
-#define CFG_NAND_LEGACY
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
@@ -143,65 +142,13 @@
#endif /* CFG_ENV_IS_IN_FLASH */
/*-----------------------------------------------------------------------
- * NAND-FLASH related
+ * NAND FLASH
*----------------------------------------------------------------------*/
-#define NAND_CMD_REG (0x00) /* NandFlash Command Register */
-#define NAND_ADDR_REG (0x04) /* NandFlash Address Register */
-#define NAND_DATA_REG (0x08) /* NandFlash Data Register */
-#define NAND_ECC0_REG (0x10) /* NandFlash ECC Register0 */
-#define NAND_ECC1_REG (0x14) /* NandFlash ECC Register1 */
-#define NAND_ECC2_REG (0x18) /* NandFlash ECC Register2 */
-#define NAND_ECC3_REG (0x1C) /* NandFlash ECC Register3 */
-#define NAND_ECC4_REG (0x20) /* NandFlash ECC Register4 */
-#define NAND_ECC5_REG (0x24) /* NandFlash ECC Register5 */
-#define NAND_ECC6_REG (0x28) /* NandFlash ECC Register6 */
-#define NAND_ECC7_REG (0x2C) /* NandFlash ECC Register7 */
-#define NAND_CR0_REG (0x30) /* NandFlash Device Bank0 Config Register */
-#define NAND_CR1_REG (0x34) /* NandFlash Device Bank1 Config Register */
-#define NAND_CR2_REG (0x38) /* NandFlash Device Bank2 Config Register */
-#define NAND_CR3_REG (0x3C) /* NandFlash Device Bank3 Config Register */
-#define NAND_CCR_REG (0x40) /* NandFlash Core Configuration Register */
-#define NAND_STAT_REG (0x44) /* NandFlash Device Status Register */
-#define NAND_HWCTL_REG (0x48) /* NandFlash Direct Hwd Control Register */
-#define NAND_REVID_REG (0x50) /* NandFlash Core Revision Id Register */
-
-/* Nand Flash K9F1208U0A Command Set => Nand Flash 0 */
-#define NAND0_CMD_READ1_HALF1 0x00 /* Starting addr for 1rst half of registers */
-#define NAND0_CMD_READ1_HALF2 0x01 /* Starting addr for 2nd half of registers */
-#define NAND0_CMD_READ2 0x50
-#define NAND0_CMD_READ_ID 0x90
-#define NAND0_CMD_READ_STATUS 0x70
-#define NAND0_CMD_RESET 0xFF
-#define NAND0_CMD_PAGE_PROG 0x80
-#define NAND0_CMD_PAGE_PROG_TRUE 0x10
-#define NAND0_CMD_PAGE_PROG_DUMMY 0x11
-#define NAND0_CMD_BLOCK_ERASE 0x60
-#define NAND0_CMD_BLOCK_ERASE_END 0xD0
-
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_CMD_REG) = d;} while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_ADDR_REG) = d;} while(0)
-#define WRITE_NAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_DATA_REG) = d;} while(0)
-#define READ_NAND(adr) (*(volatile u8 *)((ulong)adr+NAND_DATA_REG))
-#define NAND_WAIT_READY(nand) while (!(*(volatile u8 *)((ulong)nand->IO_ADDR+NAND_STAT_REG) & 0x01))
-
-/* not needed with 440EP NAND controller */
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
+#define CFG_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CFG_NAND_CS 1
+#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
+#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
/*-----------------------------------------------------------------------
* DDR SDRAM
diff --git a/include/configs/delta.h b/include/configs/delta.h
index 91284fd..1568120 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -188,7 +188,6 @@
/*
* NAND Flash
*/
-/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
#undef CFG_NAND_LEGACY
#define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index 7f55366..cc47a16 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -360,7 +360,19 @@
EBC_BXCR_BW_16BIT)
/* Memory Bank 1 (Xilinx System ACE controller) initialization */
-#define CFG_EBC_PB1AP 0x7F8FFE80
+#define CFG_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
+ EBC_BXAP_TWT_ENCODE(4) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(0) | \
+ EBC_BXAP_WBN_ENCODE(0) | \
+ EBC_BXAP_WBF_ENCODE(0) | \
+ EBC_BXAP_TH_ENCODE(0) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
#define CFG_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CFG_ACE_BASE) | \
EBC_BXCR_BS_1MB | \
EBC_BXCR_BU_RW | \
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index cb159e7..3db2877 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -28,6 +28,7 @@
#include "../board/xilinx/ml401/xparameters.h"
#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
+#define MICROBLAZE_V5 1
#define CONFIG_ML401 1 /* ML401 Board */
/* uart */
@@ -36,11 +37,11 @@
#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
/* setting reset address */
-#define CFG_RESET_ADDRESS TEXT_BASE
+/*#define CFG_RESET_ADDRESS TEXT_BASE*/
/* ethernet */
#define CONFIG_EMACLITE 1
-#define XPAR_EMAC_0_DEVICE_ID XPAR_XEMAC_NUM_INSTANCES
+#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
/* gpio */
#define CFG_GPIO_0 1
@@ -58,6 +59,10 @@
#define FREQUENCE XILINX_CLOCK_FREQ
#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
+/* FSL */
+#define CFG_FSL_2
+#define FSL_INTR_2 1
+
/*
* memory layout - Example
* TEXT_BASE = 0x1200_0000;
@@ -93,7 +98,8 @@
/* global pointer */
#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
-#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */
+/* start of global data */
+#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
/* monitor code */
#define SIZE 0x40000
@@ -117,6 +123,7 @@
#define CFG_FLASH_EMPTY_INFO 1 /* ?empty sector */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+ #define CFG_FLASH_PROTECTION /* hardware flash protection */
#ifdef RAMENV
#define CFG_ENV_IS_NOWHERE 1
@@ -135,6 +142,7 @@
#define CFG_ENV_IS_NOWHERE 1
#define CFG_ENV_SIZE 0x1000
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
+ #define CFG_FLASH_PROTECTION /* hardware flash protection */
#endif /* !FLASH */
#ifdef FLASH
@@ -152,8 +160,13 @@
CFG_CMD_IMI |\
CFG_CMD_NET |\
CFG_CMD_CACHE |\
+ CFG_CMD_FAT |\
+ CFG_CMD_EXT2 |\
+ CFG_CMD_JFFS2 |\
+ CFG_CMD_ECHO |\
CFG_CMD_IMLS |\
CFG_CMD_FLASH |\
+ CFG_CMD_MFSL |\
CFG_CMD_PING \
)
#else /* !RAMENV */
@@ -174,6 +187,11 @@
CFG_CMD_FLASH |\
CFG_CMD_PING |\
CFG_CMD_ENV |\
+ CFG_CMD_FAT |\
+ CFG_CMD_EXT2 |\
+ CFG_CMD_JFFS2 |\
+ CFG_CMD_ECHO |\
+ CFG_CMD_MFSL |\
CFG_CMD_SAVES \
)
@@ -189,16 +207,30 @@
CFG_CMD_BDI |\
CFG_CMD_RUN |\
CFG_CMD_LOADS |\
+ CFG_CMD_FAT |\
+ CFG_CMD_EXT2 |\
CFG_CMD_LOADB |\
CFG_CMD_IMI |\
CFG_CMD_NET |\
CFG_CMD_CACHE |\
+ CFG_CMD_MFSL |\
CFG_CMD_PING \
)
#endif /* !FLASH */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+/* JFFS2 partitions */
+#define CONFIG_JFFS2_CMDLINE /* mtdparts command line support */
+#define MTDIDS_DEFAULT "nor0=ml401-0"
+
+/* default mtd partition table */
+#define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\
+ "256k(env),3m(kernel),1m(romfs),"\
+ "1m(cramfs),-(jffs2)"
+#endif
+
/* Miscellaneous configurable options */
#define CFG_PROMPT "U-Boot-mONStR> "
#define CFG_CBSIZE 512 /* size of console buffer */
@@ -207,7 +239,7 @@
#define CFG_LONGHELP
#define CFG_LOAD_ADDR 0x12000000 /* default load address */
-#define CONFIG_BOOTDELAY 30
+#define CONFIG_BOOTDELAY 30
#define CONFIG_BOOTARGS "root=romfs"
#define CONFIG_HOSTNAME "ml401"
#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
@@ -221,10 +253,19 @@
#define CFG_HZ 1000
/* system ace */
-/*#define CONFIG_SYSTEMACE
-#define DEBUG_SYSTEMACE
-#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
-#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
-#define CONFIG_DOS_PARTITION
-*/
+#define CONFIG_SYSTEMACE
+/* #define DEBUG_SYSTEMACE */
+#define SYSTEMACE_CONFIG_FPGA
+#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
+#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo"
+
+#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\
+ "nor0=ml401-0\0"\
+ "mtdparts=mtdparts=ml401-0:"\
+ "256k(u-boot),256k(env),3m(kernel),"\
+ "1m(romfs),1m(cramfs),-(jffs2)\0"
+
#endif /* __CONFIG_H */
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 5328e8d..e6e0eb1 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -26,12 +26,10 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-
/*
* High Level Configuration Options
*/
-
/* CPU and board */
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
@@ -50,7 +48,13 @@
CFG_CMD_MII | \
CFG_CMD_BEDBUG | \
CFG_CMD_NET | \
- CFG_CMD_PING)
+ CFG_CMD_PING | \
+ CFG_CMD_IDE | \
+ CFG_CMD_FAT | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_I2C | \
+ CFG_CMD_DATE | \
+ CFG_CMD_EEPROM)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@@ -94,42 +98,50 @@
* Default environment settings
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
- "sdram_test=0\0" \
"netdev=eth0\0" \
"hostname=motionpro\0" \
"netmask=255.255.0.0\0" \
"ipaddr=192.168.160.22\0" \
"serverip=192.168.1.1\0" \
"gatewayip=192.168.1.1\0" \
- "kernel_addr=200000\0" \
+ "console=ttyPSC0,115200\0" \
"u-boot_addr=100000\0" \
- "kernel_sector=20\0" \
- "kernel_size=1000\0" \
- "console=ttyS0,115200\0" \
+ "kernel_addr=200000\0" \
+ "fdt_addr=400000\0" \
+ "ramdisk_addr=500000\0" \
+ "multi_image_addr=800000\0" \
"rootpath=/opt/eldk-4.1/ppc_6xx\0" \
- "bootfile=/tftpboot/motionpro/uImage\0" \
"u-boot=/tftpboot/motionpro/u-boot.bin\0" \
+ "bootfile=/tftpboot/motionpro/uImage\0" \
+ "fdt_file=/tftpboot/motionpro/motionpro.dtb\0" \
+ "ramdisk_file=/tftpboot/motionpro/uRamdisk\0" \
+ "multi_image_file=kernel+initrd+dtb.img\0" \
"load=tftp $(u-boot_addr) $(u-boot)\0" \
"update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; " \
"cp.b $(u-boot_addr) fff00000 $(filesize);" \
"prot on fff00000 fff3ffff\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) console=$(console) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):" \
- "$(netmask):$(hostname):$(netdev):off panic=1\0" \
- "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
- "flash_self=run ramargs addip;bootm $(kernel_addr) " \
- "$(ramdisk_addr)\0" \
- "net_nfs=tftp $(kernel_addr) $(bootfile); run nfsargs addip; " \
- "bootm $(kernel_addr)\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
- "fstype=ext3\0" \
- "fatargs=setenv bootargs init=/linuxrc rw\0" \
+ "fat_args=setenv bootargs rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):" \
+ "$(netmask):$(hostname):$(netdev):off panic=1 " \
+ "console=$(console)\0" \
+ "net_nfs=tftp $(kernel_addr) $(bootfile); " \
+ "tftp $(fdt_addr) $(fdt_file); run nfsargs addip; " \
+ "bootm $(kernel_addr) - $(fdt_addr)\0" \
+ "net_self=tftp $(kernel_addr) $(bootfile); " \
+ "tftp $(fdt_addr) $(fdt_file); " \
+ "tftp $(ramdisk_addr) $(ramdisk_file); " \
+ "run ramargs addip; " \
+ "bootm $(kernel_addr) $(ramdisk_addr) $(fdt_addr)\0" \
+ "fat_multi=run fat_args addip; fatload ide 0:1 " \
+ "${multi_image_addr} ${multi_image_file}; " \
+ "bootm ${multi_image_addr}\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
-
/*
* do board-specific init
*/
@@ -148,6 +160,12 @@
/*
+ * Set IPB speed to 100MHz (yes, the #define is misnamed)
+ */
+#define CFG_IPBSPEED_133
+
+
+/*
* Memory map
*/
/*
@@ -243,6 +261,53 @@
#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
#define CONFIG_FLASH_16BIT /* Flash is 16-bit */
+/*
+ * MTD configuration
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=motionpro-0"
+#define MTDPARTS_DEFAULT "mtdparts=motionpro-0:" \
+ "13m(fs),2m(kernel),256k(uboot)," \
+ "64k(env),64k(dtb),-(user_data)"
+
+/*
+ * IDE/ATA configuration
+ */
+#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
+#define CFG_IDE_MAXBUS 1
+#define CFG_IDE_MAXDEVICE 1
+#define CONFIG_IDE_PREINIT
+
+#define CFG_ATA_DATA_OFFSET 0x0060
+#define CFG_ATA_REG_OFFSET CFG_ATA_DATA_OFFSET
+#define CFG_ATA_STRIDE 4
+#define CONFIG_DOS_PARTITION
+
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CFG_I2C_MODULE 2 /* select I2C module #2 */
+#define CFG_I2C_SPEED 100000 /* 100 kHz */
+#define CFG_I2C_SLAVE 0x7F
+
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
+#define CFG_I2C_MULTI_EEPROMS 1 /* 2 EEPROMs (addr:50,52) */
+
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_DS1337 1
+#define CFG_I2C_RTC_ADDR 0x68
+
/*
* Environment settings
@@ -302,4 +367,15 @@
/* Not needed for MPC 5xxx U-Boot, but used by tools/updater */
#define CFG_RESET_ADDRESS 0xfff00100
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+#define OF_CPU "PowerPC,5200@0"
+#define OF_SOC "soc5200@f0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PAT "/soc5200@f0000000/serial@2000"
+
#endif /* __CONFIG_H */
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 1f19621..b7f79c2 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -38,7 +38,9 @@
#define CONFIG_440GRX 1 /* Specific PPC440GRx */
#endif
#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_SYS_CLK_FREQ 33000000 /* external freq to pll */
+/* Detect Sequoia PLL input clock automatically via CPLD bit */
+#define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
+ 3333333 : 33000000)
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
new file mode 100644
index 0000000..8624f4b
--- /dev/null
+++ b/include/configs/stxssa.h
@@ -0,0 +1,465 @@
+/*
+ * (C) Copyright 2005 Embedded Alley Solutions, Inc.
+ * Dan Malek <dan@embeddedalley.com>
+ * Copied from STx GP3.
+ * Updates for Silicon Tx GP3 SSA board.
+ *
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* mpc8560ads board configuration file */
+/* please refer to doc/README.mpc85xx for more info */
+/* make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
+#define CONFIG_CPM2 1 /* has CPM2 */
+#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
+
+#undef CONFIG_PCI /* pci ethernet support */
+#define CONFIG_TSEC_ENET /* tsec ethernet support*/
+#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+#undef CONFIG_DDR_DLL /* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+
+
+/* sysclk for MPC85xx
+ */
+
+#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
+
+/* Blinkin' LEDs for Robert :-)
+*/
+#define CONFIG_SHOW_ACTIVITY 1
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00200000 /* memtest region */
+#define CFG_MEMTEST_END 0x00400000
+
+
+/* Localbus connector. There are many options that can be
+ * connected here, including sdram or lots of flash.
+ * This address, however, is used to configure a 256M local bus
+ * window that includes the Config latch below.
+ */
+#define CFG_LBC_OPTION_BASE 0xf0000000 /* Localbus Extension */
+#define CFG_LBC_OPTION_SIZE 256 /* 256MB */
+
+/* There are various flash options used, we configure for the largest,
+ * which is 64Mbytes. The CFI works fine and will discover the proper
+ * sizes.
+ */
+#define CFG_FLASH_BASE 0xFC000000 /* start of FLASH 64M */
+#define CFG_BR0_PRELIM 0xFC001801 /* port size 32bit */
+#define CFG_OR0_PRELIM 0xFC000FF7 /* 64 MB Flash */
+
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+
+#define CFG_FLASH_PROTECTION
+
+/* The configuration latch is Chip Select 1.
+ * It's an 8-bit latch in the lower 8 bits of the word.
+ */
+#define CFG_LBC_CFGLATCH_BASE 0xfb000000 /* Base of config latch */
+#define CFG_BR1_PRELIM 0xfb001801 /* 32-bit port */
+#define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
+
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+#ifdef CFG_RAMBOOT
+#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
+#else
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#endif
+#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+
+
+/*
+ * DDR Setup
+ */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+
+#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/* local bus definitions */
+#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
+#define CFG_OR2_PRELIM 0xfc006901
+#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
+#define CFG_LBC_LBCR 0x00000000
+#define CFG_LBC_LSRT 0x20000000
+#define CFG_LBC_MRTPR 0x20000000
+#define CFG_LBC_LSDMR_1 0x2861b723
+#define CFG_LBC_LSDMR_2 0x0861b723
+#define CFG_LBC_LSDMR_3 0x0861b723
+#define CFG_LBC_LSDMR_4 0x1861b723
+#define CFG_LBC_LSDMR_5 0x4061b723
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 2
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#if 0
+#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */
+#else
+/* I did the 'if 0' so we could keep the syntax above if ever needed. */
+#undef CFG_I2C_NOPROBES
+#endif
+#define CFG_I2C_OFFSET 0x3000
+
+/* I2C EEPROM. AT24C32, we keep our environment in here.
+*/
+#define CFG_I2C_EEPROM_ADDR 0x51 /* 1010001x */
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+
+/*
+ * Standard 8555 PCI mapping.
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xe2000000
+#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */
+
+#define CFG_PCI2_MEM_BASE 0xa0000000
+#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI2_IO_BASE 0x00000000
+#define CFG_PCI2_IO_PHYS 0xe3000000
+#define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */
+
+#if defined(CONFIG_PCI) /* PCI Ethernet card */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xe0000000
+ #define PCI_ENET0_MEMADDR 0xe0000000
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW
+#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+#define CONFIG_MII 1 /* MII PHY management */
+
+#define CONFIG_MPC85XX_TSEC1 1
+#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
+#define CONFIG_MPC85XX_TSEC2 1
+#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
+#undef CONFIG_MPS85XX_FEC
+
+#define TSEC1_PHY_ADDR 2
+#define TSEC2_PHY_ADDR 4
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define CONFIG_ETHPRIME "TSEC0"
+
+#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
+
+#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
+#undef CONFIG_ETHER_NONE /* define if ether on something else */
+#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
+
+#if (CONFIG_ETHER_INDEX == 2)
+ /*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - Select bus for bd/buffers
+ * - Full duplex
+ */
+ #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+ #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+ #define CFG_CPMFCR_RAMTYPE 0
+#if 0
+ #define CFG_FCC_PSMR (FCC_PSMR_FDE)
+#else
+ #define CFG_FCC_PSMR 0
+#endif
+ #define FETH2_RST 0x01
+#elif (CONFIG_ETHER_INDEX == 3)
+ /* need more definitions here for FE3 */
+ #define FETH3_RST 0x80
+#endif /* CONFIG_ETHER_INDEX */
+
+/* MDIO is done through the TSEC0 control.
+*/
+#define CONFIG_MII /* MII PHY management */
+#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
+
+#endif
+
+/* Environment - default config is in flash, see below */
+#if 0 /* in EEPROM */
+#define CFG_ENV_IS_IN_EEPROM 1
+#define CFG_ENV_OFFSET 0
+#define CFG_ENV_SIZE 2048
+#else /* in flash */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SECT_SIZE 0x40000
+
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_TIMESTAMP /* Print image info with ts */
+
+#if defined(CFG_RAMBOOT)
+ #if defined(CONFIG_PCI)
+ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
+ CFG_CMD_PING | CFG_CMD_I2C) & \
+ ~(CFG_CMD_ENV | \
+ CFG_CMD_LOADS ))
+ #elif defined(CONFIG_TSEC_ENET)
+ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \
+ CFG_CMD_MII | CFG_CMD_I2C ) & \
+ ~(CFG_CMD_ENV))
+ #elif defined(CONFIG_ETHER_ON_FCC)
+ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
+ CFG_CMD_PING | CFG_CMD_I2C) & \
+ ~(CFG_CMD_ENV))
+ #endif
+#else
+ #if defined(CONFIG_PCI)
+ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
+ CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
+ #elif defined(CONFIG_TSEC_ENET)
+ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \
+ CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C)
+ #elif defined(CONFIG_ETHER_ON_FCC)
+ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
+ CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
+ #endif
+#endif
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "SSA=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x1000000 /* default load address */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*Note: change below for your network setting!!! */
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
+#endif
+
+/*
+ * Environment in EEPROM is compatible with different flash sector sizes,
+ * but only little space is available, so we use a very simple setup.
+ * With environment in flash, we use a more powerful default configuration.
+ */
+#ifdef CFG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */
+
+#define CONFIG_BAUDRATE 38400
+
+#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
+#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
+#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
+#define CONFIG_SERVERIP 192.168.85.1
+#define CONFIG_IPADDR 192.168.85.60
+#define CONFIG_GATEWAYIP 192.168.85.1
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_HOSTNAME STX_SSA
+#define CONFIG_ROOTPATH /gppproot
+#define CONFIG_BOOTFILE uImage
+#define CONFIG_LOADADDR 0x1000000
+
+#else /* ENV IS IN FLASH -- use a full-blown envionment */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hostname=gp3ssa\0" \
+ "bootfile=/tftpboot/gp3ssa/uImage\0" \
+ "loadaddr=400000\0" \
+ "netdev=eth0\0" \
+ "consdev=ttyS1\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $bootargs " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
+ ":$hostname:$netdev:off panic=1\0" \
+ "addcons=setenv bootargs $bootargs " \
+ "console=$consdev,$baudrate\0" \
+ "flash_nfs=run nfsargs addip addcons;" \
+ "bootm $kernel_addr\0" \
+ "flash_self=run ramargs addip addcons;" \
+ "bootm $kernel_addr $ramdisk_addr\0" \
+ "net_nfs=tftp $loadaddr $bootfile;" \
+ "run nfsargs addip addcons;bootm\0" \
+ "rootpath=/opt/eldk/ppc_85xx\0" \
+ "kernel_addr=FC000000\0" \
+ "ramdisk_addr=FC200000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#endif /* CFG_ENV_IS_IN_EEPROM */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h
index a2f4810..b4c720d 100644
--- a/include/configs/xupv2p.h
+++ b/include/configs/xupv2p.h
@@ -132,6 +132,8 @@
CFG_CMD_LOADS |\
CFG_CMD_LOADB |\
CFG_CMD_MISC |\
+ CFG_CMD_FAT |\
+ CFG_CMD_EXT2 |\
CFG_CMD_PING \
)
@@ -163,12 +165,12 @@
"base 0;" \
"echo"
-
/* system ace */
-/*#define CONFIG_SYSTEMACE
-#define DEBUG_SYSTEMACE
-#define CFG_SYSTEMACE_BASE 0xCF000000
-#define CFG_SYSTEMACE_WIDTH 16
-#define CONFIG_DOS_PARTITION*/
+#define CONFIG_SYSTEMACE
+/* #define DEBUG_SYSTEMACE */
+#define SYSTEMACE_CONFIG_FPGA
+#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
+#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
+#define CONFIG_DOS_PARTITION
#endif /* __CONFIG_H */
diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h
index c6aa8ec..1e8ed7a 100644
--- a/include/configs/zylonite.h
+++ b/include/configs/zylonite.h
@@ -174,7 +174,6 @@
/*
* NAND Flash
*/
-/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
#define CONFIG_NEW_NAND_CODE
#define CFG_NAND0_BASE 0x0
#undef CFG_NAND1_BASE
diff --git a/include/linux/stat.h b/include/linux/stat.h
index 43fd53f..37f2924 100644
--- a/include/linux/stat.h
+++ b/include/linux/stat.h
@@ -67,7 +67,8 @@ struct stat {
#endif /* __PPC__ */
-#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__)
+#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__) ||\
+ defined (__microblaze__)
struct stat {
unsigned short st_dev;
diff --git a/include/mpc86xx.h b/include/mpc86xx.h
index bc8ba3f..673bfed 100644
--- a/include/mpc86xx.h
+++ b/include/mpc86xx.h
@@ -9,6 +9,15 @@
#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */
+
+/*
+ * platform register addresses
+ */
+
+#define GUTS_SVR (CFG_CCSRBAR + 0xE00A4)
+#define MCM_ABCR (CFG_CCSRBAR + 0x01000)
+#define MCM_DBCR (CFG_CCSRBAR + 0x01008)
+
/*
* l2cr values. Look in config_<BOARD>.h for the actual setup
*/
generated by cgit v1.1 at 2024-12-11 10:47:36 +0000