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-rw-r--r--include/bootstage.h5
-rw-r--r--include/configs/galileo.h60
-rw-r--r--include/configs/minnowmax.h72
-rw-r--r--include/configs/x86-common.h4
-rw-r--r--include/dt-bindings/mrc/quark.h83
-rw-r--r--include/fdtdec.h1
-rw-r--r--include/mmc.h14
-rw-r--r--include/pci.h3
-rw-r--r--include/pci_ids.h9
-rw-r--r--include/pci_rom.h15
10 files changed, 259 insertions, 7 deletions
diff --git a/include/bootstage.h b/include/bootstage.h
index df13ab2..0276cb3 100644
--- a/include/bootstage.h
+++ b/include/bootstage.h
@@ -86,9 +86,9 @@ enum bootstage_id {
BOOTSTAGE_ID_POST_FAIL_R, /* Post failure reported after reloc */
/*
- * This set is reported ony by x86, and the meaning is different. In
+ * This set is reported only by x86, and the meaning is different. In
* this case we are reporting completion of a particular stage.
- * This should probably change in he x86 code (which doesn't report
+ * This should probably change in the x86 code (which doesn't report
* errors in any case), but discussion this can perhaps wait until we
* have a generic board implementation.
*/
@@ -194,6 +194,7 @@ enum bootstage_id {
BOOTSTAGE_ID_MAIN_CPU_READY,
BOOTSTAGE_ID_ACCUM_LCD,
+ BOOTSTAGE_ID_ACCUM_SCSI,
/* a few spare for the user, from here */
BOOTSTAGE_ID_USER,
diff --git a/include/configs/galileo.h b/include/configs/galileo.h
new file mode 100644
index 0000000..d745f4e
--- /dev/null
+++ b/include/configs/galileo.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN (1 << 20)
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_X86_SERIAL
+
+/* ns16550 UART is memory-mapped in Quark SoC */
+#undef CONFIG_SYS_NS16550_PORT_MAPPED
+
+#define CONFIG_PCI_MEM_BUS 0x90000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x20000000
+
+#define CONFIG_PCI_PREF_BUS 0xb0000000
+#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS
+#define CONFIG_PCI_PREF_SIZE 0x20000000
+
+#define CONFIG_PCI_IO_BUS 0x2000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0xe000
+
+#define CONFIG_SYS_EARLY_PCI_INIT
+#define CONFIG_PCI_PNP
+
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+
+/* SATA is not supported in Quark SoC */
+#undef CONFIG_SCSI_AHCI
+#undef CONFIG_CMD_SCSI
+
+/* Video is not supported in Quark SoC */
+#undef CONFIG_VIDEO
+#undef CONFIG_CFB_CONSOLE
+
+/* SD/MMC support */
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SDMA
+#define CONFIG_CMD_MMC
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
new file mode 100644
index 0000000..823e051
--- /dev/null
+++ b/include/configs/minnowmax.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN (1 << 20)
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_X86_SERIAL
+#define CONFIG_SMSC_LPC47M
+
+#define CONFIG_PCI_MEM_BUS 0xd0000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x10000000
+
+#define CONFIG_PCI_PREF_BUS 0xc0000000
+#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS
+#define CONFIG_PCI_PREF_SIZE 0x10000000
+
+#define CONFIG_PCI_IO_BUS 0x2000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0xe000
+
+#define CONFIG_SYS_EARLY_PCI_INIT
+#define CONFIG_PCI_PNP
+#define CONFIG_RTL8169
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
+ "stdout=vga,serial\0" \
+ "stderr=vga,serial\0"
+
+#define CONFIG_SCSI_DEV_LIST \
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}
+#define CONFIG_SPI_FLASH_SST
+
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SDMA
+#define CONFIG_CMD_MMC
+
+#undef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+#define CONFIG_X86_OPTION_ROM_FILE vga.bin
+#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000
+
+#ifndef CONFIG_SYS_COREBOOT
+#define CONFIG_VIDEO_VESA
+#endif
+#define VIDEO_IO_OFFSET 0
+#define CONFIG_X86EMU_RAW_IO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+
+#define CONFIG_FIT_SIGNATURE
+#define CONFIG_RSA
+
+/* Avoid a warning in the Realtek Ethernet driver */
+#define CONFIG_SYS_CACHELINE_SIZE 16
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index ecedfc3..062e6c2 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -39,7 +39,6 @@
/* SATA AHCI storage */
#define CONFIG_SCSI_AHCI
-#define CONFIG_SATA_INTEL
#ifdef CONFIG_SCSI_AHCI
#define CONFIG_LIBATA
#define CONFIG_SYS_64BIT_LBA
@@ -245,6 +244,9 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTSTAGE
+#define CONFIG_CMD_BOOTSTAGE
+
#define CONFIG_CMD_USB
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/dt-bindings/mrc/quark.h b/include/dt-bindings/mrc/quark.h
new file mode 100644
index 0000000..e3ca8a2
--- /dev/null
+++ b/include/dt-bindings/mrc/quark.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Intel Quark MRC bindings include several properties
+ * as part of an Intel Quark MRC node. In most cases,
+ * the value of these properties uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_QRK_MRC_H_
+#define _DT_BINDINGS_QRK_MRC_H_
+
+/* MRC platform data flags */
+#define MRC_FLAG_ECC_EN 0x00000001
+#define MRC_FLAG_SCRAMBLE_EN 0x00000002
+#define MRC_FLAG_MEMTEST_EN 0x00000004
+/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
+#define MRC_FLAG_TOP_TREE_EN 0x00000008
+/* If set ODR signal is asserted to DRAM devices on writes */
+#define MRC_FLAG_WR_ODT_EN 0x00000010
+
+/* DRAM width */
+#define DRAM_WIDTH_X8 0
+#define DRAM_WIDTH_X16 1
+#define DRAM_WIDTH_X32 2
+
+/* DRAM speed */
+#define DRAM_FREQ_800 0
+#define DRAM_FREQ_1066 1
+
+/* DRAM type */
+#define DRAM_TYPE_DDR3 0
+#define DRAM_TYPE_DDR3L 1
+
+/* DRAM rank mask */
+#define DRAM_RANK(n) (1 << (n))
+
+/* DRAM channel mask */
+#define DRAM_CHANNEL(n) (1 << (n))
+
+/* DRAM channel width */
+#define DRAM_CHANNEL_WIDTH_X8 0
+#define DRAM_CHANNEL_WIDTH_X16 1
+#define DRAM_CHANNEL_WIDTH_X32 2
+
+/* DRAM address mode */
+#define DRAM_ADDR_MODE0 0
+#define DRAM_ADDR_MODE1 1
+#define DRAM_ADDR_MODE2 2
+
+/* DRAM refresh rate */
+#define DRAM_REFRESH_RATE_195US 1
+#define DRAM_REFRESH_RATE_39US 2
+#define DRAM_REFRESH_RATE_785US 3
+
+/* DRAM SR temprature range */
+#define DRAM_SRT_RANGE_NORMAL 0
+#define DRAM_SRT_RANGE_EXTENDED 1
+
+/* DRAM ron value */
+#define DRAM_RON_34OHM 0
+#define DRAM_RON_40OHM 1
+
+/* DRAM rtt nom value */
+#define DRAM_RTT_NOM_40OHM 0
+#define DRAM_RTT_NOM_60OHM 1
+#define DRAM_RTT_NOM_120OHM 2
+
+/* DRAM rd odt value */
+#define DRAM_RD_ODT_OFF 0
+#define DRAM_RD_ODT_60OHM 1
+#define DRAM_RD_ODT_120OHM 2
+#define DRAM_RD_ODT_180OHM 3
+
+/* DRAM density */
+#define DRAM_DENSITY_512M 0
+#define DRAM_DENSITY_1G 1
+#define DRAM_DENSITY_2G 2
+#define DRAM_DENSITY_4G 3
+
+#endif /* _DT_BINDINGS_QRK_MRC_H_ */
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 231eed7..1bc70db 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -167,6 +167,7 @@ enum fdt_compat_id {
COMPAT_INTEL_GMA, /* Intel Graphics Media Accelerator */
COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */
COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */
+ COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */
COMPAT_COUNT,
};
diff --git a/include/mmc.h b/include/mmc.h
index 09101e2..56d97bb 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -438,6 +438,20 @@ int board_mmc_init(bd_t *bis);
int cpu_mmc_init(bd_t *bis);
int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
+struct pci_device_id;
+
+/**
+ * pci_mmc_init() - set up PCI MMC devices
+ *
+ * This finds all the matching PCI IDs and sets them up as MMC devices.
+ *
+ * @name: Name to use for devices
+ * @mmc_supported: PCI IDs to search for
+ * @num_ids: Number of elements in @mmc_supported
+ */
+int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported,
+ int num_ids);
+
/* Set block count limit because of 16 bit register limit on some hardware*/
#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
diff --git a/include/pci.h b/include/pci.h
index 4fbb8f6..004a048 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -644,8 +644,7 @@ extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
-extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
- int wanted_prog_if, int index);
+pci_dev_t pci_find_class(unsigned int find_class, int index);
extern int pci_hose_config_device(struct pci_controller *hose,
pci_dev_t dev,
diff --git a/include/pci_ids.h b/include/pci_ids.h
index 26f4748..dc2ca21 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -1346,6 +1346,7 @@
#define PCI_VENDOR_ID_REALTEK 0x10ec
#define PCI_DEVICE_ID_REALTEK_8139 0x8139
+#define PCI_DEVICE_ID_REALTEK_8168 0x8168
#define PCI_VENDOR_ID_XILINX 0x10ee
#define PCI_DEVICE_ID_RME_DIGI96 0x3fc0
@@ -2591,9 +2592,17 @@
#define PCI_DEVICE_ID_INTEL_MFD_EMMC0 0x0823
#define PCI_DEVICE_ID_INTEL_MFD_EMMC1 0x0824
#define PCI_DEVICE_ID_INTEL_MRST_SD2 0x084F
+#define PCI_DEVICE_ID_INTEL_QRK_SDIO 0x08A7
+#define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
+#define PCI_DEVICE_ID_INTEL_QRK_EMAC 0x0937
+#define PCI_DEVICE_ID_INTEL_QRK_ILB 0x095E
#define PCI_DEVICE_ID_INTEL_I960 0x0960
#define PCI_DEVICE_ID_INTEL_I960RM 0x0962
#define PCI_DEVICE_ID_INTEL_CENTERTON_ILB 0x0c60
+#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO 0x0f15
+#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD 0x0f16
+#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC 0x0f1c
+#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA 0x0f23
#define PCI_DEVICE_ID_INTEL_82541ER 0x1078
#define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c
#define PCI_DEVICE_ID_INTEL_82542 0x1000
diff --git a/include/pci_rom.h b/include/pci_rom.h
index 4ba36eb..2f1665d 100644
--- a/include/pci_rom.h
+++ b/include/pci_rom.h
@@ -33,14 +33,25 @@ struct pci_rom_data {
uint16_t reserved_2;
};
+/*
+ * Determines which execution method is used and whether we allow falling back
+ * to the other if the requested method is not available.
+ */
+enum pci_rom_emul {
+ PCI_ROM_EMULATE = 0 << 0,
+ PCI_ROM_USE_NATIVE = 1 << 0,
+ PCI_ROM_ALLOW_FALLBACK = 1 << 1,
+};
+
/**
* pci_run_vga_bios() - Run the VGA BIOS in an x86 PC
*
* @dev: Video device containing the BIOS
* @int15_handler: Function to call to handle int 0x15
- * @emulate: true to use the x86 emulator, false to run native
+ * @exec_method: flags from enum pci_rom_emul
*/
-int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate);
+int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void),
+ int exec_method);
/**
* board_map_oprom_vendev() - map several PCI IDs to the one the ROM expects