diff options
Diffstat (limited to 'include')
71 files changed, 1278 insertions, 805 deletions
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index c19e16c..23c9649 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -94,4 +94,13 @@ int gpio_get_value(unsigned gpio); */ int gpio_set_value(unsigned gpio, int value); +/** + * Request a gpio. This should be called before any of the other functions + * are used on this gpio. + * + * @param gp GPIO number + * @param label User label for this GPIO + * @return 0 if ok, -1 on error + */ +int gpio_request(unsigned gpio, const char *label); #endif /* _ASM_GENERIC_GPIO_H_ */ diff --git a/include/command.h b/include/command.h index 6e1bdc2..1f06aa1 100644 --- a/include/command.h +++ b/include/command.h @@ -110,6 +110,10 @@ static inline int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd) return 0; } #endif + +extern int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc, + char *const argv[]); + extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); /* diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 0d09f0e..45d1064 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -1,7 +1,7 @@ /* * Configuation settings for the Freescale MCF5373 FireEngine board. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -59,7 +59,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO -#ifdef NANDFLASH_SIZE +#ifdef CONFIG_NANDFLASH_SIZE # define CONFIG_CMD_NAND #endif @@ -208,7 +208,7 @@ # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ #endif -#ifdef NANDFLASH_SIZE +#ifdef CONFIG_NANDFLASH_SIZE # define CONFIG_SYS_MAX_NAND_DEVICE 1 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE # define CONFIG_SYS_NAND_SIZE 1 @@ -264,9 +264,9 @@ #define CONFIG_SYS_CS1_MASK 0x001f0001 #define CONFIG_SYS_CS1_CTRL 0x002A3780 -#ifdef NANDFLASH_SIZE +#ifdef CONFIG_NANDFLASH_SIZE #define CONFIG_SYS_CS2_BASE 0x20000000 -#define CONFIG_SYS_CS2_MASK ((NANDFLASH_SIZE << 20) | 1) +#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) #define CONFIG_SYS_CS2_CTRL 0x00001f60 #endif diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 7f2761c..2d48dde 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -37,6 +37,24 @@ #define CONFIG_MISC_INIT_R +/* new uImage format support */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 + +#define CONFIG_MMC 1 + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ESDHC_USE_PIO + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + /* * On-board devices * @@ -340,6 +358,19 @@ #define CONFIG_SYS_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C2_OFFSET 0x3100 +/* + * SPI on header J8 + * + * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch) + * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins. + */ +#ifdef CONFIG_MPC8XXX_SPI +#define CONFIG_CMD_SPI +#define CONFIG_USE_SPIFLASH +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#endif /* * Board info - revision and where boot from diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 1c0eb74..3169665 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -22,7 +22,7 @@ /* * P2041 RDB board configuration file - * + * Also supports P2040 RDB */ #ifndef __CONFIG_H #define __CONFIG_H @@ -36,6 +36,15 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +/* Set 1M boot space */ +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_NO_FLASH +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ @@ -73,7 +82,7 @@ #define CONFIG_ENV_OVERWRITE #ifdef CONFIG_SYS_NO_FLASH -#ifndef CONFIG_RAMBOOT_PBL +#if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_NOWHERE #endif #else @@ -104,8 +113,12 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +#define CONFIG_ENV_IS_IN_REMOTE +#define CONFIG_ENV_ADDR 0xffe20000 +#define CONFIG_ENV_SIZE 0x2000 #elif defined(CONFIG_ENV_IS_NOWHERE) - #define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SIZE 0x2000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ @@ -374,6 +387,35 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ /* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull +/* + * for slave UCODE and ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ + +/* slave core release by master*/ +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ + +/* + * SRIO_PCIE_BOOT - SLAVE + */ +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#endif + +/* * eSPI - Enhanced SPI */ #define CONFIG_FSL_ESPI @@ -485,6 +527,16 @@ unsigned long get_board_sys_clk(unsigned long dummy); #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO or PCIE outbound window->master inbound window-> + * master LAW->the ucode address in master's memory space. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 diff --git a/include/configs/P3060QDS.h b/include/configs/P3060QDS.h deleted file mode 100644 index 8006547..0000000 --- a/include/configs/P3060QDS.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * P3060 QDS board configuration file - */ -#define CONFIG_P3060QDS -#define CONFIG_PHYS_64BIT -#define CONFIG_PPC_P3060 -#define CONFIG_FSL_QIXIS - -#define CONFIG_NAND_FSL_ELBC - -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ - -#define CONFIG_SPI_FLASH_ATMEL -#define CONFIG_SPI_FLASH_EON -#define CONFIG_SPI_FLASH_SST - -#include "corenet_ds.h" - -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F - -/* There is a PCA9547 8-channel I2C-bus multiplexer on P3060QDS board */ -#define CONFIG_I2C_MUX -#define CONFIG_I2C_MULTI_BUS diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 4a2e475..d6f2f5c 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -22,6 +22,7 @@ /* * P4080 DS board configuration file + * Also supports P4040 DS */ #define CONFIG_P4080DS #define CONFIG_PHYS_64BIT diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index 4afc4f1..8625f76 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -22,7 +22,7 @@ /* * P5020 DS board configuration file - * + * Also supports P5010 DS */ #define CONFIG_P5020DS #define CONFIG_PHYS_64BIT diff --git a/include/configs/apollon.h b/include/configs/apollon.h deleted file mode 100644 index b8ca8a8..0000000 --- a/include/configs/apollon.h +++ /dev/null @@ -1,261 +0,0 @@ -/* - * (C) Copyright 2005-2008 - * Samsung Electronics, - * Kyungmin Park <kyungmin.park@samsung.com> - * - * Configuration settings for the 2420 Samsung Apollon board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP2420 1 /* which is in a 2420 */ -#define CONFIG_OMAP2420_APOLLON 1 -#define CONFIG_APOLLON 1 -#define CONFIG_APOLLON_PLUS 1 /* If you have apollon plus 1.x */ - -#define CONFIG_ONENAND_U_BOOT y - -/* Clock config to target*/ -#define PRCM_CONFIG_I 1 -/* #define PRCM_CONFIG_II 1 */ - -/* Boot method */ -/* uncomment if you use NOR boot */ -/* #define CONFIG_SYS_NOR_BOOT 1 */ - -/* uncomment if you use NOR on CS3 */ -/* #define CONFIG_SYS_USE_NOR 1 */ - -#ifdef CONFIG_SYS_NOR_BOOT -#undef CONFIG_SYS_USE_NOR -#define CONFIG_SYS_USE_NOR 1 -#endif - -/* uncommnet if you want to use UBI */ -#define CONFIG_SYS_USE_UBI - -#include <asm/arch/omap2420.h> /* get chip and board defs */ - -#define V_SCLK 12000000 - -/* input clock of PLL */ -/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */ -#define CONFIG_SYS_CLK_FREQ V_SCLK - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */ -#define CONFIG_ENV_SIZE_FLEX SZ_256K -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_1M) - -/* - * Hardware drivers - */ - -/* - * SMC91c96 Etherent - */ -#define CONFIG_LAN91C96 -#define CONFIG_LAN91C96_BASE (APOLLON_CS1_BASE+0x300) -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */ -#define CONFIG_SYS_NS16550_COM1 OMAP2420_UART1 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* UART1 on H4 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ONENAND - -#ifdef CONFIG_SYS_USE_UBI -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_UBI -#define CONFIG_RBTREE -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_MTD_PARTITIONS -#endif - -#undef CONFIG_CMD_SOURCE - -#ifndef CONFIG_SYS_USE_NOR -# undef CONFIG_CMD_FLASH -# undef CONFIG_CMD_IMLS -#endif - -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT - -#define CONFIG_BOOTDELAY 1 - -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.116.25 -#define CONFIG_SERVERIP 192.168.116.1 -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_ETHADDR 00:0E:99:00:24:20 - -#ifdef CONFIG_APOLLON_PLUS -#define CONFIG_SYS_MEM "mem=64M" -#else -#define CONFIG_SYS_MEM "mem=128" -#endif - -#ifdef CONFIG_SYS_USE_UBI -#define CONFIG_SYS_UBI "ubi.mtd=4" -#else -#define CONFIG_SYS_UBI "" -#endif - -#define CONFIG_BOOTARGS "root=/dev/nfs rw " CONFIG_SYS_MEM \ - " console=ttyS0,115200n8" \ - " ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:" \ - "apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2 " \ - CONFIG_SYS_UBI - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "Image=tftp 0x80008000 Image; go 0x80008000\0" \ - "zImage=tftp 0x80180000 zImage; go 0x80180000\0" \ - "uImage=tftp 0x80180000 uImage; bootm 0x80180000\0" \ - "uboot=tftp 0x80008000 u-boot.bin; go 0x80008000\0" \ - "xloader=tftp 0x80180000 x-load.bin; " \ - " cp.w 0x80180000 0x00000400 0x1000; go 0x00000400\0" \ - "syncmode50=mw.w 0x1e442 0xc0c4; mw 0x6800a060 0xe30d1201\0" \ - "syncmode=mw.w 0x1e442 0xe0f4; mw 0x6800a060 0xe30d1201\0" \ - "norboot=cp32 0x18040000 0x80008000 0x200000; go 0x80008000\0" \ - "oneboot=onenand read 0x80008000 0x40000 0x200000; go 0x80008000\0" \ - "onesyncboot=run syncmode oneboot\0" \ - "updateb=tftp 0x80180000 u-boot-onenand.bin; " \ - " onenand erase 0x0 0x20000; onenand write 0x80180000 0x0 0x20000\0" \ - "ubi=setenv bootargs ${bootargs} ubi.mtd=4 ${mtdparts}; run uImage\0" \ - "bootcmd=run uboot\0" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "Apollon # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M) - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0) - -/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) - * or by 32KHz clk, or from external sig. This rate is divided by a local - * divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2 -#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_128M -#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#ifdef CONFIG_SYS_USE_NOR -/* OneNAND boot, NOR has CS3, But NOR has CS0 when NOR boot */ -# define CONFIG_SYS_FLASH_BASE 0x18000000 -# define CONFIG_SYS_MAX_FLASH_BANKS 1 -# define CONFIG_SYS_MAX_FLASH_SECT 1024 -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -/* Flash memory is CFI compliant */ -# define CONFIG_SYS_FLASH_CFI 1 -# define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ -/* Use buffered writes (~10x faster) */ -/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 */ -/* Use h/w sector protection*/ -# define CONFIG_SYS_FLASH_PROTECTION 1 - -#else /* !CONFIG_SYS_USE_NOR */ -# define CONFIG_SYS_NO_FLASH 1 -#endif /* CONFIG_SYS_USE_NOR */ - -/* OneNAND boot, OneNAND has CS0, NOR boot ONeNAND has CS2 */ -#define CONFIG_SYS_ONENAND_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN SZ_256K /* U-Boot image size */ -#define CONFIG_ENV_IS_IN_ONENAND 1 -#define CONFIG_ENV_ADDR 0x00020000 -#define CONFIG_ENV_ADDR_FLEX 0x00040000 - -#ifdef CONFIG_SYS_USE_UBI -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "onenand0=onenand" -#define MTDPARTS_DEFAULT "mtdparts=onenand:128k(bootloader)," \ - "128k(params)," \ - "2m(kernel)," \ - "16m(rootfs)," \ - "32m(fs)," \ - "-(ubifs)" -#endif - -#define PHYS_SRAM 0x4020F800 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM - -#endif /* __CONFIG_H */ diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h new file mode 100644 index 0000000..f85374f --- /dev/null +++ b/include/configs/atngw100mkii.h @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com> + * + * Configuration settings for the AVR32 Network Gateway + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/hardware.h> + +#define CONFIG_AVR32 +#define CONFIG_AT32AP +#define CONFIG_AT32AP7000 +#define CONFIG_ATNGW100MKII + +/* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency + */ +#define CONFIG_SYS_HZ 1000 + +/* + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency + * and the PBA bus to run at 1/4 the PLL frequency. + */ +#define CONFIG_PLL +#define CONFIG_SYS_POWER_MANAGER +#define CONFIG_SYS_OSC0_HZ 20000000 +#define CONFIG_SYS_PLL0_DIV 1 +#define CONFIG_SYS_PLL0_MUL 7 +#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 +/* + * Set the CPU running at: + * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz + */ +#define CONFIG_SYS_CLKDIV_CPU 0 +/* + * Set the HSB running at: + * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz + */ +#define CONFIG_SYS_CLKDIV_HSB 1 +/* + * Set the PBA running at: + * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz + */ +#define CONFIG_SYS_CLKDIV_PBA 2 +/* + * Set the PBB running at: + * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz + */ +#define CONFIG_SYS_CLKDIV_PBB 1 + +/* Reserve VM regions for NOR flash, NAND flash and SDRAM */ +#define CONFIG_SYS_NR_VM_REGIONS 3 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CONFIG_SYS_PLL0_OPT 0x04 + +#define CONFIG_USART_BASE ATMEL_BASE_USART1 +#define CONFIG_USART_ID 1 + +/* User serviceable stuff */ +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "root=mtd:main rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND \ + "fsload 0x10400000 /uImage; bootm" + +/* + * Only interrupt autoboot if <space> is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * After booting the board for the first time, new ethernet addresses + * should be generated and assigned to the environment variables + * "ethaddr" and "eth1addr". This is normally done during production. + */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_NET_MULTI + +/* + * BOOTP/DHCP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_MII + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#define CONFIG_ATMEL_USART +#define CONFIG_MACB +#define CONFIG_PORTMUX_PIO +#define CONFIG_SYS_NR_PIOS 5 +#define CONFIG_SYS_HSDRAMC +#define CONFIG_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#define CONFIG_GENERIC_MMC +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 +#define CONFIG_ATMEL_SPI + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL + +#define CONFIG_SYS_DCACHE_LINESZ 32 +#define CONFIG_SYS_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_PROTECTION + +#define CONFIG_SYS_FLASH_BASE 0x00000000 +#define CONFIG_SYS_FLASH_SIZE 0x800000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 135 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE +#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SIZE 65536 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) + +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#define CONFIG_SYS_DMA_ALLOC_LEN (16384) + +/* Allow 4MB for the kernel run-time image */ +#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) +#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) + +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS + +#endif /* __CONFIG_H */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index f8f7a82..f4f9bd1 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -31,13 +31,21 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg +#if defined(CONFIG_P3041DS) +#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg +#elif defined(CONFIG_P4080DS) +#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg +#elif defined(CONFIG_P5020DS) +#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg +#endif #endif -#ifdef CONFIG_SRIOBOOT_SLAVE +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_NO_FLASH #endif @@ -77,7 +85,7 @@ #define CONFIG_ENV_OVERWRITE #ifdef CONFIG_SYS_NO_FLASH -#if !defined(CONFIG_SRIOBOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) +#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) #define CONFIG_ENV_IS_NOWHERE #endif #else @@ -108,7 +116,7 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIOBOOT_SLAVE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 #define CONFIG_ENV_SIZE 0x2000 @@ -186,11 +194,7 @@ #define CONFIG_DDR_SPD #define CONFIG_FSL_DDR3 -#ifdef CONFIG_P3060QDS -#define CONFIG_SYS_SPD_BUS_NUM 0 -#else #define CONFIG_SYS_SPD_BUS_NUM 1 -#endif #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ @@ -389,51 +393,32 @@ #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ /* - * SRIOBOOT - MASTER - */ -#ifdef CONFIG_SRIOBOOT_MASTER -/* master port for srioboot*/ -#define CONFIG_SRIOBOOT_MASTER_PORT 0 -/* #define CONFIG_SRIOBOOT_MASTER_PORT 1 */ -/* * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 0xfef080000ull -#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 0xfff80000ull -#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000 /* 512K */ -#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull -#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull /* - * for slave UCODE instored in master memory space, + * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 0xfef020000ull -#define CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 0x3ffe00000ull -#define CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE 0x10000 /* 64K */ -/* - * for slave ENV instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 0xfef060000ull -#define CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 0x3ffe20000ull -#define CONFIG_SRIOBOOT_SLAVE_ENV_SIZE 0x20000 /* 128K */ +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ + /* slave core release by master*/ -#define CONFIG_SRIOBOOT_SLAVE_HOLDOFF -#define CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK 0x00000001 /* release core 0 */ -#endif +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ /* - * SRIOBOOT - SLAVE + * SRIO_PCIE_BOOT - SLAVE */ -#ifdef CONFIG_SRIOBOOT_SLAVE -/* slave port for srioboot */ -#define CONFIG_SRIOBOOT_SLAVE_PORT0 -/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */ -#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR) +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) #endif /* @@ -556,13 +541,13 @@ #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIOBOOT_SLAVE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing * in two corenet boards, slave's ucode could be stored in master's memory * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO outbound window->master inbound window->master LAW-> - * the ucode address in master's NOR flash. + * slave SRIO or PCIE outbound window->master inbound window-> + * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 @@ -724,7 +709,7 @@ #define CONFIG_BAUDRATE 115200 -#if defined(CONFIG_P4080DS) || defined(CONFIG_P3060QDS) +#ifdef CONFIG_P4080DS #define __USB_PHY_TYPE ulpi #else #define __USB_PHY_TYPE utmi diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h index d4104de..9371ec3 100644 --- a/include/configs/eb_cpux9k2.h +++ b/include/configs/eb_cpux9k2.h @@ -44,7 +44,12 @@ #define MACH_TYPE_EB_CPUX9K2 1977 #define CONFIG_MACH_TYPE MACH_TYPE_EB_CPUX9K2 /*--------------------------------------------------------------------------*/ -#define CONFIG_SYS_TEXT_BASE 0x00000000 +#ifndef CONFIG_RAMBOOT +#define CONFIG_SYS_TEXT_BASE 0x00000000 +#else +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_TEXT_BASE 0x21f00000 +#endif #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ #define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */ diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index f0fb488..f2cfaf8 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -69,13 +69,18 @@ * - GPIO16 is Power LED control (0 = on, 1 = off) * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) - * - Last GPIO is 26, further bits are supposed to be 0. + * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) + * - GPIO22 is SATA disk power status () + * - GPIO23 is supply status for SATA disk () + * - GPIO24 is supply control for board (write 1 to power off) + * Last GPIO is 25, further bits are supposed to be 0. * Enable mask has ones for INPUT, 0 for OUTPUT. - * Default is LED ON. + * Default is LED ON, board ON :) */ -#define ORION5X_GPIO_OUT_ENABLE 0x03fcffff -#define ORION5X_GPIO_OUT_VALUE 0x03fcffff +#define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca +#define ORION5X_GPIO_OUT_VALUE 0x00000000 +#define ORION5X_GPIO_IN_POLARITY 0x000000d0 /* * NS16550 Configuration diff --git a/include/configs/flea3.h b/include/configs/flea3.h index 4350518..46171b9 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -31,7 +31,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX35 -#define CONFIG_MX35_HCLK_FREQ 24000000 #define CONFIG_SYS_DCACHE_OFF #define CONFIG_SYS_CACHELINE_SIZE 32 @@ -213,7 +212,6 @@ * NAND FLASH driver setup */ #define CONFIG_NAND_MXC -#define CONFIG_NAND_MXC_V1_1 #define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) diff --git a/include/configs/harmony.h b/include/configs/harmony.h index d0555c1..e407ff4 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -34,15 +34,15 @@ /* High-level configuration options */ #define V_PROMPT "Tegra20 (Harmony) # " -#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Harmony" +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Harmony" /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA20_ENABLE_UARTD +#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: keyboard satellite board UART, default */ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#ifdef CONFIG_TEGRA20_ENABLE_UARTA +#ifdef CONFIG_TEGRA_ENABLE_UARTA /* UARTA: debug board UART */ #define CONFIG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE #endif @@ -62,8 +62,15 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT -/* Environment not stored */ -#define CONFIG_ENV_IS_NOWHERE +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_TEGRA_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE + +/* Environment in NAND (which is 512M), aligned to start of last sector */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */ /* USB Host support */ #define CONFIG_USB_EHCI @@ -80,6 +87,6 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP -#include "tegra20-common-post.h" +#include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h index 567061a..dbc59b9 100644 --- a/include/configs/ima3-mx53.h +++ b/include/configs/ima3-mx53.h @@ -64,7 +64,6 @@ /* Ethernet on FEC */ #define CONFIG_NET_MULTI #define CONFIG_MII -#define CONFIG_DISCOVER_PHY #define CONFIG_FEC_MXC #define IMX_FEC_BASE FEC_BASE_ADDR @@ -72,7 +71,7 @@ #define CONFIG_PHY_ADDR CONFIG_FEC_MXC_PHYADDR #define CONFIG_RESET_PHY_R #define CONFIG_FEC_MXC_NO_ANEG -#define CONFIG_PRIME "FEC0" +#define CONFIG_ETHPRIME "FEC0" /* SPI */ #define CONFIG_HARD_SPI diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 8cca478..6ae764a 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -33,7 +33,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ #define CONFIG_MX31 1 /* in a mx31 */ -#define CONFIG_MX31_HCLK_FREQ 26000000 #define CONFIG_MX31_CLK32 32000 #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index b21621c..f36ceea 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -33,7 +33,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX31 /* in a mx31 */ -#define CONFIG_MX31_HCLK_FREQ 26000000 #define CONFIG_MX31_CLK32 32000 #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h new file mode 100644 index 0000000..564b418 --- /dev/null +++ b/include/configs/integrator-common.h @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2012 + * Linaro + * Linus Walleij <linus.walleij@linaro.org> + * Common ARM Integrator configuration settings + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define CONFIG_INTEGRATOR + +#define CONFIG_SYS_TEXT_BASE 0x01000000 +#define CONFIG_SYS_MEMTEST_START 0x100000 +#define CONFIG_SYS_MEMTEST_END 0x10000000 +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ +#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size*/ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_MISC_INIT_R /* call misc_init_r during start up */ + +/* + * There are various dependencies on the core module (CM) fitted + * Users should refer to their CM user guide + */ +#include "armcoremodule.h" + +/* + * Initialize and remap the core module, use SPD to detect memory size + * If CONFIG_SKIP_LOWLEVEL_INIT is not defined & + * the core module has a CM_INIT register + * then the U-Boot initialisation code will + * e.g. ARM Boot Monitor or pre-loader is repeated once + * (to re-initialise any existing CM_INIT settings to safe values). + * + * This is usually not the desired behaviour since the platform + * will either reboot into the ARM monitor (or pre-loader) + * or continuously cycle thru it without U-Boot running, + * depending upon the setting of Integrator/CP switch S2-4. + * + * However it may be needed if Integrator/CP switch S2-1 + * is set OFF to boot direct into U-Boot. + * In that case comment out the line below. + */ +#define CONFIG_CM_INIT +#define CONFIG_CM_REMAP +#define CONFIG_CM_SPD_DETECT + +/* + * The ARM boot monitor initializes the board. + * However, the default U-Boot code also performs the initialization. + * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT + * - see documentation supplied with board for details of how to choose the + * image to run at reset/power up + * e.g. whether the ARM Boot Monitor runs before U-Boot + */ +/* #define CONFIG_SKIP_LOWLEVEL_INIT */ + +/* + * The ARM boot monitor does not relocate U-Boot. + * However, the default U-Boot code performs the relocation check, + * and may relocate the code if the memory map is changed. + * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT + */ +/* #define SKIP_CONFIG_RELOCATE_UBOOT */ + + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index 2770c82..c6907b5 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -31,32 +31,11 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_INTEGRATOR +#include "integrator-common.h" + +/* Integrator/AP-specific configuration */ #define CONFIG_ARCH_INTEGRATOR -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SYS_TEXT_BASE 0x01000000 -#define CONFIG_SYS_MEMTEST_START 0x100000 -#define CONFIG_SYS_MEMTEST_END 0x10000000 -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ -#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ - -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_CM_INIT 1 -#define CONFIG_CM_REMAP 1 -#define CONFIG_CM_SPD_DETECT - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* * PL010 Configuration @@ -90,29 +69,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "Integrator-AP # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_FLASH_BASE 0x24000000 diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index d5043df..ca02a6f 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -31,32 +31,11 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* Integrator-specific configuration */ -#define CONFIG_INTEGRATOR -#define CONFIG_ARCH_CINTEGRATOR -#define CONFIG_CM_INIT -#define CONFIG_CM_REMAP -#define CONFIG_CM_SPD_DETECT +#include "integrator-common.h" -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SYS_TEXT_BASE 0x01000000 -#define CONFIG_SYS_MEMTEST_START 0x100000 -#define CONFIG_SYS_MEMTEST_END 0x10000000 -#define CONFIG_SYS_HZ 1000 +/* Integrator CP-specific configuration */ +#define CONFIG_ARCH_CINTEGRATOR #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */ -#define CONFIG_SYS_TIMERBASE 0x13000100 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* * Hardware drivers @@ -66,9 +45,7 @@ #define CONFIG_SMC91111_BASE 0xC8000000 #undef CONFIG_SMC91111_EXT_PHY -/* - * NS16550 Configuration - */ +/* PL011 configuration */ #define CONFIG_PL011_SERIAL #define CONFIG_PL011_CLOCK 14745600 #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, (void *)CONFIG_SYS_SERIAL1 } @@ -77,16 +54,6 @@ #define CONFIG_SYS_SERIAL0 0x16000000 #define CONFIG_SYS_SERIAL1 0x17000000 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - /* * Command line configuration. */ @@ -102,32 +69,10 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_PROMPT "Integrator-CP # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size*/ -#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- +/* * FLASH and environment organization - * Top varies according to amount fitted * Reserve top 4 blocks of flash * - ARM Boot Monitor @@ -136,7 +81,6 @@ * - U-Boot environment * * Base is always 0x24000000 - */ #define CONFIG_SYS_FLASH_BASE 0x24000000 #define CONFIG_SYS_FLASH_CFI 1 @@ -178,53 +122,4 @@ #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ #define CONFIG_ENV_SIZE 8192 /* 8KB */ -/* - * The ARM boot monitor initializes the board. - * However, the default U-Boot code also performs the initialization. - * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT - * - see documentation supplied with board for details of how to choose the - * image to run at reset/power up - * e.g. whether the ARM Boot Monitor runs before U-Boot - -#define CONFIG_SKIP_LOWLEVEL_INIT - - */ - -/* - * The ARM boot monitor does not relocate U-Boot. - * However, the default U-Boot code performs the relocation check, - * and may relocate the code if the memory map is changed. - * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT - -#define SKIP_CONFIG_RELOCATE_UBOOT - - */ -/*----------------------------------------------------------------------- - * There are various dependencies on the core module (CM) fitted - * Users should refer to their CM user guide - * - when porting adjust u-boot/Makefile accordingly - * to define the necessary CONFIG_ s for the CM involved - * see e.g. cp_926ejs_config - */ - -#include "armcoremodule.h" - -/* - * If CONFIG_SKIP_LOWLEVEL_INIT is not defined & - * the core module has a CM_INIT register - * then the U-Boot initialisation code will - * e.g. ARM Boot Monitor or pre-loader is repeated once - * (to re-initialise any existing CM_INIT settings to safe values). - * - * This is usually not the desired behaviour since the platform - * will either reboot into the ARM monitor (or pre-loader) - * or continuously cycle thru it without U-Boot running, - * depending upon the setting of Integrator/CP switch S2-4. - * - * However it may be needed if Integrator/CP switch S2-1 - * is set OFF to boot direct into U-Boot. - * In that case comment out the line below. -#undef CONFIG_CM_INIT - */ - #endif /* __CONFIG_H */ diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 7ed9958..9983104 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -81,7 +81,6 @@ #define CONFIG_LOADS_ECHO #define CONFIG_SYS_LOADS_BAUD_CHANGE -#define CONFIG_SYS_BOARD_DRAM_INIT /* Used board specific dram_init */ #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_MAX_I2C_BUS 1 diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 27b77d3..44d5373 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -57,10 +57,14 @@ #define CONFIG_CMD_SF #define CONFIG_SOFT_I2C /* I2C bit-banged */ +/* SPI NOR Flash default params, used by sf commands */ +#define CONFIG_SF_DEFAULT_SPEED 8100000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 + #if defined CONFIG_KM_ENV_IS_IN_SPI_NOR #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 5000000 +#define CONFIG_ENV_SPI_MAX_HZ 8100000 #define CONFIG_ENV_SPI_MODE SPI_MODE_3 #endif diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index d0f2b48..9eb2a54 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -171,9 +171,9 @@ #define CONFIG_LZO #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define MTDIDS_DEFAULT "nand0=gpmi-nand.0" +#define MTDIDS_DEFAULT "nand0=gpmi-nand" #define MTDPARTS_DEFAULT \ - "mtdparts=gpmi-nand.0:" \ + "mtdparts=gpmi-nand:" \ "3m(bootloader)ro," \ "512k(environment)," \ "512k(redundant-environment)," \ diff --git a/include/configs/medcom.h b/include/configs/medcom.h index bce03a4..678b36b 100644 --- a/include/configs/medcom.h +++ b/include/configs/medcom.h @@ -35,11 +35,11 @@ /* High-level configuration options */ #define V_PROMPT "Tegra20 (Medcom) # " -#define CONFIG_TEGRA20_BOARD_STRING "Avionic Design Medcom" +#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Medcom" /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA20_ENABLE_UARTD /* UARTD: debug UART */ +#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #define CONFIG_BOARD_EARLY_INIT_F @@ -78,6 +78,6 @@ "ext2load mmc 0 0x17000000 /boot/uImage;" \ "bootm" -#include "tegra20-common-post.h" +#include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 1266cf7..721cd90 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -115,19 +115,11 @@ #endif /* timer */ -#ifdef XILINX_TIMER_BASEADDR -# if (XILINX_TIMER_IRQ != -1) -# define CONFIG_SYS_TIMER_0 1 +#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ) # define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR # define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ -# define FREQUENCE XILINX_CLOCK_FREQ -# define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) -# endif -#elif XILINX_CLOCK_FREQ -# define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ -#else -# error BAD CLOCK FREQ #endif + /* FSL */ /* #define CONFIG_SYS_FSL_2 */ /* #define FSL_INTR_2 1 */ diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h index 5db6d57..8d35943 100644 --- a/include/configs/mt_ventoux.h +++ b/include/configs/mt_ventoux.h @@ -2,6 +2,9 @@ * Copyright (C) 2011 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. * + * + * Configuration settings for the Teejet mt_ventoux board. + * * Copyright (C) 2009 TechNexion Ltd. * * This program is free software; you can redistribute it and/or modify @@ -24,6 +27,10 @@ #include "tam3517-common.h" +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ + 6 * 1024 * 1024) + #define MACH_TYPE_AM3517_MT_VENTOUX 3832 #define CONFIG_MACH_TYPE MACH_TYPE_AM3517_MT_VENTOUX @@ -31,6 +38,7 @@ #define CONFIG_BOOTFILE "uImage" #define CONFIG_AUTO_COMPLETE +#define CONFIG_OMAP3_GPIO_4 #define CONFIG_HOSTNAME mt_ventoux /* @@ -62,6 +70,15 @@ #define CONFIG_FPGA_DELAY() udelay(1) #define CONFIG_SYS_FPGA_PROG_FEEDBACK +#define CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SPLASH_SCREEN +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_CMD_BMP +#define CONFIG_VIDEO_OMAP3 /* DSS Support */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + #define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \ "bootcmd=run net_nfs\0" diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index 359a308..96c143e 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -17,7 +17,6 @@ /* High Level Configuration Options */ -#define CONFIG_MX25_CLK32 32768 /* OSC32K frequency */ #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_TEXT_BASE 0x81200000 diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 4e1e6bc..dffb744 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -184,6 +184,9 @@ #define CONFIG_EHCI_MXS_PORT 1 #define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX #endif /* I2C */ @@ -199,6 +202,7 @@ #ifdef CONFIG_CMD_SPI #define CONFIG_HARD_SPI #define CONFIG_MXS_SPI +#define CONFIG_MXS_SPI_DMA_ENABLE #define CONFIG_SPI_HALF_DUPLEX #define CONFIG_DEFAULT_SPI_BUS 2 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 @@ -235,7 +239,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTCOMMAND "run bootcmd_net" #define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_OF_LIBFDT @@ -244,13 +247,80 @@ * Extra Environments */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "console_fsl=console=ttyAM0" \ - "console_mainline=console=ttyAMA0" \ - "netargs=setenv bootargs console=${console_mainline}" \ + "update_nand_full_filename=u-boot.nand\0" \ + "update_nand_firmware_filename=u-boot.sb\0" \ + "update_sd_firmware_filename=u-boot.sd\0" \ + "update_nand_firmware_maxsz=0x100000\0" \ + "update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \ + "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \ + "update_nand_get_fcb_size=" /* Get size of FCB blocks */ \ + "nand device 0 ; " \ + "nand info ; " \ + "setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \ + "setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \ + "update_nand_full=" /* Update FCB, DBBT and FW */ \ + "if tftp ${update_nand_full_filename} ; then " \ + "run update_nand_get_fcb_size ; " \ + "nand scrub -y 0x0 ${filesize} ; " \ + "nand write.raw ${loadaddr} 0x0 ${update_nand_fcb} ; " \ + "setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \ + "setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \ + "nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \ + "fi\0" \ + "update_nand_firmware=" /* Update only firmware */ \ + "if tftp ${update_nand_firmware_filename} ; then " \ + "run update_nand_get_fcb_size ; " \ + "setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \ + "setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \ + "setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \ + "nand erase ${fcb_sz} ${fw_sz} ; " \ + "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \ + "nand write ${loadaddr} ${fw_off} ${filesize} ; " \ + "fi\0" \ + "update_sd_firmware=" /* Update the SD firmware partition */ \ + "if mmc rescan ; then " \ + "if tftp ${update_sd_firmware_filename} ; then " \ + "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ + "setexpr fw_sz ${fw_sz} + 1 ; " \ + "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ + "fi ; " \ + "fi\0" \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "console_fsl=ttyAM0\0" \ + "console_mainline=ttyAMA0\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p3 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "mmcargs=setenv bootargs console=${console_mainline},${baudrate} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm\0" \ + "netargs=setenv bootargs console=${console_mainline},${baudrate} " \ "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot}\0" \ - "bootcmd_net=echo Booting from net ...; " \ - "run netargs; " \ - "dhcp ${uimage}; bootm\0" \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "dhcp ${uimage}; bootm\0" + +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" #endif /* __MX28EVK_CONFIG_H__ */ diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index 081fbf6..9d9f4a7 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -27,8 +27,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ #define CONFIG_MX31 1 /* in a mx31 */ -#define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */ -#define CONFIG_MX31_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 17d3143..b272674 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -35,8 +35,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX31 /* in a mx31 */ -#define CONFIG_MX31_HCLK_FREQ 26000000 -#define CONFIG_MX31_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 9bc6bd4..69bd654 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -31,7 +31,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX35 -#define CONFIG_MX35_HCLK_FREQ 24000000 #define CONFIG_DISPLAY_CPUINFO @@ -111,6 +110,12 @@ #define CONFIG_NET_RETRY_COUNT 100 #define CONFIG_CMD_DATE +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + #define CONFIG_BOOTDELAY 3 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ @@ -231,13 +236,19 @@ * NAND FLASH driver setup */ #define CONFIG_NAND_MXC -#define CONFIG_NAND_MXC_V1_1 #define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) #define CONFIG_MXC_NAND_HWECC #define CONFIG_SYS_NAND_LARGEPAGE +/* mmc driver */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 1 + /* * Default environment and default scripts * to update uboot and load kernel @@ -279,8 +290,8 @@ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ "load=tftp ${loadaddr} ${u-boot}\0" \ "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \ - "update=protect off ${uboot_addr} +40000;" \ - "erase ${uboot_addr} +40000;" \ + "update=protect off ${uboot_addr} +80000;" \ + "erase ${uboot_addr} +80000;" \ "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ "upd=if run load;then echo Updating u-boot;if run update;" \ "then echo U-Boot updated;" \ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index a8882d4..b18f4a0 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -31,7 +31,7 @@ #endif #if defined(CONFIG_P1020MBG) -#define CONFIG_BOARDNAME "P1020MBG" +#define CONFIG_BOARDNAME "P1020MBG-PC" #define CONFIG_P1020 #define CONFIG_VSC7385_ENET #define CONFIG_SLIC @@ -41,7 +41,7 @@ #endif #if defined(CONFIG_P1020UTM) -#define CONFIG_BOARDNAME "P1020UTM" +#define CONFIG_BOARDNAME "P1020UTM-PC" #define CONFIG_P1020 #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xe0 @@ -49,7 +49,7 @@ #endif #if defined(CONFIG_P1020RDB) -#define CONFIG_BOARDNAME "P1020RDB" +#define CONFIG_BOARDNAME "P1020RDB-PC" #define CONFIG_NAND_FSL_ELBC #define CONFIG_P1020 #define CONFIG_SPI_FLASH @@ -64,7 +64,7 @@ #endif #if defined(CONFIG_P1021RDB) -#define CONFIG_BOARDNAME "P1021RDB" +#define CONFIG_BOARDNAME "P1021RDB-PC" #define CONFIG_NAND_FSL_ELBC #define CONFIG_P1021 #define CONFIG_QE @@ -111,7 +111,7 @@ #endif #if defined(CONFIG_P2020RDB) -#define CONFIG_BOARDNAME "P2020RDB" +#define CONFIG_BOARDNAME "P2020RDB-PCA" #define CONFIG_NAND_FSL_ELBC #define CONFIG_P2020 #define CONFIG_SPI_FLASH diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 0eb9f3b..24cda48 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -27,11 +27,11 @@ /* High-level configuration options */ #define V_PROMPT "Tegra20 (Paz00) MOD # " -#define CONFIG_TEGRA20_BOARD_STRING "Compal Paz00" +#define CONFIG_TEGRA_BOARD_STRING "Compal Paz00" /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA20_ENABLE_UARTA +#define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define CONFIG_MACH_TYPE MACH_TYPE_PAZ00 @@ -51,8 +51,9 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 /* USB Host support */ #define CONFIG_USB_EHCI @@ -68,6 +69,6 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP -#include "tegra20-common-post.h" +#include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h index 42291d4..65b42ed 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -35,11 +35,11 @@ /* High-level configuration options */ #define V_PROMPT "Tegra20 (Plutux) # " -#define CONFIG_TEGRA20_BOARD_STRING "Avionic Design Plutux" +#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Plutux" /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA20_ENABLE_UARTD /* UARTD: debug UART */ +#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #define CONFIG_BOARD_EARLY_INIT_F @@ -78,6 +78,6 @@ "ext2load mmc 0 0x17000000 /boot/uImage;" \ "bootm" -#include "tegra20-common-post.h" +#include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index 306c173..b8b9705 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -100,7 +100,12 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "qemu-mips # " /* Monitor Command Prompt */ +/* Monitor Command Prompt */ +#if defined(CONFIG_SYS_LITTLE_ENDIAN) +#define CONFIG_SYS_PROMPT "qemu-mipsel # " +#else +#define CONFIG_SYS_PROMPT "qemu-mips # " +#endif #define CONFIG_AUTO_COMPLETE #define CONFIG_CMDLINE_EDITING diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h index a3fc465..4bb5bbc 100644 --- a/include/configs/qi_lb60.h +++ b/include/configs/qi_lb60.h @@ -11,6 +11,7 @@ #define __CONFIG_QI_LB60_H #define CONFIG_MIPS32 /* MIPS32 CPU core */ +#define CONFIG_SYS_LITTLE_ENDIAN #define CONFIG_JZSOC /* Jz SoC */ #define CONFIG_JZ4740 /* Jz4740 SoC */ #define CONFIG_NAND_JZ4740 diff --git a/include/configs/qong.h b/include/configs/qong.h index 485e1b1..c2bd097 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -28,8 +28,6 @@ #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX31 /* in a mx31 */ #define CONFIG_QONG -#define CONFIG_MX31_HCLK_FREQ 26000000 /* 26MHz */ -#define CONFIG_MX31_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h index 0ebdfb8..f5dc393 100644 --- a/include/configs/sc_sps_1.h +++ b/include/configs/sc_sps_1.h @@ -39,8 +39,6 @@ #include <asm/arch/regs-base.h> #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_CPU_INIT #define CONFIG_ARCH_MISC_INIT diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index afc4a85..de19e38 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -27,7 +27,7 @@ #include <asm/sizes.h> /* LP0 suspend / resume */ -#define CONFIG_TEGRA20_LP0 +#define CONFIG_TEGRA_LP0 #define CONFIG_AES #define CONFIG_TEGRA_PMU #define CONFIG_TPS6586X_POWER @@ -42,11 +42,11 @@ /* High-level configuration options */ #define V_PROMPT "Tegra20 (SeaBoard) # " -#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Seaboard" +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Seaboard" /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA20_ENABLE_UARTD +#define CONFIG_TEGRA_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */ @@ -77,8 +77,9 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 /* USB Host support */ #define CONFIG_USB_EHCI @@ -95,14 +96,23 @@ #define CONFIG_CMD_DHCP /* Enable keyboard */ -#define CONFIG_TEGRA20_KEYBOARD +#define CONFIG_TEGRA_KEYBOARD #define CONFIG_KEYBOARD -#undef TEGRA20_DEVICE_SETTINGS -#define TEGRA20_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \ - "stdout=serial\0" \ - "stderr=serial\0" +#undef TEGRA_DEVICE_SETTINGS +#define TEGRA_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \ + "stdout=serial\0" \ + "stderr=serial\0" -#include "tegra20-common-post.h" +#include "tegra-common-post.h" +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_TEGRA_NAND + +/* Max number of NAND devices */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* Somewhat oddly, the NAND base address must be a config option */ +#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE #endif /* __CONFIG_H */ diff --git a/include/configs/stamp9g20.h b/include/configs/stamp9g20.h index a2a0156..a881eef 100644 --- a/include/configs/stamp9g20.h +++ b/include/configs/stamp9g20.h @@ -59,6 +59,7 @@ #define CONFIG_INITRD_TAG /* pass initrd param to kernel */ #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ #define CONFIG_BOARD_EARLY_INIT_f /* call board_early_init_f() */ +#define CONFIG_BOARD_POSTCLK_INIT /* call board_postclk_init() */ #define CONFIG_DISPLAY_CPUINFO /* display CPU Info at startup */ /* setting board specific options */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 375265d..a13fd93 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -124,6 +124,7 @@ #define CONFIG_CMD_NAND /* NAND support */ #define CONFIG_CMD_PING #define CONFIG_CMD_USB +#define CONFIG_CMD_EEPROM #undef CONFIG_CMD_FLASH /* only NAND on the SOM */ #undef CONFIG_CMD_IMLS @@ -134,6 +135,9 @@ #define CONFIG_SYS_I2C_SLAVE 1 #define CONFIG_SYS_I2C_BUS 0 #define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 #define CONFIG_DRIVER_OMAP34XX_I2C @@ -347,4 +351,66 @@ "fi;" \ "else echo U-Boot not downloaded..exiting;fi\0" \ + +/* + * this is common code for all TAM3517 boards. + * MAC address is stored from manufacturer in + * I2C EEPROM + */ +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) + +/* + * The I2C EEPROM on the TAM3517 contains + * mac address and production data + */ +struct tam3517_module_info { + char customer[48]; + char product[48]; + + /* + * bit 0~47 : sequence number + * bit 48~55 : week of year, from 0. + * bit 56~63 : year + */ + unsigned long long sequence_number; + + /* + * bit 0~7 : revision fixed + * bit 8~15 : revision major + * bit 16~31 : TNxxx + */ + unsigned int revision; + unsigned char eth_addr[4][8]; + unsigned char _rev[100]; +}; + +#define TAM3517_READ_MAC_FROM_EEPROM \ +do { \ + struct tam3517_module_info info;\ + char buf[80], ethname[20]; \ + int i; \ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); \ + if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ + (void *)&info, sizeof(info))) \ + break; \ + memset(buf, 0, sizeof(buf)); \ + for (i = 0 ; i < ARRAY_SIZE(info.eth_addr); i++) { \ + sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ + info.eth_addr[i][5], \ + info.eth_addr[i][4], \ + info.eth_addr[i][3], \ + info.eth_addr[i][2], \ + info.eth_addr[i][1], \ + info.eth_addr[i][0]); \ + \ + if (i) \ + sprintf(ethname, "eth%daddr", i); \ + else \ + sprintf(ethname, "ethaddr"); \ + printf("Setting %s from EEPROM with %s\n", ethname, buf);\ + setenv(ethname, buf); \ + } \ +} while (0) +#endif + #endif /* __TAM3517_H */ diff --git a/include/configs/tec.h b/include/configs/tec.h index 9b3f88d..d5da3c7 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -35,24 +35,32 @@ /* High-level configuration options */ #define V_PROMPT "Tegra20 (TEC) # " -#define CONFIG_TEGRA20_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" +#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" #define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011 /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA20_ENABLE_UARTD /* UARTD: debug UART */ +#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_ENV_IS_NOWHERE - /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC #define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_TEGRA_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE + +/* Environment in NAND, aligned to start of last sector */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */ + /* USB host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA @@ -79,6 +87,6 @@ "ext2load mmc 0 0x17000000 /boot/uImage;" \ "bootm" -#include "tegra20-common-post.h" +#include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/tegra20-common-post.h b/include/configs/tegra-common-post.h index 42f270f..168b64b 100644 --- a/include/configs/tegra20-common-post.h +++ b/include/configs/tegra-common-post.h @@ -21,8 +21,8 @@ * MA 02111-1307 USA */ -#ifndef __TEGRA20_COMMON_POST_H -#define __TEGRA20_COMMON_POST_H +#ifndef __TEGRA_COMMON_POST_H +#define __TEGRA_COMMON_POST_H #ifdef CONFIG_BOOTCOMMAND @@ -141,7 +141,7 @@ #endif #define CONFIG_EXTRA_ENV_SETTINGS \ - TEGRA20_DEVICE_SETTINGS \ + TEGRA_DEVICE_SETTINGS \ "fdt_load=0x01000000\0" \ "fdt_high=01100000\0" \ BOOTCMDS_COMMON @@ -174,8 +174,8 @@ #ifdef CONFIG_GENERIC_MMC #undef CONFIG_GENERIC_MMC #endif -#ifdef CONFIG_TEGRA20_MMC -#undef CONFIG_TEGRA20_MMC +#ifdef CONFIG_TEGRA_MMC +#undef CONFIG_TEGRA_MMC #endif #ifdef CONFIG_CMD_MMC #undef CONFIG_CMD_MMC @@ -211,4 +211,4 @@ #endif /* CONFIG_SPL_BUILD */ -#endif /* __TEGRA20_COMMON_POST_H */ +#endif /* __TEGRA_COMMON_POST_H */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 4c02f20..098cdb4 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -54,7 +54,7 @@ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_OF_LIBFDT /* enable passing of devicetree */ -#ifdef CONFIG_TEGRA20_LP0 +#ifdef CONFIG_TEGRA_LP0 #define TEGRA_LP0_ADDR 0x1C406000 #define TEGRA_LP0_SIZE 0x2000 #define TEGRA_LP0_VEC \ @@ -132,9 +132,9 @@ /* Environment information, boards can override if required */ #define CONFIG_CONSOLE_MUX #define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define TEGRA20_DEVICE_SETTINGS "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" +#define TEGRA_DEVICE_SETTINGS "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" #define CONFIG_LOADADDR 0x408000 /* def. location for kernel */ #define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */ @@ -157,7 +157,7 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) -#define CONFIG_SYS_MEMTEST_START (TEGRA20_SDRC_CS0 + 0x600000) +#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) #define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */ @@ -169,7 +169,7 @@ * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 TEGRA20_SDRC_CS0 +#define PHYS_SDRAM_1 NV_PA_SDRC_CS0 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_TEXT_BASE 0x0010c000 @@ -201,4 +201,6 @@ #define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds" +#define CONFIG_SYS_NAND_SELF_INIT + #endif /* __TEGRA20_COMMON_H */ diff --git a/include/configs/trats.h b/include/configs/trats.h index f8da9c01..b3b5a3d 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -78,6 +78,7 @@ #define CONFIG_MMC #define CONFIG_S5P_SDHCI #define CONFIG_SDHCI +#define CONFIG_MMC_SDMA /* PWM */ #define CONFIG_PWM @@ -211,18 +212,28 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_CACHELINE_SIZE 32 -#include <asm/arch/gpio.h> -/* - * I2C Settings - */ -#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7) -#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6) #define CONFIG_SOFT_I2C #define CONFIG_SOFT_I2C_READ_REPEATED_START +#define CONFIG_SYS_I2C_INIT_BOARD #define CONFIG_SYS_I2C_SPEED 50000 #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_MAX_I2C_BUS 7 +#define CONFIG_SOFT_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS 15 + +#include <asm/arch/gpio.h> + +/* I2C PMIC */ +#define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7) +#define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6) + +/* I2C FG */ +#define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1) +#define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0) + +#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin() +#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin() +#define I2C_INIT multi_i2c_init() #define CONFIG_PMIC #define CONFIG_PMIC_I2C diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index b3c5249..a46890c 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -34,12 +34,12 @@ /* High-level configuration options */ #define V_PROMPT "Tegra20 (TrimSlice) # " -#define CONFIG_TEGRA20_BOARD_STRING "Compulab Trimslice" +#define CONFIG_TEGRA_BOARD_STRING "Compulab Trimslice" /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA20_ENABLE_UARTA -#define CONFIG_TEGRA20_UARTA_GPU +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_TEGRA_UARTA_GPU #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE @@ -94,6 +94,6 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP -#include "tegra20-common-post.h" +#include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/tt01.h b/include/configs/tt01.h index cc68a42..f46efa5 100644 --- a/include/configs/tt01.h +++ b/include/configs/tt01.h @@ -31,8 +31,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 #define CONFIG_MX31 -#define CONFIG_MX31_HCLK_FREQ 26000000 -#define CONFIG_MX31_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/tx25.h b/include/configs/tx25.h index c8a49bb..71b1d32 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -107,7 +107,6 @@ /* NAND */ #define CONFIG_NAND_MXC -#define CONFIG_NAND_MXC_V1_1 #define CONFIG_MXC_NAND_REGS_BASE (0xBB000000) #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE (0xBB000000) diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 25ec2eb..7d3a54f 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -34,11 +34,11 @@ /* High-level configuration options */ #define V_PROMPT "Tegra20 (Ventana) # " -#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Ventana" +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Ventana" /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA20_ENABLE_UARTD +#define CONFIG_TEGRA_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #define CONFIG_MACH_TYPE MACH_TYPE_VENTANA @@ -58,8 +58,9 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 /* USB Host support */ #define CONFIG_USB_EHCI @@ -75,6 +76,6 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP -#include "tegra20-common-post.h" +#include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/whistler.h b/include/configs/whistler.h index b747d0e..6c565ba 100644 --- a/include/configs/whistler.h +++ b/include/configs/whistler.h @@ -34,12 +34,12 @@ /* High-level configuration options */ #define V_PROMPT "Tegra20 (Whistler) # " -#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Whistler" +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Whistler" /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA20_ENABLE_UARTA -#define CONFIG_TEGRA20_UARTA_UAA_UAB +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_TEGRA_UARTA_UAA_UAB #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER @@ -72,8 +72,9 @@ * particular card is standard practice as far as I know. */ #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 /* USB Host support */ #define CONFIG_USB_EHCI @@ -89,6 +90,6 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP -#include "tegra20-common-post.h" +#include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index 072945a..447683a 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -28,7 +28,6 @@ #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_MX25 -#define CONFIG_MX25_CLK32 32768 /* OSC32K frequency */ #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_TEXT_BASE 0xA0000000 diff --git a/include/ddr_spd.h b/include/ddr_spd.h index a9230b9..9e74d87 100644 --- a/include/ddr_spd.h +++ b/include/ddr_spd.h @@ -221,7 +221,12 @@ typedef struct ddr3_spd_eeprom_s { unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */ unsigned char therm_sensor; /* 32 Module Thermal Sensor */ unsigned char device_type; /* 33 SDRAM device type */ - unsigned char res_34_59[26]; /* 34-59 Reserved, General Section */ + int8_t fine_tCK_min; /* 34 Fine offset for tCKmin */ + int8_t fine_tAA_min; /* 35 Fine offset for tAAmin */ + int8_t fine_tRCD_min; /* 36 Fine offset for tRCDmin */ + int8_t fine_tRP_min; /* 37 Fine offset for tRPmin */ + int8_t fine_tRC_min; /* 38 Fine offset for tRCmin */ + unsigned char res_39_59[21]; /* 39-59 Reserved, General Section */ /* Module-Specific Section: Bytes 60-116 */ union { diff --git a/include/environment.h b/include/environment.h index ae3f7b6..e8ab703 100644 --- a/include/environment.h +++ b/include/environment.h @@ -181,9 +181,21 @@ void env_crc_update(void); /* [re]set to the default environment */ void set_default_env(const char *s); +/* [re]set individual variables to their value in the default environment */ +int set_default_vars(int nvars, char * const vars[]); + /* Import from binary representation into hash table */ int env_import(const char *buf, int check); +/* + * Check if variable "name" can be changed from oldval to newval, + * and if so, apply the changes (e.g. baudrate). + * When (flag & H_FORCE) is set, it does not print out any error + * message and forces overwriting of write-once variables. + */ +int env_check_apply(const char *name, const char *oldval, + const char *newval, int flag); + #endif /* DO_DEPS_ONLY */ #endif /* _ENVIRONMENT_H_ */ diff --git a/include/ext2fs.h b/include/ext2fs.h deleted file mode 100644 index 163a9bb..0000000 --- a/include/ext2fs.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * GRUB -- GRand Unified Bootloader - * Copyright (C) 2000, 2001 Free Software Foundation, Inc. - * - * (C) Copyright 2003 Sysgo Real-Time Solutions, AG <www.elinos.com> - * Pavel Bartusek <pba@sysgo.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* An implementation for the Ext2FS filesystem ported from GRUB. - * Some parts of this code (mainly the structures and defines) are - * from the original ext2 fs code, as found in the linux kernel. - */ - - -#define SECTOR_SIZE 0x200 -#define SECTOR_BITS 9 - -/* Error codes */ -typedef enum -{ - ERR_NONE = 0, - ERR_BAD_FILENAME, - ERR_BAD_FILETYPE, - ERR_BAD_GZIP_DATA, - ERR_BAD_GZIP_HEADER, - ERR_BAD_PART_TABLE, - ERR_BAD_VERSION, - ERR_BELOW_1MB, - ERR_BOOT_COMMAND, - ERR_BOOT_FAILURE, - ERR_BOOT_FEATURES, - ERR_DEV_FORMAT, - ERR_DEV_VALUES, - ERR_EXEC_FORMAT, - ERR_FILELENGTH, - ERR_FILE_NOT_FOUND, - ERR_FSYS_CORRUPT, - ERR_FSYS_MOUNT, - ERR_GEOM, - ERR_NEED_LX_KERNEL, - ERR_NEED_MB_KERNEL, - ERR_NO_DISK, - ERR_NO_PART, - ERR_NUMBER_PARSING, - ERR_OUTSIDE_PART, - ERR_READ, - ERR_SYMLINK_LOOP, - ERR_UNRECOGNIZED, - ERR_WONT_FIT, - ERR_WRITE, - ERR_BAD_ARGUMENT, - ERR_UNALIGNED, - ERR_PRIVILEGED, - ERR_DEV_NEED_INIT, - ERR_NO_DISK_SPACE, - ERR_NUMBER_OVERFLOW, - - MAX_ERR_NUM -} ext2fs_error_t; - - -extern int ext2fs_set_blk_dev(block_dev_desc_t *rbdd, int part); -extern int ext2fs_ls (const char *dirname); -extern int ext2fs_open (const char *filename); -extern int ext2fs_read (char *buf, unsigned len); -extern int ext2fs_mount (unsigned part_length); -extern int ext2fs_close(void); diff --git a/include/ext4fs.h b/include/ext4fs.h new file mode 100644 index 0000000..b6eedde --- /dev/null +++ b/include/ext4fs.h @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2011 - 2012 Samsung Electronics + * EXT4 filesystem implementation in Uboot by + * Uma Shankar <uma.shankar@samsung.com> + * Manjunatha C Achar <a.manjunatha@samsung.com> + * + * Ext4 Extent data structures are taken from original ext4 fs code + * as found in the linux kernel. + * + * Copyright (c) 2003-2006, Cluster File Systems, Inc, info@clusterfs.com + * Written by Alex Tomas <alex@clusterfs.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __EXT4__ +#define __EXT4__ +#include <ext_common.h> + +#define EXT4_EXTENTS_FL 0x00080000 /* Inode uses extents */ +#define EXT4_EXT_MAGIC 0xf30a +#define EXT4_FEATURE_RO_COMPAT_GDT_CSUM 0x0010 +#define EXT4_FEATURE_INCOMPAT_EXTENTS 0x0040 +#define EXT4_INDIRECT_BLOCKS 12 + +#define EXT4_BG_INODE_UNINIT 0x0001 +#define EXT4_BG_BLOCK_UNINIT 0x0002 +#define EXT4_BG_INODE_ZEROED 0x0004 + +/* + * ext4_inode has i_block array (60 bytes total). + * The first 12 bytes store ext4_extent_header; + * the remainder stores an array of ext4_extent. + */ + +/* + * This is the extent on-disk structure. + * It's used at the bottom of the tree. + */ +struct ext4_extent { + __le32 ee_block; /* first logical block extent covers */ + __le16 ee_len; /* number of blocks covered by extent */ + __le16 ee_start_hi; /* high 16 bits of physical block */ + __le32 ee_start_lo; /* low 32 bits of physical block */ +}; + +/* + * This is index on-disk structure. + * It's used at all the levels except the bottom. + */ +struct ext4_extent_idx { + __le32 ei_block; /* index covers logical blocks from 'block' */ + __le32 ei_leaf_lo; /* pointer to the physical block of the next * + * level. leaf or next index could be there */ + __le16 ei_leaf_hi; /* high 16 bits of physical block */ + __u16 ei_unused; +}; + +/* Each block (leaves and indexes), even inode-stored has header. */ +struct ext4_extent_header { + __le16 eh_magic; /* probably will support different formats */ + __le16 eh_entries; /* number of valid entries */ + __le16 eh_max; /* capacity of store in entries */ + __le16 eh_depth; /* has tree real underlying blocks? */ + __le32 eh_generation; /* generation of the tree */ +}; + +struct ext_filesystem { + /* Total Sector of partition */ + uint64_t total_sect; + /* Block size of partition */ + uint32_t blksz; + /* Inode size of partition */ + uint32_t inodesz; + /* Sectors per Block */ + uint32_t sect_perblk; + /* Group Descriptor Block Number */ + uint32_t gdtable_blkno; + /* Total block groups of partition */ + uint32_t no_blkgrp; + /* No of blocks required for bgdtable */ + uint32_t no_blk_pergdt; + /* Superblock */ + struct ext2_sblock *sb; + /* Block group descritpor table */ + struct ext2_block_group *gd; + char *gdtable; + + /* Block Bitmap Related */ + unsigned char **blk_bmaps; + long int curr_blkno; + uint16_t first_pass_bbmap; + + /* Inode Bitmap Related */ + unsigned char **inode_bmaps; + int curr_inode_no; + uint16_t first_pass_ibmap; + + /* Journal Related */ + + /* Block Device Descriptor */ + block_dev_desc_t *dev_desc; +}; + +extern struct ext2_data *ext4fs_root; +extern struct ext2fs_node *ext4fs_file; + +#if defined(CONFIG_CMD_EXT4_WRITE) +extern struct ext2_inode *g_parent_inode; +extern int gd_index; +extern int gindex; + +int ext4fs_init(void); +void ext4fs_deinit(void); +int ext4fs_filename_check(char *filename); +int ext4fs_write(const char *fname, unsigned char *buffer, + unsigned long sizebytes); +#endif + +struct ext_filesystem *get_fs(void); +int ext4fs_open(const char *filename); +int ext4fs_read(char *buf, unsigned len); +int ext4fs_mount(unsigned part_length); +void ext4fs_close(void); +int ext4fs_ls(const char *dirname); +void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot); +int ext4fs_devread(int sector, int byte_offset, int byte_len, char *buf); +void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); +long int read_allocated_block(struct ext2_inode *inode, int fileblock); +#endif diff --git a/include/ext_common.h b/include/ext_common.h new file mode 100644 index 0000000..ce73857 --- /dev/null +++ b/include/ext_common.h @@ -0,0 +1,201 @@ +/* + * (C) Copyright 2011 - 2012 Samsung Electronics + * EXT4 filesystem implementation in Uboot by + * Uma Shankar <uma.shankar@samsung.com> + * Manjunatha C Achar <a.manjunatha@samsung.com> + * + * Data structures and headers for ext4 support have been taken from + * ext2 ls load support in Uboot + * + * (C) Copyright 2004 + * esd gmbh <www.esd-electronics.com> + * Reinhard Arlt <reinhard.arlt@esd-electronics.com> + * + * based on code from grub2 fs/ext2.c and fs/fshelp.c by + * GRUB -- GRand Unified Bootloader + * Copyright (C) 2003, 2004 Free Software Foundation, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __EXT_COMMON__ +#define __EXT_COMMON__ +#include <command.h> +#define SECTOR_SIZE 0x200 +#define SECTOR_BITS 9 + +/* Magic value used to identify an ext2 filesystem. */ +#define EXT2_MAGIC 0xEF53 +/* Amount of indirect blocks in an inode. */ +#define INDIRECT_BLOCKS 12 +/* Maximum lenght of a pathname. */ +#define EXT2_PATH_MAX 4096 +/* Maximum nesting of symlinks, used to prevent a loop. */ +#define EXT2_MAX_SYMLINKCNT 8 + +/* Filetype used in directory entry. */ +#define FILETYPE_UNKNOWN 0 +#define FILETYPE_REG 1 +#define FILETYPE_DIRECTORY 2 +#define FILETYPE_SYMLINK 7 + +/* Filetype information as used in inodes. */ +#define FILETYPE_INO_MASK 0170000 +#define FILETYPE_INO_REG 0100000 +#define FILETYPE_INO_DIRECTORY 0040000 +#define FILETYPE_INO_SYMLINK 0120000 +#define EXT2_ROOT_INO 2 /* Root inode */ + +/* Bits used as offset in sector */ +#define DISK_SECTOR_BITS 9 +/* The size of an ext2 block in bytes. */ +#define EXT2_BLOCK_SIZE(data) (1 << LOG2_BLOCK_SIZE(data)) + +/* Log2 size of ext2 block in 512 blocks. */ +#define LOG2_EXT2_BLOCK_SIZE(data) (__le32_to_cpu \ + (data->sblock.log2_block_size) + 1) + +/* Log2 size of ext2 block in bytes. */ +#define LOG2_BLOCK_SIZE(data) (__le32_to_cpu \ + (data->sblock.log2_block_size) + 10) +#define INODE_SIZE_FILESYSTEM(data) (__le32_to_cpu \ + (data->sblock.inode_size)) + +#define EXT2_FT_DIR 2 +#define SUCCESS 1 + +/* Macro-instructions used to manage several block sizes */ +#define EXT2_MIN_BLOCK_LOG_SIZE 10 /* 1024 */ +#define EXT2_MAX_BLOCK_LOG_SIZE 16 /* 65536 */ +#define EXT2_MIN_BLOCK_SIZE (1 << EXT2_MIN_BLOCK_LOG_SIZE) +#define EXT2_MAX_BLOCK_SIZE (1 << EXT2_MAX_BLOCK_LOG_SIZE) + +/* The ext2 superblock. */ +struct ext2_sblock { + uint32_t total_inodes; + uint32_t total_blocks; + uint32_t reserved_blocks; + uint32_t free_blocks; + uint32_t free_inodes; + uint32_t first_data_block; + uint32_t log2_block_size; + uint32_t log2_fragment_size; + uint32_t blocks_per_group; + uint32_t fragments_per_group; + uint32_t inodes_per_group; + uint32_t mtime; + uint32_t utime; + uint16_t mnt_count; + uint16_t max_mnt_count; + uint16_t magic; + uint16_t fs_state; + uint16_t error_handling; + uint16_t minor_revision_level; + uint32_t lastcheck; + uint32_t checkinterval; + uint32_t creator_os; + uint32_t revision_level; + uint16_t uid_reserved; + uint16_t gid_reserved; + uint32_t first_inode; + uint16_t inode_size; + uint16_t block_group_number; + uint32_t feature_compatibility; + uint32_t feature_incompat; + uint32_t feature_ro_compat; + uint32_t unique_id[4]; + char volume_name[16]; + char last_mounted_on[64]; + uint32_t compression_info; +}; + +struct ext2_block_group { + __u32 block_id; /* Blocks bitmap block */ + __u32 inode_id; /* Inodes bitmap block */ + __u32 inode_table_id; /* Inodes table block */ + __u16 free_blocks; /* Free blocks count */ + __u16 free_inodes; /* Free inodes count */ + __u16 used_dir_cnt; /* Directories count */ + __u16 bg_flags; + __u32 bg_reserved[2]; + __u16 bg_itable_unused; /* Unused inodes count */ + __u16 bg_checksum; /* crc16(s_uuid+grouo_num+group_desc)*/ +}; + +/* The ext2 inode. */ +struct ext2_inode { + uint16_t mode; + uint16_t uid; + uint32_t size; + uint32_t atime; + uint32_t ctime; + uint32_t mtime; + uint32_t dtime; + uint16_t gid; + uint16_t nlinks; + uint32_t blockcnt; /* Blocks of 512 bytes!! */ + uint32_t flags; + uint32_t osd1; + union { + struct datablocks { + uint32_t dir_blocks[INDIRECT_BLOCKS]; + uint32_t indir_block; + uint32_t double_indir_block; + uint32_t triple_indir_block; + } blocks; + char symlink[60]; + } b; + uint32_t version; + uint32_t acl; + uint32_t dir_acl; + uint32_t fragment_addr; + uint32_t osd2[3]; +}; + +/* The header of an ext2 directory entry. */ +struct ext2_dirent { + uint32_t inode; + uint16_t direntlen; + uint8_t namelen; + uint8_t filetype; +}; + +struct ext2fs_node { + struct ext2_data *data; + struct ext2_inode inode; + int ino; + int inode_read; +}; + +/* Information about a "mounted" ext2 filesystem. */ +struct ext2_data { + struct ext2_sblock sblock; + struct ext2_inode *inode; + struct ext2fs_node diropen; +}; + +extern unsigned long part_offset; + +int do_ext2ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +int do_ext2load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +int do_ext4_load(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]); +int do_ext4_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); +int do_ext4_write(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]); +int do_ext_load(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]); +int do_ext_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); +#endif diff --git a/include/fdtdec.h b/include/fdtdec.h index a8f783f..0b14075 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -19,6 +19,8 @@ * MA 02111-1307 USA */ +#ifndef __fdtdec_h +#define __fdtdec_h /* * This file contains convenience functions for decoding useful and @@ -63,6 +65,7 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra20 memory controller */ COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */ COMPAT_NVIDIA_TEGRA20_KBC, /* Tegra20 Keyboard */ + COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */ COMPAT_COUNT, }; @@ -382,3 +385,4 @@ int fdtdec_get_byte_array(const void *blob, int node, const char *prop_name, */ const u8 *fdtdec_locate_byte_array(const void *blob, int node, const char *prop_name, int count); +#endif diff --git a/include/fm_eth.h b/include/fm_eth.h index c7c6882..e56541d 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -35,6 +35,7 @@ enum fm_port { FM2_DTSEC2, FM2_DTSEC3, FM2_DTSEC4, + FM2_DTSEC5, FM2_10GEC1, NUM_FM_PORTS, }; @@ -109,6 +110,7 @@ void fman_enet_init(void); void fdt_fixup_fman_ethernet(void *fdt); phy_interface_t fm_info_get_enet_if(enum fm_port port); void fm_info_set_phy_address(enum fm_port port, int address); +int fm_info_get_phy_address(enum fm_port port); void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus); void fm_disable_port(enum fm_port port); diff --git a/include/fsl_nfc.h b/include/fsl_nfc.h index 279aaa5..ff537b4 100644 --- a/include/fsl_nfc.h +++ b/include/fsl_nfc.h @@ -24,49 +24,48 @@ #define __FSL_NFC_H /* - * TODO: Use same register defs for nand_spl mxc nand driver - * and mtd mxc nand driver. + * Register map and bit definitions for the Freescale NAND Flash Controller + * present in various i.MX devices. * - * Register map and bit definitions for the Freescale NAND Flash - * Controller present in various i.MX devices. + * MX31 and MX27 have version 1, which has: + * 4 512-byte main buffers and + * 4 16-byte spare buffers + * to support up to 2K byte pagesize nand. + * Reading or writing a 2K page requires 4 FDI/FDO cycles. * - * MX31 and MX27 have version 1 which has - * 4 512 byte main buffers and - * 4 16 byte spare buffers - * to support up to 2K byte pagesize nand. - * Reading or writing a 2K page requires 4 FDI/FDO cycles. - * - * MX25 has version 1.1 which has - * 8 512 byte main buffers and - * 8 64 byte spare buffers - * to support up to 4K byte pagesize nand. - * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle. - * Also some of registers are moved and/or changed meaning as seen below. + * MX25 and MX35 have version 2.1, which has: + * 8 512-byte main buffers and + * 8 64-byte spare buffers + * to support up to 4K byte pagesize nand. + * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle. + * Also some of registers are moved and/or changed meaning as seen below. */ -#if defined(CONFIG_MX31) || defined(CONFIG_MX27) +#if defined(CONFIG_MX27) || defined(CONFIG_MX31) #define MXC_NFC_V1 -#elif defined(CONFIG_MX25) -#define MXC_NFC_V1_1 +#define is_mxc_nfc_1() 1 +#define is_mxc_nfc_21() 0 +#elif defined(CONFIG_MX25) || defined(CONFIG_MX35) +#define MXC_NFC_V2_1 +#define is_mxc_nfc_1() 0 +#define is_mxc_nfc_21() 1 #else -#warning "MXC NFC version not defined" +#error "MXC NFC implementation not supported" #endif #if defined(MXC_NFC_V1) #define NAND_MXC_NR_BUFS 4 #define NAND_MXC_SPARE_BUF_SIZE 16 #define NAND_MXC_REG_OFFSET 0xe00 -#define NAND_MXC_2K_MULTI_CYCLE 1 -#elif defined(MXC_NFC_V1_1) +#define NAND_MXC_2K_MULTI_CYCLE +#elif defined(MXC_NFC_V2_1) #define NAND_MXC_NR_BUFS 8 #define NAND_MXC_SPARE_BUF_SIZE 64 #define NAND_MXC_REG_OFFSET 0x1e00 -#else -#error "define CONFIG_NAND_MXC_VXXX to use the mxc spl_nand driver" #endif struct fsl_nfc_regs { - u32 main_area[NAND_MXC_NR_BUFS][512/4]; - u32 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE/4]; + u8 main_area[NAND_MXC_NR_BUFS][0x200]; + u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE]; /* * reserved size is offset of nfc registers * minus total main and spare sizes @@ -74,44 +73,43 @@ struct fsl_nfc_regs { u8 reserved1[NAND_MXC_REG_OFFSET - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)]; #if defined(MXC_NFC_V1) - u16 bufsiz; + u16 buf_size; u16 reserved2; - u16 buffer_address; - u16 flash_add; + u16 buf_addr; + u16 flash_addr; u16 flash_cmd; - u16 configuration; + u16 config; u16 ecc_status_result; - u16 ecc_rslt_main_area; - u16 ecc_rslt_spare_area; - u16 nf_wr_prot; - u16 unlock_start_blk_add; - u16 unlock_end_blk_add; - u16 nand_flash_wr_pr_st; - u16 nand_flash_config1; - u16 nand_flash_config2; -#elif defined(MXC_NFC_V1_1) + u16 rsltmain_area; + u16 rsltspare_area; + u16 wrprot; + u16 unlockstart_blkaddr; + u16 unlockend_blkaddr; + u16 nf_wrprst; + u16 config1; + u16 config2; +#elif defined(MXC_NFC_V2_1) u16 reserved2[2]; - u16 buffer_address; - u16 flash_add; + u16 buf_addr; + u16 flash_addr; u16 flash_cmd; - u16 configuration; - u16 ecc_status_result; - u16 ecc_status_result2; + u16 config; + u32 ecc_status_result; u16 spare_area_size; - u16 nf_wr_prot; + u16 wrprot; u16 reserved3[2]; - u16 nand_flash_wr_pr_st; - u16 nand_flash_config1; - u16 nand_flash_config2; + u16 nf_wrprst; + u16 config1; + u16 config2; u16 reserved4; - u16 unlock_start_blk_add0; - u16 unlock_end_blk_add0; - u16 unlock_start_blk_add1; - u16 unlock_end_blk_add1; - u16 unlock_start_blk_add2; - u16 unlock_end_blk_add2; - u16 unlock_start_blk_add3; - u16 unlock_end_blk_add3; + u16 unlockstart_blkaddr; + u16 unlockend_blkaddr; + u16 unlockstart_blkaddr1; + u16 unlockend_blkaddr1; + u16 unlockstart_blkaddr2; + u16 unlockend_blkaddr2; + u16 unlockstart_blkaddr3; + u16 unlockend_blkaddr3; #endif }; @@ -157,7 +155,7 @@ struct fsl_nfc_regs { */ #define NFC_INT 0x8000 -#ifdef MXC_NFC_V1_1 +#ifdef MXC_NFC_V2_1 #define NFC_4_8N_ECC (1 << 0) #endif #define NFC_SP_EN (1 << 2) @@ -167,5 +165,6 @@ struct fsl_nfc_regs { #define NFC_RST (1 << 6) #define NFC_CE (1 << 7) #define NFC_ONE_CYCLE (1 << 8) +#define NFC_FP_INT (1 << 11) #endif /* __FSL_NFC_H */ diff --git a/include/i2c.h b/include/i2c.h index 1f35acf..16f099d 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -250,4 +250,16 @@ static inline void I2C_SET_BUS(unsigned int bus) i2c_set_bus_num(bus); } +/* Multi I2C definitions */ +enum { + I2C_0, I2C_1, I2C_2, I2C_3, I2C_4, I2C_5, I2C_6, I2C_7, + I2C_8, I2C_9, I2C_10, +}; + +/* Multi I2C busses handling */ +#ifdef CONFIG_SOFT_I2C_MULTI_BUS +extern int get_multi_scl_pin(void); +extern int get_multi_sda_pin(void); +extern int multi_i2c_init(void); +#endif #endif /* _I2C_H_ */ diff --git a/include/image.h b/include/image.h index aa9daa2..e5f6649 100644 --- a/include/image.h +++ b/include/image.h @@ -164,6 +164,7 @@ #define IH_TYPE_OMAPIMAGE 12 /* TI OMAP Config Header Image */ #define IH_TYPE_AISIMAGE 13 /* TI Davinci AIS Image */ #define IH_TYPE_KERNEL_NOLOAD 14 /* OS Kernel Image, can run from any load address */ +#define IH_TYPE_PBLIMAGE 15 /* Freescale PBL Boot Image */ /* * Compression Types diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 82704de..f63e04b 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -85,8 +85,10 @@ extern void nand_wait_ready(struct mtd_info *mtd); #define NAND_CMD_RESET 0xff #define NAND_CMD_LOCK 0x2a +#define NAND_CMD_LOCK_TIGHT 0x2c #define NAND_CMD_UNLOCK1 0x23 #define NAND_CMD_UNLOCK2 0x24 +#define NAND_CMD_LOCK_STATUS 0x7a /* Extended commands for large page devices */ #define NAND_CMD_READSTART 0x30 @@ -205,9 +207,6 @@ typedef enum { #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \ && (chip->page_shift > 9)) -/* Mask to zero out the chip options, which come from the id table */ -#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) - /* Non chip related options */ /* * Use a flash based bad block table. OOB identifier is saved in OOB area. @@ -391,9 +390,10 @@ struct nand_ecc_ctrl { * consecutive order. */ struct nand_buffers { - uint8_t ecccalc[NAND_MAX_OOBSIZE]; - uint8_t ecccode[NAND_MAX_OOBSIZE]; - uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; + uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; + uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; + uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, + ARCH_DMA_MINALIGN)]; }; /** diff --git a/include/mmc.h b/include/mmc.h index 7b094a4..a13e2bd 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -160,6 +160,7 @@ #define EXT_CSD_CARD_TYPE 196 /* RO */ #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ +#define EXT_CSD_BOOT_MULT 226 /* RO */ /* * EXT_CSD field definitions diff --git a/include/nand.h b/include/nand.h index c554c55..bbe28b2 100644 --- a/include/nand.h +++ b/include/nand.h @@ -141,11 +141,11 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts); #define NAND_LOCK_STATUS_TIGHT 0x01 -#define NAND_LOCK_STATUS_LOCK 0x02 #define NAND_LOCK_STATUS_UNLOCK 0x04 -int nand_lock( nand_info_t *meminfo, int tight ); -int nand_unlock( nand_info_t *meminfo, ulong start, ulong length ); +int nand_lock(nand_info_t *meminfo, int tight); +int nand_unlock(nand_info_t *meminfo, loff_t start, size_t length, + int allexcept); int nand_get_lock_status(nand_info_t *meminfo, loff_t offset); int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst); diff --git a/include/part.h b/include/part.h index e1478f4..27ea283 100644 --- a/include/part.h +++ b/include/part.h @@ -93,11 +93,15 @@ typedef struct disk_partition { ulong blksz; /* block size in bytes */ uchar name[32]; /* partition name */ uchar type[32]; /* string type description */ + int bootable; /* Active/Bootable flag is set */ +#ifdef CONFIG_PARTITION_UUIDS + char uuid[37]; /* filesystem UUID as string, if exists */ +#endif } disk_partition_t; /* Misc _get_dev functions */ #ifdef CONFIG_PARTITIONS -block_dev_desc_t* get_dev(char* ifname, int dev); +block_dev_desc_t *get_dev(const char *ifname, int dev); block_dev_desc_t* ide_get_dev(int dev); block_dev_desc_t* sata_get_dev(int dev); block_dev_desc_t* scsi_get_dev(int dev); @@ -111,8 +115,14 @@ int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t void print_part (block_dev_desc_t *dev_desc); void init_part (block_dev_desc_t *dev_desc); void dev_print(block_dev_desc_t *dev_desc); +int get_device(const char *ifname, const char *dev_str, + block_dev_desc_t **dev_desc); +int get_device_and_partition(const char *ifname, const char *dev_part_str, + block_dev_desc_t **dev_desc, + disk_partition_t *info, int allow_whole_dev); #else -static inline block_dev_desc_t* get_dev(char* ifname, int dev) { return NULL; } +static inline block_dev_desc_t *get_dev(const char *ifname, int dev) +{ return NULL; } static inline block_dev_desc_t* ide_get_dev(int dev) { return NULL; } static inline block_dev_desc_t* sata_get_dev(int dev) { return NULL; } static inline block_dev_desc_t* scsi_get_dev(int dev) { return NULL; } @@ -126,6 +136,15 @@ static inline int get_partition_info (block_dev_desc_t * dev_desc, int part, static inline void print_part (block_dev_desc_t *dev_desc) {} static inline void init_part (block_dev_desc_t *dev_desc) {} static inline void dev_print(block_dev_desc_t *dev_desc) {} +static inline int get_device(const char *ifname, const char *dev_str, + block_dev_desc_t **dev_desc) +{ return -1; } +static inline int get_device_and_partition(const char *ifname, + const char *dev_part_str, + block_dev_desc_t **dev_desc, + disk_partition_t *info, + int allow_whole_dev) +{ *dev_desc = NULL; return -1; } #endif #ifdef CONFIG_MAC_PARTITION diff --git a/include/reiserfs.h b/include/reiserfs.h index c465b3c..dc89342 100644 --- a/include/reiserfs.h +++ b/include/reiserfs.h @@ -75,7 +75,7 @@ typedef enum } reiserfs_error_t; -extern int reiserfs_set_blk_dev(block_dev_desc_t *rbdd, int part); +extern void reiserfs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); extern int reiserfs_ls (char *dirname); extern int reiserfs_open (char *filename); extern int reiserfs_read (char *buf, unsigned len); diff --git a/include/sdhci.h b/include/sdhci.h index 9d37183..c0345ed 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -76,6 +76,8 @@ #define SDHCI_SPACE_AVAILABLE 0x00000400 #define SDHCI_DATA_AVAILABLE 0x00000800 #define SDHCI_CARD_PRESENT 0x00010000 +#define SDHCI_CARD_STATE_STABLE 0x00020000 +#define SDHCI_CARD_DETECT_PIN_LEVEL 0x00040000 #define SDHCI_WRITE_PROTECT 0x00080000 #define SDHCI_HOST_CONTROL 0x28 @@ -87,7 +89,9 @@ #define SDHCI_CTRL_ADMA1 0x08 #define SDHCI_CTRL_ADMA32 0x10 #define SDHCI_CTRL_ADMA64 0x18 -#define SDHCI_CTRL_8BITBUS 0x20 +#define SDHCI_CTRL_8BITBUS 0x20 +#define SDHCI_CTRL_CD_TEST_INS 0x40 +#define SDHCI_CTRL_CD_TEST 0x80 #define SDHCI_POWER_CONTROL 0x29 #define SDHCI_POWER_ON 0x01 @@ -219,6 +223,7 @@ #define SDHCI_QUIRK_BROKEN_R1B (1 << 2) #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3) #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4) +#define SDHCI_QUIRK_NO_CD (1 << 5) /* to make gcc happy */ struct sdhci_host; @@ -248,8 +253,10 @@ struct sdhci_host { unsigned int clock; struct mmc *mmc; const struct sdhci_ops *ops; + int index; void (*set_control_reg)(struct sdhci_host *host); + void (*set_clock)(int dev_index, unsigned int div); uint voltages; }; diff --git a/include/search.h b/include/search.h index ef53edb..93e1cbc 100644 --- a/include/search.h +++ b/include/search.h @@ -57,13 +57,23 @@ struct hsearch_data { struct _ENTRY *table; unsigned int size; unsigned int filled; +/* + * Callback function which will check whether the given change for variable + * "name" from "oldval" to "newval" may be applied or not, and possibly apply + * such change. + * When (flag & H_FORCE) is set, it shall not print out any error message and + * shall force overwriting of write-once variables. +.* Must return 0 for approval, 1 for denial. + */ + int (*apply)(const char *name, const char *oldval, + const char *newval, int flag); }; /* Create a new hashing table which will at most contain NEL elements. */ extern int hcreate_r(size_t __nel, struct hsearch_data *__htab); /* Destroy current internal hashing table. */ -extern void hdestroy_r(struct hsearch_data *__htab); +extern void hdestroy_r(struct hsearch_data *__htab, int do_apply); /* * Search for entry matching ITEM.key in internal hash table. If @@ -88,17 +98,25 @@ extern int hstrstr_r(const char *__match, int __last_idx, ENTRY ** __retval, struct hsearch_data *__htab); /* Search and delete entry matching ITEM.key in internal hash table. */ -extern int hdelete_r(const char *__key, struct hsearch_data *__htab); +extern int hdelete_r(const char *__key, struct hsearch_data *__htab, + int do_apply); extern ssize_t hexport_r(struct hsearch_data *__htab, const char __sep, char **__resp, size_t __size, int argc, char * const argv[]); +/* + * nvars: length of vars array + * vars: array of strings (variable names) to import (nvars == 0 means all) + * do_apply: whether to call callback function to check the new argument, + * and possibly apply changes (false means accept everything) + */ extern int himport_r(struct hsearch_data *__htab, const char *__env, size_t __size, const char __sep, - int __flag); + int __flag, int nvars, char * const vars[], int do_apply); /* Flags for himport_r() */ -#define H_NOCLEAR 1 /* do not clear hash table before importing */ +#define H_NOCLEAR (1 << 0) /* do not clear hash table before importing */ +#define H_FORCE (1 << 1) /* overwrite read-only/write-once variables */ #endif /* search.h */ diff --git a/include/serial.h b/include/serial.h index cbdf8a9..d76d6df 100644 --- a/include/serial.h +++ b/include/serial.h @@ -31,7 +31,8 @@ extern struct serial_device *default_serial_console(void); defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \ defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \ defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \ - defined(CONFIG_TEGRA20) || defined(CONFIG_SYS_COREBOOT) + defined(CONFIG_TEGRA20) || defined(CONFIG_SYS_COREBOOT) || \ + defined(CONFIG_MICROBLAZE) extern struct serial_device serial0_device; extern struct serial_device serial1_device; #if defined(CONFIG_SYS_NS16550_SERIAL) diff --git a/include/zfs_common.h b/include/zfs_common.h index 04e73d0..3bd575e 100644 --- a/include/zfs_common.h +++ b/include/zfs_common.h @@ -66,9 +66,6 @@ struct zfs_filesystem { block_dev_desc_t *dev_desc; }; - -extern block_dev_desc_t *zfs_dev_desc; - struct device_s { uint64_t part_length; }; @@ -94,8 +91,6 @@ struct zfs_dirhook_info { struct zfs_filesystem *zfsget_fs(void); -int init_fs(block_dev_desc_t *dev_desc); -void deinit_fs(block_dev_desc_t *dev_desc); int zfs_open(zfs_file_t, const char *filename); uint64_t zfs_read(zfs_file_t, char *buf, uint64_t len); struct zfs_data *zfs_mount(device_t); @@ -103,7 +98,7 @@ int zfs_close(zfs_file_t); int zfs_ls(device_t dev, const char *path, int (*hook) (const char *, const struct zfs_dirhook_info *)); int zfs_devread(int sector, int byte_offset, int byte_len, char *buf); -int zfs_set_blk_dev(block_dev_desc_t *rbdd, int part); +void zfs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); void zfs_unmount(struct zfs_data *data); int lzjb_decompress(void *, void *, uint32_t, uint32_t); #endif |