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-rw-r--r--include/asm-ppc/config.h6
-rw-r--r--include/asm-ppc/fsl_law.h31
-rw-r--r--include/asm-ppc/fsl_lbc.h12
-rw-r--r--include/asm-ppc/fsl_pci.h12
-rw-r--r--include/asm-ppc/immap_85xx.h289
-rw-r--r--include/asm-ppc/mmu.h9
-rw-r--r--include/asm-ppc/processor.h4
-rw-r--r--include/configs/MPC8536DS.h2
-rw-r--r--include/configs/MPC8572DS.h4
-rw-r--r--include/configs/P1_P2_RDB.h13
-rw-r--r--include/configs/P2020DS.h4
-rw-r--r--include/configs/SBC8540.h19
-rw-r--r--include/configs/XPEDITE5170.h2
-rw-r--r--include/configs/XPEDITE5200.h2
-rw-r--r--include/configs/XPEDITE5370.h2
-rw-r--r--include/configs/sbc8548.h147
-rw-r--r--include/configs/sbc8560.h17
-rw-r--r--include/e500.h6
18 files changed, 488 insertions, 93 deletions
diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h
index 5670d06..e35b0b7 100644
--- a/include/asm-ppc/config.h
+++ b/include/asm-ppc/config.h
@@ -40,9 +40,11 @@
#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \
defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
-#define CONFIG_MAX_CPUS 2
+#define CONFIG_MAX_CPUS 2
+#elif defined(CONFIG_PPC_P4080)
+#define CONFIG_MAX_CPUS 8
#else
-#define CONFIG_MAX_CPUS 1
+#define CONFIG_MAX_CPUS 1
#endif
#endif /* _ASM_CONFIG_H_ */
diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h
index e06a1a6..31bb754 100644
--- a/include/asm-ppc/fsl_law.h
+++ b/include/asm-ppc/fsl_law.h
@@ -1,8 +1,18 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
#ifndef _FSL_LAW_H_
#define _FSL_LAW_H_
#include <asm/io.h>
+#define LAW_EN 0x80000000
+
#define SET_LAW_ENTRY(idx, a, sz, trgt) \
{ .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
@@ -36,6 +46,25 @@ enum law_size {
LAW_SIZE_32G,
};
+#ifdef CONFIG_FSL_CORENET
+enum law_trgt_if {
+ LAW_TRGT_IF_PCIE_1 = 0x00,
+ LAW_TRGT_IF_PCIE_2 = 0x01,
+ LAW_TRGT_IF_PCIE_3 = 0x02,
+ LAW_TRGT_IF_RIO_1 = 0x08,
+ LAW_TRGT_IF_RIO_2 = 0x09,
+
+ LAW_TRGT_IF_DDR_1 = 0x10,
+ LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */
+ LAW_TRGT_IF_DDR_INTRLV = 0x14,
+
+ LAW_TRGT_IF_BMAN = 0x18,
+ LAW_TRGT_IF_DCSR = 0x1d,
+ LAW_TRGT_IF_LBC = 0x1f,
+ LAW_TRGT_IF_QMAN = 0x3c,
+};
+#define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1
+#else
enum law_trgt_if {
LAW_TRGT_IF_PCI = 0x00,
LAW_TRGT_IF_PCI_2 = 0x01,
@@ -64,6 +93,7 @@ enum law_trgt_if {
#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
#endif
+#endif /* CONFIG_FSL_CORENET */
struct law_entry {
int index;
@@ -76,6 +106,7 @@ extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if
extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id);
+extern struct law_entry find_law(phys_addr_t addr);
extern void disable_law(u8 idx);
extern void init_laws(void);
extern void print_laws(void);
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index a28082e..5723de6 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -311,9 +311,21 @@
*/
#define LCRR_CLKDIV 0x0000001F
#define LCRR_CLKDIV_SHIFT 0
+#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \
+ defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \
+ defined(CONFIG_MPC8560)
#define LCRR_CLKDIV_2 0x00000002
#define LCRR_CLKDIV_4 0x00000004
#define LCRR_CLKDIV_8 0x00000008
+#elif defined(CONFIG_FSL_CORENET)
+#define LCRR_CLKDIV_8 0x00000002
+#define LCRR_CLKDIV_16 0x00000004
+#define LCRR_CLKDIV_32 0x00000008
+#else
+#define LCRR_CLKDIV_4 0x00000002
+#define LCRR_CLKDIV_8 0x00000004
+#define LCRR_CLKDIV_16 0x00000008
+#endif
/* LTEDR - Transfer Error Check Disable Register
*/
diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h
index b9972da..2790da7 100644
--- a/include/asm-ppc/fsl_pci.h
+++ b/include/asm-ppc/fsl_pci.h
@@ -173,6 +173,18 @@ struct fsl_pci_info {
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
struct pci_controller *hose, int busno);
+#define SET_STD_PCI_INFO(x, num) \
+{ \
+ x.regs = CONFIG_SYS_PCI##num##_ADDR; \
+ x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \
+ x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \
+ x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \
+ x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
+ x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
+ x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
+ x.pci_num = num; \
+}
+
#define SET_STD_PCIE_INFO(x, num) \
{ \
x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index e7d412d..100dfe1 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -16,6 +16,29 @@
#include <asm/fsl_i2c.h>
#include <asm/fsl_lbc.h>
+typedef struct ccsr_local {
+ u32 ccsrbarh; /* 0x0 - Control Configuration Status Registers Base Address Register High */
+ u32 ccsrbarl; /* 0x4 - Control Configuration Status Registers Base Address Register Low */
+ u32 ccsrar; /* 0x8 - Configuration, Control, and Status Attribute Register */
+#define CCSRAR_C 0x80000000 /* Commit */
+ u8 res1[4];
+ u32 altcbarh; /* 0x10 - Alternate Configuration Base Address Register High */
+ u32 altcbarl; /* 0x14 - Alternate Configuration Base Address Register Low */
+ u32 altcar; /* 0x18 - Alternate Configuration Attribute Register */
+ u8 res2[4];
+ u32 bstrh; /* 0x20 - Boot space translation register high */
+ u32 bstrl; /* 0x24 - Boot space translation register Low */
+ u32 bstrar; /* 0x28 - Boot space translation attributes register */
+ u8 res3[0xbd4];
+ struct {
+ u32 lawbarh; /* 0xc00 + n * 0x10 - LAW0 base address register high */
+ u32 lawbarl; /* 0xc04 + n * 0x10 - LAW0 base address register low */
+ u32 lawar; /* 0xc08 + n * 0x10 - LAW0 attributes register */
+ u8 res4[4];
+ } law[32];
+ u8 res35[0x204];
+} ccsr_local_t;
+
/*
* Local-Access Registers and ECM Registers(0x0000-0x2000)
*/
@@ -165,7 +188,21 @@ typedef struct ccsr_ddr {
uint debug_2;
uint debug_3;
uint debug_4;
- char res12[240];
+ uint debug_5;
+ uint debug_6;
+ uint debug_7;
+ uint debug_8;
+ uint debug_9;
+ uint debug_10;
+ uint debug_11;
+ uint debug_12;
+ uint debug_13; /* +0xF30 */
+ uint debug_14;
+ uint debug_15;
+ uint debug_16;
+ uint debug_17;
+ uint debug_18; /* +0xF44 */
+ char res12[184];
} ccsr_ddr_t;
/*
@@ -1531,6 +1568,193 @@ typedef struct par_io {
/*
* Global Utilities Register Block(0xe_0000-0xf_ffff)
*/
+#ifdef CONFIG_FSL_CORENET
+typedef struct ccsr_gur {
+ u32 porsr1; /* 0xe0000 - POR status register */
+ u8 res1[28]; /* 0xe0004 - 0xe001c Reserved: PORSRn */
+ u32 gpporcr1; /* 0xe0020 - General-purpose POR configuration register */
+ u8 res2[12];
+ u32 gpiocr; /* 0xe0030 - GPIO control register */
+ u8 res3[12];
+ u32 gpoutdr; /* 0xe0040 - General-purpose output data register */
+ u8 res4[12];
+ u32 gpindr; /* 0xe0050 - General-purpose input data register */
+ u8 res5[12];
+ u32 pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
+ u8 res6[12];
+ u32 devdisr; /* 0xe0070 - Device disable control */
+#define FSL_CORENET_DEVDISR_PCIE1 0x80000000
+#define FSL_CORENET_DEVDISR_PCIE2 0x40000000
+#define FSL_CORENET_DEVDISR_PCIE3 0x20000000
+#define FSL_CORENET_DEVDISR_RMU 0x08000000
+#define FSL_CORENET_DEVDISR_SRIO1 0x04000000
+#define FSL_CORENET_DEVDISR_SRIO2 0x02000000
+#define FSL_CORENET_DEVDISR_DMA1 0x00400000
+#define FSL_CORENET_DEVDISR_DMA2 0x00200000
+#define FSL_CORENET_DEVDISR_DDR1 0x00100000
+#define FSL_CORENET_DEVDISR_DDR2 0x00080000
+#define FSL_CORENET_DEVDISR_DBG 0x00010000
+#define FSL_CORENET_DEVDISR_NAL 0x00008000
+#define FSL_CORENET_DEVDISR_ELBC 0x00001000
+#define FSL_CORENET_DEVDISR_USB1 0x00000800
+#define FSL_CORENET_DEVDISR_USB2 0x00000400
+#define FSL_CORENET_DEVDISR_ESDHC 0x00000100
+#define FSL_CORENET_DEVDISR_GPIO 0x00000080
+#define FSL_CORENET_DEVDISR_ESPI 0x00000040
+#define FSL_CORENET_DEVDISR_I2C1 0x00000020
+#define FSL_CORENET_DEVDISR_I2C2 0x00000010
+#define FSL_CORENET_DEVDISR_DUART1 0x00000002
+#define FSL_CORENET_DEVDISR_DUART2 0x00000001
+ u8 res7[12];
+ u32 powmgtcsr; /* 0xe0080 - Power management status and control register */
+ u8 res8[12];
+ u32 coredisru; /* 0xe0090 - uppper portion for support of 64 cores */
+ u32 coredisrl; /* 0xe0094 - lower portion for support of 64 cores */
+ u8 res9[8];
+ u32 pvr; /* 0xe00a0 - Processor version register */
+ u32 svr; /* 0xe00a4 - System version register */
+ u8 res10[8];
+ u32 rstcr; /* 0xe00b0 - Reset control register */
+ u32 rstrqpblsr; /* 0xe00b4 - Reset request preboot loader status register */
+ u8 res11[8];
+ u32 rstrqmr1; /* 0xe00c0 - Reset request mask register */
+ u8 res12[4]; /* Reserved: RSTRQMR2 */
+ u32 rstrqsr1; /* 0xe00c8 - Reset request status register */
+ u8 res13[4]; /* Reserved: RSTRQSR2 */
+ u8 res14[4]; /* Reserved: RSTRQWDTMRU */
+ u32 rstrqwdtmrl; /* 0xe00d4 - Reset request WDT mask register */
+ u8 res15[4]; /* Reserved: RSTRQWDTSRU */
+ u32 rstrqwdtsrl; /* 0xe00dc - Reset request WDT status register */
+ u8 res16[4]; /* Reserved: BRRU max total of 2 for up to 64 cores */
+ u32 brrl; /* 0xe00e4 Boot release register */
+ u8 res17[24];
+ u32 rcwsr[16]; /* 0xe0100 - 0xe013c: Reset control word status register */
+#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
+#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00008000
+#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 15
+#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
+#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
+#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
+ u8 res18[192]; /* Reserved: RCWSRn (max total of 64)*/
+ u32 scratchrw[4]; /* 0xe0200 - 0xe020c: Scratch Read/Write register */
+ u8 res19[240]; /* Reserved: SCRATCHRWn (max total of 64)*/
+ u32 scratchw1r[4]; /* 0xe0300 - 0xe030c: Scratch Read register (Write once) */
+ u8 res20[240]; /* Reserved: SCRATCHW1Rn (max total of 64)*/
+ u32 scrtsr[8]; /* 0xe0400 - 0xe041c: Core reset status register */
+ u8 res21[224]; /* Reserved: CRSTSRn (max total of 64 for up to 64 cores)*/
+ u32 pex1liodnr; /* 0xe0500 PCI Express 1 Logical I/O Device Number register*/
+ u32 pex2liodnr; /* 0xe0504 PCI Express 2 Logical I/O Device Number register*/
+ u32 pex3liodnr; /* 0xe0508 PCI Express 3 Logical I/O Device Number register*/
+ u32 pex4liodnr; /* 0xe050c PCI Express 4 Logical I/O Device Number register*/
+ u32 rio1liodnr; /* 0xe0510 RIO 1 Logical I/O Device Number register*/
+ u32 rio2liodnr; /* 0xe0514 RIO 2 Logical I/O Device Number register*/
+ u32 rio3liodnr; /* 0xe0518 RIO 3 Logical I/O Device Number register*/
+ u32 rio4liodnr; /* 0xe051c RIO 4 Logical I/O Device Number register*/
+ u32 usb1liodnr; /* 0xe0520 USB 1 Logical I/O Device Number register*/
+ u32 usb2liodnr; /* 0xe0524 USB 2 Logical I/O Device Number register*/
+ u32 usb3liodnr; /* 0xe0528 USB 3 Logical I/O Device Number register*/
+ u32 usb4liodnr; /* 0xe052c USB 4 Logical I/O Device Number register*/
+ u32 sdmmc1liodnr; /* 0xe0530 SD/MMC 1 Logical I/O Device Number register*/
+ u32 sdmmc2liodnr; /* 0xe0534 SD/MMC 2 Logical I/O Device Number register*/
+ u32 sdmmc3liodnr; /* 0xe0538 SD/MMC 3 Logical I/O Device Number register*/
+ u32 sdmmc4liodnr; /* 0xe053c SD/MMC 4 Logical I/O Device Number register*/
+ u32 rmuliodnr; /* 0xe0540 RIO Message Unit Logical I/O Device Number register*/
+ u32 rduliodnr; /* 0xe0544 RIO Doorbell Unit Logical I/O Device Number register*/
+ u32 rpwuliodnr; /* 0xe0548 RIO Port Write Unit Logical I/O Device Number register*/
+ u8 res22[52]; /* Reserved: for future LIODN register expansion */
+ u32 dma1liodnr; /* 0xe0580 DMA 1 Logical I/O Device Number register*/
+ u32 dma2liodnr; /* 0xe0584 DMA 2 Logical I/O Device Number register*/
+ u32 dma3liodnr; /* 0xe0588 DMA 3 Logical I/O Device Number register*/
+ u32 dma4liodnr; /* 0xe058c DMA 4 Logical I/O Device Number register*/
+ u8 res23[48]; /* Reserved: for future LIODN register expansion */
+ u8 res24[64]; /* Reserved */
+ u32 pblsr; /* 0xe0600 Preboot loader status register*/
+ u32 pamubypenr; /* 0xe0604 PAMU bypass enable register*/
+ u32 dmacr1; /* 0xe0608 DMA control register*/
+ u8 res25[4]; /* Reserved: DMACR2 (max total of 2)*/
+ u32 gensr1; /* 0xe0610 General status register*/
+ u8 res26[12]; /* Reserved: GENSRn (max total of 4)*/
+ u32 gencr1; /* 0xe0620 General control register*/
+ u8 res27[12]; /* Reserved: GENCRn (max total of 4)*/
+ u8 res28[4]; /* Reserved: CGENSRU (upper portion for support of 64 cores) */
+ u32 cgensrl; /* 0xe0634 Core general status register*/
+ u8 res29[8]; /* Reserved */
+ u8 res30[4]; /* Reserved: CGENCRU (upper portion for support of 64 cores) */
+ u32 cgencrl; /* 0xe0634 Core general control register*/
+ u8 res31[184]; /* Reserved 0xe0648 - 0xe06fc */
+ u32 sriopstecr; /* 0xe0700 SRIO prescaler timer enable control register*/
+ u8 res32[2300]; /* Reserved 0xe0704 - 0xe0ffc */
+} ccsr_gur_t;
+
+typedef struct ccsr_clk {
+ u32 clkc0csr; /* 0xe1000 - Core 0 Clock control/status register */
+ u8 res1[0x1c];
+ u32 clkc1csr; /* 0xe1020 - Core 1 Clock control/status register */
+ u8 res2[0x1c];
+ u32 clkc2csr; /* 0xe1040 - Core 2 Clock control/status register */
+ u8 res3[0x1c];
+ u32 clkc3csr; /* 0xe1060 - Core 3 Clock control/status register */
+ u8 res4[0x1c];
+ u32 clkc4csr; /* 0xe1080 - Core 4 Clock control/status register */
+ u8 res5[0x1c];
+ u32 clkc5csr; /* 0xe10a0 - Core 5 Clock control/status register */
+ u8 res6[0x1c];
+ u32 clkc6csr; /* 0xe10c0 - Core 6 Clock control/status register */
+ u8 res7[0x1c];
+ u32 clkc7csr; /* 0xe10e0 - Core 7 Clock control/status register */
+ u8 res8[0x71c];
+ u32 pllc1gsr; /* 0xe1800 - Cluster PLL 1 General Status Register */
+ u8 res10[0x1c];
+ u32 pllc2gsr; /* 0xe1820 - Cluster PLL 2 General Status Register */
+ u8 res11[0x1c];
+ u32 pllc3gsr; /* 0xe1840 - Cluster PLL 3 General Status Register */
+ u8 res12[0x1c];
+ u32 pllc4gsr; /* 0xe1860 - Cluster PLL 4 General Status Register */
+ u8 res13[0x39c];
+ u32 pllpgsr; /* 0xe1c00 - Platform PLL General Status Register */
+ u8 res14[0x1c];
+ u32 plldgsr; /* 0xe1c20 - DDR PLL General Status Register */
+ u8 res15[0x3dc];
+} ccsr_clk_t;
+
+typedef struct ccsr_rcpm {
+ u8 res1[4]; /* 0xe2000 - Reserved */
+ u32 cdozsrl; /* 0xe2004 - Core Doze Status Register */
+ u8 res2[4]; /* 0xe2008 - Reserved */
+ u32 cdozcrl; /* 0xe200c - Core Doze Control Register */
+ u8 res3[4]; /* 0xe2010 - Reserved */
+ u32 cnapsrl; /* 0xe2014 - Core Nap Status Register */
+ u8 res4[4]; /* 0xe2018 - Reserved */
+ u32 cnapcrl; /* 0xe201c - Core Nap Control Register */
+ u8 res5[4]; /* 0xe2020 - Reserved */
+ u32 cdozpsrl; /* 0xe2024 - Core Doze Previous Status Register */
+ u8 res6[4]; /* 0xe2028 - Reserved */
+ u32 cdozpcrl; /* 0xe202c - Core Doze Previous Control Register */
+ u8 res7[4]; /* 0xe2030 - Reserved */
+ u32 cwaitsrl; /* 0xe2034 - Core Wait Status Register */
+ u8 res8[8]; /* Reserved */
+ u32 powmgtcsr; /* 0xe2040 - Power Mangement Control & Status Register */
+ u8 res9[12]; /* Reserved */
+ u32 ippdexpcr0; /* 0xe2050 - IP Powerdown Exception Control Register 0 */
+ u8 res10[12]; /* Reserved */
+ u8 res11[4]; /* Reserved */
+ u32 cpmimrl; /* 0xe2064 - Core Power Management Interrupt Masking Register */
+ u8 res12[4]; /* Reserved */
+ u32 cpmcimrl; /* 0xe206c - Core Power Management Critical Interrupt Masking Register */
+ u8 res13[4]; /* Reserved */
+ u32 cpmmcimrl; /* 0xe2074 - Core Power Management Machine Check Interrupt Masking Register */
+ u8 res14[4]; /* Reserved */
+ u32 cpmnmimrl; /* 0xe207c - Core Power Management NMI Masking Register */
+ u8 res15[4]; /* Reserved */
+ u32 ctbenrl; /* 0xe2084 - Core Time Base Enable Register */
+ u8 res16[4]; /* Reserved */
+ u32 ctbclkselrl; /* 0xe208c - Core Time Base Clock Select Register */
+ u8 res17[4]; /* Reserved */
+ u32 ctbhltcrl; /* 0xe2094 - Core Time Base Halt Control Register */
+ u8 res18[0xf68];
+} ccsr_rcpm_t;
+
+#else
typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
#ifdef CONFIG_MPC8536
@@ -1542,6 +1766,8 @@ typedef struct ccsr_gur {
#endif
#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
+#define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
+#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
uint porbmsr; /* 0xe0004 - POR boot mode status register */
#define MPC85xx_PORBMSR_HA 0x00070000
#define MPC85xx_PORBMSR_HA_SHIFT 16
@@ -1645,42 +1871,65 @@ typedef struct ccsr_gur {
uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
char res15[61648]; /* 0xe0f30 to 0xefffff */
} ccsr_gur_t;
+#endif
+
+#ifdef CONFIG_FSL_CORENET
+#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
+#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
+#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000
+#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
+#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
+#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x100000
+#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
+#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
+#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
+#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
+#define CONFIG_SYS_MPC85xx_QMAN_OFFSET 0x318000
+#define CONFIG_SYS_MPC85xx_BMAN_OFFSET 0x31a000
+#else
+#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
+#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000
+#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
+#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000
+#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
+#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
+#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
+#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
+#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
+#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
+#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
+#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
+#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
+#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
+#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
+#define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
+#endif
+
+#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
+#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
-#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000)
+#define CONFIG_SYS_MPC85xx_QMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_QMAN_OFFSET)
+#define CONFIG_SYS_MPC85xx_BMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_BMAN_OFFSET)
#define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
-#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000)
+#define CONFIG_SYS_FSL_CORENET_CCM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_CLK_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
#define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
-#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000)
#define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
-#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000)
#define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
-#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000)
#define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
-#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000)
#define CONFIG_SYS_MPC85xx_ESPI_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
-#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000)
#define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
-#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000)
#define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
-#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0xF000)
-#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
-#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000)
+#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
#define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
-#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000)
#define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
-#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000)
#define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
-#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000)
#define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
-#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000)
#define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
-#define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000)
#define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
-#define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000)
#define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
-#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000)
#define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
-#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100)
#define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
#define CONFIG_SYS_MPC85xx_USB_ADDR \
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index a019d0b..d516d91 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -504,13 +504,7 @@ extern int num_tlb_entries;
#endif
#endif
-#if defined(CONFIG_MPC86xx)
-#define LAWBAR_BASE_ADDR 0x00FFFFFF
-#define LAWAR_TRGT_IF 0x01F00000
-#else
-#define LAWBAR_BASE_ADDR 0x000FFFFF
-#define LAWAR_TRGT_IF 0x00F00000
-#endif
+#ifdef CONFIG_MPC83xx
#define LAWAR_EN 0x80000000
#define LAWAR_SIZE 0x0000003F
@@ -554,6 +548,7 @@ extern int num_tlb_entries;
#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22)
#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23)
#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24)
+#endif
#ifdef CONFIG_440
/* General */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 3764a5a..d009957 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -1031,6 +1031,10 @@
#define SVR_P2010_E 0x80EB00
#define SVR_P2020 0x80E200
#define SVR_P2020_E 0x80EA00
+#define SVR_P4040 0x820100
+#define SVR_P4040_E 0x820900
+#define SVR_P4080 0x820000
+#define SVR_P4080_E 0x820800
#define SVR_8610 0x80A000
#define SVR_8641 0x809000
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 4746e2e..faca805 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -27,7 +27,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#ifdef CONFIG_MPC8536DS_36BIT
+#ifdef CONFIG_MK_36BIT
#define CONFIG_PHYS_64BIT 1
#endif
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 55c1f29..000f8f6 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -27,6 +27,10 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#ifdef CONFIG_MK_36BIT
+#define CONFIG_PHYS_64BIT
+#endif
+
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 6d44d6c..8e97ad0 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -30,6 +30,19 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#ifdef CONFIG_MK_P1011RDB
+#define CONFIG_P1011
+#endif
+#ifdef CONFIG_MK_P1020RDB
+#define CONFIG_P1020
+#endif
+#ifdef CONFIG_MK_P2010RDB
+#define CONFIG_P2010
+#endif
+#ifdef CONFIG_MK_P2020RDB
+#define CONFIG_P2020
+#endif
+
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index 2a2b9ac..b48c199 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -27,6 +27,10 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#ifdef CONFIG_MK_36BIT
+#define CONFIG_PHYS_64BIT
+#endif
+
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index 272b5dd..7cde39b 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -24,22 +24,25 @@
* MA 02111-1307 USA
*/
-/* mpc8560ads board configuration file */
-/* please refer to doc/README.mpc85xx for more info */
-/* make sure you change the MAC address and other network params first,
- * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
+/*
+ * sbc8540 board configuration file.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-#if XXX
-#define DEBUG /* General debug */
-#define ET_DEBUG
+/*
+ * Top level Makefile configuration choices
+ */
+#ifdef CONFIG_MK_66
+#define CONFIG_PCI_66
#endif
+
#define TSEC_DEBUG
-/* High Level Configuration Options */
+/*
+ * High Level Configuration Options
+ */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h
index 242466a..30642cd 100644
--- a/include/configs/XPEDITE5170.h
+++ b/include/configs/XPEDITE5170.h
@@ -122,7 +122,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
*/
-#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_2 | LCRR_EADC_3)
+#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
/*
* NAND flash configuration
diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h
index deda208..d79231b 100644
--- a/include/configs/XPEDITE5200.h
+++ b/include/configs/XPEDITE5200.h
@@ -103,7 +103,7 @@
* 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
*/
-#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
+#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
/*
* NAND flash configuration
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index 3c58ebe..65e1afd 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -116,7 +116,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
* 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
*/
-#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
+#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
/*
* NAND flash configuration
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 838b4db..d10792a 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2007 Wind River Systems <www.windriver.com>
+ * Copyright 2007,2009 Wind River Systems <www.windriver.com>
* Copyright 2007 Embedded Specialties, Inc.
* Copyright 2004, 2007 Freescale Semiconductor.
*
@@ -24,26 +24,49 @@
/*
* sbc8548 board configuration file
- *
- * Please refer to doc/README.sbc85xx for more info.
- *
+ * Please refer to doc/README.sbc8548 for more info.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-/* High Level Configuration Options */
+/*
+ * Top level Makefile configuration choices
+ */
+#ifdef CONFIG_MK_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI1
+#endif
+
+#ifdef CONFIG_MK_66
+#define CONFIG_SYS_CLK_DIV 1
+#endif
+
+#ifdef CONFIG_MK_33
+#define CONFIG_SYS_CLK_DIV 2
+#endif
+
+#ifdef CONFIG_MK_PCIE
+#define CONFIG_PCIE1
+#endif
+
+/*
+ * High Level Configuration Options
+ */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_SBC8548 1 /* SBC8548 board specific */
-#undef CONFIG_PCI /* enable any pci type devices */
-#undef CONFIG_PCI1 /* PCI controller 1 */
-#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
#undef CONFIG_RIO
-#undef CONFIG_PCI2
-#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+
+#ifdef CONFIG_PCI
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
+#endif
+#ifdef CONFIG_PCIE1
+#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+#endif
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@@ -52,7 +75,13 @@
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-#define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */
+/*
+ * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
+ */
+#ifndef CONFIG_SYS_CLK_DIV
+#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */
+#endif
+#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV)
/*
* These can be toggled for performance analysis, otherwise use default.
@@ -164,6 +193,7 @@
*/
#define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
+#define CONFIG_SYS_ALT_FLASH 0xfb800000 /* 64MB "user" flash */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */
#define CONFIG_SYS_BR0_PRELIM 0xff800801
@@ -172,9 +202,10 @@
#define CONFIG_SYS_OR0_PRELIM 0xff806e65
#define CONFIG_SYS_OR6_PRELIM 0xf8006e65
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
+ CONFIG_SYS_ALT_FLASH}
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
@@ -196,13 +227,13 @@
#define CONFIG_SYS_EEPROM_BASE 0xf8b00000
/*
- * SDRAM on the Local Bus
+ * SDRAM on the Local Bus (CS3 and CS4)
*/
#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
/*
- * Base Register 3 and Option Register 3 configure SDRAM.
+ * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
*
* For BR3, need:
@@ -220,7 +251,7 @@
#define CONFIG_SYS_BR3_PRELIM 0xf0001861
/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
*
* For OR3, need:
* 64MB mask for AM, OR3[0:7] = 1111 1100
@@ -235,6 +266,40 @@
#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
+/*
+ * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
+ * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
+ *
+ * For BR4, need:
+ * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
+ * port-size = 32-bits = BR2[19:20] = 11
+ * no parity checking = BR2[21:22] = 00
+ * SDRAM for MSEL = BR2[24:26] = 011
+ * Valid = BR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
+ *
+ */
+
+#define CONFIG_SYS_BR4_PRELIM 0xf4001861
+
+/*
+ * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR4, need:
+ * 64MB mask for AM, OR3[0:7] = 1111 1100
+ * XAM, OR3[17:18] = 11
+ * 10 columns OR3[19-21] = 011
+ * 12 rows OR3[23-25] = 011
+ * EAD set for extra time OR[31] = 0
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
+ */
+
+#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
+
#define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
@@ -274,7 +339,7 @@
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK 400000000 /* get_bus_freq(0) */
+#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
@@ -308,31 +373,27 @@
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
+#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#ifdef CONFIG_PCI2
-#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
-#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
-#endif
+#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
#endif
#ifdef CONFIG_RIO
@@ -343,14 +404,6 @@
#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
#endif
-#ifdef CONFIG_LEGACY
-#define BRIDGE_ID 17
-#define VIA_ID 2
-#else
-#define BRIDGE_ID 28
-#define VIA_ID 4
-#endif
-
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
@@ -359,7 +412,7 @@
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index 46c94bf..a6b15f7 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -24,16 +24,23 @@
* MA 02111-1307 USA
*/
-/* sbc8560 board configuration file */
-/* please refer to doc/README.sbc8560 for more info */
-/* make sure you change the MAC address and other network params first,
- * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
+/*
+ * sbc8560 board configuration file.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-/* High Level Configuration Options */
+/*
+ * Top level Makefile configuration choices
+ */
+#ifdef CONFIG_MK_66
+#define CONFIG_PCI_66
+#endif
+
+/*
+ * High Level Configuration Options
+ */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
diff --git a/include/e500.h b/include/e500.h
index f8c8266..e1708b9 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -15,6 +15,12 @@ typedef struct
unsigned long freqDDRBus;
unsigned long freqLocalBus;
unsigned long freqQE;
+#ifdef CONFIG_SYS_DPAA_FMAN
+ unsigned long freqFMan[CONFIG_SYS_NUM_FMAN];
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+ unsigned long freqPME;
+#endif
} MPC85xx_SYS_INFO;
#endif /* _ASMLANGUAGE */