diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/MPC8315ERDB.h | 95 | ||||
| -rw-r--r-- | include/configs/kmeter1.h | 8 | ||||
| -rw-r--r-- | include/configs/vme8349.h | 98 |
3 files changed, 140 insertions, 61 deletions
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 79376b3..cfed4ca 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -25,6 +25,11 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_MK_NAND +#define CONFIG_NAND_U_BOOT 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0x00100000 +#endif + /* * High Level Configuration Options */ @@ -51,20 +56,29 @@ HRCWL_SVCOD_DIV_2 |\ HRCWL_CSB_TO_CLKIN_2X1 |\ HRCWL_CORE_TO_CSB_3X1) -#define CONFIG_SYS_HRCW_HIGH (\ +#define CONFIG_SYS_HRCW_HIGH_BASE (\ HRCWH_PCI_HOST |\ HRCWH_PCI1_ARBITER_ENABLE |\ HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ HRCWH_BOOTSEQ_DISABLE |\ HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ HRCWH_TSEC1M_IN_RGMII |\ HRCWH_TSEC2M_IN_RGMII |\ HRCWH_BIG_ENDIAN |\ HRCWH_LALE_NORMAL) +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_ROM_LOC_NAND_SP_8BIT |\ + HRCWH_RL_EXT_NAND) +#else +#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY) +#endif + /* * System IO Config */ @@ -79,6 +93,10 @@ */ #define CONFIG_SYS_IMMR 0xE0000000 +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR +#endif + /* * Arbiter Setup */ @@ -161,12 +179,6 @@ */ #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ @@ -200,10 +212,10 @@ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */ -#define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \ +#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ | (2 << BR_PS_SHIFT) /* 16 bit port size */ \ | BR_V ) /* valid */ -#define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ +#define CONFIG_SYS_NOR_OR_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ @@ -223,18 +235,31 @@ /* * NAND Flash on the Local Bus */ -#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ + +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_NAND_BASE 0xFFF00000 +#else +#define CONFIG_SYS_NAND_BASE 0xE0600000 +#endif + #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 + +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 -#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \ +#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V ) /* valid */ -#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ +#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \ | OR_FCM_CSCT \ | OR_FCM_CST \ | OR_FCM_CHT \ @@ -243,9 +268,31 @@ | OR_FCM_EHTR ) /* 0xFFFF8396 */ +#ifdef CONFIG_NAND_U_BOOT +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM +#else +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM +#endif + #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ +#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM +#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM + +#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \ + !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + /* * Serial Port */ @@ -254,7 +301,7 @@ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} @@ -408,7 +455,16 @@ /* * Environment */ -#ifndef CONFIG_SYS_RAMBOOT +#if defined(CONFIG_NAND_U_BOOT) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET (512 * 1024) + #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE + #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) + #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_RANGE) +#elif !defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ @@ -442,7 +498,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_PCI -#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif @@ -504,7 +560,8 @@ /* FLASH: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | \ + BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index bec08da..b023326 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -72,6 +72,14 @@ #define CONFIG_SYS_IMMR 0xE0000000 /* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* * DDR Setup */ #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index f9db73b..dbc15b2 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -35,6 +35,13 @@ #define __CONFIG_H /* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_caddy2 +#define VME_CADDY2 +#endif + +/* * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ @@ -43,6 +50,8 @@ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ +#define CONFIG_MISC_INIT_R + #define CONFIG_PCI /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ @@ -75,7 +84,9 @@ */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ -#undef CONFIG_SPD_EEPROM /* dont use SPD EEPROM for DDR setup*/ +#define CONFIG_SPD_EEPROM +#define SPD_EEPROM_ADDRESS 0x54 +#define CONFIG_SYS_READ_SPD vme8349_read_spd #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ /* @@ -96,54 +107,40 @@ #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING - -/* - * Manually set up DDR parameters - */ -#define CONFIG_SYS_DDR_SIZE 512 /* MB */ - -#if (CONFIG_SYS_DDR_SIZE == 512) -#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10 | \ - CSCONFIG_BANK_BIT_3) -#endif - -/* - * Manually set up DDR parameters - */ -#define CONFIG_SYS_DDR_TIMING_0 0x00220802 -#define CONFIG_SYS_DDR_TIMING_1 0x39377322 -#define CONFIG_SYS_DDR_TIMING_2 0x2f9848ca /* P9-45, tuning? */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuf,no DYN_PWR */ -#define CONFIG_SYS_DDR_MODE 0x07940242 -#define CONFIG_SYS_DDR_MODE2 0x00000000 -/* autocharge,no open page */ -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 -#define CONFIG_SYS_DDR_SDRAM_CFG 0x63000000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x04061000 +#define CONFIG_SYS_DDRCDR 0x80080001 /* * FLASH on the Local Bus */ #define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ -/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ +#ifdef VME_CADDY2 +#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + (2 << BR_PS_SHIFT) | /* 32bit */ \ + BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM 0xffc06ff7 /* 4 MB flash size */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000015 /* 4 MB window size */ +#else +#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ (2 << BR_PS_SHIFT) | /* 32bit */ \ BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM 0xF8006FF7 /* 128 MB flash size */ +#define CONFIG_SYS_OR0_PRELIM 0xf8006ff7 /* 128 MB flash size */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001A /* 128 MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001a /* 128 MB window size */ +#endif +/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ #define CONFIG_SYS_BR1_PRELIM (0xf0000000 | 0x00001801) -#define CONFIG_SYS_OR1_PRELIM (0xffff8000 | 0x00000200) +#define CONFIG_SYS_OR1_PRELIM (0xfffc0008 | 0x00000200) #define CONFIG_SYS_LBLAWBAR1_PRELIM 0xf0000000 -#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x0000000e) +#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x00000011) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ @@ -157,7 +154,7 @@ #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) #define CONFIG_SYS_RAMBOOT #else -#undef CONFIG_SYS_RAMBOOT +#undef CONFIG_SYS_RAMBOOT #endif #define CONFIG_SYS_INIT_RAM_LOCK 1 @@ -174,11 +171,10 @@ /* * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 + * LCRR: no DLL bypass, Clock divider is 4 * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 @@ -268,10 +264,10 @@ #undef PCI_ONE_PCI1 #endif -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - +#ifndef VME_CADDY2 #define CONFIG_NET_MULTI +#endif +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -282,19 +278,26 @@ #define PCI_IDSEL_NUMBER 0xFIXME #endif +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + #endif /* CONFIG_PCI */ /* * TSEC configuration */ +#ifdef VME_CADDY2 +#define CONFIG_E1000 +#else #define CONFIG_TSEC_ENET /* TSEC ethernet support */ +#endif #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI #endif -#define CONFIG_GMII /* MII PHY management */ +#define CONFIG_GMII /* MII PHY management */ #define CONFIG_TSEC1 #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 @@ -312,6 +315,12 @@ #endif /* CONFIG_TSEC_ENET */ +#if defined(CONFIG_E1000) +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI +#endif +#endif + /* * Environment */ @@ -560,7 +569,7 @@ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 9600 #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ @@ -605,4 +614,9 @@ #define CONFIG_BOOTCOMMAND "run flash_self" +#ifndef __ASSEMBLY__ +int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len); +#endif + #endif /* __CONFIG_H */ |