diff options
Diffstat (limited to 'include')
28 files changed, 444 insertions, 1123 deletions
diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index 9cb7a9a..a9106f4 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -20,5 +20,18 @@ #undef CONFIG_CMD_SNTP #undef CONFIG_CMD_TFTPPUT #undef CONFIG_CMD_TFTPSRV +#undef CONFIG_OF_CONTROL + +#ifndef CONFIG_SPL_DM +#undef CONFIG_DM_SERIAL +#undef CONFIG_DM_GPIO +#undef CONFIG_DM_I2C +#undef CONFIG_DM_SPI +#endif + +#undef CONFIG_DM_WARN +#undef CONFIG_DM_DEVICE_REMOVE +#undef CONFIG_DM_STDIO + #endif /* CONFIG_SPL_BUILD */ #endif /* __CONFIG_UNCMD_SPL_H__ */ diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h deleted file mode 100644 index 0d3cf36..0000000 --- a/include/configs/a320evb.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * Configuation settings for the Faraday A320 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/a320.h> - -/* - * mach-type definition - */ -#define MACH_TYPE_FARADAY 758 -#define CONFIG_MACH_TYPE MACH_TYPE_FARADAY - -/* - * Linux kernel tagged list - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -/* - * CPU and Board Configuration Options - */ -#undef CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Power Management Unit - */ -#define CONFIG_FTPMU010_POWER - -/* - * Timer - */ - -/* - * Real Time Clock - */ -#define CONFIG_RTC_FTRTC010 - -/* - * Serial console configuration - */ - -/* FTUART is a high speed NS 16C550A compatible UART */ -#define CONFIG_BAUDRATE 38400 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_COM1 0x98200000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_CLK 18432000 - -/* - * Ethernet - */ -#define CONFIG_FTMAC100 - -#define CONFIG_BOOTDELAY 3 - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_PING - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) - -/* - * SDRAM controller configuration - */ -#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \ - FTSDMC020_TP0_TRP(1) | \ - FTSDMC020_TP0_TRCD(1) | \ - FTSDMC020_TP0_TRF(3) | \ - FTSDMC020_TP0_TWR(1) | \ - FTSDMC020_TP0_TCL(2)) - -#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \ - FTSDMC020_TP1_INI_REFT(8) | \ - FTSDMC020_TP1_REF_INTV(0x180)) - -#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \ - FTSDMC020_BANK_DDW_X16 | \ - FTSDMC020_BANK_DSZ_256M | \ - FTSDMC020_BANK_MBW_32 | \ - FTSDMC020_BANK_SIZE_64M) - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Load address and memory test area should agree with - * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself. - */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x2000000) - -/* memtest works on 63 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x3F00000) - -#define CONFIG_SYS_TEXT_BASE 0 - -/* - * Static memory controller configuration - */ - -#define CONFIG_FTSMC020 -#include <faraday/ftsmc020.h> - -#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ - FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ - FTSMC020_BANK_SIZE_1M | \ - FTSMC020_BANK_MBW_8) - -#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \ - FTSMC020_TPR_AST(3) | \ - FTSMC020_TPR_CTW(3) | \ - FTSMC020_TPR_ATI(0xf) | \ - FTSMC020_TPR_AT2(3) | \ - FTSMC020_TPR_WTC(3) | \ - FTSMC020_TPR_AHT(3) | \ - FTSMC020_TPR_TRNA(0xf)) - -#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \ - FTSMC020_BANK_BASE(PHYS_FLASH_2) | \ - FTSMC020_BANK_SIZE_32M | \ - FTSMC020_BANK_MBW_32) - -#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \ - FTSMC020_TPR_CTW(3) | \ - FTSMC020_TPR_ATI(0xf) | \ - FTSMC020_TPR_AT2(3) | \ - FTSMC020_TPR_WTC(3) | \ - FTSMC020_TPR_AHT(3) | \ - FTSMC020_TPR_TRNA(0xf)) - -#define CONFIG_SYS_FTSMC020_CONFIGS { \ - { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ - { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ -} - -/* - * FLASH and environment organization - */ - -/* use CFI framework */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -/* support JEDEC */ -#define CONFIG_FLASH_CFI_LEGACY -#define CONFIG_SYS_FLASH_LEGACY_512Kx8 - -#define PHYS_FLASH_1 0x00000000 -#define PHYS_FLASH_2 0x00400000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, } - -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 - -/* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 - -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -#undef CONFIG_SYS_FLASH_EMPTY_INFO - -/* environments */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) -#define CONFIG_ENV_SIZE 0x20000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h deleted file mode 100644 index 1cb54b3..0000000 --- a/include/configs/cm4008.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * (C) Copyright 2004 - * Greg Ungerer <greg.ungerer@opengear.com>. - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_KS8695 1 /* it is a KS8695 CPU */ -#define CONFIG_CM4008 1 /* it is an OpenGear CM4008 boad */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ - -/* - * select serial console configuration - */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_KS8695_SERIAL -#define CONFIG_SERIAL1 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#undef CONFIG_CMD_SAVEENV - - -#define CONFIG_BOOTDELAY 0 -#define CONFIG_BOOTARGS "mem=16M console=ttyAM0,115200" -#define CONFIG_BOOTCOMMAND "gofsk 0x02200000" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -#define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */ - -#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h deleted file mode 100644 index adebd4b..0000000 --- a/include/configs/cm41xx.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * (C) Copyright 2005 - * Greg Ungerer <greg.ungerer@opengear.com>. - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_KS8695 1 /* it is a KS8695 CPU */ -#define CONFIG_CM41xx 1 /* it is an OpenGear CM41xx boad */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ - -/* - * select serial console configuration - */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_KS8695_SERIAL -#define CONFIG_SERIAL1 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#undef CONFIG_CMD_SAVEENV - - -#define CONFIG_BOOTDELAY 0 -#define CONFIG_BOOTARGS "mem=32M console=ttyAM0,115200" -#define CONFIG_BOOTCOMMAND "gofsk 0x02200000" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -#define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */ - -#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/dkb.h b/include/configs/dkb.h deleted file mode 100644 index 7ffbb14..0000000 --- a/include/configs/dkb.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Lei Wen <leiwen@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_DKB_H -#define __CONFIG_DKB_H - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nMarvell-TTC DKB" - -/* - * High Level Configuration Options - */ -#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */ -#define CONFIG_PANTHEON 1 /* SOC Family Name */ -#define CONFIG_MACH_TTC_DKB 1 /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000) -#define CONFIG_NR_DRAM_BANKS_MAX 2 - -/* - * Commands configuration - */ -#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ -#include <config_cmd_default.h> -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MMC -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -#undef CONFIG_ARCH_MISC_INIT - -/* - * Environment variables configurations - */ -#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ -#define CONFIG_ENV_SIZE 0x20000 /* 64k */ - -#endif /* __CONFIG_DKB_H */ diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h deleted file mode 100644 index 1d78e72..0000000 --- a/include/configs/hawkboard.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * Based on davinci_dvevm.h. Original Copyrights follow: - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Board - */ -#define CONFIG_SYS_USE_NAND 1 - -/* - * SoC Configuration - */ -#define CONFIG_MACH_DAVINCI_HAWK -#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ -#define CONFIG_SOC_DA850 /* TI DA850 SoC */ -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH -#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_AIS_CONFIG_FILE "board/$(BOARDDIR)/hawkboard-ais-nand.cfg" - -#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ - DAVINCI_SYSCFG_SUSPSRC_EMAC | \ - DAVINCI_SYSCFG_SUSPSRC_I2C | \ - DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ - DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ - DAVINCI_SYSCFG_SUSPSRC_UART2) - -#if defined(CONFIG_UART_U_BOOT) -#define CONFIG_SYS_TEXT_BASE 0xc1080000 -#elif !defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_TEXT_BASE 0xc1180000 -#endif - -/* Spl */ -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SPL_LIBGENERIC_SUPPORT /* for udelay and __div64_32 for NAND */ -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-hawk.lds" -#define CONFIG_SPL_TEXT_BASE 0xc1080000 -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR - -/* - * Memory Info - */ -#define CONFIG_SYS_MALLOC_LEN (1*1024*1024) /* malloc() len */ -#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE -#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 -\ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MONITOR_LEN 0x60000 - -/* memtest start addr */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1) - -/* memtest will be run on 16MB */ -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024) - -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ - -/* - * Serial Driver info - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* - * Network & Ethernet Configuration - */ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_MII -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 - -/* - * Nand Flash - */ -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE -#define CONFIG_CLE_MASK 0x10 -#define CONFIG_ALE_MASK 0x8 -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST -#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST /* SPL nand driver configuration */ -#define CFG_DAVINCI_STD_NAND_LAYOUT -#define CONFIG_SYS_NAND_CS 3 -#define CONFIG_SYS_NAND_PAGE_2K -/* Max number of NAND devices */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE_LIST { 0x62000000, } -/* Block 0--not used by bootcode */ -#define CONFIG_ENV_OFFSET 0x0 - -#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0xe0000 -#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1180000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ - CONFIG_SYS_NAND_U_BOOT_SIZE - \ - CONFIG_SYS_MALLOC_LEN - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_NAND_ECCPOS { \ - 24, 25, 26, 27, 28, \ - 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ - 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ - 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ - 59, 60, 61, 62, 63 } -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 10 -#define CONFIG_SYS_NAND_OOBSIZE 64 - -#endif /* CONFIG_SYS_USE_NAND */ - -/* USB Configs */ -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_USB_OHCI_NEW -#define CONFIG_USB_OHCI_DA8XX -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x01E25000 -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "hawkboard" - -/* - * U-Boot general configuration - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_PROMPT "hawkboard > " /* Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC - -/* - * Linux Information - */ -#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100) -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS \ - "mem=128M console=ttyS2,115200n8 root=/dev/ram0 rw initrd=0xc1180000,"\ - "4M ip=static" -#define CONFIG_BOOTDELAY 3 - -/* - * U-Boot commands - */ -#include <config_cmd_default.h> -#define CONFIG_CMD_ENV -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_USB -#define CONFIG_CMD_EXT2 - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#ifdef CONFIG_SYS_USE_NAND -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_IMLS -#define CONFIG_CMD_NAND -#endif - -#ifndef CONFIG_DRIVER_TI_EMAC -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_DHCP -#undef CONFIG_CMD_MII -#undef CONFIG_CMD_PING -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 4195fa3..49039d6 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -18,6 +18,8 @@ #define CONFIG_MX31 /* This is a mx31 */ #define CONFIG_MX31_CLK32 32000 +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h deleted file mode 100644 index 8175621..0000000 --- a/include/configs/jadecpu.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * (C) Copyright 2010 - * Matthias Weisser <weisserm@arcor.de> - * - * Configuation settings for the jadecpu board - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MB86R0x -#define CONFIG_MB86R0x_IOCLK get_bus_freq(0) -#define CONFIG_SYS_TEXT_BASE 0x10000000 - - -#define CONFIG_USE_ARCH_MEMCPY -#define CONFIG_USE_ARCH_MEMSET - -#define MACH_TYPE_JADECPU 2636 - -#define CONFIG_MACH_TYPE MACH_TYPE_JADECPU - -/* - * Environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "gs_fast_boot=setenv bootdelay 5\0" \ - "gs_slow_boot=setenv bootdelay 10\0" \ - "bootcmd=dcache off; mw.l 0x40000000 0 1024; usb start;" \ - "fatls usb 0; fatload usb 0 0x40000000 jadecpu-init.bin;" \ - "bootelf 0x40000000\0" \ - "" - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_BOARD_LATE_INIT - -/* - * Compressions - */ -#define CONFIG_LZO - -/* - * Hardware drivers - */ - -/* - * Serial - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SYS_NS16550_COM1 0xfffe1000 /* UART 0 */ -#define CONFIG_SYS_NS16550_COM2 0xfff50000 /* UART 2 */ -#define CONFIG_SYS_NS16550_COM3 0xfff51000 /* UART 3 */ -#define CONFIG_SYS_NS16550_COM4 0xfff43000 /* UART 4 */ - -#define CONFIG_CONS_INDEX 4 - -/* - * Ethernet - */ -#define CONFIG_SMC911X -#define CONFIG_SMC911X_BASE 0x02000000 -#define CONFIG_SMC911X_16_BIT - -/* - * Video - */ -#define CONFIG_VIDEO -#define CONFIG_VIDEO_MB86R0xGDC -#define CONFIG_SYS_WHITE_ON_BLACK -#define CONFIG_CFB_CONSOLE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE -#define CONFIG_VIDEO_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (800*480 + 256*4 + 10*1024) -#define VIDEO_FB_16BPP_WORD_SWAP -#define VIDEO_KBD_INIT_FCT 0 -#define VIDEO_TSTC_FCT serial_stub_tstc -#define VIDEO_GETC_FCT serial_stub_getc - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 -#define CONFIG_BOOTP_BOOTPATH 1 -#define CONFIG_BOOTP_GATEWAY 1 -#define CONFIG_BOOTP_HOSTNAME 1 - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_SOURCE -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG - -#define CONFIG_CMD_BMP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB -#define CONFIG_CMD_CACHE - -#define CONFIG_SYS_HUSH_PARSER - -/* USB */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0xFFF81000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mb86r0x" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION - -/* SDRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x40000000 /* Start address of DDRRAM */ -#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_SP_ADDR 0x01008000 - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE 0x10000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE (128 * 1024) - -/* - * CFI FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */ - -#define CONFIG_SYS_LOAD_ADDR 0x40000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024)) -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE) - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_PROMPT "jade> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 - -#define CONFIG_PREBOOT "" - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "delaygs" -#define CONFIG_AUTOBOOT_STOP_STR "stopgs" - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (10 << 20) -#define CONFIG_SYS_MEM_TOP_HIDE (4 << 20) - -/* - * Clock reset generator init - */ -#define CONFIG_SYS_CRG_CRHA_INIT 0xffff -#define CONFIG_SYS_CRG_CRPA_INIT 0xffff -#define CONFIG_SYS_CRG_CRPB_INIT 0xfffe -#define CONFIG_SYS_CRG_CRHB_INIT 0xffff -#define CONFIG_SYS_CRG_CRAM_INIT 0xffef - -/* - * Memory controller settings - */ -#define CONFIG_SYS_MEMC_MCFMODE0_INIT 0x00000001 /* 16bit */ -#define CONFIG_SYS_MEMC_MCFMODE2_INIT 0x00000001 /* 16bit */ -#define CONFIG_SYS_MEMC_MCFMODE4_INIT 0x00000021 /* 16bit, Page*/ -#define CONFIG_SYS_MEMC_MCFTIM0_INIT 0x16191008 -#define CONFIG_SYS_MEMC_MCFTIM2_INIT 0x03061008 -#define CONFIG_SYS_MEMC_MCFTIM4_INIT 0x03061804 -#define CONFIG_SYS_MEMC_MCFAREA0_INIT 0x000000c0 /* 0x0c000000 1MB */ -#define CONFIG_SYS_MEMC_MCFAREA2_INIT 0x00000020 /* 0x02000000 1MB */ -#define CONFIG_SYS_MEMC_MCFAREA4_INIT 0x001f0000 /* 0x10000000 32 MB */ - -/* - * DDR2 controller init settings - */ -#define CONFIG_SYS_DDR2_DRIMS_INIT 0x5555 -#define CONFIG_SYS_CCNT_CDCRC_INIT_1 0x00000002 -#define CONFIG_SYS_CCNT_CDCRC_INIT_2 0x00000003 -#define CONFIG_SYS_DDR2_DRIC1_INIT 0x003f -#define CONFIG_SYS_DDR2_DRIC2_INIT 0x0000 -#define CONFIG_SYS_DDR2_DRCA_INIT 0xc124 /* 512Mbit DDR2SDRAM x 2 */ -#define CONFIG_SYS_DDR2_DRCM_INIT 0x0032 -#define CONFIG_SYS_DDR2_DRCST1_INIT 0x3418 -#define CONFIG_SYS_DDR2_DRCST2_INIT 0x6e32 -#define CONFIG_SYS_DDR2_DRCR_INIT 0x0141 -#define CONFIG_SYS_DDR2_DRCF_INIT 0x0002 -#define CONFIG_SYS_DDR2_DRASR_INIT 0x0001 -#define CONFIG_SYS_DDR2_DROBS_INIT 0x0001 -#define CONFIG_SYS_DDR2_DROABA_INIT 0x0103 -#define CONFIG_SYS_DDR2_DRIBSODT1_INIT 0x003F -#define CONFIG_SYS_DDR2_DROS_INIT 0x0001 - -/* - * DRAM init sequence - */ - -/* PALL Command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_1 0x0017 -#define CONFIG_SYS_DDR2_INIT_DRIC2_1 0x0400 - -/* EMR(2) command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_2 0x0006 -#define CONFIG_SYS_DDR2_INIT_DRIC2_2 0x0000 - -/* EMR(3) command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_3 0x0007 -#define CONFIG_SYS_DDR2_INIT_DRIC2_3 0x0000 - -/* EMR(1) command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_4 0x0005 -#define CONFIG_SYS_DDR2_INIT_DRIC2_4 0x0000 - -/* MRS command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_5 0x0004 -#define CONFIG_SYS_DDR2_INIT_DRIC2_5 0x0532 - -/* PALL command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_6 0x0017 -#define CONFIG_SYS_DDR2_INIT_DRIC2_6 0x0400 - -/* REF command 1 */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_7 0x000f -#define CONFIG_SYS_DDR2_INIT_DRIC2_7 0x0000 - -/* MRS command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_8 0x0004 -#define CONFIG_SYS_DDR2_INIT_DRIC2_8 0x0432 - -/* EMR(1) command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_9 0x0005 -#define CONFIG_SYS_DDR2_INIT_DRIC2_9 0x0380 - -/* EMR(1) command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_10 0x0005 -#define CONFIG_SYS_DDR2_INIT_DRIC2_10 0x0002 - -#endif /* __CONFIG_H */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 2874ccc..3dc4da3 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -510,6 +510,30 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" +#define CONFIG_SYS_PCI_64BIT + +#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 +#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ +#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 +#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ + +#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 +#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 +#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 +#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP +#define CONFIG_E1000 +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 0a0bb5f..a13876b 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -303,6 +303,30 @@ #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" +#define CONFIG_SYS_PCI_64BIT + +#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 +#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ +#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 +#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ + +#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 +#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 +#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 +#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP +#define CONFIG_E1000 +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 6fe032c..17a1cde 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -13,6 +13,7 @@ #define CONFIG_FSL_LSCH3 #define CONFIG_LS2085A #define CONFIG_GICV3 +#define CONFIG_FSL_TZPC_BP147 /* Link Definitions */ #define CONFIG_SYS_TEXT_BASE 0x30001000 @@ -26,9 +27,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_IDENT_STRING " LS2085A-EMU" -#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU" - /* Flat Device Tree Definitions */ #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP @@ -209,12 +207,10 @@ #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) #define CONFIG_SYS_LS_MC_FW_IN_NOR #define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL -/* TODO Actual FW length needs to be determined at runtime from FW header */ -#define CONFIG_SYS_LS_MC_FW_LENGTH (4U * 1024 * 1024) #define CONFIG_SYS_LS_MC_DPL_IN_NOR #define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ -#define CONFIG_SYS_LS_MC_DPL_LENGTH 4096 +#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH (256 * 1024) #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0xe00000 /* Carve the MC private DRAM block from the end of DRAM */ @@ -248,7 +244,8 @@ /* Physical Memory Map */ /* fixme: these need to be checked against the board */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_SYS_CLK_FREQ 133333333 +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 133333333 #define CONFIG_NR_DRAM_BANKS 3 @@ -268,12 +265,14 @@ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_start=0x581200000\0" \ - "kernel_load=0x806f0000\0" \ + "kernel_load=0xa0000000\0" \ "kernel_size=0x1000000\0" \ "console=ttyAMA0,38400n8\0" -#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ - "earlyprintk=uart8250-8bit,0x21c0600" +#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ + "earlycon=uart8250,mmio,0x21c0600,115200 " \ + "default_hugepagesz=2m hugepagesz=2m " \ + "hugepages=16" #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ "$kernel_size && bootm $kernel_load" #define CONFIG_BOOTDELAY 1 diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2085a_emu.h index 487cd99..a02d694 100644 --- a/include/configs/ls2085a_emu.h +++ b/include/configs/ls2085a_emu.h @@ -9,6 +9,9 @@ #include "ls2085a_common.h" +#define CONFIG_IDENT_STRING " LS2085A-EMU" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU" + #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */ #define SPD_EEPROM_ADDRESS1 0x51 @@ -17,4 +20,5 @@ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */ +#define CONFIG_FSL_DDR_SYNC_REFRESH #endif /* __LS2_EMU_H */ diff --git a/include/configs/ls2085a_simu.h b/include/configs/ls2085a_simu.h index 0f40b78..af34f3f 100644 --- a/include/configs/ls2085a_simu.h +++ b/include/configs/ls2085a_simu.h @@ -9,6 +9,9 @@ #include "ls2085a_common.h" +#define CONFIG_IDENT_STRING " LS2085A-SIMU" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-SIMU" + /* SMSC 91C111 ethernet configuration */ #define CONFIG_SMC91111 #define CONFIG_SMC91111_BASE (0x2210000) diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index 0f4bd91..bed071f 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -14,6 +14,8 @@ /* High Level Configuration Options */ #define CONFIG_MX31 1 /* This is a mx31 */ +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index e0528ce..29b72b2 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -28,6 +28,8 @@ #define CONFIG_SYS_PL310_BASE L2_PL310_BASE #endif +#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE + #define CONFIG_MP #define CONFIG_MXC_GPT_HCLK diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h deleted file mode 100644 index 00a1a9e..0000000 --- a/include/configs/tnetv107x_evm.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (C) 2008 Texas Instruments, Inc <www.ti.com> - * - * Based on davinci_dvevm.h. Original Copyrights follow: - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/sizes.h> -#include <asm/arch/hardware.h> -#include <asm/arch/clock.h> - -/* Architecture, CPU, etc */ -#define CONFIG_TNETV107X -#define CONFIG_TNETV107X_EVM -#define CONFIG_TNETV107X_WATCHDOG -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_DISABLE_TCM -#define CONFIG_PERIPORT_REMAP -#define CONFIG_PERIPORT_BASE 0x2000000 -#define CONFIG_PERIPORT_SIZE 0x10 -#define CONFIG_SYS_CLK_FREQ clk_get_rate(TNETV107X_LPSC_ARM) - -#define CONFIG_SYS_TIMERBASE TNETV107X_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get_rate(TNETV107X_LPSC_TIMER0) - -#define CONFIG_PLL_SYS_EXT_FREQ 25000000 -#define CONFIG_PLL_TDM_EXT_FREQ 19200000 -#define CONFIG_PLL_ETH_EXT_FREQ 25000000 - -/* Memory Info */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) -#define PHYS_SDRAM_1 TNETV107X_DDR_EMIF_DATA_BASE -#define PHYS_SDRAM_1_SIZE 0x04000000 -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024) -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* Serial Driver Info */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 TNETV107X_UART1_BASE -#define CONFIG_SYS_NS16550_CLK clk_get_rate(TNETV107X_LPSC_UART1) -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* Flash and environment info */ -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_NAND_DAVINCI -#define CONFIG_ENV_SIZE (SZ_128K) -#define CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_NAND_1BIT_ECC -#define CONFIG_SYS_NAND_CS 2 -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_BASE TNETV107X_ASYNC_EMIF_DATA_CE0_BASE -#define CONFIG_SYS_NAND_MASK_CLE 0x10 -#define CONFIG_SYS_NAND_MASK_ALE 0x8 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_PARTITIONS -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE -#define CONFIG_JFFS2_NAND -#define CONFIG_ENV_OFFSET 0x180000 - -/* - * davinci_nand is a bit of a misnomer since this particular EMIF block is - * commonly used across multiple TI devices. Unfortunately, this misnomer - * (amongst others) carries forward into the kernel too. Consequently, if we - * use a different device name here, the mtdparts variable won't be usable as - * a kernel command-line argument. - */ -#define MTDIDS_DEFAULT "nand0=davinci_nand.0" -#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \ - "1536k(uboot)ro," \ - "128k(params)ro," \ - "4m(kernel)," \ - "-(filesystem)" - -/* General U-Boot configuration */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_SYS_PROMPT "U-Boot > " -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_MEMTEST_START + \ - 0x700000) -#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100) -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS "mem=32M console=ttyS1,115200n8 " \ - "root=/dev/mmcblk0p1 rw noinitrd" -#define CONFIG_BOOTCOMMAND "" -#define CONFIG_BOOTDELAY 1 - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EDITENV -#define CONFIG_CMD_IMI -#define CONFIG_CMD_ITEST -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_SOURCE -#define CONFIG_CMD_ENV -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NAND -#define CONFIG_CMD_JFFS2 - -#endif /* __CONFIG_H */ diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index 356ac88..342fa2c 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -15,6 +15,8 @@ #define CONFIG_MX25 #define CONFIG_SYS_TEXT_BASE 0xA0000000 +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_SYS_TIMER_RATE 32768 #define CONFIG_SYS_TIMER_COUNTER \ (&((struct gpt_regs *)IMX_GPT1_BASE)->counter) diff --git a/include/fsl-mc/fsl_dpmng.h b/include/fsl-mc/fsl_dpmng.h new file mode 100644 index 0000000..c2e1ddd --- /dev/null +++ b/include/fsl-mc/fsl_dpmng.h @@ -0,0 +1,121 @@ +/* Copyright 2014 Freescale Semiconductor Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/*! + * @file fsl_dpmng.h + * @brief Management Complex General API + */ + +#ifndef __FSL_DPMNG_H +#define __FSL_DPMNG_H + +/*! + * @Group grp_dpmng Management Complex General API + * + * @brief Contains general API for the Management Complex firmware + * @{ + */ + +struct fsl_mc_io; + +/** + * @brief Management Complex firmware version information + */ +#define MC_VER_MAJOR 4 +#define MC_VER_MINOR 0 + +struct mc_version { + uint32_t major; + /*!< Major version number: incremented on API compatibility changes */ + uint32_t minor; + /*!< Minor version number: incremented on API additions (that are + * backward compatible); reset when major version is incremented + */ + uint32_t revision; + /*!< Internal revision number: incremented on implementation changes + * and/or bug fixes that have no impact on API + */ +}; + +/** + * @brief Retrieves the Management Complex firmware version information + * + * @param[in] mc_io Pointer to opaque I/O object + * @param[out] mc_ver_info Pointer to version information structure + * + * @returns '0' on Success; Error code otherwise. + */ +int mc_get_version(struct fsl_mc_io *mc_io, struct mc_version *mc_ver_info); + +/** + * @brief Resets an AIOP tile + * + * @param[in] mc_io Pointer to opaque I/O object + * @param[in] container_id AIOP container ID + * @param[in] aiop_tile_id AIOP tile ID to reset + * + * @returns '0' on Success; Error code otherwise. + */ +int dpmng_reset_aiop(struct fsl_mc_io *mc_io, + int container_id, + int aiop_tile_id); + +/** + * @brief Loads an image to AIOP tile + * + * @param[in] mc_io Pointer to opaque I/O object + * @param[in] container_id AIOP container ID + * @param[in] aiop_tile_id AIOP tile ID to reset + * @param[in] img_iova I/O virtual address of AIOP ELF image + * @param[in] img_size Size of AIOP ELF image in memory (in bytes) + * + * @returns '0' on Success; Error code otherwise. + */ +int dpmng_load_aiop(struct fsl_mc_io *mc_io, + int container_id, + int aiop_tile_id, + uint64_t img_iova, + uint32_t img_size); + +/** + * @brief AIOP run configuration + */ +struct dpmng_aiop_run_cfg { + uint32_t cores_mask; + /*!< Mask of AIOP cores to run (core 0 in most significant bit) */ + uint64_t options; + /*!< Execution options (currently none defined) */ +}; + +/** + * @brief Starts AIOP tile execution + * + * @param[in] mc_io Pointer to MC portal's I/O object + * @param[in] container_id AIOP container ID + * @param[in] aiop_tile_id AIOP tile ID to reset + * @param[in] cfg AIOP run configuration + * + * @returns '0' on Success; Error code otherwise. + */ +int dpmng_run_aiop(struct fsl_mc_io *mc_io, + int container_id, + int aiop_tile_id, + const struct dpmng_aiop_run_cfg *cfg); + +/** + * @brief Resets MC portal + * + * This function closes all object handles (tokens) that are currently + * open in the MC portal on which the command is submitted. This allows + * cleanup of stale handles that belong to non-functional user processes. + * + * @param[in] mc_io Pointer to MC portal's I/O object + * + * @returns '0' on Success; Error code otherwise. + */ +int dpmng_reset_mc_portal(struct fsl_mc_io *mc_io); + +/** @} */ + +#endif /* __FSL_DPMNG_H */ diff --git a/include/fsl_mc.h b/include/fsl-mc/fsl_mc.h index b9f089e..b9f089e 100644 --- a/include/fsl_mc.h +++ b/include/fsl-mc/fsl_mc.h diff --git a/include/fsl-mc/fsl_mc_cmd.h b/include/fsl-mc/fsl_mc_cmd.h new file mode 100644 index 0000000..e7fcb5b --- /dev/null +++ b/include/fsl-mc/fsl_mc_cmd.h @@ -0,0 +1,132 @@ +/* Copyright 2014 Freescale Semiconductor Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __FSL_MC_CMD_H +#define __FSL_MC_CMD_H + +#define MC_CMD_NUM_OF_PARAMS 7 + +#define MAKE_UMASK64(_width) \ + ((uint64_t)((_width) < 64 ? ((uint64_t)1 << (_width)) - 1 : -1)) + +static inline uint64_t u64_enc(int lsoffset, int width, uint64_t val) +{ + return (uint64_t)(((uint64_t)val & MAKE_UMASK64(width)) << lsoffset); +} +static inline uint64_t u64_dec(uint64_t val, int lsoffset, int width) +{ + return (uint64_t)((val >> lsoffset) & MAKE_UMASK64(width)); +} + +struct mc_command { + uint64_t header; + uint64_t params[MC_CMD_NUM_OF_PARAMS]; +}; + +enum mc_cmd_status { + MC_CMD_STATUS_OK = 0x0, /*!< Completed successfully */ + MC_CMD_STATUS_READY = 0x1, /*!< Ready to be processed */ + MC_CMD_STATUS_AUTH_ERR = 0x3, /*!< Authentication error */ + MC_CMD_STATUS_NO_PRIVILEGE = 0x4, /*!< No privilege */ + MC_CMD_STATUS_DMA_ERR = 0x5, /*!< DMA or I/O error */ + MC_CMD_STATUS_CONFIG_ERR = 0x6, /*!< Configuration error */ + MC_CMD_STATUS_TIMEOUT = 0x7, /*!< Operation timed out */ + MC_CMD_STATUS_NO_RESOURCE = 0x8, /*!< No resources */ + MC_CMD_STATUS_NO_MEMORY = 0x9, /*!< No memory available */ + MC_CMD_STATUS_BUSY = 0xA, /*!< Device is busy */ + MC_CMD_STATUS_UNSUPPORTED_OP = 0xB, /*!< Unsupported operation */ + MC_CMD_STATUS_INVALID_STATE = 0xC /*!< Invalid state */ +}; + +#define MC_CMD_HDR_CMDID_O 52 /* Command ID field offset */ +#define MC_CMD_HDR_CMDID_S 12 /* Command ID field size */ +#define MC_CMD_HDR_AUTHID_O 38 /* Authentication ID field offset */ +#define MC_CMD_HDR_AUTHID_S 10 /* Authentication ID field size */ +#define MC_CMD_HDR_STATUS_O 16 /* Status field offset */ +#define MC_CMD_HDR_STATUS_S 8 /* Status field size*/ +#define MC_CMD_HDR_PRI_O 15 /* Priority field offset */ +#define MC_CMD_HDR_PRI_S 1 /* Priority field size */ + +#define MC_CMD_HDR_READ_STATUS(_hdr) \ + ((enum mc_cmd_status)u64_dec((_hdr), \ + MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S)) + +#define MC_CMD_HDR_READ_AUTHID(_hdr) \ + ((uint16_t)u64_dec((_hdr), MC_CMD_HDR_AUTHID_O, MC_CMD_HDR_AUTHID_S)) + +#define MC_CMD_PRI_LOW 0 /*!< Low Priority command indication */ +#define MC_CMD_PRI_HIGH 1 /*!< High Priority command indication */ + +#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ + ((_cmd).params[_param] |= u64_enc((_offset), (_width), _arg)) + +#define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \ + (_arg = (_type)u64_dec(_cmd.params[_param], (_offset), (_width))) + +static inline uint64_t mc_encode_cmd_header(uint16_t cmd_id, + uint8_t priority, + uint16_t auth_id) +{ + uint64_t hdr; + + hdr = u64_enc(MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S, cmd_id); + hdr |= u64_enc(MC_CMD_HDR_AUTHID_O, MC_CMD_HDR_AUTHID_S, auth_id); + hdr |= u64_enc(MC_CMD_HDR_PRI_O, MC_CMD_HDR_PRI_S, priority); + hdr |= u64_enc(MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S, + MC_CMD_STATUS_READY); + + return hdr; +} + +/** + * mc_write_command - writes a command to a Management Complex (MC) portal + * + * @portal: pointer to an MC portal + * @cmd: pointer to a filled command + */ +static inline void mc_write_command(struct mc_command __iomem *portal, + struct mc_command *cmd) +{ + int i; + + /* copy command parameters into the portal */ + for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++) + writeq(cmd->params[i], &portal->params[i]); + + /* submit the command by writing the header */ + writeq(cmd->header, &portal->header); +} + +/** + * mc_read_response - reads the response for the last MC command from a + * Management Complex (MC) portal + * + * @portal: pointer to an MC portal + * @resp: pointer to command response buffer + * + * Returns MC_CMD_STATUS_OK on Success; Error code otherwise. + */ +static inline enum mc_cmd_status mc_read_response( + struct mc_command __iomem *portal, + struct mc_command *resp) +{ + int i; + enum mc_cmd_status status; + + /* Copy command response header from MC portal: */ + resp->header = readq(&portal->header); + status = MC_CMD_HDR_READ_STATUS(resp->header); + if (status != MC_CMD_STATUS_OK) + return status; + + /* Copy command response data from MC portal: */ + for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++) + resp->params[i] = readq(&portal->params[i]); + + return status; +} + +int mc_send_command(struct fsl_mc_io *mc_io, struct mc_command *cmd); + +#endif /* __FSL_MC_CMD_H */ diff --git a/include/fsl-mc/fsl_mc_sys.h b/include/fsl-mc/fsl_mc_sys.h new file mode 100644 index 0000000..c0befe0 --- /dev/null +++ b/include/fsl-mc/fsl_mc_sys.h @@ -0,0 +1,26 @@ +/* + * Freescale Layerscape Management Complex (MC) Environment-specific code + * + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_MC_SYS_H +#define _FSL_MC_SYS_H + +#include <asm/io.h> + +struct mc_command; + +/* + * struct mc_portal_wrapper - MC command portal wrapper object + */ +struct fsl_mc_io { + struct mc_command __iomem *mmio_regs; +}; + +int mc_send_command(struct fsl_mc_io *mc_io, + struct mc_command *cmd); + +#endif /* _FSL_MC_SYS_H */ diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 3286c95..feccef9 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -44,11 +44,12 @@ u32 fsl_ddr_get_version(void); * to this specific DDR technology. */ static __inline__ int -compute_dimm_parameters(const generic_spd_eeprom_t *spd, +compute_dimm_parameters(const unsigned int ctrl_num, + const generic_spd_eeprom_t *spd, dimm_params_t *pdimm, unsigned int dimm_number) { - return ddr_compute_dimm_parameters(spd, pdimm, dimm_number); + return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number); } #endif @@ -92,13 +93,15 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, unsigned int size_only); const char *step_to_string(unsigned int step); -unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts, +unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num, + const memctl_options_t *popts, fsl_ddr_cfg_regs_t *ddr, const common_timing_params_t *common_dimm, const dimm_params_t *dimm_parameters, unsigned int dbw_capacity_adjust, unsigned int size_only); unsigned int compute_lowest_common_dimm_parameters( + const unsigned int ctrl_num, const dimm_params_t *dimm_params, common_timing_params_t *outpdimm, unsigned int number_of_dimms); @@ -108,13 +111,15 @@ unsigned int populate_memctl_options(int all_dimms_registered, unsigned int ctrl_num); void check_interleaving_options(fsl_ddr_info_t *pinfo); -unsigned int mclk_to_picos(unsigned int mclk); -unsigned int get_memory_clk_period_ps(void); -unsigned int picos_to_mclk(unsigned int picos); +unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk); +unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num); +unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos); void fsl_ddr_set_lawbar( const common_timing_params_t *memctl_common_params, unsigned int memctl_interleaved, unsigned int ctrl_num); +void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, + unsigned int last_ctrl); int fsl_ddr_interactive_env_var_exists(void); unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); diff --git a/include/fsl_ddr_dimm_params.h b/include/fsl_ddr_dimm_params.h index 09a67a6..751e935 100644 --- a/include/fsl_ddr_dimm_params.h +++ b/include/fsl_ddr_dimm_params.h @@ -112,7 +112,7 @@ typedef struct dimm_params_s { #endif } dimm_params_t; -extern unsigned int ddr_compute_dimm_parameters( +unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, const generic_spd_eeprom_t *spd, dimm_params_t *pdimm, unsigned int dimm_number); diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index c1b6648..313fa1e 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -108,6 +108,7 @@ #define XFERTYP_RSPTYP_48_BUSY 0x00030000 #define XFERTYP_MSBSEL 0x00000020 #define XFERTYP_DTDSEL 0x00000010 +#define XFERTYP_DDREN 0x00000008 #define XFERTYP_AC12EN 0x00000004 #define XFERTYP_BCEN 0x00000002 #define XFERTYP_DMAEN 0x00000001 diff --git a/include/fsl_sec.h b/include/fsl_sec.h index aa850a3..b6e6f04 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -175,6 +175,32 @@ struct jr_regs { u32 jrcr; }; +/* + * Scatter Gather Entry - Specifies the the Scatter Gather Format + * related information + */ +struct sg_entry { +#ifdef CONFIG_SYS_FSL_SEC_LE + uint32_t addr_lo; /* Memory Address - lo */ + uint16_t addr_hi; /* Memory Address of start of buffer - hi */ + uint16_t reserved_zero; +#else + uint16_t reserved_zero; + uint16_t addr_hi; /* Memory Address of start of buffer - hi */ + uint32_t addr_lo; /* Memory Address - lo */ +#endif + + uint32_t len_flag; /* Length of the data in the frame */ +#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF +#define SG_ENTRY_EXTENSION_BIT 0x80000000 +#define SG_ENTRY_FINAL_BIT 0x40000000 + uint32_t bpid_offset; +#define SG_ENTRY_BPID_MASK 0x00FF0000 +#define SG_ENTRY_BPID_SHIFT 16 +#define SG_ENTRY_OFFSET_MASK 0x00001FFF +#define SG_ENTRY_OFFSET_SHIFT 0 +}; + int sec_init(void); #endif diff --git a/include/hw_sha.h b/include/hw_sha.h index 783350d..ab19a99 100644 --- a/include/hw_sha.h +++ b/include/hw_sha.h @@ -7,7 +7,7 @@ */ #ifndef __HW_SHA_H #define __HW_SHA_H - +#include <hash.h> /** * Computes hash value of input pbuf using h/w acceleration @@ -34,4 +34,43 @@ void hw_sha256(const uchar * in_addr, uint buflen, */ void hw_sha1(const uchar * in_addr, uint buflen, uchar * out_addr, uint chunk_size); + +/* + * Create the context for sha progressive hashing using h/w acceleration + * + * @algo: Pointer to the hash_algo struct + * @ctxp: Pointer to the pointer of the context for hashing + * @return 0 if ok, -ve on error + */ +int hw_sha_init(struct hash_algo *algo, void **ctxp); + +/* + * Update buffer for sha progressive hashing using h/w acceleration + * + * The context is freed by this function if an error occurs. + * + * @algo: Pointer to the hash_algo struct + * @ctx: Pointer to the context for hashing + * @buf: Pointer to the buffer being hashed + * @size: Size of the buffer being hashed + * @is_last: 1 if this is the last update; 0 otherwise + * @return 0 if ok, -ve on error + */ +int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf, + unsigned int size, int is_last); + +/* + * Copy sha hash result at destination location + * + * The context is freed after completion of hash operation or after an error. + * + * @algo: Pointer to the hash_algo struct + * @ctx: Pointer to the context for hashing + * @dest_buf: Pointer to the destination buffer where hash is to be copied + * @size: Size of the buffer being hashed + * @return 0 if ok, -ve on error + */ +int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf, + int size); + #endif diff --git a/include/netdev.h b/include/netdev.h index daffc12..90140bd 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -55,7 +55,6 @@ int ftmac100_initialize(bd_t *bits); int ftmac110_initialize(bd_t *bits); int greth_initialize(bd_t *bis); void gt6426x_eth_initialize(bd_t *bis); -int ks8695_eth_initialize(void); int ks8851_mll_initialize(u8 dev_num, int base_addr); int lan91c96_initialize(u8 dev_num, int base_addr); int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); diff --git a/include/serial.h b/include/serial.h index 66ed12c..de40e94 100644 --- a/include/serial.h +++ b/include/serial.h @@ -29,7 +29,7 @@ extern struct serial_device *default_serial_console(void); #if defined(CONFIG_405GP) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) || defined(CONFIG_440) || \ - defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \ + defined(CONFIG_MPC5xxx) || \ defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \ defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \ defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \ @@ -182,7 +182,6 @@ void evb64260_serial_initialize(void); void imx_serial_initialize(void); void iop480_serial_initialize(void); void jz_serial_initialize(void); -void ks8695_serial_initialize(void); void leon2_serial_initialize(void); void leon3_serial_initialize(void); void lh7a40x_serial_initialize(void); |