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-rw-r--r--include/asm-arm/arch-davinci/hardware.h2
-rw-r--r--include/asm-arm/arch-mx31/mx31-regs.h151
-rw-r--r--include/asm-arm/arch-mx31/mx31.h32
-rw-r--r--include/asm-arm/arch-omap24xx/bits.h (renamed from include/asm-arm/arch-arm1136/bits.h)0
-rw-r--r--include/asm-arm/arch-omap24xx/clocks.h (renamed from include/asm-arm/arch-arm1136/clocks.h)0
-rw-r--r--include/asm-arm/arch-omap24xx/i2c.h (renamed from include/asm-arm/arch-arm1136/i2c.h)0
-rw-r--r--include/asm-arm/arch-omap24xx/mem.h (renamed from include/asm-arm/arch-arm1136/mem.h)0
-rw-r--r--include/asm-arm/arch-omap24xx/mux.h (renamed from include/asm-arm/arch-arm1136/mux.h)0
-rw-r--r--include/asm-arm/arch-omap24xx/omap2420.h (renamed from include/asm-arm/arch-arm1136/omap2420.h)0
-rw-r--r--include/asm-arm/arch-omap24xx/sizes.h (renamed from include/asm-arm/arch-arm1136/sizes.h)0
-rw-r--r--include/asm-arm/arch-omap24xx/sys_info.h (renamed from include/asm-arm/arch-arm1136/sys_info.h)0
-rw-r--r--include/asm-arm/arch-omap24xx/sys_proto.h (renamed from include/asm-arm/arch-arm1136/sys_proto.h)0
-rw-r--r--include/asm-blackfin/blackfin-config-post.h6
-rw-r--r--include/asm-m68k/coldfire/dspi.h10
-rw-r--r--include/asm-m68k/immap.h24
-rw-r--r--include/asm-m68k/immap_5275.h469
-rw-r--r--include/asm-m68k/m5275.h241
-rw-r--r--include/asm-ppc/global_data.h3
-rw-r--r--include/asm-sh/cache.h35
-rw-r--r--include/asm-sh/cpu_sh4.h13
-rw-r--r--include/asm-sh/cpu_sh7720.h25
-rw-r--r--include/asm-sh/cpu_sh7750.h4
-rw-r--r--include/asm-sh/cpu_sh7780.h503
-rw-r--r--include/asm-sh/pci.h47
-rw-r--r--include/asm-sh/processor.h3
-rw-r--r--include/configs/DU440.h16
-rw-r--r--include/configs/M52277EVB.h1
-rw-r--r--include/configs/M5275EVB.h (renamed from include/configs/r5200.h)153
-rw-r--r--include/configs/M54455EVB.h28
-rw-r--r--include/configs/MPC8315ERDB.h23
-rw-r--r--include/configs/MPC8323ERDB.h12
-rw-r--r--include/configs/MPC837XEMDS.h28
-rw-r--r--include/configs/MPC837XERDB.h23
-rw-r--r--include/configs/MigoR.h151
-rw-r--r--include/configs/alpr.h14
-rw-r--r--include/configs/bf533-ezkit.h44
-rw-r--r--include/configs/bf533-stamp.h113
-rw-r--r--include/configs/bf537-stamp.h104
-rw-r--r--include/configs/bf561-ezkit.h40
-rw-r--r--include/configs/canyonlands.h126
-rw-r--r--include/configs/davinci_dvevm.h44
-rw-r--r--include/configs/davinci_schmoogie.h19
-rw-r--r--include/configs/davinci_sonata.h18
-rw-r--r--include/configs/imx31_litekit.h167
-rw-r--r--include/configs/imx31_phycore.h190
-rw-r--r--include/configs/korat.h67
-rw-r--r--include/configs/lwmon5.h8
-rw-r--r--include/configs/mpr2.h92
-rw-r--r--include/configs/mx31ads.h170
-rw-r--r--include/configs/pmdra.h186
-rw-r--r--include/configs/r2dplus.h150
-rw-r--r--include/configs/r7780mp.h165
-rw-r--r--include/configs/sequoia.h4
-rw-r--r--include/linux/stat.h4
-rw-r--r--include/mpc83xx.h95
-rw-r--r--include/pci_ids.h1
-rw-r--r--include/ppc440.h4
-rw-r--r--include/ppc4xx_enet.h4
58 files changed, 3373 insertions, 459 deletions
diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h
index ebcdcfe..2b3eb90 100644
--- a/include/asm-arm/arch-davinci/hardware.h
+++ b/include/asm-arm/arch-davinci/hardware.h
@@ -150,6 +150,8 @@ typedef volatile unsigned int * dv_reg_p;
#define VDD3P3V_PWDN (0x01c40048)
#define UART0_PWREMU_MGMT (0x01c20030)
+#define UART1_PWREMU_MGMT (0x01c20430)
+#define UART2_PWREMU_MGMT (0x01c20830)
#define PSC_SILVER_BULLET (0x01c41a20)
diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
new file mode 100644
index 0000000..2f0d809
--- /dev/null
+++ b/include/asm-arm/arch-mx31/mx31-regs.h
@@ -0,0 +1,151 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_MX31_REGS_H
+#define __ASM_ARCH_MX31_REGS_H
+
+#define __REG(x) (*((volatile u32 *)(x)))
+#define __REG16(x) (*((volatile u16 *)(x)))
+#define __REG8(x) (*((volatile u8 *)(x)))
+
+#define CCM_BASE 0x53f80000
+#define CCM_CCMR (CCM_BASE + 0x00)
+#define CCM_PDR0 (CCM_BASE + 0x04)
+#define CCM_PDR1 (CCM_BASE + 0x08)
+#define CCM_RCSR (CCM_BASE + 0x0c)
+#define CCM_MPCTL (CCM_BASE + 0x10)
+#define CCM_UPCTL (CCM_BASE + 0x10)
+#define CCM_SPCTL (CCM_BASE + 0x18)
+#define CCM_COSR (CCM_BASE + 0x1C)
+
+#define CCMR_MDS (1 << 7)
+#define CCMR_SBYCS (1 << 4)
+#define CCMR_MPE (1 << 3)
+#define CCMR_PRCS_MASK (3 << 1)
+#define CCMR_FPM (1 << 1)
+#define CCMR_CKIH (2 << 1)
+
+#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
+#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
+#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
+#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
+#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
+#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
+#define PDR0_MCU_PODF(x) ((x) & 0x7)
+
+#define PLL_PD(x) (((x) & 0xf) << 26)
+#define PLL_MFD(x) (((x) & 0x3ff) << 16)
+#define PLL_MFI(x) (((x) & 0xf) << 10)
+#define PLL_MFN(x) (((x) & 0x3ff) << 0)
+
+#define WEIM_BASE 0xb8002000
+#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
+#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
+#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
+
+#define IOMUXC_BASE 0x43FAC000
+#define IOMUXC_GPR (IOMUXC_BASE + 0x8)
+#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
+#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
+
+#define IPU_BASE 0x53fc0000
+#define IPU_CONF IPU_BASE
+
+#define IPU_CONF_PXL_ENDIAN (1<<8)
+#define IPU_CONF_DU_EN (1<<7)
+#define IPU_CONF_DI_EN (1<<6)
+#define IPU_CONF_ADC_EN (1<<5)
+#define IPU_CONF_SDC_EN (1<<4)
+#define IPU_CONF_PF_EN (1<<3)
+#define IPU_CONF_ROT_EN (1<<2)
+#define IPU_CONF_IC_EN (1<<1)
+#define IPU_CONF_SCI_EN (1<<0)
+
+#define WDOG_BASE 0x53FDC000
+
+/*
+ * Signal Multiplexing (IOMUX)
+ */
+
+/* bits in the SW_MUX_CTL registers */
+#define MUX_CTL_OUT_GPIO_DR (0 << 4)
+#define MUX_CTL_OUT_FUNC (1 << 4)
+#define MUX_CTL_OUT_ALT1 (2 << 4)
+#define MUX_CTL_OUT_ALT2 (3 << 4)
+#define MUX_CTL_OUT_ALT3 (4 << 4)
+#define MUX_CTL_OUT_ALT4 (5 << 4)
+#define MUX_CTL_OUT_ALT5 (6 << 4)
+#define MUX_CTL_OUT_ALT6 (7 << 4)
+#define MUX_CTL_IN_NONE (0 << 0)
+#define MUX_CTL_IN_GPIO (1 << 0)
+#define MUX_CTL_IN_FUNC (2 << 0)
+#define MUX_CTL_IN_ALT1 (4 << 0)
+#define MUX_CTL_IN_ALT2 (8 << 0)
+
+#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
+#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
+#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
+#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
+
+/* Register offsets based on IOMUXC_BASE */
+/* 0x00 .. 0x7b */
+#define MUX_CTL_RTS1 0x7c
+#define MUX_CTL_CTS1 0x7d
+#define MUX_CTL_DTR_DCE1 0x7e
+#define MUX_CTL_DSR_DCE1 0x7f
+#define MUX_CTL_CSPI2_SCLK 0x80
+#define MUX_CTL_CSPI2_SPI_RDY 0x81
+#define MUX_CTL_RXD1 0x82
+#define MUX_CTL_TXD1 0x83
+#define MUX_CTL_CSPI2_MISO 0x84
+/* 0x85 .. 0x8a */
+#define MUX_CTL_CSPI2_MOSI 0x8b
+
+/* The modes a specific pin can be in
+ * these macros can be used in mx31_gpio_mux() and have the form
+ * MUX_[contact name]__[pin function]
+ */
+#define MUX_RXD1__UART1_RXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1)
+#define MUX_TXD1__UART1_TXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1)
+#define MUX_RTS1__UART1_RTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1)
+#define MUX_RTS1__UART1_CTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1)
+
+#define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI)
+#define MUX_CSPI2_MISO__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
+
+/*
+ * Memory regions and CS
+ */
+#define IPU_MEM_BASE 0x70000000
+#define CSD0_BASE 0x80000000
+#define CSD1_BASE 0x90000000
+#define CS0_BASE 0xA0000000
+#define CS1_BASE 0xA8000000
+#define CS2_BASE 0xB0000000
+#define CS3_BASE 0xB2000000
+#define CS4_BASE 0xB4000000
+#define CS4_PSRAM_BASE 0xB5000000
+#define CS5_BASE 0xB6000000
+#define PCMCIA_MEM_BASE 0xC0000000
+
+#endif /* __ASM_ARCH_MX31_REGS_H */
diff --git a/include/asm-arm/arch-mx31/mx31.h b/include/asm-arm/arch-mx31/mx31.h
new file mode 100644
index 0000000..f89a401
--- /dev/null
+++ b/include/asm-arm/arch-mx31/mx31.h
@@ -0,0 +1,32 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_MX31_H
+#define __ASM_ARCH_MX31_H
+
+u32 mx31_get_mpl_dpdgck_clk(void);
+u32 mx31_get_mcu_main_clk(void);
+u32 mx31_get_ipg_clk(void);
+void mx31_gpio_mux(unsigned long mode);
+
+#endif /* __ASM_ARCH_MX31_H */
diff --git a/include/asm-arm/arch-arm1136/bits.h b/include/asm-arm/arch-omap24xx/bits.h
index 8522335..8522335 100644
--- a/include/asm-arm/arch-arm1136/bits.h
+++ b/include/asm-arm/arch-omap24xx/bits.h
diff --git a/include/asm-arm/arch-arm1136/clocks.h b/include/asm-arm/arch-omap24xx/clocks.h
index 2a95af1..2a95af1 100644
--- a/include/asm-arm/arch-arm1136/clocks.h
+++ b/include/asm-arm/arch-omap24xx/clocks.h
diff --git a/include/asm-arm/arch-arm1136/i2c.h b/include/asm-arm/arch-omap24xx/i2c.h
index 7248950..7248950 100644
--- a/include/asm-arm/arch-arm1136/i2c.h
+++ b/include/asm-arm/arch-omap24xx/i2c.h
diff --git a/include/asm-arm/arch-arm1136/mem.h b/include/asm-arm/arch-omap24xx/mem.h
index c81f1c4..c81f1c4 100644
--- a/include/asm-arm/arch-arm1136/mem.h
+++ b/include/asm-arm/arch-omap24xx/mem.h
diff --git a/include/asm-arm/arch-arm1136/mux.h b/include/asm-arm/arch-omap24xx/mux.h
index 4fdb9c6..4fdb9c6 100644
--- a/include/asm-arm/arch-arm1136/mux.h
+++ b/include/asm-arm/arch-omap24xx/mux.h
diff --git a/include/asm-arm/arch-arm1136/omap2420.h b/include/asm-arm/arch-omap24xx/omap2420.h
index 0c11bec..0c11bec 100644
--- a/include/asm-arm/arch-arm1136/omap2420.h
+++ b/include/asm-arm/arch-omap24xx/omap2420.h
diff --git a/include/asm-arm/arch-arm1136/sizes.h b/include/asm-arm/arch-omap24xx/sizes.h
index aaba18f..aaba18f 100644
--- a/include/asm-arm/arch-arm1136/sizes.h
+++ b/include/asm-arm/arch-omap24xx/sizes.h
diff --git a/include/asm-arm/arch-arm1136/sys_info.h b/include/asm-arm/arch-omap24xx/sys_info.h
index 53c231a..53c231a 100644
--- a/include/asm-arm/arch-arm1136/sys_info.h
+++ b/include/asm-arm/arch-omap24xx/sys_info.h
diff --git a/include/asm-arm/arch-arm1136/sys_proto.h b/include/asm-arm/arch-omap24xx/sys_proto.h
index 9d8e5b2..9d8e5b2 100644
--- a/include/asm-arm/arch-arm1136/sys_proto.h
+++ b/include/asm-arm/arch-omap24xx/sys_proto.h
diff --git a/include/asm-blackfin/blackfin-config-post.h b/include/asm-blackfin/blackfin-config-post.h
index 4422225..6a1ffa1 100644
--- a/include/asm-blackfin/blackfin-config-post.h
+++ b/include/asm-blackfin/blackfin-config-post.h
@@ -14,9 +14,9 @@
# error Memory Map does not fit into configuration
#endif
-/* Sanity check BFIN_CPU */
-#ifndef BFIN_CPU
-# error BFIN_CPU: your board config needs to define this
+/* Sanity check CONFIG_BFIN_CPU */
+#ifndef CONFIG_BFIN_CPU
+# error CONFIG_BFIN_CPU: your board config needs to define this
#endif
/* Make sure the structure is properly aligned */
diff --git a/include/asm-m68k/coldfire/dspi.h b/include/asm-m68k/coldfire/dspi.h
index 3c579d3..8327e1b 100644
--- a/include/asm-m68k/coldfire/dspi.h
+++ b/include/asm-m68k/coldfire/dspi.h
@@ -64,10 +64,15 @@ typedef struct dspi {
#define DSPI_DMCR_CTXF (0x00000800)
#define DSPI_DMCR_DRXF (0x00001000)
#define DSPI_DMCR_DTXF (0x00002000)
+#define DSPI_DMCR_MDIS (0x00004000)
#define DSPI_DMCR_CSIS0 (0x00010000)
+#define DSPI_DMCR_CSIS1 (0x00020000)
#define DSPI_DMCR_CSIS2 (0x00040000)
#define DSPI_DMCR_CSIS3 (0x00080000)
+#define DSPI_DMCR_CSIS4 (0x00100000)
#define DSPI_DMCR_CSIS5 (0x00200000)
+#define DSPI_DMCR_CSIS6 (0x00400000)
+#define DSPI_DMCR_CSIS7 (0x00800000)
#define DSPI_DMCR_ROOE (0x01000000)
#define DSPI_DMCR_PCSSE (0x02000000)
#define DSPI_DMCR_MTFE (0x04000000)
@@ -92,6 +97,7 @@ typedef struct dspi {
#define DSPI_DCTAR_CPHA (0x02000000)
#define DSPI_DCTAR_CPOL (0x04000000)
#define DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27)
+#define DSPI_DCTAR_DBR (0x80000000)
#define DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
#define DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
#define DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
@@ -153,4 +159,8 @@ typedef struct dspi {
/* Bit definitions and macros for DRFDR group */
#define DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF))
+void dspi_init(void);
+void dspi_tx(int chipsel, u8 attrib, u16 data);
+u16 dspi_rx(void);
+
#endif /* __DSPI_H__ */
diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h
index 916bf96..f1586d5 100644
--- a/include/asm-m68k/immap.h
+++ b/include/asm-m68k/immap.h
@@ -180,6 +180,30 @@
#endif
#endif /* CONFIG_M5272 */
+#ifdef CONFIG_M5275
+#include <asm/immap_5275.h>
+#include <asm/m5275.h>
+
+#define CFG_FEC0_IOBASE (MMAP_FEC0)
+#define CFG_FEC1_IOBASE (MMAP_FEC1)
+#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+#define CFG_INTR_BASE (MMAP_INTC0)
+#define CFG_NUM_IRQS (192)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_TMR_BASE (MMAP_DTMR3)
+#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
+#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
+#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
+#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI (0x1E)
+#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+#endif /* CONFIG_M5275 */
+
#ifdef CONFIG_M5282
#include <asm/immap_5282.h>
#include <asm/m5282.h>
diff --git a/include/asm-m68k/immap_5275.h b/include/asm-m68k/immap_5275.h
new file mode 100644
index 0000000..774866e
--- /dev/null
+++ b/include/asm-m68k/immap_5275.h
@@ -0,0 +1,469 @@
+/*
+ * MCF5274/5 Internal Memory Map
+ *
+ * Copyright (c) 2005 Arthur Shipkowski <art@videon-central.com>
+ * Based on work Copyright (c) 2003 Josef Baumgartner
+ * <josef.baumgartner@telex.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5275__
+#define __IMMAP_5275__
+
+#define MMAP_SCM (CFG_MBAR + 0x00000000)
+#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_MBAR + 0x00000080)
+#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
+#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
+#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
+#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
+#define MMAP_UART0 (CFG_MBAR + 0x00000200)
+#define MMAP_UART1 (CFG_MBAR + 0x00000240)
+#define MMAP_UART2 (CFG_MBAR + 0x00000280)
+#define MMAP_I2C (CFG_MBAR + 0x00000300)
+#define MMAP_QSPI (CFG_MBAR + 0x00000340)
+#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
+#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
+#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
+#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
+#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
+#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
+#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
+#define MMAP_FEC0 (CFG_MBAR + 0x00001000)
+#define MMAP_FEC0FIFO (CFG_MBAR + 0x00001400)
+#define MMAP_FEC1 (CFG_MBAR + 0x00001800)
+#define MMAP_FEC1FIFO (CFG_MBAR + 0x00001C00)
+#define MMAP_GPIO (CFG_MBAR + 0x00100000)
+#define MMAP_RCM (CFG_MBAR + 0x00110000)
+#define MMAP_CCM (CFG_MBAR + 0x00110004)
+#define MMAP_PLL (CFG_MBAR + 0x00120000)
+#define MMAP_EPORT (CFG_MBAR + 0x00130000)
+#define MMAP_WDOG (CFG_MBAR + 0x00140000)
+#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
+#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
+#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
+#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
+#define MMAP_MDHA (CFG_MBAR + 0x00190000)
+#define MMAP_RNG (CFG_MBAR + 0x001A0000)
+#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
+#define MMAP_USB (CFG_MBAR + 0x001C0000)
+#define MMAP_PWM0 (CFG_MBAR + 0x001D0000)
+
+/* System configuration registers
+*/
+typedef struct sys_ctrl {
+ u32 ipsbar;
+ u32 res1;
+ u32 rambar;
+ u32 res2;
+ u8 crsr;
+ u8 cwcr;
+ u8 lpicr;
+ u8 cwsr;
+ u8 res3[8];
+ u32 mpark;
+ u8 mpr;
+ u8 res4[3];
+ u8 pacr0;
+ u8 pacr1;
+ u8 pacr2;
+ u8 pacr3;
+ u8 pacr4;
+ u8 res5;
+ u8 pacr5;
+ u8 pacr6;
+ u8 pacr7;
+ u8 res6;
+ u8 pacr8;
+ u8 res7;
+ u8 gpacr;
+ u8 res8[3];
+} sysctrl_t;
+/* SDRAM controller registers, offset: 0x040
+ */
+typedef struct sdram_ctrl {
+ u32 sdmr;
+ u32 sdcr;
+ u32 sdcfg1;
+ u32 sdcfg2;
+ u32 sdbar0;
+ u32 sdbmr0;
+ u32 sdbar1;
+ u32 sdbmr1;
+} sdramctrl_t;
+
+/* Chip select module registers, offset: 0x080
+*/
+typedef struct cs_ctlr {
+ u16 ar0;
+ u16 res1;
+ u32 mr0;
+ u16 res2;
+ u16 cr0;
+ u16 ar1;
+ u16 res3;
+ u32 mr1;
+ u16 res4;
+ u16 cr1;
+ u16 ar2;
+ u16 res5;
+ u32 mr2;
+ u16 res6;
+ u16 cr2;
+ u16 ar3;
+ u16 res7;
+ u32 mr3;
+ u16 res8;
+ u16 cr3;
+ u16 ar4;
+ u16 res9;
+ u32 mr4;
+ u16 res10;
+ u16 cr4;
+ u16 ar5;
+ u16 res11;
+ u32 mr5;
+ u16 res12;
+ u16 cr5;
+ u16 ar6;
+ u16 res13;
+ u32 mr6;
+ u16 res14;
+ u16 cr6;
+ u16 ar7;
+ u16 res15;
+ u32 mr7;
+ u16 res16;
+ u16 cr7;
+} csctrl_t;
+
+/* DMA module registers, offset 0x100
+ */
+typedef struct dma_ctrl {
+ u32 sar;
+ u32 dar;
+ u32 dsrbcr;
+ u32 dcr;
+} dma_t;
+
+/* QSPI module registers, offset 0x340
+ */
+typedef struct qspi_ctrl {
+ u16 qmr;
+ u8 res1[2];
+ u16 qdlyr;
+ u8 res2[2];
+ u16 qwr;
+ u8 res3[2];
+ u16 qir;
+ u8 res4[2];
+ u16 qar;
+ u8 res5[2];
+ u16 qdr;
+ u8 res6[2];
+} qspi_t;
+
+/* Interrupt module registers, offset 0xc00
+*/
+typedef struct int_ctrl {
+ u32 iprh0;
+ u32 iprl0;
+ u32 imrh0;
+ u32 imrl0;
+ u32 frch0;
+ u32 frcl0;
+ u8 irlr;
+ u8 iacklpr;
+ u8 res1[0x26];
+ u8 icr0[64]; /* No ICR0, done this way for readability */
+ u8 res2[0x60];
+ u8 swiack0;
+ u8 res3[3];
+ u8 Lniack0_1;
+ u8 res4[3];
+ u8 Lniack0_2;
+ u8 res5[3];
+ u8 Lniack0_3;
+ u8 res6[3];
+ u8 Lniack0_4;
+ u8 res7[3];
+ u8 Lniack0_5;
+ u8 res8[3];
+ u8 Lniack0_6;
+ u8 res9[3];
+ u8 Lniack0_7;
+ u8 res10[3];
+} int0_t;
+
+/* GPIO port registers
+*/
+typedef struct gpio_ctrl {
+ /* Port Output Data Registers */
+ u8 podr_res1[4];
+ u8 podr_busctl;
+ u8 podr_addr;
+ u8 podr_res2[2];
+ u8 podr_cs;
+ u8 podr_res3;
+ u8 podr_fec0h;
+ u8 podr_fec0l;
+ u8 podr_feci2c;
+ u8 podr_qspi;
+ u8 podr_sdram;
+ u8 podr_timerh;
+ u8 podr_timerl;
+ u8 podr_uartl;
+ u8 podr_fec1h;
+ u8 podr_fec1l;
+ u8 podr_bs;
+ u8 podr_res4;
+ u8 podr_usbh;
+ u8 podr_usbl;
+ u8 podr_uarth;
+ u8 podr_res5[3];
+ /* Port Data Direction Registers */
+ u8 pddr_res1[4];
+ u8 pddr_busctl;
+ u8 pddr_addr;
+ u8 pddr_res2[2];
+ u8 pddr_cs;
+ u8 pddr_res3;
+ u8 pddr_fec0h;
+ u8 pddr_fec0l;
+ u8 pddr_feci2c;
+ u8 pddr_qspi;
+ u8 pddr_sdram;
+ u8 pddr_timerh;
+ u8 pddr_timerl;
+ u8 pddr_uartl;
+ u8 pddr_fec1h;
+ u8 pddr_fec1l;
+ u8 pddr_bs;
+ u8 pddr_res4;
+ u8 pddr_usbh;
+ u8 pddr_usbl;
+ u8 pddr_uarth;
+ u8 pddr_res5[3];
+ /* Port Pin Data/Set Registers */
+ u8 ppdsdr_res1[4];
+ u8 ppdsdr_busctl;
+ u8 ppdsdr_addr;
+ u8 ppdsdr_res2[2];
+ u8 ppdsdr_cs;
+ u8 ppdsdr_res3;
+ u8 ppdsdr_fec0h;
+ u8 ppdsdr_fec0l;
+ u8 ppdsdr_feci2c;
+ u8 ppdsdr_qspi;
+ u8 ppdsdr_sdram;
+ u8 ppdsdr_timerh;
+ u8 ppdsdr_timerl;
+ u8 ppdsdr_uartl;
+ u8 ppdsdr_fec1h;
+ u8 ppdsdr_fec1l;
+ u8 ppdsdr_bs;
+ u8 ppdsdr_res4;
+ u8 ppdsdr_usbh;
+ u8 ppdsdr_usbl;
+ u8 ppdsdr_uarth;
+ u8 ppdsdr_res5[3];
+ /* Port Clear Output Data Registers */
+ u8 pclrr_res1[4];
+ u8 pclrr_busctl;
+ u8 pclrr_addr;
+ u8 pclrr_res2[2];
+ u8 pclrr_cs;
+ u8 pclrr_res3;
+ u8 pclrr_fec0h;
+ u8 pclrr_fec0l;
+ u8 pclrr_feci2c;
+ u8 pclrr_qspi;
+ u8 pclrr_sdram;
+ u8 pclrr_timerh;
+ u8 pclrr_timerl;
+ u8 pclrr_uartl;
+ u8 pclrr_fec1h;
+ u8 pclrr_fec1l;
+ u8 pclrr_bs;
+ u8 pclrr_res4;
+ u8 pclrr_usbh;
+ u8 pclrr_usbl;
+ u8 pclrr_uarth;
+ u8 pclrr_res5[3];
+ /* Pin Assignment Registers */
+ u8 par_addr;
+ u8 par_cs;
+ u16 par_busctl;
+ u8 par_res1[2];
+ u16 par_usb;
+ u8 par_fec0hl;
+ u8 par_fec1hl;
+ u16 par_timer;
+ u16 par_uart;
+ u16 par_qspi;
+ u16 par_sdram;
+ u16 par_feci2c;
+ u8 par_bs;
+ u8 par_res2[3];
+} gpio_t;
+
+
+/* PWM module registers
+ */
+typedef struct pwm_ctrl {
+ u8 pwcr0;
+ u8 res1[3];
+ u8 pwcr1;
+ u8 res2[3];
+ u8 pwcr2;
+ u8 res3[7];
+ u8 pwwd0;
+ u8 res4[3];
+ u8 pwwd1;
+ u8 res5[3];
+ u8 pwwd2;
+ u8 res6[7];
+} pwm_t;
+
+/* Watchdog registers
+ */
+typedef struct wdog_ctrl {
+ u16 wcr;
+ u16 wmr;
+ u16 wcntr;
+ u16 wsr;
+ u8 res4[114];
+} wdog_t;
+
+/* USB module registers
+*/
+typedef struct usb {
+ u16 res1;
+ u16 fnr;
+ u16 res2;
+ u16 fnmr;
+ u16 res3;
+ u16 rfmr;
+ u16 res4;
+ u16 rfmmr;
+ u8 res5[3];
+ u8 far;
+ u32 asr;
+ u32 drr1;
+ u32 drr2;
+ u16 res6;
+ u16 specr;
+ u16 res7;
+ u16 ep0sr;
+ u32 iep0cfg;
+ u32 oep0cfg;
+ u32 ep1cfg;
+ u32 ep2cfg;
+ u32 ep3cfg;
+ u32 ep4cfg;
+ u32 ep5cfg;
+ u32 ep6cfg;
+ u32 ep7cfg;
+ u32 ep0ctl;
+ u16 res8;
+ u16 ep1ctl;
+ u16 res9;
+ u16 ep2ctl;
+ u16 res10;
+ u16 ep3ctl;
+ u16 res11;
+ u16 ep4ctl;
+ u16 res12;
+ u16 ep5ctl;
+ u16 res13;
+ u16 ep6ctl;
+ u16 res14;
+ u16 ep7ctl;
+ u32 ep0isr;
+ u16 res15;
+ u16 ep1isr;
+ u16 res16;
+ u16 ep2isr;
+ u16 res17;
+ u16 ep3isr;
+ u16 res18;
+ u16 ep4isr;
+ u16 res19;
+ u16 ep5isr;
+ u16 res20;
+ u16 ep6isr;
+ u16 res21;
+ u16 ep7isr;
+ u32 ep0imr;
+ u16 res22;
+ u16 ep1imr;
+ u16 res23;
+ u16 ep2imr;
+ u16 res24;
+ u16 ep3imr;
+ u16 res25;
+ u16 ep4imr;
+ u16 res26;
+ u16 ep5imr;
+ u16 res27;
+ u16 ep6imr;
+ u16 res28;
+ u16 ep7imr;
+ u32 ep0dr;
+ u32 ep1dr;
+ u32 ep2dr;
+ u32 ep3dr;
+ u32 ep4dr;
+ u32 ep5dr;
+ u32 ep6dr;
+ u32 ep7dr;
+ u16 res29;
+ u16 ep0dpr;
+ u16 res30;
+ u16 ep1dpr;
+ u16 res31;
+ u16 ep2dpr;
+ u16 res32;
+ u16 ep3dpr;
+ u16 res33;
+ u16 ep4dpr;
+ u16 res34;
+ u16 ep5dpr;
+ u16 res35;
+ u16 ep6dpr;
+ u16 res36;
+ u16 ep7dpr;
+ u8 res37[788];
+ u8 cfgram[1024];
+} usb_t;
+
+/* PLL module registers
+ */
+typedef struct pll_ctrl {
+ u32 syncr;
+ u32 synsr;
+} pll_t;
+
+typedef struct rcm {
+ u8 rcr;
+ u8 rsr;
+} rcm_t;
+
+#endif /* __IMMAP_5275__ */
diff --git a/include/asm-m68k/m5275.h b/include/asm-m68k/m5275.h
new file mode 100644
index 0000000..89c6c92
--- /dev/null
+++ b/include/asm-m68k/m5275.h
@@ -0,0 +1,241 @@
+/*
+ * MCF5275 Internal Memory Map
+ *
+ * Copyright (C) 2003-2004, Greg Ungerer (gerg@snapgear.com)
+ * Copyright (C) 2004-2008 Arthur Shipkowski (art@videon-central.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __M5275_H__
+#define __M5275_H__
+
+/*
+ * Define the 5275 SIM register set addresses. These are similar,
+ * but not quite identical to the 5282 registers and offsets.
+ */
+#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */
+#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
+#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
+#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
+#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
+#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
+#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
+#define MCFINTC_IRLR 0x18 /* */
+#define MCFINTC_IACKL 0x19 /* */
+#define MCFINTC_ICR0 0x40 /* Base ICR register */
+
+#define MCF_GPIO_PAR_UART 0x10007c
+#define UART0_ENABLE_MASK 0x000f
+#define UART1_ENABLE_MASK 0x00f0
+#define UART2_ENABLE_MASK 0x3f00
+
+#define MCF_GPIO_PAR_FECI2C 0x100082
+#define PAR_SDA_ENABLE_MASK 0x0003
+#define PAR_SCL_ENABLE_MASK 0x000c
+
+#define MCFSIM_WRRR 0x140000
+#define MCFSIM_SDCR 0x40
+
+/*********************************************************************
+ * SDRAM Controller (SDRAMC)
+ *********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SDRAMC_SDMR (*(vuint32*)(void*)(&__IPSBAR[0x000040]))
+#define MCF_SDRAMC_SDCR (*(vuint32*)(void*)(&__IPSBAR[0x000044]))
+#define MCF_SDRAMC_SDCFG1 (*(vuint32*)(void*)(&__IPSBAR[0x000048]))
+#define MCF_SDRAMC_SDCFG2 (*(vuint32*)(void*)(&__IPSBAR[0x00004C]))
+#define MCF_SDRAMC_SDBAR0 (*(vuint32*)(void*)(&__IPSBAR[0x000050]))
+#define MCF_SDRAMC_SDBAR1 (*(vuint32*)(void*)(&__IPSBAR[0x000058]))
+#define MCF_SDRAMC_SDMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000054]))
+#define MCF_SDRAMC_SDMR1 (*(vuint32*)(void*)(&__IPSBAR[0x00005C]))
+
+/* Bit definitions and macros for MCF_SDRAMC_SDMR */
+#define MCF_SDRAMC_SDMR_CMD (0x00010000)
+#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
+#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30)
+#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000)
+#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCR */
+#define MCF_SDRAMC_SDCR_IPALL (0x00000002)
+#define MCF_SDRAMC_SDCR_IREF (0x00000004)
+#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10)
+#define MCF_SDRAMC_SDCR_DQP_BP (0x00008000)
+#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
+#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
+#define MCF_SDRAMC_SDCR_REF (0x10000000)
+#define MCF_SDRAMC_SDCR_CKE (0x40000000)
+#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
+#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
+#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
+#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
+#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
+#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
+#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
+#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
+#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
+#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
+#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
+#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDBARn */
+#define MCF_SDRAMC_SDBARn_BASE(x) (((x)&0x00003FFF)<<18)
+#define MCF_SDRAMC_SDBARn_BA(x) ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDMRn */
+#define MCF_SDRAMC_SDMRn_V (0x00000001)
+#define MCF_SDRAMC_SDMRn_WP (0x00000080)
+#define MCF_SDRAMC_SDMRn_MASK(x) (((x)&0x00003FFF)<<18)
+#define MCF_SDRAMC_SDMRn_BAM_4G (0xFFFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_2G (0x7FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_1G (0x3FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_1024M (0x3FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_512M (0x1FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_256M (0x0FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_128M (0x07FF0000)
+#define MCF_SDRAMC_SDMRn_BAM_64M (0x03FF0000)
+#define MCF_SDRAMC_SDMRn_BAM_32M (0x01FF0000)
+#define MCF_SDRAMC_SDMRn_BAM_16M (0x00FF0000)
+#define MCF_SDRAMC_SDMRn_BAM_8M (0x007F0000)
+#define MCF_SDRAMC_SDMRn_BAM_4M (0x003F0000)
+#define MCF_SDRAMC_SDMRn_BAM_2M (0x001F0000)
+#define MCF_SDRAMC_SDMRn_BAM_1M (0x000F0000)
+#define MCF_SDRAMC_SDMRn_BAM_1024K (0x000F0000)
+#define MCF_SDRAMC_SDMRn_BAM_512K (0x00070000)
+#define MCF_SDRAMC_SDMRn_BAM_256K (0x00030000)
+#define MCF_SDRAMC_SDMRn_BAM_128K (0x00010000)
+#define MCF_SDRAMC_SDMRn_BAM_64K (0x00000000)
+
+/*********************************************************************
+ * Interrupt Controller (INTC)
+ ********************************************************************/
+#define INT0_LO_RSVD0 (0)
+#define INT0_LO_EPORT1 (1)
+#define INT0_LO_EPORT2 (2)
+#define INT0_LO_EPORT3 (3)
+#define INT0_LO_EPORT4 (4)
+#define INT0_LO_EPORT5 (5)
+#define INT0_LO_EPORT6 (6)
+#define INT0_LO_EPORT7 (7)
+#define INT0_LO_SCM (8)
+#define INT0_LO_DMA0 (9)
+#define INT0_LO_DMA1 (10)
+#define INT0_LO_DMA2 (11)
+#define INT0_LO_DMA3 (12)
+#define INT0_LO_UART0 (13)
+#define INT0_LO_UART1 (14)
+#define INT0_LO_UART2 (15)
+#define INT0_LO_RSVD1 (16)
+#define INT0_LO_I2C (17)
+#define INT0_LO_QSPI (18)
+#define INT0_LO_DTMR0 (19)
+#define INT0_LO_DTMR1 (20)
+#define INT0_LO_DTMR2 (21)
+#define INT0_LO_DTMR3 (22)
+#define INT0_LO_FEC0_TXF (23)
+#define INT0_LO_FEC0_TXB (24)
+#define INT0_LO_FEC0_UN (25)
+#define INT0_LO_FEC0_RL (26)
+#define INT0_LO_FEC0_RXF (27)
+#define INT0_LO_FEC0_RXB (28)
+#define INT0_LO_FEC0_MII (29)
+#define INT0_LO_FEC0_LC (30)
+#define INT0_LO_FEC0_HBERR (31)
+#define INT0_HI_FEC0_GRA (32)
+#define INT0_HI_FEC0_EBERR (33)
+#define INT0_HI_FEC0_BABT (34)
+#define INT0_HI_FEC0_BABR (35)
+#define INT0_HI_PIT0 (36)
+#define INT0_HI_PIT1 (37)
+#define INT0_HI_PIT2 (38)
+#define INT0_HI_PIT3 (39)
+#define INT0_HI_RNG (40)
+#define INT0_HI_SKHA (41)
+#define INT0_HI_MDHA (42)
+#define INT0_HI_USB (43)
+#define INT0_HI_USB_EP0 (44)
+#define INT0_HI_USB_EP1 (45)
+#define INT0_HI_USB_EP2 (46)
+#define INT0_HI_USB_EP3 (47)
+/* 48-63 Reserved */
+
+/* 0-22 Reserved */
+#define INT1_LO_FEC1_TXF (23)
+#define INT1_LO_FEC1_TXB (24)
+#define INT1_LO_FEC1_UN (25)
+#define INT1_LO_FEC1_RL (26)
+#define INT1_LO_FEC1_RXF (27)
+#define INT1_LO_FEC1_RXB (28)
+#define INT1_LO_FEC1_MII (29)
+#define INT1_LO_FEC1_LC (30)
+#define INT1_LO_FEC1_HBERR (31)
+#define INT1_HI_FEC1_GRA (32)
+#define INT1_HI_FEC1_EBERR (33)
+#define INT1_HI_FEC1_BABT (34)
+#define INT1_HI_FEC1_BABR (35)
+/* 36-63 Reserved */
+
+/* Bit definitions and macros for INTC_IPRL */
+#define INTC_IPRL_INT31 (0x80000000)
+#define INTC_IPRL_INT30 (0x40000000)
+#define INTC_IPRL_INT29 (0x20000000)
+#define INTC_IPRL_INT28 (0x10000000)
+#define INTC_IPRL_INT27 (0x08000000)
+#define INTC_IPRL_INT26 (0x04000000)
+#define INTC_IPRL_INT25 (0x02000000)
+#define INTC_IPRL_INT24 (0x01000000)
+#define INTC_IPRL_INT23 (0x00800000)
+#define INTC_IPRL_INT22 (0x00400000)
+#define INTC_IPRL_INT21 (0x00200000)
+#define INTC_IPRL_INT20 (0x00100000)
+#define INTC_IPRL_INT19 (0x00080000)
+#define INTC_IPRL_INT18 (0x00040000)
+#define INTC_IPRL_INT17 (0x00020000)
+#define INTC_IPRL_INT16 (0x00010000)
+#define INTC_IPRL_INT15 (0x00008000)
+#define INTC_IPRL_INT14 (0x00004000)
+#define INTC_IPRL_INT13 (0x00002000)
+#define INTC_IPRL_INT12 (0x00001000)
+#define INTC_IPRL_INT11 (0x00000800)
+#define INTC_IPRL_INT10 (0x00000400)
+#define INTC_IPRL_INT9 (0x00000200)
+#define INTC_IPRL_INT8 (0x00000100)
+#define INTC_IPRL_INT7 (0x00000080)
+#define INTC_IPRL_INT6 (0x00000040)
+#define INTC_IPRL_INT5 (0x00000020)
+#define INTC_IPRL_INT4 (0x00000010)
+#define INTC_IPRL_INT3 (0x00000008)
+#define INTC_IPRL_INT2 (0x00000004)
+#define INTC_IPRL_INT1 (0x00000002)
+#define INTC_IPRL_INT0 (0x00000001)
+
+/* Bit definitions and macros for RCR */
+#define RCM_RCR_FRCRSTOUT (0x40)
+#define RCM_RCR_SOFTRST (0x80)
+
+#define FMPLL_SYNSR_LOCK (0x00000008)
+
+#endif /* __M5275_H__ */
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index b43dba3..9ccf7d6 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -74,7 +74,6 @@ typedef struct global_data {
u32 enc_clk;
u32 lbiu_clk;
u32 lclk_clk;
- u32 ddr_clk;
u32 pci_clk;
#if defined(CONFIG_MPC837X)
u32 pciexp1_clk;
@@ -84,7 +83,7 @@ typedef struct global_data {
u32 sata_clk;
#endif
#if defined(CONFIG_MPC8360)
- u32 ddr_sec_clk;
+ u32 mem_sec_clk;
#endif /* CONFIG_MPC8360 */
#endif
#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h
new file mode 100644
index 0000000..67474c7
--- /dev/null
+++ b/include/asm-sh/cache.h
@@ -0,0 +1,35 @@
+#ifndef __ASM_SH_CACHE_H
+#define __ASM_SH_CACHE_H
+
+#if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
+
+#define L1_CACHE_BYTES 32
+struct __large_struct { unsigned long buf[100]; };
+#define __m(x) (*(struct __large_struct *)(x))
+
+void dcache_wback_range(u32 start, u32 end)
+{
+ u32 v;
+
+ start &= ~(L1_CACHE_BYTES-1);
+ for (v = start; v < end; v+=L1_CACHE_BYTES) {
+ asm volatile("ocbwb %0"
+ : /* no output */
+ : "m" (__m(v)));
+ }
+}
+
+void dcache_invalid_range(u32 start, u32 end)
+{
+ u32 v;
+
+ start &= ~(L1_CACHE_BYTES-1);
+ for (v = start; v < end; v+=L1_CACHE_BYTES) {
+ asm volatile("ocbi %0"
+ : /* no output */
+ : "m" (__m(v)));
+ }
+}
+#endif /* CONFIG_SH4 || CONFIG_SH4A */
+
+#endif /* __ASM_SH_CACHE_H */
diff --git a/include/asm-sh/cpu_sh4.h b/include/asm-sh/cpu_sh4.h
index 2658039..c200ba5 100644
--- a/include/asm-sh/cpu_sh4.h
+++ b/include/asm-sh/cpu_sh4.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -30,12 +30,15 @@
#define CACHE_OC_NUM_ENTRIES 512
#define CACHE_OC_ENTRY_SHIFT 5
-#if defined (CONFIG_CPU_SH7750)
-#include <asm/cpu_sh7750.h>
+#if defined (CONFIG_CPU_SH7750) || \
+ defined(CONFIG_CPU_SH7751)
+# include <asm/cpu_sh7750.h>
#elif defined (CONFIG_CPU_SH7722)
-#include <asm/cpu_sh7722.h>
+# include <asm/cpu_sh7722.h>
+#elif defined (CONFIG_CPU_SH7780)
+# include <asm/cpu_sh7780.h>
#else
-#error "Unknown SH4 variant"
+# error "Unknown SH4 variant"
#endif
#endif /* _ASM_CPU_SH4_H_ */
diff --git a/include/asm-sh/cpu_sh7720.h b/include/asm-sh/cpu_sh7720.h
index bafb8de..1b393b8 100644
--- a/include/asm-sh/cpu_sh7720.h
+++ b/include/asm-sh/cpu_sh7720.h
@@ -1,5 +1,9 @@
/*
- * (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ * Copyright 2007 (C)
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * Copyright 2008 (C)
+ * Mark Jonas <mark.jonas@de.bosch.com>
*
* SH7720 Internal I/O register
*
@@ -201,6 +205,25 @@
#define PSELD (PFC_BASE + 0x2A)
/* I/O Port */
+#define PORT_BASE 0xA4050100
+#define PADR (PORT_BASE + 0x40)
+#define PBDR (PORT_BASE + 0x42)
+#define PCDR (PORT_BASE + 0x44)
+#define PDDR (PORT_BASE + 0x46)
+#define PEDR (PORT_BASE + 0x48)
+#define PFDR (PORT_BASE + 0x4A)
+#define PGDR (PORT_BASE + 0x4C)
+#define PHDR (PORT_BASE + 0x4E)
+#define PJDR (PORT_BASE + 0x50)
+#define PKDR (PORT_BASE + 0x52)
+#define PLDR (PORT_BASE + 0x54)
+#define PMDR (PORT_BASE + 0x56)
+#define PPDR (PORT_BASE + 0x58)
+#define PRDR (PORT_BASE + 0x5A)
+#define PSDR (PORT_BASE + 0x5C)
+#define PTDR (PORT_BASE + 0x5E)
+#define PUDR (PORT_BASE + 0x60)
+#define PVDR (PORT_BASE + 0x62)
/* H-UDI */
diff --git a/include/asm-sh/cpu_sh7750.h b/include/asm-sh/cpu_sh7750.h
index bb6461a..3c3c309 100644
--- a/include/asm-sh/cpu_sh7750.h
+++ b/include/asm-sh/cpu_sh7750.h
@@ -25,10 +25,10 @@
#ifdef CONFIG_CPU_TYPE_R
#define CACHE_OC_NUM_WAYS 2
-#define CCR_CACHE_INIT 0x8000090d /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
+#define CCR_CACHE_INIT 0x8000090D /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
#else
#define CACHE_OC_NUM_WAYS 1
-#define CCR_CACHE_INIT 0x0000090b
+#define CCR_CACHE_INIT 0x0000090B
#endif
/* OCN */
diff --git a/include/asm-sh/cpu_sh7780.h b/include/asm-sh/cpu_sh7780.h
new file mode 100644
index 0000000..d4f824e
--- /dev/null
+++ b/include/asm-sh/cpu_sh7780.h
@@ -0,0 +1,503 @@
+#ifndef _ASM_CPU_SH7780_H_
+#define _ASM_CPU_SH7780_H_
+
+/*
+ * Copyright (c) 2007,2008 Nobuhiro Iwamatsu
+ * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#define CACHE_OC_NUM_WAYS 1
+#define CCR_CACHE_INIT 0x0000090b
+
+/* Exceptions */
+#define TRA 0xFF000020
+#define EXPEVT 0xFF000024
+#define INTEVT 0xFF000028
+
+/* Memory Management Unit */
+#define PTEH 0xFF000000
+#define PTEL 0xFF000004
+#define TTB 0xFF000008
+#define TEA 0xFF00000C
+#define MMUCR 0xFF000010
+#define PASCR 0xFF000070
+#define IRMCR 0xFF000078
+
+/* Cache Controller */
+#define CCR 0xFF00001C
+#define QACR0 0xFF000038
+#define QACR1 0xFF00003C
+#define RAMCR 0xFF000074
+
+/* L Memory */
+#define RAMCR 0xFF000074
+#define LSA0 0xFF000050
+#define LSA1 0xFF000054
+#define LDA0 0xFF000058
+#define LDA1 0xFF00005C
+
+/* Interrupt Controller */
+#define ICR0 0xFFD00000
+#define ICR1 0xFFD0001C
+#define INTPRI 0xFFD00010
+#define INTREQ 0xFFD00024
+#define INTMSK0 0xFFD00044
+#define INTMSK1 0xFFD00048
+#define INTMSK2 0xFFD40080
+#define INTMSKCLR0 0xFFD00064
+#define INTMSKCLR1 0xFFD00068
+#define INTMSKCLR2 0xFFD40084
+#define NMIFCR 0xFFD000C0
+#define USERIMASK 0xFFD30000
+#define INT2PRI0 0xFFD40000
+#define INT2PRI1 0xFFD40004
+#define INT2PRI2 0xFFD40008
+#define INT2PRI3 0xFFD4000C
+#define INT2PRI4 0xFFD40010
+#define INT2PRI5 0xFFD40014
+#define INT2PRI6 0xFFD40018
+#define INT2PRI7 0xFFD4001C
+#define INT2A0 0xFFD40030
+#define INT2A1 0xFFD40034
+#define INT2MSKR 0xFFD40038
+#define INT2MSKCR 0xFFD4003C
+#define INT2B0 0xFFD40040
+#define INT2B1 0xFFD40044
+#define INT2B2 0xFFD40048
+#define INT2B3 0xFFD4004C
+#define INT2B4 0xFFD40050
+#define INT2B5 0xFFD40054
+#define INT2B6 0xFFD40058
+#define INT2B7 0xFFD4005C
+#define INT2GPIC 0xFFD40090
+
+/* local Bus State Controller */
+#define MMSELR 0xFF400020
+#define BCR 0xFF801000
+#define CS0BCR 0xFF802000
+#define CS1BCR 0xFF802010
+#define CS2BCR 0xFF802020
+#define CS4BCR 0xFF802040
+#define CS5BCR 0xFF802050
+#define CS6BCR 0xFF802060
+#define CS0WCR 0xFF802008
+#define CS1WCR 0xFF802018
+#define CS2WCR 0xFF802028
+#define CS4WCR 0xFF802048
+#define CS5WCR 0xFF802058
+#define CS6WCR 0xFF802068
+#define CS5PCR 0xFF802070
+#define CS6PCR 0xFF802080
+
+/* DDR-SDRAM I/F */
+#define MIM_1 0xFE800008
+#define MIM_2 0xFE80000C
+#define SCR_1 0xFE800010
+#define SCR_2 0xFE800014
+#define STR_1 0xFE800018
+#define STR_2 0xFE80001C
+#define SDR_1 0xFE800030
+#define SDR_2 0xFE800034
+#define DBK_1 0xFE800400
+#define DBK_2 0xFE800404
+
+/* PCI Controller */
+#define SH7780_PCIECR 0xFE000008
+#define SH7780_PCIVID 0xFE040000
+#define SH7780_PCIDID 0xFE040002
+#define SH7780_PCICMD 0xFE040004
+#define SH7780_PCISTATUS 0xFE040006
+#define SH7780_PCIRID 0xFE040008
+#define SH7780_PCIPIF 0xFE040009
+#define SH7780_PCISUB 0xFE04000A
+#define SH7780_PCIBCC 0xFE04000B
+#define SH7780_PCICLS 0xFE04000C
+#define SH7780_PCILTM 0xFE04000D
+#define SH7780_PCIHDR 0xFE04000E
+#define SH7780_PCIBIST 0xFE04000F
+#define SH7780_PCIIBAR 0xFE040010
+#define SH7780_PCIMBAR0 0xFE040014
+#define SH7780_PCIMBAR1 0xFE040018
+#define SH7780_PCISVID 0xFE04002C
+#define SH7780_PCISID 0xFE04002E
+#define SH7780_PCICP 0xFE040034
+#define SH7780_PCIINTLINE 0xFE04003C
+#define SH7780_PCIINTPIN 0xFE04003D
+#define SH7780_PCIMINGNT 0xFE04003E
+#define SH7780_PCIMAXLAT 0xFE04003F
+#define SH7780_PCICID 0xFE040040
+#define SH7780_PCINIP 0xFE040041
+#define SH7780_PCIPMC 0xFE040042
+#define SH7780_PCIPMCSR 0xFE040044
+#define SH7780_PCIPMCSRBSE 0xFE040046
+#define SH7780_PCI_CDD 0xFE040047
+#define SH7780_PCICR 0xFE040100
+#define SH7780_PCILSR0 0xFE040104
+#define SH7780_PCILSR1 0xFE040108
+#define SH7780_PCILAR0 0xFE04010C
+#define SH7780_PCILAR1 0xFE040110
+#define SH7780_PCIIR 0xFE040114
+#define SH7780_PCIIMR 0xFE040118
+#define SH7780_PCIAIR 0xFE04011C
+#define SH7780_PCICIR 0xFE040120
+#define SH7780_PCIAINT 0xFE040130
+#define SH7780_PCIAINTM 0xFE040134
+#define SH7780_PCIBMIR 0xFE040138
+#define SH7780_PCIPAR 0xFE0401C0
+#define SH7780_PCIPINT 0xFE0401CC
+#define SH7780_PCIPINTM 0xFE0401D0
+#define SH7780_PCIMBR0 0xFE0401E0
+#define SH7780_PCIMBMR0 0xFE0401E4
+#define SH7780_PCIMBR1 0xFE0401E8
+#define SH7780_PCIMBMR1 0xFE0401EC
+#define SH7780_PCIMBR2 0xFE0401F0
+#define SH7780_PCIMBMR2 0xFE0401F4
+#define SH7780_PCIIOBR 0xFE0401F8
+#define SH7780_PCIIOBMR 0xFE0401FC
+#define SH7780_PCICSCR0 0xFE040210
+#define SH7780_PCICSCR1 0xFE040214
+#define SH7780_PCICSAR0 0xFE040218
+#define SH7780_PCICSAR1 0xFE04021C
+#define SH7780_PCIPDR 0xFE040220
+
+/* DMAC */
+#define DMAC_SAR0 0xFC808020
+#define DMAC_DAR0 0xFC808024
+#define DMAC_TCR0 0xFC808028
+#define DMAC_CHCR0 0xFC80802C
+#define DMAC_SAR1 0xFC808030
+#define DMAC_DAR1 0xFC808034
+#define DMAC_TCR1 0xFC808038
+#define DMAC_CHCR1 0xFC80803C
+#define DMAC_SAR2 0xFC808040
+#define DMAC_DAR2 0xFC808044
+#define DMAC_TCR2 0xFC808048
+#define DMAC_CHCR2 0xFC80804C
+#define DMAC_SAR3 0xFC808050
+#define DMAC_DAR3 0xFC808054
+#define DMAC_TCR3 0xFC808058
+#define DMAC_CHCR3 0xFC80805C
+#define DMAC_DMAOR0 0xFC808060
+#define DMAC_SAR4 0xFC808070
+#define DMAC_DAR4 0xFC808074
+#define DMAC_TCR4 0xFC808078
+#define DMAC_CHCR4 0xFC80807C
+#define DMAC_SAR5 0xFC808080
+#define DMAC_DAR5 0xFC808084
+#define DMAC_TCR5 0xFC808088
+#define DMAC_CHCR5 0xFC80808C
+#define DMAC_SARB0 0xFC808120
+#define DMAC_DARB0 0xFC808124
+#define DMAC_TCRB0 0xFC808128
+#define DMAC_SARB1 0xFC808130
+#define DMAC_DARB1 0xFC808134
+#define DMAC_TCRB1 0xFC808138
+#define DMAC_SARB2 0xFC808140
+#define DMAC_DARB2 0xFC808144
+#define DMAC_TCRB2 0xFC808148
+#define DMAC_SARB3 0xFC808150
+#define DMAC_DARB3 0xFC808154
+#define DMAC_TCRB3 0xFC808158
+#define DMAC_DMARS0 0xFC809000
+#define DMAC_DMARS1 0xFC809004
+#define DMAC_DMARS2 0xFC809008
+#define DMAC_SAR6 0xFC818020
+#define DMAC_DAR6 0xFC818024
+#define DMAC_TCR6 0xFC818028
+#define DMAC_CHCR6 0xFC81802C
+#define DMAC_SAR7 0xFC818030
+#define DMAC_DAR7 0xFC818034
+#define DMAC_TCR7 0xFC818038
+#define DMAC_CHCR7 0xFC81803C
+#define DMAC_SAR8 0xFC818040
+#define DMAC_DAR8 0xFC818044
+#define DMAC_TCR8 0xFC818048
+#define DMAC_CHCR8 0xFC81804C
+#define DMAC_SAR9 0xFC818050
+#define DMAC_DAR9 0xFC818054
+#define DMAC_TCR9 0xFC818058
+#define DMAC_CHCR9 0xFC81805C
+#define DMAC_DMAOR1 0xFC818060
+#define DMAC_SAR10 0xFC818070
+#define DMAC_DAR10 0xFC818074
+#define DMAC_TCR10 0xFC818078
+#define DMAC_CHCR10 0xFC81807C
+#define DMAC_SAR11 0xFC818080
+#define DMAC_DAR11 0xFC818084
+#define DMAC_TCR11 0xFC818088
+#define DMAC_CHCR11 0xFC81808C
+#define DMAC_SARB6 0xFC818120
+#define DMAC_DARB6 0xFC818124
+#define DMAC_TCRB6 0xFC818128
+#define DMAC_SARB7 0xFC818130
+#define DMAC_DARB7 0xFC818134
+#define DMAC_TCRB7 0xFC818138
+#define DMAC_SARB8 0xFC818140
+#define DMAC_DARB8 0xFC818144
+#define DMAC_TCRB8 0xFC818148
+#define DMAC_SARB9 0xFC818150
+#define DMAC_DARB9 0xFC818154
+#define DMAC_TCRB9 0xFC818158
+
+/* Clock Pulse Generator */
+#define FRQCR 0xFFC80000
+#define PLLCR 0xFFC80024
+#define MSTPCR 0xFFC80030
+
+/* Watchdog Timer and Reset */
+#define WTCNT WDTCNT
+#define WDTST 0xFFCC0000
+#define WDTCSR 0xFFCC0004
+#define WDTBST 0xFFCC0008
+#define WDTCNT 0xFFCC0010
+#define WDTBCNT 0xFFCC0018
+
+/* System Control */
+#define MSTPCR 0xFFC80030
+
+/* Timer Unit */
+#define TSTR TSTR0
+#define TOCR 0xFFD80000
+#define TSTR0 0xFFD80004
+#define TCOR0 0xFFD80008
+#define TCNT0 0xFFD8000C
+#define TCR0 0xFFD80010
+#define TCOR1 0xFFD80014
+#define TCNT1 0xFFD80018
+#define TCR1 0xFFD8001C
+#define TCOR2 0xFFD80020
+#define TCNT2 0xFFD80024
+#define TCR2 0xFFD80028
+#define TCPR2 0xFFD8002C
+#define TSTR1 0xFFDC0004
+#define TCOR3 0xFFDC0008
+#define TCNT3 0xFFDC000C
+#define TCR3 0xFFDC0010
+#define TCOR4 0xFFDC0014
+#define TCNT4 0xFFDC0018
+#define TCR4 0xFFDC001C
+#define TCOR5 0xFFDC0020
+#define TCNT5 0xFFDC0024
+#define TCR5 0xFFDC0028
+
+/* Timer/Counter */
+#define CMTCFG 0xFFE30000
+#define CMTFRT 0xFFE30004
+#define CMTCTL 0xFFE30008
+#define CMTIRQS 0xFFE3000C
+#define CMTCH0T 0xFFE30010
+#define CMTCH0ST 0xFFE30020
+#define CMTCH0C 0xFFE30030
+#define CMTCH1T 0xFFE30014
+#define CMTCH1ST 0xFFE30024
+#define CMTCH1C 0xFFE30034
+#define CMTCH2T 0xFFE30018
+#define CMTCH2C 0xFFE30038
+#define CMTCH3T 0xFFE3001C
+#define CMTCH3C 0xFFE3003C
+
+/* Realtime Clock */
+#define R64CNT 0xFFE80000
+#define RSECCNT 0xFFE80004
+#define RMINCNT 0xFFE80008
+#define RHRCNT 0xFFE8000C
+#define RWKCNT 0xFFE80010
+#define RDAYCNT 0xFFE80014
+#define RMONCNT 0xFFE80018
+#define RYRCNT 0xFFE8001C
+#define RSECAR 0xFFE80020
+#define RMINAR 0xFFE80024
+#define RHRAR 0xFFE80028
+#define RWKAR 0xFFE8002C
+#define RDAYAR 0xFFE80030
+#define RMONAR 0xFFE80034
+#define RCR1 0xFFE80038
+#define RCR2 0xFFE8003C
+#define RCR3 0xFFE80050
+#define RYRAR 0xFFE80054
+
+/* Serial Communication Interface with FIFO */
+#define SCIF0_BASE SCSMR0
+#define SCSMR0 0xFFE00000
+#define SCBRR0 0xFFE00004
+#define SCSCR0 0xFFE00008
+#define SCFSR0 0xFFE00010
+#define SCFCR0 0xFFE00018
+#define SCTFDR0 0xFFE0001C
+#define SCRFDR0 0xFFE00020
+#define SCSPTR0 0xFFE00024
+#define SCLSR0 0xFFE00028
+#define SCRER0 0xFFE0002C
+#define SCSMR1 0xFFE10000
+#define SCBRR1 0xFFE10004
+#define SCSCR1 0xFFE10008
+#define SCFSR1 0xFFE10010
+#define SCFCR1 0xFFE10018
+#define SCTFDR1 0xFFE1001C
+#define SCRFDR1 0xFFE10020
+#define SCSPTR1 0xFFE10024
+#define SCLSR1 0xFFE10028
+#define SCRER1 0xFFE1002C
+
+/* Serial I/O with FIFO */
+#define SIMDR 0xFFE20000
+#define SISCR 0xFFE20002
+#define SITDAR 0xFFE20004
+#define SIRDAR 0xFFE20006
+#define SICDAR 0xFFE20008
+#define SICTR 0xFFE2000C
+#define SIFCTR 0xFFE20010
+#define SISTR 0xFFE20014
+#define SIIER 0xFFE20016
+#define SITCR 0xFFE20028
+#define SIRCR 0xFFE2002C
+#define SPICR 0xFFE20030
+
+/* Serial Protocol Interface */
+#define SPCR 0xFFE50000
+#define SPSR 0xFFE50004
+#define SPSCR 0xFFE50008
+#define SPTBR 0xFFE5000C
+#define SPRBR 0xFFE50010
+
+/* Multimedia Card Interface */
+#define CMDR0 0xFFE60000
+#define CMDR1 0xFFE60001
+#define CMDR2 0xFFE60002
+#define CMDR3 0xFFE60003
+#define CMDR4 0xFFE60004
+#define CMDR5 0xFFE60005
+#define CMDSTRT 0xFFE60006
+#define OPCR 0xFFE6000A
+#define CSTR 0xFFE6000B
+#define INTCR0 0xFFE6000C
+#define INTCR1 0xFFE6000D
+#define INTSTR0 0xFFE6000E
+#define INTSTR1 0xFFE6000F
+#define CLKON 0xFFE60010
+#define CTOCR 0xFFE60011
+#define TBCR 0xFFE60014
+#define MODER 0xFFE60016
+#define CMDTYR 0xFFE60018
+#define RSPTYR 0xFFE60019
+#define TBNCR 0xFFE6001A
+#define RSPR0 0xFFE60020
+#define RSPR1 0xFFE60021
+#define RSPR2 0xFFE60022
+#define RSPR3 0xFFE60023
+#define RSPR4 0xFFE60024
+#define RSPR5 0xFFE60025
+#define RSPR6 0xFFE60026
+#define RSPR7 0xFFE60027
+#define RSPR8 0xFFE60028
+#define RSPR9 0xFFE60029
+#define RSPR10 0xFFE6002A
+#define RSPR11 0xFFE6002B
+#define RSPR12 0xFFE6002C
+#define RSPR13 0xFFE6002D
+#define RSPR14 0xFFE6002E
+#define RSPR15 0xFFE6002F
+#define RSPR16 0xFFE60030
+#define RSPRD 0xFFE60031
+#define DTOUTR 0xFFE60032
+#define DR 0xFFE60040
+#define DMACR 0xFFE60044
+#define INTCR2 0xFFE60046
+#define INTSTR2 0xFFE60048
+
+/* Audio Codec Interface */
+#define HACCR 0xFFE40008
+#define HACCSAR 0xFFE40020
+#define HACCSDR 0xFFE40024
+#define HACPCML 0xFFE40028
+#define HACPCMR 0xFFE4002C
+#define HACTIER 0xFFE40050
+#define HACTSR 0xFFE40054
+#define HACRIER 0xFFE40058
+#define HACRSR 0xFFE4005C
+#define HACACR 0xFFE40060
+
+/* Serial Sound Interface */
+#define SSICR 0xFFE70000
+#define SSISR 0xFFE70004
+#define SSITDR 0xFFE70008
+#define SSIRDR 0xFFE7000C
+
+/* Flash memory Controller */
+#define FLCMNCR 0xFFE90000
+#define FLCMDCR 0xFFE90004
+#define FLCMCDR 0xFFE90008
+#define FLADR 0xFFE9000C
+#define FLDATAR 0xFFE90010
+#define FLDTCNTR 0xFFE90014
+#define FLINTDMACR 0xFFE90018
+#define FLBSYTMR 0xFFE9001C
+#define FLBSYCNT 0xFFE90020
+#define FLTRCR 0xFFE9002C
+
+/* General Purpose I/O */
+#define PACR 0xFFEA0000
+#define PBCR 0xFFEA0002
+#define PCCR 0xFFEA0004
+#define PDCR 0xFFEA0006
+#define PECR 0xFFEA0008
+#define PFCR 0xFFEA000A
+#define PGCR 0xFFEA000C
+#define PHCR 0xFFEA000E
+#define PJCR 0xFFEA0010
+#define PKCR 0xFFEA0012
+#define PLCR 0xFFEA0014
+#define PMCR 0xFFEA0016
+#define PADR 0xFFEA0020
+#define PBDR 0xFFEA0022
+#define PCDR 0xFFEA0024
+#define PDDR 0xFFEA0026
+#define PEDR 0xFFEA0028
+#define PFDR 0xFFEA002A
+#define PGDR 0xFFEA002C
+#define PHDR 0xFFEA002E
+#define PJDR 0xFFEA0030
+#define PKDR 0xFFEA0032
+#define PLDR 0xFFEA0034
+#define PMDR 0xFFEA0036
+#define PEPUPR 0xFFEA0048
+#define PHPUPR 0xFFEA004E
+#define PJPUPR 0xFFEA0050
+#define PKPUPR 0xFFEA0052
+#define PMPUPR 0xFFEA0056
+#define PPUPR1 0xFFEA0060
+#define PPUPR2 0xFFEA0062
+#define PMSELR 0xFFEA0080
+
+/* User Break Controller */
+#define CBR0 0xFF200000
+#define CRR0 0xFF200004
+#define CAR0 0xFF200008
+#define CAMR0 0xFF20000C
+#define CBR1 0xFF200020
+#define CRR1 0xFF200024
+#define CAR1 0xFF200028
+#define CAMR1 0xFF20002C
+#define CDR1 0xFF200030
+#define CDMR1 0xFF200034
+#define CETR1 0xFF200038
+#define CCMFR 0xFF200600
+#define CBCR 0xFF200620
+
+#endif /* _ASM_CPU_SH7780_H_ */
diff --git a/include/asm-sh/pci.h b/include/asm-sh/pci.h
new file mode 100644
index 0000000..bc59491
--- /dev/null
+++ b/include/asm-sh/pci.h
@@ -0,0 +1,47 @@
+/*
+ * SH4 PCI Controller (PCIC) for U-Boot.
+ * (C) Dustin McIntire (dustin@sensoria.com)
+ * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * u-boot/include/asm-sh/pci.h
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _ASM_PCI_H_
+#define _ASM_PCI_H_
+
+#include <pci.h>
+#if defined(CONFIG_SH7751_PCI)
+int pci_sh7751_init(struct pci_controller *hose);
+#elif defined(CONFIG_SH7780_PCI)
+int pci_sh7780_init(struct pci_controller *hose);
+#else
+#error "Not support PCI."
+#endif
+
+/* PCI dword read for sh4 */
+int pci_sh4_read_config_dword(struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32 *value);
+
+/* PCI dword write for sh4 */
+int pci_sh4_write_config_dword(struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32 value);
+
+#endif /* _ASM_PCI_H_ */
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index bb9a35f..388aa69 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -2,7 +2,8 @@
#define _ASM_SH_PROCESSOR_H_
#if defined CONFIG_SH3
# include <asm/cpu_sh3.h>
-#elif defined (CONFIG_SH4)
+#elif defined (CONFIG_SH4) || \
+ defined (CONFIG_SH4A)
# include <asm/cpu_sh4.h>
#endif
#endif
diff --git a/include/configs/DU440.h b/include/configs/DU440.h
index 4fb6921..d54da97 100644
--- a/include/configs/DU440.h
+++ b/include/configs/DU440.h
@@ -157,10 +157,9 @@
*/
#define CFG_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
+#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
+ /* 440EPx errata CHIP 11 */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
-#if 0
-#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
-#endif
#define CONFIG_DDR_ECC /* Use ECC when available */
#define SPD_EEPROM_ADDRESS {0x50}
#define CONFIG_PROG_SDRAM_TLB
@@ -244,9 +243,6 @@
"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
"cp.b 100000 FFFA0000 60000\0" \
""
-#if 0
-#define CONFIG_BOOTCOMMAND "run flash_self"
-#endif
#define CONFIG_PREBOOT /* enable preboot variable */
@@ -264,7 +260,7 @@ int du440_phy_addr(int devnum);
#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_PHY_GIGE 1 /* Include GbE detection */
+#undef CONFIG_PHY_GIGE /* no GbE detection */
#define CONFIG_HAS_ETH0
#define CFG_RX_ETH_BUFFER 128
@@ -295,7 +291,9 @@ int du440_phy_addr(int devnum);
#include <config_cmd_default.h>
+#define CONFIG_CMD_AUTOSCRIPT
#define CONFIG_CMD_BSP
+#define CONFIG_CMD_BMP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
@@ -431,8 +429,6 @@ int du440_phy_addr(int devnum);
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
-#if 0
-#define CONFIG_SHOW_ACTIVITY 1
-#endif
+#define CONFIG_AUTOSCRIPT 1
#endif /* __CONFIG_H */
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index a3d7bc4..3d28913 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -86,6 +86,7 @@
"save\0" \
""
+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
/* LCD */
#ifdef CONFIG_CMD_BMP
#define CONFIG_LCD
diff --git a/include/configs/r5200.h b/include/configs/M5275EVB.h
index fc7658b..599f8dc 100644
--- a/include/configs/r5200.h
+++ b/include/configs/M5275EVB.h
@@ -1,9 +1,11 @@
/*
- * Configuation settings for the R5200 board
+ * Configuation settings for the Motorola MC5275EVB board.
*
- * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
- * Based on Motorola MC5272C3 board config
- * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ * By Arthur Shipkowski <art@videon-central.com>
+ * Copyright (C) 2005 Videon Central, Inc.
+ *
+ * Based off of M5272C3 board code by Josef Baumgartner
+ * <josef.baumgartner@telex.de>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -28,42 +30,38 @@
* board/config.h - configuration options, board specific
*/
-#ifndef _R5200_H
-#define _R5200_H
+#ifndef _M5275EVB_H
+#define _M5275EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF52x2 /* define processor family */
-#define CONFIG_M5271 /* define processor type */
-#define CONFIG_R5200 /* define board type */
+#define CONFIG_M5275 /* define processor type */
+#define CONFIG_M5275EVB /* define board type */
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
-#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
-
-#define CONFIG_WATCHDOG
-#define CONFIG_WATCHDOG_TIMEOUT 0xFFFF /* clock modulus */
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
-#define CFG_ENV_OFFSET 0x20000
-#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_ENV_OFFSET 0x4000
+#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_IS_EMBEDDED 1
#else
-#define CFG_ENV_ADDR 0xf0020000
+#define CFG_ENV_ADDR 0xffe04000
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#endif
-
/*
* BOOTP options
*/
@@ -72,64 +70,80 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
+/* Available command configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DHCP
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
-# define CONFIG_NET_MULTI 1
-# define CONFIG_MII 1
-# define CFG_DISCOVER_PHY
-# define CFG_RX_ETH_BUFFER 8
-# define CFG_FAULT_ECHO_LINK_DOWN
-
-# define CFG_FEC0_PINMUX 0
-# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MII 1
+#define CFG_DISCOVER_PHY
+#define CFG_RX_ETH_BUFFER 8
+#define CFG_FAULT_ECHO_LINK_DOWN
+#define CFG_FEC0_PINMUX 0
+#define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+#define CFG_FEC1_PINMUX 0
+#define CFG_FEC1_MIIBASE CFG_FEC1_IOBASE
+#define MCFFEC_TOUT_LOOP 50000
+#define CONFIG_HAS_ETH1
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
-# ifndef CFG_DISCOVER_PHY
-# define FECDUPLEX FULL
-# define FECSPEED _100BASET
-# else
-# ifndef CFG_FAULT_ECHO_LINK_DOWN
-# define CFG_FAULT_ECHO_LINK_DOWN
-# endif
-# endif /* CFG_DISCOVER_PHY */
+#ifndef CFG_DISCOVER_PHY
+#define FECDUPLEX FULL
+#define FECSPEED _100BASET
+#else
+#ifndef CFG_FAULT_ECHO_LINK_DOWN
+#define CFG_FAULT_ECHO_LINK_DOWN
+#endif
+#endif
#endif
-/* Note: We only copy one sectors worth of application code from location
- * 10200000 for speed purposes. Increase the size if necessary */
-#define CONFIG_BOOTCOMMAND "cp.b 10200000 0 20000; go 400"
-#define CONFIG_BOOTDELAY 1
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C
+#define CFG_I2C_SPEED 80000
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x00000300
+#define CFG_IMMR CFG_MBAR
-#define CFG_PROMPT "u-boot> "
-#define CFG_LONGHELP /* undef to save memory */
+#ifdef CONFIG_MCFFEC
+#define CONFIG_ETHADDR 00:06:3b:01:41:55
+#define CONFIG_ETH1ADDR 00:0e:0c:bc:e5:60
+#endif
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_PROMPT "-> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#if (CONFIG_CMD_KGDB)
+# define CFG_CBSIZE 1024
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+# define CFG_CBSIZE 256
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_MAXARGS 16
+#define CFG_BARGSIZE CFG_CBSIZE
-#define CFG_LOAD_ADDR 0x00002000
+#define CFG_LOAD_ADDR 0x800000
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOTCOMMAND "bootm ffe40000"
#define CFG_MEMTEST_START 0x400
#define CFG_MEMTEST_END 0x380000
-#define CFG_HZ 1000000
-#define CFG_CLK 100000000
+#define CFG_HZ 1000
+#define CFG_CLK 150000000
/*
* Low Level Configuration Settings
@@ -137,16 +151,14 @@
* You should know what you are doing if you make changes here.
*/
-#define CFG_MBAR 0x40000000 /* Register Base Addrs */
-
-#define CFG_ENET_BD_BASE 0x480000
+#define CFG_MBAR 0x40000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
-#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
-#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
+#define CFG_GBL_DATA_SIZE 1000 /* bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -156,16 +168,16 @@
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */
-#define CFG_FLASH_BASE 0x10000000
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_FLASH_BASE 0xffe00000
-#ifdef CONFIG_MONITOR_IS_IN_RAM
+#ifdef CONFIG_MONITOR_IS_IN_RAM
#define CFG_MONITOR_BASE 0x20000
#else
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
#endif
-#define CFG_MONITOR_LEN 0x20001
+#define CFG_MONITOR_LEN 0x20000
#define CFG_MALLOC_LEN (256 << 10)
#define CFG_BOOTPARAMS_LEN 64*1024
@@ -174,18 +186,18 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial mmap for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 1000
#define CFG_FLASH_CFI 1
#define CFG_FLASH_CFI_DRIVER 1
-#define CFG_FLASH_SIZE 0x800000
+#define CFG_FLASH_SIZE 0x200000
/*-----------------------------------------------------------------------
* Cache Configuration
@@ -195,10 +207,17 @@
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
+#define CFG_AR0_PRELIM (CFG_FLASH_BASE >> 16)
+#define CFG_CR0_PRELIM 0x1980
+#define CFG_MR0_PRELIM 0x001F0001
+
+#define CFG_AR1_PRELIM 0x3000
+#define CFG_CR1_PRELIM 0x1900
+#define CFG_MR1_PRELIM 0x00070001
/*-----------------------------------------------------------------------
* Port configuration
*/
-#define CFG_FECI2C 0xF0
+#define CFG_FECI2C 0x0FA0
-#endif /* _R5200_H */
+#endif /* _M5275EVB_H */
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 5f55761..f33ccb0 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -171,6 +171,10 @@
#define CFG_I2C_OFFSET 0x58000
#define CFG_IMMR CFG_MBAR
+/* DSPI and Serial Flash */
+#define CONFIG_CF_DSPI
+#define CONFIG_SERIAL_FLASH
+
/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI 1
@@ -309,7 +313,7 @@
#else
-# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+# define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
# define CFG_ATMEL_REGION 4
# define CFG_ATMEL_TOTALSECT 11
@@ -326,6 +330,28 @@
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
# define CFG_FLASH_CHECKSUM
+#ifdef CONFIG_SERIAL_FLASH
+# define CFG_FLASH2_BASE 0x01000000
+# define CFG_STM_SECT 32
+# define CFG_STM_SECTSZ 0x10000
+
+# undef CFG_FLASH_ERASE_TOUT
+# define CFG_FLASH_ERASE_TOUT 20000
+
+# define SER_WREN 0x06
+# define SER_WRDI 0x04
+# define SER_RDID 0x9F
+# define SER_RDSR 0x05
+# define SER_WRSR 0x01
+# define SER_READ 0x03
+# define SER_F_READ 0x0B
+# define SER_PAGE_PROG 0x02
+# define SER_SECT_ERASE 0xD8
+# define SER_BULK_ERASE 0xC7
+# define SER_DEEP_PWRDN 0xB9
+# define SER_RES 0xAB
+#endif
+
#endif
/*
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index af78726..432fb31 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -349,6 +349,29 @@
#define CONFIG_ETHPRIME "eTSEC1"
/*
+ * SATA
+ */
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CFG_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CFG_SATA1_OFFSET 0x18000
+#define CFG_SATA1 (CFG_IMMR + CFG_SATA1_OFFSET)
+#define CFG_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CFG_SATA2_OFFSET 0x19000
+#define CFG_SATA2 (CFG_IMMR + CFG_SATA2_OFFSET)
+#define CFG_SATA2_FLAGS FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
* Environment
*/
#ifndef CFG_RAMBOOT
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 94c4c6b..92d7aa4 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -323,8 +323,11 @@
/*
* Config on-board EEPROM
*/
-#define CFG_I2C_EEPROM_ADDR 0x50
-#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_BITS 6
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*
* General PCI
@@ -341,7 +344,7 @@
#define CFG_PCI1_IO_SIZE 0x04000000 /* 64M */
#ifdef CONFIG_PCI
-
+#define CONFIG_PCI_SKIP_HOST_BRIDGE
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
@@ -549,6 +552,9 @@
#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02
+/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CFG_I2C_EEPROM) */
+#define CFG_I2C_MAC_OFFSET 0x7f00 /* MAC address offset in I2C EEPROM */
+
#define CONFIG_IPADDR 10.0.0.2
#define CONFIG_SERVERIP 10.0.0.1
#define CONFIG_GATEWAYIP 10.0.0.1
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index b307bf7..7c4e76e 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -389,6 +389,34 @@
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "eTSEC1"
+/* SERDES */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1 0xe3000
+#define CONFIG_FSL_SERDES2 0xe3100
+
+/*
+ * SATA
+ */
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CFG_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CFG_SATA1_OFFSET 0x18000
+#define CFG_SATA1 (CFG_IMMR + CFG_SATA1_OFFSET)
+#define CFG_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CFG_SATA2_OFFSET 0x19000
+#define CFG_SATA2 (CFG_IMMR + CFG_SATA2_OFFSET)
+#define CFG_SATA2_FLAGS FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
/*
* Environment
*/
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 90812e9..eaac525 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -416,6 +416,29 @@
#endif
/*
+ * SATA
+ */
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CFG_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CFG_SATA1_OFFSET 0x18000
+#define CFG_SATA1 (CFG_IMMR + CFG_SATA1_OFFSET)
+#define CFG_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CFG_SATA2_OFFSET 0x19000
+#define CFG_SATA2 (CFG_IMMR + CFG_SATA2_OFFSET)
+#define CFG_SATA2_FLAGS FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
* Environment
*/
#ifndef CFG_RAMBOOT
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
new file mode 100644
index 0000000..99e1179
--- /dev/null
+++ b/include/configs/MigoR.h
@@ -0,0 +1,151 @@
+/*
+ * Configuation settings for the Renesas Solutions Migo-R board
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MIGO_R_H
+#define __MIGO_R_H
+
+#undef DEBUG
+#define CONFIG_SH 1
+#define CONFIG_SH4 1
+#define CONFIG_CPU_SH7722 1
+#define CONFIG_MIGO_R 1
+
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_ENV
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.10.100
+#define CONFIG_SERVERIP 192.168.10.77
+#define CONFIG_GATEWAYIP 192.168.10.77
+
+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+/* SMC9111 */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE (0xB0000000)
+
+/* MEMORY */
+#define MIGO_R_SDRAM_BASE (0x8C000000)
+#define MIGO_R_FLASH_BASE_1 (0xA0000000)
+#define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024)
+
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Buffer size for input from the Console */
+#define CFG_PBSIZE 256 /* Buffer size for Console output */
+#define CFG_MAXARGS 16 /* max args accepted for monitor commands */
+#define CFG_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */
+#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
+
+/* SCIF */
+#define CFG_SCIF_CONSOLE 1
+#define CONFIG_CONS_SCIF0 1
+#undef CFG_CONSOLE_INFO_QUIET /* Suppress display of console
+ information at boot */
+#undef CFG_CONSOLE_OVERWRITE_ROUTINE
+#undef CFG_CONSOLE_ENV_OVERWRITE
+
+#define CFG_MEMTEST_START (MIGO_R_SDRAM_BASE)
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024))
+
+/* Enable alternate, more extensive, memory test */
+#undef CFG_ALT_MEMTEST
+/* Scratch address used by the alternate memory test */
+#undef CFG_MEMTEST_SCRATCH
+
+/* Enable temporary baudrate change while serial download */
+#undef CFG_LOADS_BAUD_CHANGE
+
+#define CFG_SDRAM_BASE (MIGO_R_SDRAM_BASE)
+/* maybe more, but if so u-boot doesn't know about it... */
+#define CFG_SDRAM_SIZE (64 * 1024 * 1024)
+/* default load address for scripts ?!? */
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 16 * 1024 * 1024)
+
+/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
+#define CFG_MONITOR_BASE (MIGO_R_FLASH_BASE_1)
+/* Monitor size */
+#define CFG_MONITOR_LEN (128 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CFG_MALLOC_LEN (256 * 1024)
+/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE (256)
+#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
+
+/* FLASH */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#undef CFG_FLASH_QUIET_TEST
+/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO
+/* Physical start address of Flash memory */
+#define CFG_FLASH_BASE (MIGO_R_FLASH_BASE_1)
+/* Max number of sectors on each Flash chip */
+#define CFG_MAX_FLASH_SECT 512
+
+/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
+
+/* Timeout for Flash erase operations (in ms) */
+#define CFG_FLASH_ERASE_TOUT (3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CFG_FLASH_WRITE_TOUT (3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CFG_FLASH_LOCK_TOUT (3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT (3 * 1000)
+
+/* Use hardware flash sectors protection instead of U-Boot software protection */
+#undef CFG_FLASH_PROTECTION
+#undef CFG_DIRECT_FLASH_TFTP
+
+/* ENV setting */
+#define CFG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE 1
+#define CFG_ENV_SECT_SIZE (128 * 1024)
+#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
+/* Offset of env Flash sector relative to CFG_FLASH_BASE */
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE)
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ 33333333
+#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
+#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+
+#endif /* __MIGO_R_H */
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index 38fb7c6..3e906c4 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2006-2007
+ * (C) Copyright 2006-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -35,6 +35,7 @@
#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+#define CONFIG_4xx_DCACHE /* Enable i- and d-cache */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
@@ -144,6 +145,8 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth3\0" \
"hostname=alpr\0" \
+ "fdt_file=alpr/alpr.dtb\0" \
+ "fdt_addr=400000\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath} ${init}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
@@ -158,6 +161,10 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
+ "net_nfs_fdt=tftp 200000 ${bootfile};" \
+ "tftp ${fdt_addr} ${fdt_file};" \
+ "run nfsargs addip addtty;" \
+ "bootm 200000 - ${fdt_addr}\0" \
"rootpath=/opt/projects/alpr/nfs_root\0" \
"bootfile=/alpr/uImage\0" \
"kernel_addr=fff00000\0" \
@@ -370,4 +377,9 @@
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
index f2c8703..2f551ad 100644
--- a/include/configs/bf533-ezkit.h
+++ b/include/configs/bf533-ezkit.h
@@ -8,7 +8,6 @@
#include <asm/blackfin-config-pre.h>
#define CONFIG_BAUDRATE 57600
-#define CONFIG_STAMP 1
#define CONFIG_BOOTDELAY 5
#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */
@@ -30,28 +29,15 @@
#define CONFIG_RTC_BFIN 1
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
-/*
- * Boot Mode Set
- * Blackfin can support several boot modes
- */
-#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
-#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
-#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */
-/* Define the boot mode */
-#define BFIN_BOOT_MODE BF533_BYPASS_BOOT
-/* #define BFIN_BOOT_MODE BF533_SPI_BOOT */
-
#define CONFIG_PANIC_HANG 1
#define CONFIG_BFIN_CPU bf533-0.3
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/* This sets the default state of the cache on U-Boot's boot */
#define CONFIG_ICACHE_ON
#define CONFIG_DCACHE_ON
-/* Define where the uboot will be loaded by on-chip boot rom */
-#define APP_ENTRY 0x00001000
-
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 27000000
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
@@ -216,24 +202,14 @@
#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
-/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
-/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
-#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
- ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
-#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
- B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
-*/
-#define AMGCTLVAL 0xFF
-#define AMBCTL0VAL 0x7BB07BB0
-#define AMBCTL1VAL 0xFFC27BB0
-
-#define CONFIG_VDSP 1
-
-#ifdef CONFIG_VDSP
-#define ET_EXEC_VDSP 0x8
-#define SHT_STRTAB_VDSP 0x1
-#define ELFSHDRSIZE_VDSP 0x2C
-#define VDSP_ENTRY_ADDR 0xFFA00000
-#endif
+#define CONFIG_EBIU_SDRRC_VAL 0x398
+#define CONFIG_EBIU_SDGCTL_VAL 0x91118d
+#define CONFIG_EBIU_SDBCTL_VAL 0x13
+
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
+
+#include <asm/blackfin-config-post.h>
#endif
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index 76dd2fa..66a0af6 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -7,37 +7,17 @@
#include <asm/blackfin-config-pre.h>
-#define CONFIG_STAMP 1
#define CONFIG_RTC_BFIN 1
-#define CONFIG_BF533 1
-/*
- * Boot Mode Set
- * Blackfin can support several boot modes
- */
-#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
-#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
-#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */
-/* Define the boot mode */
-#define BFIN_BOOT_MODE BF533_BYPASS_BOOT
-/* #define BFIN_BOOT_MODE BF533_SPI_BOOT */
#define CONFIG_PANIC_HANG 1
#define CONFIG_BFIN_CPU bf533-0.3
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/* This sets the default state of the cache on U-Boot's boot */
#define CONFIG_ICACHE_ON
#define CONFIG_DCACHE_ON
-/* Define where the uboot will be loaded by on-chip boot rom */
-#define APP_ENTRY 0x00001000
-
-/*
- * Stringize definitions - needed for environmental settings
- */
-#define STRINGIZE2(x) #x
-#define STRINGIZE(x) STRINGIZE2(x)
-
/*
* Board settings
*/
@@ -61,8 +41,6 @@
*/
#define CONFIG_VIDEO 0
-#define CONFIG_VDSP 1
-
/*
* Clock settings
*/
@@ -88,10 +66,7 @@
/* Values can range from 2-65535 */
/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
#define CONFIG_SPI_BAUD 2
-
-#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
#define CONFIG_SPI_BAUD_INITBLOCK 4
-#endif
/*
* Network settings
@@ -126,14 +101,14 @@
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
-#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR 0x20004000
-#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
-#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CFG_ENV_IS_IN_EEPROM 1
#define CFG_ENV_OFFSET 0x4000
#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */
+#else
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR 0x20004000
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
#endif
#define CFG_ENV_SIZE 0x2000
@@ -165,11 +140,7 @@
#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */
#define CONFIG_MEM_MT48LC64M4A2FB_7E 1
-#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
-#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
-#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
-#endif
#define CFG_SDRAM_BASE 0x00000000
@@ -207,14 +178,6 @@
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
#endif
-#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
-#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
-#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
-#else
-#undef CONFIG_SPI_FLASH_FAST_READ
-#endif
-#endif
-
/*
* Command settings
*/
@@ -222,26 +185,18 @@
#define CFG_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
-#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */
-#endif
/* configuration lookup from the BOOTP/DHCP server, */
/* but not try to load any image using TFTP */
#define CONFIG_BOOTDELAY 5
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
-#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#define CONFIG_BOOTCOMMAND "run ramboot"
-#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
-#define CONFIG_BOOTCOMMAND "eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000"
-#endif
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
-#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
-#if (CONFIG_DRIVER_SMC91111)
#define CONFIG_EXTRA_ENV_SETTINGS \
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
@@ -257,29 +212,6 @@
"protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
""
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
- "flashboot=bootm 0x20100000\0" \
- "
-#endif
-
-#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
- "$(rootpath) console=ttyBF0,57600\0" \
- "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
- "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
- "ramboot=tftpboot $(loadaddr) linux; " \
- "run ramargs;run addip;bootelf\0" \
- "nfsboot=tftpboot $(loadaddr) linux; " \
- "run nfsargs;run addip;bootelf\0" \
- "flashboot=bootm 0x20100000\0" \
- "update=tftpboot $(loadaddr) u-boot.ldr;" \
- "eeprom write $(loadaddr) 0x0 $(filesize);\0"\
- ""
-#endif
#ifdef CONFIG_SOFT_I2C
#if (!CONFIG_SOFT_I2C)
@@ -316,9 +248,7 @@
#define CONFIG_CMD_I2C
#endif
-#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#define CONFIG_CMD_DHCP
-#endif
/*
@@ -428,25 +358,16 @@
/*
* FLASH organization and environment definitions
*/
-#define CFG_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */
-
-/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
-/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
-#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \
- B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
-#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \
- B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
-*/
-#define AMGCTLVAL 0xFF
-#define AMBCTL0VAL 0xBBC3BBC3
-#define AMBCTL1VAL 0x99B39983
-#define CF_AMBCTL1VAL 0x99B3ffc2
-
-#ifdef CONFIG_VDSP
-#define ET_EXEC_VDSP 0x8
-#define SHT_STRTAB_VDSP 0x1
-#define ELFSHDRSIZE_VDSP 0x2C
-#define VDSP_ENTRY_ADDR 0xFFA00000
-#endif
+
+#define CONFIG_EBIU_SDRRC_VAL 0x268
+#define CONFIG_EBIU_SDGCTL_VAL 0x911109
+#define CONFIG_EBIU_SDBCTL_VAL 0x37
+
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
+#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
+#define CF_CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
+
+#include <asm/blackfin-config-post.h>
#endif
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 0e189d4..39c7359 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -12,28 +12,15 @@
#define CONFIG_BAUDRATE 57600
/* Set default serial console for bf537 */
#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BF537 1
#define CONFIG_BOOTDELAY 5
/* define CONFIG_BF537_STAMP_LEDCMD to enable LED command*/
/*#define CONFIG_BF537_STAMP_LEDCMD 1*/
-/*
- * Boot Mode Set
- * Blackfin can support several boot modes
- */
-#define BF537_BYPASS_BOOT 0x0011 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
-#define BF537_PARA_BOOT 0x0012 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
-#define BF537_SPI_MASTER_BOOT 0x0014 /* Bootmode 3: SPI master mode boot from SPI flash */
-#define BF537_SPI_SLAVE_BOOT 0x0015 /* Bootmode 4: SPI slave mode boot from SPI flash */
-#define BF537_TWI_MASTER_BOOT 0x0016 /* Bootmode 5: TWI master mode boot from EEPROM */
-#define BF537_TWI_SLAVE_BOOT 0x0017 /* Bootmode 6: TWI slave mode boot from EEPROM */
-#define BF537_UART_BOOT 0x0018 /* Bootmode 7: UART slave mdoe boot via UART host */
-/* Define the boot mode */
-#define BFIN_BOOT_MODE BF537_BYPASS_BOOT
-
#define CONFIG_PANIC_HANG 1
#define CONFIG_BFIN_CPU bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
+
#define CONFIG_BFIN_MAC
/* This sets the default state of the cache on U-Boot's boot */
@@ -43,9 +30,6 @@
/* Define if want to do post memory test */
#undef CONFIG_POST_TEST
-/* Define where the uboot will be loaded by on-chip boot rom */
-#define APP_ENTRY 0x00001000
-
#define CONFIG_RTC_BFIN 1
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
@@ -70,9 +54,7 @@
/* Values can range from 2-65535 */
/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
#define CONFIG_SPI_BAUD 2
-#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
#define CONFIG_SPI_BAUD_INITBLOCK 4
-#endif
#if ( CONFIG_CLKIN_HALF == 0 )
#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
@@ -88,14 +70,6 @@
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
#endif
-#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
-#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
-#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
-#else
-#undef CONFIG_SPI_FLASH_FAST_READ
-#endif
-#endif
-
#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */
#define CONFIG_MEM_MT48LC32M8A2_75 1
@@ -131,7 +105,7 @@
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
#define CONFIG_BOOTCOMMAND "run ramboot"
-#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) && defined(CONFIG_POST_TEST)
+#if defined(CONFIG_POST_TEST)
/* POST support */
#define CONFIG_POST ( CFG_POST_MEMORY | \
CFG_POST_UART | \
@@ -177,8 +151,6 @@
*/
#include <config_cmd_default.h>
-#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
-
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_CACHE
@@ -198,10 +170,6 @@
#define CONFIG_CMD_IDE
#endif
-#endif
-
-#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
-
#define CONFIG_CMD_DHCP
#if defined(CONFIG_POST)
@@ -212,14 +180,10 @@
#define CONFIG_CMD_NAND
#endif
-#endif
-
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
#define CONFIG_LOADADDR 0x1000000
-#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
-#ifdef CONFIG_BFIN_MAC
#define CONFIG_EXTRA_ENV_SETTINGS \
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
@@ -236,36 +200,6 @@
"protect off 0x20000000 0x2007FFFF;" \
"erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0" \
""
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
- "flashboot=bootm 0x20100000\0" \
- ""
-#endif
-#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
-#ifdef CONFIG_BFIN_MAC
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):eth0:off\0" \
- "ramboot=tftpboot $(loadaddr) linux;" \
- "run ramargs;run addip;bootelf\0" \
- "nfsboot=tftpboot $(loadaddr) linux;" \
- "run nfsargs;run addip;bootelf\0" \
- "flashboot=bootm 0x20100000\0" \
- "update=tftpboot $(loadaddr) u-boot.ldr;" \
- "eeprom write $(loadaddr) 0x0 $(filesize);\0" \
- ""
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
- "flashboot=bootm 0x20100000\0" \
- ""
-#endif
-#endif
#define CFG_PROMPT "bfin> " /* Monitor Command Prompt */
@@ -300,21 +234,18 @@
#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
-#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_UART_BOOT)
-/* for bf537-stamp, usrt boot mode still store env in flash */
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR 0x20004000
-#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
-#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CFG_ENV_IS_IN_EEPROM 1
#define CFG_ENV_OFFSET 0x4000
#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
+#else
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR 0x20004000
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
#endif
#define CFG_ENV_SIZE 0x2000
#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
-/* #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) */
#define ENV_IS_EMBEDDED
-/* #endif */
/* JFFS Partition offset set */
#define CFG_JFFS2_FIRST_BANK 0
@@ -383,6 +314,14 @@
#define CONFIG_TWICLK_KHZ 50
#endif
+#define CONFIG_EBIU_SDRRC_VAL 0x306
+#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
+#define CONFIG_EBIU_SDBCTL_VAL 0x25
+
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
+
#if defined CONFIG_SOFT_I2C
/*
* Software (bit-bang) I2C driver configuration
@@ -428,15 +367,6 @@
#define AMBCTL0VAL 0x7BB07BB0
#define AMBCTL1VAL 0xFFC27BB0
-#define CONFIG_VDSP 1
-
-#ifdef CONFIG_VDSP
-#define ET_EXEC_VDSP 0x8
-#define SHT_STRTAB_VDSP 0x1
-#define ELFSHDRSIZE_VDSP 0x2C
-#define VDSP_ENTRY_ADDR 0xFFA00000
-#endif
-
#if defined(CONFIG_BFIN_IDE)
#define CONFIG_DOS_PARTITION 1
@@ -492,4 +422,6 @@
#endif /*CONFIG_BFIN_IDE */
+#include <asm/blackfin-config-post.h>
+
#endif
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index c29555a..641548d 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -7,9 +7,6 @@
#include <asm/blackfin-config-pre.h>
-#define CONFIG_VDSP 1
-#define CONFIG_BF561 1
-
#define CFG_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_BAUDRATE 57600
@@ -21,30 +18,12 @@
#define CONFIG_PANIC_HANG 1
#define CONFIG_BFIN_CPU bf561-0.3
-
-/*
-* Boot Mode Set
-* Blackfin can support several boot modes
-*/
-#define BF561_BYPASS_BOOT 0x21
-#define BF561_PARA_BOOT 0x22
-#define BF561_SPI_BOOT 0x24
-/* Define the boot mode */
-#define BFIN_BOOT_MODE BF561_BYPASS_BOOT
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/* This sets the default state of the cache on U-Boot's boot */
#define CONFIG_ICACHE_ON
#define CONFIG_DCACHE_ON
-/* Define where the uboot will be loaded by on-chip boot rom */
-#define APP_ENTRY 0x00001000
-
-/*
- * Stringize definitions - needed for environmental settings
- */
-#define STRINGIZE2(x) #x
-#define STRINGIZE(x) STRINGIZE2(x)
-
/*
* Board settings
*/
@@ -242,17 +221,14 @@
/*
* FLASH organization and environment definitions
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_EBIU_SDRRC_VAL 0x306
+#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
+#define CONFIG_EBIU_SDBCTL_VAL 0x15
-#define AMGCTLVAL 0x3F
-#define AMBCTL0VAL 0x7BB07BB0
-#define AMBCTL1VAL 0xFFC27BB0
+#define CONFIG_EBIU_AMGCTL_VAL 0x3F
+#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-#ifdef CONFIG_VDSP
-#define ET_EXEC_VDSP 0x8
-#define SHT_STRTAB_VDSP 0x1
-#define ELFSHDRSIZE_VDSP 0x2C
-#define VDSP_ENTRY_ADDR 0xFFA00000
-#endif
+#include <asm/blackfin-config-post.h>
#endif /* __CONFIG_EZKIT561_H__ */
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index a4bcc65..a1c6674 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -27,16 +27,21 @@
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
-#define CONFIG_CANYONLANDS 1 /* Board is Canyonlands */
+/* This config file is used for Canyonlands (460EX) and Glacier (460GT) */
+#ifndef CONFIG_CANYONLANDS
+#define CONFIG_460GT 1 /* Specific PPC460GT */
+#else
+#define CONFIG_460EX 1 /* Specific PPC460EX */
+#endif
#define CONFIG_440 1
#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_460EX 1 /* Specific PPC460EX support */
#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+#define CONFIG_BOARD_TYPES 1 /* support board types */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
@@ -262,8 +267,15 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
#define CONFIG_PHY1_ADDR 1
-#define CONFIG_HAS_ETH0 1
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+/* Only Glacier (460GT) has 4 EMAC interfaces */
+#ifdef CONFIG_460GT
+#define CONFIG_PHY2_ADDR 2
+#define CONFIG_PHY3_ADDR 3
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#endif
#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
@@ -275,6 +287,8 @@
/*-----------------------------------------------------------------------
* USB-OHCI
*----------------------------------------------------------------------*/
+/* Only Canyonlands (460EX) has USB */
+#ifdef CONFIG_460EX
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
#undef CFG_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors */
@@ -283,6 +297,7 @@
#define CFG_USB_OHCI_REGS_BASE (CFG_AHB_BASE | 0xd0000)
#define CFG_USB_OHCI_SLOT_NAME "ppc440"
#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+#endif
/*-----------------------------------------------------------------------
* Default environment
@@ -293,9 +308,21 @@
#undef CONFIG_BOOTARGS
+/* Setup some board specific values for the default environment variables */
+#ifdef CONFIG_CANYONLANDS
+#define CONFIG_HOSTNAME canyonlands
+#define CFG_BOOTFILE "bootfile=canyonlands/uImage\0"
+#define CFG_DTBFILE "fdt_file=canyonlands/canyonlands.dtb\0"
+#else
+#define CONFIG_HOSTNAME glacier
+#define CFG_BOOTFILE "bootfile=glacier/uImage\0"
+#define CFG_DTBFILE "fdt_file=glacier/glacier.dtb\0"
+#endif
+
#define CONFIG_EXTRA_ENV_SETTINGS \
+ CFG_BOOTFILE \
+ CFG_DTBFILE \
"netdev=eth0\0" \
- "hostname=canyonlands\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
@@ -315,18 +342,16 @@
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"rootpath=/opt/eldk/ppc_4xxFP\0" \
- "bootfile=canyonlands/uImage\0" \
- "fdt_file=canyonlands/canyonlands.dtb\0" \
"fdt_addr=400000\0" \
"kernel_addr=fc000000\0" \
"ramdisk_addr=fc200000\0" \
"initrd_high=30000000\0" \
- "load=tftp 200000 canyonlands/u-boot.bin\0" \
+ "load=tftp 200000 ${hostname}/u-boot.bin\0" \
"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
"cp.b ${fileaddr} fffa0000 ${filesize};" \
"setenv filesize;saveenv\0" \
"upd=run load update\0" \
- "nload=tftp 200000 canyonlands/u-boot-nand.bin\0" \
+ "nload=tftp 200000 ${hostname}/u-boot-nand.bin\0" \
"nupdate=nand erase 0 60000;nand write 200000 0 60000;" \
"setenv filesize;saveenv\0" \
"nupd=run nload nupdate\0" \
@@ -361,8 +386,6 @@
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
@@ -373,7 +396,11 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
+#ifdef CONFIG_460EX
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
#define CONFIG_CMD_USB
+#endif
/* Partitions */
#define CONFIG_MAC_PARTITION
@@ -487,6 +514,8 @@
/*
* PPC4xx GPIO Configuration
*/
+#ifdef CONFIG_460EX
+/* 460EX: Use USB configuration */
#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
{ \
/* GPIO Core 0 */ \
@@ -559,6 +588,81 @@
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
} \
}
+#else
+/* 460GT: Use EMAC2+3 configuration */
+#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
+{ \
+/* GPIO Core 0 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
+}, \
+{ \
+/* GPIO Core 1 */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
+{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
+} \
+}
+#endif
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index 8ecd059..17d3b03 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -52,6 +52,9 @@
#define DV_EVM
#define CFG_NAND_SMALLPAGE
#define CFG_USE_NOR
+#define CFG_USE_INTEL_NOR /* Define this when your DVEVM has Intel
+ * flash instead of AMD flash
+ */
/*===================*/
/* SoC Configuration */
/*===================*/
@@ -60,6 +63,24 @@
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CFG_HZ 1000
+#define CFG_DAVINCI_PINMUX_0 0x00000c1f
+#define CFG_DAVINCI_WAITCFG 0x00000000
+#define CFG_DAVINCI_ACFG2 0x3ffffffd /* CE configs */
+#define CFG_DAVINCI_ACFG3 0x3ffffffd
+#define CFG_DAVINCI_ACFG4 0x3ffffffd
+#define CFG_DAVINCI_ACFG5 0x3ffffffd
+#undef CFG_DAVINCI_NANDCE /* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
+#define CFG_DAVINCI_SDREF 0x000005c3
+#define CFG_DAVINCI_SDCFG 0x00178632 /* 8 banks */
+#define CFG_DAVINCI_SDTIM0 0x28923211
+#define CFG_DAVINCI_SDTIM1 0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0 0x00444400
+/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_DAVINCI_PLL1_PLLM 0x15
+#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
+#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
+#define CFG_DAVINCI_PLL2_DIV2 0x01
/*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
@@ -114,7 +135,7 @@
#ifdef CFG_USE_NAND
#undef CFG_ENV_IS_IN_FLASH
#define CFG_NO_FLASH
-#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
+#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#ifdef CFG_NAND_SMALLPAGE
#define CFG_ENV_SECT_SIZE 512 /* Env sector Size */
#define CFG_ENV_SIZE SZ_16K
@@ -139,24 +160,31 @@
#undef CONFIG_SKIP_RELOCATE_UBOOT
#endif
#define CFG_ENV_IS_IN_FLASH
-#undef CFG_NO_FLASH
+#undef CFG_NO_FLASH
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */
-#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */
-#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*3)
-#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR)
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
-#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
+#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */
+#ifdef CFG_USE_INTEL_NOR
+#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size INTEL Flash */
+#define CFG_FLASH_PROTECTION 1
+#else
+#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */
+#endif
#endif
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
-#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_MISC_INIT_R
-#undef CONFIG_BOOTDELAY
+#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index 96c9a30..cb69535 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -35,6 +35,24 @@
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CFG_HZ 1000
+#define CFG_DAVINCI_PINMUX_0 0x00000c1f
+#define CFG_DAVINCI_WAITCFG 0x00000000
+#define CFG_DAVINCI_ACFG2 0x0432229c /* CE configs */
+#define CFG_DAVINCI_ACFG3 0x3ffffffd
+#define CFG_DAVINCI_ACFG4 0x3ffffffd
+#define CFG_DAVINCI_ACFG5 0x3ffffffd
+#define CFG_DAVINCI_NANDCE 2 /* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
+#define CFG_DAVINCI_SDREF 0x000005c3
+#define CFG_DAVINCI_SDCFG 0x00178622 /* 4 banks */
+#define CFG_DAVINCI_SDTIM0 0x28923211
+#define CFG_DAVINCI_SDTIM1 0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0 0x00444400
+/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_DAVINCI_PLL1_PLLM 0x15
+#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
+#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
+#define CFG_DAVINCI_PLL2_DIV2 0x01
/*=============*/
/* Memory Info */
/*=============*/
@@ -46,7 +64,6 @@
#define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
-#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
/*====================*/
/* Serial Driver info */
/*====================*/
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index de8c4fa..b2c0d7d 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -60,6 +60,24 @@
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CFG_HZ 1000
+#define CFG_DAVINCI_PINMUX_0 0x00000c1f
+#define CFG_DAVINCI_WAITCFG 0x00000000
+#define CFG_DAVINCI_ACFG2 0x3ffffffd /* CE configs */
+#define CFG_DAVINCI_ACFG3 0x3ffffffd
+#define CFG_DAVINCI_ACFG4 0x3ffffffd
+#define CFG_DAVINCI_ACFG5 0x3ffffffd
+#undef CFG_DAVINCI_NANDCE /* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
+#define CFG_DAVINCI_SDREF 0x000005c3
+#define CFG_DAVINCI_SDCFG 0x00178632 /* 8 banks */
+#define CFG_DAVINCI_SDTIM0 0x28923211
+#define CFG_DAVINCI_SDTIM1 0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0 0x00444400
+/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_DAVINCI_PLL1_PLLM 0x15
+#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
+#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
+#define CFG_DAVINCI_PLL2_DIV2 0x01
/*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
new file mode 100644
index 0000000..a6ed77a
--- /dev/null
+++ b/include/configs/imx31_litekit.h
@@ -0,0 +1,167 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Kshitij Gupta <kshitij@ti.com>
+ *
+ * Configuration settings for the 242x TI H4 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
+#define CONFIG_MX31 1 /* in a mx31 */
+#define CONFIG_MX31_HCLK_FREQ 26000000
+#define CONFIG_MX31_CLK32 32000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Temporarily disabled */
+#if 0
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#endif
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE 128 /* num bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MX31_UART 1
+#define CFG_MX31_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.23.168
+#define CONFIG_SERVERIP 192.168.23.2
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
+ "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
+ "ip=dhcp nfsroot=$(serverip):$(nfsrootfs), v3, tcp\0" \
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
+ "tftpboot 0x80000000 uImage-mx31; bootm\0" \
+ "prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; " \
+ "protect off all; erase 0xa00d0000 0xa01effff; " \
+ "cp.b 0x80000000 0xa00d0000 $(filesize)\0"
+
+#define CONFIG_DRIVER_SMC911X 1
+#define CONFIG_DRIVER_SMC911X_BASE 0xb4020000
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "uboot> "
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0 /* memtest works on */
+#define CFG_MEMTEST_END 0x10000
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0 /* default load address */
+
+#define CFG_HZ 32000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_FLASH_BASE 0xa0000000
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+
+#define CFG_ENV_ADDR 0xa01f0000
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SECT_SIZE (64 * 1024)
+#define CFG_ENV_SIZE (64 * 1024)
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
+#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */
+
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
new file mode 100644
index 0000000..647b05b
--- /dev/null
+++ b/include/configs/imx31_phycore.h
@@ -0,0 +1,190 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Kshitij Gupta <kshitij@ti.com>
+ *
+ * Configuration settings for the 242x TI H4 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
+#define CONFIG_MX31 1 /* in a mx31 */
+#define CONFIG_MX31_HCLK_FREQ 26000000
+#define CONFIG_MX31_CLK32 32000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Temporarily disabled */
+#if 0
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#endif
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE 128 /* num bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CFG_I2C_MX31_PORT2 1
+#define CFG_I2C_SPEED 100000
+#define CFG_I2C_SLAVE 0xfe
+
+#define CONFIG_MX31_UART 1
+#define CFG_MX31_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+
+#define CONFIG_BOOTDELAY 3
+
+#define MTDPARTS_DEFAULT \
+ "mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)"
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.23.168
+#define CONFIG_SERVERIP 192.168.23.2
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
+ "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
+ "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
+ "bootargs_flash=setenv bootargs $(bootargs) " \
+ "root=/dev/mtdblock2 rootfstype=jffs2\0" \
+ "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
+ "tftpboot 0x80000000 $(uimage); bootm\0" \
+ "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash; " \
+ "bootm 0x80000000\0" \
+ "unlock=yes\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "prg_uboot=tftpboot 0x80000000 $(uboot); " \
+ "protect off 0xa0000000 +0x20000; " \
+ "erase 0xa0000000 +0x20000; " \
+ "cp.b 0x80000000 0xa0000000 $(filesize)\0" \
+ "prg_kernel=tftpboot 0x80000000 $(uimage); " \
+ "erase 0xa0040000 +0x180000; " \
+ "cp.b 0x80000000 0xa0040000 $(filesize)\0" \
+ "prg_jffs2=tftpboot 0x80000000 $(jffs2); " \
+ "erase 0xa01c0000 0xa1ffffff; " \
+ "cp.b 0x80000000 0xa01c0000 $(filesize)\0"
+
+#define CONFIG_DRIVER_SMC911X 1
+#define CONFIG_DRIVER_SMC911X_BASE 0xa8000000
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "uboot> "
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0 /* memtest works on */
+#define CFG_MEMTEST_END 0x10000
+
+#define CFG_LOAD_ADDR 0 /* default load address */
+
+#define CFG_HZ 32000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_FLASH_BASE 0xa0000000
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 259 /* max number of sectors on one chip */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
+
+#define CFG_ENV_IS_IN_EEPROM 1
+#define CFG_ENV_OFFSET 0x00 /* environment starts here */
+#define CFG_ENV_SIZE 4096
+#define CFG_I2C_EEPROM_ADDR 0x52
+#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of byte address */
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
+#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */
+
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/korat.h b/include/configs/korat.h
index dcec9b0..48d73ac 100644
--- a/include/configs/korat.h
+++ b/include/configs/korat.h
@@ -45,10 +45,10 @@
* Manufacturer's information serial EEPROM parameters
*/
#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */
-#define MAN_SERIAL_NO_FIELD 2
-#define MAN_SERIAL_NO_LENGTH 13
+#define MAN_INFO_FIELD 2
+#define MAN_INFO_LENGTH 9
#define MAN_MAC_ADDR_FIELD 3
-#define MAN_MAC_ADDR_LENGTH 17
+#define MAN_MAC_ADDR_LENGTH 12
/*
* Base addresses -- Note these are effective addresses where the actual
@@ -57,17 +57,18 @@
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
-#define CFG_BOOT_BASE_ADDR 0xf0000000
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
+#define CFG_FLASH0_SIZE 0x01000000
+#define CFG_FLASH0_ADDR (-CFG_FLASH0_SIZE)
+#define CFG_FLASH1_TOP 0xF8000000
+#define CFG_FLASH1_MAX_SIZE 0x08000000
+#define CFG_FLASH1_ADDR (CFG_FLASH1_TOP - CFG_FLASH1_MAX_SIZE)
+#define CFG_FLASH_BASE CFG_FLASH1_ADDR /* start of FLASH */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_OCM_BASE 0xe0010000 /* ocm */
#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
-#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
/* Don't change either of these */
#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
@@ -108,13 +109,14 @@
/*
* FLASH related
*/
-#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_LEGACY /* Allow hard-coded config for FLASH0 */
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH1_ADDR, CFG_FLASH0_ADDR }
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
@@ -126,12 +128,12 @@
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR (CFG_FLASH1_TOP - CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-/* Address and size of Redundant Environment Sector */
-#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
/*
* DDR SDRAM
@@ -144,6 +146,8 @@
#define SPD_EEPROM_ADDRESS {0x50}
#define CONFIG_PROG_SDRAM_TLB
#define CFG_DRAM_TEST
+#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
+ /* 440EPx errata CHIP 11 */
/*
* I2C
@@ -180,6 +184,7 @@
#define CFG_BOOTFILE "bootfile=/tftpboot/korat/uImage\0"
#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
+/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
#define CONFIG_EXTRA_ENV_SETTINGS \
CFG_BOOTFILE \
CFG_ROOTPATH \
@@ -197,8 +202,8 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
- "kernel_addr=FC000000\0" \
- "ramdisk_addr=FC180000\0" \
+ "kernel_addr=F4000000\0" \
+ "ramdisk_addr=F4400000\0" \
"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
"cp.b 200000 FFFA0000 60000\0" \
@@ -216,7 +221,7 @@
#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
#define CONFIG_PHY_DYNAMIC_ANEG 1
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#undef CONFIG_PHY_RESET /* Don't do software PHY reset */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_HAS_ETH0
@@ -322,6 +327,11 @@
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*
+ * Korat-specific options
+ */
+#define CFG_KORAT_MAN_RESET_MS 10000 /* timeout for manufacturer reset */
+
+/*
* PCI stuff
*/
/* General PCI */
@@ -350,12 +360,23 @@
*/
/* Memory Bank 0 (NOR-FLASH) initialization */
+#if CFG_FLASH0_SIZE == 0x01000000
+#define CFG_EBC_PB0AP 0x04017300
+#define CFG_EBC_PB0CR (CFG_FLASH0_ADDR | 0x0009A000)
+#elif CFG_FLASH0_SIZE == 0x04000000
#define CFG_EBC_PB0AP 0x04017300
-#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0x000DA000)
+#define CFG_EBC_PB0CR (CFG_FLASH0_ADDR | 0x000DA000)
+#else
+#error Unable to configure chip select for current CFG_FLASH0_SIZE
+#endif
/* Memory Bank 1 (NOR-FLASH) initialization */
+#if CFG_FLASH1_MAX_SIZE == 0x08000000
#define CFG_EBC_PB1AP 0x04017300
-#define CFG_EBC_PB1CR (0xF8000000 | 0x000DA000)
+#define CFG_EBC_PB1CR (CFG_FLASH1_ADDR | 0x000FA000)
+#else
+#error Unable to configure chip select for current CFG_FLASH1_MAX_SIZE
+#endif
/* Memory Bank 2 (CPLD) initialization */
#define CFG_EBC_PB2AP 0x04017300
@@ -426,6 +447,7 @@
* GPIO63 xxxx x x (reserved for trace port)
*/
+#define CFG_GPIO_ATMEGA_RESET_ 12
#define CFG_GPIO_ATMEGA_SS_ 13
#define CFG_GPIO_PHY0_FIBER_SEL 27
#define CFG_GPIO_PHY1_FIBER_SEL 28
@@ -435,6 +457,7 @@
#define CFG_GPIO_SFP1_TX_EN_ 33
#define CFG_GPIO_PHY0_EN 45
#define CFG_GPIO_PHY1_EN 46
+#define CFG_GPIO_RESET_PRESSED_ 47
/*
* PPC440 GPIO Configuration
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index ced7ba6..4398b87 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
@@ -86,6 +86,8 @@
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
/* unused GPT0 COMP reg */
+#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
+ /* 440EPx errata CHIP 11 */
/* Additional registers for watchdog timer post test */
@@ -149,12 +151,8 @@
#define CFG_MBYTES_SDRAM (256) /* 256MB */
#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
-#if 0 /* test-only: disable ECC for now */
#define CONFIG_DDR_ECC 1 /* enable ECC */
#define CFG_POST_ECC_ON CFG_POST_ECC
-#else
-#define CFG_POST_ECC_ON 0
-#endif
/* POST support */
#define CONFIG_POST (CFG_POST_CACHE | \
diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h
new file mode 100644
index 0000000..0fc0b97
--- /dev/null
+++ b/include/configs/mpr2.h
@@ -0,0 +1,92 @@
+/*
+ * Configuation settings for MPR2
+ *
+ * Copyright (C) 2008
+ * Mark Jonas <mark.jonas@de.bosch.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MPR2_H
+#define __MPR2_H
+
+/* Supported commands */
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_FLASH
+
+/* Default environment variables */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTARGS "console=ttySC0,115200"
+#define CONFIG_BOOTFILE /boot/zImage
+#define CONFIG_LOADADDR 0x8E000000
+#define CONFIG_VERSION_VARIABLE
+
+/* CPU and platform */
+#define CONFIG_SH 1
+#define CONFIG_SH3 1
+#define CONFIG_CPU_SH7720 1
+#define CONFIG_MPR2 1
+
+/* U-Boot internals */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Buffer size for input from the Console */
+#define CFG_PBSIZE 256 /* Buffer size for Console output */
+#define CFG_MAXARGS 16 /* max args accepted for monitor commands */
+#define CFG_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */
+#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024)
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MONITOR_LEN (128 * 1024)
+#define CFG_MALLOC_LEN (256 * 1024)
+#define CFG_GBL_DATA_SIZE 256
+
+/* Memory */
+#define CFG_SDRAM_BASE 0x8C000000
+#define CFG_SDRAM_SIZE (64 * 1024 * 1024)
+#define CFG_MEMTEST_START CFG_SDRAM_BASE
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024))
+
+/* Flash */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_BASE 0xA0000000
+#define CFG_MAX_FLASH_SECT 256
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE (128 * 1024)
+#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_FLASH_ERASE_TOUT 120000
+#define CFG_FLASH_WRITE_TOUT 500
+
+/* Clocks */
+#define CONFIG_SYS_CLK_FREQ 24000000
+#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */
+#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+
+/* UART */
+#define CFG_SCIF_CONSOLE 1
+#define CONFIG_CONS_SCIF0 1
+
+#endif /* __MPR2_H */
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
new file mode 100644
index 0000000..be7f3c6
--- /dev/null
+++ b/include/configs/mx31ads.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration settings for the MX31ADS Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx31-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
+#define CONFIG_MX31 1 /* in a mx31 */
+#define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */
+#define CONFIG_MX31_CLK32 32000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/*
+ * Disabled for now due to build problems under Debian and
+ * a significant increase in the final file size: 144260 vs. 109536 Bytes
+ */
+#if 0
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#endif
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE 128 /* num bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MX31_UART 1
+#define CFG_MX31_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.23.168
+#define CONFIG_SERVERIP 192.168.23.2
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
+ "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
+ "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
+ "tftpboot 0x80000000 uImage-mx31; bootm\0" \
+ "prg_uboot=tftpboot 0x80000000 u-boot-mx31ads.bin; " \
+ "protect off 0xa0000000 0xa001ffff; " \
+ "erase 0xa0000000 0xa001ffff; " \
+ "cp.b 0x80000000 0xa0000000 $(filesize)\0"
+
+#define CONFIG_DRIVER_CS8900 1
+#define CS8900_BASE 0xb4020300
+#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> "
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0 /* memtest works on */
+#define CFG_MEMTEST_END 0x10000
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR CSD0_BASE /* default load address */
+
+#define CFG_HZ 32000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_FLASH_BASE CS0_BASE
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 262 /* max number of sectors on one chip */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
+#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128KiB */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SECT_SIZE (32 * 1024)
+#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+/* S29WS256N NOR flash has 4 32KiB small sectors at beginning and end.
+ * The rest of 32MiB is in 128KiB big sectors.
+ * U-Boot occupies the low 4 sectors,
+ * if we put environment next to it, we will have to occupy 128KiB for it.
+ * Putting it at the top of flash we use only 32KiB. */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 32 * 1024 * 1024 - CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#if 0 /* Doesn't work yet, work in progress */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes(~10x faster)*/
+#endif
+#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
+
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/pmdra.h b/include/configs/pmdra.h
new file mode 100644
index 0000000..e170ee9
--- /dev/null
+++ b/include/configs/pmdra.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2008 Prodrive BV <pieter.voorthijsen@prodrive.nl>
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*=======*/
+/* Board */
+/*=======*/
+#define CFG_PMDRA
+#define CFG_NAND_LARGEPAGE
+/*===================*/
+/* SoC Configuration */
+/*===================*/
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SYS_CLK_FREQ ((CFG_HZ_CLOCK * (CFG_DAVINCI_PLL1_PLLM + 1))/2)
+#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
+#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
+#define CFG_HZ 1000
+#define CFG_DAVINCI_PINMUX_0 0x00000c1f
+#define CFG_DAVINCI_WAITCFG 0x10000000
+#define CFG_DAVINCI_ACFG2 0x00460385 /* NOR CE Config */
+#define CFG_DAVINCI_ACFG3 0x0822218c /* NAND CE Config */
+#define CFG_DAVINCI_ACFG4 0x3ffffffd
+#define CFG_DAVINCI_ACFG5 0x3ffffffd
+#define CFG_DAVINCI_NANDCE 3 /* Use CE3 for NAND */
+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
+#define CFG_DAVINCI_SDREF 0x000005c3
+#define CFG_DAVINCI_SDCFG 0x00178832 /* 8 banks , CAS = 4*/
+#define CFG_DAVINCI_SDTIM0 0x28923211
+#define CFG_DAVINCI_SDTIM1 0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0 0x00444400
+/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_DAVINCI_PLL1_PLLM 0x12
+#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
+#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
+#define CFG_DAVINCI_PLL2_DIV2 0x01
+/*====================================================*/
+/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
+/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
+/*====================================================*/
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_EEPROM_PAGE_WRITE_BITS 6
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+/*=============*/
+/* Memory Info */
+/*=============*/
+#define CFG_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
+#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */
+#define CFG_MEMTEST_START 0x80000000 /* memtest start address */
+#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
+#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */
+#define DDR_8BANKS /* 8-bank DDR2 (256MB) */
+/*====================*/
+/* Serial Driver info */
+/*====================*/
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */
+#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */
+#define CFG_NS16550_COM2 0x01c20800 /* Base address of UART2 */
+#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+/*===================*/
+/* I2C Configuration */
+/*===================*/
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CFG_I2C_SPEED 50000 /* 100Kbps won't work, silicon bug */
+#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+/*==================================*/
+/* Network & Ethernet Configuration */
+/*==================================*/
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#define CFG_USE_NAND
+#define CFG_NAND_BASE 0x04000000
+#undef CFG_NAND_HW_ECC
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#define DEF_BOOTM ""
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR)
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster)*/
+#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
+#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
+#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
+#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
+#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */
+#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size INTEL Flash */
+#define CFG_FLASH_PROTECTION 1
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CFG_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_ENV_OVERWRITE
+/*===================*/
+/* Linux Information */
+/*===================*/
+#define LINUX_BOOT_PARAM_ADDR 0x80000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_BOOTARGS \
+ "mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND "run nand"
+#define CONFIG_EXTRA_ENV_SETTINGS "ethaddr=00:11:22:33:44:55\n"
+/*=================*/
+/* U-Boot commands */
+/*=================*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+/*=======================*/
+/* KGDB support (if any) */
+/*=======================*/
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
new file mode 100644
index 0000000..c20baca
--- /dev/null
+++ b/include/configs/r2dplus.h
@@ -0,0 +1,150 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+#define CONFIG_SH 1
+#define CONFIG_SH4 1
+#define CONFIG_CPU_SH7751 1
+#define CONFIG_CPU_SH_TYPE_R 1
+#define CONFIG_R2DPLUS 1
+#define __LITTLE_ENDIAN__ 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+
+/* SCIF */
+#define CFG_SCIF_CONSOLE 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONS_SCIF1 1
+#define BOARD_LATE_INIT 1
+
+#define CONFIG_BOOTDELAY -1
+#define CONFIG_BOOTARGS "console=ttySC0,115200"
+#define CONFIG_ENV_OVERWRITE 1
+
+/* Network setting */
+#define CONFIG_NETMASK 255.0.0.0
+#define CONFIG_IPADDR 10.0.192.51
+#define CONFIG_SERVERIP 10.0.0.1
+#define CONFIG_GATEWAYIP 10.0.0.1
+
+/* SDRAM */
+#define CFG_SDRAM_BASE (0x8C000000)
+#define CFG_SDRAM_SIZE (0x04000000)
+
+#define CFG_LONGHELP
+#define CFG_PROMPT "=> "
+#define CFG_CBSIZE 256
+#define CFG_PBSIZE 256
+#define CFG_MAXARGS 16
+#define CFG_BARGSIZE 512
+/* List of legal baudrate settings for this board */
+#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
+
+#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
+#define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
+
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024)
+/* Address of u-boot image in Flash */
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
+#define CFG_MONITOR_LEN (128 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CFG_MALLOC_LEN (256 * 1024)
+/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE (256)
+#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
+
+/*
+ * NOR Flash
+ */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+
+#if defined(CONFIG_R2DPLUS_OLD)
+#define CFG_FLASH_BASE (0xA0000000)
+#define CFG_MAX_FLASH_BANKS (1) /* Max number of
+ * Flash memory banks
+ */
+#define CFG_MAX_FLASH_SECT 142
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+
+#else /* CONFIG_R2DPLUS_OLD */
+
+#define CFG_FLASH_BASE (0xA0000000)
+#define CFG_FLASH_CFI_WIDTH 0x04 /* 32bit */
+#define CFG_MAX_FLASH_BANKS (2)
+#define CFG_MAX_FLASH_SECT 270
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
+ CFG_FLASH_BASE + 0x100000,\
+ CFG_FLASH_BASE + 0x400000,\
+ CFG_FLASH_BASE + 0x700000, }
+#endif /* CONFIG_R2DPLUS_OLD */
+
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_FLASH_ERASE_TOUT 120000
+#define CFG_FLASH_WRITE_TOUT 500
+
+/*
+ * SuperH Clock setting
+ */
+#define CONFIG_SYS_CLK_FREQ 60000000
+#define TMU_CLK_DIVIDER 4
+#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CFG_PLL_SETTLING_TIME 100/* in us */
+
+/*
+ * IDE support
+ */
+#define CONFIG_IDE_RESET 1
+#define CFG_PIO_MODE 1
+#define CFG_IDE_MAXBUS 1 /* IDE bus */
+#define CFG_IDE_MAXDEVICE 1
+#define CFG_ATA_BASE_ADDR 0xb4000000
+#define CFG_ATA_STRIDE 2 /* 1bit shift */
+#define CFG_ATA_DATA_OFFSET 0x1000 /* data reg offset */
+#define CFG_ATA_REG_OFFSET 0x1000 /* reg offset */
+#define CFG_ATA_ALT_OFFSET 0x800 /* alternate register offset */
+
+/*
+ * SuperH PCI Bridge Configration
+ */
+#define CONFIG_PCI
+#define CONFIG_SH4_PCI
+#define CONFIG_SH7751_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW 1
+#define __io
+#define __mem_pci
+
+#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
+#define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
+
+/*
+ * Network device (RTL8139) support
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_RTL8139
+#define _IO_BASE 0x00000000
+#define KSEG1ADDR(x) (x)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
new file mode 100644
index 0000000..42787f4
--- /dev/null
+++ b/include/configs/r7780mp.h
@@ -0,0 +1,165 @@
+/*
+ * Configuation settings for the Renesas R7780MP board
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __R7780RP_H
+#define __R7780RP_H
+
+#undef DEBUG
+#define CONFIG_SH 1
+#define CONFIG_SH4A 1
+#define CONFIG_CPU_SH7780 1
+#define CONFIG_R7780MP 1
+#define __LITTLE_ENDIAN 1
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+
+#define CFG_SCIF_CONSOLE 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONS_SCIF0 1
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttySC0,115200"
+#define CONFIG_ENV_OVERWRITE 1
+
+/* check for keypress on bootdelay==0 */
+/*#define CONFIG_ZERO_BOOTDELAY_CHECK*/
+
+/* Network setting */
+#define CONFIG_NETMASK 255.0.0.0
+#define CONFIG_IPADDR 10.0.192.82
+#define CONFIG_SERVERIP 10.0.0.1
+#define CONFIG_GATEWAYIP 10.0.0.1
+
+#define CFG_SDRAM_BASE (0x08000000)
+#define CFG_SDRAM_SIZE (128 * 1024 * 1024)
+
+#define CFG_LONGHELP
+#define CFG_PROMPT "=> "
+#define CFG_CBSIZE 256
+#define CFG_PBSIZE 256
+#define CFG_MAXARGS 16
+#define CFG_BARGSIZE 512
+/* List of legal baudrate settings for this board */
+#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
+
+#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
+#define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
+
+/* NOR Flash (S29PL127J60TFI130) */
+#define CFG_FLASH_BASE (0xA0000000)
+#define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
+#define CFG_MAX_FLASH_BANKS (2)
+#define CFG_MAX_FLASH_SECT 270
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
+ CFG_FLASH_BASE + 0x100000,\
+ CFG_FLASH_BASE + 0x400000,\
+ CFG_FLASH_BASE + 0x700000, }
+
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024)
+/* Address of u-boot image in Flash */
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
+#define CFG_MONITOR_LEN (112 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CFG_MALLOC_LEN (256 * 1024)
+
+/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE (256)
+#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
+#define CFG_RX_ETH_BUFFER (8)
+
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#undef CFG_FLASH_CFI_BROKEN_TABLE
+#undef CFG_FLASH_QUIET_TEST
+/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO
+
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE (16 * 1024)
+#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_FLASH_ERASE_TOUT 120000
+#define CFG_FLASH_WRITE_TOUT 500
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ 33333333
+#define TMU_CLK_DIVIDER 4
+#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+
+/* PCI Controller */
+#if defined(CONFIG_CMD_PCI)
+#define CONFIG_PCI
+#define CONFIG_SH4_PCI
+#define CONFIG_SH7780_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW 1
+#define __io
+#define __mem_pci
+
+#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
+
+#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
+#endif /* CONFIG_CMD_PCI */
+
+#if defined(CONFIG_CMD_NET)
+/* #define CONFIG_NET_MULTI
+ #define CONFIG_RTL8169 */
+/* AX88696L Support(NE2000 base chip) */
+#define CONFIG_DRIVER_NE2000
+#define CONFIG_DRIVER_AX88796L
+#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
+#endif
+
+/* Compact flash Support */
+#if defined(CONFIG_CMD_IDE)
+#define CONFIG_IDE_RESET 1
+#define CFG_PIO_MODE 1
+#define CFG_IDE_MAXBUS 1 /* IDE bus */
+#define CFG_IDE_MAXDEVICE 1
+#define CFG_ATA_BASE_ADDR 0xb4000000
+#define CFG_ATA_STRIDE 2 /* 1bit shift */
+#define CFG_ATA_DATA_OFFSET 0x1000 /* data reg offset */
+#define CFG_ATA_REG_OFFSET 0x1000 /* reg offset */
+#define CFG_ATA_ALT_OFFSET 0x800 /* alternate register offset */
+#endif /* CONFIG_CMD_IDE */
+
+#endif /* __R7780RP_H */
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index dfa8779..555316f 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -221,6 +221,8 @@
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#endif
+#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
+ /* 440EPx errata CHIP 11 */
/*
* I2C
@@ -275,7 +277,7 @@
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \
+ "addmisc=setenv bootargs ${bootargs}\0" \
"flash_nfs=run nfsargs addip addtty addmisc;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty addmisc;" \
diff --git a/include/linux/stat.h b/include/linux/stat.h
index 37f2924..2ce1c25 100644
--- a/include/linux/stat.h
+++ b/include/linux/stat.h
@@ -126,7 +126,7 @@ struct stat {
#endif /* __MIPS__ */
-#if defined(__AVR32__)
+#if defined(__AVR32__) || defined(__SH__)
struct stat {
unsigned long st_dev;
@@ -149,7 +149,7 @@ struct stat {
unsigned long __unused5;
};
-#endif /* __AVR32__ */
+#endif /* __AVR32__ || __SH__ */
#ifdef __cplusplus
}
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 4ee38aa..d2e1e2b 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -48,71 +48,36 @@
/* SPRIDR - System Part and Revision ID Register
*/
-#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */
-#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */
-
-#define SPR_8349E_REV10 0x80300100
-#define SPR_8349_REV10 0x80310100
-#define SPR_8347E_REV10_TBGA 0x80320100
-#define SPR_8347_REV10_TBGA 0x80330100
-#define SPR_8347E_REV10_PBGA 0x80340100
-#define SPR_8347_REV10_PBGA 0x80350100
-#define SPR_8343E_REV10 0x80360100
-#define SPR_8343_REV10 0x80370100
-
-#define SPR_8349E_REV11 0x80300101
-#define SPR_8349_REV11 0x80310101
-#define SPR_8347E_REV11_TBGA 0x80320101
-#define SPR_8347_REV11_TBGA 0x80330101
-#define SPR_8347E_REV11_PBGA 0x80340101
-#define SPR_8347_REV11_PBGA 0x80350101
-#define SPR_8343E_REV11 0x80360101
-#define SPR_8343_REV11 0x80370101
-
-#define SPR_8349E_REV31 0x80300300
-#define SPR_8349_REV31 0x80310300
-#define SPR_8347E_REV31_TBGA 0x80320300
-#define SPR_8347_REV31_TBGA 0x80330300
-#define SPR_8347E_REV31_PBGA 0x80340300
-#define SPR_8347_REV31_PBGA 0x80350300
-#define SPR_8343E_REV31 0x80360300
-#define SPR_8343_REV31 0x80370300
-
-#define SPR_8360E_REV10 0x80480010
-#define SPR_8360_REV10 0x80490010
-#define SPR_8360E_REV11 0x80480011
-#define SPR_8360_REV11 0x80490011
-#define SPR_8360E_REV12 0x80480012
-#define SPR_8360_REV12 0x80490012
-#define SPR_8360E_REV20 0x80480020
-#define SPR_8360_REV20 0x80490020
-#define SPR_8360E_REV21 0x80480021
-#define SPR_8360_REV21 0x80490021
-
-#define SPR_8323E_REV10 0x80620010
-#define SPR_8323_REV10 0x80630010
-#define SPR_8321E_REV10 0x80660010
-#define SPR_8321_REV10 0x80670010
-#define SPR_8323E_REV11 0x80620011
-#define SPR_8323_REV11 0x80630011
-#define SPR_8321E_REV11 0x80660011
-#define SPR_8321_REV11 0x80670011
-
-#define SPR_8313E_REV10 0x80B00010
-#define SPR_8313_REV10 0x80B10010
-#define SPR_8311E_REV10 0x80B20010
-#define SPR_8311_REV10 0x80B30010
-#define SPR_8315E_REV10 0x80B40010
-#define SPR_8315_REV10 0x80B50010
-#define SPR_8314E_REV10 0x80B60010
-#define SPR_8314_REV10 0x80B70010
-
-#define SPR_8379E_REV10 0x80C20010
-#define SPR_8379_REV10 0x80C30010
-#define SPR_8378E_REV10 0x80C40010
-#define SPR_8378_REV10 0x80C50010
-#define SPR_8377E_REV10 0x80C60010
-#define SPR_8377_REV10 0x80C70010
+#define SPRIDR_PARTID 0xFFFF0000 /* Part Id */
+#define SPRIDR_REVID 0x0000FFFF /* Revision Id */
+
+#if defined(CONFIG_MPC834X)
+#define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8)
+#define REVID_MINOR(spridr) (spridr & 0x000000FF)
+#else
+#define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4)
+#define REVID_MINOR(spridr) (spridr & 0x0000000F)
+#endif
+
+#define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16)
+#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) /* has SEC */
+
+#define SPR_8311 0x80B2
+#define SPR_8313 0x80B0
+#define SPR_8314 0x80B6
+#define SPR_8315 0x80B4
+#define SPR_8321 0x8066
+#define SPR_8323 0x8062
+#define SPR_8343 0x8036
+#define SPR_8347_TBGA_ 0x8032
+#define SPR_8347_PBGA_ 0x8034
+#define SPR_8349 0x8030
+#define SPR_8358_TBGA_ 0x804A
+#define SPR_8358_PBGA_ 0x804E
+#define SPR_8360 0x8048
+#define SPR_8377 0x80C6
+#define SPR_8378 0x80C4
+#define SPR_8379 0x80C2
/* SPCR - System Priority Configuration Register
*/
diff --git a/include/pci_ids.h b/include/pci_ids.h
index b0c1957..593c074 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -1810,6 +1810,7 @@
#define PCI_DEVICE_ID_INTEL_82434 0x04a3
#define PCI_DEVICE_ID_INTEL_I960 0x0960
#define PCI_DEVICE_ID_INTEL_I960RM 0x0962
+#define PCI_DEVICE_ID_INTEL_82541ER 0x1078
#define PCI_DEVICE_ID_INTEL_82542 0x1000
#define PCI_DEVICE_ID_INTEL_82543GC_FIBER 0x1001
#define PCI_DEVICE_ID_INTEL_82543GC_COPPER 0x1004
diff --git a/include/ppc440.h b/include/ppc440.h
index 10517cb..642d1de 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -2023,9 +2023,13 @@
#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */
#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */
#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg */
+#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg */
+#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg */
#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
+#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
+#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
#endif /* CONFIG_440GX */
diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
index 0208454..89ff26f 100644
--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@@ -213,6 +213,10 @@ typedef struct emac_4xx_hw_st {
#define RGMII_FER (RGMII_BASE + 0x00)
#define RGMII_SSR (RGMII_BASE + 0x04)
+#if defined(CONFIG_460GT)
+#define RGMII1_BASE_OFFSET 0x100
+#endif
+
/* RGMII Function Enable (FER) Register Bit Definitions */
/* Note: for EMAC 2 and 3 only, 440GX only */
#define RGMII_FER_DIS (0x00)