diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/config.h | 3 | ||||
| -rw-r--r-- | include/asm-ppc/processor.h | 12 | ||||
| -rw-r--r-- | include/configs/MPC8536DS.h | 3 | ||||
| -rw-r--r-- | include/configs/MPC8569MDS.h | 3 | ||||
| -rw-r--r-- | include/configs/MPC8610HPCD.h | 2 | ||||
| -rw-r--r-- | include/configs/P1_P2_RDB.h | 3 | ||||
| -rw-r--r-- | include/configs/P2020DS.h | 62 | ||||
| -rw-r--r-- | include/fdt_support.h | 1 | ||||
| -rw-r--r-- | include/fsl_esdhc.h | 6 |
9 files changed, 37 insertions, 58 deletions
diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index 0d78aa4..fc3facb 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -41,6 +41,7 @@ #endif #if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \ + defined(CONFIG_P1021) || defined(CONFIG_P1022) || \ defined(CONFIG_P2020) || defined(CONFIG_MPC8641) #define CONFIG_MAX_CPUS 2 #elif defined(CONFIG_PPC_P4080) diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 9b3d616..9ec319a 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -265,6 +265,7 @@ #define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ #define HID1_ASTME (1<<13) /* Address bus streaming mode */ #define HID1_ABE (1<<12) /* Address broadcast enable */ +#define HID1_MBDD (1<<6) /* optimized sync instruction */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #ifndef CONFIG_BOOKE #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ @@ -533,6 +534,9 @@ #define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ #define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ #define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */ +#define BUCSR_BBFI 0x00000200 /* Branch buffer flash invalidate */ +#define BUCSR_BPEN 0x00000001 /* Branch prediction enable */ +#define BUCSR_ENABLE (BUCSR_BBFI|BUCSR_BPEN) #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ #define SPRN_PID1 0x279 /* Process ID Register 1 */ @@ -1032,8 +1036,16 @@ #define SVR_8572_E 0x80E800 #define SVR_P1011 0x80E500 #define SVR_P1011_E 0x80ED00 +#define SVR_P1012 0x80E501 +#define SVR_P1012_E 0x80ED01 +#define SVR_P1013 0x80E700 +#define SVR_P1013_E 0x80EF00 #define SVR_P1020 0x80E400 #define SVR_P1020_E 0x80EC00 +#define SVR_P1021 0x80E401 +#define SVR_P1021_E 0x80EC01 +#define SVR_P1022 0x80E600 +#define SVR_P1022_E 0x80EE00 #define SVR_P2010 0x80E300 #define SVR_P2010_E 0x80EB00 #define SVR_P2020 0x80E200 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 87901b3..da4313a 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -413,6 +413,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 9b81703..0c43b2b 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -284,6 +284,9 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index fed441e..8382e3c 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -177,7 +177,7 @@ #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ -#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x0C /* Reset altbank mask*/ +#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 405e6d5..a9b4004 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -286,6 +286,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 30a5a31..66be725 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -238,7 +238,9 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ -#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ +#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ + +#ifdef CONFIG_FSL_NGPIXIS #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ #ifdef CONFIG_PHYS_64BIT #define PIXIS_BASE_PHYS 0xfffdf0000ull @@ -249,59 +251,11 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ -#define PIXIS_ID 0x0 /* Board ID at offset 0 */ -#define PIXIS_VER 0x1 /* Board version at offset 1 */ -#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ -#define PIXIS_CSR 0x3 /* PIXIS General control/status register */ -#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ -#define PIXIS_PWR 0x5 /* PIXIS Power status register */ -#define PIXIS_AUX 0x6 /* Auxiliary 1 register */ -#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ -#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ -#define PIXIS_VCTL 0x10 /* VELA Control Register */ -#define PIXIS_VSTAT 0x11 /* VELA Status Register */ -#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ -#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ -#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ -#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ -#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ -#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ -#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ -#define PIXIS_VSYSCLK0 0x19 /* VELA SYSCLK0 Register */ -#define PIXIS_VSYSCLK1 0x1A /* VELA SYSCLK1 Register */ -#define PIXIS_VSYSCLK2 0x1B /* VELA SYSCLK2 Register */ -#define PIXIS_VDDRCLK0 0x1C /* VELA DDRCLK0 Register */ -#define PIXIS_VDDRCLK1 0x1D /* VELA DDRCLK1 Register */ -#define PIXIS_VDDRCLK2 0x1E /* VELA DDRCLK2 Register */ - -#define PIXIS_VWATCH 0x24 /* Watchdog Register */ -#define PIXIS_LED 0x25 /* LED Register */ - -#define PIXIS_SW(x) 0x20 + (x - 1) * 2 -#define PIXIS_EN(x) 0x21 + (x - 1) * 2 -#define PIXIS_SW7_LBMAP 0xc0 /* SW7 - cfg_lbmap */ -#define PIXIS_SW7_VBANK 0x30 /* SW7 - cfg_vbank */ - -/* old pixis referenced names */ -#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ -#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ -#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 -#define PIXIS_VSPEED2_TSEC1SER 0x8 -#define PIXIS_VSPEED2_TSEC2SER 0x4 -#define PIXIS_VSPEED2_TSEC3SER 0x2 -#define PIXIS_VSPEED2_TSEC4SER 0x1 -#define PIXIS_VCFGEN1_TSEC1SER 0x20 -#define PIXIS_VCFGEN1_TSEC2SER 0x20 -#define PIXIS_VCFGEN1_TSEC3SER 0x20 -#define PIXIS_VCFGEN1_TSEC4SER 0x20 -#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ - | PIXIS_VSPEED2_TSEC2SER \ - | PIXIS_VSPEED2_TSEC3SER \ - | PIXIS_VSPEED2_TSEC4SER) -#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ - | PIXIS_VCFGEN1_TSEC2SER \ - | PIXIS_VCFGEN1_TSEC3SER \ - | PIXIS_VCFGEN1_TSEC4SER) +#define PIXIS_LBMAP_SWITCH 7 +#define PIXIS_LBMAP_MASK 0xf0 +#define PIXIS_LBMAP_SHIFT 4 +#define PIXIS_LBMAP_ALTBANK 0x20 +#endif #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ diff --git a/include/fdt_support.h b/include/fdt_support.h index a3d5f8c..9a453af 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -82,6 +82,7 @@ int fdt_resize(void *blob); int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size); void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size); +void fdt_del_node_and_alias(void *blob, const char *alias); #endif /* ifdef CONFIG_OF_LIBFDT */ #endif /* ifndef __FDT_SUPPORT_H */ diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 01b7dec..f9ae15a 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -2,7 +2,7 @@ * FSL SD/MMC Defines *------------------------------------------------------------------- * - * Copyright 2007-2008, Freescale Semiconductor, Inc + * Copyright 2007-2008,2010 Freescale Semiconductor, Inc * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -39,6 +39,7 @@ #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 +#define SYSCTL_RSTA 0x01000000 #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) @@ -132,6 +133,8 @@ #define WML 0x2e044 #define WML_WRITE 0x00010000 +#define WML_RD_WML_MASK 0xff +#define WML_WR_WML_MASK 0xff0000 #define BLKATTR 0x2e004 #define BLKATTR_CNT(x) ((x & 0xffff) << 16) @@ -148,7 +151,6 @@ struct fsl_esdhc_cfg { u32 esdhc_base; u32 no_snoop; - u32 clk_enable; }; /* Select the correct accessors depending on endianess */ |