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-rw-r--r--include/configs/chromebook_link.h4
-rw-r--r--include/configs/x86-common.h2
-rw-r--r--include/fdtdec.h1
3 files changed, 6 insertions, 1 deletions
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
index 3063bd9..8caeca6 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -18,12 +18,16 @@
#define CONFIG_SYS_CAR_ADDR 0xff7e0000
#define CONFIG_SYS_CAR_SIZE (128 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
+#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000
#define CONFIG_SYS_X86_START16 0xfffff800
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_X86_RESET_VECTOR
#define CONFIG_NR_DRAM_BANKS 8
+#define CONFIG_X86_MRC_START 0xfffa0000
+#define CONFIG_CACHE_MRC_SIZE_KB 512
#define CONFIG_COREBOOT_SERIAL
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index 825e9f7..f16ae32 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -192,7 +192,7 @@
#define CONFIG_SYS_STACK_SIZE (32 * 1024)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x200000
-#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
+#define CONFIG_SYS_MALLOC_F_LEN (2 << 10)
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 3bd60b7..abfd678 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -119,6 +119,7 @@ enum fdt_compat_id {
COMPAT_PARADE_PS8625, /* Parade PS8622 EDP->LVDS bridge */
COMPAT_INTEL_LPC, /* Intel Low Pin Count I/F */
COMPAT_INTEL_MICROCODE, /* Intel microcode update */
+ COMPAT_MEMORY_SPD, /* Memory SPD information */
COMPAT_COUNT,
};