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-rw-r--r--include/api_public.h45
-rw-r--r--include/asm-generic/u-boot.h1
-rw-r--r--include/configs/B4860QDS.h10
-rw-r--r--include/configs/BSC9132QDS.h4
-rw-r--r--include/configs/C29XPCIE.h456
-rw-r--r--include/configs/CANBT.h215
-rw-r--r--include/configs/MPC8313ERDB.h1
-rw-r--r--include/configs/P1022DS.h166
-rw-r--r--include/configs/P2041RDB.h1
-rw-r--r--include/configs/T4240EMU.h170
-rw-r--r--include/configs/T4240QDS.h542
-rw-r--r--include/configs/a3m071.h31
-rw-r--r--include/configs/blackstamp.h4
-rw-r--r--include/configs/calimain.h1
-rw-r--r--include/configs/cam_enc_4xx.h1
-rw-r--r--include/configs/corenet_ds.h1
-rw-r--r--include/configs/da830evm.h1
-rw-r--r--include/configs/da850evm.h1
-rw-r--r--include/configs/dalmore.h3
-rw-r--r--include/configs/davinci_dm365evm.h1
-rw-r--r--include/configs/davinci_dm6467evm.h1
-rw-r--r--include/configs/davinci_dvevm.h1
-rw-r--r--include/configs/davinci_schmoogie.h1
-rw-r--r--include/configs/davinci_sffsdr.h1
-rw-r--r--include/configs/davinci_sonata.h1
-rw-r--r--include/configs/dlvision-10g.h11
-rw-r--r--include/configs/dlvision.h3
-rw-r--r--include/configs/ea20.h1
-rw-r--r--include/configs/enbw_cmc.h1
-rw-r--r--include/configs/exynos5250-dt.h1
-rw-r--r--include/configs/galaxy5200.h7
-rw-r--r--include/configs/hawkboard.h1
-rw-r--r--include/configs/igep0033.h1
-rw-r--r--include/configs/io.h8
-rw-r--r--include/configs/io64.h6
-rw-r--r--include/configs/iocon.h60
-rw-r--r--include/configs/linkstation.h12
-rw-r--r--include/configs/mcx.h1
-rw-r--r--include/configs/microblaze-generic.h2
-rw-r--r--include/configs/neo.h8
-rw-r--r--include/configs/omap5_uevm.h25
-rw-r--r--include/configs/p1_p2_rdb_pc.h51
-rw-r--r--include/configs/p1_twr.h619
-rw-r--r--include/configs/pcm051.h1
-rw-r--r--include/configs/t4qds.h575
-rw-r--r--include/configs/tam3517-common.h1
-rw-r--r--include/configs/tegra-common.h3
-rw-r--r--include/configs/tegra114-common.h3
-rw-r--r--include/configs/tegra20-common.h3
-rw-r--r--include/configs/tegra30-common.h3
-rw-r--r--include/configs/ti814x_evm.h1
-rw-r--r--include/configs/trats.h3
-rw-r--r--include/configs/zynq.h9
-rw-r--r--include/dfu.h4
-rw-r--r--include/e500.h16
-rw-r--r--include/edid.h2
-rw-r--r--include/elf.h22
-rw-r--r--include/fsl_esdhc.h1
-rw-r--r--include/fsl_usb.h64
-rw-r--r--include/gdsys_fpga.h58
-rw-r--r--include/i2c.h2
-rw-r--r--include/miiphy.h29
-rw-r--r--include/mpc86xx.h6
-rw-r--r--include/mtd/cfi_flash.h14
-rw-r--r--include/net.h2
-rw-r--r--include/pci.h7
-rw-r--r--include/serial.h2
-rw-r--r--include/stdio_dev.h3
-rw-r--r--include/usb/mv_udc.h88
-rw-r--r--include/video_font.h9
-rw-r--r--include/video_font_4x6.h2154
-rw-r--r--include/video_font_data.h7
-rw-r--r--include/zynqpl.h5
73 files changed, 4510 insertions, 1065 deletions
diff --git a/include/api_public.h b/include/api_public.h
index 4420c99..f5c89f3 100644
--- a/include/api_public.h
+++ b/include/api_public.h
@@ -3,50 +3,7 @@
*
* Written by: Rafal Jaworowski <raj@semihalf.com>
*
- * This file is dual licensed; you can use it under the terms of
- * either the GPL, or the BSD license, at your option.
- *
- * I. GPL:
- *
- * This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Alternatively,
- *
- * II. BSD license:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause
*/
#ifndef _API_PUBLIC_H_
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index 29e0438..4387201 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -69,7 +69,6 @@ typedef struct bd_info {
unsigned int bi_baudrate; /* Console Baudrate */
#if defined(CONFIG_405) || \
defined(CONFIG_405GP) || \
- defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || \
defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || \
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 0904343..2f0bc6b 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -33,7 +33,6 @@
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
-#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_MP /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
@@ -75,6 +74,13 @@
#define VSC3308_TX_ADDRESS 0x02
#define VSC3308_RX_ADDRESS 0x03
+/* IDT clock synthesizers */
+#define CONFIG_IDT8T49N222A
+#define I2C_CH_IDT 0x9
+
+#define IDT_SERDES1_ADDRESS 0x6E
+#define IDT_SERDES2_ADDRESS 0x6C
+
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
@@ -578,6 +584,8 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_RMAN
+
/* Default address of microcode for the Linux Fman driver */
#if defined(CONFIG_SPIFLASH)
/*
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 1ab6891..03f3a4f 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -224,6 +224,10 @@ combinations. this should be removed later
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
+/* DSP CCSRBAR */
+#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+
/*
* IFC Definitions
*/
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
new file mode 100644
index 0000000..83779ef
--- /dev/null
+++ b/include/configs/C29XPCIE.h
@@ -0,0 +1,456 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * C29XPCIE board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_PHYS_64BIT
+
+#ifdef CONFIG_C29XPCIE
+#define CONFIG_PPC_C29X
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_SYS_TEXT_BASE 0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE /* BOOKE */
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_MPC85xx
+#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
+
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#ifdef CONFIG_PCI
+#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+
+#define CONFIG_E1000
+
+/*
+ * PCI Windows
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME "Slot 1"
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_TSEC_ENET
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_DDR_CLK_FREQ 100000000
+#define CONFIG_SYS_CLK_FREQ 66666666
+
+#define CONFIG_HWCONFIG
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START 0x00200000
+#define CONFIG_SYS_MEMTEST_END 0x00400000
+#define CONFIG_PANIC_HANG
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR3
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS 0x50
+#define CONFIG_SYS_DDR_RAW_TIMING
+
+/* DDR ECC Setup*/
+#define CONFIG_DDR_ECC
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+
+#define CONFIG_SYS_SDRAM_SIZE 512
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+
+#define CONFIG_SYS_CCSRBAR 0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+
+/* Platform SRAM setting */
+#define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
+#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
+ (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
+#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
+
+/*
+ * IFC Definitions
+ */
+/* NOR Flash on IFC */
+#define CONFIG_SYS_FLASH_BASE 0xec000000
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
+
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
+
+/* 16Bit NOR Flash - S29GL512S10TFI01 */
+#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
+#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1e) | \
+ FTIM1_NOR_TRAD_NOR(0x0f) | \
+ FTIM1_NOR_TSEQRAD_NOR(0x0f))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+/* CFI for NOR Flash */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE 0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+/* 8Bit NAND Flash - K9F1G08U0B */
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_NAND \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2k */ \
+ | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
+ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
+ FTIM0_NAND_TWP(0x0c) | \
+ FTIM0_NAND_TWCHT(0x08) | \
+ FTIM0_NAND_TWH(0x06))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
+ FTIM1_NAND_TWBE(0x1d) | \
+ FTIM1_NAND_TRR(0x08) | \
+ FTIM1_NAND_TRP(0x0c))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x18))
+#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
+
+#define CONFIG_SYS_NAND_DDR_LAW 11
+
+/* Set up IFC registers for boot location NOR/NAND */
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+
+/* CPLD on IFC, selected by CS2 */
+#define CONFIG_SYS_CPLD_BASE 0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
+ | CONFIG_SYS_CPLD_BASE)
+
+#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2 0x0
+/* CPLD Timing parameters for IFC CS2 */
+#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+ FTIM0_GPCM_TEADC(0x0e) | \
+ FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+ FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+ FTIM2_GPCM_TCH(0x0) | \
+ FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3 0x0
+
+#if defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
+#define CONFIG_SYS_INIT_RAM_END 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
+ - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+
+/* I2C EEPROM */
+/* enable read and write access to EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+#define CONFIG_CMD_I2C
+
+/* eSPI - Enhanced SPI */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_EON
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+
+#ifdef CONFIG_TSEC_ENET
+#define CONFIG_NET_MULTI
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+
+/* Default mode is RGMII mode */
+#define TSEC1_PHY_ADDR 0
+#define TSEC2_PHY_ADDR 2
+
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#define CONFIG_PHY_GIGE
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_SIZE 0x2000
+#endif
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR 0xfff80000
+#else
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#endif
+
+#define CONFIG_LOADS_ECHO
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+
+#ifdef CONFIG_TSEC_ENET
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "loadaddr=1000000\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=rootfs.ext2.gz.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=name/of/device-tree.dtb\0" \
+ "othbootargs=ramdisk_size=600000\0" \
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs; " \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h
deleted file mode 100644
index 40471b7..0000000
--- a/include/configs/CANBT.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * (C) Copyright 2001
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405CR 1 /* This is a PPC405CR CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-#define CONFIG_CANBT 1 /* ...on a CANBT board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-
-#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw console=ttyS0,115200; " \
- "bootm ffe00000 ffe80000"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#undef CONFIG_PCI_PNP /* no pci plug-and-play */
-
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_EEPROM
-
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#if 0 /* Use FLASH for environment variables */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
-
-#else /* Use EEPROM for environment variables */
-
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
- /* total size of a CAT24WC08 is 1024 bytes */
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC08) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (CAN/USB) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x010053C0 /* enable Ready, BEM=1 */
-#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (Misc-IO/LEDs) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 3 (CAN Features) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x80000040 /* no Ready, BEM=1 */
-#define CONFIG_SYS_EBC_PB3CR 0xF021C000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in RAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00ef0000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x0f00 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 6c6ce58..ddcbfa6 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -24,7 +24,6 @@
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index d1ce9fd..edece1f 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -16,42 +16,105 @@
#endif
#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_PAD_TO 0x18000
+#define CONFIG_SPL_MAX_SIZE (96 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
#endif
#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_PAD_TO 0x18000
+#define CONFIG_SPL_MAX_SIZE (96 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_SPI_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
#endif
#define CONFIG_NAND_FSL_ELBC
#ifdef CONFIG_NAND
#define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE (128 << 10)
+#define CONFIG_SPL_TEXT_BASE 0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-
-#define CONFIG_SYS_TEXT_BASE 0x00201000
-#define CONFIG_SPL_TEXT_BASE 0xfffff000
-#define CONFIG_SPL_MAX_SIZE 4096
-#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
-#define CONFIG_SPL_RELOC_STACK 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
-#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_TEXT_BASE 0xff800000
+#define CONFIG_SPL_MAX_SIZE 4096
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_TPL_PAD_TO 0x20000
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif
/* High Level Configuration Options */
@@ -225,11 +288,11 @@
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#endif
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
+#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
/* NAND flash config */
@@ -292,6 +355,43 @@
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
/*
+ * Config the L2 Cache as L2 SRAM
+*/
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
+
+/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
@@ -299,7 +399,7 @@
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
@@ -521,7 +621,7 @@
/*
* Environment
*/
-#ifdef CONFIG_RAMBOOT_SPIFLASH
+#ifdef CONFIG_SPIFLASH
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
@@ -530,14 +630,20 @@
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
-#elif defined(CONFIG_RAMBOOT_SDCARD)
+#elif defined(CONFIG_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MMC_ENV_DEV 0
#elif defined(CONFIG_NAND)
-#define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (1024 * 1024)
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
#elif defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 9814ca2..905bacf 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -37,7 +37,6 @@
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
-#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_MP /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/T4240EMU.h b/include/configs/T4240EMU.h
new file mode 100644
index 0000000..9fa6b77
--- /dev/null
+++ b/include/configs/T4240EMU.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * T4240 EMU board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_T4240EMU
+#define CONFIG_PHYS_64BIT
+
+#define CONFIG_SYS_NO_FLASH 1
+#define CONFIG_SYS_FSL_DDR_EMU 1
+#define CONFIG_SYS_FSL_NO_QIXIS 1
+#define CONFIG_SYS_FSL_NO_SERDES 1
+
+#include "t4qds.h"
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CACHE_FLUSH
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x2000
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 133333333
+#define CONFIG_FSL_TBCLK_EXTRA_DIV 100
+
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SPD_BUS_NUM 1
+#define SPD_EEPROM_ADDRESS1 0x51
+#define SPD_EEPROM_ADDRESS2 0x52
+#define SPD_EEPROM_ADDRESS3 0x53
+#define SPD_EEPROM_ADDRESS4 0x54
+#define SPD_EEPROM_ADDRESS5 0x55
+#define SPD_EEPROM_ADDRESS6 0x56
+#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000) | \
+ CSPR_PORT_SIZE_32 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(0)
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
+ FTIM0_NOR_TEADC(0x1) | \
+ FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
+ FTIM1_NOR_TRAD_NOR(0x1))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
+ FTIM2_NOR_TCH(0x0) | \
+ FTIM2_NOR_TWP(0x1))
+#define CONFIG_SYS_NOR_FTIM3 0x04000000
+#define CONFIG_SYS_IFC_CCR 0x01000000
+
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+
+
+/* I2C */
+#define CONFIG_SYS_FSL_I2C_SPEED 4000000 /* faster speed for emulator */
+#define CONFIG_SYS_FSL_I2C2_SPEED 4000000
+
+/* Qman/Bman */
+#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS 50
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS 50
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN
+#define CONFIG_SYS_INTERLAKEN
+
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+
+
+#define CONFIG_BOOTDELAY 0
+
+/*
+ * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
+ * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
+ * interleaving. It can be cacheline, page, bank, superbank.
+ * See doc/README.fsl-ddr for details.
+ */
+#ifdef CONFIG_PPC_T4240
+#define CTRL_INTLV_PREFERED 3way_4KB
+#else
+#define CTRL_INTLV_PREFERED cacheline
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:" \
+ "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
+ "bank_intlv=auto;" \
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=t4240emu/ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=t4240emu/t4240emu.dtb\0" \
+ "bdev=sda3\0" \
+ "c=ffe\0"
+
+/*
+ * For emulation this causes u-boot to jump to the start of the proof point
+ * app code automatically
+ */
+#define CONFIG_PROOF_POINTS \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "cpu 1 release 0x29000000 - - -;" \
+ "cpu 2 release 0x29000000 - - -;" \
+ "cpu 3 release 0x29000000 - - -;" \
+ "cpu 4 release 0x29000000 - - -;" \
+ "cpu 5 release 0x29000000 - - -;" \
+ "cpu 6 release 0x29000000 - - -;" \
+ "cpu 7 release 0x29000000 - - -;" \
+ "go 0x29000000"
+
+#define CONFIG_HVBOOT \
+ "setenv bootargs config-addr=0x60000000; " \
+ "bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_LINUX \
+ "errata;" \
+ "setenv othbootargs ignore_loglevel;" \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "setenv ramdiskaddr 0x02000000;" \
+ "setenv fdtaddr 0x00c00000;" \
+ "setenv loadaddr 0x1000000;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 9ac7f69..92a30ab 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -7,6 +7,9 @@
/*
* T4240 QDS board configuration file
*/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
#define CONFIG_T4240QDS
#define CONFIG_PHYS_64BIT
@@ -15,4 +18,543 @@
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
+#endif
+
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#define CONFIG_DDR_ECC
+
#include "t4qds.h"
+
+#ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (512 * 1097)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR 0xffe20000
+#define CONFIG_ENV_SIZE 0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS1 0x51
+#define SPD_EEPROM_ADDRESS2 0x52
+#define SPD_EEPROM_ADDRESS3 0x53
+#define SPD_EEPROM_ADDRESS4 0x54
+#define SPD_EEPROM_ADDRESS5 0x55
+#define SPD_EEPROM_ADDRESS6 0x56
+#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1A) |\
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0x0E) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_FSL_QIXIS /* use common QIXIS code */
+#define QIXIS_BASE 0xffdf0000
+#define QIXIS_LBMAP_SWITCH 6
+#define QIXIS_LBMAP_MASK 0x0f
+#define QIXIS_LBMAP_SHIFT 0
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x04
+#define QIXIS_RST_CTL_RESET 0x83
+#define QIXIS_RST_FORCE_MEM 0x1
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
+
+#define CONFIG_SYS_CSPR3_EXT (0xf)
+#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
+#define CONFIG_SYS_CSOR3 0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+ FTIM0_GPCM_TEADC(0x0e) | \
+ FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+ FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+ FTIM2_GPCM_TCH(0x0) | \
+ FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3 0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE 0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
+ | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x07) | \
+ FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0x0e) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW 11
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+
+/* I2C */
+#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
+#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
+#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
+
+#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+#define I2C_MUX_CH_VSC3316_FS 0xc
+#define I2C_MUX_CH_VSC3316_BS 0xd
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
+/* VSC Crossbar switches */
+#define CONFIG_VSC_CROSSBAR
+#define VSC3316_FSM_TX_ADDR 0x70
+#define VSC3316_FSM_RX_ADDR 0x71
+
+/*
+ * RapidIO
+ */
+
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE 0
+
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS 50
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS 50
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 545KB (1089 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+#define FM1_10GEC1_PHY_ADDR 0x0
+#define FM1_10GEC2_PHY_ADDR 0x1
+#define FM2_10GEC1_PHY_ADDR 0x2
+#define FM2_10GEC2_PHY_ADDR 0x3
+#endif
+
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC1"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+
+#define __USB_PHY_TYPE utmi
+
+/*
+ * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
+ * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
+ * interleaving. It can be cacheline, page, bank, superbank.
+ * See doc/README.fsl-ddr for details.
+ */
+#ifdef CONFIG_PPC_T4240
+#define CTRL_INTLV_PREFERED 3way_4KB
+#else
+#define CTRL_INTLV_PREFERED cacheline
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:" \
+ "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
+ "bank_intlv=auto;" \
+ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot && " \
+ "protect off $ubootaddr +$filesize && " \
+ "erase $ubootaddr +$filesize && " \
+ "cp.b $loadaddr $ubootaddr $filesize && " \
+ "protect on $ubootaddr +$filesize && " \
+ "cmp.b $loadaddr $ubootaddr $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=t4240qds/ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=t4240qds/t4240qds.dtb\0" \
+ "bdev=sda3\0" \
+ "c=ffe\0"
+
+#define CONFIG_HVBOOT \
+ "setenv bootargs config-addr=0x60000000; " \
+ "bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "cpu 1 release 0x01000000 - - -;" \
+ "cpu 2 release 0x01000000 - - -;" \
+ "cpu 3 release 0x01000000 - - -;" \
+ "cpu 4 release 0x01000000 - - -;" \
+ "cpu 5 release 0x01000000 - - -;" \
+ "cpu 6 release 0x01000000 - - -;" \
+ "cpu 7 release 0x01000000 - - -;" \
+ "go 0x01000000"
+
+#define CONFIG_LINUX \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "setenv ramdiskaddr 0x02000000;" \
+ "setenv fdtaddr 0x00c00000;" \
+ "setenv loadaddr 0x1000000;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index b18a3fa..43d3d99 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -31,6 +31,8 @@
#define CONFIG_HOSTNAME a3m071
#endif
+#define CONFIG_BOOTCOUNT_LIMIT
+
/*
* Serial console configuration
*/
@@ -65,7 +67,8 @@
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=fc000000.flash"
#define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \
- "256k(env)," \
+ "128k(env1)," \
+ "128k(env2)," \
"128k(hwinfo)," \
"1M(nvramsim)," \
"128k(dtb)," \
@@ -73,7 +76,9 @@
"128k(sysinfo)," \
"7552k(root)," \
"4M(app)," \
- "13568k(data)"
+ "5376k(data)," \
+ "8M(install)"
+
#define CONFIG_LZO /* needed for UBI */
#define CONFIG_RBTREE /* needed for UBI */
#define CONFIG_CMD_MTDPARTS
@@ -367,7 +372,7 @@
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "mtdargs=setenv bootargs root=/dev/mtdblock7 " \
+ "mtdargs=setenv bootargs root=/dev/mtdblock8 " \
"rootfstype=squashfs,jffs2\0" \
"addhost=setenv bootargs ${bootargs} " \
"hostname=${hostname}\0" \
@@ -376,22 +381,32 @@
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} " \
"console=${consoledev},${baudrate}\0" \
- "flash_nfs=run nfsargs addip addtty addhost;" \
+ "flash_nfs=run nfsargs addip addtty addmtd addhost;" \
"bootm ${kernel_addr} - ${fdt_addr}\0" \
- "flash_mtd=run mtdargs addip addtty addhost;" \
+ "flash_mtd=run mtdargs addip addtty addmtd addhost;" \
"bootm ${kernel_addr} - ${fdt_addr}\0" \
- "flash_self=run ramargs addip addtty addhost;" \
+ "flash_self=run ramargs addip addtty addmtd addhost;" \
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
"tftp ${fdt_addr_r} ${fdtfile};" \
- "run nfsargs addip addtty addhost;" \
+ "run nfsargs addip addtty addmtd addhost;" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
"load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \
"/u-boot-img.bin\0" \
- "update=protect off fc000000 fc07ffff; " \
+ "update=protect off fc000000 fc07ffff;" \
"era fc000000 fc07ffff;" \
"cp.b ${loadaddr} fc000000 ${filesize}\0" \
"upd=run load;run update\0" \
+ "upd_fdt=tftp 1800000 a3m071/a3m071.dtb;" \
+ "run mtdargs addip addtty addmtd addhost;" \
+ "fdt addr 1800000;fdt boardsetup;fdt chosen;" \
+ "erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000" \
+ "upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;" \
+ "erase fc200000 fc6fffff;" \
+ "cp.b 1000000 fc200000 ${filesize}" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_mtd"
diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h
index 7d82275..5b3aac7 100644
--- a/include/configs/blackstamp.h
+++ b/include/configs/blackstamp.h
@@ -206,8 +206,8 @@
#ifdef CONFIG_SYS_I2C_SOFT
#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF9
#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF8
-#define CONFIG_SYS_SOFT_I2C_SPEED 50000
-#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
#endif
/*
diff --git a/include/configs/calimain.h b/include/configs/calimain.h
index c76bc2c..d20074c 100644
--- a/include/configs/calimain.h
+++ b/include/configs/calimain.h
@@ -185,7 +185,6 @@
#ifdef CONFIG_DRIVER_TI_EMAC
#define CONFIG_EMAC_MDIO_PHY_NUM 1
#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h
index 0f3f61a..ac7ed81 100644
--- a/include/configs/cam_enc_4xx.h
+++ b/include/configs/cam_enc_4xx.h
@@ -49,7 +49,6 @@
#define CONFIG_EMAC_MDIO_PHY_NUM 0
#define CONFIG_SYS_EMAC_TI_CLKDIV 0xa9 /* 1MHz */
#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index c0591c5..c3fb80c 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -42,7 +42,6 @@
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
-#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_MP /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h
index 9407eaf..3e71ae5 100644
--- a/include/configs/da830evm.h
+++ b/include/configs/da830evm.h
@@ -74,7 +74,6 @@
*/
#ifdef CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 3c0aacd..e63d7c4 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -227,7 +227,6 @@
*/
#ifdef CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h
index 145e7ac..bdf012b 100644
--- a/include/configs/dalmore.h
+++ b/include/configs/dalmore.h
@@ -21,9 +21,6 @@
#include "tegra114-common.h"
-/* Must be off for Dalmore to boot !?!? FIXME */
-#define CONFIG_SYS_DCACHE_OFF
-
/* Enable fdt support for Dalmore. Flash the image in u-boot-dtb.bin */
#define CONFIG_DEFAULT_DEVICE_TREE tegra114-dalmore
#define CONFIG_OF_CONTROL
diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h
index e3084d3..82dc1a2 100644
--- a/include/configs/davinci_dm365evm.h
+++ b/include/configs/davinci_dm365evm.h
@@ -44,7 +44,6 @@
/* Network Configuration */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h
index 3c430ae..7f57877 100644
--- a/include/configs/davinci_dm6467evm.h
+++ b/include/configs/davinci_dm6467evm.h
@@ -69,7 +69,6 @@ extern unsigned int davinci_arm_clk_get(void);
/* Network & Ethernet Configuration */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index 6526478..a49a989 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -87,7 +87,6 @@
/*==================================*/
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index 29b10dd..1595bc7 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -56,7 +56,6 @@
/*==================================*/
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index 34a64b3..6ebbe81 100644
--- a/include/configs/davinci_sffsdr.h
+++ b/include/configs/davinci_sffsdr.h
@@ -50,7 +50,6 @@
/* Network & Ethernet Configuration */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index d35aea7..3eaa7c0 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -88,7 +88,6 @@
/*==================================*/
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 17391cd..68e5246 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -18,7 +18,7 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME dlvsion-10g
-#define CONFIG_IDENT_STRING " dlvision-10g 0.03"
+#define CONFIG_IDENT_STRING " dlvision-10g 0.05"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F
@@ -123,9 +123,15 @@
#define CONFIG_SYS_FPGA_COUNT 2
+#define CONFIG_SYS_FPGA_PTR { \
+ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
+ (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
#define CONFIG_SYS_LATCH0_RESET 0xffff
#define CONFIG_SYS_LATCH0_BOOT 0xffff
-#define CONFIG_SYS_LATCH1_RESET 0xffcf
+#define CONFIG_SYS_LATCH1_RESET 0xffbf
#define CONFIG_SYS_LATCH1_BOOT 0xffff
#define CONFIG_SYS_FPGA_NO_RFL_HI
@@ -145,7 +151,6 @@
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h
index 2747128..2f8d6b4 100644
--- a/include/configs/dlvision.h
+++ b/include/configs/dlvision.h
@@ -18,7 +18,7 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME dlvision
-#define CONFIG_IDENT_STRING " dlvision 0.01"
+#define CONFIG_IDENT_STRING " dlvision 0.02"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
@@ -109,7 +109,6 @@
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index 14a8db3..e08423a 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -89,7 +89,6 @@
#ifdef CONFIG_DRIVER_TI_EMAC
#define CONFIG_EMAC_MDIO_PHY_NUM 0
#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h
index 43cf6bc..90033fa 100644
--- a/include/configs/enbw_cmc.h
+++ b/include/configs/enbw_cmc.h
@@ -135,7 +135,6 @@
*/
#ifdef CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 2ce5a78..8f8f85f 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -23,7 +23,6 @@
#define CONFIG_DISPLAY_BOARDINFO
/* Enable fdt support for Exynos5250 */
-#define CONFIG_ARCH_DEVICE_TREE exynos5250
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h
index 984f274..47e65d8 100644
--- a/include/configs/galaxy5200.h
+++ b/include/configs/galaxy5200.h
@@ -360,10 +360,9 @@
#define CONFIG_CRC32_VERIFY 1
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME )
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_VERSION_VARIABLE 1
diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h
index 2e478cc..b8197ac 100644
--- a/include/configs/hawkboard.h
+++ b/include/configs/hawkboard.h
@@ -97,7 +97,6 @@
*/
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h
index e08fc14..3e18a65 100644
--- a/include/configs/igep0033.h
+++ b/include/configs/igep0033.h
@@ -174,7 +174,6 @@
/* Ethernet support */
#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/io.h b/include/configs/io.h
index 33743e6..79ada68 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -18,7 +18,7 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME io
-#define CONFIG_IDENT_STRING " io 0.05"
+#define CONFIG_IDENT_STRING " io 0.06"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F
@@ -123,7 +123,6 @@
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
@@ -230,6 +229,11 @@
#define CONFIG_SYS_FPGA_COUNT 1
+#define CONFIG_SYS_FPGA_PTR \
+ { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
/* Memory Bank 3 (Latches) initialization */
#define CONFIG_SYS_LATCH_BASE 0x7f200000
#define CONFIG_SYS_EBC_PB3AP 0xa2015480
diff --git a/include/configs/io64.h b/include/configs/io64.h
index dcd1b82..f110b70 100644
--- a/include/configs/io64.h
+++ b/include/configs/io64.h
@@ -498,6 +498,12 @@
#define CONFIG_SYS_FPGA_COUNT 2
+#define CONFIG_SYS_FPGA_PTR { \
+ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
+ (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
#define CONFIG_SYS_LATCH0_RESET 0xffff
#define CONFIG_SYS_LATCH0_BOOT 0xffff
#define CONFIG_SYS_LATCH1_RESET 0xffbf
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 32d9050..ec9016a 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -18,7 +18,7 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME iocon
-#define CONFIG_IDENT_STRING " iocon 0.04"
+#define CONFIG_IDENT_STRING " iocon 0.05"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F
@@ -63,6 +63,7 @@
* Commands additional to the ones defined in amcc-common.h
*/
#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_FPGAD
#undef CONFIG_CMD_EEPROM
/*
@@ -100,23 +101,53 @@
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
+#define CONFIG_SYS_I2C_SPEED 400000
+
+#define CONFIG_PCA953X /* NXP PCA9554 */
+#define CONFIG_PCA9698 /* NXP PCA9698 */
+
/*
* Software (bit-bang) I2C driver configuration
*/
+#define CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
+#define I2C_SOFT_DECLARATIONS2
+#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
+#define I2C_SOFT_DECLARATIONS3
+#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
+#define I2C_SOFT_DECLARATIONS4
+#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
+
+#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
#ifndef __ASSEMBLY__
-void fpga_gpio_set(int pin);
-void fpga_gpio_clear(int pin);
-int fpga_gpio_get(int pin);
+void fpga_gpio_set(unsigned int bus, int pin);
+void fpga_gpio_clear(unsigned int bus, int pin);
+int fpga_gpio_get(unsigned int bus, int pin);
#endif
#define I2C_ACTIVE { }
#define I2C_TRISTATE { }
-#define I2C_READ fpga_gpio_get(0x0040) ? 1 : 0
-#define I2C_SDA(bit) if (bit) fpga_gpio_set(0x0040); \
- else fpga_gpio_clear(0x0040)
-#define I2C_SCL(bit) if (bit) fpga_gpio_set(0x0020); \
- else fpga_gpio_clear(0x0020)
+#define I2C_READ \
+ (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
+#define I2C_SDA(bit) \
+ do { \
+ if (bit) \
+ fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
+ else \
+ fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
+ } while (0)
+#define I2C_SCL(bit) \
+ do { \
+ if (bit) \
+ fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
+ else \
+ fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
+ } while (0)
#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
/*
@@ -141,7 +172,6 @@ int fpga_gpio_get(int pin);
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
@@ -236,6 +266,11 @@ int fpga_gpio_get(int pin);
#define CONFIG_SYS_FPGA_COUNT 1
+#define CONFIG_SYS_MCLINK_MAX 3
+
+#define CONFIG_SYS_FPGA_PTR \
+ { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
+
/* Memory Bank 3 (Latches) initialization */
#define CONFIG_SYS_LATCH_BASE 0x7f200000
#define CONFIG_SYS_EBC_PB3AP 0x02025080
@@ -251,6 +286,9 @@ int fpga_gpio_get(int pin);
*/
#define CONFIG_SYS_MPC92469AC
#define CONFIG_SYS_CH7301
-#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
+#define CONFIG_SYS_OSD_SCREENS 1
+
+#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
+#define CONFIG_BITBANGMII_MULTI
#endif /* __CONFIG_H */
diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h
index 2ec7761..932dac3 100644
--- a/include/configs/linkstation.h
+++ b/include/configs/linkstation.h
@@ -95,7 +95,17 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_EXT2
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NISDOMAIN
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_TIMEOFFSET
#define CONFIG_OF_LIBFDT 1
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 85ae016..5e27ab2 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -409,7 +409,6 @@
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 87f3d13..0e3de77 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -18,7 +18,7 @@
/* Open Firmware DTS */
#define CONFIG_OF_CONTROL 1
#define CONFIG_OF_EMBED 1
-#define CONFIG_DEFAULT_DEVICE_TREE microblaze
+#define CONFIG_DEFAULT_DEVICE_TREE microblaze-generic
/* linear and spi flash memory */
#ifdef XILINX_FLASH_START
diff --git a/include/configs/neo.h b/include/configs/neo.h
index 5abb8b1..ccbb1fa 100644
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -19,7 +19,7 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME neo
-#define CONFIG_IDENT_STRING " neo 0.01"
+#define CONFIG_IDENT_STRING " neo 0.02"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F
@@ -130,7 +130,6 @@
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
@@ -222,6 +221,11 @@
#define CONFIG_SYS_FPGA_COUNT 1
+#define CONFIG_SYS_FPGA_PTR \
+ { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
/* Memory Bank 3 (Latches) initialization */
#define CONFIG_SYS_LATCH_BASE 0x7f200000
#define CONFIG_SYS_EBC_PB3AP 0x92015480
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index d10c2b5..3c4249b 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -17,6 +17,8 @@
"uuid_disk=${uuid_gpt_disk};" \
"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
+#include <configs/omap5_common.h>
+
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 UART3_BASE
#define CONFIG_BAUDRATE 115200
@@ -40,9 +42,28 @@
#define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4
#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22
+/* USB UHH support options */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80
+#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79
+
+/* Enabled commands */
+#define CONFIG_CMD_DHCP /* DHCP Support */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_NFS /* NFS support */
+
+/* USB Networking options */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+
#define CONSOLEDEV "ttyO2"
#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296
-#include <configs/omap5_common.h>
-
#endif /* __CONFIG_OMAP5_EVM_H */
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 1b0be23..5f0c4fb 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -34,7 +34,7 @@
#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
-#if defined(CONFIG_P1020RDB)
+#if defined(CONFIG_P1020RDB_PC)
#define CONFIG_BOARDNAME "P1020RDB-PC"
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_P1020
@@ -50,6 +50,35 @@
#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
+/*
+ * P1020RDB-PD board has user selectable switches for evaluating different
+ * frequency and boot options for the P1020 device. The table that
+ * follow describe the available options. The front six binary number was in
+ * accordance with SW3[1:6].
+ * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
+ * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
+ * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
+ * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
+ * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
+ * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
+ * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
+ */
+#if defined(CONFIG_P1020RDB_PD)
+#define CONFIG_BOARDNAME "P1020RDB-PD"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_P1020
+#define CONFIG_SPI_FLASH
+#define CONFIG_VSC7385_ENET
+#define CONFIG_SLIC
+#define __SW_BOOT_MASK 0x03
+#define __SW_BOOT_NOR 0x64
+#define __SW_BOOT_SPI 0x34
+#define __SW_BOOT_SD 0x24
+#define __SW_BOOT_NAND 0x44
+#define __SW_BOOT_PCIE 0x74
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#endif
+
#if defined(CONFIG_P1021RDB)
#define CONFIG_BOARDNAME "P1021RDB-PC"
#define CONFIG_NAND_FSL_ELBC
@@ -143,7 +172,6 @@
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
@@ -259,7 +287,7 @@
#define SPD_EEPROM_ADDRESS 0x52
#undef CONFIG_FSL_DDR_INTERACTIVE
-#ifdef CONFIG_P1020MBG
+#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#else
@@ -330,7 +358,7 @@
/*
* Local Bus Definitions
*/
-#if defined(CONFIG_P1020MBG)
+#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
#define CONFIG_SYS_FLASH_BASE 0xec000000
#elif defined(CONFIG_P1020UTM)
@@ -381,13 +409,27 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
+#if defined(CONFIG_P1020RDB_PD)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#else
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
+#endif
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
+#if defined(CONFIG_P1020RDB_PD)
+#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
+ | OR_FCM_PGS /* Large Page*/ \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_1 \
+ | OR_FCM_TRLX \
+ | OR_FCM_EHTR)
+#else
#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
@@ -395,6 +437,7 @@
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
+#endif
#endif /* CONFIG_NAND_FSL_ELBC */
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
new file mode 100644
index 0000000..4aa7064
--- /dev/null
+++ b/include/configs/p1_twr.h
@@ -0,0 +1,619 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * QorIQ P1 Tower boards configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if defined(CONFIG_TWR_P1025)
+#define CONFIG_BOARDNAME "TWR-P1025"
+#define CONFIG_P1025
+#define CONFIG_PHY_ATHEROS
+#define CONFIG_QE
+#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */
+#define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE 0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500
+#define CONFIG_MPC85xx
+
+#define CONFIG_MP
+
+#define CONFIG_FSL_ELBC
+#define CONFIG_PCI
+#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
+#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_CMD_SATA
+#define CONFIG_SATA_SIL3114
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */
+
+#define CONFIG_DDR_CLK_FREQ 66666666
+
+#define CONFIG_HWCONFIG
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE
+#define CONFIG_BTB
+
+#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
+
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x1fffffff
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+#define CONFIG_SYS_CCSRBAR 0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR3
+
+#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+
+#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+
+/* Default settings for DDR3 */
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
+#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
+#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
+#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
+
+#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
+
+#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608
+#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
+#define CONFIG_SYS_DDR_RCW_1 0x00000000
+#define CONFIG_SYS_DDR_RCW_2 0x00000000
+#define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */
+#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
+#define CONFIG_SYS_DDR_TIMING_4 0x00220001
+#define CONFIG_SYS_DDR_TIMING_5 0x03402400
+
+#define CONFIG_SYS_DDR_TIMING_3 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0 0x00220004
+#define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544
+#define CONFIG_SYS_DDR_TIMING_2 0x0fa880de
+#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
+#define CONFIG_SYS_DDR_MODE_1 0x80461320
+#define CONFIG_SYS_DDR_MODE_2 0x00008000
+#define CONFIG_SYS_DDR_INTERVAL 0x09480000
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable
+ * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
+ * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
+ *
+ * Localbus
+ * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable
+ * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable
+ *
+ * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable
+ * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable
+ * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
+#define CONFIG_SYS_FLASH_BASE 0xec000000
+
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
+ | BR_PS_16 | BR_V)
+
+#define CONFIG_FLASH_OR_PRELIM 0xfc0000b1
+
+#define CONFIG_SYS_SSD_BASE 0xe0000000
+#define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE
+#define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
+ BR_PS_16 | BR_V)
+#define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+ OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
+ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
+#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
+
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
+/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+/* Size of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)/* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
+
+#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
+
+/* Serial Port
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+#define CONFIG_SYS_64BIT_STRTOUL
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+
+#define CONFIG_SYS_I2C_PCA9555_ADDR 0x23
+
+/* enable read and write access to EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_HARD_SPI
+#define CONFIG_FSL_ESPI
+
+#if defined(CONFIG_PCI)
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT"
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI
+#endif
+
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#undef CONFIG_TSEC2
+#undef CONFIG_TSEC2_NAME
+#define CONFIG_TSEC3
+#define CONFIG_TSEC3_NAME "eTSEC3"
+
+#define TSEC1_PHY_ADDR 2
+#define TSEC2_PHY_ADDR 0
+#define TSEC3_PHY_ADDR 1
+
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC3_PHYIDX 0
+
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#undef CONFIG_HAS_ETH2
+#endif /* CONFIG_TSEC_ENET */
+
+#ifdef CONFIG_QE
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#endif /* CONFIG_QE */
+
+#ifdef CONFIG_TWR_P1025
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
+
+#undef CONFIG_UEC_ETH
+#define CONFIG_PHY_MODE_NEED_CHANGE
+
+#define CONFIG_UEC_ETH1 /* ETH1 */
+#define CONFIG_HAS_ETH0
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
+#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
+#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
+#endif /* CONFIG_UEC_ETH1 */
+
+#define CONFIG_UEC_ETH5 /* ETH5 */
+#define CONFIG_HAS_ETH1
+
+#ifdef CONFIG_UEC_ETH5
+#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
+#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
+#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
+#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */
+#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
+#endif /* CONFIG_UEC_ETH5 */
+#endif /* CONFIG_TWR-P1025 */
+
+/*
+ * Environment
+ */
+#ifdef CONFIG_SYS_RAMBOOT
+#ifdef CONFIG_RAMBOOT_SDCARD
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#else
+#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE 0x2000
+#endif
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR 0xfff80000
+#else
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#endif
+#endif
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#endif
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
+ || defined(CONFIG_FSL_SATA)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_HOSTNAME unknown
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#define CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+"netdev=eth0\0" \
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+"loadaddr=1000000\0" \
+"bootfile=uImage\0" \
+"dtbfile=twr-p1025twr.dtb\0" \
+"ramdiskfile=rootfs.ext2.gz.uboot\0" \
+"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \
+"tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+"kernelflash=tftpboot $loadaddr $bootfile; " \
+ "protect off 0xefa80000 +$filesize; " \
+ "erase 0xefa80000 +$filesize; " \
+ "cp.b $loadaddr 0xefa80000 $filesize; " \
+ "protect on 0xefa80000 +$filesize; " \
+ "cmp.b $loadaddr 0xefa80000 $filesize\0" \
+"dtbflash=tftpboot $loadaddr $dtbfile; " \
+ "protect off 0xefe80000 +$filesize; " \
+ "erase 0xefe80000 +$filesize; " \
+ "cp.b $loadaddr 0xefe80000 $filesize; " \
+ "protect on 0xefe80000 +$filesize; " \
+ "cmp.b $loadaddr 0xefe80000 $filesize\0" \
+"ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \
+ "protect off 0xeeb80000 +$filesize; " \
+ "erase 0xeeb80000 +$filesize; " \
+ "cp.b $loadaddr 0xeeb80000 $filesize; " \
+ "protect on 0xeeb80000 +$filesize; " \
+ "cmp.b $loadaddr 0xeeb80000 $filesize\0" \
+"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \
+ "protect off 0xefec0000 +$filesize; " \
+ "erase 0xefec0000 +$filesize; " \
+ "cp.b $loadaddr 0xefec0000 $filesize; " \
+ "protect on 0xefec0000 +$filesize; " \
+ "cmp.b $loadaddr 0xefec0000 $filesize\0" \
+"consoledev=ttyS0\0" \
+"ramdiskaddr=2000000\0" \
+"ramdiskfile=rootfs.ext2.gz.uboot\0" \
+"fdtaddr=c00000\0" \
+"bdev=sda1\0" \
+"norbootaddr=ef080000\0" \
+"norfdtaddr=ef040000\0" \
+"ramdisk_size=120000\0" \
+"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
+"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
+
+#define CONFIG_NFSBOOTCOMMAND \
+"setenv bootargs root=/dev/nfs rw " \
+"nfsroot=$serverip:$rootpath " \
+"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+"console=$consoledev,$baudrate $othbootargs;" \
+"tftp $loadaddr $bootfile&&" \
+"tftp $fdtaddr $fdtfile&&" \
+"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_HDBOOT \
+"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
+"console=$consoledev,$baudrate $othbootargs;" \
+"usb start;" \
+"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
+"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
+"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_USB_FAT_BOOT \
+"setenv bootargs root=/dev/ram rw " \
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;" \
+"usb start;" \
+"fatload usb 0:2 $loadaddr $bootfile;" \
+"fatload usb 0:2 $fdtaddr $fdtfile;" \
+"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_USB_EXT2_BOOT \
+"setenv bootargs root=/dev/ram rw " \
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;" \
+"usb start;" \
+"ext2load usb 0:4 $loadaddr $bootfile;" \
+"ext2load usb 0:4 $fdtaddr $fdtfile;" \
+"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_NORBOOT \
+"setenv bootargs root=/dev/mtdblock3 rw " \
+"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
+"bootm $norbootaddr - $norfdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND_TFTP \
+"setenv bootargs root=/dev/ram rw " \
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;" \
+"tftp $ramdiskaddr $ramdiskfile;" \
+"tftp $loadaddr $bootfile;" \
+"tftp $fdtaddr $fdtfile;" \
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+"setenv bootargs root=/dev/ram rw " \
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;" \
+"bootm 0xefa80000 0xeeb80000 0xefe80000"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index d4d4d79..e2b4de7 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -289,7 +289,6 @@
#define CONFIG_CMD_PING
#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 1ed53db..3e82fc2 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -7,24 +7,8 @@
/*
* Corenet DS style board configuration file
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
-#endif
-
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-/* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_NO_FLASH
-#endif
+#ifndef __T4QDS_H
+#define __T4QDS_H
#define CONFIG_CMD_REGINFO
@@ -34,7 +18,6 @@
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
-#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_MP /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
@@ -58,70 +41,16 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
-#ifdef CONFIG_SYS_NO_FLASH
-#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-#else
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#endif
-
-#if defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 10000000
-#define CONFIG_ENV_SPI_MODE 0
-#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
-#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET (512 * 1097)
-#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-#define CONFIG_ENV_IS_IN_REMOTE
-#define CONFIG_ENV_ADDR 0xffe20000
-#define CONFIG_ENV_SIZE 0x2000
-#elif defined(CONFIG_ENV_IS_NOWHERE)
-#define CONFIG_ENV_SIZE 0x2000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
@@ -129,14 +58,9 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_ADDR_MAP
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-#if 0
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
-#endif
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
#define CONFIG_SYS_ALT_MEMTEST
@@ -147,17 +71,8 @@ unsigned long get_board_ddr_clk(void);
*/
#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-#endif
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
/*
* DDR Setup
@@ -174,199 +89,16 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_DDR_SPD
#define CONFIG_FSL_DDR3
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS1 0x51
-#define SPD_EEPROM_ADDRESS2 0x52
-#define SPD_EEPROM_ADDRESS3 0x53
-#define SPD_EEPROM_ADDRESS4 0x54
-#define SPD_EEPROM_ADDRESS5 0x55
-#define SPD_EEPROM_ADDRESS6 0x56
-#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/*
* IFC Definitions
*/
#define CONFIG_SYS_FLASH_BASE 0xe0000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-
-#define CONFIG_FSL_QIXIS /* use common QIXIS code */
-#define QIXIS_BASE 0xffdf0000
-#define QIXIS_LBMAP_SWITCH 6
-#define QIXIS_LBMAP_MASK 0x0f
-#define QIXIS_LBMAP_SHIFT 0
-#define QIXIS_LBMAP_DFLTBANK 0x00
-#define QIXIS_LBMAP_ALTBANK 0x04
-#define QIXIS_RST_CTL_RESET 0x83
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-#ifdef CONFIG_PHYS_64BIT
-#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
-#else
-#define QIXIS_BASE_PHYS QIXIS_BASE
-#endif
-
-#define CONFIG_SYS_CSPR3_EXT (0xf)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
-#define CONFIG_SYS_CSOR3 0x0
-/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
- FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x0) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
-
-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-#if defined(CONFIG_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_MISC_INIT_R
@@ -376,18 +108,12 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
@@ -431,149 +157,55 @@ unsigned long get_board_ddr_clk(void);
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 100000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_SPEED 100000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
-#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
-
-#define I2C_MUX_CH_DEFAULT 0x8
-#define I2C_MUX_CH_VOL_MONITOR 0xa
-#define I2C_MUX_CH_VSC3316_FS 0xc
-#define I2C_MUX_CH_VSC3316_BS 0xd
-
-/* Voltage monitor on channel 2*/
-#define I2C_VOL_MONITOR_ADDR 0x40
-#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
-#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
-#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
-
-/* VSC Crossbar switches */
-#define CONFIG_VSC_CROSSBAR
-#define VSC3316_FSM_TX_ADDR 0x70
-#define VSC3316_FSM_RX_ADDR 0x71
-
/*
* RapidIO
*/
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
-#endif
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
-#else
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
-#endif
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/*
- * for slave u-boot IMAGE instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
-/*
- * for slave UCODE and ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
-
-/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
-
-/*
- * SRIO_PCIE_BOOT - SLAVE
- */
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
-#endif
-/*
- * eSPI - Enhanced SPI
- */
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_CMD_SF
-#define CONFIG_SF_DEFAULT_SPEED 10000000
-#define CONFIG_SF_DEFAULT_MODE 0
-
-/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
-#endif
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#endif
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
-#endif
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
-#endif
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
-#endif
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 4, Base address 203000 */
@@ -584,84 +216,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS 50
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#else
-#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_NUM_PORTALS 50
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#else
-#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_PMAN
-#define CONFIG_SYS_DPAA_DCE
-#define CONFIG_SYS_INTERLAKEN
-
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 545KB (1089 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
- */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
-#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
-#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_TERANETICS
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-#define FM1_10GEC1_PHY_ADDR 0x0
-#define FM1_10GEC2_PHY_ADDR 0x1
-#define FM2_10GEC1_PHY_ADDR 0x2
-#define FM2_10GEC2_PHY_ADDR 0x3
-#endif
-
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_NET_MULTI
@@ -724,30 +278,6 @@ unsigned long get_board_ddr_clk(void);
#endif
/*
-* USB
-*/
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_CMD_EXT2
-#define CONFIG_HAS_FSL_DR_USB
-
-#define CONFIG_MMC
-
-#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
@@ -788,112 +318,11 @@ unsigned long get_board_ddr_clk(void);
/* default location for tftp and bootm */
#define CONFIG_LOADADDR 1000000
-#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
-#define __USB_PHY_TYPE utmi
-
-/*
- * T4240 has 3 DDR controllers. Default to 3way_4KB interleaving. It can be
- * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to
- * cacheline interleaving. It can be cacheline, page, bank, superbank.
- * See doc/README.fsl-ddr for details.
- */
-#ifdef CONFIG_PPC_T4240
-#define CTRL_INTLV_PREFERED 3way_4KB
-#else
-#define CTRL_INTLV_PREFERED cacheline
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:" \
- "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
- "bank_intlv=auto;" \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=t4240qds/ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=t4240qds/t4240qds.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
-
-/* For emulation this causes u-boot to jump to the start of the proof point
- app code automatically */
-#define CONFIG_PROOF_POINTS \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "cpu 1 release 0x29000000 - - -;" \
- "cpu 2 release 0x29000000 - - -;" \
- "cpu 3 release 0x29000000 - - -;" \
- "cpu 4 release 0x29000000 - - -;" \
- "cpu 5 release 0x29000000 - - -;" \
- "cpu 6 release 0x29000000 - - -;" \
- "cpu 7 release 0x29000000 - - -;" \
- "go 0x29000000"
-
#define CONFIG_HVBOOT \
"setenv bootargs config-addr=0x60000000; " \
"bootm 0x01000000 - 0x00f00000"
-#define CONFIG_ALU \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "cpu 1 release 0x01000000 - - -;" \
- "cpu 2 release 0x01000000 - - -;" \
- "cpu 3 release 0x01000000 - - -;" \
- "cpu 4 release 0x01000000 - - -;" \
- "cpu 5 release 0x01000000 - - -;" \
- "cpu 6 release 0x01000000 - - -;" \
- "cpu 7 release 0x01000000 - - -;" \
- "go 0x01000000"
-
-#define CONFIG_LINUX \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-
-#ifdef CONFIG_SECURE_BOOT
-#include <asm/fsl_secure_boot.h>
-#endif
-
#endif /* __CONFIG_H */
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index c215f0b..60dd8ff 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -215,7 +215,6 @@
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_MII
#define CONFIG_EMAC_MDIO_PHY_NUM 0
-#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index ccd68a1..ba6c6bb 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -17,8 +17,6 @@
#define CONFIG_TEGRA /* which is a Tegra generic machine */
#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#include <asm/arch/tegra.h> /* get chip and board defs */
/*
@@ -135,6 +133,7 @@
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_ENTERRCM
#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
/* Defines for SPL */
#define CONFIG_SPL
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index 44e98e5..c3de9a9 100644
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -18,6 +18,9 @@
#define _TEGRA114_COMMON_H_
#include "tegra-common.h"
+/* Cortex-A15 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
/*
* NS16550 Configuration
*/
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index d5e9ee4..b009a31 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -9,6 +9,9 @@
#define _TEGRA20_COMMON_H_
#include "tegra-common.h"
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
/*
* Errata configuration
*/
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index 5ac8816..99acbfd 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -9,6 +9,9 @@
#define _TEGRA30_COMMON_H_
#include "tegra-common.h"
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
/*
* Errata configuration
*/
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index dfc4c75..2fc2c10 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -226,7 +226,6 @@
#define CONFIG_CMD_MII
#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 9b6aac9..24ea06b 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -263,6 +263,9 @@
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
+#define I2C_SOFT_DECLARATIONS2
+#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_I2C_MULTI_BUS
diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index 79fa5bb..b9f381f 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -72,6 +72,15 @@
# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
#endif
+#define CONFIG_ZYNQ_SPI
+
+/* SPI */
+#ifdef CONFIG_ZYNQ_SPI
+# define CONFIG_SPI_FLASH
+# define CONFIG_SPI_FLASH_SST
+# define CONFIG_CMD_SF
+#endif
+
/* Enable the PL to be downloaded */
#define CONFIG_FPGA
#define CONFIG_FPGA_XILINX
diff --git a/include/dfu.h b/include/dfu.h
index 6c7d227..47b9055 100644
--- a/include/dfu.h
+++ b/include/dfu.h
@@ -47,6 +47,8 @@ struct nand_internal_data {
unsigned int dev;
unsigned int part;
+ /* for nand/ubi use */
+ unsigned int ubi;
};
static inline unsigned int get_mmc_blk_size(int dev)
@@ -109,6 +111,8 @@ const char *dfu_get_dev_type(enum dfu_device_type t);
const char *dfu_get_layout(enum dfu_layout l);
struct dfu_entity *dfu_get_entity(int alt);
char *dfu_extract_token(char** e, int *n);
+void dfu_trigger_reset(void);
+bool dfu_reset(void);
int dfu_read(struct dfu_entity *de, void *buf, int size, int blk_seq_num);
int dfu_write(struct dfu_entity *de, void *buf, int size, int blk_seq_num);
diff --git a/include/e500.h b/include/e500.h
index 0ff8e89..0c24326 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -10,19 +10,19 @@
typedef struct
{
- unsigned long freqProcessor[CONFIG_MAX_CPUS];
- unsigned long freqSystemBus;
- unsigned long freqDDRBus;
- unsigned long freqLocalBus;
- unsigned long freqQE;
+ unsigned long freq_processor[CONFIG_MAX_CPUS];
+ unsigned long freq_systembus;
+ unsigned long freq_ddrbus;
+ unsigned long freq_localbus;
+ unsigned long freq_qe;
#ifdef CONFIG_SYS_DPAA_FMAN
- unsigned long freqFMan[CONFIG_SYS_NUM_FMAN];
+ unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
#endif
#ifdef CONFIG_SYS_DPAA_QBMAN
- unsigned long freqQMAN;
+ unsigned long freq_qman;
#endif
#ifdef CONFIG_SYS_DPAA_PME
- unsigned long freqPME;
+ unsigned long freq_pme;
#endif
} MPC85xx_SYS_INFO;
diff --git a/include/edid.h b/include/edid.h
index f153091..480a773 100644
--- a/include/edid.h
+++ b/include/edid.h
@@ -54,7 +54,7 @@ struct edid_detailed_timing {
(_x).vertical_blanking)
unsigned char hsync_offset;
unsigned char hsync_pulse_width;
- unsigned char sync_offset_pulse_width;
+ unsigned char vsync_offset_pulse_width;
unsigned char hsync_vsync_offset_pulse_width_hi;
#define EDID_DETAILED_TIMING_HSYNC_OFFSET(_x) \
((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 7, 6) << 8) + \
diff --git a/include/elf.h b/include/elf.h
index 29f276d..b8ecc41 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -2,27 +2,7 @@
* Copyright (c) 1995, 1996, 2001, 2002
* Erik Theisen. All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
*/
/*
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 2c97398..89bcbd1 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -182,5 +182,6 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd);
static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
#endif /* CONFIG_FSL_ESDHC */
+void __noreturn mmc_boot(void);
#endif /* __FSL_ESDHC_H__ */
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
new file mode 100644
index 0000000..915774c
--- /dev/null
+++ b/include/fsl_usb.h
@@ -0,0 +1,64 @@
+/*
+ * Freescale USB Controller
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_FSL_USB_H_
+#define _ASM_FSL_USB_H_
+
+#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+struct ccsr_usb_port_ctrl {
+ u32 ctrl;
+ u32 drvvbuscfg;
+ u32 pwrfltcfg;
+ u32 sts;
+ u8 res_14[0xc];
+ u32 bistcfg;
+ u32 biststs;
+ u32 abistcfg;
+ u32 abiststs;
+ u8 res_30[0x10];
+ u32 xcvrprg;
+ u32 anaprg;
+ u32 anadrv;
+ u32 anasts;
+};
+
+struct ccsr_usb_phy {
+ u32 id;
+ struct ccsr_usb_port_ctrl port1;
+ u8 res_50[0xc];
+ u32 tvr;
+ u32 pllprg[4];
+ u8 res_70[0x4];
+ u32 anaccfg;
+ u32 dbg;
+ u8 res_7c[0x4];
+ struct ccsr_usb_port_ctrl port2;
+ u8 res_dc[0x334];
+};
+
+#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
+#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
+#define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
+#else
+struct ccsr_usb_phy {
+ u8 res0[0x18];
+ u32 usb_enable_override;
+ u8 res[0xe4];
+};
+#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
+#endif
+
+#endif /*_ASM_FSL_USB_H_ */
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index 0a8268c..f50e0e2 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -19,6 +19,23 @@ enum {
int get_fpga_state(unsigned dev);
void print_fpga_state(unsigned dev);
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
+
+extern struct ihs_fpga *fpga_ptr[];
+
+#define FPGA_SET_REG(ix, fld, val) \
+ fpga_set_reg((ix), \
+ &fpga_ptr[ix]->fld, \
+ offsetof(struct ihs_fpga, fld), \
+ val)
+
+#define FPGA_GET_REG(ix, fld, val) \
+ fpga_get_reg((ix), \
+ &fpga_ptr[ix]->fld, \
+ offsetof(struct ihs_fpga, fld), \
+ val)
+
struct ihs_gpio {
u16 read;
u16 clear;
@@ -67,6 +84,19 @@ struct ihs_fpga {
#endif
#ifdef CONFIG_IO64
+
+struct ihs_fpga_channel {
+ u16 status_int;
+ u16 config_int;
+ u16 switch_connect_config;
+ u16 tx_destination;
+};
+
+struct ihs_fpga_hicb {
+ u16 status_int;
+ u16 config_int;
+};
+
struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
u16 versions; /* 0x0002 */
@@ -75,12 +105,9 @@ struct ihs_fpga {
u16 reserved_0[5]; /* 0x0008 */
u16 quad_serdes_reset; /* 0x0012 */
u16 reserved_1[502]; /* 0x0014 */
- u16 ch0_status_int; /* 0x0400 */
- u16 ch0_config_int; /* 0x0402 */
- u16 reserved_2[126]; /* 0x0404 */
- u16 ch0_hicb_status_int;/* 0x0500 */
- u16 ch0_hicb_config_int;/* 0x0502 */
- u16 reserved_3[7549]; /* 0x0504 */
+ struct ihs_fpga_channel ch[32]; /* 0x0400 */
+ struct ihs_fpga_channel hicb_ch[32]; /* 0x0500 */
+ u16 reserved_2[7487]; /* 0x0580 */
u16 reflection_high; /* 0x3ffe */
};
#endif
@@ -96,11 +123,22 @@ struct ihs_fpga {
u16 mpc3w_control; /* 0x001a */
u16 reserved_1[19]; /* 0x001c */
u16 videocontrol; /* 0x0042 */
- u16 reserved_2[93]; /* 0x0044 */
+ u16 reserved_2[14]; /* 0x0044 */
+ u16 mc_int; /* 0x0060 */
+ u16 mc_int_en; /* 0x0062 */
+ u16 mc_status; /* 0x0064 */
+ u16 mc_control; /* 0x0066 */
+ u16 mc_tx_data; /* 0x0068 */
+ u16 mc_tx_address; /* 0x006a */
+ u16 mc_tx_cmd; /* 0x006c */
+ u16 mc_res; /* 0x006e */
+ u16 mc_rx_cmd_status; /* 0x0070 */
+ u16 mc_rx_data; /* 0x0072 */
+ u16 reserved_3[69]; /* 0x0074 */
u16 reflection_high; /* 0x00fe */
struct ihs_osd osd; /* 0x0100 */
- u16 reserved_3[889]; /* 0x010e */
- u16 videomem; /* 0x0800 */
+ u16 reserved_4[889]; /* 0x010e */
+ u16 videomem[31736]; /* 0x0800 */
};
#endif
@@ -121,7 +159,7 @@ struct ihs_fpga {
u16 reserved_4[176]; /* 0x00a0 */
struct ihs_osd osd; /* 0x0200 */
u16 reserved_5[761]; /* 0x020e */
- u16 videomem; /* 0x0800 */
+ u16 videomem[31736]; /* 0x0800 */
};
#endif
diff --git a/include/i2c.h b/include/i2c.h
index d8674ef..8fd17d1 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -390,7 +390,7 @@ unsigned int i2c_get_bus_speed(void);
# if !defined(CONFIG_SYS_MAX_I2C_BUS)
# define CONFIG_SYS_MAX_I2C_BUS 2
# endif
-# define I2C_MULTI_BUS 0
+# define I2C_MULTI_BUS 1
#else
# define CONFIG_SYS_MAX_I2C_BUS 1
# define I2C_MULTI_BUS 0
diff --git a/include/miiphy.h b/include/miiphy.h
index ca5040e..657b496 100644
--- a/include/miiphy.h
+++ b/include/miiphy.h
@@ -1,27 +1,8 @@
-/*----------------------------------------------------------------------------+
-| This source code is dual-licensed. You may use it under the terms of the
-| GNU General Public License version 2, or under the license below.
-|
-| This source code has been made available to you by IBM on an AS-IS
-| basis. Anyone receiving this source is licensed under IBM
-| copyrights to use it in any way he or she deems fit, including
-| copying it, modifying it, compiling it, and redistributing it either
-| with or without modifications. No license under IBM patents or
-| patent applications is to be implied by the copyright license.
-|
-| Any user of this software should understand that IBM cannot provide
-| technical support for this software and will not be responsible for
-| any consequences resulting from the use of this software.
-|
-| Any person who transfers this source code or any derivative work
-| must include the IBM copyright notice, this paragraph, and the
-| preceding two paragraphs in the transferred software.
-|
-| COPYRIGHT I B M CORPORATION 1999
-| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
-|
-| Additions (C) Copyright 2009 Industrie Dial Face S.p.A.
-+----------------------------------------------------------------------------*/
+/*
+ * SPDX-License-Identifier: GPL-2.0 ibm-pibs
+ *
+ * Additions (C) Copyright 2009 Industrie Dial Face S.p.A.
+ */
/*----------------------------------------------------------------------------+
|
| File Name: miiphy.h
diff --git a/include/mpc86xx.h b/include/mpc86xx.h
index 31e83f2..9fe4748 100644
--- a/include/mpc86xx.h
+++ b/include/mpc86xx.h
@@ -41,9 +41,9 @@
#ifndef __ASSEMBLY__
typedef struct {
- unsigned long freqProcessor;
- unsigned long freqSystemBus;
- unsigned long freqLocalBus;
+ unsigned long freq_processor;
+ unsigned long freq_systembus;
+ unsigned long freq_localbus;
} MPC86xx_SYS_INFO;
#define l1icache_enable icache_enable
diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h
index 5198ecd..048b477 100644
--- a/include/mtd/cfi_flash.h
+++ b/include/mtd/cfi_flash.h
@@ -167,5 +167,19 @@ extern int cfi_flash_num_flash_banks;
void flash_write_cmd(flash_info_t * info, flash_sect_t sect,
uint offset, u32 cmd);
+phys_addr_t cfi_flash_bank_addr(int i);
+unsigned long cfi_flash_bank_size(int i);
+void flash_cmd_reset(flash_info_t *info);
+
+#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+void flash_write8(u8 value, void *addr);
+void flash_write16(u16 value, void *addr);
+void flash_write32(u32 value, void *addr);
+void flash_write64(u64 value, void *addr);
+u8 flash_read8(void *addr);
+u16 flash_read16(void *addr);
+u32 flash_read32(void *addr);
+u64 flash_read64(void *addr);
+#endif
#endif /* __CFI_FLASH_H__ */
diff --git a/include/net.h b/include/net.h
index 7673470..5aedc17 100644
--- a/include/net.h
+++ b/include/net.h
@@ -357,7 +357,7 @@ struct icmp_hdr {
} echo;
ulong gateway;
struct {
- ushort __unused;
+ ushort unused;
ushort mtu;
} frag;
uchar data[0];
diff --git a/include/pci.h b/include/pci.h
index 01002a4..911ba89 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -410,13 +410,6 @@
#define PCI_MAX_PCI_DEVICES 32
#define PCI_MAX_PCI_FUNCTIONS 8
-#define PCI_DCR 0x54 /* PCIe Device Control Register */
-#define PCI_DSR 0x56 /* PCIe Device Status Register */
-#define PCI_LSR 0x5e /* PCIe Link Status Register */
-#define PCI_LCR 0x5c /* PCIe Link Control Register */
-#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
-#define PCI_LTSSM_L0 0x16 /* L0 state */
-
/* Include the ID list */
#include <pci_ids.h>
diff --git a/include/serial.h b/include/serial.h
index f6bb2b9..d232d47 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -26,7 +26,7 @@ extern struct serial_device serial_smc_device;
extern struct serial_device serial_scc_device;
extern struct serial_device *default_serial_console(void);
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+#if defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || defined(CONFIG_440) || \
defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
diff --git a/include/stdio_dev.h b/include/stdio_dev.h
index d0b5593..e6dc12a 100644
--- a/include/stdio_dev.h
+++ b/include/stdio_dev.h
@@ -83,9 +83,6 @@ struct list_head* stdio_get_list(void);
struct stdio_dev* stdio_get_by_name(const char* name);
struct stdio_dev* stdio_clone(struct stdio_dev *dev);
-#ifdef CONFIG_ARM_DCC
-int drv_arm_dcc_init(void);
-#endif
#ifdef CONFIG_LCD
int drv_lcd_init (void);
#endif
diff --git a/include/usb/mv_udc.h b/include/usb/mv_udc.h
index c7696e6..c71516c 100644
--- a/include/usb/mv_udc.h
+++ b/include/usb/mv_udc.h
@@ -14,39 +14,19 @@
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
-/* Endpoint 0 states */
-#define EP0_IDLE 0
-#define EP0_IN_DATA 1
-#define EP0_OUT_DATA 2
-#define EP0_XFER_COMPLETE 3
+#include "../../drivers/usb/host/ehci.h"
+#define NUM_ENDPOINTS 6
/* Endpoint parameters */
#define MAX_ENDPOINTS 4
-#define EP_MAX_PACKET_SIZE 0x200
+#define EP_MAX_PACKET_SIZE 0x200
#define EP0_MAX_PACKET_SIZE 64
-#define UDC_OUT_ENDPOINT 0x02
-#define UDC_OUT_PACKET_SIZE EP_MAX_PACKET_SIZE
-#define UDC_IN_ENDPOINT 0x01
-#define UDC_IN_PACKET_SIZE EP_MAX_PACKET_SIZE
-#define UDC_INT_ENDPOINT 0x05
-#define UDC_INT_PACKET_SIZE EP_MAX_PACKET_SIZE
-#define UDC_BULK_PACKET_SIZE EP_MAX_PACKET_SIZE
-
-#define NUM_ENDPOINTS 6
-#define REQ_COUNT 12
-struct mv_ep {
- struct usb_ep ep;
- struct usb_request req;
- struct list_head queue;
- const struct usb_endpoint_descriptor *desc;
-};
struct mv_udc {
- u32 pad0[80];
#define MICRO_8FRAME 0x8
-#define USBCMD_ITC(x) (((x > 0xff) ? 0xff : x) << 16)
+#define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16)
#define USBCMD_FS2 (1 << 15)
#define USBCMD_RST (1 << 1)
#define USBCMD_RUN (1)
@@ -62,37 +42,52 @@ struct mv_udc {
u32 epinitaddr; /* 0x158 */
u32 pad2[10];
#define PTS_ENABLE 2
-#define PTS(x) ((x & 0x3) << 30)
+#define PTS(x) (((x) & 0x3) << 30)
#define PFSC (1 << 24)
u32 portsc; /* 0x184 */
u32 pad3[8];
#define USBMODE_DEVICE 2
u32 usbmode; /* 0x1a8 */
u32 epstat; /* 0x1ac */
-#define EPT_TX(x) (1 << ((x & 0xffff) + 16))
-#define EPT_RX(x) (1 << (x & 0xffff))
+#define EPT_TX(x) (1 << (((x) & 0xffff) + 16))
+#define EPT_RX(x) (1 << ((x) & 0xffff))
u32 epprime; /* 0x1b0 */
u32 epflush; /* 0x1b4 */
u32 pad4;
u32 epcomp; /* 0x1bc */
-#define CTRL_TXE (1 << 23)
-#define CTRL_TXR (1 << 22)
-#define CTRL_RXE (1 << 7)
-#define CTRL_RXR (1 << 6)
-#define CTRL_TXT_BULK (2 << 18)
-#define CTRL_RXT_BULK (2 << 2)
+#define CTRL_TXE (1 << 23)
+#define CTRL_TXR (1 << 22)
+#define CTRL_RXE (1 << 7)
+#define CTRL_RXR (1 << 6)
+#define CTRL_TXT_BULK (2 << 18)
+#define CTRL_RXT_BULK (2 << 2)
u32 epctrl[16]; /* 0x1c0 */
};
+struct mv_ep {
+ struct usb_ep ep;
+ struct list_head queue;
+ const struct usb_endpoint_descriptor *desc;
+
+ struct usb_request req;
+ uint8_t *b_buf;
+ uint32_t b_len;
+ uint8_t b_fast[64] __aligned(ARCH_DMA_MINALIGN);
+};
+
struct mv_drv {
struct usb_gadget gadget;
- struct usb_gadget_driver *driver;
- struct mv_udc *udc;
+ struct usb_gadget_driver *driver;
+ struct ehci_ctrl *ctrl;
+ struct ept_queue_head *epts;
+ struct ept_queue_item *items[2 * NUM_ENDPOINTS];
+ uint8_t *items_mem;
+ struct mv_ep ep[NUM_ENDPOINTS];
};
struct ept_queue_head {
unsigned config;
- unsigned current; /* read-only */
+ unsigned current; /* read-only */
unsigned next;
unsigned info;
@@ -111,9 +106,9 @@ struct ept_queue_head {
unsigned reserved_4;
};
-#define CONFIG_MAX_PKT(n) ((n) << 16)
-#define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */
-#define CONFIG_IOS (1 << 15) /* IRQ on setup */
+#define CONFIG_MAX_PKT(n) ((n) << 16)
+#define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */
+#define CONFIG_IOS (1 << 15) /* IRQ on setup */
struct ept_queue_item {
unsigned next;
@@ -127,12 +122,11 @@ struct ept_queue_item {
};
#define TERMINATE 1
-#define INFO_BYTES(n) ((n) << 16)
-#define INFO_IOC (1 << 15)
-#define INFO_ACTIVE (1 << 7)
-#define INFO_HALTED (1 << 6)
-#define INFO_BUFFER_ERROR (1 << 5)
-#define INFO_TX_ERROR (1 << 3)
-
-extern int usb_lowlevel_init(int index, void **controller);
+#define INFO_BYTES(n) ((n) << 16)
+#define INFO_IOC (1 << 15)
+#define INFO_ACTIVE (1 << 7)
+#define INFO_HALTED (1 << 6)
+#define INFO_BUFFER_ERROR (1 << 5)
+#define INFO_TX_ERROR (1 << 3)
+
#endif /* __MV_UDC_H__ */
diff --git a/include/video_font.h b/include/video_font.h
index 7ef9519..96b9edb 100644
--- a/include/video_font.h
+++ b/include/video_font.h
@@ -8,9 +8,10 @@
#ifndef _VIDEO_FONT_
#define _VIDEO_FONT_
-#define VIDEO_FONT_CHARS 256
-#define VIDEO_FONT_WIDTH 8
-#define VIDEO_FONT_HEIGHT 16
-#define VIDEO_FONT_SIZE (VIDEO_FONT_CHARS * VIDEO_FONT_HEIGHT)
+#ifdef CONFIG_VIDEO_FONT_4X6
+#include <video_font_4x6.h>
+#else
+#include <video_font_data.h>
+#endif
#endif /* _VIDEO_FONT_ */
diff --git a/include/video_font_4x6.h b/include/video_font_4x6.h
new file mode 100644
index 0000000..d1778d5
--- /dev/null
+++ b/include/video_font_4x6.h
@@ -0,0 +1,2154 @@
+
+/* Hand composed "Minuscule" 4x6 font, with binary data generated using
+ * Perl stub.
+ *
+ * Use 'perl -x mini_4x6.c < mini_4x6.c > new_version.c' to regenerate
+ * binary data.
+ *
+ * Created by Kenneth Albanowski.
+ * No rights reserved, released to the public domain.
+ *
+ * Version 1.0
+ */
+
+/*
+
+#!/usr/bin/perl -pn
+
+s{((0x)?[0-9a-fA-F]+)(.*\[([\*\ ]{4})\])}{
+
+ ($num,$pat,$bits) = ($1,$3,$4);
+
+ $bits =~ s/([^\s0])|(.)/ defined($1) + 0 /ge;
+
+ $num = ord(pack("B8", $bits));
+ $num |= $num >> 4;
+ $num = sprintf("0x%.2x", $num);
+
+ #print "$num,$pat,$bits\n";
+
+ $num . $pat;
+}ge;
+
+__END__;
+*/
+
+/* Note: binary data consists of one byte for each row of each character top
+ to bottom, character 0 to character 255, six bytes per character. Each
+ byte contains the same four character bits in both nybbles.
+ MSBit to LSBit = left to right.
+ */
+
+#ifndef _VIDEO_FONT_DATA_
+#define _VIDEO_FONT_DATA_
+
+#define VIDEO_FONT_CHARS 256
+#define VIDEO_FONT_WIDTH 4
+#define VIDEO_FONT_HEIGHT 6
+#define VIDEO_FONT_SIZE (VIDEO_FONT_CHARS * VIDEO_FONT_HEIGHT)
+
+static unsigned char video_fontdata[VIDEO_FONT_SIZE] = {
+
+ /*{*/
+ /* Char 0: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 1: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 2: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 3: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 4: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 5: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 6: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 7: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 8: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 9: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 10: '' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 11: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 12: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 13: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 14: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 15: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 16: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 17: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 18: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 19: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 20: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 21: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 22: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 23: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 24: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 25: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 26: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 27: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 28: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 29: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 30: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 31: ' ' */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 32: ' ' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 33: '!' */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 34: '"' */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 35: '#' */
+ 0xaa, /*= [* * ] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 36: '$' */
+ 0x44, /*= [ * ] */
+ 0x66, /*= [ ** ] */
+ 0xee, /*= [*** ] */
+ 0xcc, /*= [** ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 37: '%' */
+ 0xaa, /*= [* * ] */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 38: '&' */
+ 0x66, /*= [ ** ] */
+ 0x99, /*= [* *] */
+ 0x66, /*= [ ** ] */
+ 0xaa, /*= [* * ] */
+ 0xdd, /*= [** *] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 39: ''' */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 40: '(' */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 41: ')' */
+ 0x44, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 42: '*' */
+ 0x00, /*= [ ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 43: '+' */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0xee, /*= [*** ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 44: ',' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 45: '-' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 46: '.' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 47: '/' */
+ 0x00, /*= [ ] */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 48: '0' */
+ 0x44, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 49: '1' */
+ 0x44, /*= [ * ] */
+ 0xcc, /*= [** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 50: '2' */
+ 0xcc, /*= [** ] */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/
+ /* Char 51: '3' */
+ 0xee, /*= [*** ] */
+ 0x22, /*= [ * ] */
+ 0x66, /*= [ ** ] */
+ 0x22, /*= [ * ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 52: '4' */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 53: '5' */
+ 0xee, /*= [*** ] */
+ 0x88, /*= [* ] */
+ 0xee, /*= [*** ] */
+ 0x22, /*= [ * ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 54: '6' */
+ 0xee, /*= [*** ] */
+ 0x88, /*= [* ] */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 55: '7' */
+ 0xee, /*= [*** ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 56: '8' */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 57: '9' */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 58: ':' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 59: ';' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ /*}*/
+ /*{*/ /* Char 60: '<' */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0x44, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 61: '=' */
+ 0x00, /*= [ ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 62: '>' */
+ 0x88, /*= [* ] */
+ 0x44, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 63: '?' */
+ 0xee, /*= [*** ] */
+ 0x22, /*= [ * ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 64: '@' */
+ 0x44, /*= [ * ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x88, /*= [* ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 65: 'A' */
+ 0x44, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 66: 'B' */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xcc, /*= [** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 67: 'C' */
+ 0x66, /*= [ ** ] */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 68: 'D' */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xcc, /*= [** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 69: 'E' */
+ 0xee, /*= [*** ] */
+ 0x88, /*= [* ] */
+ 0xee, /*= [*** ] */
+ 0x88, /*= [* ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 70: 'F' */
+ 0xee, /*= [*** ] */
+ 0x88, /*= [* ] */
+ 0xee, /*= [*** ] */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 71: 'G' */
+ 0x66, /*= [ ** ] */
+ 0x88, /*= [* ] */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 72: 'H' */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 73: 'I' */
+ 0xee, /*= [*** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 74: 'J' */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 75: 'K' */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 76: 'L' */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 77: 'M' */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 78: 'N' */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 79: 'O' */
+ 0x44, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 80: 'P' */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xcc, /*= [** ] */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 81: 'Q' */
+ 0x44, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 82: 'R' */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 83: 'S' */
+ 0x66, /*= [ ** ] */
+ 0x88, /*= [* ] */
+ 0x44, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0xcc, /*= [** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 84: 'T' */
+ 0xee, /*= [*** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 85: 'U' */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 86: 'V' */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 87: 'W' */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 88: 'X' */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x44, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 89: 'Y' */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 90: 'Z' */
+ 0xee, /*= [*** ] */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 91: '[' */
+ 0x66, /*= [ ** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 92: '\' */
+ 0x00, /*= [ ] */
+ 0x88, /*= [* ] */
+ 0x44, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 93: ']' */
+ 0x66, /*= [ ** ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 94: '^' */
+ 0x44, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 95: '_' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xff, /*= [****] */
+ /*}*/
+ /*{*/ /* Char 96: '`' */
+ 0x88, /*= [* ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 97: 'a' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x66, /*= [ ** ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 98: 'b' */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xcc, /*= [** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 99: 'c' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x66, /*= [ ** ] */
+ 0x88, /*= [* ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 100: 'd' */
+ 0x22, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x66, /*= [ ** ] */
+ 0xaa, /*= [* * ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 101: 'e' */
+ 0x00, /*= [ ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x88, /*= [* ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 102: 'f' */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xee, /*= [*** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 103: 'g' */
+ 0x00, /*= [ ] */
+ 0x66, /*= [ ** ] */
+ 0xaa, /*= [* * ] */
+ 0x66, /*= [ ** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 104: 'h' */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 105: 'i' */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 106: 'j' */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 107: 'k' */
+ 0x00, /*= [ ] */
+ 0x88, /*= [* ] */
+ 0xaa, /*= [* * ] */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 108: 'l' */
+ 0x00, /*= [ ] */
+ 0xcc, /*= [** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 109: 'm' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 110: 'n' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 111: 'o' */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 112: 'p' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0xcc, /*= [** ] */
+ 0x88, /*= [* ] */
+ /*}*/
+ /*{*/ /* Char 113: 'q' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x66, /*= [ ** ] */
+ 0xaa, /*= [* * ] */
+ 0x66, /*= [ ** ] */
+ 0x22, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 114: 'r' */
+ 0x00, /*= [ ] */
+ 0xcc, /*= [** ] */
+ 0xaa, /*= [* * ] */
+ 0x88, /*= [* ] */
+ 0x88, /*= [* ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 115: 's' */
+ 0x00, /*= [ ] */
+ 0x66, /*= [ ** ] */
+ 0xcc, /*= [** ] */
+ 0x22, /*= [ * ] */
+ 0xcc, /*= [** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 116: 't' */
+ 0x00, /*= [ ] */
+ 0x44, /*= [ * ] */
+ 0xee, /*= [*** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 117: 'u' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 118: 'v' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 119: 'w' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 120: 'x' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xaa, /*= [* * ] */
+ 0x44, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 121: 'y' */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0x22, /*= [ * ] */
+ 0xcc, /*= [** ] */
+ /*}*/
+ /*{*/ /* Char 122: 'z' */
+ 0x00, /*= [ ] */
+ 0xee, /*= [*** ] */
+ 0x66, /*= [ ** ] */
+ 0xcc, /*= [** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 123: '{' */
+ 0x22, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xcc, /*= [** ] */
+ 0x44, /*= [ * ] */
+ 0x22, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 124: '|' */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 125: '}' */
+ 0x88, /*= [* ] */
+ 0x44, /*= [ * ] */
+ 0x66, /*= [ ** ] */
+ 0x44, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 126: '~' */
+ 0x55, /*= [ * *] */
+ 0xaa, /*= [* * ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 127: '' */
+ 0x44, /*= [ * ] */
+ 0xaa, /*= [* * ] */
+ 0xaa, /*= [* * ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 128: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 129: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 130: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 131: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 132: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 133: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 134: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 135: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 136: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 137: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 138: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 139: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 140: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 141: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 142: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 143: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 144: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 145: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 146: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 147: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 148: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 149: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 150: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 151: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 152: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 153: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 154: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 155: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 156: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 157: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 158: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 159: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 160: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 161: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 162: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 163: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 164: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 165: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 166: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 167: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 168: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 169: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 170: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 171: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 172: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 173: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 174: */
+ 0x00, /*= [ ] */
+ 0x66, /*= [ ** ] */
+ 0xcc, /*= [** ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 175: */
+ 0x00, /*= [ ] */
+ 0xcc, /*= [** ] */
+ 0x66, /*= [ ** ] */
+ 0xcc, /*= [** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 176: */
+ 0x88, /*= [* ] */
+ 0x22, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0x22, /*= [ * ] */
+ 0x88, /*= [* ] */
+ 0x22, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 177: */
+ 0xaa, /*= [* * ] */
+ 0x55, /*= [ * *] */
+ 0xaa, /*= [* * ] */
+ 0x55, /*= [ * *] */
+ 0xaa, /*= [* * ] */
+ 0x55, /*= [ * *] */
+ /*}*/
+ /*{*/ /* Char 178: */
+ 0xdd, /*= [** *] */
+ 0xbb, /*= [* **] */
+ 0xdd, /*= [** *] */
+ 0xbb, /*= [* **] */
+ 0xdd, /*= [** *] */
+ 0xbb, /*= [* **] */
+ /*}*/
+ /*{*/ /* Char 179: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 180: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xcc, /*= [** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 181: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xcc, /*= [** ] */
+ 0xcc, /*= [** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 182: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0xee, /*= [*** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 183: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xee, /*= [*** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 184: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xcc, /*= [** ] */
+ 0xcc, /*= [** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 185: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 186: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 187: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 188: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 189: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 190: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xcc, /*= [** ] */
+ 0xcc, /*= [** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 191: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xcc, /*= [** ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 192: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x77, /*= [ ***] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 193: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xff, /*= [****] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 194: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xff, /*= [****] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 195: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x77, /*= [ ***] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 196: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xff, /*= [****] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 197: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xff, /*= [****] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 198: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x77, /*= [ ***] */
+ 0x77, /*= [ ***] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 199: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x77, /*= [ ***] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 200: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x77, /*= [ ***] */
+ 0x77, /*= [ ***] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 201: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x77, /*= [ ***] */
+ 0x77, /*= [ ***] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 202: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 203: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 204: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x77, /*= [ ***] */
+ 0x77, /*= [ ***] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 205: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 206: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 207: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 208: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0xff, /*= [****] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 209: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 210: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xff, /*= [****] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 211: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x77, /*= [ ***] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 212: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x77, /*= [ ***] */
+ 0x77, /*= [ ***] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 213: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x77, /*= [ ***] */
+ 0x77, /*= [ ***] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 214: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x77, /*= [ ***] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 215: */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0xff, /*= [****] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ /*}*/
+ /*{*/ /* Char 216: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 217: */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0xcc, /*= [** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 218: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x77, /*= [ ***] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ 0x44, /*= [ * ] */
+ /*}*/
+ /*{*/ /* Char 219: */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ /*}*/
+ /*{*/ /* Char 220: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ /*}*/
+ /*{*/ /* Char 221: */
+ 0xcc, /*= [** ] */
+ 0xcc, /*= [** ] */
+ 0xcc, /*= [** ] */
+ 0xcc, /*= [** ] */
+ 0xcc, /*= [** ] */
+ 0xcc, /*= [** ] */
+ /*}*/
+ /*{*/ /* Char 222: */
+ 0x33, /*= [ **] */
+ 0x33, /*= [ **] */
+ 0x33, /*= [ **] */
+ 0x33, /*= [ **] */
+ 0x33, /*= [ **] */
+ 0x33, /*= [ **] */
+ /*}*/
+ /*{*/ /* Char 223: */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0xff, /*= [****] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 224: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 225: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 226: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 227: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 228: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 229: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 230: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 231: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 232: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 233: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 234: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 235: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 236: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 237: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 238: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 239: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 240: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 241: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 242: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 243: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 244: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 245: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 246: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 247: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 248: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 249: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 250: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 251: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 252: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 253: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 254: */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ 0x66, /*= [ ** ] */
+ 0x66, /*= [ ** ] */
+ 0x00, /*= [ ] */
+ 0x00, /*= [ ] */
+ /*}*/
+ /*{*/ /* Char 255: */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0xee, /*= [*** ] */
+ 0x00, /*= [ ] */
+ /*}*/
+};
+
+#endif
diff --git a/include/video_font_data.h b/include/video_font_data.h
index 4e544f0..346a162 100644
--- a/include/video_font_data.h
+++ b/include/video_font_data.h
@@ -8,7 +8,12 @@
#ifndef _VIDEO_FONT_DATA_
#define _VIDEO_FONT_DATA_
-static unsigned char video_fontdata[VIDEO_FONT_SIZE] = {
+#define VIDEO_FONT_CHARS 256
+#define VIDEO_FONT_WIDTH 8
+#define VIDEO_FONT_HEIGHT 16
+#define VIDEO_FONT_SIZE (VIDEO_FONT_CHARS * VIDEO_FONT_HEIGHT)
+
+static unsigned char __maybe_unused video_fontdata[VIDEO_FONT_SIZE] = {
/* 0 0x00 '^@' */
0x00, /* 00000000 */
diff --git a/include/zynqpl.h b/include/zynqpl.h
index f8211cd..6107cbf 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -20,12 +20,14 @@ extern int zynq_info(Xilinx_desc *desc);
#define XILINX_ZYNQ_7020 0x7
#define XILINX_ZYNQ_7030 0xc
#define XILINX_ZYNQ_7045 0x11
+#define XILINX_ZYNQ_7100 0x16
/* Device Image Sizes */
#define XILINX_XC7Z010_SIZE 16669920/8
#define XILINX_XC7Z020_SIZE 32364512/8
#define XILINX_XC7Z030_SIZE 47839328/8
#define XILINX_XC7Z045_SIZE 106571232/8
+#define XILINX_XC7Z100_SIZE 139330784/8
/* Descriptor Macros */
#define XILINX_XC7Z010_DESC(cookie) \
@@ -40,4 +42,7 @@ extern int zynq_info(Xilinx_desc *desc);
#define XILINX_XC7Z045_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" }
+#define XILINX_XC7Z100_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, "7z100" }
+
#endif /* _ZYNQPL_H_ */