diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-at91/at91_pmc.h | 30 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91/at91sam9263.h | 1 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91/at91sam9_sdramc.h | 87 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91/clk.h | 19 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91/hardware.h | 20 | ||||
| -rw-r--r-- | include/asm-arm/u-boot-arm.h | 3 | ||||
| -rw-r--r-- | include/configs/afeb9260.h | 7 | ||||
| -rw-r--r-- | include/configs/at91cap9adk.h | 8 | ||||
| -rw-r--r-- | include/configs/at91sam9260ek.h | 10 | ||||
| -rw-r--r-- | include/configs/at91sam9261ek.h | 7 | ||||
| -rw-r--r-- | include/configs/at91sam9263ek.h | 8 | ||||
| -rw-r--r-- | include/configs/at91sam9rlek.h | 7 | ||||
| -rw-r--r-- | include/configs/pm9263.h | 367 |
13 files changed, 528 insertions, 46 deletions
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h index b57875d..07580da 100644 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ b/include/asm-arm/arch-at91/at91_pmc.h @@ -1,5 +1,5 @@ /* - * [origin: Linux kernel include/asm-arm/arch-at91/at91_pmc.h] + * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h] * * Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) SAN People @@ -23,6 +23,7 @@ #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ +#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */ #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ #define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ @@ -39,10 +40,14 @@ #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ +#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ +#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ +#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ +#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ -#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ +#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ @@ -76,10 +81,17 @@ #define AT91_PMC_PRES_32 (5 << 2) #define AT91_PMC_PRES_64 (6 << 2) #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ -#define AT91_PMC_MDIV_1 (0 << 8) -#define AT91_PMC_MDIV_2 (1 << 8) -#define AT91_PMC_MDIV_3 (2 << 8) -#define AT91_PMC_MDIV_4 (3 << 8) +#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ +#define AT91RM9200_PMC_MDIV_2 (1 << 8) +#define AT91RM9200_PMC_MDIV_3 (2 << 8) +#define AT91RM9200_PMC_MDIV_4 (3 << 8) +#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ +#define AT91SAM9_PMC_MDIV_2 (1 << 8) +#define AT91SAM9_PMC_MDIV_4 (2 << 8) +#define AT91SAM9_PMC_MDIV_6 (3 << 8) +#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ +#define AT91_PMC_PDIV_1 (0 << 12) +#define AT91_PMC_PDIV_2 (1 << 12) #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ @@ -90,6 +102,8 @@ #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ +#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */ +#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */ #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ @@ -97,8 +111,8 @@ #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ #define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ -#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ +#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ -#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ +#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ #endif diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h index 98251cb..07b265f 100644 --- a/include/asm-arm/arch-at91/at91sam9263.h +++ b/include/asm-arm/arch-at91/at91sam9263.h @@ -106,6 +106,7 @@ #define AT91_USART2 AT91SAM9263_BASE_US2 #define AT91_SMC AT91_SMC0 +#define AT91_SDRAMC AT91_SDRAMC0 /* * Internal Memory. diff --git a/include/asm-arm/arch-at91/at91sam9_sdramc.h b/include/asm-arm/arch-at91/at91sam9_sdramc.h new file mode 100644 index 0000000..5af2b54 --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9_sdramc.h @@ -0,0 +1,87 @@ +/* + * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h] + * + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * Copyright (C) 2007 Andrew Victor + * Copyright (C) 2007 Atmel Corporation. + * + * SDRAM Controllers (SDRAMC) - System peripherals registers. + * Based on AT91SAM9261 datasheet revision D. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9_SDRAMC_H +#define AT91SAM9_SDRAMC_H + +/* SDRAM Controller (SDRAMC) registers */ +#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ +#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ +#define AT91_SDRAMC_MODE_NORMAL 0 +#define AT91_SDRAMC_MODE_NOP 1 +#define AT91_SDRAMC_MODE_PRECHARGE 2 +#define AT91_SDRAMC_MODE_LMR 3 +#define AT91_SDRAMC_MODE_REFRESH 4 +#define AT91_SDRAMC_MODE_EXT_LMR 5 +#define AT91_SDRAMC_MODE_DEEP 6 + +#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ +#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ + +#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ +#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ +#define AT91_SDRAMC_NC_8 (0 << 0) +#define AT91_SDRAMC_NC_9 (1 << 0) +#define AT91_SDRAMC_NC_10 (2 << 0) +#define AT91_SDRAMC_NC_11 (3 << 0) +#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ +#define AT91_SDRAMC_NR_11 (0 << 2) +#define AT91_SDRAMC_NR_12 (1 << 2) +#define AT91_SDRAMC_NR_13 (2 << 2) +#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ +#define AT91_SDRAMC_NB_2 (0 << 4) +#define AT91_SDRAMC_NB_4 (1 << 4) +#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ +#define AT91_SDRAMC_CAS_1 (1 << 5) +#define AT91_SDRAMC_CAS_2 (2 << 5) +#define AT91_SDRAMC_CAS_3 (3 << 5) +#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ +#define AT91_SDRAMC_DBW_32 (0 << 7) +#define AT91_SDRAMC_DBW_16 (1 << 7) +#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ +#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ +#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ +#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ +#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ +#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ + +#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ +#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ +#define AT91_SDRAMC_LPCB_DISABLE 0 +#define AT91_SDRAMC_LPCB_SELF_REFRESH 1 +#define AT91_SDRAMC_LPCB_POWER_DOWN 2 +#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 +#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ +#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ +#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */ +#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ +#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) +#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) +#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) + +#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ +#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ +#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ +#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ +#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ + +#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ +#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ +#define AT91_SDRAMC_MD_SDRAM 0 +#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 + + +#endif diff --git a/include/asm-arm/arch-at91/clk.h b/include/asm-arm/arch-at91/clk.h index 1b502c8..6aaf82e 100644 --- a/include/asm-arm/arch-at91/clk.h +++ b/include/asm-arm/arch-at91/clk.h @@ -2,6 +2,7 @@ * (C) Copyright 2007 * Stelian Pop <stelian.pop@leadtechdesign.com> * Lead Tech Design <www.leadtechdesign.com> + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> * * See file CREDITS for list of people who contributed to this * project. @@ -26,20 +27,32 @@ #include <asm/arch/hardware.h> +unsigned long get_cpu_clk_rate(void); +unsigned long get_main_clk_rate(void); +unsigned long get_mck_clk_rate(void); +unsigned long get_plla_clk_rate(void); +unsigned long get_pllb_clk_rate(void); +unsigned int get_pllb_init(void); + static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) { - return AT91_MASTER_CLOCK; + return get_mck_clk_rate(); } static inline unsigned long get_usart_clk_rate(unsigned int dev_id) { - return AT91_MASTER_CLOCK; + return get_mck_clk_rate(); } static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id) { - return AT91_MASTER_CLOCK; + return get_mck_clk_rate(); } +static inline unsigned long get_twi_clk_rate(unsigned int dev_id) +{ + return get_mck_clk_rate(); +} +int at91_clock_init(unsigned long main_clock); #endif /* __ASM_ARM_ARCH_CLK_H__ */ diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index 4f0e1a7..8704106 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h @@ -48,4 +48,24 @@ #error "Unsupported AT91 processor" #endif +/* External Memory Map */ +#define AT91_CHIPSELECT_0 0x10000000 +#define AT91_CHIPSELECT_1 0x20000000 +#define AT91_CHIPSELECT_2 0x30000000 +#define AT91_CHIPSELECT_3 0x40000000 +#define AT91_CHIPSELECT_4 0x50000000 +#define AT91_CHIPSELECT_5 0x60000000 +#define AT91_CHIPSELECT_6 0x70000000 +#define AT91_CHIPSELECT_7 0x80000000 + +/* SDRAM */ +#ifdef CONFIG_DRAM_BASE +#define AT91_SDRAM_BASE CONFIG_DRAM_BASE +#else +#define AT91_SDRAM_BASE AT91_CHIPSELECT_1 +#endif + +/* Clocks */ +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + #endif diff --git a/include/asm-arm/u-boot-arm.h b/include/asm-arm/u-boot-arm.h index 4ee5a32..e7d58fe 100644 --- a/include/asm-arm/u-boot-arm.h +++ b/include/asm-arm/u-boot-arm.h @@ -40,6 +40,9 @@ extern ulong FIQ_STACK_START; /* top of FIQ stack */ int cpu_init(void); int cleanup_before_linux(void); +/* cpu/.../arch/cpu.c */ +int arch_cpu_init(void); + /* board/.../... */ int board_init(void); int dram_init (void); diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index de938f7..c5134a2 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -28,14 +28,11 @@ /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */ -#define AT91_MASTER_CLOCK 89999598 /* peripheral = main / 2 */ -#define CONFIG_SYS_AT91_PLLB 0x107c3e18 /* PLLB settings for USB */ -#define CONFIG_SYS_HZ 1000000 /* 1us resolution */ - -#define AT91_SLOW_CLOCK 32768 /* slow clock */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/ #define CONFIG_AFEB9260 1 /* on an AFEB9260 Board */ +#define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index b978731..b2e6d7d 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -30,16 +30,12 @@ /* ARM asynchronous clock */ #define AT91_CPU_NAME "AT91CAP9" #define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ -#define AT91_MASTER_CLOCK 100000000 /* peripheral */ -#define AT91_CPU_CLOCK 200000000 /* cpu */ -#define CONFIG_SYS_AT91_PLLB 0x10073e01 /* PLLB settings for USB */ -#define CONFIG_SYS_HZ 1000000 /* 1us resolution */ - -#define AT91_SLOW_CLOCK 32768 /* slow clock */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_AT91CAP9 1 /* It's an Atmel AT91CAP9 SoC */ #define CONFIG_AT91CAP9ADK 1 /* on an AT91CAP9ADK Board */ +#define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index bcc65bd..e46c9d6 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -29,25 +29,19 @@ /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ -#define CONFIG_SYS_AT91_PLLB 0x107c3e18 /* PLLB settings for USB */ -#define CONFIG_SYS_HZ 1000000 /* 1us resolution */ - -#define AT91_SLOW_CLOCK 32768 /* slow clock */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #ifdef CONFIG_AT91SAM9G20EK #define AT91_CPU_NAME "AT91SAM9G20" -#define AT91_MASTER_CLOCK 132000000 /* peripheral */ -#define AT91_CPU_CLOCK 396000000 /* cpu */ #define CONFIG_AT91SAM9G20 1 /* It's an Atmel AT91SAM9G20 SoC*/ #else #define AT91_CPU_NAME "AT91SAM9260" -#define AT91_MASTER_CLOCK 100000000 /* peripheral */ -#define AT91_CPU_CLOCK 200000000 /* cpu */ #define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/ #endif +#define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index cc40d7b..fdaa71c 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -30,15 +30,12 @@ /* ARM asynchronous clock */ #define AT91_CPU_NAME "AT91SAM9261" #define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ -#define AT91_MASTER_CLOCK 100000000 /* peripheral */ -#define AT91_CPU_CLOCK 200000000 /* cpu */ -#define CONFIG_SYS_HZ 1000000 /* 1us resolution */ - -#define AT91_SLOW_CLOCK 32768 /* slow clock */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/ #define CONFIG_AT91SAM9261EK 1 /* on an AT91SAM9261EK Board */ +#define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index ee1531f..d03ecee 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -30,16 +30,12 @@ /* ARM asynchronous clock */ #define AT91_CPU_NAME "AT91SAM9263" #define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ -#define AT91_MASTER_CLOCK 100000000 /* peripheral */ -#define AT91_CPU_CLOCK 200000000 /* cpu */ -#define CONFIG_SYS_AT91_PLLB 0x133a3e8d /* PLLB settings for USB */ -#define CONFIG_SYS_HZ 1000000 /* 1us resolution */ - -#define AT91_SLOW_CLOCK 32768 /* slow clock */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ #define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */ +#define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index fec48b6..846d165 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -30,15 +30,12 @@ /* ARM asynchronous clock */ #define AT91_CPU_NAME "AT91SAM9RL" #define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ -#define AT91_MASTER_CLOCK 100000000 /* peripheral */ -#define AT91_CPU_CLOCK 200000000 /* cpu */ -#define CONFIG_SYS_HZ 1000000 /* 1us resolution */ - -#define AT91_SLOW_CLOCK 32768 /* slow clock */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_AT91SAM9RL 1 /* It's an Atmel AT91SAM9RL SoC*/ #define CONFIG_AT91SAM9RLEK 1 /* on an AT91SAM9RLEK Board */ +#define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h new file mode 100644 index 0000000..0db17b3 --- /dev/null +++ b/include/configs/pm9263.h @@ -0,0 +1,367 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * Ilko Iliev <www.ronetix.at> + * + * Configuation settings for the RONETIX PM9263 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91_CPU_NAME "AT91SAM9263" + +#define CONFIG_DISPLAY_BOARDINFO + +#define MASTER_PLL_DIV 15 +#define MASTER_PLL_MUL 162 +#define MAIN_PLL_DIV 2 /* 2 or 4 */ +#define AT91_MAIN_CLOCK 18432000 + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ +#define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */ +#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* clocks */ +#define CONFIG_SYS_MOR_VAL 0x00002001 /* CKGR_MOR - enable main osc. */ +#define CONFIG_SYS_PLLAR_VAL \ + (0x2000BF00 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) + +#if (MAIN_PLL_DIV == 2) +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR1_VAL 0x00000100 +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR2_VAL 0x00000102 +#else +/* PCK/4 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR1_VAL 0x00000200 +/* PCK/4 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR2_VAL 0x00000202 +#endif +/* define PDC[31:16] as DATA[31:16] */ +#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +/* no pull-up for D[31:16] */ +#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 +/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ +#define CONFIG_SYS_MATRIX_EBI0CSA_VAL 0x0001010A +/* EBI1_CSA, 3.3v, no pull-ups */ +#define CONFIG_SYS_MATRIX_EBI1CSA_VAL 0x00010100 + +/* SDRAM */ +/* SDRAMC_MR Mode register */ +#define CONFIG_SYS_SDRC_MR_VAL1 0 +/* SDRAMC_TR - Refresh Timer register */ +#define CONFIG_SYS_SDRC_TR_VAL1 0x13C +#define CONFIG_SYS_SDRC_CR_VAL 0x85227279 /*CL3*/ +/* Memory Device Register -> SDRAM */ +#define CONFIG_SYS_SDRC_MDR_VAL 0 +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000002 /* SDRAMC_MR */ +#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL3 4 /* SDRC_MR */ +#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL4 3 /* SDRC_MR */ +#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL5 0 /* SDRC_MR */ +#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ + +/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ +#define CONFIG_SYS_SMC0_SETUP0_VAL 0x0A0A0A0A /* SMC_SETUP */ +#define CONFIG_SYS_SMC0_PULSE0_VAL 0x0B0B0B0B /* SMC_PULSE */ +#define CONFIG_SYS_SMC0_CYCLE0_VAL 0x00160016 /* SMC_CYCLE */ +#define CONFIG_SYS_SMC0_CTRL0_VAL 0x00161003 /* SMC_MODE */ + +/* setup SMC1, CS0 (PSRAM) - 16-bit */ +#define CONFIG_SYS_SMC1_SETUP0_VAL 0x00000000 /* SMC_SETUP */ +#define CONFIG_SYS_SMC1_PULSE0_VAL 0x07020707 /* SMC_PULSE */ +#define CONFIG_SYS_SMC1_CYCLE0_VAL 0x00080008 /* SMC_CYCLE */ +#define CONFIG_SYS_SMC1_CTRL0_VAL 0x31001000 /* SMC_MODE */ + +#define CONFIG_SYS_RSTC_RMR_VAL 0xA5000301 /* user reset enable */ + +/* Watchdog */ +#define CONFIG_SYS_WDTC_WDMR_VAL 0x3fff8fff /* disable watchdog */ + +/* */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_RELOCATE_UBOOT +#define CONFIG_USER_LOWLEVEL_INIT 1 + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +/* LCD */ +#define CONFIG_LCD 1 +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CONFIG_SYS_WHITE_ON_BLACK 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_BGR555 1 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + +#define CONFIG_LCD_IN_PSRAM 1 + +/* LED */ +#define CONFIG_AT91_LED +#define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */ +#define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */ + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* DataFlash */ +#define CONFIG_ATMEL_DATAFLASH_SPI +#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* NOR flash, if populated */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define PHYS_FLASH_1 0x10000000 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PB30 +#endif + +#define CONFIG_CMD_JFFS2 1 +#define CONFIG_JFFS2_CMDLINE 1 +#define CONFIG_JFFS2_NAND 1 +#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ +#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/ + +/* PSRAM */ +#define PHYS_PSRAM 0x70000000 +#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ + +/* Ethernet */ +#define CONFIG_MACB 1 +#define CONFIG_RMII 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R 1 + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END 0x23e00000 + +#define CONFIG_SYS_USE_FLASH 1 +#undef CONFIG_SYS_USE_DATAFLASH +#undef CONFIG_SYS_USE_NANDFLASH + +#ifdef CONFIG_SYS_USE_DATAFLASH + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CONFIG_ENV_IS_IN_DATAFLASH +#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) +#define CONFIG_ENV_OFFSET 0x4200 +#define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x4200 +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) "\ + "rw rootfstype=jffs2" + +#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */ + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x60000 +#define CONFIG_ENV_OFFSET_REDUND 0x80000 +#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock5 " \ + "mtdparts=at91_nand:" \ + "128k(bootstrap)ro," \ + "256k(uboot)ro," \ + "128k(env1)ro," \ + "128k(env2)ro," \ + "2M(linux)," \ + "-(root) " \ + "rw rootfstype=jffs2" + +#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */ + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_OVERWRITE 1 + +/* JFFS Partition offset set */ +#define CONFIG_SYS_JFFS2_FIRST_BANK 0 +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +/* 512k reserved for u-boot */ +#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 + +#define CONFIG_BOOTCOMMAND "run flashboot" +#define CONFIG_ROOTPATH /ronetix/rootfs +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" + +#define CONFIG_CON_ROT "fbcon=rotate:3 " +#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\ + CONFIG_CON_ROT + +#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand" +#define MTDPARTS_DEFAULT \ + "mtdparts=physmap-flash.0:" \ + "256k(u-boot)ro," \ + "64k(u-boot-env)ro," \ + "1408k(kernel)," \ + "-(rootfs);" \ + "nand:-(nand)" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "partition=nand0,0\0" \ + "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + CONFIG_CON_ROT \ + "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ + ":$(hostname):eth0:off\0" \ + "ramboot=tftpboot 0x22000000 vmImage;" \ + "run ramargs;run addip;bootm 22000000\0" \ + "nfsboot=tftpboot 0x22000000 vmImage;" \ + "run nfsargs;run addip;bootm 22000000\0" \ + "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ + "" + +#else +#error "Undefined memory device" +#endif + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "u-boot-pm9263> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif |