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-rw-r--r--include/asm-arm/arch-arm1136/clocks.h52
-rw-r--r--include/asm-arm/arch-arm1136/mem.h124
-rw-r--r--include/asm-arm/arch-arm1136/omap2420.h3
-rw-r--r--include/asm-arm/arch-arm1136/sys_info.h1
-rw-r--r--include/asm-arm/arch-arm1136/sys_proto.h6
-rw-r--r--include/configs/omap2420h4.h73
6 files changed, 213 insertions, 46 deletions
diff --git a/include/asm-arm/arch-arm1136/clocks.h b/include/asm-arm/arch-arm1136/clocks.h
index 9a88e85..bd1b088 100644
--- a/include/asm-arm/arch-arm1136/clocks.h
+++ b/include/asm-arm/arch-arm1136/clocks.h
@@ -61,15 +61,53 @@
#define II_BUS_DIV_ES1 0x04601026
#define II_DPLL_300 0x01832100
+/****************************************************************************;
+; PRCM Scheme III
+;
+; Enable clocks and DPLL for:
+; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266
+; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
+; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0]
+; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0]
+; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5]
+; DSP_S ACTIVATED CM_CLKSEL_DSP[7]
+; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8]
+; IVAF=88.67 auto
+; IVAI auto
+; IVA_MPU auto
+; IVA_S ACTIVATED CM_CLKSEL_DSP[13]
+; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]:
+; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20]
+; SSI_SSTF=88.67 auto
+; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0]
+; L4=66.5Mhz /8
+; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5]
+***************************************************************************/
+#define III_DPLL_OUT_X2 0x2 /* x2 core out */
+#define III_MPU_DIV 0x2 /* mpu = core/2 */
+#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/
+#define III_GFX_DIV 0x2
+#define III_BUS_DIV 0x08300c44
+#define III_BUS_DIV_ES1 0x08301044
+#define III_DPLL_266 0x01885500
+
/* set defaults for boot up */
#ifdef PRCM_CONFIG_II
-#define DPLL_OUT II_DPLL_OUT_X2
-#define MPU_DIV II_MPU_DIV
-#define DSP_DIV II_DSP_DIV
-#define GFX_DIV II_GFX_DIV
-#define BUS_DIV II_BUS_DIV
-#define BUS_DIV_ES1 II_BUS_DIV_ES1
-#define DPLL_VAL II_DPLL_300
+# define DPLL_OUT II_DPLL_OUT_X2
+# define MPU_DIV II_MPU_DIV
+# define DSP_DIV II_DSP_DIV
+# define GFX_DIV II_GFX_DIV
+# define BUS_DIV II_BUS_DIV
+# define BUS_DIV_ES1 II_BUS_DIV_ES1
+# define DPLL_VAL II_DPLL_300
+#elif PRCM_CONFIG_III
+# define DPLL_OUT III_DPLL_OUT_X2
+# define MPU_DIV III_MPU_DIV
+# define DSP_DIV III_DSP_DIV
+# define GFX_DIV III_GFX_DIV
+# define BUS_DIV III_BUS_DIV
+# define BUS_DIV_ES1 III_BUS_DIV_ES1
+# define DPLL_VAL III_DPLL_266
#endif
/* lock delay time out */
diff --git a/include/asm-arm/arch-arm1136/mem.h b/include/asm-arm/arch-arm1136/mem.h
index bd6fd50..2ead7d8 100644
--- a/include/asm-arm/arch-arm1136/mem.h
+++ b/include/asm-arm/arch-arm1136/mem.h
@@ -33,51 +33,99 @@
early in init when NO global access are there */
struct sdrc_data_s {
u32 sdrc_sharing;
- u32 sdrc_mdcfg_0;
+ u32 sdrc_mdcfg_0_ddr;
+ u32 sdrc_mdcfg_0_sdr;
u32 sdrc_actim_ctrla_0;
u32 sdrc_actim_ctrlb_0;
u32 sdrc_rfr_ctrl;
- u32 sdrc_mr_0;
+ u32 sdrc_mr_0_ddr;
+ u32 sdrc_mr_0_sdr;
u32 sdrc_dlla_ctrl;
u32 sdrc_dllb_ctrl;
} /*__attribute__ ((packed))*/;
typedef struct sdrc_data_s sdrc_data_t;
+
+typedef enum {
+ STACKED = 0,
+ IP_DDR = 1,
+ COMBO_DDR = 2,
+ IP_SDR = 3,
+} mem_t;
+
#endif
/* Slower full frequency range default timings for x32 operation*/
#define H4_2420_SDRC_SHARING 0x00000100
-#define H4_2420_SDRC_MDCFG_0 0x01702011
-#define H4_2420_SDRC_ACTIM_CTRLA_0 0x9bead909
-#define H4_2420_SDRC_ACTIM_CTRLB_0 0x00000014
-#define H4_2420_SDRC_RFR_CTRL_ES1 0x00002401
-#define H4_2420_SDRC_RFR_CTRL 0x0002da01
-#define H4_2420_SDRC_MR_0 0x00000032
-#define H4_2420_SDRC_DLLA_CTRL 0x00007307
-#define H4_2420_SDRC_DLLB_CTRL 0x00007307
-
-#define H4_2422_SDRC_SHARING 0x00004b00
-#define H4_2422_SDRC_MDCFG_0 0x00801011
-#define H4_2422_SDRC_ACTIM_CTRLA_0 0x9BEAD909
-#define H4_2422_SDRC_ACTIM_CTRLB_0 0x00000020
-#define H4_2422_SDRC_RFR_CTRL_ES1 0x00002401
-#define H4_2422_SDRC_RFR_CTRL 0x0002da03
-#define H4_2422_SDRC_MR_0 0x00000032
-#define H4_2422_SDRC_DLLA_CTRL 0x00007307
-#define H4_2422_SDRC_DLLB_CTRL 0x00007307
-
-#define H4_2420_COMBO_MDCFG_0 0x00801011
+#define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */
+#define H4_2420_SDRC_MR_0_SDR 0x00000031
+#define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */
+#define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */
+#define H4_2420_SDRC_MR_0_DDR 0x00000032
+
+#ifndef CONFIG_OPTIMIZE_DDR
+# define H4_2420_SDRC_ACTIM_CTRLA_0 0x9bead909
+# define H4_2420_SDRC_ACTIM_CTRLB_0 0x00000014
+# define H4_2420_SDRC_RFR_CTRL_ES1 0x00002401
+# define H4_2420_SDRC_RFR_CTRL 0x0002da01
+#endif
+#define H4_2420_SDRC_DLLA_CTRL 0x00007307 /* load value at 100Mhz */
+#define H4_2420_SDRC_DLLB_CTRL 0x00007307
+
+#define H4_2422_SDRC_SHARING 0x00004b00
+#define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked ddr on 2422 */
+#ifndef CONFIG_OPTIMIZE_DDR
+# define H4_2422_SDRC_ACTIM_CTRLA_0 0x9BEAD909
+# define H4_2422_SDRC_ACTIM_CTRLB_0 0x00000020
+# define H4_2422_SDRC_RFR_CTRL_ES1 0x00002401
+# define H4_2422_SDRC_RFR_CTRL 0x0002da01
+#endif
+#define H4_2422_SDRC_MR_0_DDR 0x00000032
+#define H4_2422_SDRC_DLLA_CTRL 0x00007307
+#define H4_2422_SDRC_DLLB_CTRL 0x00007307
/* optimized timings */
-#define H4_2420_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485
-#define H4_2420_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e
+#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485
+#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e
+#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settigs */
+#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */
+#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01 /* this is not optimal yet */
+#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01
+
+#ifdef CONFIG_OPTIMIZE_DDR
+# ifdef PRCM_CONFIG_II
+# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
+# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
+# define H4_2420_SDRC_RFR_CTRL_ES1 H4_242X_SDRC_RFR_CTRL_100MHz
+# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
+# elif PRCM_CONFIG_III
+# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
+# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
+# define H4_2420_SDRC_RFR_CTRL_ES1 H4_242X_SDRC_RFR_CTRL_133MHz
+# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz
+# endif
+# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_2420_SDRC_ACTIM_CTRLA_0
+# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_2420_SDRC_ACTIM_CTRLB_0
+# define H4_2422_SDRC_RFR_CTRL_ES1 H4_2420_SDRC_RFR_CTRL_ES1
+# define H4_2422_SDRC_RFR_CTRL H4_2420_SDRC_RFR_CTRL
+#endif
+/* GPMC settings */
#ifdef PRCM_CONFIG_II /* L3 at 100MHz */
+#ifdef CFG_NAND_BOOT
+#define H4_24XX_GPMC_CONFIG1_0 0x0
+#define H4_24XX_GPMC_CONFIG2_0 0x00141400
+#define H4_24XX_GPMC_CONFIG3_0 0x00141400
+#define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
+#define H4_24XX_GPMC_CONFIG5_0 0x010C1414
+#define H4_24XX_GPMC_CONFIG6_0 0x00000A80
+#else
#define H4_24XX_GPMC_CONFIG1_0 0x3
-#define H4_24XX_GPMC_CONFIG2_0 0x001f1f01
-#define H4_24XX_GPMC_CONFIG3_0 0x00030301
-#define H4_24XX_GPMC_CONFIG4_0 0x0C030C03
+#define H4_24XX_GPMC_CONFIG2_0 0x000f0f01
+#define H4_24XX_GPMC_CONFIG3_0 0x00050502
+#define H4_24XX_GPMC_CONFIG4_0 0x0C060C06
#define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
+#endif
#define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
#define H4_24XX_GPMC_CONFIG1_1 0x00011000
@@ -90,18 +138,28 @@ typedef struct sdrc_data_s sdrc_data_t;
#endif
#ifdef PRCM_CONFIG_III /* L3 at 133MHz */
+#ifdef CFG_NAND_BOOT
+#define H4_24XX_GPMC_CONFIG1_0 0x0
+#define H4_24XX_GPMC_CONFIG2_0 0x00141400
+#define H4_24XX_GPMC_CONFIG3_0 0x00141400
+#define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
+#define H4_24XX_GPMC_CONFIG5_0 0x010C1414
+#define H4_24XX_GPMC_CONFIG6_0 0x00000A80
+#else
#define H4_24XX_GPMC_CONFIG1_0 0x3
-#define H4_24XX_GPMC_CONFIG2_0 0x001f1f01
-#define H4_24XX_GPMC_CONFIG3_0 0x001F1F00
-#define H4_24XX_GPMC_CONFIG4_0 0x16061606
+#define H4_24XX_GPMC_CONFIG2_0 0x00151501
+#define H4_24XX_GPMC_CONFIG3_0 0x00060602
+#define H4_24XX_GPMC_CONFIG4_0 0x10081008
#define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
+#define H4_24XX_GPMC_CONFIG6_0 0x000004c4
+#endif
#define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
#define H4_24XX_GPMC_CONFIG1_1 0x00011000
#define H4_24XX_GPMC_CONFIG2_1 0x001f1f01
-#define H4_24XX_GPMC_CONFIG3_1 0x001F1F00
-#define H4_24XX_GPMC_CONFIG4_1 0x1A061A06
-#define H4_24XX_GPMC_CONFIG5_1 0x041F1F1F
+#define H4_24XX_GPMC_CONFIG3_1 0x00080803
+#define H4_24XX_GPMC_CONFIG4_1 0x1C091C09
+#define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F
#define H4_24XX_GPMC_CONFIG6_1 0x000004C4
#define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24))
#endif
diff --git a/include/asm-arm/arch-arm1136/omap2420.h b/include/asm-arm/arch-arm1136/omap2420.h
index 357ad14..a2a9798 100644
--- a/include/asm-arm/arch-arm1136/omap2420.h
+++ b/include/asm-arm/arch-arm1136/omap2420.h
@@ -50,6 +50,7 @@
#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68)
#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C)
#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70)
+#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74)
#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78)
#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90)
#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94)
@@ -62,6 +63,8 @@
/* SMS */
#define OMAP2420_SMS_BASE 0x68008000
#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10)
+#define SMS_CLASS_ARB0 (OMAP2420_SMS_BASE+0xD0)
+# define BURSTCOMPLETE_GROUP7 BIT31
/* SDRC */
#define OMAP2420_SDRC_BASE 0x68009000
diff --git a/include/asm-arm/arch-arm1136/sys_info.h b/include/asm-arm/arch-arm1136/sys_info.h
index fe68ccc..ef301ba 100644
--- a/include/asm-arm/arch-arm1136/sys_info.h
+++ b/include/asm-arm/arch-arm1136/sys_info.h
@@ -39,6 +39,7 @@ typedef struct h4_system_data {
u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/
} h4_sys_data;
+#define SDR_DISCRETE 4
#define DDR_STACKED 3 /* stacked part on 2422 */
#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */
#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
diff --git a/include/asm-arm/arch-arm1136/sys_proto.h b/include/asm-arm/arch-arm1136/sys_proto.h
index 4a7612f..2cd8455 100644
--- a/include/asm-arm/arch-arm1136/sys_proto.h
+++ b/include/asm-arm/arch-arm1136/sys_proto.h
@@ -44,4 +44,10 @@ u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound);
u32 get_board_type(void);
void display_board_info(u32);
void update_mux(u32,u32);
+
+u32 running_in_sdram(void);
+u32 running_in_sram(void);
+u32 running_in_flash(void);
+u32 running_from_internal_boot(void);
+
#endif
diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h
index da68c1c..8516054 100644
--- a/include/configs/omap2420h4.h
+++ b/include/configs/omap2420h4.h
@@ -38,11 +38,20 @@
/*#define CONFIG_APTIX 1 #* define if on APTIX test chip */
/*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */
-#define PRCM_CONFIG_II 1
-#define CONFIG_PARTIAL_SRAM 1
+/* Clock config to target*/
+#define PRCM_CONFIG_II 1
+//#define PRCM_CONFIG_III 1
+
+/* Memory configuration on board */
+//#define CONFIG_OPTIMIZE_DDR 1
#include <asm/arch/omap2420.h> /* get chip and board defs */
+/* On H4, NOR and NAND flash are mutual exclusive.
+ Define this if you want to use NAND
+ */
+//#define CFG_NAND_BOOT
+
#ifdef CONFIG_APTIX
#define V_SCLK 1500000
#else
@@ -59,6 +68,7 @@
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
/*
* Size of malloc() pool
@@ -112,8 +122,11 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C)
-
+#ifdef CFG_NAND_BOOT
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_NAND | CFG_CMD_JFFS2)
+#else
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2)
+#endif
/* I'd like to get to these. Snap kernel loads if we make MMC go */
/* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_DHCP | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_I2C) */
@@ -122,6 +135,43 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
+/*
+ * Board NAND Info.
+ */
+#define CFG_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/
+
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0)
+#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0)
+#define READ_NAND(adr) (*(volatile u16 *)0x6800A084)
+#define NAND_WAIT_READY(nand) udelay(10)
+
+#define NAND_NO_RB 1
+
+#define CFG_NAND_WP
+#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
+#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
+
+
+#define NAND_CTL_CLRALE(nandptr)
+#define NAND_CTL_SETALE(nandptr)
+#define NAND_CTL_CLRCLE(nandptr)
+#define NAND_CTL_SETCLE(nandptr)
+#define NAND_DISABLE_CE(nand)
+#define NAND_ENABLE_CE(nand)
+
+
#define CONFIG_BOOTDELAY 3
#ifdef NFS_BOOT_DEFAULTS
@@ -203,11 +253,22 @@
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
+#ifdef CFG_NAND_BOOT
+#define CFG_ENV_IS_IN_NAND 1
+#define CFG_ENV_OFFSET 0x80000 /* environment starts here */
+#else
#define CFG_ENV_ADDR (CFG_FLASH_BASE + SZ_128K)
#define CFG_ENV_IS_IN_FLASH 1
+#endif
/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT (10*75*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT (10*75*CFG_HZ) /* Timeout for Flash Write */
+#define CFG_FLASH_ERASE_TOUT (30*75*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (30*75*CFG_HZ) /* Timeout for Flash Write */
+
+/* Flash banks JFFS2 should use */
+#define CFG_MAX_MTD_BANKS (CFG_MAX_FLASH_BANKS+CFG_MAX_NAND_DEVICE)
+#define CFG_JFFS2_MEM_NAND
+#define CFG_JFFS2_FIRST_BANK 1 /* use flash_info[1] */
+#define CFG_JFFS2_NUM_BANKS 1
#endif /* __CONFIG_H */
generated by cgit v1.1 at 2024-11-09 21:25:47 +0000