diff options
Diffstat (limited to 'include')
49 files changed, 2498 insertions, 164 deletions
diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h new file mode 100644 index 0000000..7cb8840 --- /dev/null +++ b/include/asm-ppc/fsl_law.h @@ -0,0 +1,80 @@ +#ifndef _FSL_LAW_H_ +#define _FSL_LAW_H_ + +#include <asm/io.h> + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define SET_LAW_ENTRY(idx, a, sz, trgt) \ + { .index = idx, .addr = a, .size = sz, .trgt_id = trgt } + +enum law_size { + LAW_SIZE_4K = 0xb, + LAW_SIZE_8K, + LAW_SIZE_16K, + LAW_SIZE_32K, + LAW_SIZE_64K, + LAW_SIZE_128K, + LAW_SIZE_256K, + LAW_SIZE_512K, + LAW_SIZE_1M, + LAW_SIZE_2M, + LAW_SIZE_4M, + LAW_SIZE_8M, + LAW_SIZE_16M, + LAW_SIZE_32M, + LAW_SIZE_64M, + LAW_SIZE_128M, + LAW_SIZE_256M, + LAW_SIZE_512M, + LAW_SIZE_1G, + LAW_SIZE_2G, + LAW_SIZE_4G, + LAW_SIZE_8G, + LAW_SIZE_16G, + LAW_SIZE_32G, +}; + +enum law_trgt_if { + LAW_TRGT_IF_PCI = 0x00, + LAW_TRGT_IF_PCI_2 = 0x01, +#ifndef CONFIG_MPC8641 + LAW_TRGT_IF_PCIE_1 = 0x02, +#endif +#ifndef CONFIG_MPC8572 + LAW_TRGT_IF_PCIE_3 = 0x03, +#endif + LAW_TRGT_IF_LBC = 0x04, + LAW_TRGT_IF_CCSR = 0x08, + LAW_TRGT_IF_DDR_INTRLV = 0x0b, + LAW_TRGT_IF_RIO = 0x0c, + LAW_TRGT_IF_DDR = 0x0f, + LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */ +}; +#define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR +#define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI +#define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI +#define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2 + +#ifdef CONFIG_MPC8641 +#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI +#endif + +#ifdef CONFIG_MPC8572 +#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI +#endif + +struct law_entry { + int index; + phys_addr_t addr; + enum law_size size; + enum law_trgt_if trgt_id; +}; + +extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id); +extern void disable_law(u8 idx); +extern void init_laws(void); + +/* define in board code */ +extern struct law_entry law_table[]; +extern int num_law_entries; +#endif diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 34ea295..5b21539 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -30,6 +30,7 @@ #include <asm/types.h> #include <asm/fsl_i2c.h> +#include <asm/mpc8xxx_spi.h> /* * Local Access Window @@ -384,20 +385,6 @@ typedef struct lbus83xx { } lbus83xx_t; /* - * Serial Peripheral Interface - */ -typedef struct spi83xx { - u32 mode; /* mode register */ - u32 event; /* event register */ - u32 mask; /* mask register */ - u32 com; /* command register */ - u8 res0[0x10]; - u32 tx; /* transmit register */ - u32 rx; /* receive register */ - u8 res1[0xFD8]; -} spi83xx_t; - -/* * DMA/Messaging Unit */ typedef struct dma83xx { @@ -627,7 +614,7 @@ typedef struct immap { u8 res3[0x900]; lbus83xx_t lbus; /* Local Bus Controller Registers */ u8 res4[0x1000]; - spi83xx_t spi; /* Serial Peripheral Interface */ + spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */ ios83xx_t ios; /* Sequencer */ @@ -661,7 +648,7 @@ typedef struct immap { u8 res2[0x900]; lbus83xx_t lbus; /* Local Bus Controller Registers */ u8 res3[0x1000]; - spi83xx_t spi; /* Serial Peripheral Interface */ + spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ u8 res4[0x80]; @@ -696,7 +683,7 @@ typedef struct immap { u8 res2[0x900]; lbus83xx_t lbus; /* Local Bus Controller Registers */ u8 res3[0x1000]; - spi83xx_t spi; /* Serial Peripheral Interface */ + spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ u8 res4[0x80]; @@ -741,7 +728,7 @@ typedef struct immap { u8 res2[0x900]; lbus83xx_t lbus; /* Local Bus Controller Registers */ u8 res3[0x1000]; - spi83xx_t spi; /* Serial Peripheral Interface */ + spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ u8 res4[0x80]; diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 45a4764..ec1ca53 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -418,6 +418,37 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define BOOKE_PAGESZ_256GB 14 #define BOOKE_PAGESZ_1TB 15 +#ifdef CONFIG_E500 +#ifndef __ASSEMBLY__ +extern void set_tlb(u8 tlb, u32 epn, u64 rpn, + u8 perms, u8 wimge, + u8 ts, u8 esel, u8 tsize, u8 iprot); +extern void disable_tlb(u8 esel); +extern void invalidate_tlb(u8 tlb); +extern void init_tlbs(void); + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ + { .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \ + .wimge = _wimge, .ts = _ts, .esel = _esel, .tsize = _sz, .iprot = _iprot } + +struct fsl_e_tlb_entry { + u8 tlb; + u32 epn; + u64 rpn; + u8 perms; + u8 wimge; + u8 ts; + u8 esel; + u8 tsize; + u8 iprot; +}; + +extern struct fsl_e_tlb_entry tlb_table[]; +extern int num_tlb_entries; +#endif +#endif + #if defined(CONFIG_MPC86xx) #define LAWBAR_BASE_ADDR 0x00FFFFFF #define LAWAR_TRGT_IF 0x01F00000 diff --git a/include/asm-ppc/mpc8xxx_spi.h b/include/asm-ppc/mpc8xxx_spi.h new file mode 100644 index 0000000..48b15e4 --- /dev/null +++ b/include/asm-ppc/mpc8xxx_spi.h @@ -0,0 +1,48 @@ +/* + * Freescale non-CPM SPI Controller + * + * Copyright 2008 Qstreams Networks, Inc. + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_MPC8XXX_SPI_H_ +#define _ASM_MPC8XXX_SPI_H_ + +#include <asm/types.h> + +#if defined(CONFIG_MPC834X) || \ + defined(CONFIG_MPC8313) || \ + defined(CONFIG_MPC8315) || \ + defined(CONFIG_MPC837X) + +typedef struct spi8xxx { + u8 res0[0x20]; /* 0x0-0x01f reserved */ + u32 mode; /* mode register */ + u32 event; /* event register */ + u32 mask; /* mask register */ + u32 com; /* command register */ + u32 tx; /* transmit register */ + u32 rx; /* receive register */ + u8 res1[0xFC8]; /* fill up to 0x1000 */ +} spi8xxx_t; + +#endif + +#endif /* _ASM_MPC8XXX_SPI_H_ */ diff --git a/include/asm-sh/cpu_sh3.h b/include/asm-sh/cpu_sh3.h new file mode 100644 index 0000000..6db38a2 --- /dev/null +++ b/include/asm-sh/cpu_sh3.h @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_CPU_SH3_H_ +#define _ASM_CPU_SH3_H_ + +/* cache control */ +#define CCR_CACHE_STOP 0x00000008 +#define CCR_CACHE_ENABLE 0x00000005 +#define CCR_CACHE_ICI 0x00000008 + +#define CACHE_OC_ADDRESS_ARRAY 0xf0000000 +#define CACHE_OC_WAY_SHIFT 13 +#define CACHE_OC_NUM_ENTRIES 256 +#define CACHE_OC_ENTRY_SHIFT 4 + +#if defined(CONFIG_CPU_SH7710) +#include <asm/cpu_sh7710.h> +#elif defined(CONFIG_CPU_SH7720) +#include <asm/cpu_sh7720.h> +#else +#error "Unknown SH3 variant" +#endif + +#endif /* _ASM_CPU_SH3_H_ */ diff --git a/include/asm-sh/cpu_sh7710.h b/include/asm-sh/cpu_sh7710.h new file mode 100644 index 0000000..e223f1c --- /dev/null +++ b/include/asm-sh/cpu_sh7710.h @@ -0,0 +1,64 @@ +#ifndef _ASM_CPU_SH7710_H_ +#define _ASM_CPU_SH7710_H_ + +#define CACHE_OC_NUM_WAYS 4 +#define CCR_CACHE_INIT 0x0000000D + +/* MMU and Cache control */ +#define MMUCR 0xFFFFFFE0 +#define CCR 0xFFFFFFEC + +/* PFC */ +#define PACR 0xA4050100 +#define PBCR 0xA4050102 +#define PCCR 0xA4050104 +#define PETCR 0xA4050106 + +/* Port Data Registers */ +#define PADR 0xA4050120 +#define PBDR 0xA4050122 +#define PCDR 0xA4050124 + +/* BSC */ +#define CMNCR 0xA4FD0000 +#define CS0BCR 0xA4FD0004 +#define CS2BCR 0xA4FD0008 +#define CS3BCR 0xA4FD000C +#define CS4BCR 0xA4FD0010 +#define CS5ABCR 0xA4FD0014 +#define CS5BBCR 0xA4FD0018 +#define CS6ABCR 0xA4FD001C +#define CS6BBCR 0xA4FD0020 +#define CS0WCR 0xA4FD0024 +#define CS2WCR 0xA4FD0028 +#define CS3WCR 0xA4FD002C +#define CS4WCR 0xA4FD0030 +#define CS5AWCR 0xA4FD0034 +#define CS5BWCR 0xA4FD0038 +#define CS6AWCR 0xA4FD003C +#define CS6BWCR 0xA4FD0040 + +/* SDRAM controller */ +#define SDCR 0xA4FD0044 +#define RTCSR 0xA4FD0048 +#define RTCNT 0xA4FD004C +#define RTCOR 0xA4FD0050 + +/* SCIF */ +#define SCSMR_0 0xA4400000 +#define SCIF0_BASE SCSMR_0 +#define SCSMR_0 0xA4410000 +#define SCIF1_BASE SCSMR_1 + +/* Timer */ +#define TSTR0 0xA412FE92 +#define TSTR TSTR0 +#define TCNT0 0xa412FE98 +#define TCR0 0xa412FE9C + +/* On chip oscillator circuits */ +#define FRQCR 0xA415FF80 +#define WTCNT 0xA415FF84 +#define WTCSR 0xA415FF86 + +#endif /* _ASM_CPU_SH7710_H_ */ diff --git a/include/asm-sh/cpu_sh7720.h b/include/asm-sh/cpu_sh7720.h new file mode 100644 index 0000000..bafb8de --- /dev/null +++ b/include/asm-sh/cpu_sh7720.h @@ -0,0 +1,207 @@ +/* + * (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * SH7720 Internal I/O register + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_CPU_SH7720_H_ +#define _ASM_CPU_SH7720_H_ + +#define CACHE_OC_NUM_WAYS 4 +#define CCR_CACHE_INIT 0x0000000B + +/* EXP */ +#define TRA 0xFFFFFFD0 +#define EXPEVT 0xFFFFFFD4 +#define INTEVT 0xFFFFFFD8 + +/* MMU */ +#define MMUCR 0xFFFFFFE0 +#define PTEH 0xFFFFFFF0 +#define PTEL 0xFFFFFFF4 +#define TTB 0xFFFFFFF8 + +/* CACHE */ +#define CCR 0xFFFFFFEC + +/* INTC */ +#define IPRF 0xA4080000 +#define IPRG 0xA4080002 +#define IPRH 0xA4080004 +#define IPRI 0xA4080006 +#define IPRJ 0xA4080008 +#define IRR5 0xA4080020 +#define IRR6 0xA4080022 +#define IRR7 0xA4080024 +#define IRR8 0xA4080026 +#define IRR9 0xA4080028 +#define IRR0 0xA4140004 +#define IRR1 0xA4140006 +#define IRR2 0xA4140008 +#define IRR3 0xA414000A +#define IRR4 0xA414000C +#define ICR1 0xA4140010 +#define ICR2 0xA4140012 +#define PINTER 0xA4140014 +#define IPRC 0xA4140016 +#define IPRD 0xA4140018 +#define IPRE 0xA414001A +#define ICR0 0xA414FEE0 +#define IPRA 0xA414FEE2 +#define IPRB 0xA414FEE4 + +/* BSC */ +#define BSC_BASE 0xA4FD0000 +#define CMNCR (BSC_BASE + 0x00) +#define CS0BCR (BSC_BASE + 0x04) +#define CS2BCR (BSC_BASE + 0x08) +#define CS3BCR (BSC_BASE + 0x0C) +#define CS4BCR (BSC_BASE + 0x10) +#define CS5ABCR (BSC_BASE + 0x14) +#define CS5BBCR (BSC_BASE + 0x18) +#define CS6ABCR (BSC_BASE + 0x1C) +#define CS6BBCR (BSC_BASE + 0x20) +#define CS0WCR (BSC_BASE + 0x24) +#define CS2WCR (BSC_BASE + 0x28) +#define CS3WCR (BSC_BASE + 0x2C) +#define CS4WCR (BSC_BASE + 0x30) +#define CS5AWCR (BSC_BASE + 0x34) +#define CS5BWCR (BSC_BASE + 0x38) +#define CS6AWCR (BSC_BASE + 0x3C) +#define CS6BWCR (BSC_BASE + 0x40) +#define SDCR (BSC_BASE + 0x44) +#define RTCSR (BSC_BASE + 0x48) +#define RTCNR (BSC_BASE + 0x4C) +#define RTCOR (BSC_BASE + 0x50) +#define SDMR2 (BSC_BASE + 0x4000) +#define SDMR3 (BSC_BASE + 0x5000) + +/* DMAC */ + +/* CPG */ +#define UCLKCR 0xA40A0008 +#define FRQCR 0xA415FF80 + +/* LOW POWER MODE */ + +/* TMU */ +#define TMU_BASE 0xA412FE90 +#define TSTR (TMU_BASE + 0x02) +#define TCOR0 (TMU_BASE + 0x04) +#define TCNT0 (TMU_BASE + 0x08) +#define TCR0 (TMU_BASE + 0x0C) +#define TCOR1 (TMU_BASE + 0x10) +#define TCNT1 (TMU_BASE + 0x14) +#define TCR1 (TMU_BASE + 0x18) +#define TCOR2 (TMU_BASE + 0x1C) +#define TCNT2 (TMU_BASE + 0x20) +#define TCR2 (TMU_BASE + 0x24) + +/* TPU */ +#define TPU_BASE 0xA4480000 +#define TPU_TSTR (TPU_BASE + 0x00) +#define TPU_TCR0 (TPU_BASE + 0x10) +#define TPU_TMDR0 (TPU_BASE + 0x14) +#define TPU_TIOR0 (TPU_BASE + 0x18) +#define TPU_TIER0 (TPU_BASE + 0x1C) +#define TPU_TSR0 (TPU_BASE + 0x20) +#define TPU_TCNT0 (TPU_BASE + 0x24) +#define TPU_TGRA0 (TPU_BASE + 0x28) +#define TPU_TGRB0 (TPU_BASE + 0x2C) +#define TPU_TGRC0 (TPU_BASE + 0x30) +#define TPU_TGRD0 (TPU_BASE + 0x34) +#define TPU_TCR1 (TPU_BASE + 0x50) +#define TPU_TMDR1 (TPU_BASE + 0x54) +#define TPU_TIOR1 (TPU_BASE + 0x58) +#define TPU_TIER1 (TPU_BASE + 0x5C) +#define TPU_TSR1 (TPU_BASE + 0x60) +#define TPU_TCNT1 (TPU_BASE + 0x64) +#define TPU_TGRA1 (TPU_BASE + 0x68) +#define TPU_TGRB1 (TPU_BASE + 0x6C) +#define TPU_TGRC1 (TPU_BASE + 0x70) +#define TPU_TGRD1 (TPU_BASE + 0x74) +#define TPU_TCR2 (TPU_BASE + 0x90) +#define TPU_TMDR2 (TPU_BASE + 0x94) +#define TPU_TIOR2 (TPU_BASE + 0x98) +#define TPU_TIER2 (TPU_BASE + 0x9C) +#define TPU_TSR2 (TPU_BASE + 0xB0) +#define TPU_TCNT2 (TPU_BASE + 0xB4) +#define TPU_TGRA2 (TPU_BASE + 0xB8) +#define TPU_TGRB2 (TPU_BASE + 0xBC) +#define TPU_TGRC2 (TPU_BASE + 0xC0) +#define TPU_TGRD2 (TPU_BASE + 0xC4) +#define TPU_TCR3 (TPU_BASE + 0xD0) +#define TPU_TMDR3 (TPU_BASE + 0xD4) +#define TPU_TIOR3 (TPU_BASE + 0xD8) +#define TPU_TIER3 (TPU_BASE + 0xDC) +#define TPU_TSR3 (TPU_BASE + 0xE0) +#define TPU_TCNT3 (TPU_BASE + 0xE4) +#define TPU_TGRA3 (TPU_BASE + 0xE8) +#define TPU_TGRB3 (TPU_BASE + 0xEC) +#define TPU_TGRC3 (TPU_BASE + 0xF0) +#define TPU_TGRD3 (TPU_BASE + 0xF4) + +/* CMT */ + +/* SIOF */ + +/* SCIF */ +#define SCIF0_BASE 0xA4430000 + +/* SIM */ + +/* IrDA */ + +/* IIC */ + +/* LCDC */ + +/* USBF */ + +/* MMCIF */ + +/* PFC */ +#define PFC_BASE 0xA4050100 +#define PACR (PFC_BASE + 0x00) +#define PBCR (PFC_BASE + 0x02) +#define PCCR (PFC_BASE + 0x04) +#define PDCR (PFC_BASE + 0x06) +#define PECR (PFC_BASE + 0x08) +#define PFCR (PFC_BASE + 0x0A) +#define PGCR (PFC_BASE + 0x0C) +#define PHCR (PFC_BASE + 0x0E) +#define PJCR (PFC_BASE + 0x10) +#define PKCR (PFC_BASE + 0x12) +#define PLCR (PFC_BASE + 0x14) +#define PMCR (PFC_BASE + 0x16) +#define PPCR (PFC_BASE + 0x18) +#define PRCR (PFC_BASE + 0x1A) +#define PSCR (PFC_BASE + 0x1C) +#define PTCR (PFC_BASE + 0x1E) +#define PUCR (PFC_BASE + 0x20) +#define PVCR (PFC_BASE + 0x22) +#define PSELA (PFC_BASE + 0x24) +#define PSELB (PFC_BASE + 0x26) +#define PSELC (PFC_BASE + 0x28) +#define PSELD (PFC_BASE + 0x2A) + +/* I/O Port */ + +/* H-UDI */ + +#endif /* _ASM_CPU_SH7720_H_ */ diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h index 03427ad..51fd10b 100644 --- a/include/asm-sh/io.h +++ b/include/asm-sh/io.h @@ -227,5 +227,32 @@ out: static inline void sync(void) { } + +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + #endif /* __KERNEL__ */ #endif /* __ASM_SH_IO_H */ diff --git a/include/commproc.h b/include/commproc.h index 6b1b4e8..32a3e1c 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -1448,7 +1448,9 @@ typedef struct scc_enet { */ #define PROFF_ENET PROFF_SCC2 #define CPM_CR_ENET CPM_CR_CH_SCC2 +#if (!defined(CONFIG_TK885D)) /* TK885D does not use SCC Ethernet */ #define SCC_ENET 1 +#endif #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index f7020b4..c14376e 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -63,6 +63,8 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ #define CONFIG_SYS_CLK_FREQ 33000000 diff --git a/include/configs/DU440.h b/include/configs/DU440.h new file mode 100644 index 0000000..4fb6921 --- /dev/null +++ b/include/configs/DU440.h @@ -0,0 +1,438 @@ +/* + * (C) Copyright 2008 + * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com + * + * based on the Sequoia board configuration by + * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + ********************************************************************** + * DU440.h - configuration for esd's DU440 board (Power PC440EPx) + ********************************************************************** + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_DU440 1 /* Board is esd DU440 */ +#define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */ + +#define CFG_BOOT_BASE_ADDR 0xf0000000 +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_NAND0_ADDR 0xd0000000 /* NAND Flash */ +#define CFG_NAND1_ADDR 0xd0100000 /* NAND Flash */ +#define CFG_OCM_BASE 0xe0010000 /* ocm */ +#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 +#define CFG_PCI_IOBASE 0xe8000000 + + +/* Don't change either of these */ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ + +#define CFG_USB2D0_BASE 0xe0000100 +#define CFG_USB_DEVICE 0xe0000000 +#define CFG_USB_HOST 0xe0000400 + +/* + * Initial RAM & stack pointer + */ +/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ +#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ +#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ + +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Serial Port + */ +/* TODO: external clock oscillator will be removed */ +#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/* + * Video Port + */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_SMI_LYNXEM +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */ +#define CFG_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img */ +#define CFG_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */ +#define CFG_CONSOLE_IS_IN_ENV +#define CFG_ISA_IO CFG_PCI_IOBASE + +/* + * Environment + */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */ + +/* + * FLASH related + */ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +/* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */ +#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ + +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_OFFSET 0 /* environment starts at */ + /* the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */ +#endif + +/* + * DDR SDRAM + */ +#define CFG_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */ +#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ +#if 0 +#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */ +#endif +#define CONFIG_DDR_ECC /* Use ECC when available */ +#define SPD_EEPROM_ADDRESS {0x50} +#define CONFIG_PROG_SDRAM_TLB + +/* + * I2C + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CONFIG_I2C_CMD_TREE 1 +#define CONFIG_I2C_MULTI_BUS 1 + +#define CFG_SPD_BUS_NUM 0 +#define IIC1_MCP3021_ADDR 0x4d +#define IIC1_USB2507_ADDR 0x2c +#ifdef CONFIG_I2C_MULTI_BUS +#define CFG_I2C_NOPROBES {{1, IIC1_USB2507_ADDR}} +#endif +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR 0x54 +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 5 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 + +#define CFG_EEPROM_WREN 1 +#define CFG_I2C_BOOT_EEPROM_ADDR 0x52 + +/* + * standard dtt sensor configuration - bottom bit will determine local or + * remote sensor of the TMP401 + */ +#define CONFIG_DTT_SENSORS { 0, 1 } + +/* + * The PMC440 uses a TI TMP401 temperature sensor. This part + * is basically compatible to the ADM1021 that is supported + * by U-Boot. + * + * - i2c addr 0x4c + * - conversion rate 0x02 = 0.25 conversions/second + * - ALERT ouput disabled + * - local temp sensor enabled, min set to 0 deg, max set to 70 deg + * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg + */ +#define CONFIG_DTT_ADM1021 +#define CFG_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} } + +/* + * RTC stuff + */ +#define CONFIG_RTC_DS1338 +#define CFG_I2C_RTC_ADDR 0x68 + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethrotate=no\0" \ + "hostname=du440\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_self=run ramargs addip addtty optargs;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \ + "bootm\0" \ + "rootpath=/tftpboot/du440/target_root_du440\0" \ + "img=/tftpboot/du440/uImage\0" \ + "kernel_addr=FFC00000\0" \ + "ramdisk_addr=FFE00000\0" \ + "initrd_high=30000000\0" \ + "load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \ + "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ + "cp.b 100000 FFFA0000 60000\0" \ + "" +#if 0 +#define CONFIG_BOOTCOMMAND "run flash_self" +#endif + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#ifndef __ASSEMBLY__ +int du440_phy_addr(int devnum); +#endif + +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_GIGE 1 /* Include GbE detection */ + +#define CONFIG_HAS_ETH0 +#define CFG_RX_ETH_BUFFER 128 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR du440_phy_addr(1) + +/* + * USB + */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_USB_STORAGE +#define CFG_OHCI_BE_CONTROLLER + +#define CFG_USB_OHCI_CPU_INIT 1 +#define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST +#define CFG_USB_OHCI_SLOT_NAME "du440" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 + +/* Comment this out to enable USB 1.1 device */ +#define USB_2_0_DEVICE + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#include <config_cmd_default.h> + +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DTT +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM + +#define CONFIG_SUPPORT_VFAT + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * PCI stuff + */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ + +/* Board-specific PCI */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * External Bus Controller (EBC) Setup + */ +#define CFG_FLASH CFG_FLASH_BASE + +#define CFG_CPLD_BASE 0xC0000000 +#define CFG_CPLD_RANGE 0x00000010 +#define CFG_DUMEM_BASE 0xC0100000 +#define CFG_DUMEM_RANGE 0x00100000 +#define CFG_DUIO_BASE 0xC0200000 +#define CFG_DUIO_RANGE 0x00010000 + +#define CFG_NAND0_CS 2 /* NAND chip connected to CSx */ +#define CFG_NAND1_CS 3 /* NAND chip connected to CSx */ +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x04017200 +#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000) + +/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */ +#define CFG_EBC_PB1AP 0x018003c0 +#define CFG_EBC_PB1CR (CFG_CPLD_BASE | 0x18000) + +/* Memory Bank 2 (NAND-FLASH) initialization */ +#define CFG_EBC_PB2AP 0x018003c0 +#define CFG_EBC_PB2CR (CFG_NAND0_ADDR | 0x1c000) + +/* Memory Bank 3 (NAND-FLASH) initialization */ +#define CFG_EBC_PB3AP 0x018003c0 +#define CFG_EBC_PB3CR (CFG_NAND1_ADDR | 0x1c000) + +/* Memory Bank 4 (DUMEM, 1MB) initialization */ +#define CFG_EBC_PB4AP 0x018053c0 +#define CFG_EBC_PB4CR (CFG_DUMEM_BASE | 0x18000) + +/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */ +#define CFG_EBC_PB5AP 0x018053c0 +#define CFG_EBC_PB5CR (CFG_DUIO_BASE | 0x18000) + +/* + * NAND FLASH + */ +#define CFG_MAX_NAND_DEVICE 2 +#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ +#define CFG_NAND_BASE_LIST {CFG_NAND0_ADDR + CFG_NAND0_CS, \ + CFG_NAND1_ADDR + CFG_NAND1_CS} + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +#if 0 +#define CONFIG_SHOW_ACTIVITY 1 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 455bbe0..f12a3e6 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -76,10 +76,10 @@ * seem to have the SPD connected to I2C. */ #define CFG_DDR_SIZE 128 /* MB */ -#define CFG_DDR_CONFIG ( CSCONFIG_EN | CSCONFIG_AP \ - | 0x00040000 /* TODO */ \ +#define CFG_DDR_CONFIG ( CSCONFIG_EN \ + | 0x00010000 /* TODO */ \ | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) - /* 0x80840102 */ + /* 0x80010102 */ #define CFG_DDR_TIMING_3 0x00000000 #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ @@ -92,25 +92,25 @@ | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) /* 0x00220802 */ #define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ - | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ + | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ - | (13 << TIMING_CFG1_REFREC_SHIFT ) \ + | (10 << TIMING_CFG1_REFREC_SHIFT ) \ | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) - /* 0x3935d322 */ -#define CFG_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \ - | (31 << TIMING_CFG2_CPO_SHIFT ) \ + /* 0x3835a322 */ +#define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ + | ( 5 << TIMING_CFG2_CPO_SHIFT ) \ | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ - | (10 << TIMING_CFG2_FOUR_ACT_SHIFT) ) - /* 0x0f9048ca */ /* P9-45,may need tuning */ -#define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \ - | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) - /* 0x03200064 */ + | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) ) + /* 0x129048c6 */ /* P9-45,may need tuning */ +#define CFG_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \ + | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) + /* 0x05100500 */ #if defined(CONFIG_DDR_2T_TIMING) #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ | SDRAM_CFG_SDRAM_TYPE_DDR2 \ @@ -124,9 +124,9 @@ #endif #define CFG_SDRAM_CFG2 0x00401000; /* set burst length to 8 for 32-bit data path */ -#define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \ - | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) - /* 0x44400232 */ +#define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ + | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) ) + /* 0x44480632 */ #define CFG_DDR_MODE_2 0x8000C000; #define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h new file mode 100644 index 0000000..ad2305c --- /dev/null +++ b/include/configs/MPC8315ERDB.h @@ -0,0 +1,547 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * Dave Liu <daveliu@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_MPC83XX 1 /* MPC83xx family */ +#define CONFIG_MPC831X 1 /* MPC831x CPU family */ +#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ +#define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */ + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +/* + * Hardware Reset Configuration Word + * if CLKIN is 66.66MHz, then + * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz + */ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_SVCOD_DIV_2 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_CORE_TO_CSB_3X1) +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) + +/* + * System IO Config + */ +#define CFG_SICRH 0x00000000 +#define CFG_SICRL 0x00000000 /* 3.3V, no delay */ + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ + +/* + * IMMR new address + */ +#define CFG_IMMR 0xE0000000 + +/* + * Arbiter Setup + */ +#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ +#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ +#define CFG_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +#define CFG_DDRCDR_VALUE ( DDRCDR_EN \ + | DDRCDR_PZ_LOZ \ + | DDRCDR_NZ_LOZ \ + | DDRCDR_ODT \ + | DDRCDR_Q_DRN ) + /* 0x7b880001 */ +/* + * Manually set up DDR parameters + * consist of two chips HY5PS12621BFP-C4 from HYNIX + */ +#define CFG_DDR_SIZE 128 /* MB */ +#define CFG_DDR_CS0_BNDS 0x00000007 +#define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \ + | 0x00010000 /* ODT_WR to CSn */ \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) + /* 0x80010102 */ +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ + | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ + | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) + /* 0x00220802 */ +#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ + | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ + | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ + | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ + | ( 6 << TIMING_CFG1_REFREC_SHIFT ) \ + | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \ + | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ + | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) + /* 0x39356222 */ +#define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ + | ( 4 << TIMING_CFG2_CPO_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ + | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ + | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ + | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) ) + /* 0x121048c7 */ +#define CFG_DDR_INTERVAL ( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \ + | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) + /* 0x03600100 */ +#define CFG_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_32_BE ) + /* 0x43080000 */ +#define CFG_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ +#define CFG_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \ + | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) + /* ODT 150ohm CL=3, AL=1 on SDRAM */ +#define CFG_DDR_MODE2 0x00000000 + +/* + * Memory test + */ +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00040000 /* memtest region */ +#define CFG_MEMTEST_END 0x00140000 + +/* + * The reserved memory + */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) +#define CFG_LBC_LBCR 0x00040000 + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CFG_FLASH_SIZE 8 /* FLASH size is 8M */ + +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */ + +#define CFG_BR0_PRELIM ( CFG_FLASH_BASE /* Flash Base address */ \ + | (2 << BR_PS_SHIFT) /* 16 bit port size */ \ + | BR_V ) /* valid */ +#define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_0b11 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX \ + | OR_GPCM_EHTR \ + | OR_GPCM_EAD ) + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors and 8 8KB top sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +/* + * NAND Flash on the Local Bus + */ +#define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE + +#define CFG_BR1_PRELIM ( CFG_NAND_BASE \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V ) /* valid */ +#define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR ) + /* 0xFFFF8396 */ + +#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE +#define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_FSL_I2C +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 + +/* + * Board info - revision and where boot from + */ +#define CFG_I2C_PCF8574A_ADDR 0x39 + +/* + * Config on-board RTC + */ +#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI_MEM_BASE 0x80000000 +#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE +#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_MMIO_BASE 0x90000000 +#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE +#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_IO_BASE 0xE0300000 +#define CFG_PCI_IO_PHYS 0xE0300000 +#define CFG_PCI_IO_SIZE 0x100000 /* 1M */ + +#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE +#define CFG_PCI_SLV_MEM_BUS 0x00000000 +#define CFG_PCI_SLV_MEM_SIZE 0x80000000 + +#define CONFIG_PCI +#define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_EEPRO100 +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +/* + * TSEC + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) + +/* + * TSEC ethernet configuration + */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: eTSEC[0-1] */ +#define CONFIG_ETHPRIME "eTSEC1" + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PCI + +#if defined(CFG_RAMBOOT) + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS +#endif + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if defined(CONFIG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) +#define CFG_HID2 HID2_HBE + +/* + * MMU Setup + */ + +/* DDR: cache cacheable */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP) +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U + +/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ +#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT1U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CFG_IBAT2L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT2U (CFG_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP) +#define CFG_DBAT2L (CFG_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U CFG_IBAT2U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CFG_IBAT3L (CFG_INIT_RAM_ADDR | BATL_PP_10) +#define CFG_IBAT3U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* PCI MEM space: cacheable */ +#define CFG_IBAT4L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT4U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U + +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT5L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U + +#define CFG_IBAT6L 0 +#define CFG_IBAT6U 0 +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U + +#define CFG_IBAT7L 0 +#define CFG_IBAT7U 0 +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_ETHADDR 04:00:00:00:00:0A +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 04:00:00:00:00:0B +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=1000000\0" \ + "ramdiskfile=ramfs.83xx\0" \ + "fdtaddr=400000\0" \ + "fdtfile=mpc8315erdb.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 4ea8709..295e785 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -321,7 +321,7 @@ * QE UEC ethernet configuration */ #define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "Freescale GETH" +#define CONFIG_ETHPRIME "FSL UEC0" #define CONFIG_UEC_ETH1 /* ETH3 */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 25ac58c..6c0e68a 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -377,7 +377,7 @@ * QE UEC ethernet configuration */ #define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "Freescale GETH" +#define CONFIG_ETHPRIME "FSL UEC0" #define CONFIG_UEC_ETH1 /* ETH3 */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 437a9a5..07f2f30 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -355,6 +355,15 @@ #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 +/* SPI */ +#define CONFIG_HARD_SPI /* SPI with hardware support */ +#undef CONFIG_SOFT_SPI /* SPI bit-banged */ + +/* GPIOs. Used as SPI chip selects */ +#define CFG_GPIO1_PRELIM +#define CFG_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ +#define CFG_GPIO1_DAT 0xC0000000 /* Both are active LOW */ + /* TSEC */ #define CFG_TSEC1_OFFSET 0x24000 #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index fdacb90..168ca2a 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -405,7 +405,7 @@ * QE UEC ethernet configuration */ #define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "Freescale GETH" +#define CONFIG_ETHPRIME "FSL UEC0" #define CONFIG_PHY_MODE_NEED_CHANGE #define CONFIG_UEC_ETH1 /* GETH1 */ @@ -466,6 +466,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_ASKENV +#define CONFIG_CMD_SDRAM #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index 0f6f8f1..83a4b1e 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -282,7 +282,7 @@ * QE UEC ethernet configuration */ #define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "Freescale GETH" +#define CONFIG_ETHPRIME "FSL UEC0" #define CONFIG_UEC_ETH1 /* GETH1 */ @@ -387,15 +387,6 @@ #define CFG_HID2 HID2_HBE /* - * Cache Config - */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ -#endif - -/* * MMU Setup */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h new file mode 100644 index 0000000..2da4f29 --- /dev/null +++ b/include/configs/MPC837XERDB.h @@ -0,0 +1,596 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Kevin Lam <kevin.lam@freescale.com> + * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC837X 1 /* MPC837X CPU specific */ +#define CONFIG_MPC837XERDB 1 + +#define CONFIG_PCI 1 + +/* + * System Clock Setup + */ +#ifdef CONFIG_PCISLAVE +#define CONFIG_83XX_PCICLK 66666667 /* in HZ */ +#else +#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ +#define CONFIG_83XX_GENERIC_PCI 1 +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN +#endif + +/* + * Hardware Reset Configuration Word + */ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_SVCOD_DIV_2 |\ + HRCWL_CSB_TO_CLKIN_5X1 |\ + HRCWL_CORE_TO_CSB_2X1) + +#ifdef CONFIG_PCISLAVE +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_AGENT |\ + HRCWH_PCI1_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LDP_CLEAR) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LDP_CLEAR) +#endif + +/* System performance - define the value i.e. CFG_XXX +*/ + +/* Arbiter Configuration Register */ +#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ + +/* System Priority Control Regsiter */ +#define CFG_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ + +/* System Clock Configuration Register */ +#define CFG_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ +#define CFG_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ +#define CFG_SCCR_SATACM SCCR_SATACM_1 /* SATA1-4 clock mode (0-3) */ + +/* + * System IO Config + */ +#define CFG_SICRH 0x08200000 +#define CFG_SICRL 0x00000000 + +/* + * Output Buffer Impedance + */ +#define CFG_OBIR 0x30100000 + +/* + * IMMR new address + */ +#define CFG_IMMR 0xE0000000 + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_CLK_CNTL 0x03000000 +#define CFG_83XX_DDR_USES_CS0 + +#define CFG_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) + +#undef CONFIG_DDR_ECC /* support DDR ECC function */ +#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ + +#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ + +/* + * Manually set up DDR parameters + */ +#define CFG_DDR_SIZE 256 /* MB */ +#define CFG_DDR_CS0_BNDS 0x0000000f +#define CFG_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) + +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00220802 */ + /* 0x00260802 */ /* DDR400 */ +#define CFG_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (7 << TIMING_CFG1_CASLAT_SHIFT) \ + | (13 << TIMING_CFG1_REFREC_SHIFT) \ + | (3 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x3935d322 */ + /* 0x3937d322 */ +#define CFG_DDR_TIMING_2 0x02984cc8 + +#define CFG_DDR_INTERVAL ((1545 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (256 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x06090100 */ + +#if defined(CONFIG_DDR_2T_TIMING) +#define CFG_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ + | SDRAM_CFG_2T_EN \ + | SDRAM_CFG_DBW_32) +#else +#define CFG_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT) + /* 0x43000000 */ +#endif +#define CFG_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ +#define CFG_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0442 << SDRAM_MODE_SD_SHIFT)) + /* 0x04400442 */ /* DDR400 */ +#define CFG_DDR_MODE2 0x00000000; + +/* + * Memory test + */ +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00040000 /* memtest region */ +#define CFG_MEMTEST_END 0x0ef70010 + +/* + * The reserved memory + */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) +#define CFG_LBC_LBCR 0x00000000 + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CFG_FLASH_SIZE 8 /* max FLASH size is 32M */ + +#define CFG_FLASH_EMPTY_INFO /* display empty sectors */ +#define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ + +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) /* valid */ +#define CFG_OR0_PRELIM (0xFF800000 /* 8 MByte */ \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_9 \ + | OR_GPCM_EHTR \ + | OR_GPCM_EAD) + /* 0xFF806FF7 TODO SLOW 8 MB flash size */ + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_VSC7385_BASE 0xF0000000 + +/* VSC7385 Gigabit Switch support */ +#define CONFIG_VSC7385_ENET +#define CFG_BR2_PRELIM 0xf0000801 /* Base address */ +#define CFG_OR2_PRELIM 0xfffe09ff /* 128K bytes*/ +#define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE /* Access Base */ +#define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 + +/* + * Config on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI_MEM_BASE 0x80000000 +#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE +#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_MMIO_BASE 0x90000000 +#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE +#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_IO_BASE 0xE0300000 +#define CFG_PCI_IO_PHYS 0xE0300000 +#define CFG_PCI_IO_SIZE 0x100000 /* 1M */ + +#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE +#define CFG_PCI_SLV_MEM_BUS 0x00000000 +#define CFG_PCI_SLV_MEM_SIZE 0x80000000 + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ +#endif /* CONFIG_PCI */ + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +/* + * TSEC + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) + +/* + * TSEC ethernet configuration + */ +#define CONFIG_GMII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 0x1c +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE+CFG_MONITOR_LEN) + #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ + #define CFG_ENV_SIZE 0x4000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE-0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#endif + +#if defined(CFG_RAMBOOT) +#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_LOADS +#endif + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if defined(CONFIG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CFG_HID2 HID2_HBE + +/* + * MMU Setup + */ + +/* DDR: cache cacheable */ +#define CFG_SDRAM_LOWER CFG_SDRAM_BASE +#define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000) + +#define CFG_IBAT0L (CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U + +#define CFG_IBAT1L (CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ +#define CFG_IBAT2L (CFG_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U + +/* L2 Switch: cache-inhibit and guarded */ +#define CFG_IBAT3L (CFG_VSC7385_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT3U (CFG_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CFG_IBAT4L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT4U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_DBAT4L (CFG_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4U CFG_IBAT4U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) +#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else +#define CFG_IBAT6L (0) +#define CFG_IBAT6U (0) +#define CFG_IBAT7L (0) +#define CFG_IBAT7U (0) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */ +#define CONFIG_ETHADDR 00:04:9f:ef:04:01 +#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ +#define CONFIG_ETH1ADDR 00:04:9f:ef:04:02 + +#define CONFIG_IPADDR 10.0.0.2 +#define CONFIG_SERVERIP 10.0.0.1 +#define CONFIG_GATEWAYIP 10.0.0.1 +#define CONFIG_NETMASK 255.0.0.0 +#define CONFIG_NETDEV eth1 + +#define CONFIG_HOSTNAME mpc837x_rdb +#define CONFIG_ROOTPATH /nfsroot +#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ +#define CONFIG_FDTFILE mpc837x_rdb.dtb + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ +#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ +#define CONFIG_BAUDRATE 115200 + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftp $loadaddr $uboot;" \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "fdtaddr=400000\0" \ + "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ + "ramdiskaddr=1000000\0" \ + "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \ + "console=ttyS0\0" \ + "setbootargs=setenv bootargs " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ + "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv rootdev /dev/nfs;" \ + "run setbootargs;" \ + "run setipargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv rootdev /dev/ram;" \ + "run setbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#undef MK_STR +#undef XMK_STR + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index afce7fb..5ea7b25 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -55,6 +55,7 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * sysclk for MPC85xx diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 2868dcb..bf64f27 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -43,6 +43,8 @@ #undef CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + /* Using Localbus SDRAM to emulate flash before we can program the flash, * normally you only need a flash-boot image(u-boot.bin),if unsure undef this. * Not availabe for EVAL board diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index c83382f..7334088 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -47,6 +47,7 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * When initializing flash, if we cannot find the manufacturer ID, diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 5a96db5..a894209 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -42,6 +42,8 @@ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 90beb25..a3db9f4 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -55,6 +55,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * When initializing flash, if we cannot find the manufacturer ID, diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 76d673c..93877ae 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -47,6 +47,7 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * When initializing flash, if we cannot find the manufacturer ID, diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 5f10555..08884b3 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -52,6 +52,7 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * sysclk for MPC85xx diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 2b089d9..a12d193 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -49,6 +49,7 @@ /*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * When initializing flash, if we cannot find the manufacturer ID, diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index eb6ccb6..a53953c 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -141,6 +141,9 @@ #endif #define CFG_ID_EEPROM +#ifdef CFG_ID_EEPROM +#define CONFIG_ID_EEPROM +#endif #define ID_EEPROM_ADDR 0x57 @@ -312,11 +315,8 @@ #define CONFIG_CMD_NET #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_RTL8139 -#define CONFIG_SK98 -#define CONFIG_EEPRO100 -#define CONFIG_TULIP -#ifdef CONFIG_TULIP +#define CONFIG_ULI526X +#ifdef CONFIG_ULI526X #define CONFIG_ETHADDR 00:E0:0C:00:00:01 #endif @@ -493,6 +493,7 @@ * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 7f485c6..985182f 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -152,6 +152,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif #define CFG_ID_EEPROM 1 +#ifdef CFG_ID_EEPROM +#define CONFIG_ID_EEPROM +#endif #define ID_EEPROM_ADDR 0x57 /* @@ -552,6 +555,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ diff --git a/include/configs/PM854.h b/include/configs/PM854.h index f0d0399..819bee7 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -51,6 +51,7 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_MEM_INIT_VALUE 0xDEADBEEF +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * sysclk for MPC85xx diff --git a/include/configs/PM856.h b/include/configs/PM856.h index ae2645c..8902f42 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -51,6 +51,7 @@ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_MEM_INIT_VALUE 0xDEADBEEF +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * sysclk for MPC85xx diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 67bf4b1..e8b405a 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -385,7 +385,7 @@ *----------------------------------------------------------------------*/ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -503,7 +503,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 3ca85b8..2bbfe9a 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -56,6 +56,7 @@ #undef CONFIG_PCI /* pci ethernet support */ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/TK885D.h b/include/configs/TK885D.h index 761a352..c43fef6 100644 --- a/include/configs/TK885D.h +++ b/include/configs/TK885D.h @@ -64,6 +64,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_EXTRA_ENV_SETTINGS \ + "ethprime=FEC ETHERNET\0" \ + "ethact=FEC ETHERNET\0" \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ @@ -77,7 +79,8 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM885D/uImage\0" \ + "bootfile=/tftpboot/tk885d/uImage\0" \ + "u-boot=/tftpboot/tk885d/u-boot.bin\0" \ "kernel_addr=40080000\0" \ "ramdisk_addr=40180000\0" \ "load=tftp 200000 ${u-boot}\0" \ @@ -254,7 +257,7 @@ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index f3b1a53..dd0654b 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -50,6 +50,8 @@ #define CONFIG_CPM2 1 /* has CPM2 */ #endif +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + /* * sysclk for MPC85xx * diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index a4de552..ce458ae5 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -295,7 +295,7 @@ * to 0xFFFF, watchdog timeouts after about 64s. For details refer * to chapter 36 of the MPC5121e Reference Manual. */ -#define CONFIG_WATCHDOG /* enable watchdog */ +/* #define CONFIG_WATCHDOG */ /* enable watchdog */ #define CFG_WATCHDOG_VALUE 0xFFFF /* @@ -306,9 +306,9 @@ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #ifdef CONFIG_CMD_KGDB - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif @@ -340,8 +340,8 @@ * * Boot Flags */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ @@ -351,7 +351,7 @@ /* * Environment Configuration */ -#define CONFIG_ENV_OVERWRITE +#define CONFIG_TIMESTAMP #define CONFIG_HOSTNAME ads5121 #define CONFIG_BOOTFILE ads5121/uImage diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h index b43b228..cb51406 100644 --- a/include/configs/hcu4.h +++ b/include/configs/hcu4.h @@ -46,8 +46,8 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ +#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ @@ -67,7 +67,7 @@ #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR /*----------------------------------------------------------------------- * Serial Port @@ -82,8 +82,8 @@ * set Linux BASE_BAUD to 403200. */ #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ -#undef CONFIG_SERIAL_MULTI /* needed to be able to define - CONFIG_SERIAL_SOFTWARE_FIFO */ +#define CONFIG_SERIAL_MULTI 1 +/* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO */ #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CFG_BASE_BAUD 691200 @@ -101,12 +101,23 @@ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} /*----------------------------------------------------------------------- + * Flash + *----------------------------------------------------------------------*/ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ #undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_IS_IN_FLASH #undef CFG_ENV_IS_NOWHERE #ifdef CFG_ENV_IS_IN_EEPROM @@ -120,7 +131,7 @@ /* Put the environment in Flash */ #define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) @@ -158,7 +169,7 @@ /* Setup some board specific values for the default environment variables */ #define CONFIG_HOSTNAME hcu4 -#define CONFIG_IPADDR 172.25.1.42 +#define CONFIG_IPADDR 172.25.1.99 #define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ #define CONFIG_OVERWRITE_ETHADDR_ONCE #define CONFIG_SERVERIP 172.25.1.3 @@ -180,21 +191,17 @@ "rootpath=/home/diagnose/eldk/ppc_4xx\0" \ "bootfile=/tftpboot/hcu4/uImage\0" \ "load=tftp 100000 hcu4/u-boot.bin\0" \ - "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \ - "cp.b 100000 FFFa0000 60000\0" \ + "update=protect off FFFB0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \ + "cp.b 100000 FFFB0000 50000\0" \ "upd=run load;run update\0" \ "vx=tftp ${loadaddr} hcu4_vx_rom;" \ - "setenv bootargs emac(0,0)hcu4_vx_rom e=${ipaddr} " \ - " h=${serverip} u=dpu pw=netstal8752 tn=hcu4 f=0x3008;" \ + "vx=tftp ${loadaddr} hcu4/hcu4_vx_rom;" \ + "setenv bootargs emac(0,0)c:hcu4/hcu4_vx_rom e=${ipaddr} " \ "bootvx ${loadaddr}\0" \ "" #define CONFIG_BOOTCOMMAND "run vx" -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -202,10 +209,10 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_HAS_ETH0 -#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & desC */ /* * BOOTP options @@ -221,7 +228,6 @@ #include <config_cmd_default.h> #define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP #define CONFIG_CMD_CACHE #define CONFIG_CMD_DHCP #define CONFIG_CMD_DIAG @@ -241,15 +247,30 @@ #define CONFIG_SPD_EEPROM 1 #define SPD_EEPROM_ADDRESS 0x50 +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_UART | \ + CFG_POST_I2C | \ + CFG_POST_CACHE | \ + CFG_POST_ETHER | \ + CFG_POST_SPR) + +#define CFG_POST_UART_TABLE {UART0_BASE} +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#undef CONFIG_LOGBUFFER +#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */ +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ + /*----------------------------------------------------------------------- * Miscellaneous configurable options *----------------------------------------------------------------------*/ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ @@ -266,47 +287,40 @@ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x02005400 -#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ +#define CFG_EBC_CFG 0x98400000 -#define CFG_EBC_PB1AP 0x03041200 -#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */ +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x02005400 +#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ -#define CFG_EBC_PB2AP 0x02054500 -#define CFG_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */ +#define CFG_EBC_PB1AP 0x03041200 +#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */ -#define CFG_EBC_PB3AP 0x01840300 -#define CFG_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */ +#define CFG_EBC_PB2AP 0x02054500 +#define CFG_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */ -#define CFG_EBC_PB4AP 0x01800300 -#define CFG_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */ +#define CFG_EBC_PB3AP 0x01840300 +#define CFG_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */ -#define CFG_GPIO0_TCR 0x7ffe0000 /* GPIO value */ +#define CFG_EBC_PB4AP 0x01800300 +#define CFG_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */ + +#define CFG_GPIO0_OR 0xF27FFFFF /* GPIO value */ +#define CFG_GPIO0_TCR 0x7FFE0000 /* GPIO value */ +#define CFG_GPIO0_ODR 0x00E897FC /* GPIO value */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */ /* Init Memory Controller: * @@ -326,8 +340,8 @@ * * Boot Flags */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ #define CFG_HUSH_PARSER /* use "hush" command parser */ #ifdef CFG_HUSH_PARSER @@ -338,4 +352,9 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index 1214bc3..d66c47a 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -48,14 +48,16 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ +#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ +#define CFG_TLB_FOR_BOOT_FLASH 3 #define CFG_BOOT_BASE_ADDR 0xfff00000 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ #define CFG_MONITOR_BASE TEXT_BASE #define CFG_OCM_BASE 0xe0010000 /* ocm */ +#define CFG_OCM_DATA_ADDR CFG_OCM_BASE #define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 @@ -78,14 +80,15 @@ #define CFG_INIT_RAM_END (4 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ #define CONFIG_BAUDRATE 9600 -#undef CONFIG_SERIAL_MULTI /* needed to be able to define +#define CONFIG_SERIAL_MULTI 1 +/* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO, but CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */ /* Size (bytes) of interrupt driven serial port buffer. @@ -95,6 +98,7 @@ #undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CONFIG_UART1_CONSOLE +#undef CONFIG_CMD_HWFLOW #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} @@ -103,8 +107,8 @@ *----------------------------------------------------------------------*/ #undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_IN_EEPROM #undef CFG_ENV_IS_NOWHERE #ifdef CFG_ENV_IS_IN_EEPROM @@ -117,22 +121,28 @@ #ifdef CFG_ENV_IS_IN_FLASH /* Put the environment in Flash */ -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + #endif /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */ -#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ -#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */ -#define CONFIG_DDR_ECC 1 /* enable ECC */ +#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */ +#define CFG_DDR_CACHED_ADDR 0x50000000 /* setup 2nd TLB cached here */ +#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */ +#define CONFIG_DDR_ECC 1 /* enable ECC */ + +/* Following two definitions must be kept in sync with config.h of vxWorks */ +#define USER_RESERVED_MEM ( 0) /* in kB */ +#define PM_RESERVED_MEM ( 64) /* in kB: pmLib reserved area size */ +#define CONFIG_PRAM ( USER_RESERVED_MEM + PM_RESERVED_MEM ) /*----------------------------------------------------------------------- * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the @@ -165,8 +175,8 @@ /* Setup some board specific values for the default environment variables */ #define CONFIG_HOSTNAME hcu5 -#define CONFIG_IPADDR 172.25.1.42 -#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ +#define CONFIG_IPADDR 172.25.1.99 +#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ #define CONFIG_OVERWRITE_ETHADDR_ONCE #define CONFIG_SERVERIP 172.25.1.3 @@ -187,21 +197,27 @@ "bootfile=hcu5/uImage\0" \ "rootpath=/home/hcu/eldk/ppc_4xxFP\0" \ "load=tftp 100000 hcu5/u-boot.bin\0" \ - "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \ - "cp.b 100000 FFFa0000 60000\0" \ + "update=protect off FFFb0000 FFFFFFFF;era FFFb0000 FFFFFFFF;" \ + "cp.b 100000 FFFb0000 50000\0" \ "upd=run load;run update\0" \ - "vx=tftp ${loadaddr} hcu5/hcu5_vx_rom;" \ - "setenv bootargs emac(0,0)hcu5_vx_rom e=${ipaddr} " \ - " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008;" \ - "bootvx ${loadaddr}\0" \ + "vx=tftp ${loadaddr} hcu5/hcu5_vx_rom; run vxboot\0" \ + "vxusb=usb start; fatload usb 0 ${loadaddr} vxWorks.st; run vxboot\0" \ + "vxargs=emac(0,0)c:hcu5/hcu5_vx_rom e=${ipaddr} h=${serverip}" \ + " u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0" \ + "vxboot=setenv bootargs $(vxargs); bootvx ${loadaddr}\0" \ + "usbargs=setenv bootargs root=/dev/sda1 ro\0" \ + "linux=usb start; ext2load usb 0 ${loadaddr} /boot/uImage;" \ + "run usbargs addip addtty; bootm\0" \ + "net_nfs_fdt=tftp 200000 ${bootfile};" \ + "tftp ${fdt_addr} ${fdt_file};" \ + "run nfsargs addip addtty;" \ + "bootm 200000 - ${fdt_addr}\0" \ + "fdt_file=hcu5/hcu5.dtb\0" \ + "fdt_addr=400000\0" \ "" #define CONFIG_BOOTCOMMAND "run vx" -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -214,7 +230,7 @@ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_HAS_ETH0 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & desc. */ #define CONFIG_NET_MULTI 1 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ @@ -246,7 +262,6 @@ #include <config_cmd_default.h> #define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP #define CONFIG_CMD_DHCP #define CONFIG_CMD_DIAG #define CONFIG_CMD_EEPROM @@ -264,6 +279,21 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_USB +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_UART | \ + CFG_POST_I2C | \ + CFG_POST_CACHE | \ + CFG_POST_FPU | \ + CFG_POST_ETHER | \ + CFG_POST_SPR) +#define CFG_POST_UART_TABLE {UART0_BASE} + +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ + #define CONFIG_SUPPORT_VFAT /*----------------------------------------------------------------------- @@ -276,7 +306,7 @@ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ @@ -291,17 +321,16 @@ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------*/ /* General PCI */ -#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI 1 /* include pci support */ #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr map to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ #define CFG_PCI_TARGET_INIT @@ -315,7 +344,17 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Flash + *----------------------------------------------------------------------*/ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup @@ -324,40 +363,30 @@ #define CFG_CS_1 0xC8000000 /* CAN */ #define CFG_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */ #define CFG_CPLD CFG_CS_2 -#define CFG_CS_3 0xCD000000 /* CPLD and IMC-Bus Fast */ +#define CFG_CS_3 0xCE000000 /* CPLD and IMC-Bus Fast */ -/*----------------------------------------------------------------------- - * FLASH organization - * Memory Bank 0 (BOOT-FLASH) initialization - */ -#define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */ +#define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */ #define CFG_EBC_PB0AP 0x02005400 #define CFG_EBC_PB0CR 0xFFF18000 /* (CFG_FLASH | 0xda000) */ #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* Memory Bank 1 CAN-Chips initialization */ +/* Memory Bank 1 CAN-Chips initialization */ #define CFG_EBC_PB1AP 0x02054500 #define CFG_EBC_PB1CR 0xC8018000 -/* Memory Bank 2 CPLD/IMC-Bus standard initialization */ +/* Memory Bank 2 CPLD/IMC-Bus standard initialization */ #define CFG_EBC_PB2AP 0x01840300 #define CFG_EBC_PB2CR 0xCC0BA000 -/* Memory Bank 3 IMC-Bus fast mode initialization */ +/* Memory Bank 3 IMC-Bus fast mode initialization */ #define CFG_EBC_PB3AP 0x01800300 #define CFG_EBC_PB3CR 0xCE0BA000 -/* Memory Bank 4 (not used) initialization */ +/* Memory Bank 4 (not used) initialization */ #undef CFG_EBC_PB4AP #undef CFG_EBC_PB4CR -/* Memory Bank 5 (not used) initialization */ +/* Memory Bank 5 (not used) initialization */ #undef CFG_EBC_PB5AP #undef CFG_EBC_PB5CR @@ -369,8 +398,8 @@ * * Boot Flags */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ #define CFG_HUSH_PARSER /* use "hush" command parser */ #ifdef CFG_HUSH_PARSER @@ -381,4 +410,9 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index f3e8601..a1d1533 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -476,7 +476,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index c5c2724..d8a2267 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -321,6 +321,12 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + #if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else diff --git a/include/configs/makalu.h b/include/configs/makalu.h index 8f8e867..2f0b0a8 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -385,7 +385,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h new file mode 100644 index 0000000..8a94c28 --- /dev/null +++ b/include/configs/ms7720se.h @@ -0,0 +1,134 @@ +/* + * Configuation settings for the Hitachi Solution Engine 7720 + * + * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MS7720SE_H +#define __MS7720SE_H + +#undef DEBUG +#define CONFIG_SH 1 +#define CONFIG_SH3 1 +#define CONFIG_CPU_SH7720 1 +#define CONFIG_MS7720SE 1 + +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_ENV +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_PCMCIA +#define CONFIG_CMD_IDE +#define CONFIG_CMD_EXT2 + +#define CFG_CMD_PCMCIA 0x01 +#define CFG_CMD_IDE 0x02 + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ + CFG_CMD_IDE|CFG_CMD_PCMCIA) & \ + ~(CFG_CMD_FPGA)) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS "console=ttySC0,115200" +#define CONFIG_BOOTFILE /boot/zImage +#define CONFIG_LOADADDR 0x8E000000 + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS + +/* MEMORY */ +#define MS7720SE_SDRAM_BASE 0x8C000000 +#define MS7720SE_FLASH_BASE_1 0xA0000000 +#define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024) + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Buffer size for input from the Console */ +#define CFG_PBSIZE 256 /* Buffer size for Console output */ +#define CFG_MAXARGS 16 /* max args accepted for monitor commands */ +/* Buffer size for Boot Arguments passed to kernel */ +#define CFG_BARGSIZE 512 +/* List of legal baudrate settings for this board */ +#define CFG_BAUDRATE_TABLE { 115200 } + +/* SCIF */ +#define CFG_SCIF_CONSOLE 1 +#define CONFIG_CONS_SCIF0 1 + +#define CFG_MEMTEST_START MS7720SE_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024)) + +#define CFG_SDRAM_BASE MS7720SE_SDRAM_BASE +#define CFG_SDRAM_SIZE (64 * 1024 * 1024) + +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024) +#define CFG_MONITOR_BASE MS7720SE_FLASH_BASE_1 +#define CFG_MONITOR_LEN (128 * 1024) +#define CFG_MALLOC_LEN (256 * 1024) +#define CFG_GBL_DATA_SIZE 256 +#define CFG_BOOTMAPSZ (8 * 1024 * 1024) + + +/* FLASH */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#undef CFG_FLASH_QUIET_TEST +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_FLASH_BASE MS7720SE_FLASH_BASE_1 + +#define CFG_MAX_FLASH_SECT 150 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE (64 * 1024) +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_FLASH_ERASE_TOUT 120000 +#define CFG_FLASH_WRITE_TOUT 500 + +/* Board Clock */ +#define CONFIG_SYS_CLK_FREQ 33333333 +#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */ +#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) + +/* PCMCIA */ +#define CONFIG_IDE_PCMCIA 1 +#define CONFIG_MARUBUN_PCCARD 1 +#define CONFIG_PCMCIA_SLOT_A 1 +#define CFG_IDE_MAXDEVICE 1 +#define CFG_MARUBUN_MRSHPC 0xb83fffe0 +#define CFG_MARUBUN_MW1 0xb8400000 +#define CFG_MARUBUN_MW2 0xb8500000 +#define CFG_MARUBUN_IO 0xb8600000 + +#define CFG_PIO_MODE 1 +#define CFG_IDE_MAXBUS 1 +#define CONFIG_DOS_PARTITION 1 +#define CFG_ATA_BASE_ADDR CFG_MARUBUN_IO /* base address */ +#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ +#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ +#define CFG_ATA_REG_OFFSET 0 /* reg offset */ +#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ + +#endif /* __MS7720SE_H */ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index c050a06..0a7a904 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -56,6 +56,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index b71ba78..f9ede5f 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -50,6 +50,7 @@ #undef CONFIG_PCI /* pci ethernet support */ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 3baa32c..047e1cf 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -51,6 +51,7 @@ #define CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* sysclk for MPC85xx */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 9457bce..e09dd71 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -51,6 +51,7 @@ #undef CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* sysclk for MPC85xx */ diff --git a/include/linux/mtd/fsl_upm.h b/include/linux/mtd/fsl_upm.h new file mode 100644 index 0000000..634ff02 --- /dev/null +++ b/include/linux/mtd/fsl_upm.h @@ -0,0 +1,39 @@ +/* + * FSL UPM NAND driver + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov <avorontsov@ru.mvista.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __LINUX_MTD_NAND_FSL_UPM +#define __LINUX_MTD_NAND_FSL_UPM + +#include <linux/mtd/nand.h> + +struct fsl_upm { + const u32 *array; + void __iomem *mdr; + void __iomem *mxmr; + void __iomem *mar; + void __iomem *io_addr; +}; + +struct fsl_upm_nand { + struct fsl_upm upm; + + int width; + int upm_cmd_offset; + int upm_addr_offset; + int wait_pattern; + int (*dev_ready)(void); + int chip_delay; +}; + +extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun); + +#endif diff --git a/include/mpc512x.h b/include/mpc512x.h index a06b5c6..d1c6fb2 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -185,7 +185,7 @@ /* SCFR1 System Clock Frequency Register 1 */ -#define SCFR1_IPS_DIV 0x2 +#define SCFR1_IPS_DIV 0x4 #define SCFR1_IPS_DIV_MASK 0x03800000 #define SCFR1_IPS_DIV_SHIFT 23 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 7299ca0..df052e3 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -728,6 +728,7 @@ /* TSEC1 bits are for TSEC2 as well */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 +#define SCCR_TSEC1CM_0 0x00000000 #define SCCR_TSEC1CM_1 0x40000000 #define SCCR_TSEC1CM_2 0x80000000 #define SCCR_TSEC1CM_3 0xC0000000 @@ -852,6 +853,7 @@ */ #define CSCONFIG_EN 0x80000000 #define CSCONFIG_AP 0x00800000 +#define CSCONFIG_ODT_WR_ACS 0x00010000 #define CSCONFIG_ROW_BIT 0x00000700 #define CSCONFIG_ROW_BIT_12 0x00000000 #define CSCONFIG_ROW_BIT_13 0x00000100 @@ -1480,6 +1482,7 @@ /* DDRCDR - DDR Control Driver Register */ +#define DDRCDR_DHC_EN 0x80000000 #define DDRCDR_EN 0x40000000 #define DDRCDR_PZ 0x3C000000 #define DDRCDR_PZ_MAXZ 0x00000000 |