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-rw-r--r--include/configs/MPC8536DS.h11
-rw-r--r--include/configs/MPC8569MDS.h12
-rw-r--r--include/configs/MPC8572DS.h1
-rw-r--r--include/configs/P1022DS.h1
-rw-r--r--include/configs/P1_P2_RDB.h14
-rw-r--r--include/configs/P4080DS.h6
-rw-r--r--include/configs/corenet_ds.h6
7 files changed, 39 insertions, 12 deletions
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 8410bb7..850665a 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -36,7 +36,12 @@
#ifdef CONFIG_NAND
#define CONFIG_NAND_U_BOOT 1
#define CONFIG_RAMBOOT_NAND 1
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#else
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
+#endif /* CONFIG_NAND_SPL */
#endif
#ifdef CONFIG_SDCARD
@@ -53,6 +58,10 @@
#define CONFIG_SYS_TEXT_BASE 0xeff80000
#endif
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
@@ -233,8 +242,6 @@
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
|| defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_SYS_RAMBOOT
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 6a15da5..c7973b4 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -65,13 +65,22 @@ extern unsigned long get_clock_freq(void);
#ifdef CONFIG_NAND
#define CONFIG_NAND_U_BOOT 1
#define CONFIG_RAMBOOT_NAND 1
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#else
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
#endif
+#endif
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#endif
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
/*
* Only possible on E500 Version 2 or newer cores.
*/
@@ -194,8 +203,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
#define CONFIG_SYS_RAMBOOT
#else
@@ -488,6 +495,7 @@ extern unsigned long get_clock_freq(void);
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
+#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index f949cc2..692c811 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -474,6 +474,7 @@
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#undef CONFIG_RTL8139
+#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
#ifndef CONFIG_PCI_PNP
#define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 6c8579f..b411fc8 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -270,6 +270,7 @@
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
#endif
/* SATA */
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index b99f383..610f3ed 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -46,7 +46,12 @@
#ifdef CONFIG_NAND
#define CONFIG_NAND_U_BOOT 1
#define CONFIG_RAMBOOT_NAND 1
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#else
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
+#endif /* CONFIG_NAND_SPL */
#endif
#ifdef CONFIG_SDCARD
@@ -63,6 +68,10 @@
#define CONFIG_SYS_TEXT_BASE 0xeff80000
#endif
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
@@ -192,8 +201,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
|| defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_SYS_RAMBOOT
@@ -343,6 +350,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_EEPROM_BUS_NUM 1
#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_RTC_DS1337_NOOSC
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
/*
* General PCI
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index 5e7b81f..21b48e9 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -33,11 +33,9 @@
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */
+
#define CONFIG_SYS_P4080_ERRATUM_CPU22
#define CONFIG_SYS_P4080_ERRATUM_SERDES8
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
-#endif
-
#include "corenet_ds.h"
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 2ac59e5..454a30a 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -37,6 +37,10 @@
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_MP /* support multiple processors */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
@@ -64,7 +68,6 @@
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
-#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
/*
* These can be toggled for performance analysis, otherwise use default.
@@ -475,6 +478,7 @@
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_DHCP
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
generated by cgit v1.1 at 2024-11-05 11:19:24 +0000