diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/PLU405.h | 18 | ||||
| -rw-r--r-- | include/configs/apollon.h | 2 | ||||
| -rw-r--r-- | include/configs/ipek01.h | 408 | ||||
| -rw-r--r-- | include/configs/katmai.h | 9 | ||||
| -rw-r--r-- | include/configs/lwmon5.h | 12 | ||||
| -rw-r--r-- | include/configs/sc3.h | 5 | ||||
| -rw-r--r-- | include/configs/socrates.h | 7 | ||||
| -rw-r--r-- | include/configs/yucca.h | 8 | ||||
| -rw-r--r-- | include/linux/mtd/nand.h | 2 | ||||
| -rw-r--r-- | include/linux/mtd/onenand.h | 16 | ||||
| -rw-r--r-- | include/linux/mtd/onenand_regs.h | 18 | ||||
| -rw-r--r-- | include/linux/mtd/partitions.h | 4 | ||||
| -rw-r--r-- | include/mb862xx.h | 5 | ||||
| -rw-r--r-- | include/onenand_uboot.h | 10 | ||||
| -rw-r--r-- | include/pca9564.h | 50 |
15 files changed, 552 insertions, 22 deletions
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 2e41526..955e0a8 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -266,10 +266,10 @@ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFA0000 -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (384 * 1024) /* Reserve 384kB for malloc() */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1) +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* * Environment Variable setup @@ -427,4 +427,14 @@ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" #define CONFIG_USB_STORAGE 1 +/* + * UBI + */ +#define CONFIG_CMD_UBI +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + #endif /* __CONFIG_H */ diff --git a/include/configs/apollon.h b/include/configs/apollon.h index 575f60e..ddac5fb 100644 --- a/include/configs/apollon.h +++ b/include/configs/apollon.h @@ -76,6 +76,7 @@ * Size of malloc() pool */ #define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE_FLEX SZ_256K #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_1M) /* bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_SIZE 128 @@ -255,6 +256,7 @@ #define CONFIG_SYS_MONITOR_LEN SZ_256K /* U-Boot image size */ #define CONFIG_ENV_IS_IN_ONENAND 1 #define CONFIG_ENV_ADDR 0x00020000 +#define CONFIG_ENV_ADDR_FLEX 0x00040000 #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h new file mode 100644 index 0000000..d9028fa --- /dev/null +++ b/include/configs/ipek01.h @@ -0,0 +1,408 @@ +/* + * (C) Copyright 2006 + * MicroSys GmbH + * + * (C) Copyright 2009 + * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ + +#define CONFIG_MPC5200 +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPX5200 1 /* ... on MPX5200 board */ +#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ +#define CONFIG_IPEK01 /* Motherboard is ipek01 */ + +#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ + +#define CONFIG_MISC_INIT_R + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 9600 bps */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +/* + * Video configuration for LIME GDC + */ +#define CONFIG_VIDEO +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MB862xx +#define CONFIG_VIDEO_MB862xx_ACCEL +#define VIDEO_FB_16BPP_WORD_SWAP +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CONSOLE_EXTRA_INFO +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_SPLASH_SCREEN +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ +/* Lime clock frequency */ +#define CONFIG_SYS_MB862xx_CCF 0x90000 /* geo 166MHz other 133MHz */ +/* SDRAM parameter */ +#define CONFIG_SYS_MB862xx_MMR 0x41c767e3 +#endif + +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +#define CONFIG_PCI_SCAN_SHOW 1 + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 +#define CONFIG_EEPRO100 1 +#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ + +/* Partitions */ +#define CONFIG_DOS_PARTITION + +/* USB */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_OHCI_BE_CONTROLLER +#define CONFIG_USB_STORAGE + +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#ifdef CONFIG_VIDEO +#define CONFIG_CMD_BMP /* BMP support */ +#endif +#define CONFIG_CMD_DATE /* support for RTC, date/time...*/ +#define CONFIG_CMD_DHCP /* DHCP Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_IDE /* IDE harddisk support */ +#define CONFIG_CMD_IRQ /* irqinfo */ +#define CONFIG_CMD_MII /* MII support */ +#define CONFIG_CMD_PCI /* pciinfo */ +#define CONFIG_CMD_USB /* USB Support */ + +#define CONFIG_SYS_LOWBOOT 1 + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyPSC0\0" \ + "hostname=ipek01\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} " \ + "console=${consoledev},${baudrate}\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr} - ${fdtaddr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \ + "net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};" \ + "run nfsargs addip addtty;" \ + "bootm ${loadaddr} - ${fdtaddr}\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "bootfile=ipek01/uImage\0" \ + "load=tftp 100000 ipek01/u-boot.bin\0" \ + "update=protect off FC000000 +60000; era FC000000 +60000; " \ + "cp.b 100000 FC000000 ${filesize}\0" \ + "upd=run load;run update\0" \ + "fdtaddr=800000\0" \ + "loadaddr=400000\0" \ + "fdtfile=ipek01/ipek01.dtb\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +/* + * IPB Bus clocking configuration. + */ +#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* for 133MHz */ +/* PCI clock must be 33, because board will not boot */ +#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for 66MHz */ + +/* + * Open firmware flat tree support + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_CPU "PowerPC,5200@0" +#define OF_SOC "soc5200@f0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ + +#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ +#define CONFIG_SYS_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* + * RTC configuration + */ +#define CONFIG_RTC_PCF8563 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 + +#define CONFIG_SYS_FLASH_BASE 0xFC000000 +#define CONFIG_SYS_FLASH_SIZE 0x01000000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ + CONFIG_SYS_MONITOR_LEN) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ + +/* use CFI flash driver */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +/* + * Memory map + */ +#define CONFIG_SYS_MBAR 0xf0000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 +#define CONFIG_SYS_SRAM_BASE 0xF1000000 +#define CONFIG_SYS_SRAM_SIZE 0x00200000 +#define CONFIG_SYS_LIME_BASE 0xE4000000 +#define CONFIG_SYS_LIME_SIZE 0x04000000 +#define CONFIG_SYS_FPGA_BASE 0xC0000000 +#define CONFIG_SYS_FPGA_SIZE 0x10000000 +#define CONFIG_SYS_MPEG_BASE 0xe2000000 +#define CONFIG_SYS_MPEG_SIZE 0x01000000 +#define CONFIG_SYS_CF_BASE 0xe1000000 +#define CONFIG_SYS_CF_SIZE 0x01000000 + +/* Use SRAM until RAM will be available */ +#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM +/* End of used area in DPRAM */ +#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE + + + +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +# define CONFIG_SYS_RAMBOOT 1 +#endif + +#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 +#define CONFIG_PHY_ADDR 0x00 + +/* + * GPIO configuration + */ +#define CONFIG_SYS_GPS_PORT_CONFIG 0x1d556624 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + + +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1...15 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ + +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_LOOPW + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI +#define CONFIG_SYS_HID0_FINAL HID0_ICE +#else +#define CONFIG_SYS_HID0_INIT 0 +#define CONFIG_SYS_HID0_FINAL 0 +#endif + +#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE +#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE +#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE +#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_SRAM_SIZE +#define CONFIG_SYS_CS3_START CONFIG_SYS_LIME_BASE +#define CONFIG_SYS_CS3_SIZE CONFIG_SYS_LIME_SIZE +#define CONFIG_SYS_CS6_START CONFIG_SYS_FPGA_BASE +#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_FPGA_SIZE +#define CONFIG_SYS_CS5_START CONFIG_SYS_CF_BASE +#define CONFIG_SYS_CS5_SIZE CONFIG_SYS_CF_SIZE +#define CONFIG_SYS_CS7_START CONFIG_SYS_MPEG_BASE +#define CONFIG_SYS_CS7_SIZE CONFIG_SYS_MPEG_SIZE + +#ifdef CONFIG_SYS_PCISPEED_66 +#define CONFIG_SYS_BOOTCS_CFG 0x0006F900 +#define CONFIG_SYS_CS1_CFG 0x0004FB00 +#define CONFIG_SYS_CS2_CFG 0x0006F900 +#else +#define CONFIG_SYS_BOOTCS_CFG 0x0002F900 +#define CONFIG_SYS_CS1_CFG 0x0001FB00 +#define CONFIG_SYS_CS2_CFG 0x0002F90C +#endif + +/* + * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0 + * waitstates, writeswap and readswap enabled + */ +#define CONFIG_SYS_CS3_CFG 0x00FFFB0C +#define CONFIG_SYS_CS6_CFG 0x00FFFB0C +#define CONFIG_SYS_CS7_CFG 0x4040751C + +#define CONFIG_SYS_CS_BURST 0x00000000 +#define CONFIG_SYS_CS_DEADCYCLE 0x33330000 + +#define CONFIG_SYS_RESET_ADDRESS 0xff000000 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00005000 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ +#define CONFIG_IDE_PREINIT + +#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ + +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 + +#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CONFIG_SYS_ATA_STRIDE 4 + +#endif /* __CONFIG_H */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 3840267..c013ac4 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -140,6 +140,11 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 +/* I2C bootstrap EEPROM */ +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 +#define CONFIG_4xx_CONFIG_BLOCKSIZE 8 + /* I2C RTC */ #define CONFIG_RTC_M41T11 1 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ @@ -194,8 +199,10 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_CHIP_CONFIG #define CONFIG_CMD_DATE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT #define CONFIG_CMD_PCI #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SNTP diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 777a4d6..011dd5c 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -344,10 +344,12 @@ /* Video console */ #define CONFIG_VIDEO #define CONFIG_VIDEO_MB862xx +#define CONFIG_VIDEO_MB862xx_ACCEL #define CONFIG_CFB_CONSOLE #define CONFIG_VIDEO_LOGO #define CONFIG_CONSOLE_EXTRA_INFO #define VIDEO_FB_16BPP_PIXEL_SWAP +#define VIDEO_FB_16BPP_WORD_SWAP #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_SW_CURSOR @@ -495,8 +497,6 @@ /*----------------------------------------------------------------------- * Graphics (Fujitsu Lime) *----------------------------------------------------------------------*/ -/* SDRAM Clock frequency adjustment register */ -#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038 /* Lime Clock frequency is to set 100MHz */ #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000 #if 0 @@ -504,15 +504,15 @@ #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000 #endif -/* SDRAM Parameter register */ -#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC /* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars and pixel flare on display when 133MHz was configured. According to SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */ #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ -#define CONFIG_SYS_LIME_MMR_VALUE 0x414FB7F3 +#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3 +#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ #else -#define CONFIG_SYS_LIME_MMR_VALUE 0x414FB7F2 +#define CONFIG_SYS_MB862xx_MMR 0x414FB7F2 +#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ #endif /*----------------------------------------------------------------------- diff --git a/include/configs/sc3.h b/include/configs/sc3.h index 5763760..d4697ad 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -376,11 +376,6 @@ * CONFIG_SYS_FLASH_BASE -> start address of internal flash * CONFIG_SYS_MONITOR_BASE -> start of u-boot */ -#ifndef __ASSEMBLER__ -extern unsigned long offsetOfBigFlash; -extern unsigned long offsetOfEnvironment; -#endif - #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_FLASH_BASE 0xFFE00000 #define CONFIG_SYS_MONITOR_BASE 0xFFFC0000 /* placed last 256k */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 35feed0..3632b84 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -198,11 +198,13 @@ #define CONFIG_VIDEO #define CONFIG_VIDEO_MB862xx +#define CONFIG_VIDEO_MB862xx_ACCEL #define CONFIG_CFB_CONSOLE #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO #define CONFIG_CONSOLE_EXTRA_INFO #define VIDEO_FB_16BPP_PIXEL_SWAP +#define VIDEO_FB_16BPP_WORD_SWAP #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_VIDEO_SW_CURSOR @@ -210,6 +212,11 @@ #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ +/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */ +#define CONFIG_SYS_MB862xx_CCF 0x10000 +/* SDRAM parameter */ +#define CONFIG_SYS_MB862xx_MMR 0x4157BA63 + /* Serial Port */ #define CONFIG_CONS_INDEX 1 diff --git a/include/configs/yucca.h b/include/configs/yucca.h index b165bd7..42f8807 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -389,6 +389,11 @@ #define FPGA_REG1A_PE_SELSOURCE_0 0x0002 #define FPGA_REG1A_PE_SELSOURCE_1 0x0001 +#define FPGA_REG1A_GLED_ENCODE(n) (FPGA_REG1A_PE0_GLED >> (n)) +#define FPGA_REG1A_YLED_ENCODE(n) (FPGA_REG1A_PE0_YLED >> (n)) +#define FPGA_REG1A_PWRON_ENCODE(n) (FPGA_REG1A_PE0_PWRON >> (n)) +#define FPGA_REG1A_REFCLK_ENCODE(n) (FPGA_REG1A_PE0_REFCLK_ENABLE >> (n)) + /*----------------------------------------------------------------------------+ | PCIe Miscellaneous +----------------------------------------------------------------------------*/ @@ -407,6 +412,9 @@ #define FPGA_REG1C_PE1_PERST 0x0008 #define FPGA_REG1C_PE2_PERST 0x0004 +#define FPGA_REG1C_ROOTPOINT_ENCODE(n) (FPGA_REG1C_PE0_ROOTPOINT >> (n)) +#define FPGA_REG1C_PERST_ENCODE(n) (FPGA_REG1C_PE0_PERST >> (n)) + /*----------------------------------------------------------------------------+ | Defines +----------------------------------------------------------------------------*/ diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index cb7c19a..94ad0c0 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -397,7 +397,7 @@ struct nand_chip { int bbt_erase_shift; int chip_shift; int numchips; - unsigned long chipsize; + uint64_t chipsize; int pagemask; int pagebuf; int subpagesize; diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h index 9a6f317..68e174e 100644 --- a/include/linux/mtd/onenand.h +++ b/include/linux/mtd/onenand.h @@ -20,8 +20,9 @@ #include <linux/mtd/compat.h> #include <linux/mtd/bbm.h> +#define MAX_DIES 2 #define MAX_BUFFERRAM 2 -#define MAX_ONENAND_PAGESIZE (2048 + 64) +#define MAX_ONENAND_PAGESIZE (4096 + 128) /* Scan and identify a OneNAND device */ extern int onenand_scan (struct mtd_info *mtd, int max_chips); @@ -39,9 +40,14 @@ struct onenand_bufferram { /** * struct onenand_chip - OneNAND Private Flash Chip Data * @param base [BOARDSPECIFIC] address to access OneNAND + * @dies: [INTERN][FLEXONENAND] number of dies on chip + * @boundary: [INTERN][FLEXONENAND] Boundary of the dies + * @diesize: [INTERN][FLEXONENAND] Size of the dies * @param chipsize [INTERN] the size of one chip for multichip arrays * @param device_id [INTERN] device ID * @param verstion_id [INTERN] version ID + * @technology [INTERN] describes the internal NAND array technology such as SLC or MLC. + * @density_mask: [INTERN] chip density, used for DDP devices * @param options [BOARDSPECIFIC] various chip options. They can partly be set to inform onenand_scan about * @param erase_shift [INTERN] number of address bits in a block * @param page_shift [INTERN] number of address bits in a page @@ -64,9 +70,13 @@ struct onenand_bufferram { */ struct onenand_chip { void __iomem *base; + unsigned int dies; + unsigned int boundary[MAX_DIES]; + unsigned int diesize[MAX_DIES]; unsigned int chipsize; unsigned int device_id; unsigned int version_id; + unsigned int technology; unsigned int density_mask; unsigned int options; @@ -124,6 +134,8 @@ struct onenand_chip { #define ONENAND_SET_BUFFERRAM0(this) (this->bufferram_index = 0) #define ONENAND_SET_BUFFERRAM1(this) (this->bufferram_index = 1) +#define FLEXONENAND(this) (this->device_id & DEVICE_IS_FLEXONENAND) +#define ONENAND_IS_MLC(this) (this->technology & ONENAND_TECHNOLOGY_IS_MLC) #define ONENAND_IS_DDP(this) \ (this->device_id & ONENAND_DEVICE_IS_DDP) @@ -157,4 +169,6 @@ struct onenand_manufacturers { int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops); +unsigned int onenand_block(struct onenand_chip *this, loff_t addr); +int flexonenand_region(struct mtd_info *mtd, loff_t addr); #endif /* __LINUX_MTD_ONENAND_H */ diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h index 07fed1c..8449a3c 100644 --- a/include/linux/mtd/onenand_regs.h +++ b/include/linux/mtd/onenand_regs.h @@ -67,6 +67,9 @@ /* * Device ID Register F001h (R) */ +#define DEVICE_IS_FLEXONENAND (1 << 9) +#define FLEXONENAND_PI_MASK (0x3ff) +#define FLEXONENAND_PI_UNLOCK_SHIFT (14) #define ONENAND_DEVICE_DENSITY_MASK (0xf) #define ONENAND_DEVICE_DENSITY_SHIFT (4) #define ONENAND_DEVICE_IS_DDP (1 << 3) @@ -84,6 +87,11 @@ #define ONENAND_VERSION_PROCESS_SHIFT (8) /* + * Technology Register F006h (R) + */ +#define ONENAND_TECHNOLOGY_IS_MLC (1 << 0) + +/* * Start Address 1 F100h (R/W) */ #define ONENAND_DDP_SHIFT (15) @@ -93,7 +101,7 @@ /* * Start Address 8 F107h (R/W) */ -#define ONENAND_FPA_MASK (0x3f) +#define ONENAND_FPA_MASK (0x7f) #define ONENAND_FPA_SHIFT (2) #define ONENAND_FSA_MASK (0x03) @@ -105,7 +113,7 @@ #define ONENAND_BSA_BOOTRAM (0 << 2) #define ONENAND_BSA_DATARAM0 (2 << 2) #define ONENAND_BSA_DATARAM1 (3 << 2) -#define ONENAND_BSC_MASK (0x03) +#define ONENAND_BSC_MASK (0x07) /* * Command Register F220h (R/W) @@ -125,9 +133,14 @@ #define ONENAND_CMD_ERASE_VERIFY (0x71) #define ONENAND_CMD_RESET (0xF0) #define ONENAND_CMD_READID (0x90) +#define FLEXONENAND_CMD_RESET (0xF3) +#define FLEXONENAND_CMD_PI_UPDATE (0x05) +#define FLEXONENAND_CMD_PI_ACCESS (0x66) +#define FLEXONENAND_CMD_RECOVER_LSB (0x05) /* NOTE: Those are not *REAL* commands */ #define ONENAND_CMD_BUFFERRAM (0x1978) +#define FLEXONENAND_CMD_READ_PI (0x1985) /* * System Configuration 1 Register F221h (R, R/W) @@ -190,5 +203,6 @@ #define ONENAND_ECC_2BIT (1 << 1) #define ONENAND_ECC_2BIT_ALL (0xAAAA) #define ONENAND_ECC_4BIT_UNCORRECTABLE (0x1010) +#define FLEXONENAND_UNCORRECTABLE_ERROR (0x1010) #endif /* __ONENAND_REG_H */ diff --git a/include/linux/mtd/partitions.h b/include/linux/mtd/partitions.h index 1016675..d1d9a96 100644 --- a/include/linux/mtd/partitions.h +++ b/include/linux/mtd/partitions.h @@ -38,8 +38,8 @@ struct mtd_partition { char *name; /* identifier string */ - u_int32_t size; /* partition size */ - u_int32_t offset; /* offset within the master MTD space */ + uint64_t size; /* partition size */ + uint64_t offset; /* offset within the master MTD space */ u_int32_t mask_flags; /* master MTD flags to mask out for this partition */ struct nand_ecclayout *ecclayout; /* out of band layout for this partition (NAND only)*/ struct mtd_info **mtdp; /* pointer to store the MTD object */ diff --git a/include/mb862xx.h b/include/mb862xx.h index 43f01e7..009da03 100644 --- a/include/mb862xx.h +++ b/include/mb862xx.h @@ -32,6 +32,8 @@ #define PCI_DEVICE_ID_CORAL_P 0x2019 #define PCI_DEVICE_ID_CORAL_PA 0x201E +#define MB862XX_TYPE_LIME 0x1 + #define GC_HOST_BASE 0x01fc0000 #define GC_DISP_BASE 0x01fd0000 #define GC_DRAW_BASE 0x01ff0000 @@ -39,6 +41,7 @@ /* Host interface registers */ #define GC_SRST 0x0000002c #define GC_CCF 0x00000038 +#define GC_CID 0x000000f0 #define GC_MMR 0x0000fffc /* @@ -99,6 +102,7 @@ #define GC_FC 0x00000480 #define GC_BC 0x00000484 #define GC_FIFO 0x000004a0 +#define GC_REV 0x00008084 #define GC_GEO_FIFO 0x00008400 typedef struct { @@ -106,6 +110,7 @@ typedef struct { unsigned int value; } gdc_regs; +int mb862xx_probe(unsigned int addr); const gdc_regs *board_get_regs (void); unsigned int board_video_init (void); void board_backlight_switch(int); diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h index 49da9d0..92279d5 100644 --- a/include/onenand_uboot.h +++ b/include/onenand_uboot.h @@ -23,6 +23,7 @@ struct erase_info; struct onenand_chip; extern struct mtd_info onenand_mtd; +extern struct onenand_chip onenand_chip; /* board */ extern void onenand_board_init(struct mtd_info *); @@ -38,6 +39,15 @@ extern int onenand_erase(struct mtd_info *mtd, struct erase_info *instr); extern char *onenand_print_device_info(int device, int version); +extern unsigned onenand_block(struct onenand_chip *this, loff_t addr); + +extern loff_t onenand_addr(struct onenand_chip *this, int block); + +extern int flexonenand_region(struct mtd_info *mtd, loff_t addr); + +extern int flexonenand_set_boundary(struct mtd_info *mtd, int die, + int boundary, int lock); + /* S3C64xx */ extern void s3c64xx_onenand_init(struct mtd_info *); extern void s3c64xx_set_width_regs(struct onenand_chip *); diff --git a/include/pca9564.h b/include/pca9564.h new file mode 100644 index 0000000..3e75259 --- /dev/null +++ b/include/pca9564.h @@ -0,0 +1,50 @@ +/* + * File: include/pca9564.h + * Author: + * + * Created: 2009-06-23 + * Description: PCA9564 i2c bridge driver + * + * Modified: + * Copyright 2009 CJSC "NII STT", http://www.niistt.ru/ + * + * Bugs: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PCA9564_H +#define _PCA9564_H + +/* Clock speeds for the bus */ +#define PCA_CON_330kHz 0x00 +#define PCA_CON_288kHz 0x01 +#define PCA_CON_217kHz 0x02 +#define PCA_CON_146kHz 0x03 +#define PCA_CON_88kHz 0x04 +#define PCA_CON_59kHz 0x05 +#define PCA_CON_44kHz 0x06 +#define PCA_CON_36kHz 0x07 + +#define PCA_CON_AA 0x80 /* Assert Acknowledge */ +#define PCA_CON_ENSIO 0x40 /* Enable */ +#define PCA_CON_STA 0x20 /* Start */ +#define PCA_CON_STO 0x10 /* Stop */ +#define PCA_CON_SI 0x08 /* Serial Interrupt */ +#define PCA_CON_CR 0x07 /* Clock Rate (MASK) */ + +#endif + |