diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/fsl_lbc.h | 264 | ||||
| -rw-r--r-- | include/configs/MPC8315ERDB.h | 2 | ||||
| -rw-r--r-- | include/configs/MPC8349EMDS.h | 2 | ||||
| -rw-r--r-- | include/configs/MPC8349ITX.h | 4 | ||||
| -rw-r--r-- | include/configs/MPC8360EMDS.h | 2 | ||||
| -rw-r--r-- | include/configs/MPC8360ERDK.h | 2 | ||||
| -rw-r--r-- | include/configs/MPC837XEMDS.h | 2 | ||||
| -rw-r--r-- | include/configs/MVBLM7.h | 479 | ||||
| -rw-r--r-- | include/configs/TQM834x.h | 2 | ||||
| -rw-r--r-- | include/mpc83xx.h | 235 | ||||
| -rw-r--r-- | include/mpc85xx.h | 37 | ||||
| -rw-r--r-- | include/mpc86xx.h | 2 |
12 files changed, 757 insertions, 276 deletions
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h new file mode 100644 index 0000000..4529f02 --- /dev/null +++ b/include/asm-ppc/fsl_lbc.h @@ -0,0 +1,264 @@ +/* + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __ASM_PPC_FSL_LBC_H +#define __ASM_PPC_FSL_LBC_H + +#include <config.h> + +/* BR - Base Registers + */ +#define BR0 0x5000 /* Register offset to immr */ +#define BR1 0x5008 +#define BR2 0x5010 +#define BR3 0x5018 +#define BR4 0x5020 +#define BR5 0x5028 +#define BR6 0x5030 +#define BR7 0x5038 + +#define BR_BA 0xFFFF8000 +#define BR_BA_SHIFT 15 +#define BR_PS 0x00001800 +#define BR_PS_SHIFT 11 +#define BR_PS_8 0x00000800 /* Port Size 8 bit */ +#define BR_PS_16 0x00001000 /* Port Size 16 bit */ +#define BR_PS_32 0x00001800 /* Port Size 32 bit */ +#define BR_DECC 0x00000600 +#define BR_DECC_SHIFT 9 +#define BR_DECC_OFF 0x00000000 +#define BR_DECC_CHK 0x00000200 +#define BR_DECC_CHK_GEN 0x00000400 +#define BR_WP 0x00000100 +#define BR_WP_SHIFT 8 +#define BR_MSEL 0x000000E0 +#define BR_MSEL_SHIFT 5 +#define BR_MS_GPCM 0x00000000 /* GPCM */ +#define BR_MS_FCM 0x00000020 /* FCM */ +#ifdef CONFIG_MPC83xx +#define BR_MS_SDRAM 0x00000060 /* SDRAM */ +#elif defined(CONFIG_MPC85xx) +#define BR_MS_SDRAM 0x00000000 /* SDRAM */ +#endif +#define BR_MS_UPMA 0x00000080 /* UPMA */ +#define BR_MS_UPMB 0x000000A0 /* UPMB */ +#define BR_MS_UPMC 0x000000C0 /* UPMC */ +#if !defined(CONFIG_MPC834X) +#define BR_ATOM 0x0000000C +#define BR_ATOM_SHIFT 2 +#endif +#define BR_V 0x00000001 +#define BR_V_SHIFT 0 + +#if defined(CONFIG_MPC834X) +#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) +#else +#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) +#endif + +/* OR - Option Registers + */ +#define OR0 0x5004 /* Register offset to immr */ +#define OR1 0x500C +#define OR2 0x5014 +#define OR3 0x501C +#define OR4 0x5024 +#define OR5 0x502C +#define OR6 0x5034 +#define OR7 0x503C + +#define OR_GPCM_AM 0xFFFF8000 +#define OR_GPCM_AM_SHIFT 15 +#define OR_GPCM_BCTLD 0x00001000 +#define OR_GPCM_BCTLD_SHIFT 12 +#define OR_GPCM_CSNT 0x00000800 +#define OR_GPCM_CSNT_SHIFT 11 +#define OR_GPCM_ACS 0x00000600 +#define OR_GPCM_ACS_SHIFT 9 +#define OR_GPCM_ACS_DIV2 0x00000600 +#define OR_GPCM_ACS_DIV4 0x00000400 +#define OR_GPCM_XACS 0x00000100 +#define OR_GPCM_XACS_SHIFT 8 +#define OR_GPCM_SCY 0x000000F0 +#define OR_GPCM_SCY_SHIFT 4 +#define OR_GPCM_SCY_1 0x00000010 +#define OR_GPCM_SCY_2 0x00000020 +#define OR_GPCM_SCY_3 0x00000030 +#define OR_GPCM_SCY_4 0x00000040 +#define OR_GPCM_SCY_5 0x00000050 +#define OR_GPCM_SCY_6 0x00000060 +#define OR_GPCM_SCY_7 0x00000070 +#define OR_GPCM_SCY_8 0x00000080 +#define OR_GPCM_SCY_9 0x00000090 +#define OR_GPCM_SCY_10 0x000000a0 +#define OR_GPCM_SCY_11 0x000000b0 +#define OR_GPCM_SCY_12 0x000000c0 +#define OR_GPCM_SCY_13 0x000000d0 +#define OR_GPCM_SCY_14 0x000000e0 +#define OR_GPCM_SCY_15 0x000000f0 +#define OR_GPCM_SETA 0x00000008 +#define OR_GPCM_SETA_SHIFT 3 +#define OR_GPCM_TRLX 0x00000004 +#define OR_GPCM_TRLX_SHIFT 2 +#define OR_GPCM_EHTR 0x00000002 +#define OR_GPCM_EHTR_SHIFT 1 +#define OR_GPCM_EAD 0x00000001 +#define OR_GPCM_EAD_SHIFT 0 + +/* helpers to convert values into an OR address mask (GPCM mode) */ +#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ +#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20) + +#define OR_FCM_AM 0xFFFF8000 +#define OR_FCM_AM_SHIFT 15 +#define OR_FCM_BCTLD 0x00001000 +#define OR_FCM_BCTLD_SHIFT 12 +#define OR_FCM_PGS 0x00000400 +#define OR_FCM_PGS_SHIFT 10 +#define OR_FCM_CSCT 0x00000200 +#define OR_FCM_CSCT_SHIFT 9 +#define OR_FCM_CST 0x00000100 +#define OR_FCM_CST_SHIFT 8 +#define OR_FCM_CHT 0x00000080 +#define OR_FCM_CHT_SHIFT 7 +#define OR_FCM_SCY 0x00000070 +#define OR_FCM_SCY_SHIFT 4 +#define OR_FCM_SCY_1 0x00000010 +#define OR_FCM_SCY_2 0x00000020 +#define OR_FCM_SCY_3 0x00000030 +#define OR_FCM_SCY_4 0x00000040 +#define OR_FCM_SCY_5 0x00000050 +#define OR_FCM_SCY_6 0x00000060 +#define OR_FCM_SCY_7 0x00000070 +#define OR_FCM_RST 0x00000008 +#define OR_FCM_RST_SHIFT 3 +#define OR_FCM_TRLX 0x00000004 +#define OR_FCM_TRLX_SHIFT 2 +#define OR_FCM_EHTR 0x00000002 +#define OR_FCM_EHTR_SHIFT 1 + +#define OR_UPM_AM 0xFFFF8000 +#define OR_UPM_AM_SHIFT 15 +#define OR_UPM_XAM 0x00006000 +#define OR_UPM_XAM_SHIFT 13 +#define OR_UPM_BCTLD 0x00001000 +#define OR_UPM_BCTLD_SHIFT 12 +#define OR_UPM_BI 0x00000100 +#define OR_UPM_BI_SHIFT 8 +#define OR_UPM_TRLX 0x00000004 +#define OR_UPM_TRLX_SHIFT 2 +#define OR_UPM_EHTR 0x00000002 +#define OR_UPM_EHTR_SHIFT 1 +#define OR_UPM_EAD 0x00000001 +#define OR_UPM_EAD_SHIFT 0 + +#define MxMR_OP_NORM 0x00000000 /* Normal Operation */ +#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */ +#define MxMR_OP_WARR 0x10000000 /* Write to Array */ +#define MxMR_BSEL 0x80000000 /* Bus Select */ + +#define OR_SDRAM_AM 0xFFFF8000 +#define OR_SDRAM_AM_SHIFT 15 +#define OR_SDRAM_XAM 0x00006000 +#define OR_SDRAM_XAM_SHIFT 13 +#define OR_SDRAM_COLS 0x00001C00 +#define OR_SDRAM_COLS_SHIFT 10 +#define OR_SDRAM_ROWS 0x000001C0 +#define OR_SDRAM_ROWS_SHIFT 6 +#define OR_SDRAM_PMSEL 0x00000020 +#define OR_SDRAM_PMSEL_SHIFT 5 +#define OR_SDRAM_EAD 0x00000001 +#define OR_SDRAM_EAD_SHIFT 0 + +#define OR_AM_32KB 0xFFFF8000 +#define OR_AM_64KB 0xFFFF0000 +#define OR_AM_128KB 0xFFFE0000 +#define OR_AM_256KB 0xFFFC0000 +#define OR_AM_512KB 0xFFF80000 +#define OR_AM_1MB 0xFFF00000 +#define OR_AM_2MB 0xFFE00000 +#define OR_AM_4MB 0xFFC00000 +#define OR_AM_8MB 0xFF800000 +#define OR_AM_16MB 0xFF000000 +#define OR_AM_32MB 0xFE000000 +#define OR_AM_64MB 0xFC000000 +#define OR_AM_128MB 0xF8000000 +#define OR_AM_256MB 0xF0000000 +#define OR_AM_512MB 0xE0000000 +#define OR_AM_1GB 0xC0000000 +#define OR_AM_2GB 0x80000000 +#define OR_AM_4GB 0x00000000 + +#define LBLAWAR_EN 0x80000000 +#define LBLAWAR_4KB 0x0000000B +#define LBLAWAR_8KB 0x0000000C +#define LBLAWAR_16KB 0x0000000D +#define LBLAWAR_32KB 0x0000000E +#define LBLAWAR_64KB 0x0000000F +#define LBLAWAR_128KB 0x00000010 +#define LBLAWAR_256KB 0x00000011 +#define LBLAWAR_512KB 0x00000012 +#define LBLAWAR_1MB 0x00000013 +#define LBLAWAR_2MB 0x00000014 +#define LBLAWAR_4MB 0x00000015 +#define LBLAWAR_8MB 0x00000016 +#define LBLAWAR_16MB 0x00000017 +#define LBLAWAR_32MB 0x00000018 +#define LBLAWAR_64MB 0x00000019 +#define LBLAWAR_128MB 0x0000001A +#define LBLAWAR_256MB 0x0000001B +#define LBLAWAR_512MB 0x0000001C +#define LBLAWAR_1GB 0x0000001D +#define LBLAWAR_2GB 0x0000001E + +/* LBCR - Local Bus Configuration Register + */ +#define LBCR_LDIS 0x80000000 +#define LBCR_LDIS_SHIFT 31 +#define LBCR_BCTLC 0x00C00000 +#define LBCR_BCTLC_SHIFT 22 +#define LBCR_LPBSE 0x00020000 +#define LBCR_LPBSE_SHIFT 17 +#define LBCR_EPAR 0x00010000 +#define LBCR_EPAR_SHIFT 16 +#define LBCR_BMT 0x0000FF00 +#define LBCR_BMT_SHIFT 8 + +/* LCRR - Clock Ratio Register + */ +#define LCRR_DBYP 0x80000000 +#define LCRR_DBYP_SHIFT 31 +#define LCRR_BUFCMDC 0x30000000 +#define LCRR_BUFCMDC_SHIFT 28 +#define LCRR_BUFCMDC_1 0x10000000 +#define LCRR_BUFCMDC_2 0x20000000 +#define LCRR_BUFCMDC_3 0x30000000 +#define LCRR_BUFCMDC_4 0x00000000 +#define LCRR_ECL 0x03000000 +#define LCRR_ECL_SHIFT 24 +#define LCRR_ECL_4 0x00000000 +#define LCRR_ECL_5 0x01000000 +#define LCRR_ECL_6 0x02000000 +#define LCRR_ECL_7 0x03000000 +#define LCRR_EADC 0x00030000 +#define LCRR_EADC_SHIFT 16 +#define LCRR_EADC_1 0x00010000 +#define LCRR_EADC_2 0x00020000 +#define LCRR_EADC_3 0x00030000 +#define LCRR_EADC_4 0x00000000 +#define LCRR_CLKDIV 0x0000000F +#define LCRR_CLKDIV_SHIFT 0 +#define LCRR_CLKDIV_2 0x00000002 +#define LCRR_CLKDIV_4 0x00000004 +#define LCRR_CLKDIV_8 0x00000008 + +#endif /* __ASM_PPC_FSL_LBC_H */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 7a5d0aa..095f665 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -203,7 +203,7 @@ #define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ - | OR_GPCM_ACS_0b11 \ + | OR_GPCM_ACS_DIV2 \ | OR_GPCM_XACS \ | OR_GPCM_SCY_15 \ | OR_GPCM_TRLX \ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index bd77540..37e3ca4 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -157,7 +157,7 @@ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 38410a1..82d0686 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -211,7 +211,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE #define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT)) @@ -236,7 +236,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_LED_BASE 0xF9000000 #define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) -#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ +#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ OR_GPCM_EHTR | OR_GPCM_EAD) diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index fcfbe6f..b4bff9a 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -203,7 +203,7 @@ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index adedcb9..ca8d53c 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -195,7 +195,7 @@ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 4e159a0..0dd0279 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -239,7 +239,7 @@ #define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ - | OR_GPCM_ACS_0b11 \ + | OR_GPCM_ACS_DIV2 \ | OR_GPCM_XACS \ | OR_GPCM_SCY_15 \ | OR_GPCM_TRLX \ diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h new file mode 100644 index 0000000..349ca14 --- /dev/null +++ b/include/configs/MVBLM7.h @@ -0,0 +1,479 @@ +/* + * Copyright (C) Matrix Vision GmbH 2008 + * + * Matrix Vision mvBlueLYNX-M7 configuration file + * based on Freescale's MPC8349ITX. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define MV_VERSION "v1.0.1" + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 +#define CONFIG_MPC83XX 1 +#define CONFIG_MPC834X 1 +#define CONFIG_MPC8343 1 + +#define CFG_IMMR 0xE0000000 + +#define CONFIG_PCI +#define CONFIG_83XX_GENERIC_PCI +#define CONFIG_PCI_SKIP_HOST_BRIDGE +#define CONFIG_HARD_I2C +#define CONFIG_TSEC_ENET +#define CONFIG_MPC8XXX_SPI +#define CONFIG_HARD_SPI +#define MVBLM7_MMC_CS 0x04000000 + +/* I2C */ +#undef CONFIG_SOFT_I2C + +#define CONFIG_FSL_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 + +#define CFG_I2C_SPEED 100000 +#define CFG_I2C_SLAVE 0x7F + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_83XX_DDR_USES_CS0 1 +#define CFG_MEMTEST_START (60<<20) +#define CFG_MEMTEST_END (70<<20) + +#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + +#define CFG_DDR_SIZE 256 + +/* HC, 75Ohm, DDR-II, DRQ */ +#define CFG_DDRCDR 0x80000001 +/* EN, ODT_WR, 3BA, 14row, 10col */ +#define CFG_DDR_CS0_CONFIG 0x80014102 +#define CFG_DDR_CS1_CONFIG 0x0 +#define CFG_DDR_CS2_CONFIG 0x0 +#define CFG_DDR_CS3_CONFIG 0x0 + +#define CFG_DDR_CS0_BNDS 0x0000000f +#define CFG_DDR_CS1_BNDS 0x0 +#define CFG_DDR_CS2_BNDS 0x0 +#define CFG_DDR_CS3_BNDS 0x0 + +#define CFG_DDR_CLK_CNTL 0x02000000 + +#define CFG_DDR_TIMING_0 0x00260802 +#define CFG_DDR_TIMING_1 0x2625b221 +#define CFG_DDR_TIMING_2 0x1f9820c7 +#define CFG_DDR_TIMING_3 0x00000000 + +/* ~MEM_EN, SREN, DDR-II, 32_BE */ +#define CFG_DDR_SDRAM_CFG 0x43080000 +#define CFG_DDR_SDRAM_CFG2 0x00401000 +#define CFG_DDR_INTERVAL 0x04060100 + +#define CFG_DDR_MODE 0x078e0232 + +/* Flash */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +#define CFG_FLASH_BASE 0xFF800000 +#define CFG_FLASH_SIZE 8 +#define CFG_FLASH_SIZE_SHIFT 3 +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_ERASE_TOUT 60000 +#define CFG_FLASH_WRITE_TOUT 500 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 256 + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) +#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\ + OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \ + OR_GPCM_EAD) +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE +#define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT)) + +/* + * U-Boot memory configuration + */ +#define CFG_MONITOR_BASE TEXT_BASE +#undef CFG_RAMBOOT + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ +#define CFG_MONITOR_LEN (512 * 1024) +#define CFG_MALLOC_LEN (512 * 1024) + +/* + * Local Bus LCRR and LBCR regs + * LCRR: DLL bypass, Clock divider is 4 + * External Local Bus rate is + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CFG_LBC_LBCR 0x00000000 + +/* LB sdram refresh timer, about 6us */ +#define CFG_LBC_LSRT 0x32000000 +/* LB refresh timer prescal, 266MHz/32*/ +#define CFG_LBC_MRTPR 0x20000000 + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_CONSOLE ttyS0 +#define CONFIG_BAUDRATE 115200 + +#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 +#define MV_DTB_NAME "mvblm7.dtb" + +/* + * PCI + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x10000000 +#define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE) +#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE +#define CFG_PCI1_MMIO_SIZE 0x10000000 +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xE2000000 +#define CFG_PCI1_IO_SIZE 0x01000000 + +#define _IO_BASE 0x00000000 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 3 + +#define PCI_66M +#define CONFIG_83XX_CLKIN 66666667 +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW + +/* TSEC */ +#define CONFIG_GMII +#define CFG_VSC8601_SKEWFIX +#define CFG_VSC8601_SKEW_TX 3 +#define CFG_VSC8601_SKEW_RX 3 + +#define CONFIG_TSEC1 +#define CONFIG_TSEC2 + +#define CONFIG_HAS_ETH0 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_FEC1_PHY_NORXERR +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) +#define TSEC1_PHY_ADDR 0x10 +#define TSEC1_PHYIDX 0 +#define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) + +#define CONFIG_HAS_ETH1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_FEC2_PHY_NORXERR +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) +#define TSEC2_PHY_ADDR 0x11 +#define TSEC2_PHYIDX 0 +#define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) + +#define CONFIG_ETHPRIME "TSEC0" + +#define CONFIG_BOOTP_VENDOREX +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_NTPSERVER +#define CONFIG_BOOTP_RANDOM_DELAY +#define CONFIG_BOOTP_SEND_HOSTNAME + +/* USB */ +#define CONFIG_HAS_FSL_DR_USB + +/* + * Environment + */ +#undef CFG_FLASH_PROTECTION +#define CONFIG_ENV_OVERWRITE + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0xFF800000 +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE + +#define CONFIG_LOADS_ECHO +#define CFG_LOADS_BAUD_CHANGE + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_PCI +#define CONFIG_CMD_I2C +#define CONFIG_CMD_FPGA + +#undef CONFIG_WATCHDOG + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +/* default load address */ +#define CFG_LOAD_ADDR 0x2000000 +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 0x200000 + +#define CFG_PROMPT "mvBL-M7> " +#define CFG_CBSIZE 256 + +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_MAXARGS 16 +#define CFG_BARGSIZE CFG_CBSIZE +#define CFG_HZ 1000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +#define CFG_HRCW_LOW 0x0 +#define CFG_HRCW_HIGH 0x0 + +/* + * System performance + */ +#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ +#define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ +#define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ + +/* clocking */ +#define CFG_SCCR_ENCCM 0 +#define CFG_SCCR_USBMPHCM 0 +#define CFG_SCCR_USBDRCM 2 +#define CFG_SCCR_TSEC1CM 1 +#define CFG_SCCR_TSEC2CM 1 + +#define CFG_SICRH 0x1fff8003 +#define CFG_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0) + +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL CFG_HID0_INIT + +#define CFG_HID2 HID2_HBE + +/* DDR */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI */ +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* no PCI2 */ +#define CFG_IBAT3L 0 +#define CFG_IBAT3U 0 +#define CFG_IBAT4L 0 +#define CFG_IBAT4U 0 + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ +#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) + +/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */ +#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT7L 0 +#define CFG_IBAT7U 0 + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_NETDEV eth0 + +/* Default path and filenames */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR "s" +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_RESET_TO_RETRY 1000 + +#define MV_CI "mvBL-M7" +#define MV_VCI "mvBL-M7" +#define MV_FPGA_DATA "0xfff80000" +#define MV_FPGA_SIZE "0x76ca2" +#define MV_KERNEL_ADDR "0xff810000" +#define MV_INITRD_ADDR "0xffc00000" +#define MV_AUTOSCR_ADDR "0xff804000" +#define MV_AUTOSCR_ADDR2 "0xff806000" +#define MV_DTB_ADDR "0xff808000" +#define MV_INITRD_LENGTH "0x00300000" + +#define CONFIG_SHOW_BOOT_PROGRESS 1 + +#define MV_KERNEL_ADDR_RAM "0x00100000" +#define MV_DTB_ADDR_RAM "0x00600000" +#define MV_INITRD_ADDR_RAM "0x01000000" + +#define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \ + then autoscr ${autoscr_addr}; \ + else autoscr ${autoscr_addr2}; \ + fi;" +#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console_nr=0\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "fpga=0\0" \ + "fpgadata=" MV_FPGA_DATA "\0" \ + "fpgadatasize=" MV_FPGA_SIZE "\0" \ + "autoscr_addr=" MV_AUTOSCR_ADDR "\0" \ + "autoscr_addr2=" MV_AUTOSCR_ADDR2 "\0" \ + "mv_kernel_addr=" MV_KERNEL_ADDR "\0" \ + "mv_kernel_addr_ram=" MV_KERNEL_ADDR_RAM "\0" \ + "mv_initrd_addr=" MV_INITRD_ADDR "\0" \ + "mv_initrd_addr_ram=" MV_INITRD_ADDR_RAM "\0" \ + "mv_initrd_length=" MV_INITRD_LENGTH "\0" \ + "mv_dtb_addr=" MV_DTB_ADDR "\0" \ + "mv_dtb_addr_ram=" MV_DTB_ADDR_RAM "\0" \ + "dtb_name=" MV_DTB_NAME "\0" \ + "mv_version=" MV_VERSION "\0" \ + "dhcp_client_id=" MV_CI "\0" \ + "dhcp_vendor-class-identifier=" MV_VCI "\0" \ + "netretry=no\0" \ + "use_static_ipaddr=no\0" \ + "static_ipaddr=192.168.90.10\0" \ + "static_netmask=255.255.255.0\0" \ + "static_gateway=0.0.0.0\0" \ + "initrd_name=uInitrd.mvblm7-xenorfs\0" \ + "zcip=no\0" \ + "netboot=yes\0" \ + "mvtest=Ff\0" \ + "tried_bootfromflash=no\0" \ + "tried_bootfromnet=no\0" \ + "bootfile=mvblm72625.boot\0" \ + "use_dhcp=yes\0" \ + "gev_start=yes\0" \ + "mvbcdma_debug=0\0" \ + "mvbcia_debug=0\0" \ + "propdev_debug=0\0" \ + "gevss_debug=0\0" \ + "watchdog=0\0" \ + "usb_dr_mode=host\0" \ + "" + +#define CONFIG_FPGA_COUNT 1 +#define CONFIG_FPGA CFG_ALTERA_CYCLON2 +#define CONFIG_FPGA_ALTERA +#define CONFIG_FPGA_CYCLON2 + +#endif diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 89fc465..0d2ca72 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -113,7 +113,7 @@ extern int tqm834x_num_flash_banks; BR_MS_GPCM | BR_PS_32 | BR_V) /* FLASH timing (0x0000_0c54) */ -#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \ +#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \ OR_GPCM_SCY_5 | OR_GPCM_TRLX) #define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index d2e1e2b..939b825 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -14,6 +14,7 @@ #define __MPC83XX_H__ #include <config.h> +#include <asm/fsl_lbc.h> #if defined(CONFIG_E300) #include <asm/e300.h> #endif @@ -820,6 +821,7 @@ #define CSCONFIG_EN 0x80000000 #define CSCONFIG_AP 0x00800000 #define CSCONFIG_ODT_WR_ACS 0x00010000 +#define CSCONFIG_BANK_BIT_3 0x00004000 #define CSCONFIG_ROW_BIT 0x00000700 #define CSCONFIG_ROW_BIT_12 0x00000000 #define CSCONFIG_ROW_BIT_13 0x00000100 @@ -1019,239 +1021,6 @@ #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ #define ECC_ERROR_MAN_SBEC_SHIFT 0 -/* BR - Base Registers - */ -#define BR0 0x5000 /* Register offset to immr */ -#define BR1 0x5008 -#define BR2 0x5010 -#define BR3 0x5018 -#define BR4 0x5020 -#define BR5 0x5028 -#define BR6 0x5030 -#define BR7 0x5038 - -#define BR_BA 0xFFFF8000 -#define BR_BA_SHIFT 15 -#define BR_PS 0x00001800 -#define BR_PS_SHIFT 11 -#define BR_PS_8 0x00000800 /* Port Size 8 bit */ -#define BR_PS_16 0x00001000 /* Port Size 16 bit */ -#define BR_PS_32 0x00001800 /* Port Size 32 bit */ -#define BR_DECC 0x00000600 -#define BR_DECC_SHIFT 9 -#define BR_DECC_OFF 0x00000000 -#define BR_DECC_CHK 0x00000200 -#define BR_DECC_CHK_GEN 0x00000400 -#define BR_WP 0x00000100 -#define BR_WP_SHIFT 8 -#define BR_MSEL 0x000000E0 -#define BR_MSEL_SHIFT 5 -#define BR_MS_GPCM 0x00000000 /* GPCM */ -#define BR_MS_FCM 0x00000020 /* FCM */ -#define BR_MS_SDRAM 0x00000060 /* SDRAM */ -#define BR_MS_UPMA 0x00000080 /* UPMA */ -#define BR_MS_UPMB 0x000000A0 /* UPMB */ -#define BR_MS_UPMC 0x000000C0 /* UPMC */ -#if !defined(CONFIG_MPC834X) -#define BR_ATOM 0x0000000C -#define BR_ATOM_SHIFT 2 -#endif -#define BR_V 0x00000001 -#define BR_V_SHIFT 0 - -#if defined(CONFIG_MPC834X) -#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) -#else -#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) -#endif - -/* OR - Option Registers - */ -#define OR0 0x5004 /* Register offset to immr */ -#define OR1 0x500C -#define OR2 0x5014 -#define OR3 0x501C -#define OR4 0x5024 -#define OR5 0x502C -#define OR6 0x5034 -#define OR7 0x503C - -#define OR_GPCM_AM 0xFFFF8000 -#define OR_GPCM_AM_SHIFT 15 -#define OR_GPCM_BCTLD 0x00001000 -#define OR_GPCM_BCTLD_SHIFT 12 -#define OR_GPCM_CSNT 0x00000800 -#define OR_GPCM_CSNT_SHIFT 11 -#define OR_GPCM_ACS 0x00000600 -#define OR_GPCM_ACS_SHIFT 9 -#define OR_GPCM_ACS_0b10 0x00000400 -#define OR_GPCM_ACS_0b11 0x00000600 -#define OR_GPCM_XACS 0x00000100 -#define OR_GPCM_XACS_SHIFT 8 -#define OR_GPCM_SCY 0x000000F0 -#define OR_GPCM_SCY_SHIFT 4 -#define OR_GPCM_SCY_1 0x00000010 -#define OR_GPCM_SCY_2 0x00000020 -#define OR_GPCM_SCY_3 0x00000030 -#define OR_GPCM_SCY_4 0x00000040 -#define OR_GPCM_SCY_5 0x00000050 -#define OR_GPCM_SCY_6 0x00000060 -#define OR_GPCM_SCY_7 0x00000070 -#define OR_GPCM_SCY_8 0x00000080 -#define OR_GPCM_SCY_9 0x00000090 -#define OR_GPCM_SCY_10 0x000000a0 -#define OR_GPCM_SCY_11 0x000000b0 -#define OR_GPCM_SCY_12 0x000000c0 -#define OR_GPCM_SCY_13 0x000000d0 -#define OR_GPCM_SCY_14 0x000000e0 -#define OR_GPCM_SCY_15 0x000000f0 -#define OR_GPCM_SETA 0x00000008 -#define OR_GPCM_SETA_SHIFT 3 -#define OR_GPCM_TRLX 0x00000004 -#define OR_GPCM_TRLX_SHIFT 2 -#define OR_GPCM_EHTR 0x00000002 -#define OR_GPCM_EHTR_SHIFT 1 -#define OR_GPCM_EAD 0x00000001 -#define OR_GPCM_EAD_SHIFT 0 - -#define OR_FCM_AM 0xFFFF8000 -#define OR_FCM_AM_SHIFT 15 -#define OR_FCM_BCTLD 0x00001000 -#define OR_FCM_BCTLD_SHIFT 12 -#define OR_FCM_PGS 0x00000400 -#define OR_FCM_PGS_SHIFT 10 -#define OR_FCM_CSCT 0x00000200 -#define OR_FCM_CSCT_SHIFT 9 -#define OR_FCM_CST 0x00000100 -#define OR_FCM_CST_SHIFT 8 -#define OR_FCM_CHT 0x00000080 -#define OR_FCM_CHT_SHIFT 7 -#define OR_FCM_SCY 0x00000070 -#define OR_FCM_SCY_SHIFT 4 -#define OR_FCM_SCY_1 0x00000010 -#define OR_FCM_SCY_2 0x00000020 -#define OR_FCM_SCY_3 0x00000030 -#define OR_FCM_SCY_4 0x00000040 -#define OR_FCM_SCY_5 0x00000050 -#define OR_FCM_SCY_6 0x00000060 -#define OR_FCM_SCY_7 0x00000070 -#define OR_FCM_RST 0x00000008 -#define OR_FCM_RST_SHIFT 3 -#define OR_FCM_TRLX 0x00000004 -#define OR_FCM_TRLX_SHIFT 2 -#define OR_FCM_EHTR 0x00000002 -#define OR_FCM_EHTR_SHIFT 1 - -#define OR_UPM_AM 0xFFFF8000 -#define OR_UPM_AM_SHIFT 15 -#define OR_UPM_XAM 0x00006000 -#define OR_UPM_XAM_SHIFT 13 -#define OR_UPM_BCTLD 0x00001000 -#define OR_UPM_BCTLD_SHIFT 12 -#define OR_UPM_BI 0x00000100 -#define OR_UPM_BI_SHIFT 8 -#define OR_UPM_TRLX 0x00000004 -#define OR_UPM_TRLX_SHIFT 2 -#define OR_UPM_EHTR 0x00000002 -#define OR_UPM_EHTR_SHIFT 1 -#define OR_UPM_EAD 0x00000001 -#define OR_UPM_EAD_SHIFT 0 - -#define OR_SDRAM_AM 0xFFFF8000 -#define OR_SDRAM_AM_SHIFT 15 -#define OR_SDRAM_XAM 0x00006000 -#define OR_SDRAM_XAM_SHIFT 13 -#define OR_SDRAM_COLS 0x00001C00 -#define OR_SDRAM_COLS_SHIFT 10 -#define OR_SDRAM_ROWS 0x000001C0 -#define OR_SDRAM_ROWS_SHIFT 6 -#define OR_SDRAM_PMSEL 0x00000020 -#define OR_SDRAM_PMSEL_SHIFT 5 -#define OR_SDRAM_EAD 0x00000001 -#define OR_SDRAM_EAD_SHIFT 0 - -#define OR_AM_32KB 0xFFFF8000 -#define OR_AM_64KB 0xFFFF0000 -#define OR_AM_128KB 0xFFFE0000 -#define OR_AM_256KB 0xFFFC0000 -#define OR_AM_512KB 0xFFF80000 -#define OR_AM_1MB 0xFFF00000 -#define OR_AM_2MB 0xFFE00000 -#define OR_AM_4MB 0xFFC00000 -#define OR_AM_8MB 0xFF800000 -#define OR_AM_16MB 0xFF000000 -#define OR_AM_32MB 0xFE000000 -#define OR_AM_64MB 0xFC000000 -#define OR_AM_128MB 0xF8000000 -#define OR_AM_256MB 0xF0000000 -#define OR_AM_512MB 0xE0000000 -#define OR_AM_1GB 0xC0000000 -#define OR_AM_2GB 0x80000000 -#define OR_AM_4GB 0x00000000 - -#define LBLAWAR_EN 0x80000000 -#define LBLAWAR_4KB 0x0000000B -#define LBLAWAR_8KB 0x0000000C -#define LBLAWAR_16KB 0x0000000D -#define LBLAWAR_32KB 0x0000000E -#define LBLAWAR_64KB 0x0000000F -#define LBLAWAR_128KB 0x00000010 -#define LBLAWAR_256KB 0x00000011 -#define LBLAWAR_512KB 0x00000012 -#define LBLAWAR_1MB 0x00000013 -#define LBLAWAR_2MB 0x00000014 -#define LBLAWAR_4MB 0x00000015 -#define LBLAWAR_8MB 0x00000016 -#define LBLAWAR_16MB 0x00000017 -#define LBLAWAR_32MB 0x00000018 -#define LBLAWAR_64MB 0x00000019 -#define LBLAWAR_128MB 0x0000001A -#define LBLAWAR_256MB 0x0000001B -#define LBLAWAR_512MB 0x0000001C -#define LBLAWAR_1GB 0x0000001D -#define LBLAWAR_2GB 0x0000001E - -/* LBCR - Local Bus Configuration Register - */ -#define LBCR_LDIS 0x80000000 -#define LBCR_LDIS_SHIFT 31 -#define LBCR_BCTLC 0x00C00000 -#define LBCR_BCTLC_SHIFT 22 -#define LBCR_LPBSE 0x00020000 -#define LBCR_LPBSE_SHIFT 17 -#define LBCR_EPAR 0x00010000 -#define LBCR_EPAR_SHIFT 16 -#define LBCR_BMT 0x0000FF00 -#define LBCR_BMT_SHIFT 8 - -/* LCRR - Clock Ratio Register - */ -#define LCRR_DBYP 0x80000000 -#define LCRR_DBYP_SHIFT 31 -#define LCRR_BUFCMDC 0x30000000 -#define LCRR_BUFCMDC_SHIFT 28 -#define LCRR_BUFCMDC_1 0x10000000 -#define LCRR_BUFCMDC_2 0x20000000 -#define LCRR_BUFCMDC_3 0x30000000 -#define LCRR_BUFCMDC_4 0x00000000 -#define LCRR_ECL 0x03000000 -#define LCRR_ECL_SHIFT 24 -#define LCRR_ECL_4 0x00000000 -#define LCRR_ECL_5 0x01000000 -#define LCRR_ECL_6 0x02000000 -#define LCRR_ECL_7 0x03000000 -#define LCRR_EADC 0x00030000 -#define LCRR_EADC_SHIFT 16 -#define LCRR_EADC_1 0x00010000 -#define LCRR_EADC_2 0x00020000 -#define LCRR_EADC_3 0x00030000 -#define LCRR_EADC_4 0x00000000 -#define LCRR_CLKDIV 0x0000000F -#define LCRR_CLKDIV_SHIFT 0 -#define LCRR_CLKDIV_2 0x00000002 -#define LCRR_CLKDIV_4 0x00000004 -#define LCRR_CLKDIV_8 0x00000008 - /* DMAMR - DMA Mode Register */ #define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ diff --git a/include/mpc85xx.h b/include/mpc85xx.h index 321b24f..a4d4d65 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -6,6 +6,8 @@ #ifndef __MPC85xx_H__ #define __MPC85xx_H__ +#include <asm/fsl_lbc.h> + /* define for common ppc_asm.tmpl */ #define EXC_OFF_SYS_RESET 0x100 /* System reset */ #define _START_OFFSET 0 @@ -26,39 +28,4 @@ #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ -/* - * Local Bus Controller - memory controller registers - */ -#define BRx_V 0x00000001 /* Bank Valid */ -#define BRx_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */ -#define BRx_MS_SDRAM 0x00000000 /* SDRAM Machine Select */ -#define BRx_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ -#define BRx_MS_UPMB 0x000000a0 /* U.P.M.B Machine Select */ -#define BRx_MS_UPMC 0x000000c0 /* U.P.M.C Machine Select */ -#define BRx_PS_8 0x00000800 /* 8 bit port size */ -#define BRx_PS_32 0x00001800 /* 32 bit port size */ -#define BRx_BA_MSK 0xffff8000 /* Base Address Mask */ - -#define ORxG_EAD 0x00000001 /* External addr latch delay */ -#define ORxG_EHTR 0x00000002 /* Extended hold time on read */ -#define ORxG_TRLX 0x00000004 /* Timing relaxed */ -#define ORxG_SETA 0x00000008 /* External address termination */ -#define ORxG_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */ -#define ORxG_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */ -#define ORxG_XACS 0x00000100 /* Extra addr to CS setup */ -#define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/ -#define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */ - -#define ORxU_BI 0x00000100 /* Burst Inhibit */ -#define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */ - -#define MxMR_OP_NORM 0x00000000 /* Normal Operation */ -#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */ -#define MxMR_OP_WARR 0x10000000 /* Write to Array */ -#define MxMR_BSEL 0x80000000 /* Bus Select */ - -/* helpers to convert values into an OR address mask (GPCM mode) */ -#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ -#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20) - #endif /* __MPC85xx_H__ */ diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 9fd349a..ce3d784 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -7,6 +7,8 @@ #ifndef __MPC86xx_H__ #define __MPC86xx_H__ +#include <asm/fsl_lbc.h> + #define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ #define _START_OFFSET EXC_OFF_SYS_RESET |