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-rw-r--r--include/asm-arm/arch-omap3/omap3.h22
-rw-r--r--include/asm-arm/arch-omap3/sys_proto.h4
-rw-r--r--include/configs/SX1.h6
-rw-r--r--include/configs/davinci_dvevm.h3
-rw-r--r--include/configs/davinci_schmoogie.h3
-rw-r--r--include/configs/davinci_sffsdr.h3
-rw-r--r--include/configs/davinci_sonata.h3
-rw-r--r--include/configs/netstar.h6
-rw-r--r--include/configs/omap1510inn.h6
-rw-r--r--include/configs/omap3_beagle.h37
-rw-r--r--include/configs/omap3_evm.h38
-rw-r--r--include/configs/omap3_overo.h38
-rw-r--r--include/configs/omap3_pandora.h37
-rw-r--r--include/configs/omap3_zoom1.h8
-rw-r--r--include/configs/voiceblue.h4
-rw-r--r--include/s3c6400.h4
16 files changed, 59 insertions, 163 deletions
diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h
index 8c9656f..7c11019 100644
--- a/include/asm-arm/arch-omap3/omap3.h
+++ b/include/asm-arm/arch-omap3/omap3.h
@@ -167,24 +167,20 @@ typedef struct gpio {
* 343x real hardware:
* ES1 = rev 0
*
- * 343x code defines:
- * ES1 = 0+1 = 1
- * ES1 = 1+1 = 1
+ * ES2 onwards, the value maps to contents of IDCODE register [31:28].
*/
-#define CPU_3430_ES1 1
-#define CPU_3430_ES2 2
+#define CPU_3XX_ES10 0
+#define CPU_3XX_ES20 1
+#define CPU_3XX_ES21 2
+#define CPU_3XX_ES30 3
+#define CPU_3XX_ES31 4
+#define CPU_3XX_MAX_REV (CPU_3XX_ES31 + 1)
+
+#define CPU_3XX_ID_SHIFT 28
#define WIDTH_8BIT 0x0000
#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
-/* SDP definitions according to FPGA Rev. Is this OK?? */
-#define SDP_3430_V1 0x1
-#define SDP_3430_V2 0x2
-
-/* EVM definitions */
-#define OMAP3EVM_V1 0x1
-#define OMAP3EVM_V2 0x2
-
/* I2C power management companion definitions */
#define PWRMGT_ADDR_ID1 0x48
#define PWRMGT_ADDR_ID2 0x49
diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h
index 8b554bb..7361d08 100644
--- a/include/asm-arm/arch-omap3/sys_proto.h
+++ b/include/asm-arm/arch-omap3/sys_proto.h
@@ -22,8 +22,6 @@
#define _SYS_PROTO_H_
typedef struct {
- u32 board_type_v1;
- u32 board_type_v2;
u32 mtype;
char *board_string;
char *nand_string;
@@ -46,8 +44,6 @@ u32 get_sysboot_value(void);
u32 is_gpmc_muxed(void);
u32 get_gpmc0_type(void);
u32 get_gpmc0_width(void);
-u32 get_board_type(void);
-void display_board_info(u32);
u32 get_sdr_cs_size(u32);
u32 get_sdr_cs_offset(u32);
u32 is_running_in_sdram(void);
diff --git a/include/configs/SX1.h b/include/configs/SX1.h
index caa6592..6149276 100644
--- a/include/configs/SX1.h
+++ b/include/configs/SX1.h
@@ -135,12 +135,12 @@
#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
-/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
+/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
* This time is further subdivided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE /* use timer 1 */
-#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Stack sizes
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index fae430b..9fe4072 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -56,7 +56,6 @@
/* SoC Configuration */
/*===================*/
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
-#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SYS_HZ 1000
@@ -87,7 +86,7 @@
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK 27000000 /* Input clock to NS16550 */
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index 923e477..a16ac39 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -31,7 +31,6 @@
/* SoC Configuration */
/*===================*/
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
-#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SYS_HZ 1000
@@ -54,7 +53,7 @@
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK 27000000 /* Input clock to NS16550 */
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index 73a59db..c2ebd97 100644
--- a/include/configs/davinci_sffsdr.h
+++ b/include/configs/davinci_sffsdr.h
@@ -32,7 +32,6 @@
* powering ON the DSP. */
/* SoC Configuration */
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
-#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SYS_HZ 1000
@@ -56,7 +55,7 @@
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK 27000000 /* Input clock to NS16550 */
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index 70d2c7d..0fc6012 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -56,7 +56,6 @@
/* SoC Configuration */
/*===================*/
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
-#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SYS_HZ 1000
@@ -87,7 +86,7 @@
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK 27000000 /* Input clock to NS16550 */
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
diff --git a/include/configs/netstar.h b/include/configs/netstar.h
index 39560de..5cfee66 100644
--- a/include/configs/netstar.h
+++ b/include/configs/netstar.h
@@ -222,12 +222,12 @@
#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */
-/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
+/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
* This time is further subdivided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE
-#define CONFIG_SYS_PTV 7 /* 2^(pvt+1), divide by 256 */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
+#define CONFIG_SYS_PTV 7
+#define CONFIG_SYS_HZ 1000
#define OMAP5910_DPLL_DIV 1
#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \
diff --git a/include/configs/omap1510inn.h b/include/configs/omap1510inn.h
index 6c1c5ec..8408209 100644
--- a/include/configs/omap1510inn.h
+++ b/include/configs/omap1510inn.h
@@ -132,12 +132,12 @@
#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
-/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
+/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
* This time is further subdivided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE /* use timer 1 */
-#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Stack sizes
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 5a948e4..d8c328f 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -41,6 +41,12 @@
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
@@ -135,18 +141,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-#define SECTORSIZE 512
-
-#define NAND_ALLOW_ERASE_ALL
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-#define NAND_NO_RB 1
-#define CONFIG_SYS_NAND_WP
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
@@ -185,7 +179,7 @@
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
- "if mmcinit; then " \
+ "if mmc init; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
@@ -306,21 +300,4 @@ extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif
-
-#define WRITE_NAND_COMMAND(d, adr)\
- writel(d, &nand_cs_base->nand_cmd)
-#define WRITE_NAND_ADDRESS(d, adr)\
- writel(d, &nand_cs_base->nand_adr)
-#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
-#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
-
-/* Other NAND Access APIs */
-#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
- while (0)
-#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
- while (0)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
-#define NAND_WAIT_READY(nand) udelay(10)
-
#endif /* __CONFIG_H */
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 8cd8a1b..ab014e9 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -46,6 +46,12 @@
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
@@ -66,7 +72,6 @@
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */
-
/*
* Hardware drivers
*/
@@ -133,18 +138,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */
-#define SECTORSIZE 512
-
-#define NAND_ALLOW_ERASE_ALL
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-#define NAND_NO_RB 1
-#define CONFIG_SYS_NAND_WP
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
@@ -178,7 +171,7 @@
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
- "if mmcinit; then " \
+ "if mmc init; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
@@ -299,23 +292,6 @@ extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif
-
-#define WRITE_NAND_COMMAND(d, adr)\
- writel(d, &nand_cs_base->nand_cmd)
-#define WRITE_NAND_ADDRESS(d, adr)\
- writel(d, &nand_cs_base->nand_adr)
-#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
-#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
-
-/* Other NAND Access APIs */
-#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
- while (0)
-#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
- while (0)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
-#define NAND_WAIT_READY(nand) udelay(10)
-
/*----------------------------------------------------------------------------
* SMSC9115 Ethernet from SMSC9118 family
*----------------------------------------------------------------------------
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 51b04b6..d941497 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -33,6 +33,12 @@
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
@@ -122,19 +128,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-#define SECTORSIZE 512
-
-#define NAND_ALLOW_ERASE_ALL
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-#define NAND_NO_RB 1
-#define CONFIG_SYS_NAND_WP
-
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
@@ -172,7 +165,7 @@
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
- "if mmcinit; then " \
+ "if mmc init; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
@@ -293,21 +286,4 @@ extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif
-
-#define WRITE_NAND_COMMAND(d, adr)\
- writel(d, &nand_cs_base->nand_cmd)
-#define WRITE_NAND_ADDRESS(d, adr)\
- writel(d, &nand_cs_base->nand_adr)
-#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
-#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
-
-/* Other NAND Access APIs */
-#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
- while (0)
-#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
- while (0)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
-#define NAND_WAIT_READY(nand) udelay(10)
-
#endif /* __CONFIG_H */
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 40107a6..f9f6480 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -36,6 +36,12 @@
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
@@ -125,18 +131,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-#define SECTORSIZE 512
-
-#define NAND_ALLOW_ERASE_ALL
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-#define NAND_NO_RB 1
-#define CONFIG_SYS_NAND_WP
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
@@ -174,7 +168,7 @@
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
- "if mmcinit; then " \
+ "if mmc init; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
@@ -295,21 +289,4 @@ extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif
-
-#define WRITE_NAND_COMMAND(d, adr)\
- writel(d, &nand_cs_base->nand_cmd)
-#define WRITE_NAND_ADDRESS(d, adr)\
- writel(d, &nand_cs_base->nand_adr)
-#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
-#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
-
-/* Other NAND Access APIs */
-#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
- while (0)
-#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
- while (0)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
-#define NAND_WAIT_READY(nand) udelay(10)
-
#endif /* __CONFIG_H */
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 8e984b4..b275b15 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -42,6 +42,12 @@
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
@@ -182,7 +188,7 @@
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
- "if mmcinit; then " \
+ "if mmc init; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h
index 3f97843..aa8efaa 100644
--- a/include/configs/voiceblue.h
+++ b/include/configs/voiceblue.h
@@ -210,12 +210,12 @@
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - PHYS_SDRAM_1_RESERVED
-/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
+/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
* This time is further subdivided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE
#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
+#define CONFIG_SYS_HZ 1000
#define OMAP5910_DPLL_DIV 1
#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \
diff --git a/include/s3c6400.h b/include/s3c6400.h
index 87f3760..e527c08 100644
--- a/include/s3c6400.h
+++ b/include/s3c6400.h
@@ -31,10 +31,6 @@
#ifndef __S3C6400_H__
#define __S3C6400_H__
-#ifndef CONFIG_S3C6400
-#define CONFIG_S3C6400 1
-#endif
-
#define S3C64XX_UART_CHANNELS 3
#define S3C64XX_SPI_CHANNELS 2
generated by cgit v1.1 at 2024-12-24 01:30:54 +0000