diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/immap_86xx.h | 1362 | ||||
| -rw-r--r-- | include/asm-ppc/mmu.h | 15 | ||||
| -rw-r--r-- | include/asm-ppc/processor.h | 18 | ||||
| -rw-r--r-- | include/asm-ppc/u-boot.h | 2 | ||||
| -rw-r--r-- | include/common.h | 11 | ||||
| -rw-r--r-- | include/configs/MPC8641HPCN.h | 629 | ||||
| -rw-r--r-- | include/ft_build.h | 4 | ||||
| -rw-r--r-- | include/mpc86xx.h | 119 | ||||
| -rw-r--r-- | include/pci.h | 6 |
9 files changed, 2160 insertions, 6 deletions
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h new file mode 100644 index 0000000..6bbe072 --- /dev/null +++ b/include/asm-ppc/immap_86xx.h @@ -0,0 +1,1362 @@ +/* + * MPC86xx Internal Memory Map + * + * Copyright(c) 2004 Freescale Semiconductor + * Jeff Brown (Jeffrey@freescale.com) + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + */ + +#ifndef __IMMAP_86xx__ +#define __IMMAP_86xx__ + + +/* Local-Access Registers and MCM Registers(0x0000-0x2000) */ +typedef struct ccsr_local_mcm { + uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */ + char res1[4]; + uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */ + char res2[4]; + uint altcar; /* 0x10 - Alternate Configuration Attribute Register */ + char res3[12]; + uint bptr; /* 0x20 - Boot Page Translation Register */ + char res4[3044]; + uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */ + char res5[4]; + uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */ + char res6[20]; + uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */ + char res7[4]; + uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */ + char res8[20]; + uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */ + char res9[4]; + uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */ + char res10[20]; + uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */ + char res11[4]; + uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */ + char res12[20]; + uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */ + char res13[4]; + uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */ + char res14[20]; + uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */ + char res15[4]; + uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */ + char res16[20]; + uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */ + char res17[4]; + uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */ + char res18[20]; + uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ + char res19[4]; + uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ + char res20[16]; + uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */ + char res21[4]; + uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */ + char res22[20]; + uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ + char res23[4]; + uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ + char res24[720]; + uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */ + char res25[4]; + uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */ + char res26[4]; + uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */ + char res27[44]; + uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */ + uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */ + uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */ + uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */ + char res28[16]; + uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */ + uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */ + uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */ + char res29[3476]; + uint edr; /* 0x1e00 - MCM Error Detect Register */ + char res30[4]; + uint eer; /* 0x1e08 - MCM Error Enable Register */ + uint eatr; /* 0x1e0c - MCM Error Attributes Capture Register */ + uint eladr; /* 0x1e10 - MCM Error Low Address Capture Register */ + uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */ + char res31[488]; +} ccsr_local_mcm_t; + +/* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */ + +typedef struct ccsr_ddr { + uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */ + char res1[4]; + uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */ + char res2[4]; + uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */ + char res3[4]; + uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */ + char res4[4]; + uint cs4_bnds; /* 0x2020 - DDR Chip Select 4 Memory Bounds */ + char res5[4]; + uint cs5_bnds; /* 0x2028 - DDR Chip Select 5 Memory Bounds */ + char res6[84]; + uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */ + uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */ + uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */ + uint cs3_config; /* 0x208c - DDR Chip Select Configuration */ + uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */ + uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */ + char res7[104]; + uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */ + uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ + uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ + uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ + uint sdram_cfg_1; /* 0x2110 - DDR SDRAM Control Configuration 1 */ + uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ + uint sdram_mode_1; /* 0x2118 - DDR SDRAM Mode Configuration 1 */ + uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */ + uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */ + uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */ + uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */ + char res8[4]; + uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ + char res9[12]; + uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */ + uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */ + uint init_addr; /* 0x2148 - DDR training initialzation address */ + uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */ + char res10[2728]; + uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ + uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ + char res11[512]; + uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */ + uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */ + uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */ + char res12[20]; + uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */ + uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */ + uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */ + char res13[20]; + uint err_detect; /* 0x2e40 - DDR Memory Error Detect */ + uint err_disable; /* 0x2e44 - DDR Memory Error Disable */ + uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */ + uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */ + uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */ + uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */ + uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */ + char res14[164]; + uint debug_1; /* 0x2f00 */ + uint debug_2; + uint debug_3; + uint debug_4; + uint debug_5; + char res15[236]; +} ccsr_ddr_t; + + +/* Daul I2C Registers(0x3000-0x4000) */ + +typedef struct ccsr_i2c { + u_char i2cadr1; /* 0x3000 - I2C 1 Address Register */ +#define MPC86xx_I2CADR_MASK 0xFE + char res1[3]; + u_char i2cfdr1; /* 0x3004 - I2C 1 Frequency Divider Register */ +#define MPC86xx_I2CFDR_MASK 0x3F + char res2[3]; + u_char i2ccr1; /* 0x3008 - I2C 1 Control Register */ +#define MPC86xx_I2CCR_MEN 0x80 +#define MPC86xx_I2CCR_MIEN 0x40 +#define MPC86xx_I2CCR_MSTA 0x20 +#define MPC86xx_I2CCR_MTX 0x10 +#define MPC86xx_I2CCR_TXAK 0x08 +#define MPC86xx_I2CCR_RSTA 0x04 +#define MPC86xx_I2CCR_BCST 0x01 + char res3[3]; + u_char i2csr1; /* 0x300c - I2C 1 Status Register */ +#define MPC86xx_I2CSR_MCF 0x80 +#define MPC86xx_I2CSR_MAAS 0x40 +#define MPC86xx_I2CSR_MBB 0x20 +#define MPC86xx_I2CSR_MAL 0x10 +#define MPC86xx_I2CSR_BCSTM 0x08 +#define MPC86xx_I2CSR_SRW 0x04 +#define MPC86xx_I2CSR_MIF 0x02 +#define MPC86xx_I2CSR_RXAK 0x01 + char res4[3]; + u_char i2cdr1; /* 0x3010 - I2C 1 Data Register */ +#define MPC86xx_I2CDR_DATA 0xFF + char res5[3]; + u_char i2cdfsrr1; /* 0x3014 - I2C 1 Digital Filtering Sampling Rate Register */ +#define MPC86xx_I2CDFSRR 0x3F + char res6[235]; + + u_char i2cadr2; /* 0x3100 - I2C 2 Address Register */ + char res7[3]; + u_char i2cfdr2; /* 0x3104 - I2C 2 Frequency Divider Register */ + char res8[3]; + u_char i2ccr2; /* 0x3108 - I2C 2 Control Register */ + char res9[3]; + u_char i2csr2; /* 0x310c - I2C 2 Status Register */ + char res10[3]; + u_char i2cdr2; /* 0x3110 - I2C 2 Data Register */ + char res11[3]; + u_char i2cdfsrr2; /* 0x3114 - I2C 2 Digital Filtering Sampling Rate Register */ + char res12[3819]; +} ccsr_i2c_t; + +/* DUART Registers(0x4000-0x5000) */ +typedef struct ccsr_duart { + char res1[1280]; + u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */ + u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */ + u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */ + u_char ulcr1; /* 0x4503 - UART1 Line Control Register */ + u_char umcr1; /* 0x4504 - UART1 Modem Control Register */ + u_char ulsr1; /* 0x4505 - UART1 Line Status Register */ + u_char umsr1; /* 0x4506 - UART1 Modem Status Register */ + u_char uscr1; /* 0x4507 - UART1 Scratch Register */ + char res2[8]; + u_char udsr1; /* 0x4510 - UART1 DMA Status Register */ + char res3[239]; + u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */ + u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */ + u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */ + u_char ulcr2; /* 0x4603 - UART2 Line Control Register */ + u_char umcr2; /* 0x4604 - UART2 Modem Control Register */ + u_char ulsr2; /* 0x4605 - UART2 Line Status Register */ + u_char umsr2; /* 0x4606 - UART2 Modem Status Register */ + u_char uscr2; /* 0x4607 - UART2 Scratch Register */ + char res4[8]; + u_char udsr2; /* 0x4610 - UART2 DMA Status Register */ + char res5[2543]; +} ccsr_duart_t; + + +/* Local Bus Controller Registers(0x5000-0x6000) */ +typedef struct ccsr_lbc { + uint br0; /* 0x5000 - LBC Base Register 0 */ + uint or0; /* 0x5004 - LBC Options Register 0 */ + uint br1; /* 0x5008 - LBC Base Register 1 */ + uint or1; /* 0x500c - LBC Options Register 1 */ + uint br2; /* 0x5010 - LBC Base Register 2 */ + uint or2; /* 0x5014 - LBC Options Register 2 */ + uint br3; /* 0x5018 - LBC Base Register 3 */ + uint or3; /* 0x501c - LBC Options Register 3 */ + uint br4; /* 0x5020 - LBC Base Register 4 */ + uint or4; /* 0x5024 - LBC Options Register 4 */ + uint br5; /* 0x5028 - LBC Base Register 5 */ + uint or5; /* 0x502c - LBC Options Register 5 */ + uint br6; /* 0x5030 - LBC Base Register 6 */ + uint or6; /* 0x5034 - LBC Options Register 6 */ + uint br7; /* 0x5038 - LBC Base Register 7 */ + uint or7; /* 0x503c - LBC Options Register 7 */ + char res1[40]; + uint mar; /* 0x5068 - LBC UPM Address Register */ + char res2[4]; + uint mamr; /* 0x5070 - LBC UPMA Mode Register */ + uint mbmr; /* 0x5074 - LBC UPMB Mode Register */ + uint mcmr; /* 0x5078 - LBC UPMC Mode Register */ + char res3[8]; + uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */ + uint mdr; /* 0x5088 - LBC UPM Data Register */ + char res4[8]; + uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */ + char res5[8]; + uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */ + uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */ + char res6[8]; + uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */ + uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */ + uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */ + uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */ + uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */ + char res7[12]; + uint lbcr; /* 0x50d0 - LBC Configuration Register */ + uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */ + char res8[3880]; +} ccsr_lbc_t; + +/* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */ +typedef struct ccsr_pex { + uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */ + uint cfg_data; /* 0x8004 - PEX Configuration Data Register */ + char res1[4]; + uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */ + char res2[16]; + uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */ + uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */ + uint pme_msg_dis; /* 0x802C - PEX PME & message disable register */ + char res3[4]; + uint pm_command; /* 0x8030 - PEX PM Command register */ + char res4[3016]; + uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */ + uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */ + uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */ + uint potear0; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */ + char res5[8]; + uint powar0; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */ + char res6[12]; + uint potar1; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */ + uint potear1; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */ + uint powbar1; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */ + char res7[4]; + uint powar1; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */ + char res8[12]; + uint potar2; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */ + uint potear2; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */ + uint powbar2; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */ + char res9[4]; + uint powar2; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */ + char res10[12]; + uint potar3; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */ + uint potear3; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */ + uint powbar3; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */ + char res11[4]; + uint powar3; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */ + char res12[12]; + uint potar4; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */ + uint potear4; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */ + uint powbar4; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */ + char res13[4]; + uint powar4; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */ + char res14[268]; + uint pitar3; /* 0x8da0 - PEX Inbound Translation Address Register 3 */ + char res15[4]; + uint piwbar3; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */ + uint piwbear3; /* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */ + uint piwar3; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */ + char res16[12]; + uint pitar2; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */ + char res17[4]; + uint piwbar2; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */ + uint piwbear2; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */ + uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */ + char res18[12]; + uint pitar1; /* 0x8de0 - PEX Inbound Translation Address Register 1 */ + char res19[4]; + uint piwbar1; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */ + char res20[4]; + uint piwar1; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */ + char res21[12]; + uint pedr; /* 0x8e00 - PEX Error Detect Register */ + uint pecdr; /* 0x8e04 - PEX Error Capture Disable Register */ + uint peer; /* 0x8e08 - PEX Error Enable Register */ + uint perr_cap0; /* 0x8e0c - PEX Error Capture Register 0 */ + uint perr_cap1; /* 0x8e10 - PEX Error Capture Register 1 */ + uint perr_cap2; /* 0x8e14 - PEX Error Capture Register 2 */ + uint perr_cap3; /* 0x8e18 - PEX Error Capture Register 3 */ + char res22[100]; + uint perr_stat; /* 0x8e80 - PEX Error Status Register */ + char res23[124]; + uint pdebug; /* 0x8f00 - PEX Debug Register */ + char res24[248]; //Sri: changed this because of adding 4 bytes before 0x?8020. +} ccsr_pex_t; + +/* Hyper Transport Register Block (0xA000-0xB000) */ +typedef struct ccsr_ht { + uint hcfg_addr; /* 0xa000 - HT Configuration Address register */ + uint hcfg_data; /* 0xa004 - HT Configuration Data register */ + char res1[3064]; + uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */ + char res2[12]; + uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */ + char res3[12]; + uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */ + char res4[4]; + uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */ + char res5[4]; + uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */ + char res6[12]; + uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */ + char res7[4]; + uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */ + char res8[4]; + uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */ + char res9[12]; + uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */ + char res10[4]; + uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */ + char res11[4]; + uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */ + char res12[12]; + uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */ + char res13[4]; + uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */ + char res14[4]; + uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */ + char res15[236]; + uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */ + char res16[4]; + uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */ + char res17[4]; + uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */ + char res18[12]; + uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */ + char res19[4]; + uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */ + char res20[4]; + uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */ + char res21[12]; + uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */ + char res22[4]; + uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */ + char res23[4]; + uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */ + char res24[12]; + uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */ + char res25[4]; + uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */ + char res26[4]; + uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */ + char res27[12]; + uint hedr; /* 0xae00 - HT Error Detect register */ + char res28[4]; + uint heier; /* 0xae08 - HT Error Interrupt Enable register */ + char res29[4]; + uint hecdr; /* 0xae10 - HT Error Capture Disbale register */ + char res30[12]; + uint hecsr; /* 0xae20 - HT Error Capture Status register */ + char res31[4]; + uint hec0; /* 0xae28 - HT Error Capture 0 register */ + uint hec1; /* 0xae2c - HT Error Capture 1 register */ + uint hec2; /* 0xae30 - HT Error Capture 2 register */ + char res32[460]; +} ccsr_ht_t; + +/* DMA Registers(0x2_1000-0x2_2000) */ +typedef struct ccsr_dma { + char res1[256]; + uint mr0; /* 0x21100 - DMA 0 Mode Register */ + uint sr0; /* 0x21104 - DMA 0 Status Register */ + char res2[4]; + uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */ + uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */ + uint sar0; /* 0x21114 - DMA 0 Source Address Register */ + uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */ + uint dar0; /* 0x2111c - DMA 0 Destination Address Register */ + uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */ + char res3[4]; + uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */ + char res4[8]; + uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */ + char res5[4]; + uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */ + uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */ + uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */ + char res6[56]; + uint mr1; /* 0x21180 - DMA 1 Mode Register */ + uint sr1; /* 0x21184 - DMA 1 Status Register */ + char res7[4]; + uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */ + uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */ + uint sar1; /* 0x21194 - DMA 1 Source Address Register */ + uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */ + uint dar1; /* 0x2119c - DMA 1 Destination Address Register */ + uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */ + char res8[4]; + uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */ + char res9[8]; + uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */ + char res10[4]; + uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */ + uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */ + uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */ + char res11[56]; + uint mr2; /* 0x21200 - DMA 2 Mode Register */ + uint sr2; /* 0x21204 - DMA 2 Status Register */ + char res12[4]; + uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */ + uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */ + uint sar2; /* 0x21214 - DMA 2 Source Address Register */ + uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */ + uint dar2; /* 0x2121c - DMA 2 Destination Address Register */ + uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */ + char res13[4]; + uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */ + char res14[8]; + uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */ + char res15[4]; + uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */ + uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */ + uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */ + char res16[56]; + uint mr3; /* 0x21280 - DMA 3 Mode Register */ + uint sr3; /* 0x21284 - DMA 3 Status Register */ + char res17[4]; + uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */ + uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */ + uint sar3; /* 0x21294 - DMA 3 Source Address Register */ + uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */ + uint dar3; /* 0x2129c - DMA 3 Destination Address Register */ + uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */ + char res18[4]; + uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */ + char res19[8]; + uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */ + char res20[4]; + uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */ + uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */ + uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */ + char res21[56]; + uint dgsr; /* 0x21300 - DMA General Status Register */ + char res22[3324]; +} ccsr_dma_t; + +/* tsec1-4: 24000-28000 */ +typedef struct ccsr_tsec { + uint id; /* 0x24000 - Controller ID Register */ + char res1[12]; + uint ievent; /* 0x24010 - Interrupt Event Register */ + uint imask; /* 0x24014 - Interrupt Mask Register */ + uint edis; /* 0x24018 - Error Disabled Register */ + char res2[4]; + uint ecntrl; /* 0x24020 - Ethernet Control Register */ + char res2_1[4]; + uint ptv; /* 0x24028 - Pause Time Value Register */ + uint dmactrl; /* 0x2402c - DMA Control Register */ + uint tbipa; /* 0x24030 - TBI PHY Address Register */ + char res3[88]; + uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */ + char res4[8]; + uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */ + uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */ + char res4_1[4]; + uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */ + uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */ + char res5[84]; + uint tctrl; /* 0x24100 - Transmit Control Register */ + uint tstat; /* 0x24104 - Transmit Status Register */ + uint dfvlan; /* 0x24108 - Default VLAN control word */ + char res6[4]; + uint txic; /* 0x24110 - Transmit interrupt coalescing Register */ + uint tqueue; /* 0x24114 - Transmit Queue Control Register */ + char res7[40]; + uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */ + uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */ + char res8[52]; + uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */ + char res9[4]; + uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */ + char res10[4]; + uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */ + char res11[4]; + uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */ + char res12[4]; + uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */ + char res13[4]; + uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */ + char res14[4]; + uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */ + char res15[4]; + uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */ + char res16[4]; + uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */ + char res17[64]; + uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */ + uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */ + char res18[4]; + uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */ + char res19[4]; + uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */ + char res20[4]; + uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */ + char res21[4]; + uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */ + char res22[4]; + uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */ + char res23[4]; + uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */ + char res24[4]; + uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */ + char res25[192]; + uint rctrl; /* 0x24300 - Receive Control Register */ + uint rstat; /* 0x24304 - Receive Status Register */ + char res26[8]; + uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */ + uint rqueue; /* 0x24314 - Receive queue control register */ + char res27[24]; + uint rbifx; /* 0x24330 - Receive bit field extract control Register */ + uint rqfar; /* 0x24334 - Receive queue filing table address Register */ + uint rqfcr; /* 0x24338 - Receive queue filing table control Register */ + uint rqfpr; /* 0x2433c - Receive queue filing table property Register */ + uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */ + char res28[56]; + uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */ + char res29[4]; + uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */ + char res30[4]; + uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */ + char res31[4]; + uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */ + char res32[4]; + uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */ + char res33[4]; + uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */ + char res34[4]; + uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */ + char res35[4]; + uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */ + char res36[4]; + uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */ + char res37[64]; + uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */ + uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */ + char res38[4]; + uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */ + char res39[4]; + uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */ + char res40[4]; + uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */ + char res41[4]; + uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */ + char res42[4]; + uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */ + char res43[4]; + uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */ + char res44[4]; + uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */ + char res45[192]; + uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */ + uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */ + uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */ + uint hafdup; /* 0x2450c - Half Duplex Register */ + uint maxfrm; /* 0x24510 - Maximum Frame Length Register */ + char res46[12]; + uint miimcfg; /* 0x24520 - MII Management Configuration Register */ + uint miimcom; /* 0x24524 - MII Management Command Register */ + uint miimadd; /* 0x24528 - MII Management Address Register */ + uint miimcon; /* 0x2452c - MII Management Control Register */ + uint miimstat; /* 0x24530 - MII Management Status Register */ + uint miimind; /* 0x24534 - MII Management Indicator Register */ + uint ifctrl; /* 0x24538 - Interface Contrl Register */ + uint ifstat; /* 0x2453c - Interface Status Register */ + uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */ + uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */ + uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */ + uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */ + uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */ + uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */ + uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */ + uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */ + uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */ + uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */ + uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */ + uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */ + uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */ + uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */ + uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */ + uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */ + uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */ + uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */ + uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */ + uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */ + uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */ + uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */ + uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */ + uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */ + uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */ + uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */ + uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */ + uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */ + uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */ + uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */ + uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */ + uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */ + char res48[192]; + uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */ + uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */ + uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */ + uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */ + uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */ + uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */ + uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ + uint rbyt; /* 0x2469c - Receive Byte Counter */ + uint rpkt; /* 0x246a0 - Receive Packet Counter */ + uint rfcs; /* 0x246a4 - Receive FCS Error Counter */ + uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */ + uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */ + uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */ + uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */ + uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */ + uint raln; /* 0x246bc - Receive Alignment Error Counter */ + uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */ + uint rcde; /* 0x246c4 - Receive Code Error Counter */ + uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */ + uint rund; /* 0x246cc - Receive Undersize Packet Counter */ + uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */ + uint rfrg; /* 0x246d4 - Receive Fragments Counter */ + uint rjbr; /* 0x246d8 - Receive Jabber Counter */ + uint rdrp; /* 0x246dc - Receive Drop Counter */ + uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */ + uint tpkt; /* 0x246e4 - Transmit Packet Counter */ + uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */ + uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */ + uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */ + uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */ + uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */ + uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */ + uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */ + uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */ + uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */ + uint tncl; /* 0x2470c - Transmit Total Collision Counter */ + char res49[4]; + uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */ + uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */ + uint tfcs; /* 0x2471c - Transmit FCS Error Counter */ + uint txcf; /* 0x24720 - Transmit Control Frame Counter */ + uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */ + uint tund; /* 0x24728 - Transmit Undersize Frame Counter */ + uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */ + uint car1; /* 0x24730 - Carry Register One */ + uint car2; /* 0x24734 - Carry Register Two */ + uint cam1; /* 0x24738 - Carry Mask Register One */ + uint cam2; /* 0x2473c - Carry Mask Register Two */ + uint rrej; /* 0x24740 - Receive filer rejected packet counter */ + char res50[188]; + uint iaddr0; /* 0x24800 - Indivdual address register 0 */ + uint iaddr1; /* 0x24804 - Indivdual address register 1 */ + uint iaddr2; /* 0x24808 - Indivdual address register 2 */ + uint iaddr3; /* 0x2480c - Indivdual address register 3 */ + uint iaddr4; /* 0x24810 - Indivdual address register 4 */ + uint iaddr5; /* 0x24814 - Indivdual address register 5 */ + uint iaddr6; /* 0x24818 - Indivdual address register 6 */ + uint iaddr7; /* 0x2481c - Indivdual address register 7 */ + char res51[96]; + uint gaddr0; /* 0x24880 - Global address register 0 */ + uint gaddr1; /* 0x24884 - Global address register 1 */ + uint gaddr2; /* 0x24888 - Global address register 2 */ + uint gaddr3; /* 0x2488c - Global address register 3 */ + uint gaddr4; /* 0x24890 - Global address register 4 */ + uint gaddr5; /* 0x24894 - Global address register 5 */ + uint gaddr6; /* 0x24898 - Global address register 6 */ + uint gaddr7; /* 0x2489c - Global address register 7 */ + char res52[352]; + uint fifocfg; /* 0x24A00 - FIFO interface configuration register */ + char res53[500]; + uint attr; /* 0x24BF8 - DMA Attribute register */ + uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */ + char res54[1024]; +} ccsr_tsec_t; + +/* PIC Registers(0x4_0000-0x6_1000) */ + +typedef struct ccsr_pic { + char res1[64]; + uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */ + char res2[12]; + uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */ + char res3[12]; + uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */ + char res4[12]; + uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */ + char res5[12]; + uint ctpr; /* 0x40080 - Current Task Priority Register */ + char res6[12]; + uint whoami; /* 0x40090 - Who Am I Register */ + char res7[12]; + uint iack; /* 0x400a0 - Interrupt Acknowledge Register */ + char res8[12]; + uint eoi; /* 0x400b0 - End Of Interrupt Register */ + char res9[3916]; + uint frr; /* 0x41000 - Feature Reporting Register */ + char res10[28]; + uint gcr; /* 0x41020 - Global Configuration Register */ + char res11[92]; + uint vir; /* 0x41080 - Vendor Identification Register */ + char res12[12]; + uint pir; /* 0x41090 - Processor Initialization Register */ + char res13[12]; + uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */ + char res14[12]; + uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */ + char res15[12]; + uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */ + char res16[12]; + uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */ + char res17[12]; + uint svr; /* 0x410e0 - Spurious Vector Register */ + char res18[12]; + uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */ + char res19[12]; + uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */ + char res20[12]; + uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */ + char res21[12]; + uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */ + char res22[12]; + uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */ + char res23[12]; + uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */ + char res24[12]; + uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */ + char res25[12]; + uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */ + char res26[12]; + uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */ + char res27[12]; + uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */ + char res28[12]; + uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */ + char res29[12]; + uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */ + char res30[12]; + uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */ + char res31[12]; + uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */ + char res32[12]; + uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */ + char res33[12]; + uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */ + char res34[12]; + uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */ + char res35[268]; + uint tcr; /* 0x41300 - Timer Control Register */ + char res36[12]; + uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */ + char res37[12]; + uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */ + char res38[12]; + uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */ + char res39[12]; + uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */ + char res40[12]; + uint pm0mr0; /* 0x41350 - Performance monitor 0 mask register 0 */ + char res41[12]; + uint pm0mr1; /* 0x41360 - Performance monitor 0 mask register 1 */ + char res42[12]; + uint pm1mr0; /* 0x41370 - Performance monitor 1 mask register 0 */ + char res43[12]; + uint pm1mr1; /* 0x41380 - Performance monitor 1 mask register 1 */ + char res44[12]; + uint pm2mr0; /* 0x41390 - Performance monitor 2 mask register 0 */ + char res45[12]; + uint pm2mr1; /* 0x413A0 - Performance monitor 2 mask register 1 */ + char res46[12]; + uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */ + char res47[12]; + uint pm3mr1; /* 0x413C0 - Performance monitor 3 mask register 1 */ + char res48[60]; + uint msgr0; /* 0x41400 - Message Register 0 */ + char res49[12]; + uint msgr1; /* 0x41410 - Message Register 1 */ + char res50[12]; + uint msgr2; /* 0x41420 - Message Register 2 */ + char res51[12]; + uint msgr3; /* 0x41430 - Message Register 3 */ + char res52[204]; + uint mer; /* 0x41500 - Message Enable Register */ + char res53[12]; + uint msr; /* 0x41510 - Message Status Register */ + char res54[60140]; + uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */ + char res55[12]; + uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */ + char res56[12]; + uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */ + char res57[12]; + uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */ + char res58[12]; + uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */ + char res59[12]; + uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */ + char res60[12]; + uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */ + char res61[12]; + uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */ + char res62[12]; + uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */ + char res63[12]; + uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */ + char res64[12]; + uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */ + char res65[12]; + uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */ + char res66[12]; + uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */ + char res67[12]; + uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */ + char res68[12]; + uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */ + char res69[12]; + uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */ + char res70[12]; + uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */ + char res71[12]; + uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */ + char res72[12]; + uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */ + char res73[12]; + uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */ + char res74[12]; + uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */ + char res75[12]; + uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */ + char res76[12]; + uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */ + char res77[12]; + uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */ + char res78[140]; + uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */ + char res79[12]; + uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */ + char res80[12]; + uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */ + char res81[12]; + uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */ + char res82[12]; + uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */ + char res83[12]; + uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */ + char res84[12]; + uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */ + char res85[12]; + uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */ + char res86[12]; + uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */ + char res87[12]; + uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */ + char res88[12]; + uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */ + char res89[12]; + uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */ + char res90[12]; + uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */ + char res91[12]; + uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */ + char res92[12]; + uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */ + char res93[12]; + uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */ + char res94[12]; + uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */ + char res95[12]; + uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */ + char res96[12]; + uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */ + char res97[12]; + uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */ + char res98[12]; + uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */ + char res99[12]; + uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */ + char res100[12]; + uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */ + char res101[12]; + uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */ + char res102[12]; + uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */ + char res103[12]; + uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */ + char res104[12]; + uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */ + char res105[12]; + uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */ + char res106[12]; + uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */ + char res107[12]; + uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */ + char res108[12]; + uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */ + char res109[12]; + uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */ + char res110[12]; + uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */ + char res111[12]; + uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */ + char res112[12]; + uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */ + char res113[12]; + uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */ + char res114[12]; + uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */ + char res115[12]; + uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */ + char res116[12]; + uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */ + char res117[12]; + uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */ + char res118[12]; + uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */ + char res119[12]; + uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */ + char res120[12]; + uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */ + char res121[12]; + uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */ + char res122[12]; + uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */ + char res123[12]; + uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */ + char res124[12]; + uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */ + char res125[12]; + uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */ + char res126[12]; + uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */ + char res127[12]; + uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */ + char res128[12]; + uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */ + char res129[12]; + uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */ + char res130[12]; + uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */ + char res131[12]; + uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */ + char res132[12]; + uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */ + char res133[12]; + uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */ + char res134[12]; + uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */ + char res135[12]; + uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */ + char res136[12]; + uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */ + char res137[12]; + uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */ + char res138[12]; + uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */ + char res139[12]; + uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */ + char res140[12]; + uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */ + char res141[12]; + uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */ + char res142[4108]; + uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */ + char res143[12]; + uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */ + char res144[12]; + uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */ + char res145[12]; + uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */ + char res146[12]; + uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */ + char res147[12]; + uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */ + char res148[12]; + uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */ + char res149[12]; + uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */ + char res150[59852]; + uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */ + char res151[12]; + uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */ + char res152[12]; + uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */ + char res153[12]; + uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */ + char res154[12]; + uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */ + char res155[12]; + uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */ + char res156[12]; + uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */ + char res157[12]; + uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */ + char res158[3916]; +} ccsr_pic_t; + +/* RapidIO Registers(0xc_0000-0xe_0000) */ + +typedef struct ccsr_rio { + uint didcar; /* 0xc0000 - Device Identity Capability Register */ + uint dicar; /* 0xc0004 - Device Information Capability Register */ + uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */ + uint aicar; /* 0xc000c - Assembly Information Capability Register */ + uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */ + uint spicar; /* 0xc0014 - Switch Port Information Capability Register */ + uint socar; /* 0xc0018 - Source Operations Capability Register */ + uint docar; /* 0xc001c - Destination Operations Capability Register */ + char res1[32]; + uint msr; /* 0xc0040 - Mailbox Command And Status Register */ + uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */ + char res2[4]; + uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */ + char res3[12]; + uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */ + uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */ + char res4[4]; + uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */ + uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */ + char res5[144]; + uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */ + char res6[28]; + uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */ + uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */ + char res7[20]; + uint pgccsr; /* 0xc013c - Port General Command and Status Register */ + uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */ + uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */ + uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */ + char res8[12]; + uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */ + uint pccsr; /* 0xc015c - Port Control Command and Status Register */ + char res9[1184]; + uint erbh; /* 0xc0600 - Error Reporting Block Header Register */ + char res10[4]; + uint ltledcsr; /* 0xc0608 - Logical/Transport layer error detect status register */ + uint ltleecsr; /* 0xc060c - Logical/Transport layer error enable register */ + char res11[4]; + uint ltlaccsr; /* 0xc0614 - Logical/Transport layer addresss capture register */ + uint ltldidccsr; /* 0xc0618 - Logical/Transport layer device ID capture register */ + uint ltlcccsr; /* 0xc061c - Logical/Transport layer control capture register */ + char res12[32]; + uint edcsr; /* 0xc0640 - Port 0 error detect status register */ + uint erecsr; /* 0xc0644 - Port 0 error rate enable status register */ + uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */ + uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */ + uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */ + uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */ + uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */ + char res13[12]; + uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */ + uint ertcsr; /* 0xc066C - Port 0 error rate threshold status register*/ + char res14[63892]; + uint llcr; /* 0xd0004 - Logical Layer Configuration Register */ + char res15[12]; + uint epwisr; /* 0xd0010 - Error / Port-Write Interrupt Status Register */ + char res16[12]; + uint lretcr; /* 0xd0020 - Logical Retry Error Threshold Configuration Register */ + char res17[92]; + uint pretcr; /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */ + char res18[124]; + uint adidcsr; /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */ + char res19[28]; + uint ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */ + char res20[12]; + uint iecsr; /* 0xd0130 - Port 0 Implementation Error Status Register */ + char res21[12]; + uint pcr; /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */ + char res22[20]; + uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */ + char res23[4]; + uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */ + char res24[2716]; + uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */ + uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */ + char res25[8]; + uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */ + char res26[12]; + uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */ + uint rowtear1; /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */ + uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */ + char res27[4]; + uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */ + uint rows1r1; /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */ + uint rows2r1; /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */ + uint rows3r1; /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */ + uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */ + uint rowtear2; /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */ + uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */ + char res28[4]; + uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */ + uint rows1r2; /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */ + uint rows2r2; /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */ + uint rows3r2; /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */ + uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */ + uint rowtear3; /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */ + uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */ + char res29[4]; + uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */ + uint rows1r3; /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */ + uint rows2r3; /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */ + uint rows3r3; /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */ + uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */ + uint rowtear4; /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */ + uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */ + char res30[4]; + uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */ + uint rows1r4; /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */ + uint rows2r4; /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */ + uint rows3r4; /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */ + uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */ + uint rowtear5; /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */ + uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */ + char res31[4]; + uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */ + uint rows1r5; /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */ + uint rows2r5; /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */ + uint rows3r5; /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */ + uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */ + uint rowtear6; /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */ + uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */ + char res32[4]; + uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */ + uint rows1r6; /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */ + uint rows2r6; /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */ + uint rows3r6; /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */ + uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */ + uint rowtear7; /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */ + uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */ + char res33[4]; + uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */ + uint rows1r7; /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */ + uint rows2r7; /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */ + uint rows3r7; /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */ + uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */ + uint rowtear8; /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */ + uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */ + char res34[4]; + uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */ + uint rows1r8; /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */ + uint rows2r8; /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */ + uint rows3r8; /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */ + char res35[64]; + uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */ + uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */ + char res36[4]; + uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */ + char res37[12]; + uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */ + char res38[4]; + uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */ + char res39[4]; + uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */ + char res40[12]; + uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */ + char res41[4]; + uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */ + char res42[4]; + uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */ + char res43[12]; + uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */ + char res44[4]; + uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */ + char res45[4]; + uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */ + char res46[12]; + uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */ + char res47[12]; + uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */ + char res48[12]; + uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */ + uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */ + uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */ + uint pecr; /* 0xd0e0c - Port Error Control Register */ + uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */ + uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */ + uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */ + char res49[4]; + uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */ + char res50[4]; + uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */ + uint prtr; /* 0xd0e2c - Port Retry Threshold Register */ + char res51[8656]; + uint omr; /* 0xd3000 - Outbound Mode Register */ + uint osr; /* 0xd3004 - Outbound Status Register */ + uint eodqtpar; /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */ + uint odqtpar; /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */ + uint eosar; /* 0xd3010 - Extended Outbound Unit Source Address Register */ + uint osar; /* 0xd3014 - Outbound Unit Source Address Register */ + uint odpr; /* 0xd3018 - Outbound Destination Port Register */ + uint odatr; /* 0xd301c - Outbound Destination Attributes Register */ + uint odcr; /* 0xd3020 - Outbound Doubleword Count Register */ + uint eodqhpar; /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */ + uint odqhpar; /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */ + uint oretr; /* 0xd302C - Outbound Retry Error Threshold Register */ + uint omgr; /* 0xd3030 - Outbound Multicast Group Register */ + uint omlr; /* 0xd3034 - Outbound Multicast List Register */ + char res52[40]; + uint imr; /* 0xd3060 - Outbound Mode Register */ + uint isr; /* 0xd3064 - Inbound Status Register */ + uint eidqtpar; /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */ + uint idqtpar; /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */ + uint eifqhpar; /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */ + uint ifqhpar; /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */ + uint imirir; /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */ + char res53[900]; + uint oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */ + uint oddsr; /* 0xd3404 - Outbound Doorbell Status Register */ + char res54[16]; + uint oddpr; /* 0xd3418 - Outbound Doorbell Destination Port Register */ + uint oddatr; /* 0xd341C - Outbound Doorbell Destination Attributes Register */ + char res55[12]; + uint oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */ + char res56[48]; + uint idmr; /* 0xd3460 - Inbound Doorbell Mode Register */ + uint idsr; /* 0xd3464 - Inbound Doorbell Status Register */ + uint iedqtpar; /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */ + uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */ + uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */ + uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */ + uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */ + char res57[100]; + uint pwmr; /* 0xd34e0 - Port-Write Mode Register */ + uint pwsr; /* 0xd34e4 - Port-Write Status Register */ + uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */ + uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */ + char res58[51984]; +} ccsr_rio_t; + +/* Global Utilities Register Block(0xe_0000-0xf_ffff) */ +typedef struct ccsr_gur { + uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ + uint porbmsr; /* 0xe0004 - POR boot mode status register */ +#define MPC86xx_PORBMSR_HA 0x00060000 + uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ + uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ +#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000 + uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ + char res1[12]; + uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ + char res2[12]; + uint gpiocr; /* 0xe0030 - GPIO control register */ + char res3[12]; + uint gpoutdr; /* 0xe0040 - General-purpose output data register */ + char res4[12]; + uint gpindr; /* 0xe0050 - General-purpose input data register */ + char res5[12]; + uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ + char res6[12]; + uint devdisr; /* 0xe0070 - Device disable control */ +#define MPC86xx_DEVDISR_PCIEX1 0x80000000 +#define MPC86xx_DEVDISR_PCIEX2 0x40000000 + char res7[12]; + uint powmgtcsr; /* 0xe0080 - Power management status and control register */ + char res8[12]; + uint mcpsumr; /* 0xe0090 - Machine check summary register */ + char res9[12]; + uint pvr; /* 0xe00a0 - Processor version register */ + uint svr; /* 0xe00a4 - System version register */ + char res10[3416]; + uint clkocr; /* 0xe0e00 - Clock out select register */ + char res11[12]; + uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ + char res12[12]; + uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */ + int res13[57]; + uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/ + int res14[6]; + uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ + char res15[61656]; +} ccsr_gur_t; + +typedef struct immap { + ccsr_local_mcm_t im_local_mcm; + ccsr_ddr_t im_ddr1; + ccsr_i2c_t im_i2c; + ccsr_duart_t im_duart; + ccsr_lbc_t im_lbc; + ccsr_ddr_t im_ddr2; + char res1[4096]; + ccsr_pex_t im_pex1; + ccsr_pex_t im_pex2; + ccsr_ht_t im_ht; + char res2[90112]; + ccsr_dma_t im_dma; + char res3[8192]; + ccsr_tsec_t im_tsec1; + ccsr_tsec_t im_tsec2; + ccsr_tsec_t im_tsec3; + ccsr_tsec_t im_tsec4; + char res4[98304]; + ccsr_pic_t im_pic; + char res5[389120]; + ccsr_rio_t im_rio; + ccsr_gur_t im_gur; +} immap_t; + +extern immap_t *immr; + +#endif /*__IMMAP_86xx__*/ diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 2606b79..612b5df 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -434,19 +434,28 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define BOOKE_PAGESZ_1GB 10 #define BOOKE_PAGESZ_4GB 11 +#if defined(CONFIG_MPC86xx) +#define LAWBAR_BASE_ADDR 0x00FFFFFF +#define LAWAR_TRGT_IF 0x01F00000 +#else #define LAWBAR_BASE_ADDR 0x000FFFFF -#define LAWAR_EN 0x80000000 #define LAWAR_TRGT_IF 0x00F00000 +#endif +#define LAWAR_EN 0x80000000 #define LAWAR_SIZE 0x0000003F #define LAWAR_TRGT_IF_PCI 0x00000000 #define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000 #define LAWAR_TRGT_IF_PCI2 0x00100000 +#define LAWAR_TRGT_IF_HT 0x00200000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 +#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 #define LAWAR_TRGT_IF_RIO 0x00c00000 #define LAWAR_TRGT_IF_DDR 0x00f00000 +#define LAWAR_TRGT_IF_DDR1 0x00f00000 +#define LAWAR_TRGT_IF_DDR2 0x01600000 #define LAWAR_SIZE_BASE 0xa #define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1) @@ -469,5 +478,9 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18) #define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19) #define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20) +#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21) +#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) +#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) +#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) #endif /* _PPC_MMU_H_ */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 8113783..1848aaf 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -264,6 +264,7 @@ #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ +#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ #define SPRN_LR 0x008 /* Link Register */ #define SPRN_MBAR 0x137 /* System memory base address */ @@ -443,6 +444,11 @@ #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ #define ESR_ST 0x00800000 /* Store Operation */ +#if defined(CONFIG_MPC86xx) +#define SPRN_MSSCRO 0x3f6 +#endif + + /* Short-hand versions for a number of the above SPRNs */ #define CTR SPRN_CTR /* Counter Register */ @@ -501,10 +507,14 @@ #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ +#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ #define L2CR SPRN_L2CR /* PPC 750 L2 control register */ #define LR SPRN_LR #define MBAR SPRN_MBAR /* System memory base address */ -#if defined(CONFIG_E500) +#if defined(CONFIG_MPC86xx) +#define MSSCR0 SPRN_MSSCRO +#endif +#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define PIR SPRN_PIR #endif #define SVR SPRN_SVR /* System-On-Chip Version Register */ @@ -538,7 +548,7 @@ #define CSRR0 SPRN_CSRR0 #define CSRR1 SPRN_CSRR1 #define IVPR SPRN_IVPR -#define USPRG0 SPRN_USPRG0 +#define USPRG0 SPRN_USPRG #define SPRG4R SPRN_SPRG4R #define SPRG5R SPRN_SPRG5R #define SPRG6R SPRN_SPRG6R @@ -755,6 +765,8 @@ #define PVR_85xx_REV1 (PVR_85xx | 0x0010) #define PVR_85xx_REV2 (PVR_85xx | 0x0020) +#define PVR_86xx 0x80040000 +#define PVR_86xx_REV1 (PVR_86xx | 0x0010) /* * For the 8xx processors, all of them report the same PVR family for @@ -808,6 +820,8 @@ #define SVR_8548 0x8031 #define SVR_8548_E 0x8039 +#define SVR_8641 0x8090 +#define SVR_8641D 0x8091 /* I am just adding a single entry for 8260 boards. I think we may be * able to combine mbx, fads, rpxlite, bseip, and classic into a single diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index f7aa55f..f335cd8 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -45,7 +45,7 @@ typedef struct bd_info { unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ #if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ - || defined(CONFIG_E500) + || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) unsigned long bi_immr_base; /* base of IMMR register */ #endif #if defined(CONFIG_MPC5xxx) diff --git a/include/common.h b/include/common.h index 5d8b156..83ccf7c 100644 --- a/include/common.h +++ b/include/common.h @@ -79,6 +79,10 @@ typedef volatile unsigned char vu_char; #endif #include <asm/immap_8260.h> #endif +#ifdef CONFIG_MPC86xx +#include <mpc86xx.h> +#include <asm/immap_86xx.h> +#endif #ifdef CONFIG_MPC85xx #include <mpc85xx.h> #include <asm/immap_85xx.h> @@ -366,6 +370,7 @@ void trap_init (ulong); defined (CONFIG_74xx) || \ defined (CONFIG_MPC8220) || \ defined (CONFIG_MPC85xx) || \ + defined (CONFIG_MPC86xx) || \ defined (CONFIG_MPC83XX) unsigned char in8(unsigned int); void out8(unsigned int, unsigned char); @@ -454,6 +459,10 @@ ulong get_bus_freq (ulong); typedef MPC85xx_SYS_INFO sys_info_t; void get_sys_info ( sys_info_t * ); #endif +#if defined(CONFIG_MPC86xx) +typedef MPC86xx_SYS_INFO sys_info_t; +void get_sys_info ( sys_info_t * ); +#endif #if defined(CONFIG_4xx) || defined(CONFIG_IOP480) # if defined(CONFIG_440) @@ -468,7 +477,7 @@ void get_sys_info ( sys_info_t * ); #if defined(CONFIG_8xx) || defined(CONFIG_8260) void cpu_init_f (volatile immap_t *immr); #endif -#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) +#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx) void cpu_init_f (void); #endif diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h new file mode 100644 index 0000000..8d2e088 --- /dev/null +++ b/include/configs/MPC8641HPCN.h @@ -0,0 +1,629 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8641hpc3 board configuration file + * + * + * Make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_MPC86xx 1 /* MPC86xx */ +#define CONFIG_MPC8641 1 /* MPC8641 specific */ +#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ +#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ +#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ +#undef DEBUG + +//#define RUN_DIAG 1 +#ifdef RUN_DIAG +#define CFG_DIAG_ADDR 0xff800000 +#endif +#define CFG_RESET_ADDRESS 0xfff00100 + +//#define CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +/*#define CONFIG_DDR_ECC */ /* only for ECC DDR module */ +/*#define CONFIG_DDR_DLL */ /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + + +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + + +#define CONFIG_ALTIVEC 1 +/*----------------------------------------------------------------------- + * L2CR setup -- make sure this is right for your board! + */ + +#define CFG_L2 +#define L2_INIT 0 +#define L2_ENABLE (L2CR_L2E) + +#ifndef CONFIG_SYS_CLK_FREQ +//#define CONFIG_SYS_CLK_FREQ 33000000 +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +/* JB - XXX - Are these available on 86xx? */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define MPC86xx_DDR_SDRAM_CLK_CNTL + +#if defined(CONFIG_SPD_EEPROM) + /* + * Determine DDR configuration from I2C interface. + */ + #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +#else + /* + * Manually set up DDR parameters + */ + +/* DDR I */ +#if 1 + #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ + + #define CFG_DDR_CS0_BNDS 0x0000000F + #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ + #define CFG_DDR_EXT_REFRESH 0x00000000 + #define CFG_DDR_TIMING_0 0x00260802 + #define CFG_DDR_TIMING_1 0x39357322 + #define CFG_DDR_TIMING_2 0x14904cc8 + #define CFG_DDR_MODE_1 0x00480432 + #define CFG_DDR_MODE_2 0x00000000 + #define CFG_DDR_INTERVAL 0x06090100 + #define CFG_DDR_DATA_INIT 0xdeadbeef + #define CFG_DDR_CLK_CTRL 0x03800000 + #define CFG_DDR_OCD_CTRL 0x00000000 + #define CFG_DDR_OCD_STATUS 0x00000000 + #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ + #define CFG_DDR_CONTROL2 0x04400000 + + //Not used in fixed_sdram function + + #define CFG_DDR_MODE 0x00000022 + #define CFG_DDR_CS1_BNDS 0x00000000 + #define CFG_DDR_CS2_BNDS 0x00000FFF //Not done + #define CFG_DDR_CS3_BNDS 0x00000FFF //Not done + #define CFG_DDR_CS4_BNDS 0x00000FFF //Not done + #define CFG_DDR_CS5_BNDS 0x00000FFF //Not done + + + +#endif +#endif + + +/* + * SDRAM on the Local Bus + */ +//#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +//#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000 + * We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff + * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. + * However, when u-boot comes up, the flash_init needs hard start addresses + * to build its info table. For user convenience, we have the flash addresses + * as fe800000 and ff800000. That way, when we do flash operations, u-boot + * knows where the flash is and the user can download u-boot code from promjet to + * fef00000 <- more intuitive than fe700000. Note that, on switching the boot + * location, fef00000 becomes fff00000. +*/ +#define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ +#define CFG_FLASH_BASE2 0xff800000 + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} + + +/*Sri: This looks like a good place to init all the Local Bus chip selects*/ + +#define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ +#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ + +#define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */ +#define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/ + +#define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ +#define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ + +#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ +#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ + +#define PIXIS_BASE 0xf8100000 /* PIXIS registers*/ +#define PIXIS_ID 0x0 /* MPC8641HPCN Board ID at offset 0*/ +#define PIXIS_VER 0x1 /* MPC8641HPCN board version version at offset 1*/ +#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2*/ +#define PIXIS_RST 0x4 /* PIXIS Reset Control register*/ +#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ +#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ +#define PIXIS_VCTL 0x10 /* VELA Control Register */ +#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ +#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ +#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ +#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ +#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ +#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ +#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ + + +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +//#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +/*#define CFG_HPCN_FLASH_CFI_DRIVER */ +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#if !defined(CFG_RAMBOOT) +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +#define CONFIG_L1_INIT_RAM +#undef CFG_INIT_RAM_LOCK +#ifndef CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ +#else +#define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ +#endif +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8641@0" +#define OF_SOC "soc8641@f8000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" + +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +/* RapidIO MMU */ +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +//#define CFG_PCI1_MEM_BASE 0xd0000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +//#define CFG_PCI1_IO_BASE 0xe0000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +//#define CFG_PCI1_IO_BUS 0x00000000 +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +/* For RTL8139 */ +#define _IO_BASE 0x00000000 + +#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_IO_BASE 0xe3000000 +#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ + +// #define CFG_PCI1_MEM_BASE 0x80000000 +// #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +// #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +// #define CFG_PCI1_IO_BASE 0xe2000000 +// #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +// #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + + + +#if defined(CONFIG_PCI) + + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +//#define CFG_SCSI_SCAN_BUS_REVERSE + + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_RTL8139 + + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +//#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ + +#define CONFIG_MPC86XX_TSEC1 1 +#define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1" +#define CONFIG_MPC86XX_TSEC2 1 +#define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2" +#define CONFIG_MPC86XX_TSEC3 1 +#define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3" +#define CONFIG_MPC86XX_TSEC4 1 +#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" + + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC3_PHY_ADDR 2 +#define TSEC4_PHY_ADDR 3 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#endif /* CONFIG_TSEC_ENET */ + + +/* BAT0 2G Cacheable, non-guarded + * 0x0000_0000 2G DDR + */ +//#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE) +#define CFG_DBAT0U (0x0 | BATU_BL_512M | BATU_VS | BATU_VP) +//#define CFG_IBAT0L CFG_DBAT0L +//#define CFG_IBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT0L (0x0| BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) +#define CFG_IBAT0U CFG_DBAT0U + +/* BAT1 1G Cache-inhibited, guarded + * 0x8000_0000 512M PCI-Express 1 Memory + * 0xa000_0000 512M PCI-Express 2 Memory + ** SS - Changed it for operating from 0xd0000000 + */ +#define CFG_DBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT1U CFG_DBAT1U + +/* BAT2 512M Cache-inhibited, guarded + * 0xc000_0000 512M RapidIO Memory + */ +#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT2U CFG_DBAT2U + +/* BAT3 4M Cache-inhibited, guarded + * 0xf800_0000 4M CCSR + */ +#define CFG_DBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT3U CFG_DBAT3U + +/* BAT4 32M Cache-inhibited, guarded + * 0xe200_0000 16M PCI-Express 1 I/O + * 0xe300_0000 16M PCI-Express 2 I/0 + ** SS - Note that this is at 0xe0000000 + */ +#define CFG_DBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT4U CFG_DBAT4U + +/* BAT5 128K Cacheable, non-guarded + * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) + */ +#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_IBAT5L CFG_DBAT5L +#define CFG_IBAT5U CFG_DBAT5U + +/* BAT6 32M Cache-inhibited, guarded + * 0xfe00_0000 32M FLASH + */ +#define CFG_DBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT6U CFG_DBAT6U + + +#define CFG_DBAT7L 0x00000000 +#define CFG_DBAT7U 0x00000000 +#define CFG_IBAT7L 0x00000000 +#define CFG_IBAT7U 0x00000000 + + + + +/* + * Environment + */ + #ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 + #else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 + #endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_IMLS \ + | CFG_CMD_FLASH \ + | CFG_CMD_LOADS)) + #else + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_IMLS \ + | CFG_CMD_FLASH \ + | CFG_CMD_LOADS)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #else + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #endif +#endif + +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:E0:0C:00:00:01 +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD +#endif + +#define CONFIG_HAS_ETH1 1 +#define CONFIG_HAS_ETH2 1 +#define CONFIG_HAS_ETH3 1 + +#define CONFIG_IPADDR 10.82.193.138 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage + +#define CONFIG_SERVERIP 10.82.193.104 +#define CONFIG_GATEWAYIP 10.82.193.254 +#define CONFIG_NETMASK 255.255.252.0 + +#define CONFIG_LOADADDR 1000000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ +#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=400000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0" \ + "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \ + "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \ + "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \ + "pex=run pexstat; run pex1; run pexd\0" \ + "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ + "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ + "maxcpus=2" + + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/ft_build.h b/include/ft_build.h index 47ca575..5c5e063 100644 --- a/include/ft_build.h +++ b/include/ft_build.h @@ -58,7 +58,9 @@ void ft_begin(struct ft_cxt *cxt, void *blob, int max_size); void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size); void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end); - +#ifdef CONFIG_OF_BOARD_SETUP +void ft_board_setup(void *blob, bd_t *bd); +#endif void ft_dump_blob(const void *bphp); void ft_merge_blob(struct ft_cxt *cxt, void *blob); void *ft_get_prop(void *bphp, const char *propname, int *szp); diff --git a/include/mpc86xx.h b/include/mpc86xx.h new file mode 100644 index 0000000..61b5279 --- /dev/null +++ b/include/mpc86xx.h @@ -0,0 +1,119 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Jeffrey Brown (jeffrey@freescale.com) + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + */ + +#ifndef __MPC86xx_H__ +#define __MPC86xx_H__ + +#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ + +/*---------------------------------------------------------------- + * l2cr values. Look in config_<BOARD>.h for the actual setup + */ +#define l2cr 1017 + +#define L2CR_L2E 0x80000000 /* bit 0 - enable */ +#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */ +#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */ +#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */ +#define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */ +#define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */ +#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */ +#define L2CR_L2IP 0x00000001 /* global invalidate in progress */ + +/*---------------------------------------------------------------- + * BAT settings. Look in config_<BOARD>.h for the actual setup + */ + +#define BATU_BL_128K 0x00000000 +#define BATU_BL_256K 0x00000004 +#define BATU_BL_512K 0x0000000c +#define BATU_BL_1M 0x0000001c +#define BATU_BL_2M 0x0000003c +#define BATU_BL_4M 0x0000007c +#define BATU_BL_8M 0x000000fc +#define BATU_BL_16M 0x000001fc +#define BATU_BL_32M 0x000003fc +#define BATU_BL_64M 0x000007fc +#define BATU_BL_128M 0x00000ffc +#define BATU_BL_256M 0x00001ffc +#define BATU_BL_512M 0x00003ffc +#define BATU_BL_1G 0x00007ffc +#define BATU_BL_2G 0x0000fffc +#define BATU_BL_4G 0x0001fffc + +#define BATU_VS 0x00000002 +#define BATU_VP 0x00000001 +#define BATU_INVALID 0x00000000 + +#define BATL_WRITETHROUGH 0x00000040 +#define BATL_CACHEINHIBIT 0x00000020 +#define BATL_MEMCOHERENCE 0x00000010 +#define BATL_GUARDEDSTORAGE 0x00000008 +#define BATL_NO_ACCESS 0x00000000 + +#define BATL_PP_MSK 0x00000003 +#define BATL_PP_00 0x00000000 /* No access */ +#define BATL_PP_01 0x00000001 /* Read-only */ +#define BATL_PP_10 0x00000002 /* Read-write */ +#define BATL_PP_11 0x00000003 + +#define BATL_PP_NO_ACCESS BATL_PP_00 +#define BATL_PP_RO BATL_PP_01 +#define BATL_PP_RW BATL_PP_10 + +#define HID0_XBSEN 0x00000100 +#define HID0_HIGH_BAT_EN 0x00800000 +#define HID0_XAEN 0x00020000 + +#ifndef __ASSEMBLY__ + +typedef struct +{ + unsigned long freqProcessor; + unsigned long freqSystemBus; +} MPC86xx_SYS_INFO; + +#define l1icache_enable icache_enable + +void l2cache_enable(void); +void l1dcache_enable(void); + +static __inline__ unsigned long get_hid0 (void) +{ + unsigned long hid0; + asm volatile("mfspr %0, 1008" : "=r" (hid0) :); + return hid0; +} + +static __inline__ unsigned long get_hid1 (void) +{ + unsigned long hid1; + asm volatile("mfspr %0, 1009" : "=r" (hid1) :); + return hid1; +} + +static __inline__ void set_hid0 (unsigned long hid0) +{ + asm volatile("mtspr 1008, %0" : : "r" (hid0)); +} + +static __inline__ void set_hid1 (unsigned long hid1) +{ + asm volatile("mtspr 1009, %0" : : "r" (hid1)); +} + + +static __inline__ unsigned long get_l2cr (void) +{ + unsigned long l2cr_val; + asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :); + return l2cr_val; +} + +#endif /* _ASMLANGUAGE */ +#endif /* __MPC86xx_H__ */ + + diff --git a/include/pci.h b/include/pci.h index 0fc00e4..705d1fc 100644 --- a/include/pci.h +++ b/include/pci.h @@ -270,6 +270,12 @@ #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ #define PCI_AGP_SIZEOF 12 +/* PCI-X registers */ +#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */+#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ +#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ +#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ +#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ + /* Slot Identification */ #define PCI_SID_ESR 2 /* Expansion Slot Register */ |