diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/processor.h | 13 | ||||
| -rw-r--r-- | include/configs/TQM5200.h | 34 | ||||
| -rw-r--r-- | include/configs/alpr.h | 19 | ||||
| -rw-r--r-- | include/configs/sequoia.h | 5 | ||||
| -rw-r--r-- | include/configs/solidcard3.h (renamed from include/configs/SOLIDCARD3.h) | 74 | ||||
| -rw-r--r-- | include/configs/spc1920.h | 102 | ||||
| -rw-r--r-- | include/configs/uc101.h | 353 | ||||
| -rw-r--r-- | include/configs/v38b.h | 7 | ||||
| -rw-r--r-- | include/configs/yellowstone.h | 14 | ||||
| -rw-r--r-- | include/configs/yosemite.h | 14 | ||||
| -rw-r--r-- | include/dtt.h | 9 | ||||
| -rw-r--r-- | include/ppc440.h | 20 |
12 files changed, 581 insertions, 83 deletions
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 6619686..f102600 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -747,11 +747,14 @@ #define PVR_440GX_RC 0x51B21892 #define PVR_440GX_RF 0x51B21894 #define PVR_405EP_RB 0x51210950 -#define PVR_440SP_RA 0x53221850 -#define PVR_440SP_RB 0x53221891 -#define PVR_440SP_RC 0x53221892 -#define PVR_440SPe_RA 0x53421890 -#define PVR_440SPe_RB 0x53421891 +#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */ +#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */ +#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */ +#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */ +#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */ +#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */ +#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */ +#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 08674ca..7069b35 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -231,6 +231,17 @@ "protect on FC000000 +${filesize}\0" #endif +#ifndef CONFIG_CAM5200 +#define CUSTOM_ENV_SETTINGS \ + "bootfile=/tftpboot/tqm5200/uImage\0" \ + "u-boot=/tftpboot/tqm5200/u-boot.bin\0" +#else +#define CUSTOM_ENV_SETTINGS \ + "bootfile=cam5200/uImage\0" \ + "u-boot=cam5200/u-boot.bin\0" \ + "setup=tftp 200000 cam5200/setup.img; autoscr 200000\0" +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "rootpath=/opt/eldk/ppc_6xx\0" \ @@ -248,8 +259,7 @@ "bootm ${kernel_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \ "bootm\0" \ - "bootfile=/tftpboot/tqm5200/uImage\0" \ - "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ + CUSTOM_ENV_SETTINGS \ "load=tftp 200000 ${u-boot}\0" \ ENV_UPDT \ "" @@ -325,15 +335,7 @@ */ #define CFG_FLASH_BASE 0xFC000000 -#ifndef CONFIG_CAM5200 -/* use CFI flash driver */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#else /* CONFIG_CAM5200 */ +#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) #define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks (= chip selects) */ #define CFG_FLASH_WORD_SIZE unsigned int /* main flash device with */ @@ -344,7 +346,15 @@ #define CFG_FLASH_ADDR1 0x2AA #define CFG_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */ #define CFG_MAX_FLASH_SECT 128 -#endif /* ifndef CONFIG_CAM5200 */ +#else +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#endif #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ diff --git a/include/configs/alpr.h b/include/configs/alpr.h index bbe6b76..49027da 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -166,8 +166,23 @@ "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ "upd=run load;run update\0" \ + "ethprime=ppc_4xx_eth3\0" \ + "ethact=ppc_4xx_eth3\0" \ + "autoload=no\0" \ + "ipconfig=dhcp;setenv serverip 11.0.0.152\0" \ + "actkernel=kernel2\0" \ + "load_fpga=fpga load 0 ffe00000 10dd9a\0" \ + "mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \ + "rootfstype=jffs2 init=/sbin/init\0" \ + "kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\ + ";bootm 200000\0" \ + "kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \ + "addtty;bootm 200000\0" \ + "kernel1=run ipconfig load_fpga kernel1_mtd\0" \ + "kernel2=run ipconfig load_fpga kernel2_mtd\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTCOMMAND "run kernel2" #define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ @@ -291,6 +306,8 @@ /*----------------------------------------------------------------------- * Definitions for GPIO setup *-----------------------------------------------------------------------*/ +#define CFG_GPIO_SHUTDOWN (0x80000000 >> 6) +#define CFG_GPIO_SSD_EMPTY (0x80000000 >> 9) #define CFG_GPIO_EREADY (0x80000000 >> 26) #define CFG_GPIO_REV0 (0x80000000 >> 14) #define CFG_GPIO_REV1 (0x80000000 >> 15) diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 00b9222..e7f0108 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -188,7 +188,10 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#define CFG_MBYTES_SDRAM (256) /* 256MB */ +#define CFG_MBYTES_SDRAM (256) /* 256MB */ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ +#endif /*----------------------------------------------------------------------- * I2C diff --git a/include/configs/SOLIDCARD3.h b/include/configs/solidcard3.h index 16e68b5..867cba5 100644 --- a/include/configs/SOLIDCARD3.h +++ b/include/configs/solidcard3.h @@ -94,7 +94,7 @@ * define CONFIG_BAUDRATE to the baudrate value you want to use as default */ #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ @@ -137,7 +137,7 @@ #define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */ #define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | \ + (CONFIG_CMD_DFL | \ CFG_CMD_PCI | \ CFG_CMD_IRQ | \ CFG_CMD_NET | \ @@ -183,8 +183,8 @@ * Consider the OPB clock! If it get lower the BASE_BAUD must be lower to * (see 405GP datasheet for descritpion) */ -#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ -#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CFG_BASE_BAUD 921600 /* internal clock */ /* The following table includes the supported baudrates */ @@ -201,7 +201,7 @@ *----------------------------------------------------------------------- */ #define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define I2C_INIT #define I2C_ACTIVE 0 @@ -217,26 +217,26 @@ * PCI stuff *----------------------------------------------------------------------- */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ /* If you want to see, whats connected to your PCI bus */ /* #define CONFIG_PCI_SCAN_SHOW */ -#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ /*----------------------------------------------------------------------- * External peripheral base address @@ -244,8 +244,8 @@ */ #if !(CONFIG_COMMANDS & CFG_CMD_IDE) -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ /*----------------------------------------------------------------------- * IDE/ATA stuff @@ -254,9 +254,9 @@ #else /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */ #define CONFIG_START_IDE 1 /* check, if use IDE */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ #define CONFIG_ATAPI #define CONFIG_DOS_PARTITION @@ -345,7 +345,7 @@ extern unsigned long offsetOfEnvironment; */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- - * FLASH organization // FIXME: lookup in datasheet + * FLASH organization ## FIXME: lookup in datasheet */ #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ @@ -360,8 +360,8 @@ extern unsigned long offsetOfEnvironment; #define CFG_ENV_IS_IN_FLASH 1 #if CFG_ENV_IS_IN_FLASH #define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector in bottom type */ - #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - #define CFG_ENV_SECT_SIZE 0x4000 /* see README - env sector total size */ + #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + #define CFG_ENV_SECT_SIZE 0x4000 /* see README - env sector total size */ #endif /* let us changing anything in our environment */ #define CONFIG_ENV_OVERWRITE @@ -421,21 +421,21 @@ extern unsigned long offsetOfEnvironment; #undef CFG_INIT_DCACHE_CS /* Where the internal SRAM starts */ -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* Where the internal SRAM ends (only offset) */ -#define CFG_INIT_RAM_END 0x0F00 +#define CFG_INIT_RAM_END 0x0F00 /* CFG_INIT_RAM_ADDR ------> ------------ lower address - | | - | ^ | - | | | - | | Stack | + | | + | ^ | + | | | + | | Stack | CFG_GBL_DATA_OFFSET ----> ------------ - | | - | 64 Bytes | - | | + | | + | 64 Bytes | + | | CFG_INIT_RAM_END ------> ------------ higher address (offset only) diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h index 9d3609a..09bbebd 100644 --- a/include/configs/spc1920.h +++ b/include/configs/spc1920.h @@ -44,19 +44,19 @@ #define CONFIG_BAUDRATE 19200 /* use PLD CLK4 instead of brg */ -#undef CFG_SPC1920_SMC1_CLK4 +#define CFG_SPC1920_SMC1_CLK4 #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ #define CONFIG_8xx_CPUCLK_DEFAULT 50000000 #define CFG_8xx_CPUCLK_MIN 40000000 #define CFG_8xx_CPUCLK_MAX 133000000 -#define CFG_RESET_ADDRESS 0xf8000000 +#define CFG_RESET_ADDRESS 0xC0000000 #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_LAST_STAGE_INIT - -#if 1 +#if 0 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ #else #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ @@ -83,12 +83,13 @@ #ifndef CONFIG_COMMANDS #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_ASKENV \ + | CFG_CMD_DATE \ | CFG_CMD_ECHO \ | CFG_CMD_IMMAP \ | CFG_CMD_JFFS2 \ | CFG_CMD_PING \ | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ + | CFG_CMD_I2C \ | CFG_CMD_MII) /* & ~( CFG_CMD_NET)) */ @@ -193,13 +194,39 @@ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#ifdef CFG_CMD_DATE +# define CONFIG_RTC_DS3231 +# define CFG_I2C_RTC_ADDR 0x68 +#endif + /*----------------------------------------------------------------------- * I2C configuration */ #if (CONFIG_COMMANDS & CFG_CMD_I2C) -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */ -#define CFG_I2C_SLAVE 0x7F +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ + +#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CFG_I2C_SLAVE 0xFE + +#ifdef CONFIG_SOFT_I2C +/* + * Software (bit-bang) I2C driver configuration + */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ #endif /*----------------------------------------------------------------------- @@ -220,7 +247,7 @@ *----------------------------------------------------------------------- * PCMCIA config., multi-function pin tri-state */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#define CFG_SIUMCR (SIUMCR_FRC) /*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control 11-26 @@ -283,7 +310,7 @@ * FLASH timing: */ #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) + OR_SCY_6_CLK | OR_EHTR | OR_BI) #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -330,7 +357,56 @@ MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */ -/* PLD CS5 */ +/* + * DSP Host Port Interface CS3 + */ +#define CFG_SPC1920_HPI_BASE 0x90000000 +#define CFG_PRELIM_OR3_AM 0xF8000000 + +#define CFG_OR3 (CFG_PRELIM_OR3_AM | \ + OR_G5LS | \ + OR_SCY_0_CLK | \ + OR_BI) + +#define CFG_BR3 ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \ + BR_MS_UPMA | \ + BR_PS_16 | \ + BR_V); + +#define CFG_MAMR (MAMR_GPL_A4DIS | \ + MAMR_RLFA_5X | \ + MAMR_WLFA_5X) + +#define CONFIG_SPC1920_HPI_TEST + +#ifdef CONFIG_SPC1920_HPI_TEST +#define HPI_REG(x) (*((volatile u16 *) (CFG_SPC1920_HPI_BASE + x))) +#define HPI_HPIC_1 HPI_REG(0) +#define HPI_HPIC_2 HPI_REG(2) +#define HPI_HPIA_1 HPI_REG(0x2000008) +#define HPI_HPIA_2 HPI_REG(0x2000008 + 2) +#define HPI_HPID_INC_1 HPI_REG(0x1000004) +#define HPI_HPID_INC_2 HPI_REG(0x1000004 + 2) +#define HPI_HPID_NOINC_1 HPI_REG(0x300000c) +#define HPI_HPID_NOINC_2 HPI_REG(0x300000c + 2) +#endif /* CONFIG_SPC1920_HPI_TEST */ + +/* + * Ramtron FM18L08 FRAM 32KB on CS4 + */ +#define CFG_SPC1920_FRAM_BASE 0x80100000 +#define CFG_PRELIM_OR4_AM 0xffff8000 +#define CFG_OR4 (CFG_PRELIM_OR4_AM | \ + OR_ACS_DIV2 | \ + OR_BI | \ + OR_SCY_4_CLK | \ + OR_TRLX) + +#define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); + +/* + * PLD CS5 + */ #define CFG_SPC1920_PLD_BASE 0x80000000 #define CFG_PRELIM_OR5_AM 0xffff8000 @@ -343,10 +419,6 @@ #define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); -/* #define CFG_PLD_BASE 0x30000000 */ -/* #define CFG_OR5_PRELIM 0xffff1110 */ -/* #define CFG_BR5_PRELIM 0x30000401 */ - /* * Internal Definitions * diff --git a/include/configs/uc101.h b/include/configs/uc101.h new file mode 100644 index 0000000..8cd8e9b --- /dev/null +++ b/include/configs/uc101.h @@ -0,0 +1,353 @@ +/* + * (C) Copyright 2003-2006 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_UC101 1 /* UC101 board */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#define CONFIG_BOARD_EARLY_INIT_R + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* Partitions */ +#define CONFIG_DOS_PARTITION + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DISPLAY | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_DTT | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_NFS | \ + CFG_CMD_MII | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ + +#if (TEXT_BASE == 0xFFF00000) /* Boot low */ +# define CFG_LOWBOOT 1 +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addwdt=setenv bootargs ${bootargs} wdt=off" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp 300000 ${bootfile};run nfsargs addip addwdt;bootm\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +#define CONFIG_MISC_INIT_R 1 + +/* + * IPB Bus clocking configuration. + */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x58 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +/* for LM81 */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/* + * RTC configuration + */ +#define CONFIG_RTC_PCF8563 +#define CFG_I2C_RTC_ADDR 0x51 + +/* I2C SYSMON (LM75) */ +#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +/* + * Flash configuration + */ +#define CFG_FLASH_BASE 0xFF800000 + +#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ +#define CFG_MAX_FLASH_SECT 140 /* max num of sects on one chip */ + +#define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_CFI_AMD_RESET + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x4000 +#define CFG_ENV_SECT_SIZE 0x10000 +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SRAM_BASE 0x80100000 /* CS 1 */ +#define CFG_DISPLAY_BASE 0x80600000 /* CS 3 */ +#define CFG_IB_MASTER 0xc0510000 /* CS 6 */ +#define CFG_IB_EPLD 0xc0500000 /* CS 7 */ + +/* Settings for XLB = 132 MHz */ +#define SDRAM_DDR 1 +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +/* SRAM */ +#define SRAM_BASE CFG_SRAM_BASE /* SRAM base address */ +#define SRAM_LEN 0x1fffff +#define SRAM_END (SRAM_BASE + SRAM_LEN) + +/* Use ON-Chip SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#ifdef CONFIG_POST +/* preserve space for the post_word at end of on-chip SRAM */ +#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE +#else +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE +#endif + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_MII 1 + +/* + * GPIO configuration + */ +#define CFG_GPS_PORT_CONFIG 0x4d558044 + +/*use Hardware WDT */ +#define CONFIG_HW_WATCHDOG + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/* Enable an alternate, more extensive memory test */ +#define CFG_ALT_MEMTEST + +#define CFG_MEMTEST_START 0x00300000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 3 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x300000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, + * which is normally part of the default commands (CFV_CMD_DFL) + */ +#define CONFIG_LOOPW + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00045D00 +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +/* 8Mbit SRAM @0x80100000 */ +#define CFG_CS1_START CFG_SRAM_BASE +#define CFG_CS1_SIZE 0x00100000 +#define CFG_CS1_CFG 0x21D00 + +/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */ +#define CFG_CS3_START CFG_DISPLAY_BASE +#define CFG_CS3_SIZE 0x00000100 +#define CFG_CS3_CFG 0x00081802 + +/* Interbus Master 16 Bit */ +#define CFG_CS6_START CFG_IB_MASTER +#define CFG_CS6_SIZE 0x00010000 +#define CFG_CS6_CFG 0x00FF3500 + +/* Interbus EPLD 8 Bit */ +#define CFG_CS7_START CFG_IB_EPLD +#define CFG_CS7_SIZE 0x00010000 +#define CFG_CS7_CFG 0x00081800 + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ + +#define CONFIG_IDE_PREINIT 1 +/* #define CONFIG_IDE_RESET 1 beispile siehe tqm5200.c */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 + +#define CONFIG_ATAPI 1 + +/*---------------------------------------------------------------------*/ +/* Display addresses */ +/*---------------------------------------------------------------------*/ +#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38) +#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30) + +#endif /* __CONFIG_H */ diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 554a7a4..e19591d 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -39,6 +39,7 @@ #define CONFIG_NETCONSOLE 1 #define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* do board-specific init */ #define CFG_XLB_PIPELINING 1 /* gives better performance */ @@ -101,7 +102,7 @@ CFG_CMD_IRQ | \ CFG_CMD_JFFS2 | \ CFG_CMD_MII | \ - CFG_CMD_SDRAMi | \ + CFG_CMD_SDRAM | \ CFG_CMD_DATE | \ CFG_CMD_USB | \ CFG_CMD_FAT) @@ -135,7 +136,7 @@ "preboot=echo;echo Type \"run flash_nfs\" to mount root " \ "filesystem over NFS; echo\0" \ "netdev=eth0\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \ "addip=setenv bootargs $(bootargs) " \ "ip=$(ipaddr):$(serverip):$(gatewayip):" \ "$(netmask):$(hostname):$(netdev):off panic=1\0" \ @@ -144,7 +145,7 @@ "$(ramdisk_addr)\0" \ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=$(serverip):$(rootpath) wdt=off\0" \ "hostname=v38b\0" \ "ethact=FEC ETHERNET\0" \ "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \ diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h index 58717f8..911a52d 100644 --- a/include/configs/yellowstone.h +++ b/include/configs/yellowstone.h @@ -302,6 +302,20 @@ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#define CFG_FLASH CFG_FLASH_BASE +#define CFG_CPLD 0x80000000 + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x03017300 +#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000) + +/* Memory Bank 2 (CPLD) initialization */ +#define CFG_EBC_PB2AP 0x04814500 +#define CFG_EBC_PB2CR (CFG_CPLD | 0x18000) + +/*----------------------------------------------------------------------- * Cache Configuration */ #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 6e942ab..2cc18db 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -307,6 +307,20 @@ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#define CFG_FLASH CFG_FLASH_BASE +#define CFG_CPLD 0x80000000 + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x03017300 +#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000) + +/* Memory Bank 2 (CPLD) initialization */ +#define CFG_EBC_PB2AP 0x04814500 +#define CFG_EBC_PB2CR (CFG_CPLD | 0x18000) + +/*----------------------------------------------------------------------- * Cache Configuration */ #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ diff --git a/include/dtt.h b/include/dtt.h index a17aa67..842a761 100644 --- a/include/dtt.h +++ b/include/dtt.h @@ -29,6 +29,7 @@ #if defined(CONFIG_DTT_LM75) || \ defined(CONFIG_DTT_DS1621) || \ + defined(CONFIG_DTT_LM81) || \ defined(CONFIG_DTT_ADM1021) #define CONFIG_DTT /* We have a DTT */ @@ -58,6 +59,14 @@ extern int dtt_get_temp(int sensor); #define DTT_TEMP_SET 0x3 #endif +#if defined(CONFIG_DTT_LM81) +#define DTT_READ_TEMP 0x27 +#define DTT_CONFIG_TEMP 0x4b +#define DTT_TEMP_MAX 0x39 +#define DTT_TEMP_HYST 0x3a +#define DTT_CONFIG 0x40 +#endif + #if defined(CONFIG_DTT_DS1621) #define DTT_READ_TEMP 0xAA #define DTT_READ_COUNTER 0xA8 diff --git a/include/ppc440.h b/include/ppc440.h index 50f4ec4..91cff41 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -887,12 +887,14 @@ /* PLB4 Arbiter - PowerPC440EP Pass1 */ #define PLB4_DCR_BASE 0x080 +#define plb4_acr (PLB4_DCR_BASE+0x1) #define plb4_revid (PLB4_DCR_BASE+0x2) -#define plb4_acr (PLB4_DCR_BASE+0x3) #define plb4_besr (PLB4_DCR_BASE+0x4) #define plb4_bearl (PLB4_DCR_BASE+0x6) #define plb4_bearh (PLB4_DCR_BASE+0x7) +#define PLB4_ACR_WRP (0x80000000 >> 7) + /* Nebula PLB4 Arbiter - PowerPC440EP */ #define PLB_ARBITER_BASE 0x80 @@ -3284,26 +3286,26 @@ typedef struct { unsigned long add; /* gpio core base address */ /* * Macros for accessing the indirect EBC registers */ -#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) -#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd) +#define mtebc(reg, data) { mtdcr(ebccfga,reg);mtdcr(ebccfgd,data); } +#define mfebc(reg, data) { mtdcr(ebccfga,reg);data = mfdcr(ebccfgd); } /* * Macros for accessing the indirect SDRAM controller registers */ -#define mtsdram(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) -#define mfsdram(reg, data) mtdcr(memcfga,reg);data = mfdcr(memcfgd) +#define mtsdram(reg, data) { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } +#define mfsdram(reg, data) { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } /* * Macros for accessing the indirect clocking controller registers */ -#define mtclk(reg, data) mtdcr(clkcfga,reg);mtdcr(clkcfgd,data) -#define mfclk(reg, data) mtdcr(clkcfga,reg);data = mfdcr(clkcfgd) +#define mtclk(reg, data) { mtdcr(clkcfga,reg);mtdcr(clkcfgd,data); } +#define mfclk(reg, data) { mtdcr(clkcfga,reg);data = mfdcr(clkcfgd); } /* * Macros for accessing the sdr controller registers */ -#define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data) -#define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd) +#define mtsdr(reg, data) { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } +#define mfsdr(reg, data) { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } #ifndef __ASSEMBLY__ |