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-rw-r--r--include/configs/mx50_arm2.h6
-rw-r--r--include/configs/mx50_arm2_lpddr2.h7
-rw-r--r--include/fsl_esdhc.h10
-rw-r--r--include/mmc.h12
4 files changed, 32 insertions, 3 deletions
diff --git a/include/configs/mx50_arm2.h b/include/configs/mx50_arm2.h
index fbede97..4c23b95 100644
--- a/include/configs/mx50_arm2.h
+++ b/include/configs/mx50_arm2.h
@@ -201,10 +201,14 @@
#define CONFIG_CMD_FAT 1
#define CONFIG_CMD_EXT2 1
- /* detect whether ESDHC1 or ESDHC3 is boot device */
+ /* detect whether ESDHC1, ESDHC2, or ESDHC3 is boot device */
#define CONFIG_DYNAMIC_MMC_DEVNO
#define CONFIG_BOOT_PARTITION_ACCESS
+ #define CONFIG_EMMC_DDR_MODE
+
+ /* Indicate to esdhc driver which ports support 8-bit data */
+ #define CONFIG_MMC_8BIT_PORTS 0x6 /* ports 1 and 2 */
#endif
/*-----------------------------------------------------------------------
diff --git a/include/configs/mx50_arm2_lpddr2.h b/include/configs/mx50_arm2_lpddr2.h
index 505b859..a5683ad 100644
--- a/include/configs/mx50_arm2_lpddr2.h
+++ b/include/configs/mx50_arm2_lpddr2.h
@@ -202,10 +202,15 @@
#define CONFIG_CMD_FAT 1
#define CONFIG_CMD_EXT2 1
- /* detect whether ESDHC1 or ESDHC3 is boot device */
+ /* detect whether ESDHC1, ESDHC2, or ESDHC3 is boot device */
#define CONFIG_DYNAMIC_MMC_DEVNO
#define CONFIG_BOOT_PARTITION_ACCESS
+ #define CONFIG_EMMC_DDR_MODE
+
+ /* Indicate to esdhc driver which ports support 8-bit data */
+ #define CONFIG_MMC_8BIT_PORTS 0x6 /* ports 1 and 2 */
+
#endif
/*-----------------------------------------------------------------------
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 9f48afe..a0b1f5c 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -116,6 +116,7 @@
#define XFERTYP_RSPTYP_48_BUSY 0x00030000
#define XFERTYP_MSBSEL 0x00000020
#define XFERTYP_DTDSEL 0x00000010
+#define XFERTYP_DDR_EN 0x00000008
#define XFERTYP_AC12EN 0x00000004
#define XFERTYP_BCEN 0x00000002
#define XFERTYP_DMAEN 0x00000001
@@ -146,6 +147,15 @@
#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
#define ESDHC_HOSTCAPBLT_HSS 0x00200000
+#define ESDHC_HOSTVER_VVN_MASK 0x0000ff00
+#define ESDHC_HOSTVER_VVN_SHIFT 8
+#define ESDHC_HOSTVER_DDR_SUPPORT 0x13
+
+#define ESDHC_DLLCTRL_SLV_OVERRIDE_VAL 12
+#define ESDHC_DLLCTRL_SLV_OVERRIDE_VAL_MASK 0x0000FC00
+#define ESDHC_DLLCTRL_SLV_OVERRIDE_VAL_SHIFT 10
+#define ESDHC_DLLCTRL_SLV_OVERRIDE 0x200
+
struct fsl_esdhc_cfg {
u32 esdhc_base;
u32 no_snoop;
diff --git a/include/mmc.h b/include/mmc.h
index b8d6871..b450f4f 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -46,6 +46,8 @@
#define MMC_MODE_HS_52MHz 0x010
#define MMC_MODE_4BIT 0x100
#define MMC_MODE_8BIT 0x200
+#define EMMC_MODE_4BIT_DDR 0x400
+#define EMMC_MODE_8BIT_DDR 0x800
#define SD_DATA_4BIT 0x00040000
@@ -93,7 +95,7 @@
#define MMC_HS_TIMING 0x00000100
#define MMC_HS_52MHZ 0x2
-
+#define EMMC_MODE_DDR_3V 0x4
#define OCR_BUSY 0x80000000
#define OCR_HCS 0x40000000
@@ -131,6 +133,7 @@
* EXT_CSD fields
*/
+#define EXT_CSD_BOOT_BUS_WIDTH 177 /* RW */
#define EXT_CSD_BOOT_CONFIG 179 /* RW */
#define EXT_CSD_BUS_WIDTH 183 /* R/W */
#define EXT_CSD_HS_TIMING 185 /* R/W */
@@ -153,6 +156,13 @@
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
+#define EXT_CSD_BUS_WIDTH_4_DDR 5 /* eMMC 4.4 in 4-bit DDR mode */
+#define EXT_CSD_BUS_WIDTH_8_DDR 6 /* eMMC 4.4 in 8-bit DDR mode */
+
+#define EXT_CSD_BOOT_BUS_WIDTH_1BIT 0
+#define EXT_CSD_BOOT_BUS_WIDTH_4BIT 1
+#define EXT_CSD_BOOT_BUS_WIDTH_8BIT 2
+#define EXT_CSD_BOOT_BUS_WIDTH_DDR (1 << 4)
#define EXT_CSD_BOOT_PARTITION_ENABLE_MASK (0x7 << 3)
#define EXT_CSD_BOOT_PARTITION_DISABLE (0x0)