diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-mx28/clkctrl.h | 64 | ||||
| -rw-r--r-- | include/asm-arm/arch-mx28/dbguart.h | 30 | ||||
| -rw-r--r-- | include/asm-arm/arch-mx28/mx28.h | 11 | ||||
| -rw-r--r-- | include/asm-arm/arch-mx28/ocotp.h | 69 | ||||
| -rw-r--r-- | include/asm-arm/arch-mx28/pinmux.h | 42 | ||||
| -rw-r--r-- | include/asm-arm/arch-mx28/spi.h | 69 | ||||
| -rw-r--r-- | include/asm-arm/arch-mx28/ssp.h | 100 | ||||
| -rw-r--r-- | include/asm-arm/arch-mx28/timrot.h | 63 | ||||
| -rw-r--r-- | include/asm-arm/fec.h | 6 | ||||
| -rw-r--r-- | include/configs/mx28.h | 190 | ||||
| -rw-r--r-- | include/configs/mx28_evk.h | 140 |
11 files changed, 157 insertions, 627 deletions
diff --git a/include/asm-arm/arch-mx28/clkctrl.h b/include/asm-arm/arch-mx28/clkctrl.h deleted file mode 100644 index 76db80c..0000000 --- a/include/asm-arm/arch-mx28/clkctrl.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (C) 2008 Embedded Alley Solutions Inc. - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * Clock control register descriptions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef CLKCTRL_H -#define CLKCTRL_H - -#include <asm/arch/mx28.h> - -#define CLKCTRL_BASE (MX28_REGS_BASE + 0x40000) - -#define CLKCTRL_PLLCTRL0 0x000 -#define CLKCTRL_PLLCTRL1 0x010 -#define CLKCTRL_CPU 0x020 -#define CLKCTRL_HBUS 0x030 -#define CLKCTRL_XBUS 0x040 -#define CLKCTRL_XTAL 0x050 -#define CLKCTRL_PIX 0x060 -#define CLKCTRL_SSP 0x070 -#define CLKCTRL_GPMI 0x080 -#define CLKCTRL_SPDIF 0x090 -#define CLKCTRL_EMI 0x0a0 -#define CLKCTRL_IR 0x0b0 -#define CLKCTRL_SAIF 0x0c0 -#define CLKCTRL_TV 0x0d0 -#define CLKCTRL_ETM 0x0e0 -#define CLKCTRL_FRAC 0x0f0 -#define CLKCTRL_FRAC1 0x100 -#define CLKCTRL_CLKSEQ 0x110 -#define CLKCTRL_RESET 0x120 -#define CLKCTRL_STATUS 0x130 -#define CLKCTRL_VERSION 0x140 - -/* CLKCTRL_SSP register bits, bit fields and values */ -#define SSP_CLKGATE (1 << 31) -#define SSP_BUSY (1 << 29) -#define SSP_DIV_FRAC_EN (1 << 9) -#define SSP_DIV 0 - -/* CLKCTRL_FRAC register bits, bit fields and values */ -#define FRAC_CLKGATEIO (1 << 31) -#define FRAC_IOFRAC 24 - -/* CLKCTRL_FRAC register bits, bit fields and values */ -#define CLKSEQ_BYPASS_SSP (1 << 5) - -#endif /* CLKCTRL_H */ diff --git a/include/asm-arm/arch-mx28/dbguart.h b/include/asm-arm/arch-mx28/dbguart.h deleted file mode 100644 index b9a4bae..0000000 --- a/include/asm-arm/arch-mx28/dbguart.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2008 Embedded Alley Solutions Inc. - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * Debug UART register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef DBGUART_H -#define DBGUART_H - -#include <asm/arch/mx28.h> - -#define DBGUART_BASE (MX28_REGS_BASE + 0x00070000) - -#endif /* DBGUART_H */ diff --git a/include/asm-arm/arch-mx28/mx28.h b/include/asm-arm/arch-mx28/mx28.h index c050fdf..fc671ae 100644 --- a/include/asm-arm/arch-mx28/mx28.h +++ b/include/asm-arm/arch-mx28/mx28.h @@ -20,6 +20,17 @@ #ifndef __MX28_H #define __MX28_H +#ifndef __ASSEMBLER__ +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, +}; + +unsigned int mxc_get_clock(enum mxc_clock clk); +void enet_board_init(void); +#endif + /* * Most of i.MX28 SoC registers are associated with four addresses * used for different operations - read/write, set, clear and toggle bits. diff --git a/include/asm-arm/arch-mx28/ocotp.h b/include/asm-arm/arch-mx28/ocotp.h deleted file mode 100644 index 9396820..0000000 --- a/include/asm-arm/arch-mx28/ocotp.h +++ /dev/null @@ -1,69 +0,0 @@ -/* Copyright 2009 Freescale Semiconductor, Inc. - * - * On-Chip OTP register descriptions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef OCOTP_H -#define OCOTP_H - -#include <asm/arch/mx28.h> - -#define OCOTP_BASE (MX28_REGS_BASE + 0x2c000) - -#define OCOTP_CTRL 0x000 -#define OCOTP_CTRL_SET 0x004 -#define OCOTP_CTRL_CLR 0x008 -#define OCOTP_CTRL_TOG 0x00c -#define OCOTP_DATA 0x010 -#define OCOTP_CUST0 0x020 -#define OCOTP_CUST1 0x030 -#define OCOTP_CUST2 0x040 -#define OCOTP_CUST3 0x050 -#define OCOTP_CRYPTO1 0x070 -#define OCOTP_CRYPTO2 0x080 -#define OCOTP_CRYPTO3 0x090 -#define OCOTP_HWCAP0 0x0a0 -#define OCOTP_HWCAP1 0x0b0 -#define OCOTP_HWCAP2 0x0c0 -#define OCOTP_HWCAP3 0x0d0 -#define OCOTP_HWCAP4 0x0e0 -#define OCOTP_HWCAP5 0x0f0 -#define OCOTP_SWCAP 0x100 -#define OCOTP_CUSTCAP 0x110 -#define OCOTP_LOCK 0x120 -#define OCOTP_OPS0 0x130 -#define OCOTP_OPS1 0x140 -#define OCOTP_OPS2 0x150 -#define OCOTP_OPS3 0x160 -#define OCOTP_UN0 0x170 -#define OCOTP_UN1 0x180 -#define OCOTP_UN2 0x190 -#define OCOTP_ROM0 0x1a0 -#define OCOTP_ROM1 0x1b0 -#define OCOTP_ROM2 0x1c0 -#define OCOTP_ROM3 0x1d0 -#define OCOTP_ROM4 0x1e0 -#define OCOTP_ROM5 0x1f0 -#define OCOTP_ROM6 0x200 -#define OCOTP_ROM7 0x210 -#define OCOTP_VERSION 0x220 - - -/* OCOTP_CTRL register bits, bit fields and values */ -#define CTRL_RD_BANK_OPEN (1 << 12) -#define CTRL_BUSY (8 << 12) - -#endif /* OCOTP_H */ diff --git a/include/asm-arm/arch-mx28/pinmux.h b/include/asm-arm/arch-mx28/pinmux.h deleted file mode 100644 index db581bc..0000000 --- a/include/asm-arm/arch-mx28/pinmux.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2008 Embedded Alley Solutions Inc. - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * Clock control register descriptions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef PINMUX_H -#define PINMUX_H - -#include <asm/arch/mx28.h> - -#define PINCTRL_BASE (MX28_REGS_BASE + 0x18000) - -#define PINCTRL_CTRL 0x000 -#define PINCTRL_MUXSEL(n) (0x100 + 0x10*(n)) -#define PINCTRL_DRIVE(n) (0x200 + 0x10*(n)) -#define PINCTRL_PULL(n) (0x400 + 0x10*(n)) -#define PINCTRL_DOUT(n) (0x500 + 0x10*(n)) -#define PINCTRL_DIN(n) (0x600 + 0x10*(n)) -#define PINCTRL_DOE(n) (0x700 + 0x10*(n)) -#define PINCTRL_PIN2IRQ(n) (0x800 + 0x10*(n)) -#define PINCTRL_IRQEN(n) (0x900 + 0x10*(n)) -#define PINCTRL_IRQLEVEL(n) (0xa00 + 0x10*(n)) -#define PINCTRL_IRQPOL(n) (0xb00 + 0x10*(n)) -#define PINCTRL_IRQSTAT(n) (0xc00 + 0x10*(n)) - -#endif /* PINMUX_H */ diff --git a/include/asm-arm/arch-mx28/spi.h b/include/asm-arm/arch-mx28/spi.h deleted file mode 100644 index afd3245..0000000 --- a/include/asm-arm/arch-mx28/spi.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2008 Embedded Alley Solutions Inc. - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * SSP/SPI driver - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef SPI_H -#define SPI_H - -#include <config.h> -#include <common.h> -#include <asm/arch/ssp.h> - -/* - * Flags to set SPI mode - */ -#define SPI_PHASE 0x1 /* Set phase to 1 */ -#define SPI_POLARITY 0x2 /* Set polarity to 1 */ - -/* Various flags to control SPI transfers */ -#define SPI_START 0x1 /* Lock CS signal */ -#define SPI_STOP 0x2 /* Unlock CS signal */ - -/* - * Init SSPx interface, must be called first - */ -void spi_init(void); - -/* - * Set phase, polarity and CS number (SS0, SS1, SS2) - */ -void spi_set_cfg(unsigned int bus, unsigned int cs, unsigned long mode); - - -/* - * Send @rx_len bytes from @dout, then receive @rx_len bytes - * saving them to @din - */ -void spi_txrx(const char *dout, unsigned int tx_len, char *din, - unsigned int rx_len, unsigned long flags); - - -/* Lock/unlock SPI bus */ -static inline void spi_lock(void) -{ - disable_interrupts(); -} - -static inline void spi_unlock(void) -{ - enable_interrupts(); -} - -#endif /* SPI_H */ diff --git a/include/asm-arm/arch-mx28/ssp.h b/include/asm-arm/arch-mx28/ssp.h deleted file mode 100644 index f6e8e28..0000000 --- a/include/asm-arm/arch-mx28/ssp.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (C) 2008 Embedded Alley Solutions Inc. - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * SSP register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef SSP_H -#define SSP_H - -#include <asm/arch/mx28.h> - -#define SSP1_BASE (MX28_REGS_BASE + 0x10000) -#define SSP2_BASE (MX28_REGS_BASE + 0x34000) - -#define SSP_CTRL0 0x000 -#define SSP_CMD0 0x010 -#define SSP_CMD1 0x020 -#define SSP_COMPREF 0x030 -#define SSP_COMPMASK 0x040 -#define SSP_TIMING 0x050 -#define SSP_CTRL1 0x060 -#define SSP_DATA 0x070 -#define SSP_SDRESP0 0x080 -#define SSP_SDRESP1 0x090 -#define SSP_SDRESP2 0x0a0 -#define SSP_SDRESP3 0x0b0 -#define SSP_STATUS 0x0c0 -#define SSP_DEBUG 0x100 -#define SSP_VERSION 0x110 - -/* CTRL0 bits, bit fields and values */ -#define CTRL0_SFTRST (0x1 << 31) -#define CTRL0_CLKGATE (0x1 << 30) -#define CTRL0_RUN (0x1 << 29) -#define CTRL0_LOCK_CS (0x1 << 27) -#define CTRL0_IGNORE_CRC (0x1 << 26) -#define CTRL0_DATA_XFER (0x1 << 24) -#define CTRL0_READ (0x1 << 25) -#define CTRL0_BUS_WIDTH 22 -#define CTRL0_WAIT_FOR_IRQ (0x1 << 21) -#define CTRL0_WAIT_FOR_CMD (0x1 << 20) -#define CTRL0_XFER_COUNT 0 - -#define BUS_WIDTH_SPI1 (0x0 << CTRL0_BUS_WIDTH) -#define BUS_WIDTH_SPI4 (0x1 << CTRL0_BUS_WIDTH) -#define BUS_WIDTH_SPI8 (0x2 << CTRL0_BUS_WIDTH) - -#define SPI_CS0 0x0 -#define SPI_CS1 CTRL0_WAIT_FOR_CMD -#define SPI_CS2 CTRL0_WAIT_FOR_IRQ -#define SPI_CS_CLR_MASK (CTRL0_WAIT_FOR_CMD | CTRL0_WAIT_FOR_IRQ) - -/* CMD0 bits, bit fields and values */ -#define CMD0_BLOCK_SIZE 16 -#define CMD0_BLOCK_COUNT 12 -#define CMD0_CMD 0 - -/* TIMING bits, bit fields and values */ -#define TIMING_TIMEOUT 16 -#define TIMING_CLOCK_DIVIDE 8 -#define TIMING_CLOCK_RATE 0 - -/* CTRL1 bits, bit fields and values */ -#define CTRL1_DMA_ENABLE (0x1 << 13) -#define CTRL1_PHASE (0x1 << 10) -#define CTRL1_POLARITY (0x1 << 9) -#define CTRL1_SLAVE_MODE (0x1 << 8) -#define CTRL1_WORD_LENGTH 4 -#define CTRL1_SSP_MODE 0 - -#define WORD_LENGTH4 (0x3 << CTRL1_WORD_LENGTH) -#define WORD_LENGTH8 (0x7 << CTRL1_WORD_LENGTH) -#define WORD_LENGTH16 (0xF << CTRL1_WORD_LENGTH) - -#define SSP_MODE_SPI (0x0 << CTRL1_SSP_MODE) -#define SSP_MODE_SSI (0x1 << CTRL1_SSP_MODE) -#define SSP_MODE_SD_MMC (0x3 << CTRL1_SSP_MODE) -#define SSP_MODE_MS (0x4 << CTRL1_SSP_MODE) -#define SSP_MODE_ATA (0x7 << CTRL1_SSP_MODE) - -/* CTRL1 bits, bit fields and values */ -#define STATUS_FIFO_EMPTY (1 << 5) -#define STATUS_FIFO_FULL (1 << 8) - -#endif /* SSP_H */ diff --git a/include/asm-arm/arch-mx28/timrot.h b/include/asm-arm/arch-mx28/timrot.h deleted file mode 100644 index ec9e716..0000000 --- a/include/asm-arm/arch-mx28/timrot.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (C) 2008 Embedded Alley Solutions Inc. - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * Timers and rotary encoder register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef TIMROT_H -#define TIMROT_H - -#include <asm/arch/mx28.h> - -#define TIMROT_BASE (MX28_REGS_BASE + 0x00068000) - -/* Timer and rotary encoder register offsets */ -#define ROTCTRL 0x0 -#define ROTCOUNT 0x10 -#define TIMCTRL0 0x20 -#define TIMCOUNT0 0x30 -#define TIMCTRL1 0x40 -#define TIMCOUNT1 0x50 -#define TIMCTRL2 0x60 -#define TIMCOUNT2 0x70 -#define TIMCTRL3 0x80 -#define TIMCTRL3 0x90 - -/* TIMCTRL bits, bit fields and values */ -#define TIMCTRL_SELECT 0 -#define TIMCTRL_PRESCALE 4 -#define TIMCTRL_RELOAD (1 << 6) -#define TIMCTRL_UPDATE (1 << 7) -#define TIMCTRL_POLARITY (1 << 8) -#define TIMCTRL_IRQEN (1 << 14) -#define TIMCTRL_IRQ (1 << 15) - -#define TIMCTRL_SELECT_PWM0 (0x1 << TIMCTRL_SELECT) -#define TIMCTRL_SELECT_PWM1 (0x2 << TIMCTRL_SELECT) -#define TIMCTRL_SELECT_PWM2 (0x3 << TIMCTRL_SELECT) -#define TIMCTRL_SELECT_PWM3 (0x4 << TIMCTRL_SELECT) -#define TIMCTRL_SELECT_PWM4 (0x5 << TIMCTRL_SELECT) -#define TIMCTRL_SELECT_ROTARYA (0x6 << TIMCTRL_SELECT) -#define TIMCTRL_SELECT_ROTARYB (0x7 << TIMCTRL_SELECT) -#define TIMCTRL_SELECT_32KHZ (0x8 << TIMCTRL_SELECT) -#define TIMCTRL_SELECT_8KHZ (0x9 << TIMCTRL_SELECT) -#define TIMCTRL_SELECT_4KHZ (0xa << TIMCTRL_SELECT) -#define TIMCTRL_SELECT_1KHZ (0xb << TIMCTRL_SELECT) -#define TIMCTRL_SELECT_ALWAYS (0xc << TIMCTRL_SELECT) - -#endif /* TIMROT_H */ diff --git a/include/asm-arm/fec.h b/include/asm-arm/fec.h index 4e81fa0..226bb26 100644 --- a/include/asm-arm/fec.h +++ b/include/asm-arm/fec.h @@ -261,4 +261,10 @@ typedef struct fec { #define FEC_MAX_TIMEOUT 50000 #define FEC_TIMEOUT_TICKET 2 + +/* + * Functions + */ +int mxc_fec_initialize(bd_t *bis); + #endif /* fec_h */ diff --git a/include/configs/mx28.h b/include/configs/mx28.h deleted file mode 100644 index b119f76..0000000 --- a/include/configs/mx28.h +++ /dev/null @@ -1,190 +0,0 @@ -/* - * Copyright (C) 2008 Embedded Alley Solutions, Inc. - * - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H -#include <asm/sizes.h> - -/* - * Define this to make U-Boot skip low level initialization when loaded - * by initial bootloader. Not required by NAND U-Boot version but IS - * required for a NOR version used to burn the real NOR U-Boot into - * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive - * so it is NOT possible to build a U-Boot with both NAND and NOR routines. - * NOR U-Boot is loaded directly from Flash so it must perform all the - * low level initialization itself. NAND version is loaded by an initial - * bootloader (UBL in TI-ese) that performs such an initialization so it's - * skipped in NAND version. The third DaVinci boot mode loads a bootloader - * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever) - * performing low level init prior to loading. All that means we can NOT use - * NAND version to put U-Boot into NOR because it doesn't have NOR support and - * we can NOT use NOR version because it performs low level initialization - * effectively destroying itself in DDR memory. That's why a separate NOR - * version with this define is needed. It is loaded via UART, then one uses - * it to somehow download a proper NOR version built WITHOUT this define to - * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze - * NOR support into the initial bootloader so it won't be needed but DaVinci - * static RAM might be too small for this (I have something like 2Kbytes left - * as of now, without NOR support) so this might've not happened... - * - */ - -/*===================*/ -/* SoC Configuration */ -/*===================*/ -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ -#define CONFIG_MX28 /* STMP378x SoC */ -#define CONFIG_SYS_CLK_FREQ 120000000 /* Arm Clock frequency */ -#define CONFIG_USE_TIMER0 /* use timer 0 */ -#define CONFIG_SYS_HZ 1000 /* Ticks per second */ -/*=============*/ -/* Memory Info */ -/*=============*/ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */ -#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest start address */ -#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 16MB RAM test */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define CONFIG_STACKSIZE (256*1024) /* regular stack */ -#define PHYS_SDRAM_1 0x40000000 /* mDDR Start */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* mDDR size 32MB */ - -/*====================*/ -/* Serial Driver info */ -/*====================*/ -#define CONFIG_DBGUART_CLK 24000000 -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*====================*/ -/* SPI Driver info */ -/*====================*/ -#define CONFIG_SSP_CLK 48000000 -#define CONFIG_SPI_CLK 3000000 -#define CONFIG_SPI_SSP1 -#undef CONFIG_SPI_SSP2 - -/*=====================*/ -/* Flash & Environment */ -/*=====================*/ -#define CONFIG_SYS_NO_FLASH /* Flash is not supported */ -#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ - - -/* ROM loads UBOOT into DRAM */ -#define CONFIG_SKIP_RELOCATE_UBOOT - - -/*==============================*/ -/* U-Boot general configuration */ -/*==============================*/ -#define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_PROMPT "MX28 U-Boot > " -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ -#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ -#define CONFIG_AUTO_COMPLETE /* Command auto complete */ -#define CONFIG_CMDLINE_EDITING /* Command history etc */ -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#define CONFIG_CMDLINE_EDITING -#define CFG_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC - -/* - * Boot Linux - */ -#define LINUX_BOOT_PARAM_ADDR 0x40000100 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS "console=ttyAM0,115200n8 " -#define CONFIG_BOOTCOMMAND "run bootcmd_net" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* - * Extra Environments - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfsroot=/data/rootfs_home/rootfs\0" \ - "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "bootcmd_net=run bootargs_nfs; dhcp; bootm\0" \ - "bootargs_mmc=setenv bootargs ${bootargs} root=/dev/mmcblk0p2 " \ - "ip=dhcp rootfstype=ext2\0" \ - "bootcmd_mmc=run bootargs_mmc; " \ - "mmc read 0 ${loadaddr} 100 3000; bootm\0" \ - -/*=================*/ -/* U-Boot commands */ -/*=================*/ -#include <config_cmd_default.h> -#undef CONFIG_CMD_MMC /* MX28 use special mmc command*/ -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO - -/* - * ENET Driver - */ -#define CONFIG_MXC_ENET -#define CONFIG_NET_MULTI -#define CONFIG_ETH_PRIME -#define CONFIG_CMD_MII -#define CONFIG_DISCOVER_PHY -#define CONFIG_CMD_DHCP -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_DNS -#define CONFIG_CMD_PING -#define CONFIG_IPADDR 192.168.1.101 -#define CONFIG_SERVERIP 192.168.1.100 -#define CONFIG_NETMASK 255.255.255.0 - -/* - * MMC Driver - */ -#define CONFIG_IMX_SSP_MMC /* MMC driver based on SSP */ -#define CONFIG_GENERIC_MMC -#define CONFIG_CUSTOMIZE_MMCOPS /* To customize do_mmcops() */ -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_FAT -#define CONFIG_MMC - -/* - * Environments on MMC - */ -#define CONFIG_CMD_ENV -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_IS_IN_MMC -/* Assoiated with the MMC layout defined in mmcops.c */ -#define CONFIG_ENV_OFFSET (0x400) /* 1 KB */ -#define CONFIG_ENV_SIZE (0x20000 - 0x400) /* 127 KB */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx28_evk.h b/include/configs/mx28_evk.h new file mode 100644 index 0000000..fa6069e --- /dev/null +++ b/include/configs/mx28_evk.h @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __MX28_EVK_H +#define __MX28_EVK_H + +#include <asm/arch/mx28.h> + +/* + * SoC configurations + */ +#define CONFIG_MX28 /* i.MX28 SoC */ +#define CONFIG_SYS_HZ 1000 /* Ticks per second */ +/* ROM loads UBOOT into DRAM */ +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Memory configurations + */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define CONFIG_STACKSIZE 0x00020000 /* 128 KB stack */ +#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Reserved for initial data */ +#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start address */ +#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_PROMPT "MX28 U-Boot > " +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ + +/* + * Boot Linux + */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyAM0,115200n8 " +#define CONFIG_BOOTCOMMAND "run bootcmd_net" +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* + * Extra Environments + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "nfsroot=/home/notroot/nfs/rootfs\0" \ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \ + "fec_mac=${ethaddr}\0" \ + "bootcmd_net=run bootargs_nfs; dhcp; bootm\0" \ + "bootargs_mmc=setenv bootargs ${bootargs} root=/dev/mmcblk0p3 " \ + "rw rootwait ip=dhcp fec_mac=${ethaddr}\0" \ + "bootcmd_mmc=run bootargs_mmc; " \ + "mmc read 0 ${loadaddr} 100 3000; bootm\0" \ + +/* + * U-Boot Commands + */ +#define CONFIG_SYS_NO_FLASH +#include <config_cmd_default.h> +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO + +/* + * Serial Driver + */ +#define CONFIG_UARTDBG_CLK 24000000 +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * FEC Driver + */ +#define CONFIG_MXC_FEC +#define CONFIG_FEC0_IOBASE REGS_ENET_BASE +#define CONFIG_FEC0_PHY_ADDR 0 +#define CONFIG_NET_MULTI +#define CONFIG_ETH_PRIME +#define CONFIG_CMD_MII +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_IPADDR 192.168.1.103 +#define CONFIG_SERVERIP 192.168.1.101 +#define CONFIG_NETMASK 255.255.255.0 +/* Add for working with "strict" DHCP server */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + + +/* + * MMC Driver + */ +#define CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_IMX_SSP_MMC /* MMC driver based on SSP */ +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT + +/* + * Environments on MMC + */ +#define CONFIG_CMD_ENV +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_IS_IN_MMC +/* Assoiated with the MMC layout defined in mmcops.c */ +#define CONFIG_ENV_OFFSET (0x400) /* 1 KB */ +#define CONFIG_ENV_SIZE (0x20000 - 0x400) /* 127 KB */ + +#endif /* __MX28_EVK_H */ |