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-rw-r--r--include/asm-mips/addrspace.h2
-rw-r--r--include/configs/MPC8266ADS.h2
-rw-r--r--include/configs/MPC8541CDS.h1
-rw-r--r--include/configs/MPC8548CDS.h1
-rw-r--r--include/configs/MPC8555CDS.h1
-rw-r--r--include/configs/MPC8568MDS.h2
-rw-r--r--include/configs/TQM5200.h2
-rw-r--r--include/configs/TQM860M.h13
-rw-r--r--include/configs/TQM866M.h49
9 files changed, 46 insertions, 27 deletions
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index b8214b1..0e6abd7 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -49,7 +49,7 @@
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
#else /* !CONFIG_AU1X00 */
-#define UNCACHED_SDRAM(a) PHYSADDR(a)
+#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
#endif /* CONFIG_AU1X00 */
#endif /* __ASSEMBLY__ */
/*
diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
index 14b041e..d392b98 100644
--- a/include/configs/MPC8266ADS.h
+++ b/include/configs/MPC8266ADS.h
@@ -168,6 +168,7 @@
#undef CONFIG_CMD_MFSL
#undef CONFIG_CMD_MMC
#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_ONENAND
#undef CONFIG_CMD_PCMCIA
#undef CONFIG_CMD_REISER
#undef CONFIG_CMD_SCSI
@@ -177,6 +178,7 @@
#undef CONFIG_CMD_UNIVERSE
#undef CONFIG_CMD_USB
#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_AT91_SPIMUX
/* Define a command string that is automatically executed when no character
* is read on the console interface withing "Boot Delay" after reset.
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 4e061bd..8dda665 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -316,6 +316,7 @@ extern unsigned long get_clock_freq(void);
#define OF_SOC "soc8541@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600"
+#define OF_PCI "pci@e0008000"
/*
* I2C
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 6083715..4edc7fd 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -340,6 +340,7 @@ extern unsigned long get_clock_freq(void);
#define OF_SOC "soc8548@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600"
+#define OF_PCI "pci@e0008000"
/*
* I2C
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 1d1b7c9..c414bf0 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -316,6 +316,7 @@ extern unsigned long get_clock_freq(void);
#define OF_SOC "soc8555@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600"
+#define OF_PCI "pci@e0008000"
/*
* I2C
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index ba744e9..548e158 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -297,7 +297,7 @@ extern unsigned long get_clock_freq(void);
#define OF_SOC "soc8568@e0000000"
#define OF_QE "qe@e0080000"
#define OF_TBCLK (bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600"
+#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4500"
/*
* I2C
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index d553404..c3f16f5 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -547,7 +547,7 @@
# if defined (CONFIG_TQM5200_REV100)
# error TQM5200 REV100 not supported on STK52XX REV200 or above
# else/* TQM5200 REV200 and above */
-# define CFG_GPS_PORT_CONFIG 0x91500004
+# define CFG_GPS_PORT_CONFIG 0x91500404
# endif
# endif
#elif defined (CONFIG_FO300)
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 684b86f..fe3a2f0 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -69,9 +69,14 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM860M/uImage\0" \
- "fdt_addr=40080000\0" \
- "kernel_addr=400A0000\0" \
+ "fdt_addr=400C0000\0" \
+ "kernel_addr=40100000\0" \
"ramdisk_addr=40280000\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=protect off 40000000 +${filesize};" \
+ "erase 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "protect on 40000000 +${filesize}\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -172,7 +177,7 @@
#define CFG_FLASH_BASE 0x40000000
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
/*
* For booting Linux, the board info and command line data
@@ -193,7 +198,7 @@
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index 0d77891..ca3c166 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -81,9 +81,14 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM866M/uImage\0" \
- "fdt_addr=40080000\0" \
- "kernel_addr=400A0000\0" \
+ "fdt_addr=400C0000\0" \
+ "kernel_addr=40100000\0" \
"ramdisk_addr=40280000\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=protect off 40000000 +${filesize};" \
+ "erase 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "protect on 40000000 +${filesize}\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -215,7 +220,7 @@
#define CFG_FLASH_BASE 0x40000000
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
/*
* For booting Linux, the board info and command line data
@@ -236,7 +241,7 @@
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
@@ -421,26 +426,30 @@
#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
/*
- * Memory Periodic Timer Prescaler
- * Periodic timer for refresh, start with refresh rate for 40 MHz clock
- * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
+ * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
+ *
+ * CPUclock(MHz) * 31.2
+ * CFG_MAMR_PTA = ----------------------------------- with DFBRG = 0
+ * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
+ *
+ * CPU clock = 15 MHz: CFG_MAMR_PTA = 29 -> 4 * 7.73 us
+ * CPU clock = 50 MHz: CFG_MAMR_PTA = 97 -> 4 * 7.76 us
+ * CPU clock = 66 MHz: CFG_MAMR_PTA = 128 -> 4 * 7.75 us
+ * CPU clock = 133 MHz: CFG_MAMR_PTA = 255 -> 4 * 7.67 us
+ *
+ * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
+ * be met also in the default configuration, i.e. if environment variable
+ * 'cpuclk' is not set.
*/
-#define CFG_MAMR_PTA 39
+#define CFG_MAMR_PTA 97
/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
- * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
+ * Memory Periodic Timer Prescaler Register (MPTPR) values.
*/
-#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
+/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
+#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16
+/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
+#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8
/*
* MAMR settings for SDRAM
generated by cgit v1.1 at 2024-11-17 04:26:48 +0000