diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-mx51/imx_spi.h | 66 | ||||
| -rw-r--r-- | include/asm-arm/arch-mx51/imx_spi_nor.h | 54 | ||||
| -rw-r--r-- | include/asm-arm/arch-mx51/imx_spi_pmic.h | 33 | ||||
| -rw-r--r-- | include/asm-arm/arch-mx51/mx51.h | 1 | ||||
| -rw-r--r-- | include/configs/imx51.h | 27 |
5 files changed, 179 insertions, 2 deletions
diff --git a/include/asm-arm/arch-mx51/imx_spi.h b/include/asm-arm/arch-mx51/imx_spi.h new file mode 100644 index 0000000..c9d51e9 --- /dev/null +++ b/include/asm-arm/arch-mx51/imx_spi.h @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMX_SPI_H__ +#define __IMX_SPI_H__ + +#include <spi.h> + +#undef IMX_SPI_DEBUG + +#define IMX_SPI_ACTIVE_HIGH 1 +#define IMX_SPI_ACTIVE_LOW 0 +#define SPI_RETRY_TIMES 100 + +#define SPI_RX_DATA 0x0 +#define SPI_TX_DATA 0x4 +#define SPI_CON_REG 0x8 +#define SPI_CFG_REG 0xc +#define SPI_INT_REG 0x10 +#define SPI_DMA_REG 0x14 +#define SPI_STAT_REG 0x18 +#define SPI_PERIOD_REG 0x1C + +struct spi_reg_t { + u32 ctrl_reg; + u32 cfg_reg; +}; + +struct imx_spi_dev_t { + struct spi_slave slave; + u32 base; /* base address of SPI module the device is connected to */ + u32 freq; /* desired clock freq in Hz for this device */ + u32 ss_pol; /* ss polarity: 1=active high; 0=active low */ + u32 ss; /* slave select */ + u32 in_sctl; /* inactive sclk ctl: 1=stay low; 0=stay high */ + u32 in_dctl; /* inactive data ctl: 1=stay low; 0=stay high */ + u32 ssctl; /* single burst mode vs multiple: 0=single; 1=multi */ + u32 sclkpol; /* sclk polarity: active high=0; active low=1 */ + u32 sclkpha; /* sclk phase: 0=phase 0; 1=phase1 */ + u32 fifo_sz; /* fifo size in bytes for either tx or rx. Don't add them up! */ + u32 us_delay; /* us delay in each xfer */ + struct spi_reg_t reg; /* pointer to a set of SPI registers */ +}; + +extern void spi_io_init(struct imx_spi_dev_t *dev); + +#endif /* __IMX_SPI_H__ */ diff --git a/include/asm-arm/arch-mx51/imx_spi_nor.h b/include/asm-arm/arch-mx51/imx_spi_nor.h new file mode 100644 index 0000000..a12247b --- /dev/null +++ b/include/asm-arm/arch-mx51/imx_spi_nor.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _IMX_SPI_NOR_H_ +#define _IMX_SPI_NOR_H_ + +#define READ 0x03 /* tx: 1 byte cmd + 3 byte addr; rx: variable bytes */ +#define READ_HS 0x0B /* tx: 1 byte cmd + 3 byte addr + 1 byte dummy; rx: variable bytes */ +#define RDSR 0x05 /* read status register 1 byte tx cmd + 1 byte rx status */ +#define RDSR_BUSY (1 << 0) /* 1=write-in-progress (default 0) */ +#define RDSR_WEL (1 << 1) /* 1=write enable (default 0) */ +#define RDSR_BP0 (1 << 2) /* block write prot level (default 1) */ +#define RDSR_BP1 (1 << 3) /* block write prot level (default 1) */ +#define RDSR_BP2 (1 << 4) /* block write prot level (default 1) */ +#define RDSR_BP3 (1 << 5) /* block write prot level (default 1) */ +#define RDSR_AAI (1 << 6) /* 1=AAI prog mode; 0=byte prog (default 0) */ +#define RDSR_BPL (1 << 7) /* 1=BP3,BP2,BP1,BP0 RO; 0=R/W (default 0) */ +#define WREN 0x06 /* write enable. 1 byte tx cmd */ +#define WRDI 0x04 /* write disable. 1 byte tx cmd */ +#define EWSR 0x50 /* Enable write status. 1 byte tx cmd */ +#define WRSR 0x01 /* Write status register. 1 byte tx cmd + 1 byte tx value */ +#define ERASE_4K 0x20 /* sector erase. 1 byte cmd + 3 byte addr */ +#define ERASE_32K 0x52 /* 32K block erase. 1 byte cmd + 3 byte addr */ +#define ERASE_64K 0xD8 /* 64K block erase. 1 byte cmd + 3 byte addr */ +#define ERASE_CHIP 0x60 /* whole chip erase */ +#define BYTE_PROG 0x02 /* all tx: 1 cmd + 3 addr + 1 data */ +#define AAI_PROG 0xAD /* all tx: [1 cmd + 3 addr + 2 data] + RDSR */ + /* + [1cmd + 2 data] + .. + [WRDI] + [RDSR] */ +#define JEDEC_ID 0x9F /* read JEDEC ID. tx: 1 byte cmd; rx: 3 byte ID */ + +#define SZ_64K 0x10000 +#define SZ_32K 0x8000 +#define SZ_4K 0x1000 + +#endif /* _IMX_SPI_NOR_H_ */ diff --git a/include/asm-arm/arch-mx51/imx_spi_pmic.h b/include/asm-arm/arch-mx51/imx_spi_pmic.h new file mode 100644 index 0000000..1c32a9e --- /dev/null +++ b/include/asm-arm/arch-mx51/imx_spi_pmic.h @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _IMX_SPI_PMIC_H_ +#define _IMX_SPI_PMIC_H_ + +#include <linux/types.h> + +struct spi_slave *spi_pmic_probe(); +void spi_pmic_free(struct spi_slave *slave); +u32 pmic_reg(struct spi_slave *slave, + u32 reg, u32 val, u32 write); + +#endif /* _IMX_SPI_PMIC_H_ */ diff --git a/include/asm-arm/arch-mx51/mx51.h b/include/asm-arm/arch-mx51/mx51.h index 566251b..29120ab 100644 --- a/include/asm-arm/arch-mx51/mx51.h +++ b/include/asm-arm/arch-mx51/mx51.h @@ -404,6 +404,7 @@ MXC_AHB_CLK, MXC_IPG_CLK, MXC_IPG_PERCLK, MXC_UART_CLK, +MXC_CSPI_CLK, }; extern unsigned int mxc_get_clock(enum mxc_clock clk); diff --git a/include/configs/imx51.h b/include/configs/imx51.h index 4ab1acb..1808b67 100644 --- a/include/configs/imx51.h +++ b/include/configs/imx51.h @@ -68,8 +68,25 @@ #define CONFIG_MX51_UART 1 #define CONFIG_MX51_UART1 1 +/* + * SPI Configs + * */ +/* +#define CONFIG_FSL_SF 1 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_IMX +#define CONFIG_SPI_FLASH_CS 1 +#define CONFIG_IMX_SPI +#define CONFIG_IMX_SPI_PMIC +#define CONFIG_IMX_SPI_PMIC_CS 0 + +#define MAX_SPI_BYTES (64 * 4) +*/ -/* #define CONFIG_CMD_SPI */ +/* + * MMC Configs + * */ /* #define CONFIG_FSL_MMC 1 @@ -190,7 +207,9 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 /* Monitor at beginning of flash */ -#if defined(CONFIG_FSL_MMC) +#if defined(CONFIG_FSL_SF) + #define CONFIG_FSL_ENV_IN_SF +#elif defined(CONFIG_FSL_MMC) #define CONFIG_MMC 1 #define CONFIG_CMD_MMC /* @@ -209,6 +228,10 @@ #elif defined(CONFIG_FSL_ENV_IN_MMC) #define CONFIG_ENV_IS_IN_MMC 1 #define CONFIG_ENV_OFFSET (1024 * 1024) +#elif defined(CONFIG_FSL_ENV_IN_SF) + #define CONFIG_ENV_IS_IN_SPI_FLASH 1 + #define CONFIG_ENV_SPI_CS 1 + #define CONFIG_ENV_OFFSET (1024 * 1024) #else #define CONFIG_ENV_IS_NOWHERE 1 #endif |