diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-mx28/pinctrl.h | 18 | ||||
| -rw-r--r-- | include/configs/mx28_evk.h | 10 | ||||
| -rw-r--r-- | include/imx_ssp_mmc.h | 50 |
3 files changed, 73 insertions, 5 deletions
diff --git a/include/asm-arm/arch-mx28/pinctrl.h b/include/asm-arm/arch-mx28/pinctrl.h index 25a2e64..6f0eea0 100644 --- a/include/asm-arm/arch-mx28/pinctrl.h +++ b/include/asm-arm/arch-mx28/pinctrl.h @@ -106,6 +106,19 @@ extern void pin_set_group(struct pin_group *pin_group); #define PINID_GPMI_CLE PINID_ENCODE(0, 27) #define PINID_GPMI_RESETN PINID_ENCODE(0, 28) +#define PINID_SSP1_DATA0 PINID_ENCODE(0, 0) +#define PINID_SSP1_DATA1 PINID_ENCODE(0, 1) +#define PINID_SSP1_DATA2 PINID_ENCODE(0, 2) +#define PINID_SSP1_DATA3 PINID_ENCODE(0, 3) +#define PINID_SSP1_DATA4 PINID_ENCODE(0, 4) +#define PINID_SSP1_DATA5 PINID_ENCODE(0, 5) +#define PINID_SSP1_DATA6 PINID_ENCODE(0, 6) +#define PINID_SSP1_DATA7 PINID_ENCODE(0, 7) +#define PINID_SSP1_DETECT PINID_ENCODE(0, 20) +#define PINID_SSP1_CMD PINID_ENCODE(0, 21) +#define PINID_SSP1_SCK PINID_ENCODE(0, 25) +#define PINID_SSP1_GPIO_WP PINID_ENCODE(0, 28) + /* Bank 1 */ #define PINID_LCD_D00 PINID_ENCODE(1, 0) #define PINID_LCD_D01 PINID_ENCODE(1, 1) @@ -152,10 +165,7 @@ extern void pin_set_group(struct pin_group *pin_group); #define PINID_SSP0_CMD PINID_ENCODE(2, 8) #define PINID_SSP0_DETECT PINID_ENCODE(2, 9) #define PINID_SSP0_SCK PINID_ENCODE(2, 10) -#define PINID_SSP1_SCK PINID_ENCODE(2, 12) -#define PINID_SSP1_CMD PINID_ENCODE(2, 13) -#define PINID_SSP1_DATA0 PINID_ENCODE(2, 14) -#define PINID_SSP1_DATA3 PINID_ENCODE(2, 15) +#define PINID_SSP0_GPIO_WP PINID_ENCODE(2, 12) #define PINID_SSP2_SCK PINID_ENCODE(2, 16) #define PINID_SSP2_MOSI PINID_ENCODE(2, 17) #define PINID_SSP2_MISO PINID_ENCODE(2, 18) diff --git a/include/configs/mx28_evk.h b/include/configs/mx28_evk.h index 8f0b31a..5da0b05 100644 --- a/include/configs/mx28_evk.h +++ b/include/configs/mx28_evk.h @@ -119,7 +119,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_DNS - /* * MMC Driver */ @@ -130,6 +129,7 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_DOS_PARTITION #define CONFIG_CMD_FAT +#define CONFIG_SYS_SSP_MMC_NUM 2 /* * Environments on MMC @@ -140,5 +140,13 @@ /* Assoiated with the MMC layout defined in mmcops.c */ #define CONFIG_ENV_OFFSET (0x400) /* 1 KB */ #define CONFIG_ENV_SIZE (0x20000 - 0x400) /* 127 KB */ +#define CONFIG_DYNAMIC_MMC_DEVNO + +/* The global boot mode has been detected by Boot ROM and a boot mode value + * is stored at address of 0x0001a7f0. + */ +#define GLOBAL_BOOT_MODE_ADDR 0x0001a7f0 +#define BOOT_MODE_SD0 0x9 +#define BOOT_MODE_SD1 0xa #endif /* __MX28_EVK_H */ diff --git a/include/imx_ssp_mmc.h b/include/imx_ssp_mmc.h new file mode 100644 index 0000000..a3c157d --- /dev/null +++ b/include/imx_ssp_mmc.h @@ -0,0 +1,50 @@ +/* + * IMX SSP MMC Defines + *------------------------------------------------------------------- + * + * Copyright (C) 2007-2008, 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + *------------------------------------------------------------------- + * + */ + +#ifndef __IMX_SSP_MMC_H__ +#define __IMX_SSP_MMC_H__ + +/* Common definition */ +#define BM_CLKCTRL_SSP_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP_BUSY 0x20000000 +#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200 +#define BM_CLKCTRL_SSP_DIV 0x000001FF +#define BP_CLKCTRL_SSP_DIV 0 + +struct imx_ssp_mmc_cfg { + u32 ssp_mmc_base; + + /* CLKCTRL register offset */ + u32 clkctrl_ssp_offset; + u32 clkctrl_clkseq_ssp_offset; +}; + +#ifdef CONFIG_IMX_SSP_MMC +int imx_ssp_mmc_initialize(bd_t *bis, struct imx_ssp_mmc_cfg *cfg); + +extern u32 ssp_mmc_is_wp(struct mmc *mmc); +#endif /* CONFIG_IMX_SSP_MMC */ + +#endif /* __IMX_SSP_MMC_H__ */ |