745 files changed, 56476 insertions, 43063 deletions

diff --git a/include/.gitignore b/include/.gitignore
index ef7dd5f..4481412 100644
--- a/include/.gitignore
+++ b/include/.gitignore
@@ -5,4 +5,5 @@
 /bmp_logo.h
 /config.h
 /config.mk
+/timestamp_autogenerated.h
 /version_autogenerated.h
diff --git a/include/4xx_i2c.h b/include/4xx_i2c.h
index 2df4fbd..f0e772c 100644
--- a/include/4xx_i2c.h
+++ b/include/4xx_i2c.h
@@ -43,10 +43,10 @@
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define I2C_BASE_ADDR	(CFG_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS)
+#define I2C_BASE_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS)
 #elif defined(CONFIG_440) || defined(CONFIG_405EX)
 /* all remaining 440 variants */
-#define I2C_BASE_ADDR	(CFG_PERIPHERAL_BASE + 0x00000400 + I2C_BUS_OFFS)
+#define I2C_BASE_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000400 + I2C_BUS_OFFS)
 #else
 /* all 405 variants */
 #define I2C_BASE_ADDR	(0xEF600500 + I2C_BUS_OFFS)
diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h
index 4a03cec..69a2174 100644
--- a/include/74xx_7xx.h
+++ b/include/74xx_7xx.h
@@ -66,43 +66,6 @@
 #define L2CR_L2OH_INV    0x00020000 /* bits 14-15 - output hold time = long */
 #define L2CR_L2IP        0x00000001 /* global invalidate in progress */
 
-/*----------------------------------------------------------------
- * BAT settings.  Look in config_<BOARD>.h for the actual setup
- */
-
-#define BATU_BL_128K            0x00000000
-#define BATU_BL_256K            0x00000004
-#define BATU_BL_512K            0x0000000c
-#define BATU_BL_1M              0x0000001c
-#define BATU_BL_2M              0x0000003c
-#define BATU_BL_4M              0x0000007c
-#define BATU_BL_8M              0x000000fc
-#define BATU_BL_16M             0x000001fc
-#define BATU_BL_32M             0x000003fc
-#define BATU_BL_64M             0x000007fc
-#define BATU_BL_128M            0x00000ffc
-#define BATU_BL_256M            0x00001ffc
-
-#define BATU_VS                 0x00000002
-#define BATU_VP                 0x00000001
-#define BATU_INVALID            0x00000000
-
-#define BATL_WRITETHROUGH       0x00000040
-#define BATL_CACHEINHIBIT       0x00000020
-#define BATL_MEMCOHERENCE	0x00000010
-#define BATL_GUARDEDSTORAGE     0x00000008
-#define BATL_NO_ACCESS		0x00000000
-
-#define BATL_PP_MSK		0x00000003
-#define BATL_PP_00		0x00000000 /* No access */
-#define BATL_PP_01		0x00000001 /* Read-only */
-#define BATL_PP_10		0x00000002 /* Read-write */
-#define BATL_PP_11		0x00000003
-
-#define BATL_PP_NO_ACCESS	BATL_PP_00
-#define BATL_PP_RO		BATL_PP_01
-#define BATL_PP_RW		BATL_PP_10
-
 #ifndef __ASSEMBLY__
 /* cpu ids we detect */
 typedef enum __cpu_t {
diff --git a/include/addr_map.h b/include/addr_map.h
new file mode 100644
index 0000000..d55f5f6
--- /dev/null
+++ b/include/addr_map.h
@@ -0,0 +1,29 @@
+#ifndef __ADDR_MAP_H
+#define __ADDR_MAP_H
+
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/types.h>
+
+extern phys_addr_t addrmap_virt_to_phys(void *vaddr);
+extern unsigned long addrmap_phys_to_virt(phys_addr_t paddr);
+extern void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr,
+				phys_size_t size, int idx);
+
+#endif
diff --git a/include/altera.h b/include/altera.h
index c03fe87..44a1ee5 100644
--- a/include/altera.h
+++ b/include/altera.h
@@ -29,19 +29,19 @@
 
 /* Altera Model definitions
  *********************************************************************/
-#define CFG_ACEX1K		CFG_FPGA_DEV( 0x1 )
-#define CFG_CYCLON2		CFG_FPGA_DEV( 0x2 )
-#define CFG_STRATIX_II		CFG_FPGA_DEV( 0x4 )
+#define CONFIG_SYS_ACEX1K		CONFIG_SYS_FPGA_DEV( 0x1 )
+#define CONFIG_SYS_CYCLON2		CONFIG_SYS_FPGA_DEV( 0x2 )
+#define CONFIG_SYS_STRATIX_II		CONFIG_SYS_FPGA_DEV( 0x4 )
 
-#define CFG_ALTERA_ACEX1K	(CFG_FPGA_ALTERA | CFG_ACEX1K)
-#define CFG_ALTERA_CYCLON2	(CFG_FPGA_ALTERA | CFG_CYCLON2)
-#define CFG_ALTERA_STRATIX_II	(CFG_FPGA_ALTERA | CFG_STRATIX_II)
+#define CONFIG_SYS_ALTERA_ACEX1K	(CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_ACEX1K)
+#define CONFIG_SYS_ALTERA_CYCLON2	(CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_CYCLON2)
+#define CONFIG_SYS_ALTERA_STRATIX_II	(CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_STRATIX_II)
 /* Add new models here */
 
 /* Altera Interface definitions
  *********************************************************************/
-#define CFG_ALTERA_IF_PS	CFG_FPGA_IF( 0x1 )	/* passive serial */
-#define CFG_ALTERA_IF_FPP	CFG_FPGA_IF( 0x2 )	/* fast passive parallel */
+#define CONFIG_SYS_ALTERA_IF_PS	CONFIG_SYS_FPGA_IF( 0x1 )	/* passive serial */
+#define CONFIG_SYS_ALTERA_IF_FPP	CONFIG_SYS_FPGA_IF( 0x2 )	/* fast passive parallel */
 /* Add new interfaces here */
 
 typedef enum {				/* typedef Altera_iface */
diff --git a/include/api_public.h b/include/api_public.h
index 5b0c09e..5940d81 100644
--- a/include/api_public.h
+++ b/include/api_public.h
@@ -57,6 +57,7 @@
 #define API_ENOMEM		3	/* no memory		*/
 #define API_EBUSY		4	/* busy, occupied etc.	*/
 #define API_EIO			5	/* I/O error		*/
+#define API_ESYSC		6	/* syscall error	*/
 
 typedef	int (*scp_t)(int, int *, ...);
 
@@ -110,8 +111,8 @@ struct sys_info {
 	int			mr_no;	/* number of memory regions */
 };
 
-#undef CFG_64BIT_LBA
-#ifdef CFG_64BIT_LBA
+#undef CONFIG_SYS_64BIT_LBA
+#ifdef CONFIG_SYS_64BIT_LBA
 typedef	u_int64_t lbasize_t;
 #else
 typedef unsigned long lbasize_t;
diff --git a/include/asm-arm/arch-at91/gpio.h b/include/asm-arm/arch-at91/gpio.h
index c4d7b97..e2d375b 100644
--- a/include/asm-arm/arch-at91/gpio.h
+++ b/include/asm-arm/arch-at91/gpio.h
@@ -16,6 +16,7 @@
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <asm/arch/at91_pio.h>
+#include <asm/arch/hardware.h>
 
 #define PIN_BASE		32
 
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index f312419..b881e4e 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -20,7 +20,6 @@
 #include <asm/arch/at91rm9200.h>
 #elif defined(CONFIG_AT91SAM9260)
 #include <asm/arch/at91sam9260.h>
-#define AT91_BASE_EMAC	AT91SAM9260_BASE_EMAC
 #define AT91_BASE_SPI	AT91SAM9260_BASE_SPI0
 #define AT91_ID_UHP	AT91SAM9260_ID_UHP
 #define AT91_PMC_UHP	AT91SAM926x_PMC_UHP
@@ -31,7 +30,6 @@
 #define AT91_PMC_UHP	AT91SAM926x_PMC_UHP
 #elif defined(CONFIG_AT91SAM9263)
 #include <asm/arch/at91sam9263.h>
-#define AT91_BASE_EMAC	AT91SAM9263_BASE_EMAC
 #define AT91_BASE_SPI	AT91SAM9263_BASE_SPI0
 #define AT91_ID_UHP	AT91SAM9263_ID_UHP
 #define AT91_PMC_UHP	AT91SAM926x_PMC_UHP
@@ -41,7 +39,6 @@
 #define AT91_ID_UHP	AT91SAM9RL_ID_UHP
 #elif defined(CONFIG_AT91CAP9)
 #include <asm/arch/at91cap9.h>
-#define AT91_BASE_EMAC	AT91CAP9_BASE_EMAC
 #define AT91_BASE_SPI	AT91CAP9_BASE_SPI0
 #define AT91_ID_UHP	AT91CAP9_ID_UHP
 #define AT91_PMC_UHP	AT91CAP9_PMC_UHP
diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
index 95db017..00bae1c 100644
--- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h
+++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
@@ -781,5 +781,32 @@ typedef struct _AT91S_PDC
 #define AT91C_PIOB_ODR		((AT91_REG *)	0xFFFFF614) /* (PIOB) Output Disable Registerr */
 #define AT91C_PIOB_PDSR		((AT91_REG *)	0xFFFFF63C) /* (PIOB) Pin Data Status Register */
 
+#else
+/* flash */
+#define AT91C_MC_PUIA		0xFFFFFF10
+#define AT91C_MC_PUP		0xFFFFFF50
+#define AT91C_MC_PUER		0xFFFFFF54
+#define AT91C_MC_ASR		0xFFFFFF04
+#define AT91C_MC_AASR		0xFFFFFF08
+#define AT91C_EBI_CFGR		0xFFFFFF64
+#define AT91C_SMC_CSR0		0xFFFFFF70
+
+/* clocks */
+#define AT91C_PLLAR		0xFFFFFC28
+#define AT91C_PLLBR		0xFFFFFC2C
+#define AT91C_MCKR		0xFFFFFC30
+
+#define AT91C_BASE_CKGR		0xFFFFFC20
+#define AT91C_CKGR_MOR		0
+
+/* sdram */
+#define AT91C_PIOC_ASR		0xFFFFF870
+#define AT91C_PIOC_BSR		0xFFFFF874
+#define AT91C_PIOC_PDR		0xFFFFF804
+#define AT91C_EBI_CSA		0xFFFFFF60
+#define AT91C_SDRC_CR		0xFFFFFF98
+#define AT91C_SDRC_MR		0xFFFFFF90
+#define AT91C_SDRC_TR		0xFFFFFF94
+
 #endif /* __ASSEMBLY__ */
 #endif /* AT91RM9200_H */
diff --git a/include/asm-arm/arch-davinci/nand_defs.h b/include/asm-arm/arch-davinci/nand_defs.h
index 619bd47..187d3c3 100644
--- a/include/asm-arm/arch-davinci/nand_defs.h
+++ b/include/asm-arm/arch-davinci/nand_defs.h
@@ -31,9 +31,9 @@
 #define	MASK_CLE	0x10
 #define	MASK_ALE	0x0a
 
-#define NAND_CE0CLE	((volatile u_int8_t *)(CFG_NAND_BASE + 0x10))
-#define NAND_CE0ALE	((volatile u_int8_t *)(CFG_NAND_BASE + 0x0a))
-#define NAND_CE0DATA	((volatile u_int8_t *)CFG_NAND_BASE)
+#define NAND_CE0CLE	((volatile u_int8_t *)(CONFIG_SYS_NAND_BASE + 0x10))
+#define NAND_CE0ALE	((volatile u_int8_t *)(CONFIG_SYS_NAND_BASE + 0x0a))
+#define NAND_CE0DATA	((volatile u_int8_t *)CONFIG_SYS_NAND_BASE)
 
 typedef struct  {
 	u_int32_t	NRCSR;
@@ -89,7 +89,7 @@ typedef volatile nand_registers	*nandregs;
 #define NAND_READ_END		0x30
 #define NAND_STATUS		0x70
 
-#ifdef CFG_NAND_HW_ECC
+#ifdef CONFIG_SYS_NAND_HW_ECC
 #define NAND_Ecc_P1e		(1 << 0)
 #define NAND_Ecc_P2e		(1 << 1)
 #define NAND_Ecc_P4e		(1 << 2)
diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
index b04a718..3cdaa02 100644
--- a/include/asm-arm/arch-mx31/mx31-regs.h
+++ b/include/asm-arm/arch-mx31/mx31-regs.h
@@ -34,7 +34,7 @@
 #define CCM_PDR1	(CCM_BASE + 0x08)
 #define CCM_RCSR	(CCM_BASE + 0x0c)
 #define CCM_MPCTL	(CCM_BASE + 0x10)
-#define CCM_UPCTL	(CCM_BASE + 0x10)
+#define CCM_UPCTL	(CCM_BASE + 0x14)
 #define CCM_SPCTL	(CCM_BASE + 0x18)
 #define CCM_COSR	(CCM_BASE + 0x1C)
 #define CCM_CGR0	(CCM_BASE + 0x20)
@@ -87,6 +87,16 @@
 #define WDOG_BASE		0x53FDC000
 
 /*
+ * GPIO
+ */
+#define GPIO1_BASE	0x53FCC000
+#define GPIO2_BASE	0x53FD0000
+#define GPIO3_BASE	0x53FA4000
+#define GPIO_DR		0x00000000	/* data register */
+#define GPIO_GDIR	0x00000004	/* direction register */
+#define GPIO_PSR	0x00000008	/* pad status register */
+
+/*
  * Signal Multiplexing (IOMUX)
  */
 
diff --git a/include/asm-arm/arch-omap24xx/mem.h b/include/asm-arm/arch-omap24xx/mem.h
index c81f1c4..42e8ab2 100644
--- a/include/asm-arm/arch-omap24xx/mem.h
+++ b/include/asm-arm/arch-omap24xx/mem.h
@@ -103,7 +103,7 @@ typedef enum {
 
 /* GPMC settings */
 #ifdef PRCM_CONFIG_II	     /* L3 at 100MHz */
-# ifdef CFG_NAND_BOOT
+# ifdef CONFIG_SYS_NAND_BOOT
 #  define H4_24XX_GPMC_CONFIG1_0   0x0
 #  define H4_24XX_GPMC_CONFIG2_0   0x00141400
 #  define H4_24XX_GPMC_CONFIG3_0   0x00141400
@@ -116,7 +116,7 @@ typedef enum {
 #  define H4_24XX_GPMC_CONFIG3_0   0x00050502
 #  define H4_24XX_GPMC_CONFIG4_0   0x0C060C06
 #  define H4_24XX_GPMC_CONFIG5_0   0x01131F1F
-# endif /* endif CFG_NAND_BOOT */
+# endif /* endif CONFIG_SYS_NAND_BOOT */
 # define H4_24XX_GPMC_CONFIG7_0	  (0x00000C40|(H4_CS0_BASE >> 24))
 # define H4_24XX_GPMC_CONFIG1_1	  0x00011000
 # define H4_24XX_GPMC_CONFIG2_1	  0x001F1F00
@@ -128,7 +128,7 @@ typedef enum {
 #endif /* endif PRCM_CONFIG_II */
 
 #ifdef PRCM_CONFIG_III	/* L3 at 133MHz */
-# ifdef CFG_NAND_BOOT
+# ifdef CONFIG_SYS_NAND_BOOT
 #  define H4_24XX_GPMC_CONFIG1_0   0x0
 #  define H4_24XX_GPMC_CONFIG2_0   0x00141400
 #  define H4_24XX_GPMC_CONFIG3_0   0x00141400
@@ -142,7 +142,7 @@ typedef enum {
 #  define H4_24XX_GPMC_CONFIG4_0   0x10081008
 #  define H4_24XX_GPMC_CONFIG5_0   0x01131F1F
 #  define H4_24XX_GPMC_CONFIG6_0   0x000004c4
-# endif /* endif CFG_NAND_BOOT */
+# endif /* endif CONFIG_SYS_NAND_BOOT */
 # define H4_24XX_GPMC_CONFIG7_0	  (0x00000C40|(H4_CS0_BASE >> 24))
 # define H4_24XX_GPMC_CONFIG1_1	  0x00011000
 # define H4_24XX_GPMC_CONFIG2_1	  0x001f1f01
@@ -151,6 +151,6 @@ typedef enum {
 # define H4_24XX_GPMC_CONFIG5_1	  0x041f1F1F
 # define H4_24XX_GPMC_CONFIG6_1	  0x000004C4
 # define H4_24XX_GPMC_CONFIG7_1	  (0x00000F40|(H4_CS1_BASE >> 24))
-#endif /* endif CFG_PRCM_III */
+#endif /* endif CONFIG_SYS_PRCM_III */
 
 #endif /* endif _OMAP24XX_MEM_H_ */
diff --git a/include/asm-arm/arch-omap3/clocks.h b/include/asm-arm/arch-omap3/clocks.h
new file mode 100644
index 0000000..71a0cb6
--- /dev/null
+++ b/include/asm-arm/arch-omap3/clocks.h
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_H_
+#define _CLOCKS_H_
+
+#define LDELAY		12000000
+
+#define S12M		12000000
+#define S13M		13000000
+#define S19_2M		19200000
+#define S24M		24000000
+#define S26M		26000000
+#define S38_4M		38400000
+
+#define FCK_IVA2_ON	0x00000001
+#define FCK_CORE1_ON	0x03fffe29
+#define ICK_CORE1_ON	0x3ffffffb
+#define ICK_CORE2_ON	0x0000001f
+#define FCK_WKUP_ON	0x000000e9
+#define ICK_WKUP_ON	0x0000003f
+#define FCK_DSS_ON	0x00000005
+#define ICK_DSS_ON	0x00000001
+#define FCK_CAM_ON	0x00000001
+#define ICK_CAM_ON	0x00000001
+#define FCK_PER_ON	0x0003ffff
+#define ICK_PER_ON	0x0003ffff
+
+/* Used to index into DPLL parameter tables */
+typedef struct {
+	unsigned int m;
+	unsigned int n;
+	unsigned int fsel;
+	unsigned int m2;
+} dpll_param;
+
+/* Following functions are exported from lowlevel_init.S */
+extern dpll_param *get_mpu_dpll_param(void);
+extern dpll_param *get_iva_dpll_param(void);
+extern dpll_param *get_core_dpll_param(void);
+extern dpll_param *get_per_dpll_param(void);
+
+extern void *_end_vect, *_start;
+
+#endif
diff --git a/include/asm-arm/arch-omap3/clocks_omap3.h b/include/asm-arm/arch-omap3/clocks_omap3.h
new file mode 100644
index 0000000..661407b
--- /dev/null
+++ b/include/asm-arm/arch-omap3/clocks_omap3.h
@@ -0,0 +1,285 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_OMAP3_H_
+#define _CLOCKS_OMAP3_H_
+
+#define PLL_STOP		1	/* PER & IVA */
+#define PLL_LOW_POWER_BYPASS	5	/* MPU, IVA & CORE */
+#define PLL_FAST_RELOCK_BYPASS	6	/* CORE */
+#define PLL_LOCK		7	/* MPU, IVA, CORE & PER */
+
+/*
+ * The following configurations are OPP and SysClk value independant
+ * and hence are defined here. All the other DPLL related values are
+ * tabulated in lowlevel_init.S.
+ */
+
+/* CORE DPLL */
+#define CORE_M3X2	2	/* 332MHz : CM_CLKSEL1_EMU */
+#define CORE_SSI_DIV	3	/* 221MHz : CM_CLKSEL_CORE */
+#define CORE_FUSB_DIV	2	/* 41.5MHz: */
+#define CORE_L4_DIV	2	/* 83MHz  : L4 */
+#define CORE_L3_DIV	2	/* 166MHz : L3 {DDR} */
+#define GFX_DIV		2	/* 83MHz  : CM_CLKSEL_GFX */
+#define WKUP_RSM	2	/* 41.5MHz: CM_CLKSEL_WKUP */
+
+/* PER DPLL */
+#define PER_M6X2	3	/* 288MHz: CM_CLKSEL1_EMU */
+#define PER_M5X2	4	/* 216MHz: CM_CLKSEL_CAM */
+#define PER_M4X2	2	/* 432MHz: CM_CLKSEL_DSS-dss1 */
+#define PER_M3X2	16	/* 54MHz : CM_CLKSEL_DSS-tv */
+
+#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50))
+
+/* MPU DPLL */
+
+#define MPU_M_12_ES1		0x0FE
+#define MPU_N_12_ES1		0x07
+#define MPU_FSEL_12_ES1		0x05
+#define MPU_M2_12_ES1		0x01
+
+#define MPU_M_12_ES2		0x0FA
+#define MPU_N_12_ES2		0x05
+#define MPU_FSEL_12_ES2		0x07
+#define MPU_M2_ES2		0x01
+
+#define MPU_M_12		0x085
+#define MPU_N_12		0x05
+#define MPU_FSEL_12		0x07
+#define MPU_M2_12		0x01
+
+#define MPU_M_13_ES1		0x17D
+#define MPU_N_13_ES1		0x0C
+#define MPU_FSEL_13_ES1		0x03
+#define MPU_M2_13_ES1		0x01
+
+#define MPU_M_13_ES2		0x1F4
+#define MPU_N_13_ES2		0x0C
+#define MPU_FSEL_13_ES2		0x03
+#define MPU_M2_13_ES2		0x01
+
+#define MPU_M_13		0x10A
+#define MPU_N_13		0x0C
+#define MPU_FSEL_13		0x03
+#define MPU_M2_13		0x01
+
+#define MPU_M_19P2_ES1		0x179
+#define MPU_N_19P2_ES1		0x12
+#define MPU_FSEL_19P2_ES1	0x04
+#define MPU_M2_19P2_ES1		0x01
+
+#define MPU_M_19P2_ES2		0x271
+#define MPU_N_19P2_ES2		0x17
+#define MPU_FSEL_19P2_ES2	0x03
+#define MPU_M2_19P2_ES2		0x01
+
+#define MPU_M_19P2		0x14C
+#define MPU_N_19P2		0x17
+#define MPU_FSEL_19P2		0x03
+#define MPU_M2_19P2		0x01
+
+#define MPU_M_26_ES1		0x17D
+#define MPU_N_26_ES1		0x19
+#define MPU_FSEL_26_ES1		0x03
+#define MPU_M2_26_ES1		0x01
+
+#define MPU_M_26_ES2		0x0FA
+#define MPU_N_26_ES2		0x0C
+#define MPU_FSEL_26_ES2		0x07
+#define MPU_M2_26_ES2		0x01
+
+#define MPU_M_26		0x085
+#define MPU_N_26		0x0C
+#define MPU_FSEL_26		0x07
+#define MPU_M2_26		0x01
+
+#define MPU_M_38P4_ES1		0x1FA
+#define MPU_N_38P4_ES1		0x32
+#define MPU_FSEL_38P4_ES1	0x03
+#define MPU_M2_38P4_ES1		0x01
+
+#define MPU_M_38P4_ES2		0x271
+#define MPU_N_38P4_ES2		0x2F
+#define MPU_FSEL_38P4_ES2	0x03
+#define MPU_M2_38P4_ES2		0x01
+
+#define MPU_M_38P4		0x14C
+#define MPU_N_38P4		0x2F
+#define MPU_FSEL_38P4		0x03
+#define MPU_M2_38P4		0x01
+
+/* IVA DPLL */
+
+#define IVA_M_12_ES1		0x07D
+#define IVA_N_12_ES1		0x05
+#define IVA_FSEL_12_ES1		0x07
+#define IVA_M2_12_ES1		0x01
+
+#define IVA_M_12_ES2		0x0B4
+#define IVA_N_12_ES2		0x05
+#define IVA_FSEL_12_ES2		0x07
+#define IVA_M2_12_ES2		0x01
+
+#define IVA_M_12		0x085
+#define IVA_N_12		0x05
+#define IVA_FSEL_12		0x07
+#define IVA_M2_12		0x01
+
+#define IVA_M_13_ES1		0x0FA
+#define IVA_N_13_ES1		0x0C
+#define IVA_FSEL_13_ES1		0x03
+#define IVA_M2_13_ES1		0x01
+
+#define IVA_M_13_ES2		0x168
+#define IVA_N_13_ES2		0x0C
+#define IVA_FSEL_13_ES2		0x03
+#define IVA_M2_13_ES2		0x01
+
+#define IVA_M_13		0x10A
+#define IVA_N_13		0x0C
+#define IVA_FSEL_13		0x03
+#define IVA_M2_13		0x01
+
+#define IVA_M_19P2_ES1		0x082
+#define IVA_N_19P2_ES1		0x09
+#define IVA_FSEL_19P2_ES1	0x07
+#define IVA_M2_19P2_ES1		0x01
+
+#define IVA_M_19P2_ES2		0x0E1
+#define IVA_N_19P2_ES2		0x0B
+#define IVA_FSEL_19P2_ES2	0x06
+#define IVA_M2_19P2_ES2		0x01
+
+#define IVA_M_19P2		0x14C
+#define IVA_N_19P2		0x17
+#define IVA_FSEL_19P2		0x03
+#define IVA_M2_19P2		0x01
+
+#define IVA_M_26_ES1		0x07D
+#define IVA_N_26_ES1		0x0C
+#define IVA_FSEL_26_ES1		0x07
+#define IVA_M2_26_ES1		0x01
+
+#define IVA_M_26_ES2		0x0B4
+#define IVA_N_26_ES2		0x0C
+#define IVA_FSEL_26_ES2		0x07
+#define IVA_M2_26_ES2		0x01
+
+#define IVA_M_26		0x085
+#define IVA_N_26		0x0C
+#define IVA_FSEL_26		0x07
+#define IVA_M2_26		0x01
+
+#define IVA_M_38P4_ES1		0x13F
+#define IVA_N_38P4_ES1		0x30
+#define IVA_FSEL_38P4_ES1	0x03
+#define IVA_M2_38P4_ES1		0x01
+
+#define IVA_M_38P4_ES2		0x0E1
+#define IVA_N_38P4_ES2		0x17
+#define IVA_FSEL_38P4_ES2	0x06
+#define IVA_M2_38P4_ES2		0x01
+
+#define IVA_M_38P4		0x14C
+#define IVA_N_38P4		0x2F
+#define IVA_FSEL_38P4		0x03
+#define IVA_M2_38P4		0x01
+
+/* CORE DPLL */
+
+#define CORE_M_12		0xA6
+#define CORE_N_12		0x05
+#define CORE_FSEL_12		0x07
+#define CORE_M2_12		0x01	/* M3 of 2 */
+
+#define CORE_M_12_ES1		0x19F
+#define CORE_N_12_ES1		0x0E
+#define CORE_FSL_12_ES1		0x03
+#define CORE_M2_12_ES1		0x1	/* M3 of 2 */
+
+#define CORE_M_13		0x14C
+#define CORE_N_13		0x0C
+#define CORE_FSEL_13		0x03
+#define CORE_M2_13		0x01	/* M3 of 2 */
+
+#define CORE_M_13_ES1		0x1B2
+#define CORE_N_13_ES1		0x10
+#define CORE_FSL_13_ES1		0x03
+#define CORE_M2_13_ES1		0x01	/* M3 of 2 */
+
+#define CORE_M_19P2		0x19F
+#define CORE_N_19P2		0x17
+#define CORE_FSEL_19P2		0x03
+#define CORE_M2_19P2		0x01	/* M3 of 2 */
+
+#define CORE_M_19P2_ES1		0x19F
+#define CORE_N_19P2_ES1		0x17
+#define CORE_FSL_19P2_ES1	0x03
+#define CORE_M2_19P2_ES1	0x01	/* M3 of 2 */
+
+#define CORE_M_26		0xA6
+#define CORE_N_26		0x0C
+#define CORE_FSEL_26		0x07
+#define CORE_M2_26		0x01	/* M3 of 2 */
+
+#define CORE_M_26_ES1		0x1B2
+#define CORE_N_26_ES1		0x21
+#define CORE_FSL_26_ES1		0x03
+#define CORE_M2_26_ES1		0x01	/* M3 of 2 */
+
+#define CORE_M_38P4		0x19F
+#define CORE_N_38P4		0x2F
+#define CORE_FSEL_38P4		0x03
+#define CORE_M2_38P4		0x01	/* M3 of 2 */
+
+#define CORE_M_38P4_ES1		0x19F
+#define CORE_N_38P4_ES1		0x2F
+#define CORE_FSL_38P4_ES1	0x03
+#define CORE_M2_38P4_ES1	0x01	/* M3 of 2 */
+
+/* PER DPLL */
+
+#define PER_M_12		0xD8
+#define PER_N_12		0x05
+#define PER_FSEL_12		0x07
+#define PER_M2_12		0x09
+
+#define PER_M_13		0x1B0
+#define PER_N_13		0x0C
+#define PER_FSEL_13		0x03
+#define PER_M2_13		0x09
+
+#define PER_M_19P2		0xE1
+#define PER_N_19P2		0x09
+#define PER_FSEL_19P2		0x07
+#define PER_M2_19P2		0x09
+
+#define PER_M_26		0xD8
+#define PER_N_26		0x0C
+#define PER_FSEL_26		0x07
+#define PER_M2_26		0x09
+
+#define PER_M_38P4		0xE1
+#define PER_N_38P4		0x13
+#define PER_FSEL_38P4		0x07
+#define PER_M2_38P4		0x09
+
+#endif	/* endif _CLOCKS_OMAP3_H_ */
diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h
new file mode 100644
index 0000000..5b344f8
--- /dev/null
+++ b/include/asm-arm/arch-omap3/cpu.h
@@ -0,0 +1,422 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+
+/* Register offsets of common modules */
+/* Control */
+#ifndef __ASSEMBLY__
+typedef struct ctrl {
+	unsigned char res1[0xC0];
+	unsigned short gpmc_nadv_ale;	/* 0xC0 */
+	unsigned short gpmc_noe;	/* 0xC2 */
+	unsigned short gpmc_nwe;	/* 0xC4 */
+	unsigned char res2[0x22A];
+	unsigned int status;		/* 0x2F0 */
+	unsigned int gpstatus;		/* 0x2F4 */
+	unsigned char res3[0x08];
+	unsigned int rpubkey_0;		/* 0x300 */
+	unsigned int rpubkey_1;		/* 0x304 */
+	unsigned int rpubkey_2;		/* 0x308 */
+	unsigned int rpubkey_3;		/* 0x30C */
+	unsigned int rpubkey_4;		/* 0x310 */
+	unsigned char res4[0x04];
+	unsigned int randkey_0;		/* 0x318 */
+	unsigned int randkey_1;		/* 0x31C */
+	unsigned int randkey_2;		/* 0x320 */
+	unsigned int randkey_3;		/* 0x324 */
+	unsigned char res5[0x124];
+	unsigned int ctrl_omap_stat;	/* 0x44C */
+} ctrl_t;
+#else /* __ASSEMBLY__ */
+#define CONTROL_STATUS		0x2F0
+#endif /* __ASSEMBLY__ */
+
+/* cpu type */
+#define OMAP3503		0x5c00
+#define OMAP3515		0x1c00
+#define OMAP3525		0x4c00
+#define OMAP3530		0x0c00
+
+/* device type */
+#define DEVICE_MASK		(0x7 << 8)
+#define SYSBOOT_MASK		0x1F
+#define TST_DEVICE		0x0
+#define EMU_DEVICE		0x1
+#define HS_DEVICE		0x2
+#define GP_DEVICE		0x3
+
+/* GPMC CS3/cs4/cs6 not avaliable */
+#define GPMC_BASE		(OMAP34XX_GPMC_BASE)
+#define GPMC_CONFIG_CS0		0x60
+#define GPMC_CONFIG_CS6		0x150
+#define GPMC_CONFIG_CS0_BASE	(GPMC_BASE + GPMC_CONFIG_CS0)
+#define GPMC_CONFIG_CS6_BASE	(GPMC_BASE + GPMC_CONFIG_CS6)
+#define GPMC_CONFIG_WP		0x10
+
+#define GPMC_CONFIG_WIDTH	0x30
+
+#ifndef __ASSEMBLY__
+typedef struct gpmc {
+	unsigned char res1[0x10];
+	unsigned int sysconfig;		/* 0x10 */
+	unsigned char res2[0x4];
+	unsigned int irqstatus;		/* 0x18 */
+	unsigned int irqenable; 	/* 0x1C */
+	unsigned char res3[0x20];
+	unsigned int timeout_control; 	/* 0x40 */
+	unsigned char res4[0xC];
+	unsigned int config;		/* 0x50 */
+	unsigned int status;		/* 0x54 */
+	unsigned char res5[0x19C];
+	unsigned int ecc_config;	/* 0x1F4 */
+	unsigned int ecc_control;	/* 0x1F8 */
+	unsigned int ecc_size_config;	/* 0x1FC */
+	unsigned int ecc1_result;	/* 0x200 */
+	unsigned int ecc2_result;	/* 0x204 */
+	unsigned int ecc3_result;	/* 0x208 */
+	unsigned int ecc4_result;	/* 0x20C */
+	unsigned int ecc5_result;	/* 0x210 */
+	unsigned int ecc6_result;	/* 0x214 */
+	unsigned int ecc7_result;	/* 0x218 */
+	unsigned int ecc8_result;	/* 0x21C */
+	unsigned int ecc9_result;	/* 0x220 */
+} gpmc_t;
+
+typedef struct gpmc_csx {
+	unsigned int config1;		/* 0x00 */
+	unsigned int config2;		/* 0x04 */
+	unsigned int config3;		/* 0x08 */
+	unsigned int config4;		/* 0x0C */
+	unsigned int config5;		/* 0x10 */
+	unsigned int config6;		/* 0x14 */
+	unsigned int config7;		/* 0x18 */
+	unsigned int nand_cmd;		/* 0x1C */
+	unsigned int nand_adr;		/* 0x20 */
+	unsigned int nand_dat;		/* 0x24 */
+} gpmc_csx_t;
+#else /* __ASSEMBLY__ */
+#define GPMC_CONFIG1		0x00
+#define GPMC_CONFIG2		0x04
+#define GPMC_CONFIG3		0x08
+#define GPMC_CONFIG4		0x0C
+#define GPMC_CONFIG5		0x10
+#define GPMC_CONFIG6		0x14
+#define GPMC_CONFIG7		0x18
+#endif /* __ASSEMBLY__ */
+
+/* GPMC Mapping */
+#define FLASH_BASE		0x10000000	/* NOR flash, */
+						/* aligned to 256 Meg */
+#define FLASH_BASE_SDPV1	0x04000000	/* NOR flash, */
+						/* aligned to 64 Meg */
+#define FLASH_BASE_SDPV2	0x10000000	/* NOR flash, */
+						/* aligned to 256 Meg */
+#define DEBUG_BASE		0x08000000	/* debug board */
+#define NAND_BASE		0x30000000	/* NAND addr */
+						/* (actual size small port) */
+#define PISMO2_BASE		0x18000000	/* PISMO2 CS1/2 */
+#define ONENAND_MAP		0x20000000	/* OneNand addr */
+						/* (actual size small port) */
+/* SMS */
+#ifndef __ASSEMBLY__
+typedef struct sms {
+	unsigned char res1[0x10];
+	unsigned int sysconfig;		/* 0x10 */
+	unsigned char res2[0x34];
+	unsigned int rg_att0;		/* 0x48 */
+	unsigned char res3[0x84];
+	unsigned int class_arb0;	/* 0xD0 */
+} sms_t;
+#endif /* __ASSEMBLY__ */
+
+#define BURSTCOMPLETE_GROUP7	(0x1 << 31)
+
+/* SDRC */
+#ifndef __ASSEMBLY__
+typedef struct sdrc_cs {
+	unsigned int mcfg;		/* 0x80 || 0xB0 */
+	unsigned int mr;		/* 0x84 || 0xB4 */
+	unsigned char res1[0x4];
+	unsigned int emr2;		/* 0x8C || 0xBC */
+	unsigned char res2[0x14];
+	unsigned int rfr_ctrl;		/* 0x84 || 0xD4 */
+	unsigned int manual;		/* 0xA8 || 0xD8 */
+	unsigned char res3[0x4];
+} sdrc_cs_t;
+
+typedef struct sdrc_actim {
+	unsigned int ctrla;		/* 0x9C || 0xC4 */
+	unsigned int ctrlb;		/* 0xA0 || 0xC8 */
+} sdrc_actim_t;
+
+typedef struct sdrc {
+	unsigned char res1[0x10];
+	unsigned int sysconfig;		/* 0x10 */
+	unsigned int status;		/* 0x14 */
+	unsigned char res2[0x28];
+	unsigned int cs_cfg;		/* 0x40 */
+	unsigned int sharing;		/* 0x44 */
+	unsigned char res3[0x18];
+	unsigned int dlla_ctrl;		/* 0x60 */
+	unsigned int dlla_status;	/* 0x64 */
+	unsigned int dllb_ctrl;		/* 0x68 */
+	unsigned int dllb_status;	/* 0x6C */
+	unsigned int power;		/* 0x70 */
+	unsigned char res4[0xC];
+	sdrc_cs_t cs[2];		/* 0x80 || 0xB0 */
+} sdrc_t;
+#endif /* __ASSEMBLY__ */
+
+#define DLLPHASE_90		(0x1 << 1)
+#define LOADDLL			(0x1 << 2)
+#define ENADLL			(0x1 << 3)
+#define DLL_DELAY_MASK		0xFF00
+#define DLL_NO_FILTER_MASK	((0x1 << 9) | (0x1 << 8))
+
+#define PAGEPOLICY_HIGH		(0x1 << 0)
+#define SRFRONRESET		(0x1 << 7)
+#define WAKEUPPROC		(0x1 << 26)
+
+#define DDR_SDRAM		(0x1 << 0)
+#define DEEPPD			(0x1 << 3)
+#define B32NOT16		(0x1 << 4)
+#define BANKALLOCATION		(0x2 << 6)
+#define RAMSIZE_128		(0x40 << 8) /* RAM size in 2MB chunks */
+#define ADDRMUXLEGACY		(0x1 << 19)
+#define CASWIDTH_10BITS		(0x5 << 20)
+#define RASWIDTH_13BITS		(0x2 << 24)
+#define BURSTLENGTH4		(0x2 << 0)
+#define CASL3			(0x3 << 4)
+#define SDRC_ACTIM_CTRL0_BASE	(OMAP34XX_SDRC_BASE + 0x9C)
+#define SDRC_ACTIM_CTRL1_BASE	(OMAP34XX_SDRC_BASE + 0xC4)
+#define ARE_ARCV_1		(0x1 << 0)
+#define ARCV			(0x4e2 << 8) /* Autorefresh count */
+#define OMAP34XX_SDRC_CS0	0x80000000
+#define OMAP34XX_SDRC_CS1	0xA0000000
+#define CMD_NOP			0x0
+#define CMD_PRECHARGE		0x1
+#define CMD_AUTOREFRESH		0x2
+#define CMD_ENTR_PWRDOWN	0x3
+#define CMD_EXIT_PWRDOWN	0x4
+#define CMD_ENTR_SRFRSH		0x5
+#define CMD_CKE_HIGH		0x6
+#define CMD_CKE_LOW		0x7
+#define SOFTRESET		(0x1 << 1)
+#define SMART_IDLE		(0x2 << 3)
+#define REF_ON_IDLE		(0x1 << 6)
+
+/* timer regs offsets (32 bit regs) */
+
+#ifndef __ASSEMBLY__
+typedef struct gptimer {
+	unsigned int tidr;	/* 0x00 r */
+	unsigned char res[0xc];
+	unsigned int tiocp_cfg;	/* 0x10 rw */
+	unsigned int tistat;	/* 0x14 r */
+	unsigned int tisr;	/* 0x18 rw */
+	unsigned int tier;	/* 0x1c rw */
+	unsigned int twer;	/* 0x20 rw */
+	unsigned int tclr;	/* 0x24 rw */
+	unsigned int tcrr;	/* 0x28 rw */
+	unsigned int tldr;	/* 0x2c rw */
+	unsigned int ttgr;	/* 0x30 rw */
+	unsigned int twpc;	/* 0x34 r*/
+	unsigned int tmar;	/* 0x38 rw*/
+	unsigned int tcar1;	/* 0x3c r */
+	unsigned int tcicr;	/* 0x40 rw */
+	unsigned int tcar2;	/* 0x44 r */
+} gptimer_t;
+#endif /* __ASSEMBLY__ */
+
+/* enable sys_clk NO-prescale /1 */
+#define GPT_EN			((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
+
+/* Watchdog */
+#ifndef __ASSEMBLY__
+typedef struct watchdog {
+	unsigned char res1[0x34];
+	unsigned int wwps;	/* 0x34 r */
+	unsigned char res2[0x10];
+	unsigned int wspr;	/* 0x48 rw */
+} watchdog_t;
+#endif /* __ASSEMBLY__ */
+
+#define WD_UNLOCK1		0xAAAA
+#define WD_UNLOCK2		0x5555
+
+/* PRCM */
+#define PRCM_BASE		0x48004000
+
+#ifndef __ASSEMBLY__
+typedef struct prcm {
+	unsigned int fclken_iva2;	/* 0x00 */
+	unsigned int clken_pll_iva2;	/* 0x04 */
+	unsigned char res1[0x1c];
+	unsigned int idlest_pll_iva2;	/* 0x24 */
+	unsigned char res2[0x18];
+	unsigned int clksel1_pll_iva2 ;	/* 0x40 */
+	unsigned int clksel2_pll_iva2;	/* 0x44 */
+	unsigned char res3[0x8bc];
+	unsigned int clken_pll_mpu;	/* 0x904 */
+	unsigned char res4[0x1c];
+	unsigned int idlest_pll_mpu;	/* 0x924 */
+	unsigned char res5[0x18];
+	unsigned int clksel1_pll_mpu;	/* 0x940 */
+	unsigned int clksel2_pll_mpu;	/* 0x944 */
+	unsigned char res6[0xb8];
+	unsigned int fclken1_core;	/* 0xa00 */
+	unsigned char res7[0xc];
+	unsigned int iclken1_core;	/* 0xa10 */
+	unsigned int iclken2_core;	/* 0xa14 */
+	unsigned char res8[0x28];
+	unsigned int clksel_core;	/* 0xa40 */
+	unsigned char res9[0xbc];
+	unsigned int fclken_gfx;	/* 0xb00 */
+	unsigned char res10[0xc];
+	unsigned int iclken_gfx;	/* 0xb10 */
+	unsigned char res11[0x2c];
+	unsigned int clksel_gfx;	/* 0xb40 */
+	unsigned char res12[0xbc];
+	unsigned int fclken_wkup;	/* 0xc00 */
+	unsigned char res13[0xc];
+	unsigned int iclken_wkup;	/* 0xc10 */
+	unsigned char res14[0xc];
+	unsigned int idlest_wkup;	/* 0xc20 */
+	unsigned char res15[0x1c];
+	unsigned int clksel_wkup;	/* 0xc40 */
+	unsigned char res16[0xbc];
+	unsigned int clken_pll;		/* 0xd00 */
+	unsigned char res17[0x1c];
+	unsigned int idlest_ckgen;	/* 0xd20 */
+	unsigned char res18[0x1c];
+	unsigned int clksel1_pll;	/* 0xd40 */
+	unsigned int clksel2_pll;	/* 0xd44 */
+	unsigned int clksel3_pll;	/* 0xd48 */
+	unsigned char res19[0xb4];
+	unsigned int fclken_dss;	/* 0xe00 */
+	unsigned char res20[0xc];
+	unsigned int iclken_dss;	/* 0xe10 */
+	unsigned char res21[0x2c];
+	unsigned int clksel_dss;	/* 0xe40 */
+	unsigned char res22[0xbc];
+	unsigned int fclken_cam;	/* 0xf00 */
+	unsigned char res23[0xc];
+	unsigned int iclken_cam;	/* 0xf10 */
+	unsigned char res24[0x2c];
+	unsigned int clksel_cam;	/* 0xf40 */
+	unsigned char res25[0xbc];
+	unsigned int fclken_per;	/* 0x1000 */
+	unsigned char res26[0xc];
+	unsigned int iclken_per;	/* 0x1010 */
+	unsigned char res27[0x2c];
+	unsigned int clksel_per;	/* 0x1040 */
+	unsigned char res28[0xfc];
+	unsigned int clksel1_emu;	/* 0x1140 */
+} prcm_t;
+#else /* __ASSEMBLY__ */
+#define CM_CLKSEL_CORE		0x48004a40
+#define CM_CLKSEL_GFX		0x48004b40
+#define CM_CLKSEL_WKUP		0x48004c40
+#define CM_CLKEN_PLL		0x48004d00
+#define CM_CLKSEL1_PLL		0x48004d40
+#define CM_CLKSEL1_EMU		0x48005140
+#endif /* __ASSEMBLY__ */
+
+#define PRM_BASE		0x48306000
+
+#ifndef __ASSEMBLY__
+typedef struct prm {
+	unsigned char res1[0xd40];
+	unsigned int clksel;		/* 0xd40 */
+	unsigned char res2[0x50c];
+	unsigned int rstctrl;		/* 0x1250 */
+	unsigned char res3[0x1c];
+	unsigned int clksrc_ctrl;	/* 0x1270 */
+} prm_t;
+#else /* __ASSEMBLY__ */
+#define PRM_RSTCTRL		0x48307250
+#endif /* __ASSEMBLY__ */
+
+#define SYSCLKDIV_1		(0x1 << 6)
+#define SYSCLKDIV_2		(0x1 << 7)
+
+#define CLKSEL_GPT1		(0x1 << 0)
+
+#define EN_GPT1			(0x1 << 0)
+#define EN_32KSYNC		(0x1 << 2)
+
+#define ST_WDT2			(0x1 << 5)
+
+#define ST_MPU_CLK		(0x1 << 0)
+
+#define ST_CORE_CLK		(0x1 << 0)
+
+#define ST_PERIPH_CLK		(0x1 << 1)
+
+#define ST_IVA2_CLK		(0x1 << 0)
+
+#define RESETDONE		(0x1 << 0)
+
+#define TCLR_ST			(0x1 << 0)
+#define TCLR_AR			(0x1 << 1)
+#define TCLR_PRE		(0x1 << 5)
+
+/* SMX-APE */
+#define PM_RT_APE_BASE_ADDR_ARM		(SMX_APE_BASE + 0x10000)
+#define PM_GPMC_BASE_ADDR_ARM		(SMX_APE_BASE + 0x12400)
+#define PM_OCM_RAM_BASE_ADDR_ARM	(SMX_APE_BASE + 0x12800)
+#define PM_IVA2_BASE_ADDR_ARM		(SMX_APE_BASE + 0x14000)
+
+#ifndef __ASSEMBLY__
+typedef struct pm {
+	unsigned char res1[0x48];
+	unsigned int req_info_permission_0;	/* 0x48 */
+	unsigned char res2[0x4];
+	unsigned int read_permission_0;		/* 0x50 */
+	unsigned char res3[0x4];
+	unsigned int wirte_permission_0;	/* 0x58 */
+	unsigned char res4[0x4];
+	unsigned int addr_match_1;		/* 0x58 */
+	unsigned char res5[0x4];
+	unsigned int req_info_permission_1;	/* 0x68 */
+	unsigned char res6[0x14];
+	unsigned int addr_match_2;		/* 0x80 */
+} pm_t;
+#endif /*__ASSEMBLY__ */
+
+/* Permission values for registers -Full fledged permissions to all */
+#define UNLOCK_1			0xFFFFFFFF
+#define UNLOCK_2			0x00000000
+#define UNLOCK_3			0x0000FFFF
+
+#define NOT_EARLY			0
+
+/* I2C base */
+#define I2C_BASE1		(OMAP34XX_CORE_L4_IO_BASE + 0x70000)
+#define I2C_BASE2		(OMAP34XX_CORE_L4_IO_BASE + 0x72000)
+#define I2C_BASE3		(OMAP34XX_CORE_L4_IO_BASE + 0x60000)
+
+#endif /* _CPU_H */
diff --git a/include/asm-arm/arch-omap3/i2c.h b/include/asm-arm/arch-omap3/i2c.h
new file mode 100644
index 0000000..3937f35
--- /dev/null
+++ b/include/asm-arm/arch-omap3/i2c.h
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _I2C_H_
+#define _I2C_H_
+
+#define I2C_DEFAULT_BASE	I2C_BASE1
+
+#define I2C_REV		(I2C_DEFAULT_BASE + 0x00)
+#define I2C_IE 		(I2C_DEFAULT_BASE + 0x04)
+#define I2C_STAT	(I2C_DEFAULT_BASE + 0x08)
+#define I2C_IV 		(I2C_DEFAULT_BASE + 0x0c)
+#define I2C_BUF		(I2C_DEFAULT_BASE + 0x14)
+#define I2C_CNT		(I2C_DEFAULT_BASE + 0x18)
+#define I2C_DATA	(I2C_DEFAULT_BASE + 0x1c)
+#define I2C_SYSC	(I2C_DEFAULT_BASE + 0x20)
+#define I2C_CON		(I2C_DEFAULT_BASE + 0x24)
+#define I2C_OA 		(I2C_DEFAULT_BASE + 0x28)
+#define I2C_SA 		(I2C_DEFAULT_BASE + 0x2c)
+#define I2C_PSC		(I2C_DEFAULT_BASE + 0x30)
+#define I2C_SCLL	(I2C_DEFAULT_BASE + 0x34)
+#define I2C_SCLH	(I2C_DEFAULT_BASE + 0x38)
+#define I2C_SYSTEST	(I2C_DEFAULT_BASE + 0x3c)
+
+/* I2C masks */
+
+/* I2C Interrupt Enable Register (I2C_IE): */
+#define I2C_IE_GC_IE	(1 << 5)
+#define I2C_IE_XRDY_IE	(1 << 4) /* Transmit data ready interrupt enable */
+#define I2C_IE_RRDY_IE	(1 << 3) /* Receive data ready interrupt enable */
+#define I2C_IE_ARDY_IE	(1 << 2) /* Register access ready interrupt enable */
+#define I2C_IE_NACK_IE	(1 << 1) /* No acknowledgment interrupt enable */
+#define I2C_IE_AL_IE	(1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C Status Register (I2C_STAT): */
+
+#define I2C_STAT_SBD	(1 << 15) /* Single byte data */
+#define I2C_STAT_BB	(1 << 12) /* Bus busy */
+#define I2C_STAT_ROVR	(1 << 11) /* Receive overrun */
+#define I2C_STAT_XUDF	(1 << 10) /* Transmit underflow */
+#define I2C_STAT_AAS	(1 << 9)  /* Address as slave */
+#define I2C_STAT_GC	(1 << 5)
+#define I2C_STAT_XRDY	(1 << 4)  /* Transmit data ready */
+#define I2C_STAT_RRDY	(1 << 3)  /* Receive data ready */
+#define I2C_STAT_ARDY	(1 << 2)  /* Register access ready */
+#define I2C_STAT_NACK	(1 << 1)  /* No acknowledgment interrupt enable */
+#define I2C_STAT_AL	(1 << 0)  /* Arbitration lost interrupt enable */
+
+/* I2C Interrupt Code Register (I2C_INTCODE): */
+
+#define I2C_INTCODE_MASK	7
+#define I2C_INTCODE_NONE	0
+#define I2C_INTCODE_AL		1	/* Arbitration lost */
+#define I2C_INTCODE_NAK		2	/* No acknowledgement/general call */
+#define I2C_INTCODE_ARDY	3	/* Register access ready */
+#define I2C_INTCODE_RRDY	4	/* Rcv data ready */
+#define I2C_INTCODE_XRDY	5	/* Xmit data ready */
+
+/* I2C Buffer Configuration Register (I2C_BUF): */
+
+#define I2C_BUF_RDMA_EN		(1 << 15) /* Receive DMA channel enable */
+#define I2C_BUF_XDMA_EN		(1 << 7)  /* Transmit DMA channel enable */
+
+/* I2C Configuration Register (I2C_CON): */
+
+#define I2C_CON_EN	(1 << 15)  /* I2C module enable */
+#define I2C_CON_BE	(1 << 14)  /* Big endian mode */
+#define I2C_CON_STB	(1 << 11)  /* Start byte mode (master mode only) */
+#define I2C_CON_MST	(1 << 10)  /* Master/slave mode */
+#define I2C_CON_TRX	(1 << 9)   /* Transmitter/receiver mode */
+				   /* (master mode only) */
+#define I2C_CON_XA	(1 << 8)   /* Expand address */
+#define I2C_CON_STP	(1 << 1)   /* Stop condition (master mode only) */
+#define I2C_CON_STT	(1 << 0)   /* Start condition (master mode only) */
+
+/* I2C System Test Register (I2C_SYSTEST): */
+
+#define I2C_SYSTEST_ST_EN	(1 << 15) /* System test enable */
+#define I2C_SYSTEST_FREE	(1 << 14) /* Free running mode, on brkpoint) */
+#define I2C_SYSTEST_TMODE_MASK	(3 << 12) /* Test mode select */
+#define I2C_SYSTEST_TMODE_SHIFT	(12)	  /* Test mode select */
+#define I2C_SYSTEST_SCL_I	(1 << 3)  /* SCL line sense input value */
+#define I2C_SYSTEST_SCL_O	(1 << 2)  /* SCL line drive output value */
+#define I2C_SYSTEST_SDA_I	(1 << 1)  /* SDA line sense input value */
+#define I2C_SYSTEST_SDA_O	(1 << 0)  /* SDA line drive output value */
+
+#define I2C_SCLL_SCLL		0
+#define I2C_SCLL_SCLL_M		0xFF
+#define I2C_SCLL_HSSCLL		8
+#define I2C_SCLH_HSSCLL_M	0xFF
+#define I2C_SCLH_SCLH		0
+#define I2C_SCLH_SCLH_M		0xFF
+#define I2C_SCLH_HSSCLH		8
+#define I2C_SCLH_HSSCLH_M	0xFF
+
+#define OMAP_I2C_STANDARD	100
+#define OMAP_I2C_FAST_MODE	400
+#define OMAP_I2C_HIGH_SPEED	3400
+
+#define SYSTEM_CLOCK_12		12000
+#define SYSTEM_CLOCK_13		13000
+#define SYSTEM_CLOCK_192	19200
+#define SYSTEM_CLOCK_96		96000
+
+#define I2C_IP_CLK		SYSTEM_CLOCK_96
+#define I2C_PSC_MAX		0x0f
+#define I2C_PSC_MIN		0x00
+
+#endif /* _I2C_H_ */
diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h
new file mode 100644
index 0000000..6f0f90b
--- /dev/null
+++ b/include/asm-arm/arch-omap3/mem.h
@@ -0,0 +1,227 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _MEM_H_
+#define _MEM_H_
+
+#define CS0		0x0
+#define CS1		0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
+
+#ifndef __ASSEMBLY__
+typedef enum {
+	STACKED = 0,
+	IP_DDR = 1,
+	COMBO_DDR = 2,
+	IP_SDR = 3,
+} mem_t;
+#endif /* __ASSEMBLY__ */
+
+#define EARLY_INIT	1
+
+/* Slower full frequency range default timings for x32 operation*/
+#define SDP_SDRC_SHARING	0x00000100
+#define SDP_SDRC_MR_0_SDR	0x00000031
+
+/* optimized timings good for current shipping parts */
+#define SDP_3430_SDRC_RFR_CTRL_165MHz	0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
+
+#define DLL_OFFSET		0
+#define DLL_WRITEDDRCLKX2DIS	1
+#define DLL_ENADLL		1
+#define DLL_LOCKDLL		0
+#define DLL_DLLPHASE_72		0
+#define DLL_DLLPHASE_90		1
+
+/* rkw - need to find of 90/72 degree recommendation for speed like before */
+#define SDP_SDRC_DLLAB_CTRL	((DLL_ENADLL << 3) | \
+				(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
+
+/* Infineon part of 3430SDP (165MHz optimized) 6.06ns
+ *   ACTIMA
+ *	TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
+ *	TDPL (Twr) = 15/6	= 2.5 -> 3
+ *	TRRD = 12/6	= 2
+ *	TRCD = 18/6	= 3
+ *	TRP = 18/6	= 3
+ *	TRAS = 42/6	= 7
+ *	TRC = 60/6	= 10
+ *	TRFC = 72/6	= 12
+ *   ACTIMB
+ *	TCKE = 2
+ *	XSR = 120/6 = 20
+ */
+#define TDAL_165	6
+#define TDPL_165	3
+#define TRRD_165	2
+#define TRCD_165	3
+#define TRP_165		3
+#define TRAS_165	7
+#define TRC_165		10
+#define TRFC_165	21
+#define V_ACTIMA_165	((TRFC_165 << 27) | (TRC_165 << 22) | \
+			(TRAS_165 << 18) | (TRP_165 << 15) |  \
+			(TRCD_165 << 12) | (TRRD_165 << 9) |  \
+			(TDPL_165 << 6) | (TDAL_165))
+
+#define TWTR_165	1
+#define TCKE_165	1
+#define TXP_165		5
+#define XSR_165		23
+#define V_ACTIMB_165	(((TCKE_165 << 12) | (XSR_165 << 0)) |	\
+			(TXP_165 << 8) | (TWTR_165 << 16))
+
+#define SDP_SDRC_ACTIM_CTRLA_0	V_ACTIMA_165
+#define SDP_SDRC_ACTIM_CTRLB_0	V_ACTIMB_165
+#define SDP_SDRC_RFR_CTRL	SDP_3430_SDRC_RFR_CTRL_165MHz
+
+/*
+ * GPMC settings -
+ * Definitions is as per the following format
+ * #define <PART>_GPMC_CONFIG<x> <value>
+ * Where:
+ * PART is the part name e.g. STNOR - Intel Strata Flash
+ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
+ * Value is corresponding value
+ *
+ * For every valid PRCM configuration there should be only one definition of
+ * the same. if values are independent of the board, this definition will be
+ * present in this file if values are dependent on the board, then this should
+ * go into corresponding mem-boardName.h file
+ *
+ * Currently valid part Names are (PART):
+ * STNOR - Intel Strata Flash
+ * SMNAND - Samsung NAND
+ * MPDB - H4 MPDB board
+ * SBNOR - Sibley NOR
+ * MNAND - Micron Large page x16 NAND
+ * ONNAND - Samsung One NAND
+ *
+ * include/configs/file.h contains the defn - for all CS we are interested
+ * #define OMAP34XX_GPMC_CSx PART
+ * #define OMAP34XX_GPMC_CSx_SIZE Size
+ * #define OMAP34XX_GPMC_CSx_MAP Map
+ * Where:
+ * x - CS number
+ * PART - Part Name as defined above
+ * SIZE - how big is the mapping to be
+ *   GPMC_SIZE_128M - 0x8
+ *   GPMC_SIZE_64M  - 0xC
+ *   GPMC_SIZE_32M  - 0xE
+ *   GPMC_SIZE_16M  - 0xF
+ * MAP  - Map this CS to which address(GPMC address space)- Absolute address
+ *   >>24 before being used.
+ */
+#define GPMC_SIZE_128M	0x8
+#define GPMC_SIZE_64M	0xC
+#define GPMC_SIZE_32M	0xE
+#define GPMC_SIZE_16M	0xF
+
+#define SMNAND_GPMC_CONFIG1	0x00000800
+#define SMNAND_GPMC_CONFIG2	0x00141400
+#define SMNAND_GPMC_CONFIG3	0x00141400
+#define SMNAND_GPMC_CONFIG4	0x0F010F01
+#define SMNAND_GPMC_CONFIG5	0x010C1414
+#define SMNAND_GPMC_CONFIG6	0x1F0F0A80
+#define SMNAND_GPMC_CONFIG7	0x00000C44
+
+#define M_NAND_GPMC_CONFIG1	0x00001800
+#define M_NAND_GPMC_CONFIG2	0x00141400
+#define M_NAND_GPMC_CONFIG3	0x00141400
+#define M_NAND_GPMC_CONFIG4	0x0F010F01
+#define M_NAND_GPMC_CONFIG5	0x010C1414
+#define M_NAND_GPMC_CONFIG6	0x1f0f0A80
+#define M_NAND_GPMC_CONFIG7	0x00000C44
+
+#define STNOR_GPMC_CONFIG1	0x3
+#define STNOR_GPMC_CONFIG2	0x00151501
+#define STNOR_GPMC_CONFIG3	0x00060602
+#define STNOR_GPMC_CONFIG4	0x11091109
+#define STNOR_GPMC_CONFIG5	0x01141F1F
+#define STNOR_GPMC_CONFIG6	0x000004c4
+
+#define SIBNOR_GPMC_CONFIG1	0x1200
+#define SIBNOR_GPMC_CONFIG2	0x001f1f00
+#define SIBNOR_GPMC_CONFIG3	0x00080802
+#define SIBNOR_GPMC_CONFIG4	0x1C091C09
+#define SIBNOR_GPMC_CONFIG5	0x01131F1F
+#define SIBNOR_GPMC_CONFIG6	0x1F0F03C2
+
+#define SDPV2_MPDB_GPMC_CONFIG1	0x00611200
+#define SDPV2_MPDB_GPMC_CONFIG2	0x001F1F01
+#define SDPV2_MPDB_GPMC_CONFIG3	0x00080803
+#define SDPV2_MPDB_GPMC_CONFIG4	0x1D091D09
+#define SDPV2_MPDB_GPMC_CONFIG5	0x041D1F1F
+#define SDPV2_MPDB_GPMC_CONFIG6	0x1D0904C4
+
+#define MPDB_GPMC_CONFIG1	0x00011000
+#define MPDB_GPMC_CONFIG2	0x001f1f01
+#define MPDB_GPMC_CONFIG3	0x00080803
+#define MPDB_GPMC_CONFIG4	0x1c0b1c0a
+#define MPDB_GPMC_CONFIG5	0x041f1F1F
+#define MPDB_GPMC_CONFIG6	0x1F0F04C4
+
+#define P2_GPMC_CONFIG1	0x0
+#define P2_GPMC_CONFIG2	0x0
+#define P2_GPMC_CONFIG3	0x0
+#define P2_GPMC_CONFIG4	0x0
+#define P2_GPMC_CONFIG5	0x0
+#define P2_GPMC_CONFIG6	0x0
+
+#define ONENAND_GPMC_CONFIG1	0x00001200
+#define ONENAND_GPMC_CONFIG2	0x000F0F01
+#define ONENAND_GPMC_CONFIG3	0x00030301
+#define ONENAND_GPMC_CONFIG4	0x0F040F04
+#define ONENAND_GPMC_CONFIG5	0x010F1010
+#define ONENAND_GPMC_CONFIG6	0x1F060000
+
+#define NET_GPMC_CONFIG1	0x00001000
+#define NET_GPMC_CONFIG2	0x001e1e01
+#define NET_GPMC_CONFIG3	0x00080300
+#define NET_GPMC_CONFIG4	0x1c091c09
+#define NET_GPMC_CONFIG5	0x04181f1f
+#define NET_GPMC_CONFIG6	0x00000FCF
+#define NET_GPMC_CONFIG7	0x00000f6c
+
+/* max number of GPMC Chip Selects */
+#define GPMC_MAX_CS	8
+/* max number of GPMC regs */
+#define GPMC_MAX_REG	7
+
+#define PISMO1_NOR	1
+#define PISMO1_NAND	2
+#define PISMO2_CS0	3
+#define PISMO2_CS1	4
+#define PISMO1_ONENAND	5
+#define DBG_MPDB	6
+#define PISMO2_NAND_CS0 7
+#define PISMO2_NAND_CS1 8
+
+/* make it readable for the gpmc_init */
+#define PISMO1_NOR_BASE		FLASH_BASE
+#define PISMO1_NAND_BASE	NAND_BASE
+#define PISMO2_CS0_BASE		PISMO2_MAP1
+#define PISMO1_ONEN_BASE	ONENAND_MAP
+#define DBG_MPDB_BASE		DEBUG_BASE
+
+#endif /* endif _MEM_H_ */
diff --git a/include/asm-arm/arch-omap3/mmc.h b/include/asm-arm/arch-omap3/mmc.h
new file mode 100644
index 0000000..55584d9
--- /dev/null
+++ b/include/asm-arm/arch-omap3/mmc.h
@@ -0,0 +1,235 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_H
+#define MMC_H
+
+#include "mmc_host_def.h"
+
+/* Responses */
+#define RSP_TYPE_NONE	(RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
+#define RSP_TYPE_R1	(RSP_TYPE_LGHT48  | CCCE_CHECK   | CICE_CHECK)
+#define RSP_TYPE_R1B	(RSP_TYPE_LGHT48B | CCCE_CHECK   | CICE_CHECK)
+#define RSP_TYPE_R2	(RSP_TYPE_LGHT136 | CCCE_CHECK   | CICE_NOCHECK)
+#define RSP_TYPE_R3	(RSP_TYPE_LGHT48  | CCCE_NOCHECK | CICE_NOCHECK)
+#define RSP_TYPE_R4	(RSP_TYPE_LGHT48  | CCCE_NOCHECK | CICE_NOCHECK)
+#define RSP_TYPE_R5	(RSP_TYPE_LGHT48  | CCCE_CHECK   | CICE_CHECK)
+#define RSP_TYPE_R6	(RSP_TYPE_LGHT48  | CCCE_CHECK   | CICE_CHECK)
+#define RSP_TYPE_R7	(RSP_TYPE_LGHT48  | CCCE_CHECK   | CICE_CHECK)
+
+/* All supported commands */
+#define MMC_CMD0	(INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD1	(INDEX(1)  | RSP_TYPE_R3   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD2	(INDEX(2)  | RSP_TYPE_R2   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD3	(INDEX(3)  | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_SDCMD3	(INDEX(3)  | RSP_TYPE_R6   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD4	(INDEX(4)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD6	(INDEX(6)  | RSP_TYPE_R1B  | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD7_SELECT	(INDEX(7)  | RSP_TYPE_R1B  | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD7_DESELECT (INDEX(7)| RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD8	(INDEX(8)  | RSP_TYPE_R1   | DP_DATA    | DDIR_READ)
+#define MMC_SDCMD8	(INDEX(8)  | RSP_TYPE_R7   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD9	(INDEX(9)  | RSP_TYPE_R2   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD12	(INDEX(12) | RSP_TYPE_R1B  | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD13	(INDEX(13) | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD15	(INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD16	(INDEX(16) | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD17	(INDEX(17) | RSP_TYPE_R1   | DP_DATA    | DDIR_READ)
+#define MMC_CMD24	(INDEX(24) | RSP_TYPE_R1   | DP_DATA    | DDIR_WRITE)
+#define MMC_ACMD6	(INDEX(6)  | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_ACMD41	(INDEX(41) | RSP_TYPE_R3   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_ACMD51	(INDEX(51) | RSP_TYPE_R1   | DP_DATA    | DDIR_READ)
+#define MMC_CMD55	(INDEX(55) | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
+
+#define MMC_AC_CMD_RCA_MASK	(unsigned int)(0xFFFF << 16)
+#define MMC_BC_CMD_DSR_MASK	(unsigned int)(0xFFFF << 16)
+#define MMC_DSR_DEFAULT		0x0404
+#define SD_CMD8_CHECK_PATTERN	0xAA
+#define SD_CMD8_2_7_3_6_V_RANGE	(0x01 << 8)
+
+/* Clock Configurations and Macros */
+
+#define MMC_CLOCK_REFERENCE		96
+#define MMC_RELATIVE_CARD_ADDRESS	0x1234
+#define MMC_INIT_SEQ_CLK		(MMC_CLOCK_REFERENCE * 1000 / 80)
+#define MMC_400kHz_CLK			(MMC_CLOCK_REFERENCE * 1000 / 400)
+#define CLKDR(r, f, u)			((((r)*100) / ((f)*(u))) + 1)
+#define CLKD(f, u)			(CLKDR(MMC_CLOCK_REFERENCE, f, u))
+
+#define MMC_OCR_REG_ACCESS_MODE_MASK	(0x3 << 29)
+#define MMC_OCR_REG_ACCESS_MODE_BYTE 	(0x0 << 29)
+#define MMC_OCR_REG_ACCESS_MODE_SECTOR	(0x2 << 29)
+
+#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK		(0x1 << 30)
+#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE		(0x0 << 30)
+#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR	(0x1 << 30)
+
+#define MMC_SD2_CSD_C_SIZE_LSB_MASK	0xFFFF
+#define MMC_SD2_CSD_C_SIZE_MSB_MASK	0x003F
+#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET	16
+#define MMC_CSD_C_SIZE_LSB_MASK		0x0003
+#define MMC_CSD_C_SIZE_MSB_MASK		0x03FF
+#define MMC_CSD_C_SIZE_MSB_OFFSET	2
+
+#define MMC_CSD_TRAN_SPEED_UNIT_MASK	(0x07 << 0)
+#define MMC_CSD_TRAN_SPEED_FACTOR_MASK	(0x0F << 3)
+#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ	(0x3 << 0)
+#define MMC_CSD_TRAN_SPEED_FACTOR_1_0	(0x01 << 3)
+#define MMC_CSD_TRAN_SPEED_FACTOR_8_0	(0x0F << 3)
+
+typedef struct {
+	unsigned not_used:1;
+	unsigned crc:7;
+	unsigned ecc:2;
+	unsigned file_format:2;
+	unsigned tmp_write_protect:1;
+	unsigned perm_write_protect:1;
+	unsigned copy:1;
+	unsigned file_format_grp:1;
+	unsigned content_prot_app:1;
+	unsigned reserved_1:4;
+	unsigned write_bl_partial:1;
+	unsigned write_bl_len:4;
+	unsigned r2w_factor:3;
+	unsigned default_ecc:2;
+	unsigned wp_grp_enable:1;
+	unsigned wp_grp_size:5;
+	unsigned erase_grp_mult:5;
+	unsigned erase_grp_size:5;
+	unsigned c_size_mult:3;
+	unsigned vdd_w_curr_max:3;
+	unsigned vdd_w_curr_min:3;
+	unsigned vdd_r_curr_max:3;
+	unsigned vdd_r_curr_min:3;
+	unsigned c_size_lsb:2;
+	unsigned c_size_msb:10;
+	unsigned reserved_2:2;
+	unsigned dsr_imp:1;
+	unsigned read_blk_misalign:1;
+	unsigned write_blk_misalign:1;
+	unsigned read_bl_partial:1;
+	unsigned read_bl_len:4;
+	unsigned ccc:12;
+	unsigned tran_speed:8;
+	unsigned nsac:8;
+	unsigned taac:8;
+	unsigned reserved_3:2;
+	unsigned spec_vers:4;
+	unsigned csd_structure:2;
+} mmc_csd_reg_t;
+
+/* csd for sd2.0 */
+typedef struct {
+	unsigned not_used:1;
+	unsigned crc:7;
+	unsigned reserved_1:2;
+	unsigned file_format:2;
+	unsigned tmp_write_protect:1;
+	unsigned perm_write_protect:1;
+	unsigned copy:1;
+	unsigned file_format_grp:1;
+	unsigned reserved_2:5;
+	unsigned write_bl_partial:1;
+	unsigned write_bl_len:4;
+	unsigned r2w_factor:3;
+	unsigned reserved_3:2;
+	unsigned wp_grp_enable:1;
+	unsigned wp_grp_size:7;
+	unsigned sector_size:7;
+	unsigned erase_blk_len:1;
+	unsigned reserved_4:1;
+	unsigned c_size_lsb:16;
+	unsigned c_size_msb:6;
+	unsigned reserved_5:6;
+	unsigned dsr_imp:1;
+	unsigned read_blk_misalign:1;
+	unsigned write_blk_misalign:1;
+	unsigned read_bl_partial:1;
+	unsigned read_bl_len:4;
+	unsigned ccc:12;
+	unsigned tran_speed:8;
+	unsigned nsac:8;
+	unsigned taac:8;
+	unsigned reserved_6:6;
+	unsigned csd_structure:2;
+} mmc_sd2_csd_reg_t;
+
+/* extended csd - 512 bytes long */
+typedef struct {
+	unsigned char reserved_1[181];
+	unsigned char erasedmemorycontent;
+	unsigned char reserved_2;
+	unsigned char buswidthmode;
+	unsigned char reserved_3;
+	unsigned char highspeedinterfacetiming;
+	unsigned char reserved_4;
+	unsigned char powerclass;
+	unsigned char reserved_5;
+	unsigned char commandsetrevision;
+	unsigned char reserved_6;
+	unsigned char commandset;
+	unsigned char extendedcsdrevision;
+	unsigned char reserved_7;
+	unsigned char csdstructureversion;
+	unsigned char reserved_8;
+	unsigned char cardtype;
+	unsigned char reserved_9[3];
+	unsigned char powerclass_52mhz_1_95v;
+	unsigned char powerclass_26mhz_1_95v;
+	unsigned char powerclass_52mhz_3_6v;
+	unsigned char powerclass_26mhz_3_6v;
+	unsigned char reserved_10;
+	unsigned char minreadperf_4b_26mhz;
+	unsigned char minwriteperf_4b_26mhz;
+	unsigned char minreadperf_8b_26mhz_4b_52mhz;
+	unsigned char minwriteperf_8b_26mhz_4b_52mhz;
+	unsigned char minreadperf_8b_52mhz;
+	unsigned char minwriteperf_8b_52mhz;
+	unsigned char reserved_11;
+	unsigned int sectorcount;
+	unsigned char reserved_12[288];
+	unsigned char supportedcommandsets;
+	unsigned char reserved_13[7];
+} mmc_extended_csd_reg_t;
+
+/* mmc sd responce */
+typedef struct {
+	unsigned int ocr;
+} mmc_resp_r3;
+
+typedef struct {
+	unsigned short cardstatus;
+	unsigned short newpublishedrca;
+} mmc_resp_r6;
+
+extern mmc_card_data mmc_dev;
+
+unsigned char mmc_lowlevel_init(void);
+unsigned char mmc_send_command(unsigned int cmd, unsigned int arg,
+			       unsigned int *response);
+unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd);
+unsigned char mmc_set_opendrain(unsigned char state);
+unsigned char mmc_read_data(unsigned int *output_buf);
+
+#endif /* MMC_H */
diff --git a/include/asm-arm/arch-omap3/mmc_host_def.h b/include/asm-arm/arch-omap3/mmc_host_def.h
new file mode 100644
index 0000000..aa751c9
--- /dev/null
+++ b/include/asm-arm/arch-omap3/mmc_host_def.h
@@ -0,0 +1,184 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+/* T2 Register definitions */
+#define T2_BASE			0x48002000
+
+typedef struct t2 {
+	unsigned char res1[0x274];
+	unsigned int devconf0;		/* 0x274 */
+	unsigned char res2[0x2A8];
+	unsigned int pbias_lite;	/* 0x520 */
+} t2_t;
+
+#define MMCSDIO1ADPCLKISEL		(1 << 24)
+
+#define PBIASLITEPWRDNZ0		(1 << 1)
+#define PBIASSPEEDCTRL0			(1 << 2)
+#define PBIASLITEPWRDNZ1		(1 << 9)
+
+/*
+ * OMAP HSMMC register definitions
+ */
+#define OMAP_HSMMC_BASE		0x4809C000
+
+typedef struct hsmmc {
+	unsigned char res1[0x10];
+	unsigned int sysconfig;		/* 0x10 */
+	unsigned int sysstatus;		/* 0x14 */
+	unsigned char res2[0x14];
+	unsigned int con;		/* 0x2C */
+	unsigned char res3[0xD4];
+	unsigned int blk;		/* 0x104 */
+	unsigned int arg;		/* 0x108 */
+	unsigned int cmd;		/* 0x10C */
+	unsigned int rsp10;		/* 0x110 */
+	unsigned int rsp32;		/* 0x114 */
+	unsigned int rsp54;		/* 0x118 */
+	unsigned int rsp76;		/* 0x11C */
+	unsigned int data;		/* 0x120 */
+	unsigned int pstate;		/* 0x124 */
+	unsigned int hctl;		/* 0x128 */
+	unsigned int sysctl;		/* 0x12C */
+	unsigned int stat;		/* 0x130 */
+	unsigned int ie;		/* 0x134 */
+	unsigned char res4[0x8];
+	unsigned int capa;		/* 0x140 */
+} hsmmc_t;
+
+/*
+ * OMAP HS MMC Bit definitions
+ */
+#define MMC_SOFTRESET			(0x1 << 1)
+#define RESETDONE			(0x1 << 0)
+#define NOOPENDRAIN			(0x0 << 0)
+#define OPENDRAIN			(0x1 << 0)
+#define OD				(0x1 << 0)
+#define INIT_NOINIT			(0x0 << 1)
+#define INIT_INITSTREAM			(0x1 << 1)
+#define HR_NOHOSTRESP			(0x0 << 2)
+#define STR_BLOCK 			(0x0 << 3)
+#define MODE_FUNC			(0x0 << 4)
+#define DW8_1_4BITMODE 			(0x0 << 5)
+#define MIT_CTO				(0x0 << 6)
+#define CDP_ACTIVEHIGH			(0x0 << 7)
+#define WPP_ACTIVEHIGH 			(0x0 << 8)
+#define RESERVED_MASK			(0x3 << 9)
+#define CTPL_MMC_SD 			(0x0 << 11)
+#define BLEN_512BYTESLEN		(0x200 << 0)
+#define NBLK_STPCNT			(0x0 << 16)
+#define DE_DISABLE			(0x0 << 0)
+#define BCE_DISABLE			(0x0 << 1)
+#define ACEN_DISABLE			(0x0 << 2)
+#define DDIR_OFFSET			(4)
+#define DDIR_MASK			(0x1 << 4)
+#define DDIR_WRITE			(0x0 << 4)
+#define DDIR_READ			(0x1 << 4)
+#define MSBS_SGLEBLK			(0x0 << 5)
+#define RSP_TYPE_OFFSET			(16)
+#define RSP_TYPE_MASK			(0x3 << 16)
+#define RSP_TYPE_NORSP			(0x0 << 16)
+#define RSP_TYPE_LGHT136		(0x1 << 16)
+#define RSP_TYPE_LGHT48			(0x2 << 16)
+#define RSP_TYPE_LGHT48B		(0x3 << 16)
+#define CCCE_NOCHECK			(0x0 << 19)
+#define CCCE_CHECK			(0x1 << 19)
+#define CICE_NOCHECK			(0x0 << 20)
+#define CICE_CHECK			(0x1 << 20)
+#define DP_OFFSET			(21)
+#define DP_MASK				(0x1 << 21)
+#define DP_NO_DATA			(0x0 << 21)
+#define DP_DATA				(0x1 << 21)
+#define CMD_TYPE_NORMAL			(0x0 << 22)
+#define INDEX_OFFSET			(24)
+#define INDEX_MASK			(0x3f << 24)
+#define INDEX(i)			(i << 24)
+#define DATI_MASK			(0x1 << 1)
+#define DATI_CMDDIS			(0x1 << 1)
+#define DTW_1_BITMODE			(0x0 << 1)
+#define DTW_4_BITMODE			(0x1 << 1)
+#define SDBP_PWROFF			(0x0 << 8)
+#define SDBP_PWRON			(0x1 << 8)
+#define SDVS_1V8			(0x5 << 9)
+#define SDVS_3V0			(0x6 << 9)
+#define ICE_MASK			(0x1 << 0)
+#define ICE_STOP			(0x0 << 0)
+#define ICS_MASK			(0x1 << 1)
+#define ICS_NOTREADY			(0x0 << 1)
+#define ICE_OSCILLATE			(0x1 << 0)
+#define CEN_MASK			(0x1 << 2)
+#define CEN_DISABLE			(0x0 << 2)
+#define CEN_ENABLE			(0x1 << 2)
+#define CLKD_OFFSET			(6)
+#define CLKD_MASK			(0x3FF << 6)
+#define DTO_MASK			(0xF << 16)
+#define DTO_15THDTO			(0xE << 16)
+#define SOFTRESETALL			(0x1 << 24)
+#define CC_MASK				(0x1 << 0)
+#define TC_MASK				(0x1 << 1)
+#define BWR_MASK			(0x1 << 4)
+#define BRR_MASK			(0x1 << 5)
+#define ERRI_MASK			(0x1 << 15)
+#define IE_CC				(0x01 << 0)
+#define IE_TC				(0x01 << 1)
+#define IE_BWR				(0x01 << 4)
+#define IE_BRR				(0x01 << 5)
+#define IE_CTO				(0x01 << 16)
+#define IE_CCRC				(0x01 << 17)
+#define IE_CEB				(0x01 << 18)
+#define IE_CIE				(0x01 << 19)
+#define IE_DTO				(0x01 << 20)
+#define IE_DCRC				(0x01 << 21)
+#define IE_DEB				(0x01 << 22)
+#define IE_CERR				(0x01 << 28)
+#define IE_BADA				(0x01 << 29)
+
+#define VS30_3V0SUP			(1 << 25)
+#define VS18_1V8SUP			(1 << 26)
+
+/* Driver definitions */
+#define MMCSD_SECTOR_SIZE		512
+#define MMC_CARD			0
+#define SD_CARD				1
+#define BYTE_MODE			0
+#define SECTOR_MODE			1
+#define CLK_INITSEQ			0
+#define CLK_400KHZ			1
+#define CLK_MISC			2
+
+typedef struct {
+	unsigned int card_type;
+	unsigned int version;
+	unsigned int mode;
+	unsigned int size;
+	unsigned int RCA;
+} mmc_card_data;
+
+#define mmc_reg_out(addr, mask, val)\
+	writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
+
+#endif /* MMC_HOST_DEF_H */
diff --git a/include/asm-arm/arch-omap3/mux.h b/include/asm-arm/arch-omap3/mux.h
new file mode 100644
index 0000000..0c01c73
--- /dev/null
+++ b/include/asm-arm/arch-omap3/mux.h
@@ -0,0 +1,412 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MUX_H_
+#define _MUX_H_
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ */
+
+#define IEN	(1 << 8)
+
+#define IDIS	(0 << 8)
+#define PTU	(1 << 4)
+#define PTD	(0 << 4)
+#define EN	(1 << 3)
+#define DIS	(0 << 3)
+
+#define M0	0
+#define M1	1
+#define M2	2
+#define M3	3
+#define M4	4
+#define M5	5
+#define M6	6
+#define M7	7
+
+/*
+ * To get the actual address the offset has to added
+ * with OMAP34XX_CTRL_BASE to get the actual address
+ */
+
+/*SDRC*/
+#define CONTROL_PADCONF_SDRC_D0		0x0030
+#define CONTROL_PADCONF_SDRC_D1		0x0032
+#define CONTROL_PADCONF_SDRC_D2		0x0034
+#define CONTROL_PADCONF_SDRC_D3		0x0036
+#define CONTROL_PADCONF_SDRC_D4		0x0038
+#define CONTROL_PADCONF_SDRC_D5		0x003A
+#define CONTROL_PADCONF_SDRC_D6		0x003C
+#define CONTROL_PADCONF_SDRC_D7		0x003E
+#define CONTROL_PADCONF_SDRC_D8		0x0040
+#define CONTROL_PADCONF_SDRC_D9		0x0042
+#define CONTROL_PADCONF_SDRC_D10	0x0044
+#define CONTROL_PADCONF_SDRC_D11	0x0046
+#define CONTROL_PADCONF_SDRC_D12	0x0048
+#define CONTROL_PADCONF_SDRC_D13	0x004A
+#define CONTROL_PADCONF_SDRC_D14	0x004C
+#define CONTROL_PADCONF_SDRC_D15	0x004E
+#define CONTROL_PADCONF_SDRC_D16	0x0050
+#define CONTROL_PADCONF_SDRC_D17	0x0052
+#define CONTROL_PADCONF_SDRC_D18	0x0054
+#define CONTROL_PADCONF_SDRC_D19	0x0056
+#define CONTROL_PADCONF_SDRC_D20	0x0058
+#define CONTROL_PADCONF_SDRC_D21	0x005A
+#define CONTROL_PADCONF_SDRC_D22	0x005C
+#define CONTROL_PADCONF_SDRC_D23	0x005E
+#define CONTROL_PADCONF_SDRC_D24	0x0060
+#define CONTROL_PADCONF_SDRC_D25	0x0062
+#define CONTROL_PADCONF_SDRC_D26	0x0064
+#define CONTROL_PADCONF_SDRC_D27	0x0066
+#define CONTROL_PADCONF_SDRC_D28	0x0068
+#define CONTROL_PADCONF_SDRC_D29	0x006A
+#define CONTROL_PADCONF_SDRC_D30	0x006C
+#define CONTROL_PADCONF_SDRC_D31	0x006E
+#define CONTROL_PADCONF_SDRC_CLK	0x0070
+#define CONTROL_PADCONF_SDRC_DQS0	0x0072
+#define CONTROL_PADCONF_SDRC_DQS1	0x0074
+#define CONTROL_PADCONF_SDRC_DQS2	0x0076
+#define CONTROL_PADCONF_SDRC_DQS3	0x0078
+/*GPMC*/
+#define CONTROL_PADCONF_GPMC_A1		0x007A
+#define CONTROL_PADCONF_GPMC_A2		0x007C
+#define CONTROL_PADCONF_GPMC_A3		0x007E
+#define CONTROL_PADCONF_GPMC_A4		0x0080
+#define CONTROL_PADCONF_GPMC_A5		0x0082
+#define CONTROL_PADCONF_GPMC_A6		0x0084
+#define CONTROL_PADCONF_GPMC_A7		0x0086
+#define CONTROL_PADCONF_GPMC_A8		0x0088
+#define CONTROL_PADCONF_GPMC_A9		0x008A
+#define CONTROL_PADCONF_GPMC_A10	0x008C
+#define CONTROL_PADCONF_GPMC_D0		0x008E
+#define CONTROL_PADCONF_GPMC_D1		0x0090
+#define CONTROL_PADCONF_GPMC_D2		0x0092
+#define CONTROL_PADCONF_GPMC_D3		0x0094
+#define CONTROL_PADCONF_GPMC_D4		0x0096
+#define CONTROL_PADCONF_GPMC_D5		0x0098
+#define CONTROL_PADCONF_GPMC_D6		0x009A
+#define CONTROL_PADCONF_GPMC_D7		0x009C
+#define CONTROL_PADCONF_GPMC_D8		0x009E
+#define CONTROL_PADCONF_GPMC_D9		0x00A0
+#define CONTROL_PADCONF_GPMC_D10	0x00A2
+#define CONTROL_PADCONF_GPMC_D11	0x00A4
+#define CONTROL_PADCONF_GPMC_D12	0x00A6
+#define CONTROL_PADCONF_GPMC_D13	0x00A8
+#define CONTROL_PADCONF_GPMC_D14	0x00AA
+#define CONTROL_PADCONF_GPMC_D15	0x00AC
+#define CONTROL_PADCONF_GPMC_NCS0	0x00AE
+#define CONTROL_PADCONF_GPMC_NCS1	0x00B0
+#define CONTROL_PADCONF_GPMC_NCS2	0x00B2
+#define CONTROL_PADCONF_GPMC_NCS3	0x00B4
+#define CONTROL_PADCONF_GPMC_NCS4	0x00B6
+#define CONTROL_PADCONF_GPMC_NCS5	0x00B8
+#define CONTROL_PADCONF_GPMC_NCS6	0x00BA
+#define CONTROL_PADCONF_GPMC_NCS7	0x00BC
+#define CONTROL_PADCONF_GPMC_CLK	0x00BE
+#define CONTROL_PADCONF_GPMC_NADV_ALE	0x00C0
+#define CONTROL_PADCONF_GPMC_NOE	0x00C2
+#define CONTROL_PADCONF_GPMC_NWE	0x00C4
+#define CONTROL_PADCONF_GPMC_NBE0_CLE	0x00C6
+#define CONTROL_PADCONF_GPMC_NBE1	0x00C8
+#define CONTROL_PADCONF_GPMC_NWP	0x00CA
+#define CONTROL_PADCONF_GPMC_WAIT0	0x00CC
+#define CONTROL_PADCONF_GPMC_WAIT1	0x00CE
+#define CONTROL_PADCONF_GPMC_WAIT2	0x00D0
+#define CONTROL_PADCONF_GPMC_WAIT3	0x00D2
+/*DSS*/
+#define CONTROL_PADCONF_DSS_PCLK	0x00D4
+#define CONTROL_PADCONF_DSS_HSYNC	0x00D6
+#define CONTROL_PADCONF_DSS_VSYNC	0x00D8
+#define CONTROL_PADCONF_DSS_ACBIAS	0x00DA
+#define CONTROL_PADCONF_DSS_DATA0	0x00DC
+#define CONTROL_PADCONF_DSS_DATA1	0x00DE
+#define CONTROL_PADCONF_DSS_DATA2	0x00E0
+#define CONTROL_PADCONF_DSS_DATA3	0x00E2
+#define CONTROL_PADCONF_DSS_DATA4	0x00E4
+#define CONTROL_PADCONF_DSS_DATA5	0x00E6
+#define CONTROL_PADCONF_DSS_DATA6	0x00E8
+#define CONTROL_PADCONF_DSS_DATA7	0x00EA
+#define CONTROL_PADCONF_DSS_DATA8	0x00EC
+#define CONTROL_PADCONF_DSS_DATA9	0x00EE
+#define CONTROL_PADCONF_DSS_DATA10	0x00F0
+#define CONTROL_PADCONF_DSS_DATA11	0x00F2
+#define CONTROL_PADCONF_DSS_DATA12	0x00F4
+#define CONTROL_PADCONF_DSS_DATA13	0x00F6
+#define CONTROL_PADCONF_DSS_DATA14	0x00F8
+#define CONTROL_PADCONF_DSS_DATA15	0x00FA
+#define CONTROL_PADCONF_DSS_DATA16	0x00FC
+#define CONTROL_PADCONF_DSS_DATA17	0x00FE
+#define CONTROL_PADCONF_DSS_DATA18	0x0100
+#define CONTROL_PADCONF_DSS_DATA19	0x0102
+#define CONTROL_PADCONF_DSS_DATA20	0x0104
+#define CONTROL_PADCONF_DSS_DATA21	0x0106
+#define CONTROL_PADCONF_DSS_DATA22	0x0108
+#define CONTROL_PADCONF_DSS_DATA23	0x010A
+/*CAMERA*/
+#define CONTROL_PADCONF_CAM_HS		0x010C
+#define CONTROL_PADCONF_CAM_VS		0x010E
+#define CONTROL_PADCONF_CAM_XCLKA	0x0110
+#define CONTROL_PADCONF_CAM_PCLK	0x0112
+#define CONTROL_PADCONF_CAM_FLD		0x0114
+#define CONTROL_PADCONF_CAM_D0		0x0116
+#define CONTROL_PADCONF_CAM_D1		0x0118
+#define CONTROL_PADCONF_CAM_D2		0x011A
+#define CONTROL_PADCONF_CAM_D3		0x011C
+#define CONTROL_PADCONF_CAM_D4		0x011E
+#define CONTROL_PADCONF_CAM_D5		0x0120
+#define CONTROL_PADCONF_CAM_D6		0x0122
+#define CONTROL_PADCONF_CAM_D7		0x0124
+#define CONTROL_PADCONF_CAM_D8		0x0126
+#define CONTROL_PADCONF_CAM_D9		0x0128
+#define CONTROL_PADCONF_CAM_D10		0x012A
+#define CONTROL_PADCONF_CAM_D11		0x012C
+#define CONTROL_PADCONF_CAM_XCLKB	0x012E
+#define CONTROL_PADCONF_CAM_WEN		0x0130
+#define CONTROL_PADCONF_CAM_STROBE	0x0132
+#define CONTROL_PADCONF_CSI2_DX0	0x0134
+#define CONTROL_PADCONF_CSI2_DY0	0x0136
+#define CONTROL_PADCONF_CSI2_DX1	0x0138
+#define CONTROL_PADCONF_CSI2_DY1	0x013A
+/*Audio Interface */
+#define CONTROL_PADCONF_MCBSP2_FSX	0x013C
+#define CONTROL_PADCONF_MCBSP2_CLKX	0x013E
+#define CONTROL_PADCONF_MCBSP2_DR	0x0140
+#define CONTROL_PADCONF_MCBSP2_DX	0x0142
+#define CONTROL_PADCONF_MMC1_CLK	0x0144
+#define CONTROL_PADCONF_MMC1_CMD	0x0146
+#define CONTROL_PADCONF_MMC1_DAT0	0x0148
+#define CONTROL_PADCONF_MMC1_DAT1	0x014A
+#define CONTROL_PADCONF_MMC1_DAT2	0x014C
+#define CONTROL_PADCONF_MMC1_DAT3	0x014E
+#define CONTROL_PADCONF_MMC1_DAT4	0x0150
+#define CONTROL_PADCONF_MMC1_DAT5	0x0152
+#define CONTROL_PADCONF_MMC1_DAT6	0x0154
+#define CONTROL_PADCONF_MMC1_DAT7	0x0156
+/*Wireless LAN */
+#define CONTROL_PADCONF_MMC2_CLK	0x0158
+#define CONTROL_PADCONF_MMC2_CMD	0x015A
+#define CONTROL_PADCONF_MMC2_DAT0	0x015C
+#define CONTROL_PADCONF_MMC2_DAT1	0x015E
+#define CONTROL_PADCONF_MMC2_DAT2	0x0160
+#define CONTROL_PADCONF_MMC2_DAT3	0x0162
+#define CONTROL_PADCONF_MMC2_DAT4	0x0164
+#define CONTROL_PADCONF_MMC2_DAT5	0x0166
+#define CONTROL_PADCONF_MMC2_DAT6	0x0168
+#define CONTROL_PADCONF_MMC2_DAT7	0x016A
+/*Bluetooth*/
+#define CONTROL_PADCONF_MCBSP3_DX	0x016C
+#define CONTROL_PADCONF_MCBSP3_DR	0x016E
+#define CONTROL_PADCONF_MCBSP3_CLKX	0x0170
+#define CONTROL_PADCONF_MCBSP3_FSX	0x0172
+#define CONTROL_PADCONF_UART2_CTS	0x0174
+#define CONTROL_PADCONF_UART2_RTS	0x0176
+#define CONTROL_PADCONF_UART2_TX	0x0178
+#define CONTROL_PADCONF_UART2_RX	0x017A
+/*Modem Interface */
+#define CONTROL_PADCONF_UART1_TX	0x017C
+#define CONTROL_PADCONF_UART1_RTS	0x017E
+#define CONTROL_PADCONF_UART1_CTS	0x0180
+#define CONTROL_PADCONF_UART1_RX	0x0182
+#define CONTROL_PADCONF_MCBSP4_CLKX	0x0184
+#define CONTROL_PADCONF_MCBSP4_DR	0x0186
+#define CONTROL_PADCONF_MCBSP4_DX	0x0188
+#define CONTROL_PADCONF_MCBSP4_FSX	0x018A
+#define CONTROL_PADCONF_MCBSP1_CLKR	0x018C
+#define CONTROL_PADCONF_MCBSP1_FSR	0x018E
+#define CONTROL_PADCONF_MCBSP1_DX	0x0190
+#define CONTROL_PADCONF_MCBSP1_DR	0x0192
+#define CONTROL_PADCONF_MCBSP_CLKS	0x0194
+#define CONTROL_PADCONF_MCBSP1_FSX	0x0196
+#define CONTROL_PADCONF_MCBSP1_CLKX	0x0198
+/*Serial Interface*/
+#define CONTROL_PADCONF_UART3_CTS_RCTX	0x019A
+#define CONTROL_PADCONF_UART3_RTS_SD	0x019C
+#define CONTROL_PADCONF_UART3_RX_IRRX	0x019E
+#define CONTROL_PADCONF_UART3_TX_IRTX	0x01A0
+#define CONTROL_PADCONF_HSUSB0_CLK	0x01A2
+#define CONTROL_PADCONF_HSUSB0_STP	0x01A4
+#define CONTROL_PADCONF_HSUSB0_DIR	0x01A6
+#define CONTROL_PADCONF_HSUSB0_NXT	0x01A8
+#define CONTROL_PADCONF_HSUSB0_DATA0	0x01AA
+#define CONTROL_PADCONF_HSUSB0_DATA1	0x01AC
+#define CONTROL_PADCONF_HSUSB0_DATA2	0x01AE
+#define CONTROL_PADCONF_HSUSB0_DATA3	0x01B0
+#define CONTROL_PADCONF_HSUSB0_DATA4	0x01B2
+#define CONTROL_PADCONF_HSUSB0_DATA5	0x01B4
+#define CONTROL_PADCONF_HSUSB0_DATA6	0x01B6
+#define CONTROL_PADCONF_HSUSB0_DATA7	0x01B8
+#define CONTROL_PADCONF_I2C1_SCL	0x01BA
+#define CONTROL_PADCONF_I2C1_SDA	0x01BC
+#define CONTROL_PADCONF_I2C2_SCL	0x01BE
+#define CONTROL_PADCONF_I2C2_SDA	0x01C0
+#define CONTROL_PADCONF_I2C3_SCL	0x01C2
+#define CONTROL_PADCONF_I2C3_SDA	0x01C4
+#define CONTROL_PADCONF_I2C4_SCL	0x0A00
+#define CONTROL_PADCONF_I2C4_SDA	0x0A02
+#define CONTROL_PADCONF_HDQ_SIO		0x01C6
+#define CONTROL_PADCONF_MCSPI1_CLK	0x01C8
+#define CONTROL_PADCONF_MCSPI1_SIMO	0x01CA
+#define CONTROL_PADCONF_MCSPI1_SOMI	0x01CC
+#define CONTROL_PADCONF_MCSPI1_CS0	0x01CE
+#define CONTROL_PADCONF_MCSPI1_CS1	0x01D0
+#define CONTROL_PADCONF_MCSPI1_CS2	0x01D2
+#define CONTROL_PADCONF_MCSPI1_CS3	0x01D4
+#define CONTROL_PADCONF_MCSPI2_CLK	0x01D6
+#define CONTROL_PADCONF_MCSPI2_SIMO	0x01D8
+#define CONTROL_PADCONF_MCSPI2_SOMI	0x01DA
+#define CONTROL_PADCONF_MCSPI2_CS0	0x01DC
+#define CONTROL_PADCONF_MCSPI2_CS1	0x01DE
+/*Control and debug */
+#define CONTROL_PADCONF_SYS_32K		0x0A04
+#define CONTROL_PADCONF_SYS_CLKREQ	0x0A06
+#define CONTROL_PADCONF_SYS_NIRQ	0x01E0
+#define CONTROL_PADCONF_SYS_BOOT0	0x0A0A
+#define CONTROL_PADCONF_SYS_BOOT1	0x0A0C
+#define CONTROL_PADCONF_SYS_BOOT2	0x0A0E
+#define CONTROL_PADCONF_SYS_BOOT3	0x0A10
+#define CONTROL_PADCONF_SYS_BOOT4	0x0A12
+#define CONTROL_PADCONF_SYS_BOOT5	0x0A14
+#define CONTROL_PADCONF_SYS_BOOT6	0x0A16
+#define CONTROL_PADCONF_SYS_OFF_MODE	0x0A18
+#define CONTROL_PADCONF_SYS_CLKOUT1	0x0A1A
+#define CONTROL_PADCONF_SYS_CLKOUT2	0x01E2
+#define CONTROL_PADCONF_JTAG_nTRST	0x0A1C
+#define CONTROL_PADCONF_JTAG_TCK	0x0A1E
+#define CONTROL_PADCONF_JTAG_TMS	0x0A20
+#define CONTROL_PADCONF_JTAG_TDI	0x0A22
+#define CONTROL_PADCONF_JTAG_EMU0	0x0A24
+#define CONTROL_PADCONF_JTAG_EMU1	0x0A26
+#define CONTROL_PADCONF_ETK_CLK		0x0A28
+#define CONTROL_PADCONF_ETK_CTL		0x0A2A
+#define CONTROL_PADCONF_ETK_D0		0x0A2C
+#define CONTROL_PADCONF_ETK_D1		0x0A2E
+#define CONTROL_PADCONF_ETK_D2		0x0A30
+#define CONTROL_PADCONF_ETK_D3		0x0A32
+#define CONTROL_PADCONF_ETK_D4		0x0A34
+#define CONTROL_PADCONF_ETK_D5		0x0A36
+#define CONTROL_PADCONF_ETK_D6		0x0A38
+#define CONTROL_PADCONF_ETK_D7		0x0A3A
+#define CONTROL_PADCONF_ETK_D8		0x0A3C
+#define CONTROL_PADCONF_ETK_D9		0x0A3E
+#define CONTROL_PADCONF_ETK_D10		0x0A40
+#define CONTROL_PADCONF_ETK_D11		0x0A42
+#define CONTROL_PADCONF_ETK_D12		0x0A44
+#define CONTROL_PADCONF_ETK_D13		0x0A46
+#define CONTROL_PADCONF_ETK_D14		0x0A48
+#define CONTROL_PADCONF_ETK_D15		0x0A4A
+#define CONTROL_PADCONF_ETK_CLK_ES2	0x05D8
+#define CONTROL_PADCONF_ETK_CTL_ES2	0x05DA
+#define CONTROL_PADCONF_ETK_D0_ES2	0x05DC
+#define CONTROL_PADCONF_ETK_D1_ES2	0x05DE
+#define CONTROL_PADCONF_ETK_D2_ES2	0x05E0
+#define CONTROL_PADCONF_ETK_D3_ES2	0x05E2
+#define CONTROL_PADCONF_ETK_D4_ES2	0x05E4
+#define CONTROL_PADCONF_ETK_D5_ES2	0x05E6
+#define CONTROL_PADCONF_ETK_D6_ES2	0x05E8
+#define CONTROL_PADCONF_ETK_D7_ES2	0x05EA
+#define CONTROL_PADCONF_ETK_D8_ES2	0x05EC
+#define CONTROL_PADCONF_ETK_D9_ES2	0x05EE
+#define CONTROL_PADCONF_ETK_D10_ES2	0x05F0
+#define CONTROL_PADCONF_ETK_D11_ES2	0x05F2
+#define CONTROL_PADCONF_ETK_D12_ES2	0x05F4
+#define CONTROL_PADCONF_ETK_D13_ES2	0x05F6
+#define CONTROL_PADCONF_ETK_D14_ES2	0x05F8
+#define CONTROL_PADCONF_ETK_D15_ES2	0x05FA
+/*Die to Die */
+#define CONTROL_PADCONF_D2D_MCAD0	0x01E4
+#define CONTROL_PADCONF_D2D_MCAD1	0x01E6
+#define CONTROL_PADCONF_D2D_MCAD2	0x01E8
+#define CONTROL_PADCONF_D2D_MCAD3	0x01EA
+#define CONTROL_PADCONF_D2D_MCAD4	0x01EC
+#define CONTROL_PADCONF_D2D_MCAD5	0x01EE
+#define CONTROL_PADCONF_D2D_MCAD6	0x01F0
+#define CONTROL_PADCONF_D2D_MCAD7	0x01F2
+#define CONTROL_PADCONF_D2D_MCAD8	0x01F4
+#define CONTROL_PADCONF_D2D_MCAD9	0x01F6
+#define CONTROL_PADCONF_D2D_MCAD10	0x01F8
+#define CONTROL_PADCONF_D2D_MCAD11	0x01FA
+#define CONTROL_PADCONF_D2D_MCAD12	0x01FC
+#define CONTROL_PADCONF_D2D_MCAD13	0x01FE
+#define CONTROL_PADCONF_D2D_MCAD14	0x0200
+#define CONTROL_PADCONF_D2D_MCAD15	0x0202
+#define CONTROL_PADCONF_D2D_MCAD16	0x0204
+#define CONTROL_PADCONF_D2D_MCAD17	0x0206
+#define CONTROL_PADCONF_D2D_MCAD18	0x0208
+#define CONTROL_PADCONF_D2D_MCAD19	0x020A
+#define CONTROL_PADCONF_D2D_MCAD20	0x020C
+#define CONTROL_PADCONF_D2D_MCAD21	0x020E
+#define CONTROL_PADCONF_D2D_MCAD22	0x0210
+#define CONTROL_PADCONF_D2D_MCAD23	0x0212
+#define CONTROL_PADCONF_D2D_MCAD24	0x0214
+#define CONTROL_PADCONF_D2D_MCAD25	0x0216
+#define CONTROL_PADCONF_D2D_MCAD26	0x0218
+#define CONTROL_PADCONF_D2D_MCAD27	0x021A
+#define CONTROL_PADCONF_D2D_MCAD28	0x021C
+#define CONTROL_PADCONF_D2D_MCAD29	0x021E
+#define CONTROL_PADCONF_D2D_MCAD30	0x0220
+#define CONTROL_PADCONF_D2D_MCAD31	0x0222
+#define CONTROL_PADCONF_D2D_MCAD32	0x0224
+#define CONTROL_PADCONF_D2D_MCAD33	0x0226
+#define CONTROL_PADCONF_D2D_MCAD34	0x0228
+#define CONTROL_PADCONF_D2D_MCAD35	0x022A
+#define CONTROL_PADCONF_D2D_MCAD36	0x022C
+#define CONTROL_PADCONF_D2D_CLK26MI	0x022E
+#define CONTROL_PADCONF_D2D_NRESPWRON	0x0230
+#define CONTROL_PADCONF_D2D_NRESWARM	0x0232
+#define CONTROL_PADCONF_D2D_ARM9NIRQ	0x0234
+#define CONTROL_PADCONF_D2D_UMA2P6FIQ	0x0236
+#define CONTROL_PADCONF_D2D_SPINT	0x0238
+#define CONTROL_PADCONF_D2D_FRINT	0x023A
+#define CONTROL_PADCONF_D2D_DMAREQ0	0x023C
+#define CONTROL_PADCONF_D2D_DMAREQ1	0x023E
+#define CONTROL_PADCONF_D2D_DMAREQ2	0x0240
+#define CONTROL_PADCONF_D2D_DMAREQ3	0x0242
+#define CONTROL_PADCONF_D2D_N3GTRST	0x0244
+#define CONTROL_PADCONF_D2D_N3GTDI	0x0246
+#define CONTROL_PADCONF_D2D_N3GTDO	0x0248
+#define CONTROL_PADCONF_D2D_N3GTMS	0x024A
+#define CONTROL_PADCONF_D2D_N3GTCK	0x024C
+#define CONTROL_PADCONF_D2D_N3GRTCK	0x024E
+#define CONTROL_PADCONF_D2D_MSTDBY	0x0250
+#define CONTROL_PADCONF_D2D_SWAKEUP	0x0A4C
+#define CONTROL_PADCONF_D2D_IDLEREQ	0x0252
+#define CONTROL_PADCONF_D2D_IDLEACK	0x0254
+#define CONTROL_PADCONF_D2D_MWRITE	0x0256
+#define CONTROL_PADCONF_D2D_SWRITE	0x0258
+#define CONTROL_PADCONF_D2D_MREAD	0x025A
+#define CONTROL_PADCONF_D2D_SREAD	0x025C
+#define CONTROL_PADCONF_D2D_MBUSFLAG	0x025E
+#define CONTROL_PADCONF_D2D_SBUSFLAG	0x0260
+#define CONTROL_PADCONF_SDRC_CKE0	0x0262
+#define CONTROL_PADCONF_SDRC_CKE1	0x0264
+
+#define MUX_VAL(OFFSET,VALUE)\
+	writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
+
+#define	CP(x)	(CONTROL_PADCONF_##x)
+
+#endif
diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h
new file mode 100644
index 0000000..02e36d7
--- /dev/null
+++ b/include/asm-arm/arch-omap3/omap3.h
@@ -0,0 +1,222 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAP3_H_
+#define _OMAP3_H_
+
+/* Stuff on L3 Interconnect */
+#define SMX_APE_BASE			0x68000000
+
+/* GPMC */
+#define OMAP34XX_GPMC_BASE		0x6E000000
+
+/* SMS */
+#define OMAP34XX_SMS_BASE		0x6C000000
+
+/* SDRC */
+#define OMAP34XX_SDRC_BASE		0x6D000000
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP34XX_CORE_L4_IO_BASE	0x48000000
+#define OMAP34XX_WAKEUP_L4_IO_BASE	0x48300000
+#define OMAP34XX_L4_PER			0x49000000
+#define OMAP34XX_L4_IO_BASE		OMAP34XX_CORE_L4_IO_BASE
+
+/* CONTROL */
+#define OMAP34XX_CTRL_BASE		(OMAP34XX_L4_IO_BASE + 0x2000)
+
+/* UART */
+#define OMAP34XX_UART1			(OMAP34XX_L4_IO_BASE + 0x6a000)
+#define OMAP34XX_UART2			(OMAP34XX_L4_IO_BASE + 0x6c000)
+#define OMAP34XX_UART3			(OMAP34XX_L4_PER + 0x20000)
+
+/* General Purpose Timers */
+#define OMAP34XX_GPT1			0x48318000
+#define OMAP34XX_GPT2			0x49032000
+#define OMAP34XX_GPT3			0x49034000
+#define OMAP34XX_GPT4			0x49036000
+#define OMAP34XX_GPT5			0x49038000
+#define OMAP34XX_GPT6			0x4903A000
+#define OMAP34XX_GPT7			0x4903C000
+#define OMAP34XX_GPT8			0x4903E000
+#define OMAP34XX_GPT9			0x49040000
+#define OMAP34XX_GPT10			0x48086000
+#define OMAP34XX_GPT11			0x48088000
+#define OMAP34XX_GPT12			0x48304000
+
+/* WatchDog Timers (1 secure, 3 GP) */
+#define WD1_BASE			0x4830C000
+#define WD2_BASE			0x48314000
+#define WD3_BASE			0x49030000
+
+/* 32KTIMER */
+#define SYNC_32KTIMER_BASE		0x48320000
+
+#ifndef __ASSEMBLY__
+
+typedef struct s32ktimer {
+	unsigned char res[0x10];
+	unsigned int s32k_cr;		/* 0x10 */
+} s32ktimer_t;
+
+#endif /* __ASSEMBLY__ */
+
+/* OMAP3 GPIO registers */
+#define OMAP34XX_GPIO1_BASE		0x48310000
+#define OMAP34XX_GPIO2_BASE		0x49050000
+#define OMAP34XX_GPIO3_BASE		0x49052000
+#define OMAP34XX_GPIO4_BASE		0x49054000
+#define OMAP34XX_GPIO5_BASE		0x49056000
+#define OMAP34XX_GPIO6_BASE		0x49058000
+
+#ifndef __ASSEMBLY__
+typedef struct gpio {
+	unsigned char res1[0x34];
+	unsigned int oe;		/* 0x34 */
+	unsigned int datain;		/* 0x38 */
+	unsigned char res2[0x54];
+	unsigned int cleardataout;	/* 0x90 */
+	unsigned int setdataout;	/* 0x94 */
+} gpio_t;
+#endif /* __ASSEMBLY__ */
+
+#define GPIO0				(0x1 << 0)
+#define GPIO1				(0x1 << 1)
+#define GPIO2				(0x1 << 2)
+#define GPIO3				(0x1 << 3)
+#define GPIO4				(0x1 << 4)
+#define GPIO5				(0x1 << 5)
+#define GPIO6				(0x1 << 6)
+#define GPIO7				(0x1 << 7)
+#define GPIO8				(0x1 << 8)
+#define GPIO9				(0x1 << 9)
+#define GPIO10				(0x1 << 10)
+#define GPIO11				(0x1 << 11)
+#define GPIO12				(0x1 << 12)
+#define GPIO13				(0x1 << 13)
+#define GPIO14				(0x1 << 14)
+#define GPIO15				(0x1 << 15)
+#define GPIO16				(0x1 << 16)
+#define GPIO17				(0x1 << 17)
+#define GPIO18				(0x1 << 18)
+#define GPIO19				(0x1 << 19)
+#define GPIO20				(0x1 << 20)
+#define GPIO21				(0x1 << 21)
+#define GPIO22				(0x1 << 22)
+#define GPIO23				(0x1 << 23)
+#define GPIO24				(0x1 << 24)
+#define GPIO25				(0x1 << 25)
+#define GPIO26				(0x1 << 26)
+#define GPIO27				(0x1 << 27)
+#define GPIO28				(0x1 << 28)
+#define GPIO29				(0x1 << 29)
+#define GPIO30				(0x1 << 30)
+#define GPIO31				(0x1 << 31)
+
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_OFFSET0			0x40000000
+#define SRAM_OFFSET1			0x00200000
+#define SRAM_OFFSET2			0x0000F800
+#define SRAM_VECT_CODE			(SRAM_OFFSET0 | SRAM_OFFSET1 | \
+					 SRAM_OFFSET2)
+
+#define LOW_LEVEL_SRAM_STACK		0x4020FFFC
+
+#define DEBUG_LED1			149	/* gpio */
+#define DEBUG_LED2			150	/* gpio */
+
+#define XDR_POP		5	/* package on package part */
+#define SDR_DISCRETE	4	/* 128M memory SDR module */
+#define DDR_STACKED	3	/* stacked part on 2422 */
+#define DDR_COMBO	2	/* combo part on cpu daughter card */
+#define DDR_DISCRETE	1	/* 2x16 parts on daughter card */
+
+#define DDR_100		100	/* type found on most mem d-boards */
+#define DDR_111		111	/* some combo parts */
+#define DDR_133		133	/* most combo, some mem d-boards */
+#define DDR_165		165	/* future parts */
+
+#define CPU_3430	0x3430
+
+/*
+ * 343x real hardware:
+ *  ES1     = rev 0
+ *
+ * 343x code defines:
+ * ES1     = 0+1 = 1
+ * ES1     = 1+1 = 1
+ */
+#define CPU_3430_ES1		1
+#define CPU_3430_ES2		2
+
+#define WIDTH_8BIT		0x0000
+#define WIDTH_16BIT		0x1000	/* bit pos for 16 bit in gpmc */
+
+/* SDP definitions according to FPGA Rev. Is this OK?? */
+#define SDP_3430_V1		0x1
+#define SDP_3430_V2		0x2
+
+/* EVM definitions */
+#define OMAP3EVM_V1		0x1
+#define OMAP3EVM_V2		0x2
+
+/* I2C power management companion definitions */
+#define PWRMGT_ADDR_ID1		0x48
+#define PWRMGT_ADDR_ID2		0x49
+#define PWRMGT_ADDR_ID3		0x4A
+#define PWRMGT_ADDR_ID4		0x4B
+
+/* I2C ID3 (slave3) register */
+#define LEDEN			0xEE
+
+#define LEDAON			(0x1 << 0)
+#define LEDBON			(0x1 << 1)
+#define LEDAPWM			(0x1 << 4)
+#define LEDBPWM			(0x1 << 5)
+
+/* I2C ID4 (slave4) register */
+#define VAUX2_DEV_GRP		0x76
+#define VAUX2_DEDICATED		0x79
+#define VAUX3_DEV_GRP		0x7A
+#define VAUX3_DEDICATED		0x7D
+#define VMMC1_DEV_GRP		0x82
+#define VMMC1_DEDICATED		0x85
+#define VPLL2_DEV_GRP		0x8E
+#define VPLL2_DEDICATED		0x91
+#define VDAC_DEV_GRP		0x96
+#define VDAC_DEDICATED		0x99
+
+#define DEV_GRP_P1		0x20
+#define DEV_GRP_ALL		0xE0
+
+#define VAUX2_VSEL_28		0x09
+#define VAUX3_VSEL_28		0x03
+#define VPLL2_VSEL_18		0x05
+#define VDAC_VSEL_18		0x03
+#define VMMC1_VSEL_30		0x02
+
+#endif
diff --git a/include/asm-arm/arch-omap3/omap_gpmc.h b/include/asm-arm/arch-omap3/omap_gpmc.h
new file mode 100644
index 0000000..bd22bce
--- /dev/null
+++ b/include/asm-arm/arch-omap3/omap_gpmc.h
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
+ * Rohit Choraria <rohitkc@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_OMAP_GPMC_H
+#define __ASM_ARCH_OMAP_GPMC_H
+
+#define GPMC_BUF_EMPTY	0
+#define GPMC_BUF_FULL	1
+
+#define ECCCLEAR	(0x1 << 8)
+#define ECCRESULTREG1	(0x1 << 0)
+#define ECCSIZE512BYTE	0xFF
+#define ECCSIZE1	(ECCSIZE512BYTE << 22)
+#define ECCSIZE0	(ECCSIZE512BYTE << 12)
+#define ECCSIZE0SEL	(0x000 << 0)
+
+/* Generic ECC Layouts */
+/* Large Page x8 NAND device Layout */
+#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+	.eccbytes = 12,\
+	.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
+		9, 10, 11, 12},\
+	.oobfree = {\
+		{.offset = 13,\
+		 .length = 51 } } \
+}
+#endif
+
+/* Large Page x16 NAND device Layout */
+#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+	.eccbytes = 12,\
+	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
+		10, 11, 12, 13},\
+	.oobfree = {\
+		{.offset = 14,\
+		 .length = 50 } } \
+}
+#endif
+
+/* Small Page x8 NAND device Layout */
+#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+	.eccbytes = 3,\
+	.eccpos = {1, 2, 3},\
+	.oobfree = {\
+		{.offset = 4,\
+		 .length = 12 } } \
+}
+#endif
+
+/* Small Page x16 NAND device Layout */
+#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+	.eccbytes = 3,\
+	.eccpos = {2, 3, 4},\
+	.oobfree = {\
+		{.offset = 5,\
+		 .length = 11 } } \
+}
+#endif
+
+#endif /* __ASM_ARCH_OMAP_GPMC_H */
diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h
new file mode 100644
index 0000000..ab3e168
--- /dev/null
+++ b/include/asm-arm/arch-omap3/sys_proto.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+  */
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+typedef struct {
+	u32 board_type_v1;
+	u32 board_type_v2;
+	u32 mtype;
+	char *board_string;
+	char *nand_string;
+} omap3_sysinfo;
+
+void prcm_init(void);
+void per_clocks_enable(void);
+
+void memif_init(void);
+void sdrc_init(void);
+void do_sdrc_init(u32, u32);
+void gpmc_init(void);
+
+void watchdog_init(void);
+void set_muxconf_regs(void);
+
+u32 get_cpu_rev(void);
+u32 get_mem_type(void);
+u32 get_sysboot_value(void);
+u32 is_gpmc_muxed(void);
+u32 get_gpmc0_type(void);
+u32 get_gpmc0_width(void);
+u32 get_board_type(void);
+void display_board_info(u32);
+u32 get_sdr_cs_size(u32);
+u32 get_sdr_cs_offset(u32);
+u32 is_running_in_sdram(void);
+u32 is_running_in_sram(void);
+u32 is_running_in_flash(void);
+u32 get_device_type(void);
+void l2cache_enable(void);
+void secureworld_exit(void);
+void setup_auxcr(void);
+void try_unlock_memory(void);
+u32 get_boot_type(void);
+void v7_flush_dcache_all(u32);
+void sr32(void *, u32, u32, u32);
+u32 wait_on_value(u32, u32, void *, u32);
+void sdelay(unsigned long);
+void make_cs1_contiguous(void);
+void omap_nand_switch_ecc(int);
+void power_init_r(void);
+
+#endif
diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h
deleted file mode 100644
index 85e144b..0000000
--- a/include/asm-arm/arch-pxa/mmc.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- *  linux/drivers/mmc/mmc_pxa.h
- *
- *  Author: Vladimir Shebordaev, Igor Oblakov
- *  Copyright:  MontaVista Software Inc.
- *
- *  $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-#ifndef __MMC_PXA_P_H__
-#define __MMC_PXA_P_H__
-
-/* PXA-250 MMC controller registers */
-
-/* MMC_STRPCL */
-#define MMC_STRPCL_STOP_CLK		(0x0001UL)
-#define MMC_STRPCL_START_CLK		(0x0002UL)
-
-/* MMC_STAT */
-#define MMC_STAT_END_CMD_RES		(0x0001UL << 13)
-#define MMC_STAT_PRG_DONE		(0x0001UL << 12)
-#define MMC_STAT_DATA_TRAN_DONE		(0x0001UL << 11)
-#define MMC_STAT_CLK_EN			(0x0001UL << 8)
-#define MMC_STAT_RECV_FIFO_FULL		(0x0001UL << 7)
-#define MMC_STAT_XMIT_FIFO_EMPTY	(0x0001UL << 6)
-#define MMC_STAT_RES_CRC_ERROR		(0x0001UL << 5)
-#define MMC_STAT_SPI_READ_ERROR_TOKEN   (0x0001UL << 4)
-#define MMC_STAT_CRC_READ_ERROR		(0x0001UL << 3)
-#define MMC_STAT_CRC_WRITE_ERROR	(0x0001UL << 2)
-#define MMC_STAT_TIME_OUT_RESPONSE	(0x0001UL << 1)
-#define MMC_STAT_READ_TIME_OUT		(0x0001UL)
-
-#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\
-	|MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\
-	|MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR)
-
-/* MMC_CLKRT */
-#define MMC_CLKRT_20MHZ			(0x0000UL)
-#define MMC_CLKRT_10MHZ			(0x0001UL)
-#define MMC_CLKRT_5MHZ			(0x0002UL)
-#define MMC_CLKRT_2_5MHZ		(0x0003UL)
-#define MMC_CLKRT_1_25MHZ		(0x0004UL)
-#define MMC_CLKRT_0_625MHZ		(0x0005UL)
-#define MMC_CLKRT_0_3125MHZ		(0x0006UL)
-
-/* MMC_SPI */
-#define MMC_SPI_DISABLE			(0x00UL)
-#define MMC_SPI_EN			(0x01UL)
-#define MMC_SPI_CS_EN			(0x01UL << 2)
-#define MMC_SPI_CS_ADDRESS		(0x01UL << 3)
-#define MMC_SPI_CRC_ON			(0x01UL << 1)
-
-/* MMC_CMDAT */
-#define MMC_CMDAT_SD_4DAT		(0x0001UL << 8)
-#define MMC_CMDAT_MMC_DMA_EN		(0x0001UL << 7)
-#define MMC_CMDAT_INIT			(0x0001UL << 6)
-#define MMC_CMDAT_BUSY			(0x0001UL << 5)
-#define MMC_CMDAT_BCR			(0x0003UL << 5)
-#define MMC_CMDAT_STREAM		(0x0001UL << 4)
-#define MMC_CMDAT_BLOCK			(0x0000UL << 4)
-#define MMC_CMDAT_WRITE			(0x0001UL << 3)
-#define MMC_CMDAT_READ			(0x0000UL << 3)
-#define MMC_CMDAT_DATA_EN		(0x0001UL << 2)
-#define MMC_CMDAT_R0			(0)
-#define MMC_CMDAT_R1			(0x0001UL)
-#define MMC_CMDAT_R2			(0x0002UL)
-#define MMC_CMDAT_R3			(0x0003UL)
-
-/* MMC_RESTO */
-#define MMC_RES_TO_MAX			(0x007fUL) /* [6:0] */
-
-/* MMC_RDTO */
-#define MMC_READ_TO_MAX			(0x0ffffUL) /* [15:0] */
-
-/* MMC_BLKLEN */
-#define MMC_BLK_LEN_MAX			(0x03ffUL) /* [9:0] */
-
-/* MMC_PRTBUF */
-#define MMC_PRTBUF_BUF_PART_FULL	(0x01UL)
-#define MMC_PRTBUF_BUF_FULL		(0x00UL    )
-
-/* MMC_I_MASK */
-#define MMC_I_MASK_TXFIFO_WR_REQ	(0x01UL << 6)
-#define MMC_I_MASK_RXFIFO_RD_REQ	(0x01UL << 5)
-#define MMC_I_MASK_CLK_IS_OFF		(0x01UL << 4)
-#define MMC_I_MASK_STOP_CMD		(0x01UL << 3)
-#define MMC_I_MASK_END_CMD_RES		(0x01UL << 2)
-#define MMC_I_MASK_PRG_DONE		(0x01UL << 1)
-#define MMC_I_MASK_DATA_TRAN_DONE       (0x01UL)
-#define MMC_I_MASK_ALL			(0x07fUL)
-
-
-/* MMC_I_REG */
-#define MMC_I_REG_TXFIFO_WR_REQ		(0x01UL << 6)
-#define MMC_I_REG_RXFIFO_RD_REQ		(0x01UL << 5)
-#define MMC_I_REG_CLK_IS_OFF		(0x01UL << 4)
-#define MMC_I_REG_STOP_CMD		(0x01UL << 3)
-#define MMC_I_REG_END_CMD_RES		(0x01UL << 2)
-#define MMC_I_REG_PRG_DONE		(0x01UL << 1)
-#define MMC_I_REG_DATA_TRAN_DONE	(0x01UL)
-#define MMC_I_REG_ALL			(0x007fUL)
-
-/* MMC_CMD */
-#define MMC_CMD_INDEX_MAX		(0x006fUL)  /* [5:0] */
-#define CMD(x)  (x)
-
-#define MMC_DEFAULT_RCA			1
-
-#define MMC_BLOCK_SIZE			512
-#define MMC_MAX_BLOCK_SIZE		512
-
-#define MMC_R1_IDLE_STATE		0x01
-#define MMC_R1_ERASE_STATE		0x02
-#define MMC_R1_ILLEGAL_CMD		0x04
-#define MMC_R1_COM_CRC_ERR		0x08
-#define MMC_R1_ERASE_SEQ_ERR		0x01
-#define MMC_R1_ADDR_ERR			0x02
-#define MMC_R1_PARAM_ERR		0x04
-
-#define MMC_R1B_WP_ERASE_SKIP		0x0002
-#define MMC_R1B_ERR			0x0004
-#define MMC_R1B_CC_ERR			0x0008
-#define MMC_R1B_CARD_ECC_ERR		0x0010
-#define MMC_R1B_WP_VIOLATION		0x0020
-#define MMC_R1B_ERASE_PARAM		0x0040
-#define MMC_R1B_OOR			0x0080
-#define MMC_R1B_IDLE_STATE		0x0100
-#define MMC_R1B_ERASE_RESET		0x0200
-#define MMC_R1B_ILLEGAL_CMD		0x0400
-#define MMC_R1B_COM_CRC_ERR		0x0800
-#define MMC_R1B_ERASE_SEQ_ERR		0x1000
-#define MMC_R1B_ADDR_ERR		0x2000
-#define MMC_R1B_PARAM_ERR		0x4000
-
-typedef struct mmc_cid
-{
-/* FIXME: BYTE_ORDER */
-   uchar year:4,
-   month:4;
-   uchar sn[3];
-   uchar fwrev:4,
-   hwrev:4;
-   uchar name[6];
-   uchar id[3];
-} mmc_cid_t;
-
-typedef struct mmc_csd
-{
-	uint8_t		csd_structure:2,
-			spec_ver:4,
-			rsvd1:2;
-	uint8_t		taac;
-	uint8_t		nsac;
-	uint8_t		tran_speed;
-	uint16_t	ccc:12,
-			read_bl_len:4;
-	uint64_t	read_bl_partial:1,
-			write_blk_misalign:1,
-			read_blk_misalign:1,
-			dsr_imp:1,
-			rsvd2:2,
-			c_size:12,
-			vdd_r_curr_min:3,
-			vdd_r_curr_max:3,
-			vdd_w_curr_min:3,
-			vdd_w_curr_max:3,
-			c_size_mult:3,
-			erase_blk_en:1,
-			sector_size:7,
-			wp_grp_size:7,
-			wp_grp_enable:1,
-			default_ecc:2,
-			r2w_factor:3,
-			write_bl_len:4,
-			write_bl_partial:1,
-			rsvd3:4,
-			content_prot_app:1;
-	uint8_t		file_format_grp:1,
-			copy:1,
-			perm_write_protect:1,
-			tmp_write_protect:1,
-			file_format:2,
-			ecc:2;
-} mmc_csd_t;
-
-#endif /* __MMC_PXA_P_H__ */
diff --git a/include/asm-arm/arch-lpc2292/mmc.h b/include/asm-arm/config.h
index e664a5f..049c44e 100644
--- a/include/asm-arm/arch-lpc2292/mmc.h
+++ b/include/asm-arm/config.h
@@ -1,6 +1,5 @@
 /*
- * A dummy header file for use with the LPC2292 port to keep the
- * compiler happy.
+ * Copyright 2009 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -9,14 +8,17 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
+ *
  */
-#ifndef _MMC_ARM_TDM_H_
-#define _MMC_ARM_TDM_H_
-#endif /* _MMC_ARM_TDM_H_ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
diff --git a/include/asm-arm/global_data.h b/include/asm-arm/global_data.h
index f419b42..5c56ce3 100644
--- a/include/asm-arm/global_data.h
+++ b/include/asm-arm/global_data.h
@@ -30,7 +30,7 @@
  * global variables during system initialization (until we have set
  * up the memory controller so that we can use RAM).
  *
- * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
  */
 
 typedef	struct	global_data {
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index f4ae307..fec3a7e 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -57,6 +57,11 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
 
 }
 
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
 /*
  * Generic virtual read/write.  Note that we don't support half-word
  * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
index ce6d25f..2c1e69b 100644
--- a/include/asm-arm/mach-types.h
+++ b/include/asm-arm/mach-types.h
@@ -1376,7 +1376,7 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_OLIP8                1378
 #define MACH_TYPE_GHI270HG             1379
 #define MACH_TYPE_DAVINCI_DM6467_EVM   1380
-#define MACH_TYPE_DAVINCI_DM350_EVM    1381
+#define MACH_TYPE_DAVINCI_DM355_EVM    1381
 #define MACH_TYPE_BLACKRIVER           1383
 #define MACH_TYPE_SANDGATEWP           1384
 #define MACH_TYPE_CDOTBWSG             1385
@@ -1806,7 +1806,7 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_PILZ_PMI5            1820
 #define MACH_TYPE_JADE                 1821
 #define MACH_TYPE_KS8695_SOFTPLC       1822
-#define MACH_TYPE_GPRISC4              1823
+#define MACH_TYPE_GPRISC3              1823
 #define MACH_TYPE_STAMP9260            1824
 #define MACH_TYPE_SMDK6430             1825
 #define MACH_TYPE_SMDKC100             1826
@@ -1857,6 +1857,139 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_IMX27IPCAM           1871
 #define MACH_TYPE_NEMOC                1872
 #define MACH_TYPE_GENEVA               1873
+#define MACH_TYPE_HTCPHAROS            1874
+#define MACH_TYPE_NEONC                1875
+#define MACH_TYPE_NAS7100              1876
+#define MACH_TYPE_TEUPHONE             1877
+#define MACH_TYPE_ANNAX_ETH2           1878
+#define MACH_TYPE_CSB733               1879
+#define MACH_TYPE_BK3                  1880
+#define MACH_TYPE_OMAP_EM32            1881
+#define MACH_TYPE_ET9261CP             1882
+#define MACH_TYPE_JASPERC              1883
+#define MACH_TYPE_ISSI_ARM9            1884
+#define MACH_TYPE_UED                  1885
+#define MACH_TYPE_ESIBLADE             1886
+#define MACH_TYPE_EYE02                1887
+#define MACH_TYPE_IMX27KBD             1888
+#define MACH_TYPE_SST61VC010_FPGA      1889
+#define MACH_TYPE_KIXVP435             1890
+#define MACH_TYPE_KIXNP435             1891
+#define MACH_TYPE_AFRICA               1892
+#define MACH_TYPE_NH233                1893
+#define MACH_TYPE_RD88F6183AP_GE       1894
+#define MACH_TYPE_BCM4760              1895
+#define MACH_TYPE_EDDY_V2              1896
+#define MACH_TYPE_REALVIEW_PBA8        1897
+#define MACH_TYPE_HID_A7               1898
+#define MACH_TYPE_HERO                 1899
+#define MACH_TYPE_OMAP_POSEIDON        1900
+#define MACH_TYPE_REALVIEW_PBX         1901
+#define MACH_TYPE_MICRO9S              1902
+#define MACH_TYPE_MAKO                 1903
+#define MACH_TYPE_XDAFLAME             1904
+#define MACH_TYPE_PHIDGET_SBC2         1905
+#define MACH_TYPE_LIMESTONE            1906
+#define MACH_TYPE_IPROBE_C32           1907
+#define MACH_TYPE_RUT100               1908
+#define MACH_TYPE_ASUSP535             1909
+#define MACH_TYPE_HTCRAPHAEL           1910
+#define MACH_TYPE_SYGDG1               1911
+#define MACH_TYPE_SYGDG2               1912
+#define MACH_TYPE_SEOUL                1913
+#define MACH_TYPE_SALERNO              1914
+#define MACH_TYPE_UCN_S3C64XX          1915
+#define MACH_TYPE_MSM7201A             1916
+#define MACH_TYPE_LPR1                 1917
+#define MACH_TYPE_ARMADILLO500FX       1918
+#define MACH_TYPE_G3EVM                1919
+#define MACH_TYPE_Z3_DM355             1920
+#define MACH_TYPE_W90P910EVB           1921
+#define MACH_TYPE_W90P920EVB           1922
+#define MACH_TYPE_W90P950EVB           1923
+#define MACH_TYPE_W90N960EVB           1924
+#define MACH_TYPE_CAMHD                1925
+#define MACH_TYPE_MVC100               1926
+#define MACH_TYPE_ELECTRUM_200         1927
+#define MACH_TYPE_HTCJADE              1928
+#define MACH_TYPE_MEMPHIS              1929
+#define MACH_TYPE_IMX27SBC             1930
+#define MACH_TYPE_LEXTAR               1931
+#define MACH_TYPE_MV88F6281GTW_GE      1932
+#define MACH_TYPE_NCP                  1933
+#define MACH_TYPE_Z32AN                1934
+#define MACH_TYPE_TMQ_CAPD             1935
+#define MACH_TYPE_OMAP3_WL             1936
+#define MACH_TYPE_CHUMBY               1937
+#define MACH_TYPE_ATSARM9              1938
+#define MACH_TYPE_DAVINCI_DM365_EVM    1939
+#define MACH_TYPE_BAHAMAS              1940
+#define MACH_TYPE_DAS                  1941
+#define MACH_TYPE_MINIDAS              1942
+#define MACH_TYPE_VK1000               1943
+#define MACH_TYPE_CENTRO               1944
+#define MACH_TYPE_CTERA_2BAY           1945
+#define MACH_TYPE_EDGECONNECT          1946
+#define MACH_TYPE_ND27000              1947
+#define MACH_TYPE_GEMALTO_COBRA        1948
+#define MACH_TYPE_INGELABS_COMET       1949
+#define MACH_TYPE_POLLUX_WIZ           1950
+#define MACH_TYPE_BLACKSTONE           1951
+#define MACH_TYPE_TOPAZ                1952
+#define MACH_TYPE_AIXLE                1953
+#define MACH_TYPE_MW998                1954
+#define MACH_TYPE_NOKIA_RX51           1955
+#define MACH_TYPE_VSC5605EV            1956
+#define MACH_TYPE_NT98700DK            1957
+#define MACH_TYPE_ICONTACT             1958
+#define MACH_TYPE_SWARCO_FRCPU         1959
+#define MACH_TYPE_SWARCO_SCPU          1960
+#define MACH_TYPE_BBOX_P16             1961
+#define MACH_TYPE_BSTD                 1962
+#define MACH_TYPE_SBC2440II            1963
+#define MACH_TYPE_PCM034               1964
+#define MACH_TYPE_NESO                 1965
+#define MACH_TYPE_WLNX_9G20            1966
+#define MACH_TYPE_OMAP_ZOOM2           1967
+#define MACH_TYPE_TOTEMNOVA            1968
+#define MACH_TYPE_C5000                1969
+#define MACH_TYPE_UNIPO_AT91SAM9263    1970
+#define MACH_TYPE_ETHERNUT5            1971
+#define MACH_TYPE_ARM11                1972
+#define MACH_TYPE_CPUAT9260            1973
+#define MACH_TYPE_CPUPXA255            1974
+#define MACH_TYPE_CPUIMX27             1975
+#define MACH_TYPE_CHEFLUX              1976
+#define MACH_TYPE_EB_CPUX9K2           1977
+#define MACH_TYPE_OPCOTEC              1978
+#define MACH_TYPE_YT                   1979
+#define MACH_TYPE_MOTOQ                1980
+#define MACH_TYPE_BSB1                 1981
+#define MACH_TYPE_ACS5K                1982
+#define MACH_TYPE_MILAN                1983
+#define MACH_TYPE_QUARTZV2             1984
+#define MACH_TYPE_RSVP                 1985
+#define MACH_TYPE_RMP200               1986
+#define MACH_TYPE_SNAPPER_9260         1987
+#define MACH_TYPE_DSM320               1988
+#define MACH_TYPE_ADSGCM               1989
+#define MACH_TYPE_ASE2_400             1990
+#define MACH_TYPE_PIZZA                1991
+#define MACH_TYPE_SPOT_NGPL            1992
+#define MACH_TYPE_ARMATA               1993
+#define MACH_TYPE_EXEDA                1994
+#define MACH_TYPE_MX31SF005            1995
+#define MACH_TYPE_F5D8231_4_V2         1996
+#define MACH_TYPE_Q2440                1997
+#define MACH_TYPE_QQ2440               1998
+#define MACH_TYPE_MINI2440             1999
+#define MACH_TYPE_COLIBRI300           2000
+#define MACH_TYPE_JADES                2001
+#define MACH_TYPE_SPARK                2002
+#define MACH_TYPE_BENZINA              2003
+#define MACH_TYPE_BLAZE                2004
+#define MACH_TYPE_LINKSTATION_LS_HGL   2005
+#define MACH_TYPE_HTCVENUS             2006
 
 #ifdef CONFIG_ARCH_EBSA110
 # ifdef machine_arch_type
@@ -18226,14 +18359,14 @@ extern unsigned int __machine_arch_type;
 # define machine_is_davinci_dm6467_evm()	(0)
 #endif
 
-#ifdef CONFIG_MACH_DAVINCI_DM350_EVM
+#ifdef CONFIG_MACH_DAVINCI_DM355_EVM
 # ifdef machine_arch_type
 #  undef machine_arch_type
 #  define machine_arch_type	__machine_arch_type
 # else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_DM350_EVM
+#  define machine_arch_type	MACH_TYPE_DAVINCI_DM355_EVM
 # endif
-# define machine_is_davinci_dm355_evm()	(machine_arch_type == MACH_TYPE_DAVINCI_DM350_EVM)
+# define machine_is_davinci_dm355_evm()	(machine_arch_type == MACH_TYPE_DAVINCI_DM355_EVM)
 #else
 # define machine_is_davinci_dm355_evm()	(0)
 #endif
@@ -22925,9 +23058,9 @@ extern unsigned int __machine_arch_type;
 # else
 #  define machine_arch_type	MACH_TYPE_AT572D940HFEB
 # endif
-# define machine_is_at572d940hfeb()	(machine_arch_type == MACH_TYPE_AT572D940HFEB)
+# define machine_is_at572d940hfek()	(machine_arch_type == MACH_TYPE_AT572D940HFEB)
 #else
-# define machine_is_at572d940hfeb()	(0)
+# define machine_is_at572d940hfek()	(0)
 #endif
 
 #ifdef CONFIG_MACH_CYBOOK3
@@ -23386,14 +23519,14 @@ extern unsigned int __machine_arch_type;
 # define machine_is_ks8695_softplc()	(0)
 #endif
 
-#ifdef CONFIG_MACH_GPRISC4
+#ifdef CONFIG_MACH_GPRISC3
 # ifdef machine_arch_type
 #  undef machine_arch_type
 #  define machine_arch_type	__machine_arch_type
 # else
-#  define machine_arch_type	MACH_TYPE_GPRISC4
+#  define machine_arch_type	MACH_TYPE_GPRISC3
 # endif
-# define machine_is_gprisc3()	(machine_arch_type == MACH_TYPE_GPRISC4)
+# define machine_is_gprisc3()	(machine_arch_type == MACH_TYPE_GPRISC3)
 #else
 # define machine_is_gprisc3()	(0)
 #endif
@@ -23981,9 +24114,9 @@ extern unsigned int __machine_arch_type;
 # else
 #  define machine_arch_type	MACH_TYPE_NEMOC
 # endif
-# define machine_is_nenoc()	(machine_arch_type == MACH_TYPE_NEMOC)
+# define machine_is_nemoc()	(machine_arch_type == MACH_TYPE_NEMOC)
 #else
-# define machine_is_nenoc()	(0)
+# define machine_is_nemoc()	(0)
 #endif
 
 #ifdef CONFIG_MACH_GENEVA
@@ -23998,6 +24131,1602 @@ extern unsigned int __machine_arch_type;
 # define machine_is_geneva()	(0)
 #endif
 
+#ifdef CONFIG_MACH_HTCPHAROS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTCPHAROS
+# endif
+# define machine_is_htcpharos()	(machine_arch_type == MACH_TYPE_HTCPHAROS)
+#else
+# define machine_is_htcpharos()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NEONC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NEONC
+# endif
+# define machine_is_neonc()	(machine_arch_type == MACH_TYPE_NEONC)
+#else
+# define machine_is_neonc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NAS7100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NAS7100
+# endif
+# define machine_is_nas7100()	(machine_arch_type == MACH_TYPE_NAS7100)
+#else
+# define machine_is_nas7100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TEUPHONE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TEUPHONE
+# endif
+# define machine_is_teuphone()	(machine_arch_type == MACH_TYPE_TEUPHONE)
+#else
+# define machine_is_teuphone()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ANNAX_ETH2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ANNAX_ETH2
+# endif
+# define machine_is_annax_eth2()	(machine_arch_type == MACH_TYPE_ANNAX_ETH2)
+#else
+# define machine_is_annax_eth2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CSB733
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSB733
+# endif
+# define machine_is_csb733()	(machine_arch_type == MACH_TYPE_CSB733)
+#else
+# define machine_is_csb733()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BK3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BK3
+# endif
+# define machine_is_bk3()	(machine_arch_type == MACH_TYPE_BK3)
+#else
+# define machine_is_bk3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_EM32
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_EM32
+# endif
+# define machine_is_omap_em32()	(machine_arch_type == MACH_TYPE_OMAP_EM32)
+#else
+# define machine_is_omap_em32()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ET9261CP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ET9261CP
+# endif
+# define machine_is_et9261cp()	(machine_arch_type == MACH_TYPE_ET9261CP)
+#else
+# define machine_is_et9261cp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_JASPERC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_JASPERC
+# endif
+# define machine_is_jasperc()	(machine_arch_type == MACH_TYPE_JASPERC)
+#else
+# define machine_is_jasperc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ISSI_ARM9
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ISSI_ARM9
+# endif
+# define machine_is_issi_arm9()	(machine_arch_type == MACH_TYPE_ISSI_ARM9)
+#else
+# define machine_is_issi_arm9()	(0)
+#endif
+
+#ifdef CONFIG_MACH_UED
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_UED
+# endif
+# define machine_is_ued()	(machine_arch_type == MACH_TYPE_UED)
+#else
+# define machine_is_ued()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ESIBLADE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESIBLADE
+# endif
+# define machine_is_esiblade()	(machine_arch_type == MACH_TYPE_ESIBLADE)
+#else
+# define machine_is_esiblade()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EYE02
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EYE02
+# endif
+# define machine_is_eye02()	(machine_arch_type == MACH_TYPE_EYE02)
+#else
+# define machine_is_eye02()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IMX27KBD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IMX27KBD
+# endif
+# define machine_is_imx27kbd()	(machine_arch_type == MACH_TYPE_IMX27KBD)
+#else
+# define machine_is_imx27kbd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SST61VC010_FPGA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SST61VC010_FPGA
+# endif
+# define machine_is_sst61vc010_fpga()	(machine_arch_type == MACH_TYPE_SST61VC010_FPGA)
+#else
+# define machine_is_sst61vc010_fpga()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KIXVP435
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KIXVP435
+# endif
+# define machine_is_kixvp435()	(machine_arch_type == MACH_TYPE_KIXVP435)
+#else
+# define machine_is_kixvp435()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KIXNP435
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KIXNP435
+# endif
+# define machine_is_kixnp435()	(machine_arch_type == MACH_TYPE_KIXNP435)
+#else
+# define machine_is_kixnp435()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AFRICA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AFRICA
+# endif
+# define machine_is_africa()	(machine_arch_type == MACH_TYPE_AFRICA)
+#else
+# define machine_is_africa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NH233
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NH233
+# endif
+# define machine_is_nh233()	(machine_arch_type == MACH_TYPE_NH233)
+#else
+# define machine_is_nh233()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RD88F6183AP_GE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RD88F6183AP_GE
+# endif
+# define machine_is_rd88f6183ap_ge()	(machine_arch_type == MACH_TYPE_RD88F6183AP_GE)
+#else
+# define machine_is_rd88f6183ap_ge()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BCM4760
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BCM4760
+# endif
+# define machine_is_bcm4760()	(machine_arch_type == MACH_TYPE_BCM4760)
+#else
+# define machine_is_bcm4760()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDDY_V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDDY_V2
+# endif
+# define machine_is_eddy_v2()	(machine_arch_type == MACH_TYPE_EDDY_V2)
+#else
+# define machine_is_eddy_v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_REALVIEW_PBA8
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_REALVIEW_PBA8
+# endif
+# define machine_is_realview_pba8()	(machine_arch_type == MACH_TYPE_REALVIEW_PBA8)
+#else
+# define machine_is_realview_pba8()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HID_A7
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HID_A7
+# endif
+# define machine_is_hid_a7()	(machine_arch_type == MACH_TYPE_HID_A7)
+#else
+# define machine_is_hid_a7()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HERO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HERO
+# endif
+# define machine_is_hero()	(machine_arch_type == MACH_TYPE_HERO)
+#else
+# define machine_is_hero()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_POSEIDON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_POSEIDON
+# endif
+# define machine_is_omap_poseidon()	(machine_arch_type == MACH_TYPE_OMAP_POSEIDON)
+#else
+# define machine_is_omap_poseidon()	(0)
+#endif
+
+#ifdef CONFIG_MACH_REALVIEW_PBX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_REALVIEW_PBX
+# endif
+# define machine_is_realview_pbx()	(machine_arch_type == MACH_TYPE_REALVIEW_PBX)
+#else
+# define machine_is_realview_pbx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MICRO9S
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MICRO9S
+# endif
+# define machine_is_micro9s()	(machine_arch_type == MACH_TYPE_MICRO9S)
+#else
+# define machine_is_micro9s()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MAKO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MAKO
+# endif
+# define machine_is_mako()	(machine_arch_type == MACH_TYPE_MAKO)
+#else
+# define machine_is_mako()	(0)
+#endif
+
+#ifdef CONFIG_MACH_XDAFLAME
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_XDAFLAME
+# endif
+# define machine_is_xdaflame()	(machine_arch_type == MACH_TYPE_XDAFLAME)
+#else
+# define machine_is_xdaflame()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PHIDGET_SBC2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PHIDGET_SBC2
+# endif
+# define machine_is_phidget_sbc2()	(machine_arch_type == MACH_TYPE_PHIDGET_SBC2)
+#else
+# define machine_is_phidget_sbc2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LIMESTONE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LIMESTONE
+# endif
+# define machine_is_limestone()	(machine_arch_type == MACH_TYPE_LIMESTONE)
+#else
+# define machine_is_limestone()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IPROBE_C32
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IPROBE_C32
+# endif
+# define machine_is_iprobe_c32()	(machine_arch_type == MACH_TYPE_IPROBE_C32)
+#else
+# define machine_is_iprobe_c32()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RUT100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RUT100
+# endif
+# define machine_is_rut100()	(machine_arch_type == MACH_TYPE_RUT100)
+#else
+# define machine_is_rut100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ASUSP535
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ASUSP535
+# endif
+# define machine_is_asusp535()	(machine_arch_type == MACH_TYPE_ASUSP535)
+#else
+# define machine_is_asusp535()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HTCRAPHAEL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTCRAPHAEL
+# endif
+# define machine_is_htcraphael()	(machine_arch_type == MACH_TYPE_HTCRAPHAEL)
+#else
+# define machine_is_htcraphael()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SYGDG1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SYGDG1
+# endif
+# define machine_is_sygdg1()	(machine_arch_type == MACH_TYPE_SYGDG1)
+#else
+# define machine_is_sygdg1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SYGDG2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SYGDG2
+# endif
+# define machine_is_sygdg2()	(machine_arch_type == MACH_TYPE_SYGDG2)
+#else
+# define machine_is_sygdg2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SEOUL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SEOUL
+# endif
+# define machine_is_seoul()	(machine_arch_type == MACH_TYPE_SEOUL)
+#else
+# define machine_is_seoul()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SALERNO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SALERNO
+# endif
+# define machine_is_salerno()	(machine_arch_type == MACH_TYPE_SALERNO)
+#else
+# define machine_is_salerno()	(0)
+#endif
+
+#ifdef CONFIG_MACH_UCN_S3C64XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_UCN_S3C64XX
+# endif
+# define machine_is_ucn_s3c64xx()	(machine_arch_type == MACH_TYPE_UCN_S3C64XX)
+#else
+# define machine_is_ucn_s3c64xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM7201A
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM7201A
+# endif
+# define machine_is_msm7201a()	(machine_arch_type == MACH_TYPE_MSM7201A)
+#else
+# define machine_is_msm7201a()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LPR1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LPR1
+# endif
+# define machine_is_lpr1()	(machine_arch_type == MACH_TYPE_LPR1)
+#else
+# define machine_is_lpr1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARMADILLO500FX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARMADILLO500FX
+# endif
+# define machine_is_armadillo500fx()	(machine_arch_type == MACH_TYPE_ARMADILLO500FX)
+#else
+# define machine_is_armadillo500fx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_G3EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_G3EVM
+# endif
+# define machine_is_g3evm()	(machine_arch_type == MACH_TYPE_G3EVM)
+#else
+# define machine_is_g3evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_Z3_DM355
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_Z3_DM355
+# endif
+# define machine_is_z3_dm355()	(machine_arch_type == MACH_TYPE_Z3_DM355)
+#else
+# define machine_is_z3_dm355()	(0)
+#endif
+
+#ifdef CONFIG_MACH_W90P910EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_W90P910EVB
+# endif
+# define machine_is_w90p910evb()	(machine_arch_type == MACH_TYPE_W90P910EVB)
+#else
+# define machine_is_w90p910evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_W90P920EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_W90P920EVB
+# endif
+# define machine_is_w90p920evb()	(machine_arch_type == MACH_TYPE_W90P920EVB)
+#else
+# define machine_is_w90p920evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_W90P950EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_W90P950EVB
+# endif
+# define machine_is_w90p950evb()	(machine_arch_type == MACH_TYPE_W90P950EVB)
+#else
+# define machine_is_w90p950evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_W90N960EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_W90N960EVB
+# endif
+# define machine_is_w90n960evb()	(machine_arch_type == MACH_TYPE_W90N960EVB)
+#else
+# define machine_is_w90n960evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CAMHD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CAMHD
+# endif
+# define machine_is_camhd()	(machine_arch_type == MACH_TYPE_CAMHD)
+#else
+# define machine_is_camhd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MVC100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MVC100
+# endif
+# define machine_is_mvc100()	(machine_arch_type == MACH_TYPE_MVC100)
+#else
+# define machine_is_mvc100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ELECTRUM_200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ELECTRUM_200
+# endif
+# define machine_is_electrum_200()	(machine_arch_type == MACH_TYPE_ELECTRUM_200)
+#else
+# define machine_is_electrum_200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HTCJADE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTCJADE
+# endif
+# define machine_is_htcjade()	(machine_arch_type == MACH_TYPE_HTCJADE)
+#else
+# define machine_is_htcjade()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MEMPHIS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MEMPHIS
+# endif
+# define machine_is_memphis()	(machine_arch_type == MACH_TYPE_MEMPHIS)
+#else
+# define machine_is_memphis()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IMX27SBC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IMX27SBC
+# endif
+# define machine_is_imx27sbc()	(machine_arch_type == MACH_TYPE_IMX27SBC)
+#else
+# define machine_is_imx27sbc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LEXTAR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LEXTAR
+# endif
+# define machine_is_lextar()	(machine_arch_type == MACH_TYPE_LEXTAR)
+#else
+# define machine_is_lextar()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MV88F6281GTW_GE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MV88F6281GTW_GE
+# endif
+# define machine_is_mv88f6281gtw_ge()	(machine_arch_type == MACH_TYPE_MV88F6281GTW_GE)
+#else
+# define machine_is_mv88f6281gtw_ge()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NCP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NCP
+# endif
+# define machine_is_ncp()	(machine_arch_type == MACH_TYPE_NCP)
+#else
+# define machine_is_ncp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_Z32AN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_Z32AN
+# endif
+# define machine_is_z32an_series()	(machine_arch_type == MACH_TYPE_Z32AN)
+#else
+# define machine_is_z32an_series()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TMQ_CAPD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TMQ_CAPD
+# endif
+# define machine_is_tmq_capd()	(machine_arch_type == MACH_TYPE_TMQ_CAPD)
+#else
+# define machine_is_tmq_capd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_WL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_WL
+# endif
+# define machine_is_omap3_wl()	(machine_arch_type == MACH_TYPE_OMAP3_WL)
+#else
+# define machine_is_omap3_wl()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CHUMBY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CHUMBY
+# endif
+# define machine_is_chumby()	(machine_arch_type == MACH_TYPE_CHUMBY)
+#else
+# define machine_is_chumby()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ATSARM9
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ATSARM9
+# endif
+# define machine_is_atsarm9()	(machine_arch_type == MACH_TYPE_ATSARM9)
+#else
+# define machine_is_atsarm9()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_DM365_EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAVINCI_DM365_EVM
+# endif
+# define machine_is_davinci_dm365_evm()	(machine_arch_type == MACH_TYPE_DAVINCI_DM365_EVM)
+#else
+# define machine_is_davinci_dm365_evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BAHAMAS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BAHAMAS
+# endif
+# define machine_is_bahamas()	(machine_arch_type == MACH_TYPE_BAHAMAS)
+#else
+# define machine_is_bahamas()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DAS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAS
+# endif
+# define machine_is_das()	(machine_arch_type == MACH_TYPE_DAS)
+#else
+# define machine_is_das()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MINIDAS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MINIDAS
+# endif
+# define machine_is_minidas()	(machine_arch_type == MACH_TYPE_MINIDAS)
+#else
+# define machine_is_minidas()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VK1000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VK1000
+# endif
+# define machine_is_vk1000()	(machine_arch_type == MACH_TYPE_VK1000)
+#else
+# define machine_is_vk1000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CENTRO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CENTRO
+# endif
+# define machine_is_centro()	(machine_arch_type == MACH_TYPE_CENTRO)
+#else
+# define machine_is_centro()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CTERA_2BAY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CTERA_2BAY
+# endif
+# define machine_is_ctera_2bay()	(machine_arch_type == MACH_TYPE_CTERA_2BAY)
+#else
+# define machine_is_ctera_2bay()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDGECONNECT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDGECONNECT
+# endif
+# define machine_is_edgeconnect()	(machine_arch_type == MACH_TYPE_EDGECONNECT)
+#else
+# define machine_is_edgeconnect()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ND27000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ND27000
+# endif
+# define machine_is_nd27000()	(machine_arch_type == MACH_TYPE_ND27000)
+#else
+# define machine_is_nd27000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GEMALTO_COBRA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GEMALTO_COBRA
+# endif
+# define machine_is_cobra()	(machine_arch_type == MACH_TYPE_GEMALTO_COBRA)
+#else
+# define machine_is_cobra()	(0)
+#endif
+
+#ifdef CONFIG_MACH_INGELABS_COMET
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_INGELABS_COMET
+# endif
+# define machine_is_ingelabs_comet()	(machine_arch_type == MACH_TYPE_INGELABS_COMET)
+#else
+# define machine_is_ingelabs_comet()	(0)
+#endif
+
+#ifdef CONFIG_MACH_POLLUX_WIZ
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_POLLUX_WIZ
+# endif
+# define machine_is_pollux_wiz()	(machine_arch_type == MACH_TYPE_POLLUX_WIZ)
+#else
+# define machine_is_pollux_wiz()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BLACKSTONE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BLACKSTONE
+# endif
+# define machine_is_blackstone()	(machine_arch_type == MACH_TYPE_BLACKSTONE)
+#else
+# define machine_is_blackstone()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TOPAZ
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TOPAZ
+# endif
+# define machine_is_topaz()	(machine_arch_type == MACH_TYPE_TOPAZ)
+#else
+# define machine_is_topaz()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AIXLE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AIXLE
+# endif
+# define machine_is_aixle()	(machine_arch_type == MACH_TYPE_AIXLE)
+#else
+# define machine_is_aixle()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MW998
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MW998
+# endif
+# define machine_is_mw998()	(machine_arch_type == MACH_TYPE_MW998)
+#else
+# define machine_is_mw998()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NOKIA_RX51
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NOKIA_RX51
+# endif
+# define machine_is_nokia_rx51()	(machine_arch_type == MACH_TYPE_NOKIA_RX51)
+#else
+# define machine_is_nokia_rx51()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VSC5605EV
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VSC5605EV
+# endif
+# define machine_is_vsc5605ev()	(machine_arch_type == MACH_TYPE_VSC5605EV)
+#else
+# define machine_is_vsc5605ev()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NT98700DK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NT98700DK
+# endif
+# define machine_is_nt98700dk()	(machine_arch_type == MACH_TYPE_NT98700DK)
+#else
+# define machine_is_nt98700dk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ICONTACT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ICONTACT
+# endif
+# define machine_is_icontact()	(machine_arch_type == MACH_TYPE_ICONTACT)
+#else
+# define machine_is_icontact()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SWARCO_FRCPU
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SWARCO_FRCPU
+# endif
+# define machine_is_swarco_frcpu()	(machine_arch_type == MACH_TYPE_SWARCO_FRCPU)
+#else
+# define machine_is_swarco_frcpu()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SWARCO_SCPU
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SWARCO_SCPU
+# endif
+# define machine_is_swarco_scpu()	(machine_arch_type == MACH_TYPE_SWARCO_SCPU)
+#else
+# define machine_is_swarco_scpu()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BBOX_P16
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BBOX_P16
+# endif
+# define machine_is_bbox_p16()	(machine_arch_type == MACH_TYPE_BBOX_P16)
+#else
+# define machine_is_bbox_p16()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BSTD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BSTD
+# endif
+# define machine_is_bstd()	(machine_arch_type == MACH_TYPE_BSTD)
+#else
+# define machine_is_bstd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SBC2440II
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SBC2440II
+# endif
+# define machine_is_sbc2440ii()	(machine_arch_type == MACH_TYPE_SBC2440II)
+#else
+# define machine_is_sbc2440ii()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCM034
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCM034
+# endif
+# define machine_is_pcm034()	(machine_arch_type == MACH_TYPE_PCM034)
+#else
+# define machine_is_pcm034()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NESO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NESO
+# endif
+# define machine_is_neso()	(machine_arch_type == MACH_TYPE_NESO)
+#else
+# define machine_is_neso()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WLNX_9G20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WLNX_9G20
+# endif
+# define machine_is_wlnx_9g20()	(machine_arch_type == MACH_TYPE_WLNX_9G20)
+#else
+# define machine_is_wlnx_9g20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_ZOOM2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_ZOOM2
+# endif
+# define machine_is_omap_zoom2()	(machine_arch_type == MACH_TYPE_OMAP_ZOOM2)
+#else
+# define machine_is_omap_zoom2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TOTEMNOVA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TOTEMNOVA
+# endif
+# define machine_is_totemnova()	(machine_arch_type == MACH_TYPE_TOTEMNOVA)
+#else
+# define machine_is_totemnova()	(0)
+#endif
+
+#ifdef CONFIG_MACH_C5000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_C5000
+# endif
+# define machine_is_c5000()	(machine_arch_type == MACH_TYPE_C5000)
+#else
+# define machine_is_c5000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_UNIPO_AT91SAM9263
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_UNIPO_AT91SAM9263
+# endif
+# define machine_is_unipo_at91sam9263()	(machine_arch_type == MACH_TYPE_UNIPO_AT91SAM9263)
+#else
+# define machine_is_unipo_at91sam9263()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ETHERNUT5
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ETHERNUT5
+# endif
+# define machine_is_ethernut5()	(machine_arch_type == MACH_TYPE_ETHERNUT5)
+#else
+# define machine_is_ethernut5()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARM11
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARM11
+# endif
+# define machine_is_arm11()	(machine_arch_type == MACH_TYPE_ARM11)
+#else
+# define machine_is_arm11()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CPUAT9260
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CPUAT9260
+# endif
+# define machine_is_cpuat9260()	(machine_arch_type == MACH_TYPE_CPUAT9260)
+#else
+# define machine_is_cpuat9260()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CPUPXA255
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CPUPXA255
+# endif
+# define machine_is_cpupxa255()	(machine_arch_type == MACH_TYPE_CPUPXA255)
+#else
+# define machine_is_cpupxa255()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CPUIMX27
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CPUIMX27
+# endif
+# define machine_is_cpuimx27()	(machine_arch_type == MACH_TYPE_CPUIMX27)
+#else
+# define machine_is_cpuimx27()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CHEFLUX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CHEFLUX
+# endif
+# define machine_is_cheflux()	(machine_arch_type == MACH_TYPE_CHEFLUX)
+#else
+# define machine_is_cheflux()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EB_CPUX9K2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EB_CPUX9K2
+# endif
+# define machine_is_eb_cpux9k2()	(machine_arch_type == MACH_TYPE_EB_CPUX9K2)
+#else
+# define machine_is_eb_cpux9k2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OPCOTEC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OPCOTEC
+# endif
+# define machine_is_opcotec()	(machine_arch_type == MACH_TYPE_OPCOTEC)
+#else
+# define machine_is_opcotec()	(0)
+#endif
+
+#ifdef CONFIG_MACH_YT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_YT
+# endif
+# define machine_is_yt()	(machine_arch_type == MACH_TYPE_YT)
+#else
+# define machine_is_yt()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MOTOQ
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MOTOQ
+# endif
+# define machine_is_motoq()	(machine_arch_type == MACH_TYPE_MOTOQ)
+#else
+# define machine_is_motoq()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BSB1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BSB1
+# endif
+# define machine_is_bsb1()	(machine_arch_type == MACH_TYPE_BSB1)
+#else
+# define machine_is_bsb1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ACS5K
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACS5K
+# endif
+# define machine_is_acs5k()	(machine_arch_type == MACH_TYPE_ACS5K)
+#else
+# define machine_is_acs5k()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MILAN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MILAN
+# endif
+# define machine_is_milan()	(machine_arch_type == MACH_TYPE_MILAN)
+#else
+# define machine_is_milan()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QUARTZV2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QUARTZV2
+# endif
+# define machine_is_quartzv2()	(machine_arch_type == MACH_TYPE_QUARTZV2)
+#else
+# define machine_is_quartzv2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RSVP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RSVP
+# endif
+# define machine_is_rsvp()	(machine_arch_type == MACH_TYPE_RSVP)
+#else
+# define machine_is_rsvp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RMP200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RMP200
+# endif
+# define machine_is_rmp200()	(machine_arch_type == MACH_TYPE_RMP200)
+#else
+# define machine_is_rmp200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SNAPPER_9260
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SNAPPER_9260
+# endif
+# define machine_is_snapper_9260()	(machine_arch_type == MACH_TYPE_SNAPPER_9260)
+#else
+# define machine_is_snapper_9260()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DSM320
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DSM320
+# endif
+# define machine_is_dsm320()	(machine_arch_type == MACH_TYPE_DSM320)
+#else
+# define machine_is_dsm320()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ADSGCM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADSGCM
+# endif
+# define machine_is_adsgcm()	(machine_arch_type == MACH_TYPE_ADSGCM)
+#else
+# define machine_is_adsgcm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ASE2_400
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ASE2_400
+# endif
+# define machine_is_ase2_400()	(machine_arch_type == MACH_TYPE_ASE2_400)
+#else
+# define machine_is_ase2_400()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PIZZA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PIZZA
+# endif
+# define machine_is_pizza()	(machine_arch_type == MACH_TYPE_PIZZA)
+#else
+# define machine_is_pizza()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPOT_NGPL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPOT_NGPL
+# endif
+# define machine_is_spot_ngpl()	(machine_arch_type == MACH_TYPE_SPOT_NGPL)
+#else
+# define machine_is_spot_ngpl()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARMATA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARMATA
+# endif
+# define machine_is_armata()	(machine_arch_type == MACH_TYPE_ARMATA)
+#else
+# define machine_is_armata()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EXEDA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EXEDA
+# endif
+# define machine_is_exeda()	(machine_arch_type == MACH_TYPE_EXEDA)
+#else
+# define machine_is_exeda()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX31SF005
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX31SF005
+# endif
+# define machine_is_mx31sf005()	(machine_arch_type == MACH_TYPE_MX31SF005)
+#else
+# define machine_is_mx31sf005()	(0)
+#endif
+
+#ifdef CONFIG_MACH_F5D8231_4_V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_F5D8231_4_V2
+# endif
+# define machine_is_f5d8231_4_v2()	(machine_arch_type == MACH_TYPE_F5D8231_4_V2)
+#else
+# define machine_is_f5d8231_4_v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_Q2440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_Q2440
+# endif
+# define machine_is_q2440()	(machine_arch_type == MACH_TYPE_Q2440)
+#else
+# define machine_is_q2440()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QQ2440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QQ2440
+# endif
+# define machine_is_qq2440()	(machine_arch_type == MACH_TYPE_QQ2440)
+#else
+# define machine_is_qq2440()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MINI2440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MINI2440
+# endif
+# define machine_is_mini2440()	(machine_arch_type == MACH_TYPE_MINI2440)
+#else
+# define machine_is_mini2440()	(0)
+#endif
+
+#ifdef CONFIG_MACH_COLIBRI300
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_COLIBRI300
+# endif
+# define machine_is_colibri300()	(machine_arch_type == MACH_TYPE_COLIBRI300)
+#else
+# define machine_is_colibri300()	(0)
+#endif
+
+#ifdef CONFIG_MACH_JADES
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_JADES
+# endif
+# define machine_is_jades()	(machine_arch_type == MACH_TYPE_JADES)
+#else
+# define machine_is_jades()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPARK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPARK
+# endif
+# define machine_is_spark()	(machine_arch_type == MACH_TYPE_SPARK)
+#else
+# define machine_is_spark()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BENZINA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BENZINA
+# endif
+# define machine_is_benzina()	(machine_arch_type == MACH_TYPE_BENZINA)
+#else
+# define machine_is_benzina()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BLAZE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BLAZE
+# endif
+# define machine_is_blaze()	(machine_arch_type == MACH_TYPE_BLAZE)
+#else
+# define machine_is_blaze()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LINKSTATION_LS_HGL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LINKSTATION_LS_HGL
+# endif
+# define machine_is_linkstation_ls_hgl()	(machine_arch_type == MACH_TYPE_LINKSTATION_LS_HGL)
+#else
+# define machine_is_linkstation_ls_hgl()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HTCVENUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTCVENUS
+# endif
+# define machine_is_htcvenus()	(machine_arch_type == MACH_TYPE_HTCVENUS)
+#else
+# define machine_is_htcvenus()	(0)
+#endif
+
 /*
  * These have not yet been registered
  */
diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h
index e9a4fe4..d83e93b 100644
--- a/include/asm-avr32/arch-at32ap700x/clk.h
+++ b/include/asm-avr32/arch-at32ap700x/clk.h
@@ -23,28 +23,31 @@
 #define __ASM_AVR32_ARCH_CLK_H__
 
 #include <asm/arch/chip-features.h>
+#include <asm/arch/portmux.h>
 
 #ifdef CONFIG_PLL
-#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
+#define PLL0_RATE	((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV)	\
+				* CONFIG_SYS_PLL0_MUL)
+#define MAIN_CLK_RATE	PLL0_RATE
 #else
-#define MAIN_CLK_RATE (CFG_OSC0_HZ)
+#define MAIN_CLK_RATE	(CONFIG_SYS_OSC0_HZ)
 #endif
 
 static inline unsigned long get_cpu_clk_rate(void)
 {
-	return MAIN_CLK_RATE >> CFG_CLKDIV_CPU;
+	return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_CPU;
 }
 static inline unsigned long get_hsb_clk_rate(void)
 {
-	return MAIN_CLK_RATE >> CFG_CLKDIV_HSB;
+	return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB;
 }
 static inline unsigned long get_pba_clk_rate(void)
 {
-	return MAIN_CLK_RATE >> CFG_CLKDIV_PBA;
+	return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBA;
 }
 static inline unsigned long get_pbb_clk_rate(void)
 {
-	return MAIN_CLK_RATE >> CFG_CLKDIV_PBB;
+	return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBB;
 }
 
 /* Accessors for specific devices. More will be added as needed. */
@@ -82,9 +85,101 @@ static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
 #endif
 
 extern void clk_init(void);
-extern void gclk_init(void) __attribute__((weak));
 
 /* Board code may need the SDRAM base clock as a compile-time constant */
-#define SDRAMC_BUS_HZ	(MAIN_CLK_RATE >> CFG_CLKDIV_HSB)
+#define SDRAMC_BUS_HZ	(MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB)
+
+/* Generic clock control */
+enum gclk_parent {
+	GCLK_PARENT_OSC0 = 0,
+	GCLK_PARENT_OSC1 = 1,
+	GCLK_PARENT_PLL0 = 2,
+	GCLK_PARENT_PLL1 = 3,
+};
+
+/* Some generic clocks have specific roles */
+#define GCLK_DAC_SAMPLE_CLK	6
+#define GCLK_LCDC_PIXCLK	7
+
+extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
+		unsigned long rate, unsigned long parent_rate);
+
+/**
+ * gclk_set_rate - configure and enable a generic clock
+ * @id: Which GCLK[id] to enable
+ * @parent: Parent clock feeding the GCLK
+ * @rate: Target rate of the GCLK in Hz
+ *
+ * Returns the actual GCLK rate in Hz, after rounding to the nearest
+ * supported rate.
+ *
+ * All three parameters are usually constant, hence the inline.
+ */
+static inline unsigned long gclk_set_rate(unsigned int id,
+		enum gclk_parent parent, unsigned long rate)
+{
+	unsigned long parent_rate;
+
+	if (id > 7)
+		return 0;
+
+	switch (parent) {
+	case GCLK_PARENT_OSC0:
+		parent_rate = CONFIG_SYS_OSC0_HZ;
+		break;
+#ifdef CONFIG_SYS_OSC1_HZ
+	case GCLK_PARENT_OSC1:
+		parent_rate = CONFIG_SYS_OSC1_HZ;
+		break;
+#endif
+#ifdef PLL0_RATE
+	case GCLK_PARENT_PLL0:
+		parent_rate = PLL0_RATE;
+		break;
+#endif
+#ifdef PLL1_RATE
+	case GCLK_PARENT_PLL1:
+		parent_rate = PLL1_RATE;
+		break;
+#endif
+	default:
+		parent_rate = 0;
+		break;
+	}
+
+	return __gclk_set_rate(id, parent, rate, parent_rate);
+}
+
+/**
+ * gclk_enable_output - enable output on a GCLK pin
+ * @id: Which GCLK[id] pin to enable
+ * @drive_strength: Drive strength of external GCLK pin, if applicable
+ */
+static inline void gclk_enable_output(unsigned int id,
+		unsigned long drive_strength)
+{
+	switch (id) {
+	case 0:
+		portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30,
+				PORTMUX_FUNC_A, drive_strength);
+		break;
+	case 1:
+		portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31,
+				PORTMUX_FUNC_A, drive_strength);
+		break;
+	case 2:
+		portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19,
+				PORTMUX_FUNC_A, drive_strength);
+		break;
+	case 3:
+		portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29,
+				PORTMUX_FUNC_A, drive_strength);
+		break;
+	case 4:
+		portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30,
+				PORTMUX_FUNC_A, drive_strength);
+		break;
+	}
+}
 
 #endif /* __ASM_AVR32_ARCH_CLK_H__ */
diff --git a/include/asm-avr32/arch-at32ap700x/gpio.h b/include/asm-avr32/arch-at32ap700x/gpio.h
index 8c922c7..303e353 100644
--- a/include/asm-avr32/arch-at32ap700x/gpio.h
+++ b/include/asm-avr32/arch-at32ap700x/gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2006 Atmel Corporation
+ * Copyright (C) 2006, 2008 Atmel Corporation
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -31,161 +31,17 @@
  * Pin numbers identifying specific GPIO pins on the chip.
  */
 #define GPIO_PIOA_BASE	(0)
-#define GPIO_PIN_PA0	(GPIO_PIOA_BASE +  0)
-#define GPIO_PIN_PA1	(GPIO_PIOA_BASE +  1)
-#define GPIO_PIN_PA2	(GPIO_PIOA_BASE +  2)
-#define GPIO_PIN_PA3	(GPIO_PIOA_BASE +  3)
-#define GPIO_PIN_PA4	(GPIO_PIOA_BASE +  4)
-#define GPIO_PIN_PA5	(GPIO_PIOA_BASE +  5)
-#define GPIO_PIN_PA6	(GPIO_PIOA_BASE +  6)
-#define GPIO_PIN_PA7	(GPIO_PIOA_BASE +  7)
-#define GPIO_PIN_PA8	(GPIO_PIOA_BASE +  8)
-#define GPIO_PIN_PA9	(GPIO_PIOA_BASE +  9)
-#define GPIO_PIN_PA10	(GPIO_PIOA_BASE + 10)
-#define GPIO_PIN_PA11	(GPIO_PIOA_BASE + 11)
-#define GPIO_PIN_PA12	(GPIO_PIOA_BASE + 12)
-#define GPIO_PIN_PA13	(GPIO_PIOA_BASE + 13)
-#define GPIO_PIN_PA14	(GPIO_PIOA_BASE + 14)
-#define GPIO_PIN_PA15	(GPIO_PIOA_BASE + 15)
-#define GPIO_PIN_PA16	(GPIO_PIOA_BASE + 16)
-#define GPIO_PIN_PA17	(GPIO_PIOA_BASE + 17)
-#define GPIO_PIN_PA18	(GPIO_PIOA_BASE + 18)
-#define GPIO_PIN_PA19	(GPIO_PIOA_BASE + 19)
-#define GPIO_PIN_PA20	(GPIO_PIOA_BASE + 20)
-#define GPIO_PIN_PA21	(GPIO_PIOA_BASE + 21)
-#define GPIO_PIN_PA22	(GPIO_PIOA_BASE + 22)
-#define GPIO_PIN_PA23	(GPIO_PIOA_BASE + 23)
-#define GPIO_PIN_PA24	(GPIO_PIOA_BASE + 24)
-#define GPIO_PIN_PA25	(GPIO_PIOA_BASE + 25)
-#define GPIO_PIN_PA26	(GPIO_PIOA_BASE + 26)
-#define GPIO_PIN_PA27	(GPIO_PIOA_BASE + 27)
-#define GPIO_PIN_PA28	(GPIO_PIOA_BASE + 28)
-#define GPIO_PIN_PA29	(GPIO_PIOA_BASE + 29)
-#define GPIO_PIN_PA30	(GPIO_PIOA_BASE + 30)
-#define GPIO_PIN_PA31	(GPIO_PIOA_BASE + 31)
-
 #define GPIO_PIOB_BASE	(GPIO_PIOA_BASE + 32)
-#define GPIO_PIN_PB0	(GPIO_PIOB_BASE +  0)
-#define GPIO_PIN_PB1	(GPIO_PIOB_BASE +  1)
-#define GPIO_PIN_PB2	(GPIO_PIOB_BASE +  2)
-#define GPIO_PIN_PB3	(GPIO_PIOB_BASE +  3)
-#define GPIO_PIN_PB4	(GPIO_PIOB_BASE +  4)
-#define GPIO_PIN_PB5	(GPIO_PIOB_BASE +  5)
-#define GPIO_PIN_PB6	(GPIO_PIOB_BASE +  6)
-#define GPIO_PIN_PB7	(GPIO_PIOB_BASE +  7)
-#define GPIO_PIN_PB8	(GPIO_PIOB_BASE +  8)
-#define GPIO_PIN_PB9	(GPIO_PIOB_BASE +  9)
-#define GPIO_PIN_PB10	(GPIO_PIOB_BASE + 10)
-#define GPIO_PIN_PB11	(GPIO_PIOB_BASE + 11)
-#define GPIO_PIN_PB12	(GPIO_PIOB_BASE + 12)
-#define GPIO_PIN_PB13	(GPIO_PIOB_BASE + 13)
-#define GPIO_PIN_PB14	(GPIO_PIOB_BASE + 14)
-#define GPIO_PIN_PB15	(GPIO_PIOB_BASE + 15)
-#define GPIO_PIN_PB16	(GPIO_PIOB_BASE + 16)
-#define GPIO_PIN_PB17	(GPIO_PIOB_BASE + 17)
-#define GPIO_PIN_PB18	(GPIO_PIOB_BASE + 18)
-#define GPIO_PIN_PB19	(GPIO_PIOB_BASE + 19)
-#define GPIO_PIN_PB20	(GPIO_PIOB_BASE + 20)
-#define GPIO_PIN_PB21	(GPIO_PIOB_BASE + 21)
-#define GPIO_PIN_PB22	(GPIO_PIOB_BASE + 22)
-#define GPIO_PIN_PB23	(GPIO_PIOB_BASE + 23)
-#define GPIO_PIN_PB24	(GPIO_PIOB_BASE + 24)
-#define GPIO_PIN_PB25	(GPIO_PIOB_BASE + 25)
-#define GPIO_PIN_PB26	(GPIO_PIOB_BASE + 26)
-#define GPIO_PIN_PB27	(GPIO_PIOB_BASE + 27)
-#define GPIO_PIN_PB28	(GPIO_PIOB_BASE + 28)
-#define GPIO_PIN_PB29	(GPIO_PIOB_BASE + 29)
-#define GPIO_PIN_PB30	(GPIO_PIOB_BASE + 30)
-
 #define GPIO_PIOC_BASE	(GPIO_PIOB_BASE + 32)
-#define GPIO_PIN_PC0	(GPIO_PIOC_BASE +  0)
-#define GPIO_PIN_PC1	(GPIO_PIOC_BASE +  1)
-#define GPIO_PIN_PC2	(GPIO_PIOC_BASE +  2)
-#define GPIO_PIN_PC3	(GPIO_PIOC_BASE +  3)
-#define GPIO_PIN_PC4	(GPIO_PIOC_BASE +  4)
-#define GPIO_PIN_PC5	(GPIO_PIOC_BASE +  5)
-#define GPIO_PIN_PC6	(GPIO_PIOC_BASE +  6)
-#define GPIO_PIN_PC7	(GPIO_PIOC_BASE +  7)
-#define GPIO_PIN_PC8	(GPIO_PIOC_BASE +  8)
-#define GPIO_PIN_PC9	(GPIO_PIOC_BASE +  9)
-#define GPIO_PIN_PC10	(GPIO_PIOC_BASE + 10)
-#define GPIO_PIN_PC11	(GPIO_PIOC_BASE + 11)
-#define GPIO_PIN_PC12	(GPIO_PIOC_BASE + 12)
-#define GPIO_PIN_PC13	(GPIO_PIOC_BASE + 13)
-#define GPIO_PIN_PC14	(GPIO_PIOC_BASE + 14)
-#define GPIO_PIN_PC15	(GPIO_PIOC_BASE + 15)
-#define GPIO_PIN_PC16	(GPIO_PIOC_BASE + 16)
-#define GPIO_PIN_PC17	(GPIO_PIOC_BASE + 17)
-#define GPIO_PIN_PC18	(GPIO_PIOC_BASE + 18)
-#define GPIO_PIN_PC19	(GPIO_PIOC_BASE + 19)
-#define GPIO_PIN_PC20	(GPIO_PIOC_BASE + 20)
-#define GPIO_PIN_PC21	(GPIO_PIOC_BASE + 21)
-#define GPIO_PIN_PC22	(GPIO_PIOC_BASE + 22)
-#define GPIO_PIN_PC23	(GPIO_PIOC_BASE + 23)
-#define GPIO_PIN_PC24	(GPIO_PIOC_BASE + 24)
-#define GPIO_PIN_PC25	(GPIO_PIOC_BASE + 25)
-#define GPIO_PIN_PC26	(GPIO_PIOC_BASE + 26)
-#define GPIO_PIN_PC27	(GPIO_PIOC_BASE + 27)
-#define GPIO_PIN_PC28	(GPIO_PIOC_BASE + 28)
-#define GPIO_PIN_PC29	(GPIO_PIOC_BASE + 29)
-#define GPIO_PIN_PC30	(GPIO_PIOC_BASE + 30)
-#define GPIO_PIN_PC31	(GPIO_PIOC_BASE + 31)
-
 #define GPIO_PIOD_BASE	(GPIO_PIOC_BASE + 32)
-#define GPIO_PIN_PD0	(GPIO_PIOD_BASE +  0)
-#define GPIO_PIN_PD1	(GPIO_PIOD_BASE +  1)
-#define GPIO_PIN_PD2	(GPIO_PIOD_BASE +  2)
-#define GPIO_PIN_PD3	(GPIO_PIOD_BASE +  3)
-#define GPIO_PIN_PD4	(GPIO_PIOD_BASE +  4)
-#define GPIO_PIN_PD5	(GPIO_PIOD_BASE +  5)
-#define GPIO_PIN_PD6	(GPIO_PIOD_BASE +  6)
-#define GPIO_PIN_PD7	(GPIO_PIOD_BASE +  7)
-#define GPIO_PIN_PD8	(GPIO_PIOD_BASE +  8)
-#define GPIO_PIN_PD9	(GPIO_PIOD_BASE +  9)
-#define GPIO_PIN_PD10	(GPIO_PIOD_BASE + 10)
-#define GPIO_PIN_PD11	(GPIO_PIOD_BASE + 11)
-#define GPIO_PIN_PD12	(GPIO_PIOD_BASE + 12)
-#define GPIO_PIN_PD13	(GPIO_PIOD_BASE + 13)
-#define GPIO_PIN_PD14	(GPIO_PIOD_BASE + 14)
-#define GPIO_PIN_PD15	(GPIO_PIOD_BASE + 15)
-#define GPIO_PIN_PD16	(GPIO_PIOD_BASE + 16)
-#define GPIO_PIN_PD17	(GPIO_PIOD_BASE + 17)
-
 #define GPIO_PIOE_BASE	(GPIO_PIOD_BASE + 32)
-#define GPIO_PIN_PE0	(GPIO_PIOE_BASE +  0)
-#define GPIO_PIN_PE1	(GPIO_PIOE_BASE +  1)
-#define GPIO_PIN_PE2	(GPIO_PIOE_BASE +  2)
-#define GPIO_PIN_PE3	(GPIO_PIOE_BASE +  3)
-#define GPIO_PIN_PE4	(GPIO_PIOE_BASE +  4)
-#define GPIO_PIN_PE5	(GPIO_PIOE_BASE +  5)
-#define GPIO_PIN_PE6	(GPIO_PIOE_BASE +  6)
-#define GPIO_PIN_PE7	(GPIO_PIOE_BASE +  7)
-#define GPIO_PIN_PE8	(GPIO_PIOE_BASE +  8)
-#define GPIO_PIN_PE9	(GPIO_PIOE_BASE +  9)
-#define GPIO_PIN_PE10	(GPIO_PIOE_BASE + 10)
-#define GPIO_PIN_PE11	(GPIO_PIOE_BASE + 11)
-#define GPIO_PIN_PE12	(GPIO_PIOE_BASE + 12)
-#define GPIO_PIN_PE13	(GPIO_PIOE_BASE + 13)
-#define GPIO_PIN_PE14	(GPIO_PIOE_BASE + 14)
-#define GPIO_PIN_PE15	(GPIO_PIOE_BASE + 15)
-#define GPIO_PIN_PE16	(GPIO_PIOE_BASE + 16)
-#define GPIO_PIN_PE17	(GPIO_PIOE_BASE + 17)
-#define GPIO_PIN_PE18	(GPIO_PIOE_BASE + 18)
-#define GPIO_PIN_PE19	(GPIO_PIOE_BASE + 19)
-#define GPIO_PIN_PE20	(GPIO_PIOE_BASE + 20)
-#define GPIO_PIN_PE21	(GPIO_PIOE_BASE + 21)
-#define GPIO_PIN_PE22	(GPIO_PIOE_BASE + 22)
-#define GPIO_PIN_PE23	(GPIO_PIOE_BASE + 23)
-#define GPIO_PIN_PE24	(GPIO_PIOE_BASE + 24)
-#define GPIO_PIN_PE25	(GPIO_PIOE_BASE + 25)
-#define GPIO_PIN_PE26	(GPIO_PIOE_BASE + 26)
+#define GPIO_PIN_PA(x)	(GPIO_PIOA_BASE + (x))
+#define GPIO_PIN_PB(x)	(GPIO_PIOB_BASE + (x))
+#define GPIO_PIN_PC(x)	(GPIO_PIOC_BASE + (x))
+#define GPIO_PIN_PD(x)	(GPIO_PIOD_BASE + (x))
+#define GPIO_PIN_PE(x)	(GPIO_PIOE_BASE + (x))
 
-#define GPIOF_PULLUP	0x00000001	/* (not-OUT) Enable pull-up */
-#define GPIOF_OUTPUT	0x00000002	/* (OUT) Enable output driver */
-#define GPIOF_DEGLITCH	0x00000004	/* (IN) Filter glitches */
-#define GPIOF_MULTIDRV	0x00000008	/* Enable multidriver option */
-
-static inline void *gpio_pin_to_addr(unsigned int pin)
+static inline void *pio_pin_to_port(unsigned int pin)
 {
 	switch (pin >> 5) {
 	case 0:
@@ -203,30 +59,6 @@ static inline void *gpio_pin_to_addr(unsigned int pin)
 	}
 }
 
-void gpio_select_periph_A(unsigned int pin, int use_pullup);
-void gpio_select_periph_B(unsigned int pin, int use_pullup);
-void gpio_select_pio(unsigned int pin, unsigned long gpiof_flags);
-void gpio_set_value(unsigned int pin, int value);
-int gpio_get_value(unsigned int pin);
-
-void gpio_enable_ebi(void);
-
-#ifdef AT32AP700x_CHIP_HAS_USART
-void gpio_enable_usart0(void);
-void gpio_enable_usart1(void);
-void gpio_enable_usart2(void);
-void gpio_enable_usart3(void);
-#endif
-#ifdef AT32AP700x_CHIP_HAS_MACB
-void gpio_enable_macb0(void);
-void gpio_enable_macb1(void);
-#endif
-#ifdef AT32AP700x_CHIP_HAS_MMCI
-void gpio_enable_mmci(void);
-#endif
-#ifdef AT32AP700x_CHIP_HAS_SPI
-void gpio_enable_spi0(unsigned long cs_mask);
-void gpio_enable_spi1(unsigned long cs_mask);
-#endif
+#include <asm/arch-common/portmux-pio.h>
 
 #endif /* __ASM_AVR32_ARCH_GPIO_H__ */
diff --git a/include/asm-avr32/arch-at32ap700x/mmc.h b/include/asm-avr32/arch-at32ap700x/mmc.h
deleted file mode 100644
index 9caba91..0000000
--- a/include/asm-avr32/arch-at32ap700x/mmc.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __ASM_AVR32_MMC_H
-#define __ASM_AVR32_MMC_H
-
-struct mmc_cid {
-	unsigned long psn;
-	unsigned short oid;
-	unsigned char mid;
-	unsigned char prv;
-	unsigned char mdt;
-	char pnm[7];
-};
-
-struct mmc_csd
-{
-	u8	csd_structure:2,
-		spec_vers:4,
-		rsvd1:2;
-	u8	taac;
-	u8	nsac;
-	u8	tran_speed;
-	u16	ccc:12,
-		read_bl_len:4;
-	u64	read_bl_partial:1,
-		write_blk_misalign:1,
-		read_blk_misalign:1,
-		dsr_imp:1,
-		rsvd2:2,
-		c_size:12,
-		vdd_r_curr_min:3,
-		vdd_r_curr_max:3,
-		vdd_w_curr_min:3,
-		vdd_w_curr_max:3,
-		c_size_mult:3,
-		sector_size:5,
-		erase_grp_size:5,
-		wp_grp_size:5,
-		wp_grp_enable:1,
-		default_ecc:2,
-		r2w_factor:3,
-		write_bl_len:4,
-		write_bl_partial:1,
-		rsvd3:5;
-	u8	file_format_grp:1,
-		copy:1,
-		perm_write_protect:1,
-		tmp_write_protect:1,
-		file_format:2,
-		ecc:2;
-	u8	crc:7;
-	u8	one:1;
-};
-
-#define R1_ILLEGAL_COMMAND		(1 << 22)
-#define R1_APP_CMD			(1 << 5)
-
-#endif /* __ASM_AVR32_MMC_H */
diff --git a/include/asm-avr32/arch-at32ap700x/portmux.h b/include/asm-avr32/arch-at32ap700x/portmux.h
new file mode 100644
index 0000000..96fe70d
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap700x/portmux.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2006, 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_ARCH_PORTMUX_H__
+#define __ASM_AVR32_ARCH_PORTMUX_H__
+
+#include <asm/arch/gpio.h>
+
+#define PORTMUX_PORT_A		((void *)PIOA_BASE)
+#define PORTMUX_PORT_B		((void *)PIOB_BASE)
+#define PORTMUX_PORT_C		((void *)PIOC_BASE)
+#define PORTMUX_PORT_D		((void *)PIOD_BASE)
+#define PORTMUX_PORT_E		((void *)PIOE_BASE)
+
+void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width,
+		unsigned long flags, unsigned long drive_strength);
+
+#define PORTMUX_EBI_CS(x)	(1 << (x))
+#define PORTMUX_EBI_NAND	(1 << 6)
+#define PORTMUX_EBI_CF(x)	(1 << ((x) + 7))
+#define PORTMUX_EBI_NWAIT	(1 << 9)
+
+#ifdef AT32AP700x_CHIP_HAS_USART
+static inline void portmux_enable_usart0(unsigned long drive_strength)
+{
+	portmux_select_peripheral(PORTMUX_PORT_A, (1 << 8) | (1 << 9),
+			PORTMUX_FUNC_B, 0);
+}
+
+static inline void portmux_enable_usart1(unsigned long drive_strength)
+{
+	portmux_select_peripheral(PORTMUX_PORT_A, (1 << 17) | (1 << 18),
+			PORTMUX_FUNC_A, 0);
+}
+
+static inline void portmux_enable_usart2(unsigned long drive_strength)
+{
+	portmux_select_peripheral(PORTMUX_PORT_B, (1 << 26) | (1 << 27),
+			PORTMUX_FUNC_B, 0);
+}
+
+static inline void portmux_enable_usart3(unsigned long drive_strength)
+{
+	portmux_select_peripheral(PORTMUX_PORT_B, (1 << 17) | (1 << 18),
+			PORTMUX_FUNC_B, 0);
+}
+#endif
+#ifdef AT32AP700x_CHIP_HAS_MACB
+void portmux_enable_macb0(unsigned long flags, unsigned long drive_strength);
+void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength);
+
+#define PORTMUX_MACB_RMII	(0)
+#define PORTMUX_MACB_MII	(1 << 0)
+#define PORTMUX_MACB_SPEED	(1 << 1)
+
+#endif
+#ifdef AT32AP700x_CHIP_HAS_MMCI
+void portmux_enable_mmci(unsigned int slot, unsigned long flags,
+		unsigned long drive_strength);
+
+#define PORTMUX_MMCI_4BIT	(1 << 0)
+#define PORTMUX_MMCI_8BIT	(PORTMUX_MMCI_4BIT | (1 << 1))
+#define PORTMUX_MMCI_EXT_PULLUP	(1 << 2)
+
+#endif
+#ifdef AT32AP700x_CHIP_HAS_SPI
+void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength);
+void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength);
+#endif
+
+#endif /* __ASM_AVR32_ARCH_PORTMUX_H__ */
diff --git a/include/asm-avr32/arch-common/portmux-gpio.h b/include/asm-avr32/arch-common/portmux-gpio.h
new file mode 100644
index 0000000..24943ec
--- /dev/null
+++ b/include/asm-avr32/arch-common/portmux-gpio.h
@@ -0,0 +1,193 @@
+/*
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __AVR32_PORTMUX_GPIO_H__
+#define __AVR32_PORTMUX_GPIO_H__
+
+#include <asm/io.h>
+
+/* Register offsets */
+struct gpio_regs {
+	u32	GPER;
+	u32	GPERS;
+	u32	GPERC;
+	u32	GPERT;
+	u32	PMR0;
+	u32	PMR0S;
+	u32	PMR0C;
+	u32	PMR0T;
+	u32	PMR1;
+	u32	PMR1S;
+	u32	PMR1C;
+	u32	PMR1T;
+	u32	__reserved0[4];
+	u32	ODER;
+	u32	ODERS;
+	u32	ODERC;
+	u32	ODERT;
+	u32	OVR;
+	u32	OVRS;
+	u32	OVRC;
+	u32	OVRT;
+	u32	PVR;
+	u32	__reserved_PVRS;
+	u32	__reserved_PVRC;
+	u32	__reserved_PVRT;
+	u32	PUER;
+	u32	PUERS;
+	u32	PUERC;
+	u32	PUERT;
+	u32	PDER;
+	u32	PDERS;
+	u32	PDERC;
+	u32	PDERT;
+	u32	IER;
+	u32	IERS;
+	u32	IERC;
+	u32	IERT;
+	u32	IMR0;
+	u32	IMR0S;
+	u32	IMR0C;
+	u32	IMR0T;
+	u32	IMR1;
+	u32	IMR1S;
+	u32	IMR1C;
+	u32	IMR1T;
+	u32	GFER;
+	u32	GFERS;
+	u32	GFERC;
+	u32	GFERT;
+	u32	IFR;
+	u32	__reserved_IFRS;
+	u32	IFRC;
+	u32	__reserved_IFRT;
+	u32	ODMER;
+	u32	ODMERS;
+	u32	ODMERC;
+	u32	ODMERT;
+	u32	__reserved1[4];
+	u32	ODCR0;
+	u32	ODCR0S;
+	u32	ODCR0C;
+	u32	ODCR0T;
+	u32	ODCR1;
+	u32	ODCR1S;
+	u32	ODCR1C;
+	u32	ODCR1T;
+	u32	__reserved2[4];
+	u32	OSRR0;
+	u32	OSRR0S;
+	u32	OSRR0C;
+	u32	OSRR0T;
+	u32	__reserved3[8];
+	u32	STER;
+	u32	STERS;
+	u32	STERC;
+	u32	STERT;
+	u32	__reserved4[35];
+	u32	VERSION;
+};
+
+/* Register access macros */
+#define gpio_readl(port, reg)						\
+	__raw_readl(&((struct gpio_regs *)port)->reg)
+#define gpio_writel(gpio, reg, value)					\
+	__raw_writel(value, &((struct gpio_regs *)port)->reg)
+
+/* Portmux API starts here. See doc/README.AVR32-port-muxing */
+
+enum portmux_function {
+	PORTMUX_FUNC_A,
+	PORTMUX_FUNC_B,
+	PORTMUX_FUNC_C,
+	PORTMUX_FUNC_D,
+};
+
+#define PORTMUX_DIR_INPUT	(0 << 0)
+#define PORTMUX_DIR_OUTPUT	(1 << 0)
+#define PORTMUX_INIT_LOW	(0 << 1)
+#define PORTMUX_INIT_HIGH	(1 << 1)
+#define PORTMUX_PULL_UP		(1 << 2)
+#define PORTMUX_PULL_DOWN	(2 << 2)
+#define PORTMUX_BUSKEEPER	(3 << 2)
+#define PORTMUX_DRIVE_MIN	(0 << 4)
+#define PORTMUX_DRIVE_LOW	(1 << 4)
+#define PORTMUX_DRIVE_HIGH	(2 << 4)
+#define PORTMUX_DRIVE_MAX	(3 << 4)
+#define PORTMUX_OPEN_DRAIN	(1 << 6)
+
+void portmux_select_peripheral(void *port, unsigned long pin_mask,
+		enum portmux_function func, unsigned long flags);
+void portmux_select_gpio(void *port, unsigned long pin_mask,
+		unsigned long flags);
+
+/* Internal helper functions */
+
+static inline void *gpio_pin_to_port(unsigned int pin)
+{
+	return (void *)GPIO_BASE + (pin >> 5) * 0x200;
+}
+
+static inline void __gpio_set_output_value(void *port, unsigned int pin,
+		int value)
+{
+	if (value)
+		gpio_writel(port, OVRS, 1 << pin);
+	else
+		gpio_writel(port, OVRC, 1 << pin);
+}
+
+static inline int __gpio_get_input_value(void *port, unsigned int pin)
+{
+	return (gpio_readl(port, PVR) >> pin) & 1;
+}
+
+void gpio_set_output_value(unsigned int pin, int value);
+int gpio_get_input_value(unsigned int pin);
+
+/* GPIO API starts here */
+
+/*
+ * GCC doesn't realize that the constant case is extremely trivial,
+ * so we need to help it make the right decision by using
+ * always_inline.
+ */
+__attribute__((always_inline))
+static inline void gpio_set_value(unsigned int pin, int value)
+{
+	if (__builtin_constant_p(pin))
+		__gpio_set_output_value(gpio_pin_to_port(pin),
+				pin & 0x1f, value);
+	else
+		gpio_set_output_value(pin, value);
+}
+
+__attribute__((always_inline))
+static inline int gpio_get_value(unsigned int pin)
+{
+	if (__builtin_constant_p(pin))
+		return __gpio_get_input_value(gpio_pin_to_port(pin),
+				pin & 0x1f);
+	else
+		return gpio_get_input_value(pin);
+}
+
+#endif /* __AVR32_PORTMUX_GPIO_H__ */
diff --git a/include/asm-avr32/arch-common/portmux-pio.h b/include/asm-avr32/arch-common/portmux-pio.h
new file mode 100644
index 0000000..1abe5be
--- /dev/null
+++ b/include/asm-avr32/arch-common/portmux-pio.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2006, 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __AVR32_PORTMUX_PIO_H__
+#define __AVR32_PORTMUX_PIO_H__
+
+#include <asm/io.h>
+
+/* PIO register offsets */
+#define PIO_PER			0x0000
+#define PIO_PDR			0x0004
+#define PIO_PSR			0x0008
+#define PIO_OER			0x0010
+#define PIO_ODR			0x0014
+#define PIO_OSR			0x0018
+#define PIO_IFER		0x0020
+#define PIO_IFDR		0x0024
+#define PIO_ISFR		0x0028
+#define PIO_SODR		0x0030
+#define PIO_CODR		0x0034
+#define PIO_ODSR		0x0038
+#define PIO_PDSR		0x003c
+#define PIO_IER			0x0040
+#define PIO_IDR			0x0044
+#define PIO_IMR			0x0048
+#define PIO_ISR			0x004c
+#define PIO_MDER		0x0050
+#define PIO_MDDR		0x0054
+#define PIO_MDSR		0x0058
+#define PIO_PUDR		0x0060
+#define PIO_PUER		0x0064
+#define PIO_PUSR		0x0068
+#define PIO_ASR			0x0070
+#define PIO_BSR			0x0074
+#define PIO_ABSR		0x0078
+#define PIO_OWER		0x00a0
+#define PIO_OWDR		0x00a4
+#define PIO_OWSR		0x00a8
+
+/* Hardware register access */
+#define pio_readl(base, reg)				\
+	__raw_readl((void *)base + PIO_##reg)
+#define pio_writel(base, reg, value)			\
+	__raw_writel((value), (void *)base + PIO_##reg)
+
+/* Portmux API starts here. See doc/README.AVR32-port-muxing */
+
+enum portmux_function {
+	PORTMUX_FUNC_A,
+	PORTMUX_FUNC_B,
+};
+
+/* Pull-down, buskeeper and drive strength are not supported */
+#define PORTMUX_DIR_INPUT	(0 << 0)
+#define PORTMUX_DIR_OUTPUT	(1 << 0)
+#define PORTMUX_INIT_LOW	(0 << 1)
+#define PORTMUX_INIT_HIGH	(1 << 1)
+#define PORTMUX_PULL_UP		(1 << 2)
+#define PORTMUX_PULL_DOWN	(0)
+#define PORTMUX_BUSKEEPER	PORTMUX_PULL_UP
+#define PORTMUX_DRIVE_MIN	(0)
+#define PORTMUX_DRIVE_LOW	(0)
+#define PORTMUX_DRIVE_HIGH	(0)
+#define PORTMUX_DRIVE_MAX	(0)
+#define PORTMUX_OPEN_DRAIN	(1 << 3)
+
+void portmux_select_peripheral(void *port, unsigned long pin_mask,
+		enum portmux_function func, unsigned long flags);
+void portmux_select_gpio(void *port, unsigned long pin_mask,
+		unsigned long flags);
+
+/* Internal helper functions */
+
+static inline void __pio_set_output_value(void *port, unsigned int pin,
+		int value)
+{
+	/*
+	 * value will usually be constant, but it's pretty cheap
+	 * either way.
+	 */
+	if (value)
+		pio_writel(port, SODR, 1 << pin);
+	else
+		pio_writel(port, CODR, 1 << pin);
+}
+
+static inline int __pio_get_input_value(void *port, unsigned int pin)
+{
+	return (pio_readl(port, PDSR) >> pin) & 1;
+}
+
+void pio_set_output_value(unsigned int pin, int value);
+int pio_get_input_value(unsigned int pin);
+
+/* GPIO API starts here */
+
+/*
+ * GCC doesn't realize that the constant case is extremely trivial,
+ * so we need to help it make the right decision by using
+ * always_inline.
+ */
+__attribute__((always_inline))
+static inline void gpio_set_value(unsigned int pin, int value)
+{
+	if (__builtin_constant_p(pin))
+		__pio_set_output_value(pio_pin_to_port(pin), pin & 0x1f, value);
+	else
+		pio_set_output_value(pin, value);
+}
+
+__attribute__((always_inline))
+static inline int gpio_get_value(unsigned int pin)
+{
+	if (__builtin_constant_p(pin))
+		return __pio_get_input_value(pio_pin_to_port(pin), pin & 0x1f);
+	else
+		return pio_get_input_value(pin);
+}
+
+#endif /* __AVR32_PORTMUX_PIO_H__ */
diff --git a/include/asm-avr32/config.h b/include/asm-avr32/config.h
new file mode 100644
index 0000000..049c44e
--- /dev/null
+++ b/include/asm-avr32/config.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
diff --git a/include/asm-avr32/global_data.h b/include/asm-avr32/global_data.h
index 75e75cc..97a6c61 100644
--- a/include/asm-avr32/global_data.h
+++ b/include/asm-avr32/global_data.h
@@ -29,7 +29,7 @@
  * global variables during system initialization (until we have set
  * up the memory controller so that we can use RAM).
  *
- * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
  */
 
 typedef	struct	global_data {
diff --git a/include/asm-avr32/initcalls.h b/include/asm-avr32/initcalls.h
index 583e5dc..57a278b 100644
--- a/include/asm-avr32/initcalls.h
+++ b/include/asm-avr32/initcalls.h
@@ -26,6 +26,5 @@
 
 extern int cpu_init(void);
 extern int timer_init(void);
-extern void board_init_info(void);
 
 #endif /* __ASM_AVR32_INITCALLS_H__ */
diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h
index 06e52b1..50967ac 100644
--- a/include/asm-avr32/io.h
+++ b/include/asm-avr32/io.h
@@ -76,12 +76,12 @@ extern void __readwrite_bug(const char *fn);
 #include <asm/addrspace.h>
 
 /* virt_to_phys will only work when address is in P1 or P2 */
-static __inline__ unsigned long virt_to_phys(volatile void *address)
+static inline phys_addr_t virt_to_phys(volatile void *address)
 {
 	return PHYSADDR(address);
 }
 
-static __inline__ void * phys_to_virt(unsigned long address)
+static inline void *phys_to_virt(phys_addr_t address)
 {
 	return (void *)P1SEGADDR(address);
 }
diff --git a/include/asm-avr32/sdram.h b/include/asm-avr32/sdram.h
index 7bdefc1..762acfa 100644
--- a/include/asm-avr32/sdram.h
+++ b/include/asm-avr32/sdram.h
@@ -25,8 +25,8 @@
 struct sdram_config {
 	/* Number of data bits. */
 	enum {
-		SDRAM_DATA_16BIT,
-		SDRAM_DATA_32BIT,
+		SDRAM_DATA_16BIT = 16,
+		SDRAM_DATA_32BIT = 32,
 	} data_bits;
 
 	/* Number of address bits */
diff --git a/include/asm-blackfin/blackfin-config-post.h b/include/asm-blackfin/blackfin-config-post.h
index 6a1ffa1..fea4737 100644
--- a/include/asm-blackfin/blackfin-config-post.h
+++ b/include/asm-blackfin/blackfin-config-post.h
@@ -1,7 +1,7 @@
 /*
  * blackfin-config-post.h - setup common defines for Blackfin boards based on config.h
  *
- * Copyright (c) 2007 Analog Devices Inc.
+ * Copyright (c) 2007-2008 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -9,19 +9,14 @@
 #ifndef __ASM_BLACKFIN_CONFIG_POST_H__
 #define __ASM_BLACKFIN_CONFIG_POST_H__
 
-/* Check to make sure everything fits in external RAM */
-#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE)
-# error Memory Map does not fit into configuration
-#endif
-
 /* Sanity check CONFIG_BFIN_CPU */
 #ifndef CONFIG_BFIN_CPU
 # error CONFIG_BFIN_CPU: your board config needs to define this
 #endif
 
 /* Make sure the structure is properly aligned */
-#if ((CFG_GBL_DATA_ADDR & -4) != CFG_GBL_DATA_ADDR)
-# error CFG_GBL_DATA_ADDR: must be 4 byte aligned
+#if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR)
+# error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned
 #endif
 
 /* Set default CONFIG_VCO_HZ if need be */
@@ -65,8 +60,86 @@
 #endif
 
 /* Using L1 scratch pad makes sense for everyone by default. */
-#ifndef CMD_LINE_ADDR
-# define CMD_LINE_ADDR L1_SRAM_SCRATCH
+#ifndef CONFIG_LINUX_CMDLINE_ADDR
+# define CONFIG_LINUX_CMDLINE_ADDR L1_SRAM_SCRATCH
+#endif
+#ifndef CONFIG_LINUX_CMDLINE_SIZE
+# define CONFIG_LINUX_CMDLINE_SIZE L1_SRAM_SCRATCH_SIZE
+#endif
+
+/* Set default SPI flash CS to the one we boot from */
+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_SPI_CS)
+# define CONFIG_ENV_SPI_CS BFIN_BOOT_SPI_SSEL
+#endif
+
+/* Default/common Blackfin memory layout */
+#ifndef CONFIG_SYS_SDRAM_BASE
+# define CONFIG_SYS_SDRAM_BASE 0
+#endif
+#ifndef CONFIG_SYS_MAX_RAM_SIZE
+# define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
+#endif
+#ifndef CONFIG_SYS_MONITOR_BASE
+# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
+#endif
+#ifndef CONFIG_SYS_MALLOC_BASE
+# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#endif
+#ifndef CONFIG_SYS_GBL_DATA_SIZE
+# define CONFIG_SYS_GBL_DATA_SIZE (128)
+#endif
+#ifndef CONFIG_SYS_GBL_DATA_ADDR
+# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#endif
+#ifndef CONFIG_STACKBASE
+# define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
+#endif
+#ifndef CONFIG_SYS_MEMTEST_START
+# define CONFIG_SYS_MEMTEST_START 0
+#endif
+#ifndef CONFIG_SYS_MEMTEST_END
+# define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 8192 + 4)
+#endif
+
+/* Check to make sure everything fits in external RAM */
+#if ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE)
+# error Memory Map does not fit into configuration
+#endif
+
+/* Default/common Blackfin environment settings */
+#ifndef CONFIG_LOADADDR
+# define CONFIG_LOADADDR 0x1000000
+#endif
+#ifndef CONFIG_SYS_LOAD_ADDR
+# define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#endif
+#ifndef CONFIG_SYS_BOOTM_LEN
+# define CONFIG_SYS_BOOTM_LEN 0x4000000
+#endif
+#ifndef CONFIG_SYS_PROMPT
+# define CONFIG_SYS_PROMPT "bfin> "
+#endif
+#ifndef CONFIG_SYS_CBSIZE
+# ifdef CONFIG_CMD_KGDB
+#  define CONFIG_SYS_CBSIZE 1024
+# else
+#  define CONFIG_SYS_CBSIZE 256
+# endif
+#endif
+#ifndef CONFIG_SYS_BARGSIZE
+# define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#endif
+#ifndef CONFIG_SYS_PBSIZE
+# define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#endif
+#ifndef CONFIG_SYS_MAXARGS
+# define CONFIG_SYS_MAXARGS 16
+#endif
+#ifndef CONFIG_SYS_HZ
+# define CONFIG_SYS_HZ 1000
+#endif
+#ifndef CONFIG_SYS_BAUDRATE_TABLE
+# define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
 #endif
 
 #endif
diff --git a/include/asm-blackfin/blackfin-config-pre.h b/include/asm-blackfin/blackfin-config-pre.h
index f2c44f7..9df01ad 100644
--- a/include/asm-blackfin/blackfin-config-pre.h
+++ b/include/asm-blackfin/blackfin-config-pre.h
@@ -15,12 +15,12 @@
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 
 /* Configurable Blackfin-specific monitor commands */
-#define CFG_BFIN_CMD_BOOTLDR     0x01
-#define CFG_BFIN_CMD_CPLBINFO    0x02
-#define CFG_BFIN_CMD_OTP         0x04
-#define CFG_BFIN_CMD_CACHE_DUMP  0x08
+#define CONFIG_SYS_BFIN_CMD_BOOTLDR     0x01
+#define CONFIG_SYS_BFIN_CMD_CPLBINFO    0x02
+#define CONFIG_SYS_BFIN_CMD_OTP         0x04
+#define CONFIG_SYS_BFIN_CMD_CACHE_DUMP  0x08
 
-/* Bootmode defines -- your config needs to select this via BFIN_BOOT_MODE.
+/* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE.
  * Depending on your cpu, some of these may not be valid, check your HRM.
  * The actual values here are meaningless as long as they're unique.
  */
@@ -36,5 +36,37 @@
 #define BFIN_BOOT_MEM         10      /* boot ldr out of memory (warmboot) */
 #define BFIN_BOOT_16HOST_DMA  11      /* boot ldr from 16-bit host dma */
 #define BFIN_BOOT_8HOST_DMA   12      /* boot ldr from 8-bit host dma */
+#define BFIN_BOOT_NAND        13      /* boot ldr from nand flash */
+
+#ifndef __ASSEMBLY__
+static inline const char *get_bfin_boot_mode(int bfin_boot)
+{
+	switch (bfin_boot) {
+	case BFIN_BOOT_BYPASS:     return "bypass";
+	case BFIN_BOOT_PARA:       return "parallel flash";
+	case BFIN_BOOT_SPI_MASTER: return "spi flash";
+	case BFIN_BOOT_SPI_SLAVE:  return "spi slave";
+	case BFIN_BOOT_TWI_MASTER: return "i2c flash";
+	case BFIN_BOOT_TWI_SLAVE:  return "i2c slave";
+	case BFIN_BOOT_UART:       return "uart";
+	case BFIN_BOOT_IDLE:       return "idle";
+	case BFIN_BOOT_FIFO:       return "fifo";
+	case BFIN_BOOT_MEM:        return "memory";
+	case BFIN_BOOT_16HOST_DMA: return "16bit dma";
+	case BFIN_BOOT_8HOST_DMA:  return "8bit dma";
+	case BFIN_BOOT_NAND:       return "nand flash";
+	default:                   return "INVALID";
+	}
+}
+#endif
+
+/* Define the default SPI CS used when booting out of SPI */
+#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
+    defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \
+    defined(__ADSPBF51x__)
+# define BFIN_BOOT_SPI_SSEL 2
+#else
+# define BFIN_BOOT_SPI_SSEL 1
+#endif
 
 #endif
diff --git a/include/asm-blackfin/blackfin_local.h b/include/asm-blackfin/blackfin_local.h
index 6f0e662..e17d8a2 100644
--- a/include/asm-blackfin/blackfin_local.h
+++ b/include/asm-blackfin/blackfin_local.h
@@ -43,6 +43,9 @@
 #define SCLK_TO_MSEC(sclk) ((MSEC_PER_SEC * ((sclk) / USEC_PER_MSEC)) / (BFIN_SCLK / USEC_PER_MSEC))
 #define MSEC_TO_SCLK(msec) ((((BFIN_SCLK / USEC_PER_MSEC) * (msec)) / MSEC_PER_SEC) * USEC_PER_MSEC)
 
+#define L1_CACHE_SHIFT 5
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+
 #include <asm/linkage.h>
 
 #ifndef __ASSEMBLY__
@@ -52,25 +55,22 @@
 
 # include <linux/types.h>
 
+extern u_long get_vco(void);
+extern u_long get_cclk(void);
 extern u_long get_sclk(void);
 
 # define bfin_revid() (*pCHIPID >> 28)
 
 extern void blackfin_icache_flush_range(const void *, const void *);
 extern void blackfin_dcache_flush_range(const void *, const void *);
-extern void blackfin_dcache_invalidate_range(const void *, const void *);
-
-/* Use DMA to move data from on chip to external memory.  While this is
- * required for only L1 instruction (it is not directly readable by the
- * core via data loads), it isn't a huge performance issue for other
- * regions (it's probably even faster than core load/stores).  However,
- * the DMA engine does not have access to the L1 scratchpad, and we
- * cannot use DMA inside of the MMR space.
+extern void blackfin_icache_dcache_flush_range(const void *, const void *);
+extern void blackfin_dcache_flush_invalidate_range(const void *, const void *);
+
+/* Use DMA to move data from on chip to external memory.  The L1 instruction
+ * regions can only be accessed via DMA, so if the address in question is in
+ * that region, make sure we attempt to DMA indirectly.
  */
-# define addr_bfin_on_chip_mem(addr) \
-	(((unsigned long)(addr) >= 0xef000000 && (unsigned long)addr < SYSMMR_BASE) && \
-	 !((unsigned long)(addr) >= L1_SRAM_SCRATCH && \
-	   (unsigned long)(addr) < L1_SRAM_SCRATCH_END))
+# define addr_bfin_on_chip_mem(addr) (((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000)
 
 # include <asm/system.h>
 
diff --git a/include/asm-blackfin/config.h b/include/asm-blackfin/config.h
new file mode 100644
index 0000000..049c44e
--- /dev/null
+++ b/include/asm-blackfin/config.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
index e36af2d..cc21e93 100644
--- a/include/asm-blackfin/cplb.h
+++ b/include/asm-blackfin/cplb.h
@@ -73,9 +73,4 @@
 #define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
 #endif
 
-#if defined(CONFIG_BF561)
-#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 4)	/* SDRAM +L1 + ASYNC_Memory */
-#else
-#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2)	/* SDRAM + L1 + ASYNC_Memory */
-#endif
 #endif				/* _CPLB_H */
diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h
index 2f40870..5c9903b 100644
--- a/include/asm-blackfin/global_data.h
+++ b/include/asm-blackfin/global_data.h
@@ -35,7 +35,7 @@
  * global variables during system initialization (until we have set
  * up the memory controller so that we can use RAM).
  *
- * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
  */
 typedef struct global_data {
 	bd_t *bd;
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
index da58914..6806494 100644
--- a/include/asm-blackfin/io.h
+++ b/include/asm-blackfin/io.h
@@ -64,6 +64,11 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
 
 }
 
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
 /*
  * These are for ISA/PCI shared memory _only_ and should never be used
  * on any other type of memory, including Zorro memory. They are meant to
diff --git a/include/asm-blackfin/mach-bf527/BF522_cdef.h b/include/asm-blackfin/mach-bf527/BF522_cdef.h
index 480168c..987cc86 100644
--- a/include/asm-blackfin/mach-bf527/BF522_cdef.h
+++ b/include/asm-blackfin/mach-bf527/BF522_cdef.h
@@ -337,8 +337,5 @@
 #define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pDSPID                         ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID()              bfin_read32(DSPID)
-#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
 
 #endif /* __BFIN_CDEF_ADSP_BF522_proc__ */
diff --git a/include/asm-blackfin/mach-bf527/BF522_def.h b/include/asm-blackfin/mach-bf527/BF522_def.h
index ce3f8e5..44143ba 100644
--- a/include/asm-blackfin/mach-bf527/BF522_def.h
+++ b/include/asm-blackfin/mach-bf527/BF522_def.h
@@ -119,7 +119,6 @@
 #define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
 #define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
 #define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
-#define DSPID                          0xFFE05000
 #define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
 #define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
 #define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
diff --git a/include/asm-blackfin/mach-bf527/BF523_cdef.h b/include/asm-blackfin/mach-bf527/BF523_cdef.h
index 9d3cb9e..390f3dc 100644
--- a/include/asm-blackfin/mach-bf527/BF523_cdef.h
+++ b/include/asm-blackfin/mach-bf527/BF523_cdef.h
@@ -337,8 +337,5 @@
 #define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pDSPID                         ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID()              bfin_read32(DSPID)
-#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
 
 #endif /* __BFIN_CDEF_ADSP_BF523_proc__ */
diff --git a/include/asm-blackfin/mach-bf527/BF523_def.h b/include/asm-blackfin/mach-bf527/BF523_def.h
index cb15ec0..02675a9 100644
--- a/include/asm-blackfin/mach-bf527/BF523_def.h
+++ b/include/asm-blackfin/mach-bf527/BF523_def.h
@@ -119,7 +119,6 @@
 #define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
 #define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
 #define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
-#define DSPID                          0xFFE05000
 #define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
 #define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
 #define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
diff --git a/include/asm-blackfin/mach-bf527/BF524_cdef.h b/include/asm-blackfin/mach-bf527/BF524_cdef.h
index 4373bd7..9ec89c6 100644
--- a/include/asm-blackfin/mach-bf527/BF524_cdef.h
+++ b/include/asm-blackfin/mach-bf527/BF524_cdef.h
@@ -337,9 +337,6 @@
 #define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pDSPID                         ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID()              bfin_read32(DSPID)
-#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
 #define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
 #define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
 #define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
diff --git a/include/asm-blackfin/mach-bf527/BF524_def.h b/include/asm-blackfin/mach-bf527/BF524_def.h
index ef2fc0b..10793e8 100644
--- a/include/asm-blackfin/mach-bf527/BF524_def.h
+++ b/include/asm-blackfin/mach-bf527/BF524_def.h
@@ -119,7 +119,6 @@
 #define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
 #define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
 #define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
-#define DSPID                          0xFFE05000
 #define USB_FADDR                      0xFFC03800 /* Function address register */
 #define USB_POWER                      0xFFC03804 /* Power management register */
 #define USB_INTRTX                     0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
diff --git a/include/asm-blackfin/mach-bf527/BF525_cdef.h b/include/asm-blackfin/mach-bf527/BF525_cdef.h
index b406b10..8fe29db 100644
--- a/include/asm-blackfin/mach-bf527/BF525_cdef.h
+++ b/include/asm-blackfin/mach-bf527/BF525_cdef.h
@@ -337,9 +337,6 @@
 #define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pDSPID                         ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID()              bfin_read32(DSPID)
-#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
 #define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
 #define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
 #define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
diff --git a/include/asm-blackfin/mach-bf527/BF525_def.h b/include/asm-blackfin/mach-bf527/BF525_def.h
index a149eda..c4c2f2f 100644
--- a/include/asm-blackfin/mach-bf527/BF525_def.h
+++ b/include/asm-blackfin/mach-bf527/BF525_def.h
@@ -119,7 +119,6 @@
 #define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
 #define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
 #define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
-#define DSPID                          0xFFE05000
 #define USB_FADDR                      0xFFC03800 /* Function address register */
 #define USB_POWER                      0xFFC03804 /* Power management register */
 #define USB_INTRTX                     0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
diff --git a/include/asm-blackfin/mach-bf527/BF526_cdef.h b/include/asm-blackfin/mach-bf527/BF526_cdef.h
index 7653363..9438862 100644
--- a/include/asm-blackfin/mach-bf527/BF526_cdef.h
+++ b/include/asm-blackfin/mach-bf527/BF526_cdef.h
@@ -337,9 +337,6 @@
 #define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pDSPID                         ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID()              bfin_read32(DSPID)
-#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
 #define pEMAC_OPMODE                   ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
 #define bfin_read_EMAC_OPMODE()        bfin_read32(EMAC_OPMODE)
 #define bfin_write_EMAC_OPMODE(val)    bfin_write32(EMAC_OPMODE, val)
diff --git a/include/asm-blackfin/mach-bf527/BF526_def.h b/include/asm-blackfin/mach-bf527/BF526_def.h
index b432c7a..04db6c7 100644
--- a/include/asm-blackfin/mach-bf527/BF526_def.h
+++ b/include/asm-blackfin/mach-bf527/BF526_def.h
@@ -119,7 +119,6 @@
 #define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
 #define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
 #define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
-#define DSPID                          0xFFE05000
 #define EMAC_OPMODE                    0xFFC03000 /* Operating Mode Register */
 #define EMAC_ADDRLO                    0xFFC03004 /* Address Low (32 LSBs) Register */
 #define EMAC_ADDRHI                    0xFFC03008 /* Address High (16 MSBs) Register */
diff --git a/include/asm-blackfin/mach-bf527/BF527_cdef.h b/include/asm-blackfin/mach-bf527/BF527_cdef.h
index 16c8342..fb9b307 100644
--- a/include/asm-blackfin/mach-bf527/BF527_cdef.h
+++ b/include/asm-blackfin/mach-bf527/BF527_cdef.h
@@ -337,9 +337,6 @@
 #define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pDSPID                         ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID()              bfin_read32(DSPID)
-#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
 #define pEMAC_OPMODE                   ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
 #define bfin_read_EMAC_OPMODE()        bfin_read32(EMAC_OPMODE)
 #define bfin_write_EMAC_OPMODE(val)    bfin_write32(EMAC_OPMODE, val)
diff --git a/include/asm-blackfin/mach-bf527/BF527_def.h b/include/asm-blackfin/mach-bf527/BF527_def.h
index 784d627..c1e1aab 100644
--- a/include/asm-blackfin/mach-bf527/BF527_def.h
+++ b/include/asm-blackfin/mach-bf527/BF527_def.h
@@ -119,7 +119,6 @@
 #define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
 #define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
 #define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
-#define DSPID                          0xFFE05000
 #define EMAC_OPMODE                    0xFFC03000 /* Operating Mode Register */
 #define EMAC_ADDRLO                    0xFFC03004 /* Address Low (32 LSBs) Register */
 #define EMAC_ADDRHI                    0xFFC03008 /* Address High (16 MSBs) Register */
diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h
index 058d95c..035e8d8 100644
--- a/include/asm-blackfin/mach-bf527/anomaly.h
+++ b/include/asm-blackfin/mach-bf527/anomaly.h
@@ -2,41 +2,159 @@
  * File: include/asm-blackfin/mach-bf527/anomaly.h
  * Bugs: Enter bugs at http://blackfin.uclinux.org/
  *
- * Copyright (C) 2004-2007 Analog Devices Inc.
+ * Copyright (C) 2004-2008 Analog Devices Inc.
  * Licensed under the GPL-2 or later.
  */
 
 /* This file shoule be up to date with:
- *  - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List
+ *  - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List
+ *  - Revision E, 08/18/2008; ADSP-BF527 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
 #define _MACH_ANOMALY_H_
 
+#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
+# define ANOMALY_BF526 1
+#else
+# define ANOMALY_BF526 0
+#endif
+#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
+# define ANOMALY_BF527 1
+#else
+# define ANOMALY_BF527 0
+#endif
+
 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
 #define ANOMALY_05000074 (1)
 /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
+#define ANOMALY_05000119 (1)	/* note: brokenness is noted in documentation, not anomaly sheet */
 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
 #define ANOMALY_05000122 (1)
 /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
 #define ANOMALY_05000245 (1)
 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
 #define ANOMALY_05000265 (1)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
-/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_05000310 (1)
+/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
+#define ANOMALY_05000313 (__SILICON_REVISION__ < 2)
 /* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (1)
+#define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
 /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (1)
-/* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */
-#define ANOMALY_05000342 (1)
-/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (1)
+#define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
+#define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
+#define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* USB Calibration Value Is Not Initialized */
+#define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* USB Calibration Value to use */
+#define ANOMALY_05000346_value 0xE510
+/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
+#define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Security Features Are Not Functional */
+#define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1)
+/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
+#define ANOMALY_05000353 (ANOMALY_BF526)
+/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
+#define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Incorrect Revision Number in DSPID Register */
+#define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Incorrect Default CSEL Value in PLL_DIV */
+#define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
+#define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Authentication Fails To Initiate */
+#define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Data Read From L3 Memory by USB DMA May be Corrupted */
+#define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* 8-Bit NAND Flash Boot Mode Not Functional */
+#define ANOMALY_05000382 (__SILICON_REVISION__ < 2)
+/* Host Must Not Read Back During Host DMA Boot */
+#define ANOMALY_05000384 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Boot from OTP Memory Not Functional */
+#define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* bfrom_SysControl() Firmware Routine Not Functional */
+#define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Programmable Preboot Settings Not Functional */
+#define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* CRC32 Checksum Support Not Functional */
+#define ANOMALY_05000388 (__SILICON_REVISION__ < 2)
+/* Reset Vector Must Not Be in SDRAM Memory Space */
+#define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Log Buffer Not Functional */
+#define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Hook Routine Not Functional */
+#define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Header Indirect Bit Not Functional */
+#define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
+#define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
+#define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
+#define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
+#define ANOMALY_05000401 (__SILICON_REVISION__ < 2)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (__SILICON_REVISION__ < 2)
+/* Lockbox SESR Disallows Certain User Interrupts */
+#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
+/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
+#define ANOMALY_05000405 (1)
+/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
+#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
+/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
+#define ANOMALY_05000408 (1)
+/* Lockbox firmware leaves MDMA0 channel enabled */
+#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
+/* Incorrect Default Internal Voltage Regulator Setting */
+#define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
+#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
+/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
+#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
+/* DEB2_URGENT Bit Not Functional */
+#define ANOMALY_05000415 (__SILICON_REVISION__ < 2)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
+#define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
+#define ANOMALY_05000418 (__SILICON_REVISION__ < 2)
+/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
+#define ANOMALY_05000420 (__SILICON_REVISION__ < 2)
+/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
+#define ANOMALY_05000421 (1)
+/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
+#define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
+/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
+#define ANOMALY_05000423 (__SILICON_REVISION__ < 2)
+/* Internal Voltage Regulator Not Trimmed */
+#define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (__SILICON_REVISION__ < 2)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
+#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
+/* Software System Reset Corrupts PLL_LOCKCNT Register */
+#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
+/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
+#define ANOMALY_05000432 (ANOMALY_BF526)
+/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
+#define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000125 (0)
@@ -49,7 +167,12 @@
 #define ANOMALY_05000263 (0)
 #define ANOMALY_05000266 (0)
 #define ANOMALY_05000273 (0)
+#define ANOMALY_05000285 (0)
+#define ANOMALY_05000307 (0)
 #define ANOMALY_05000311 (0)
+#define ANOMALY_05000312 (0)
 #define ANOMALY_05000323 (0)
+#define ANOMALY_05000363 (0)
+#define ANOMALY_05000412 (0)
 
 #endif
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
index 98209d4..0d3a034 100644
--- a/include/asm-blackfin/mach-bf533/anomaly.h
+++ b/include/asm-blackfin/mach-bf533/anomaly.h
@@ -2,12 +2,12 @@
  * File: include/asm-blackfin/mach-bf533/anomaly.h
  * Bugs: Enter bugs at http://blackfin.uclinux.org/
  *
- * Copyright (C) 2004-2007 Analog Devices Inc.
+ * Copyright (C) 2004-2008 Analog Devices Inc.
  * Licensed under the GPL-2 or later.
  */
 
 /* This file shoule be up to date with:
- *  - Revision B, 12/10/2007; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
+ *  - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -97,11 +97,11 @@
 /* UART STB Bit Incorrectly Affects Receiver Setting */
 #define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
 /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
-#define ANOMALY_05000233 (__SILICON_REVISION__ < 4)
+#define ANOMALY_05000233 (__SILICON_REVISION__ < 6)
 /* Incorrect Revision Number in DSPID Register */
 #define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
 /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 4)
+#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
 /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
 #define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
 /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
@@ -131,7 +131,7 @@
 /* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
 #define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
+#define ANOMALY_05000265 (1)
 /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
 #define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
 /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
@@ -141,41 +141,65 @@
 /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
 #define ANOMALY_05000272 (1)
 /* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (1)
+#define ANOMALY_05000273 (__SILICON_REVISION__ < 6)
 /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
 #define ANOMALY_05000276 (1)
 /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (1)
+#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
 /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (1)
+#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
 /* False Hardware Error Exception When ISR Context Is Not Restored */
-#define ANOMALY_05000281 (1)
+#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
 /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (1)
+#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
 /* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
-#define ANOMALY_05000283 (1)
+#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
 /* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (1)
+#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
 /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
+#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
 /* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
 #define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
 /* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
 #define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
 /* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
 #define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
+/* SCKELOW Bit Does Not Maintain State Through Hibernate */
+#define ANOMALY_05000307 (1)
 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
 #define ANOMALY_05000310 (1)
 /* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
-#define ANOMALY_05000311 (1)
+#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
+#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
 /* PPI Is Level-Sensitive on First Transfer */
-#define ANOMALY_05000313 (1)
+#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
 /* Killed System MMR Write Completes Erroneously On Next System MMR Access */
-#define ANOMALY_05000315 (1)
+#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
 /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
-#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532)
+#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (__SILICON_REVISION__ < 6)
+/* UART Break Signal Issues */
+#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
+#define ANOMALY_05000371 (__SILICON_REVISION__ < 6)
+/* PPI Does Not Start Properly In Specific Mode */
+#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
+/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
+#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
 
 /* These anomalies have been "phased" out of analog.com anomaly sheets and are
  * here to show running on older silicon just isn't feasible.
@@ -249,15 +273,14 @@
 #define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
 /* Internal Voltage Regulator may not start up */
 #define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000266 (0)
 #define ANOMALY_05000323 (0)
+#define ANOMALY_05000353 (1)
+#define ANOMALY_05000386 (1)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
 
 #endif
diff --git a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h b/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h
index b000ea2..b9e4d67 100644
--- a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h
+++ b/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h
@@ -2721,9 +2721,6 @@
 #define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pDSPID                         ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID()              bfin_read32(DSPID)
-#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
 #define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
diff --git a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_def.h b/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_def.h
index 077412a..61ffa14 100644
--- a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_def.h
+++ b/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_def.h
@@ -911,7 +911,6 @@
 #define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
 #define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
 #define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
-#define DSPID                          0xFFE05000
 #define CHIPID                         0xFFC00014
 #define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
 #define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index d604457..9cb3912 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -2,12 +2,12 @@
  * File: include/asm-blackfin/mach-bf537/anomaly.h
  * Bugs: Enter bugs at http://blackfin.uclinux.org/
  *
- * Copyright (C) 2004-2007 Analog Devices Inc.
+ * Copyright (C) 2004-2008 Analog Devices Inc.
  * Licensed under the GPL-2 or later.
  */
 
 /* This file shoule be up to date with:
- *  - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
+ *  - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -132,12 +132,30 @@
 #define ANOMALY_05000322 (1)
 /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
 #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
+/* New Feature: UART Remains Enabled after UART Boot */
+#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
+/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
+#define ANOMALY_05000355 (1)
 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
 #define ANOMALY_05000357 (1)
 /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
 #define ANOMALY_05000359 (1)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
 #define ANOMALY_05000371 (1)
+/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
+#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000125 (0)
@@ -148,5 +166,11 @@
 #define ANOMALY_05000266 (0)
 #define ANOMALY_05000311 (0)
 #define ANOMALY_05000323 (0)
+#define ANOMALY_05000353 (1)
+#define ANOMALY_05000363 (0)
+#define ANOMALY_05000386 (1)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
 
 #endif
diff --git a/include/asm-blackfin/mach-bf548/BF541_cdef.h b/include/asm-blackfin/mach-bf548/BF541_cdef.h
index c0d2a42..1b8c79b 100644
--- a/include/asm-blackfin/mach-bf548/BF541_cdef.h
+++ b/include/asm-blackfin/mach-bf548/BF541_cdef.h
@@ -310,9 +310,6 @@
 #define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pDSPID                         ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID()              bfin_read32(DSPID)
-#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
 #define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
 #define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
 #define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
diff --git a/include/asm-blackfin/mach-bf548/BF541_def.h b/include/asm-blackfin/mach-bf548/BF541_def.h
index 2f9cec6..1469ac2 100644
--- a/include/asm-blackfin/mach-bf548/BF541_def.h
+++ b/include/asm-blackfin/mach-bf548/BF541_def.h
@@ -110,7 +110,6 @@
 #define IMASK                          0xFFE02104 /* Interrupt Mask Register */
 #define IPEND                          0xFFE02108 /* Interrupt Pending Register */
 #define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
-#define DSPID                          0xFFE05000
 #define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
 #define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
 #define TBUF                           0xFFE06100 /* Trace Buffer */
diff --git a/include/asm-blackfin/mach-bf548/BF542_cdef.h b/include/asm-blackfin/mach-bf548/BF542_cdef.h
index be48dfd..306b5f1 100644
--- a/include/asm-blackfin/mach-bf548/BF542_cdef.h
+++ b/include/asm-blackfin/mach-bf548/BF542_cdef.h
@@ -310,9 +310,6 @@
 #define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pDSPID                         ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID()              bfin_read32(DSPID)
-#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
 #define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
 #define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
 #define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
diff --git a/include/asm-blackfin/mach-bf548/BF542_def.h b/include/asm-blackfin/mach-bf548/BF542_def.h
index c2be4de..40fe555 100644
--- a/include/asm-blackfin/mach-bf548/BF542_def.h
+++ b/include/asm-blackfin/mach-bf548/BF542_def.h
@@ -110,7 +110,6 @@
 #define IMASK                          0xFFE02104 /* Interrupt Mask Register */
 #define IPEND                          0xFFE02108 /* Interrupt Pending Register */
 #define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
-#define DSPID                          0xFFE05000
 #define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
 #define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
 #define TBUF                           0xFFE06100 /* Trace Buffer */
diff --git a/include/asm-blackfin/mach-bf548/BF544_cdef.h b/include/asm-blackfin/mach-bf548/BF544_cdef.h
index b3232fc..47ef6e1 100644
--- a/include/asm-blackfin/mach-bf548/BF544_cdef.h
+++ b/include/asm-blackfin/mach-bf548/BF544_cdef.h
@@ -310,9 +310,6 @@
 #define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pDSPID                         ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID()              bfin_read32(DSPID)
-#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
 #define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
 #define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
 #define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
diff --git a/include/asm-blackfin/mach-bf548/BF544_def.h b/include/asm-blackfin/mach-bf548/BF544_def.h
index 834b7a6..042e2ac 100644
--- a/include/asm-blackfin/mach-bf548/BF544_def.h
+++ b/include/asm-blackfin/mach-bf548/BF544_def.h
@@ -110,7 +110,6 @@
 #define IMASK                          0xFFE02104 /* Interrupt Mask Register */
 #define IPEND                          0xFFE02108 /* Interrupt Pending Register */
 #define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
-#define DSPID                          0xFFE05000
 #define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
 #define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
 #define TBUF                           0xFFE06100 /* Trace Buffer */
diff --git a/include/asm-blackfin/mach-bf548/BF547_cdef.h b/include/asm-blackfin/mach-bf548/BF547_cdef.h
index e1a1daf..42d041a 100644
--- a/include/asm-blackfin/mach-bf548/BF547_cdef.h
+++ b/include/asm-blackfin/mach-bf548/BF547_cdef.h
@@ -310,9 +310,6 @@
 #define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pDSPID                         ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID()              bfin_read32(DSPID)
-#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
 #define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
 #define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
 #define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
diff --git a/include/asm-blackfin/mach-bf548/BF547_def.h b/include/asm-blackfin/mach-bf548/BF547_def.h
index bb7ae5e..1cb3381 100644
--- a/include/asm-blackfin/mach-bf548/BF547_def.h
+++ b/include/asm-blackfin/mach-bf548/BF547_def.h
@@ -110,7 +110,6 @@
 #define IMASK                          0xFFE02104 /* Interrupt Mask Register */
 #define IPEND                          0xFFE02108 /* Interrupt Pending Register */
 #define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
-#define DSPID                          0xFFE05000
 #define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
 #define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
 #define TBUF                           0xFFE06100 /* Trace Buffer */
diff --git a/include/asm-blackfin/mach-bf548/BF548_cdef.h b/include/asm-blackfin/mach-bf548/BF548_cdef.h
index 6cdfbf3..cf02834 100644
--- a/include/asm-blackfin/mach-bf548/BF548_cdef.h
+++ b/include/asm-blackfin/mach-bf548/BF548_cdef.h
@@ -310,9 +310,6 @@
 #define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pDSPID                         ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID()              bfin_read32(DSPID)
-#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
 #define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
 #define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
 #define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
diff --git a/include/asm-blackfin/mach-bf548/BF548_def.h b/include/asm-blackfin/mach-bf548/BF548_def.h
index e725102..950ce43 100644
--- a/include/asm-blackfin/mach-bf548/BF548_def.h
+++ b/include/asm-blackfin/mach-bf548/BF548_def.h
@@ -110,7 +110,6 @@
 #define IMASK                          0xFFE02104 /* Interrupt Mask Register */
 #define IPEND                          0xFFE02108 /* Interrupt Pending Register */
 #define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
-#define DSPID                          0xFFE05000
 #define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
 #define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
 #define TBUF                           0xFFE06100 /* Trace Buffer */
diff --git a/include/asm-blackfin/mach-bf548/BF549_cdef.h b/include/asm-blackfin/mach-bf548/BF549_cdef.h
index 9ac8c2d..3514cef 100644
--- a/include/asm-blackfin/mach-bf548/BF549_cdef.h
+++ b/include/asm-blackfin/mach-bf548/BF549_cdef.h
@@ -310,9 +310,6 @@
 #define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pDSPID                         ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID()              bfin_read32(DSPID)
-#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
 #define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
 #define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
 #define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
diff --git a/include/asm-blackfin/mach-bf548/BF549_def.h b/include/asm-blackfin/mach-bf548/BF549_def.h
index f36ecd6..55b0a29 100644
--- a/include/asm-blackfin/mach-bf548/BF549_def.h
+++ b/include/asm-blackfin/mach-bf548/BF549_def.h
@@ -110,7 +110,6 @@
 #define IMASK                          0xFFE02104 /* Interrupt Mask Register */
 #define IPEND                          0xFFE02108 /* Interrupt Pending Register */
 #define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
-#define DSPID                          0xFFE05000
 #define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
 #define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
 #define TBUF                           0xFFE06100 /* Trace Buffer */
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
index 0451ea7..3b54309 100644
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -2,18 +2,18 @@
  * File: include/asm-blackfin/mach-bf548/anomaly.h
  * Bugs: Enter bugs at http://blackfin.uclinux.org/
  *
- * Copyright (C) 2004-2007 Analog Devices Inc.
+ * Copyright (C) 2004-2008 Analog Devices Inc.
  * Licensed under the GPL-2 or later.
  */
 
 /* This file shoule be up to date with:
- *  - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
+ *  - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
 #define _MACH_ANOMALY_H_
 
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
 #define ANOMALY_05000074 (1)
 /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
 #define ANOMALY_05000119 (1)
@@ -36,14 +36,14 @@
 /* TWI Slave Boot Mode Is Not Functional */
 #define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
 /* External FIFO Boot Mode Is Not Functional */
-#define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
+#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
 /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
 #define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
 /* Incorrect Access of OTP_STATUS During otp_write() Function */
 #define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
 /* Synchronous Burst Flash Boot Mode Is Not Functional */
 #define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
-/* Host DMA Boot Mode Is Not Functional */
+/* Host DMA Boot Modes Are Not Functional */
 #define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
 /* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
 #define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
@@ -61,26 +61,104 @@
 #define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
 /* USB Calibration Value Is Not Intialized */
 #define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
-/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
+/* USB Calibration Value to use */
+#define ANOMALY_05000346_value 0x5411
+/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
 #define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
 /* Data Lost when Core Reads SDH Data FIFO */
 #define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
 /* PLL Status Register Is Inaccurate */
 #define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
+/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
+#define ANOMALY_05000353 (__SILICON_REVISION__ < 2)
+/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
+#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
+/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
+#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
 #define ANOMALY_05000357 (1)
 /* External Memory Read Access Hangs Core With PLL Bypass */
 #define ANOMALY_05000360 (1)
 /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
 #define ANOMALY_05000365 (1)
+/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
+#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
 /* Addressing Conflict between Boot ROM and Asynchronous Memory */
 #define ANOMALY_05000369 (1)
+/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
+#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 1)
+#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
+/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
+#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
 /* Mobile DDR Operation Not Functional */
 #define ANOMALY_05000377 (1)
 /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
-#define ANOMALY_05000378 (1)
+#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
+/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
+#define ANOMALY_05000379 (1)
+/* 8-Bit NAND Flash Boot Mode Not Functional */
+#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
+/* Some ATAPI Modes Are Not Functional */
+#define ANOMALY_05000383 (1)
+/* Boot from OTP Memory Not Functional */
+#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
+/* bfrom_SysControl() Firmware Routine Not Functional */
+#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
+/* Programmable Preboot Settings Not Functional */
+#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
+/* CRC32 Checksum Support Not Functional */
+#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
+/* Reset Vector Must Not Be in SDRAM Memory Space */
+#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
+/* Changed Meaning of BCODE Field in SYSCR Register */
+#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
+/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
+#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
+/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
+/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
+/* Log Buffer Not Functional */
+#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
+/* Hook Routine Not Functional */
+#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
+/* Header Indirect Bit Not Functional */
+#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
+/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
+#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
+/* Lockbox SESR Disallows Certain User Interrupts */
+#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
+/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
+#define ANOMALY_05000405 (1)
+/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
+#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
+/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
+#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
+/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
+#define ANOMALY_05000408 (1)
+/* Lockbox firmware leaves MDMA0 channel enabled */
+#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
+/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
+#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
+/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
+#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
+/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
+#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
+#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
+/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Behaves as a Buffer Status Bit Instead of an IRQ Status Bit */
+#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
+/* Software System Reset Corrupts PLL_LOCKCNT Register */
+#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000125 (0)
@@ -93,7 +171,12 @@
 #define ANOMALY_05000263 (0)
 #define ANOMALY_05000266 (0)
 #define ANOMALY_05000273 (0)
+#define ANOMALY_05000307 (0)
 #define ANOMALY_05000311 (0)
 #define ANOMALY_05000323 (0)
+#define ANOMALY_05000363 (0)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
 
 #endif
diff --git a/include/asm-blackfin/mach-bf548/ports.h b/include/asm-blackfin/mach-bf548/ports.h
index c9bd287..5f0e45e 100644
--- a/include/asm-blackfin/mach-bf548/ports.h
+++ b/include/asm-blackfin/mach-bf548/ports.h
@@ -59,38 +59,38 @@
 #define PORT_x_MUX_7_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
 #define PORT_x_MUX_7_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
 #define PORT_x_MUX_7_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_8_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_8_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_8_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_8_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_9_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_9_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_9_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_9_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_10_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_10_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_10_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_10_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_11_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_11_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_11_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_11_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_12_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_12_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_12_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_12_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_13_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_13_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_13_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_13_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_14_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_14_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_14_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_14_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_15_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_15_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_15_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_15_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
+#define PORT_x_MUX_8_FUNC_1	(PORT_x_MUX_FUNC_1 << 16)
+#define PORT_x_MUX_8_FUNC_2	(PORT_x_MUX_FUNC_2 << 16)
+#define PORT_x_MUX_8_FUNC_3	(PORT_x_MUX_FUNC_3 << 16)
+#define PORT_x_MUX_8_FUNC_4	(PORT_x_MUX_FUNC_4 << 16)
+#define PORT_x_MUX_9_FUNC_1	(PORT_x_MUX_FUNC_1 << 18)
+#define PORT_x_MUX_9_FUNC_2	(PORT_x_MUX_FUNC_2 << 18)
+#define PORT_x_MUX_9_FUNC_3	(PORT_x_MUX_FUNC_3 << 18)
+#define PORT_x_MUX_9_FUNC_4	(PORT_x_MUX_FUNC_4 << 18)
+#define PORT_x_MUX_10_FUNC_1	(PORT_x_MUX_FUNC_1 << 20)
+#define PORT_x_MUX_10_FUNC_2	(PORT_x_MUX_FUNC_2 << 20)
+#define PORT_x_MUX_10_FUNC_3	(PORT_x_MUX_FUNC_3 << 20)
+#define PORT_x_MUX_10_FUNC_4	(PORT_x_MUX_FUNC_4 << 20)
+#define PORT_x_MUX_11_FUNC_1	(PORT_x_MUX_FUNC_1 << 22)
+#define PORT_x_MUX_11_FUNC_2	(PORT_x_MUX_FUNC_2 << 22)
+#define PORT_x_MUX_11_FUNC_3	(PORT_x_MUX_FUNC_3 << 22)
+#define PORT_x_MUX_11_FUNC_4	(PORT_x_MUX_FUNC_4 << 22)
+#define PORT_x_MUX_12_FUNC_1	(PORT_x_MUX_FUNC_1 << 24)
+#define PORT_x_MUX_12_FUNC_2	(PORT_x_MUX_FUNC_2 << 24)
+#define PORT_x_MUX_12_FUNC_3	(PORT_x_MUX_FUNC_3 << 24)
+#define PORT_x_MUX_12_FUNC_4	(PORT_x_MUX_FUNC_4 << 24)
+#define PORT_x_MUX_13_FUNC_1	(PORT_x_MUX_FUNC_1 << 26)
+#define PORT_x_MUX_13_FUNC_2	(PORT_x_MUX_FUNC_2 << 26)
+#define PORT_x_MUX_13_FUNC_3	(PORT_x_MUX_FUNC_3 << 26)
+#define PORT_x_MUX_13_FUNC_4	(PORT_x_MUX_FUNC_4 << 26)
+#define PORT_x_MUX_14_FUNC_1	(PORT_x_MUX_FUNC_1 << 28)
+#define PORT_x_MUX_14_FUNC_2	(PORT_x_MUX_FUNC_2 << 28)
+#define PORT_x_MUX_14_FUNC_3	(PORT_x_MUX_FUNC_3 << 28)
+#define PORT_x_MUX_14_FUNC_4	(PORT_x_MUX_FUNC_4 << 28)
+#define PORT_x_MUX_15_FUNC_1	(PORT_x_MUX_FUNC_1 << 30)
+#define PORT_x_MUX_15_FUNC_2	(PORT_x_MUX_FUNC_2 << 30)
+#define PORT_x_MUX_15_FUNC_3	(PORT_x_MUX_FUNC_3 << 30)
+#define PORT_x_MUX_15_FUNC_4	(PORT_x_MUX_FUNC_4 << 30)
 
 /* Port A Masks */
 #define PA0			0x0001
@@ -236,7 +236,25 @@
 #define PH14			0x4000
 #define PH15			0x8000
 
-/* Port J Masks */
+/* Port I Masks */
+#define PI0			0x0001
+#define PI1			0x0002
+#define PI2			0x0004
+#define PI3			0x0008
+#define PI4			0x0010
+#define PI5			0x0020
+#define PI6			0x0040
+#define PI7			0x0080
+#define PI8			0x0100
+#define PI9			0x0200
+#define PI10			0x0400
+#define PI11			0x0800
+#define PI12			0x1000
+#define PI13			0x2000
+#define PI14			0x4000
+#define PI15			0x8000
+
+/* Port I Masks */
 #define PJ0			0x0001
 #define PJ1			0x0002
 #define PJ2			0x0004
diff --git a/include/asm-blackfin/mach-bf561/BF561_cdef.h b/include/asm-blackfin/mach-bf561/BF561_cdef.h
index 395cd28..d8883f3 100644
--- a/include/asm-blackfin/mach-bf561/BF561_cdef.h
+++ b/include/asm-blackfin/mach-bf561/BF561_cdef.h
@@ -241,9 +241,9 @@
 #define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1)
 #define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
 #define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pSICA_SWRST                    ((uint32_t volatile *)SICA_SWRST)
-#define bfin_read_SICA_SWRST()         bfin_read32(SICA_SWRST)
-#define bfin_write_SICA_SWRST(val)     bfin_write32(SICA_SWRST, val)
+#define pSICA_SWRST                    ((uint16_t volatile *)SICA_SWRST)
+#define bfin_read_SICA_SWRST()         bfin_read16(SICA_SWRST)
+#define bfin_write_SICA_SWRST(val)     bfin_write16(SICA_SWRST, val)
 #define pSICA_SYSCR                    ((uint32_t volatile *)SICA_SYSCR)
 #define bfin_read_SICA_SYSCR()         bfin_read32(SICA_SYSCR)
 #define bfin_write_SICA_SYSCR(val)     bfin_write32(SICA_SYSCR, val)
@@ -292,9 +292,9 @@
 #define pSICA_IAR7                     ((uint32_t volatile *)SICA_IAR7)
 #define bfin_read_SICA_IAR7()          bfin_read32(SICA_IAR7)
 #define bfin_write_SICA_IAR7(val)      bfin_write32(SICA_IAR7, val)
-#define pSICB_SWRST                    ((uint32_t volatile *)SICB_SWRST)
-#define bfin_read_SICB_SWRST()         bfin_read32(SICB_SWRST)
-#define bfin_write_SICB_SWRST(val)     bfin_write32(SICB_SWRST, val)
+#define pSICB_SWRST                    ((uint16_t volatile *)SICB_SWRST)
+#define bfin_read_SICB_SWRST()         bfin_read16(SICB_SWRST)
+#define bfin_write_SICB_SWRST(val)     bfin_write16(SICB_SWRST, val)
 #define pSICB_SYSCR                    ((uint32_t volatile *)SICB_SYSCR)
 #define bfin_read_SICB_SYSCR()         bfin_read32(SICB_SYSCR)
 #define bfin_write_SICB_SYSCR(val)     bfin_write32(SICB_SYSCR, val)
@@ -400,12 +400,6 @@
 #define pEVT_OVERRIDE                  ((uint32_t volatile *)EVT_OVERRIDE)
 #define bfin_read_EVT_OVERRIDE()       bfin_read32(EVT_OVERRIDE)
 #define bfin_write_EVT_OVERRIDE(val)   bfin_write32(EVT_OVERRIDE, val)
-#define pDSPID                         ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID()              bfin_read32(DSPID)
-#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
-#define pDBGSTAT                       ((uint32_t volatile *)DBGSTAT)
-#define bfin_read_DBGSTAT()            bfin_read32(DBGSTAT)
-#define bfin_write_DBGSTAT(val)        bfin_write32(DBGSTAT, val)
 #define pUART_THR                      ((uint16_t volatile *)UART_THR)
 #define bfin_read_UART_THR()           bfin_read16(UART_THR)
 #define bfin_write_UART_THR(val)       bfin_write16(UART_THR, val)
diff --git a/include/asm-blackfin/mach-bf561/BF561_def.h b/include/asm-blackfin/mach-bf561/BF561_def.h
index 22b5bac..8534962 100644
--- a/include/asm-blackfin/mach-bf561/BF561_def.h
+++ b/include/asm-blackfin/mach-bf561/BF561_def.h
@@ -140,8 +140,6 @@
 #define SRAM_BASE_ADDR_CORE_A          0xFFE00000
 #define SRAM_BASE_ADDR_CORE_B          0xFFE00000
 #define EVT_OVERRIDE                   0xFFE02100
-#define DSPID                          0xFFE05000
-#define DBGSTAT                        0xFFE05008
 #define UART_THR                       0xFFC00400
 #define UART_RBR                       0xFFC00400
 #define UART_DLL                       0xFFC00400
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
index 0c1d461..1a9e175 100644
--- a/include/asm-blackfin/mach-bf561/anomaly.h
+++ b/include/asm-blackfin/mach-bf561/anomaly.h
@@ -2,12 +2,12 @@
  * File: include/asm-blackfin/mach-bf561/anomaly.h
  * Bugs: Enter bugs at http://blackfin.uclinux.org/
  *
- * Copyright (C) 2004-2007 Analog Devices Inc.
+ * Copyright (C) 2004-2008 Analog Devices Inc.
  * Licensed under the GPL-2 or later.
  */
 
 /* This file shoule be up to date with:
- *  - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List
+ *  - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -256,15 +256,35 @@
 #define ANOMALY_05000357 (1)
 /* Conflicting Column Address Widths Causes SDRAM Errors */
 #define ANOMALY_05000362 (1)
+/* UART Break Signal Issues */
+#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
 #define ANOMALY_05000366 (1)
 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
 #define ANOMALY_05000371 (1)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (1)
+/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
+#define ANOMALY_05000412 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
+#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000158 (0)
 #define ANOMALY_05000183 (0)
 #define ANOMALY_05000273 (0)
 #define ANOMALY_05000311 (0)
+#define ANOMALY_05000353 (1)
+#define ANOMALY_05000386 (1)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
 
 #endif
diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-core_cdef.h b/include/asm-blackfin/mach-common/ADSP-EDN-core_cdef.h
index 4ac71f6..af17813 100644
--- a/include/asm-blackfin/mach-common/ADSP-EDN-core_cdef.h
+++ b/include/asm-blackfin/mach-common/ADSP-EDN-core_cdef.h
@@ -63,5 +63,11 @@
 #define pWPSTAT                        ((uint32_t volatile *)WPSTAT)
 #define bfin_read_WPSTAT()             bfin_read32(WPSTAT)
 #define bfin_write_WPSTAT(val)         bfin_write32(WPSTAT, val)
+#define pDSPID                         ((uint32_t volatile *)DSPID)
+#define bfin_read_DSPID()              bfin_read32(DSPID)
+#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
+#define pDBGSTAT                       ((uint32_t volatile *)DBGSTAT)
+#define bfin_read_DBGSTAT()            bfin_read32(DBGSTAT)
+#define bfin_write_DBGSTAT(val)        bfin_write32(DBGSTAT, val)
 
 #endif /* __BFIN_CDEF_ADSP_EDN_core__ */
diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-core_def.h b/include/asm-blackfin/mach-common/ADSP-EDN-core_def.h
index 721af12..74f5d30 100644
--- a/include/asm-blackfin/mach-common/ADSP-EDN-core_def.h
+++ b/include/asm-blackfin/mach-common/ADSP-EDN-core_def.h
@@ -25,5 +25,7 @@
 #define WPDACNT0                       0xFFE07180
 #define WPDACNT1                       0xFFE07184
 #define WPSTAT                         0xFFE07200
+#define DSPID                          0xFFE05000
+#define DBGSTAT                        0xFFE05008
 
 #endif /* __BFIN_DEF_ADSP_EDN_core__ */
diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h b/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h
index 2f5a265..4c439e5 100644
--- a/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h
+++ b/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h
@@ -897,18 +897,15 @@
 #define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count register (16-bit) */
 #define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pSWRST                         ((uint32_t volatile *)SWRST) /* Software Reset Register (16-bit) */
-#define bfin_read_SWRST()              bfin_read32(SWRST)
-#define bfin_write_SWRST(val)          bfin_write32(SWRST, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register (16-bit) */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
 #define pSYSCR                         ((uint32_t volatile *)SYSCR) /* System Configuration register */
 #define bfin_read_SYSCR()              bfin_read32(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write32(SYSCR, val)
 #define pEVT_OVERRIDE                  ((uint32_t volatile *)EVT_OVERRIDE)
 #define bfin_read_EVT_OVERRIDE()       bfin_read32(EVT_OVERRIDE)
 #define bfin_write_EVT_OVERRIDE(val)   bfin_write32(EVT_OVERRIDE, val)
-#define pDSPID                         ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID()              bfin_read32(DSPID)
-#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
 #define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-extended_def.h b/include/asm-blackfin/mach-common/ADSP-EDN-extended_def.h
index 9190270..24b56b3 100644
--- a/include/asm-blackfin/mach-common/ADSP-EDN-extended_def.h
+++ b/include/asm-blackfin/mach-common/ADSP-EDN-extended_def.h
@@ -306,7 +306,6 @@
 #define SWRST                          0xFFC00100 /* Software Reset Register (16-bit) */
 #define SYSCR                          0xFFC00104 /* System Configuration register */
 #define EVT_OVERRIDE                   0xFFE02100
-#define DSPID                          0xFFE05000
 #define CHIPID                         0xFFC00014
 #define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
 #define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
diff --git a/include/asm-blackfin/mach-common/bits/bootrom.h b/include/asm-blackfin/mach-common/bits/bootrom.h
index 6cdaa4f..fb97ff8 100644
--- a/include/asm-blackfin/mach-common/bits/bootrom.h
+++ b/include/asm-blackfin/mach-common/bits/bootrom.h
@@ -88,27 +88,42 @@
 #define _BOOTROM_REV                   0xEF000040
 #define _BOOTROM_SESR                  0xEF001000
 
+#define BOOTROM_FOLLOWS_C_ABI 1
+
 #define BOOTROM_CAPS_ADI_BOOT_STRUCTS 1
 
-/* Not available on initial BF54x or BF52x */
-#if (defined(__ADSPBF54x__) && __SILICON_REVISION__ < 1) || \
-    (defined(__ADSPBF52x__) && __SILICON_REVISION__ < 2)
-#define BOOTROM_CAPS_SYSCONTROL 0
-#else
-#define BOOTROM_CAPS_SYSCONTROL 1
 #endif
 
+#ifndef BOOTROM_FOLLOWS_C_ABI
+#define BOOTROM_FOLLOWS_C_ABI 0
 #endif
-
 #ifndef BOOTROM_CAPS_ADI_BOOT_STRUCTS
 #define BOOTROM_CAPS_ADI_BOOT_STRUCTS 0
 #endif
-#ifndef BOOTROM_CAPS_SYSCONTROL
-#define BOOTROM_CAPS_SYSCONTROL 0
-#endif
+
+/* Possible syscontrol action flags */
+#define SYSCTRL_READ        0x00000000    /* read registers */
+#define SYSCTRL_WRITE       0x00000001    /* write registers */
+#define SYSCTRL_SYSRESET    0x00000002    /* perform system reset */
+#define SYSCTRL_CORERESET   0x00000004    /* perform core reset */
+#define SYSCTRL_SOFTRESET   0x00000006    /* perform core and system reset */
+#define SYSCTRL_VRCTL       0x00000010    /* read/write VR_CTL register */
+#define SYSCTRL_EXTVOLTAGE  0x00000020    /* VDDINT supplied externally */
+#define SYSCTRL_INTVOLTAGE  0x00000000    /* VDDINT generated by on-chip regulator */
+#define SYSCTRL_OTPVOLTAGE  0x00000040    /* For Factory Purposes Only */
+#define SYSCTRL_PLLCTL      0x00000100    /* read/write PLL_CTL register */
+#define SYSCTRL_PLLDIV      0x00000200    /* read/write PLL_DIV register */
+#define SYSCTRL_LOCKCNT     0x00000400    /* read/write PLL_LOCKCNT register */
+#define SYSCTRL_PLLSTAT     0x00000800    /* read/write PLL_STAT register */
 
 #ifndef __ASSEMBLY__
 
+#if BOOTROM_FOLLOWS_C_ABI
+# define BOOTROM_CALLED_FUNC_ATTR
+#else
+# define BOOTROM_CALLED_FUNC_ATTR __attribute__((saveall))
+#endif
+
 /* Structures for the syscontrol() function */
 typedef struct ADI_SYSCTRL_VALUES {
 	uint16_t uwVrCtl;
@@ -121,25 +136,26 @@ typedef struct ADI_SYSCTRL_VALUES {
 #ifndef _BOOTROM_SYSCONTROL
 #define _BOOTROM_SYSCONTROL 0
 #endif
-static uint32_t (* const syscontrol)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)_BOOTROM_SYSCONTROL;
-
-#endif /* __ASSEMBLY__ */
-
-/* Possible syscontrol action flags */
-#define SYSCTRL_READ        0x00000000    /* read registers */
-#define SYSCTRL_WRITE       0x00000001    /* write registers */
-#define SYSCTRL_SYSRESET    0x00000002    /* perform system reset */
-#define SYSCTRL_SOFTRESET   0x00000004    /* perform core and system reset */
-#define SYSCTRL_VRCTL       0x00000010    /* read/write VR_CTL register */
-#define SYSCTRL_EXTVOLTAGE  0x00000020    /* VDDINT supplied externally */
-#define SYSCTRL_INTVOLTAGE  0x00000000    /* VDDINT generated by on-chip regulator */
-#define SYSCTRL_OTPVOLTAGE  0x00000040    /* For Factory Purposes Only */
-#define SYSCTRL_PLLCTL      0x00000100    /* read/write PLL_CTL register */
-#define SYSCTRL_PLLDIV      0x00000200    /* read/write PLL_DIV register */
-#define SYSCTRL_LOCKCNT     0x00000400    /* read/write PLL_LOCKCNT register */
-#define SYSCTRL_PLLSTAT     0x00000800    /* read/write PLL_STAT register */
+static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)_BOOTROM_SYSCONTROL;
 
-#ifndef __ASSEMBLY__
+/* We need a dedicated function since we need to screw with the stack pointer
+ * when resetting.  The on-chip ROM will save/restore registers on the stack
+ * when doing a system reset, so the stack cannot be outside of the chip.
+ */
+__attribute__((__noreturn__))
+static inline void bfrom_SoftReset(void *new_stack)
+{
+	while (1)
+		__asm__ __volatile__(
+			"sp = %[stack];"
+			"jump (%[bfrom_syscontrol]);"
+			: : [bfrom_syscontrol] "p"(bfrom_SysControl),
+				"q0"(SYSCTRL_SOFTRESET),
+				"q1"(0),
+				"q2"(NULL),
+				[stack] "p"(new_stack)
+		);
+}
 
 /* Structures for working with LDRs and boot rom callbacks */
 typedef struct ADI_BOOT_HEADER {
diff --git a/include/asm-blackfin/mach-common/bits/ebiu.h b/include/asm-blackfin/mach-common/bits/ebiu.h
index ab530ad..7c0c569 100644
--- a/include/asm-blackfin/mach-common/bits/ebiu.h
+++ b/include/asm-blackfin/mach-common/bits/ebiu.h
@@ -357,8 +357,8 @@
 #define EBSZ_32		0x0002		/* SDRAM External Bank Size = 32MB */
 #define EBSZ_64		0x0004		/* SDRAM External Bank Size = 64MB */
 #define EBSZ_128	0x0006		/* SDRAM External Bank Size = 128MB */
-#define EBSZ_256	0x0007		/* SDRAM External Bank Size = 256MB */
-#define EBSZ_512	0x0008		/* SDRAM External Bank Size = 512MB */
+#define EBSZ_256	0x0008		/* SDRAM External Bank Size = 256MB */
+#define EBSZ_512	0x000A		/* SDRAM External Bank Size = 512MB */
 #define EBCAW_8		0x0000		/* SDRAM External Bank Column Address Width = 8 Bits */
 #define EBCAW_9		0x0010		/* SDRAM External Bank Column Address Width = 9 Bits */
 #define EBCAW_10	0x0020		/* SDRAM External Bank Column Address Width = 10 Bits */
@@ -410,12 +410,31 @@
 
 /* EBIU_SDSTAT Masks */
 #define SDCI		0x0001		/* SDRAM controller is idle */
-#define SDSRA		0x0002		/* SDRAM SDRAM self refresh is active */
+#define SDSRA		0x0002		/* SDRAM self refresh is active */
 #define SDPUA		0x0004		/* SDRAM power up active */
 #define SDRS		0x0008		/* SDRAM is in reset state */
 #define SDEASE		0x0010		/* SDRAM EAB sticky error status - W1C */
 #define BGSTAT		0x0020		/* Bus granted */
 
+/* Only available on DDR based-parts */
+#else
+
+/* EBIU_ERRMST Masks */
+#define DEB0_ERROR	0x0001		/* DEB0 access on reserved memory */
+#define DEB1_ERROR	0x0002		/* DEB1 access on reserved memory */
+#define DEB2_ERROR	0x0004		/* DEB2 (USB) access on reserved memory */
+#define CORE_ERROR	0x0008		/* Core access on reserved memory */
+#define DEB0_MERROR	0x0010		/* DEB0 access on reserved memory and DEB0_ERROR is set */
+#define DEB1_MERROR	0x0020		/* DEB1 access on reserved memory and DEB1_ERROR is set */
+#define DEB2_MERROR	0x0040		/* DEB2 access on reserved memory and DEB2_ERROR is set */
+#define CORE_MERROR	0x0080		/* Core access on reserved memory and CORE_ERROR is set */
+
+/* EBIU_RSTCTL Masks */
+#define DDR_SRESET	0x0001		/* Reset Control to DDR Controller */
+#define SRREQ		0x0008		/* Self Refresh Request */
+#define SRACK		0x0010		/* Self Refresh Request Acknowledgement */
+#define MDDRENABLE	0x0020		/* Mobile DDR Enable */
+
 #endif /* EBIU_SDGCTL */
 
 #endif
diff --git a/include/asm-blackfin/mach-common/bits/otp.h b/include/asm-blackfin/mach-common/bits/otp.h
index d529a0a..4e3f1af 100644
--- a/include/asm-blackfin/mach-common/bits/otp.h
+++ b/include/asm-blackfin/mach-common/bits/otp.h
@@ -9,23 +9,22 @@
 
 #include "bootrom.h"
 
-static uint32_t (* const otp_command)(uint32_t command, uint32_t value) = (void *)_BOOTROM_OTP_COMMAND;
-static uint32_t (* const otp_read)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_READ;
-static uint32_t (* const otp_write)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_WRITE;
+static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)_BOOTROM_OTP_COMMAND;
+static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_READ;
+static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_WRITE;
 
 #endif
 
 /* otp_command(): defines for "command" */
-#define OTP_INIT             0x00000001
-#define OTP_CLOSE            0x00000002
+#define OTP_INIT                 0x00000001
+#define OTP_CLOSE                0x00000002
 
 /* otp_{read,write}(): defines for "flags" */
-#define OTP_LOWER_HALF       0x00000000 /* select upper/lower 64-bit half (bit 0) */
-#define OTP_UPPER_HALF       0x00000001
-#define OTP_NO_ECC           0x00000010 /* do not use ECC */
-#define OTP_LOCK             0x00000020 /* sets page protection bit for page */
-#define OTP_ACCESS_READ      0x00001000
-#define OTP_ACCESS_READWRITE 0x00002000
+#define OTP_LOWER_HALF           0x00000000 /* select upper/lower 64-bit half (bit 0) */
+#define OTP_UPPER_HALF           0x00000001
+#define OTP_NO_ECC               0x00000010 /* do not use ECC */
+#define OTP_LOCK                 0x00000020 /* sets page protection bit for page */
+#define OTP_CHECK_FOR_PREV_WRITE 0x00000080
 
 /* Return values for all functions */
 #define OTP_SUCCESS          0x00000000
diff --git a/include/asm-blackfin/mach-common/bits/pata.h b/include/asm-blackfin/mach-common/bits/pata.h
new file mode 100644
index 0000000..9b61824
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/pata.h
@@ -0,0 +1,220 @@
+/*
+ * ATAPI Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PATA__
+#define __BFIN_PERIPHERAL_PATA__
+
+/* Bit masks for ATAPI_CONTROL */
+#define                 PIO_START  0x1        /* Start PIO/Reg Op */
+#define               MULTI_START  0x2        /* Start Multi-DMA Op */
+#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
+#define                  XFER_DIR  0x8        /* Transfer Direction */
+#define                  IORDY_EN  0x10       /* IORDY Enable */
+#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
+#define                  SOFT_RST  0x40       /* Soft Reset */
+#define                   DEV_RST  0x80       /* Device Reset */
+#define                TFRCNT_RST  0x100      /* Trans Count Reset */
+#define               END_ON_TERM  0x200      /* End/Terminate Select */
+#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
+#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
+
+/* Bit masks for ATAPI_STATUS */
+#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
+#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
+#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
+#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
+
+/* Bit masks for ATAPI_DEV_ADDR */
+#define                  DEV_ADDR  0x1f       /* Device Address */
+
+/* Bit masks for ATAPI_INT_MASK */
+#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
+#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
+#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
+#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
+#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
+#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
+#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
+#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
+#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
+
+/* Bit masks for ATAPI_INT_STATUS */
+#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
+#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
+#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
+#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
+#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
+#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
+#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
+#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
+#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
+
+/* Bit masks for ATAPI_LINE_STATUS */
+#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
+#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
+#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
+#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
+#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
+#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
+#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
+#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
+#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
+#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
+
+/* Bit masks for ATAPI_SM_STATE */
+#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
+#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
+#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
+#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
+
+/* Bit masks for ATAPI_TERMINATE */
+#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
+
+/* Bit masks for ATAPI_REG_TIM_0 */
+#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
+#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
+
+/* Bit masks for ATAPI_PIO_TIM_0 */
+#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
+#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
+#define                    T4_REG  0xf000     /* DIOW data hold */
+
+/* Bit masks for ATAPI_PIO_TIM_1 */
+#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
+
+/* Bit masks for ATAPI_MULTI_TIM_0 */
+#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
+#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
+
+/* Bit masks for ATAPI_MULTI_TIM_1 */
+#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
+#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
+
+/* Bit masks for ATAPI_MULTI_TIM_2 */
+#define                        TH  0xff       /* Selects DIOW data hold */
+#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
+
+/* Bit masks for ATAPI_ULTRA_TIM_0 */
+#define                      TACK  0xff       /* Selects setup and hold times for TACK */
+#define                      TENV  0xff00     /* Selects envelope time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_1 */
+#define                      TDVS  0xff       /* Selects data valid setup time */
+#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_2 */
+#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
+#define                      TMLI  0xff00     /* Selects interlock time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_3 */
+#define                      TZAH  0xff       /* Selects minimum delay required for output */
+#define               READY_PAUSE  0xff00     /* Selects ready to pause */
+
+/* Bit masks for ATAPI_CONTROL */
+#define                 PIO_START  0x1        /* Start PIO/Reg Op */
+#define               MULTI_START  0x2        /* Start Multi-DMA Op */
+#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
+#define                  XFER_DIR  0x8        /* Transfer Direction */
+#define                  IORDY_EN  0x10       /* IORDY Enable */
+#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
+#define                  SOFT_RST  0x40       /* Soft Reset */
+#define                   DEV_RST  0x80       /* Device Reset */
+#define                TFRCNT_RST  0x100      /* Trans Count Reset */
+#define               END_ON_TERM  0x200      /* End/Terminate Select */
+#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
+#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
+
+/* Bit masks for ATAPI_STATUS */
+#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
+#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
+#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
+#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
+
+/* Bit masks for ATAPI_DEV_ADDR */
+#define                  DEV_ADDR  0x1f       /* Device Address */
+
+/* Bit masks for ATAPI_INT_MASK */
+#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
+#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
+#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
+#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
+#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
+#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
+#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
+#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
+#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
+
+/* Bit masks for ATAPI_INT_STATUS */
+#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
+#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
+#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
+#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
+#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
+#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
+#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
+#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
+#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
+
+/* Bit masks for ATAPI_LINE_STATUS */
+#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
+#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
+#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
+#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
+#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
+#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
+#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
+#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
+#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
+#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
+
+/* Bit masks for ATAPI_SM_STATE */
+#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
+#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
+#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
+#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
+
+/* Bit masks for ATAPI_TERMINATE */
+#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
+
+/* Bit masks for ATAPI_REG_TIM_0 */
+#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
+#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
+
+/* Bit masks for ATAPI_PIO_TIM_0 */
+#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
+#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
+#define                    T4_REG  0xf000     /* DIOW data hold */
+
+/* Bit masks for ATAPI_PIO_TIM_1 */
+#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
+
+/* Bit masks for ATAPI_MULTI_TIM_0 */
+#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
+#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
+
+/* Bit masks for ATAPI_MULTI_TIM_1 */
+#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
+#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
+
+/* Bit masks for ATAPI_MULTI_TIM_2 */
+#define                        TH  0xff       /* Selects DIOW data hold */
+#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
+
+/* Bit masks for ATAPI_ULTRA_TIM_0 */
+#define                      TACK  0xff       /* Selects setup and hold times for TACK */
+#define                      TENV  0xff00     /* Selects envelope time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_1 */
+#define                      TDVS  0xff       /* Selects data valid setup time */
+#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_2 */
+#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
+#define                      TMLI  0xff00     /* Selects interlock time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_3 */
+#define                      TZAH  0xff       /* Selects minimum delay required for output */
+#define               READY_PAUSE  0xff00     /* Selects ready to pause */
+
+#endif /* __BFIN_PERIPHERAL_PATA__ */
diff --git a/include/asm-blackfin/mach-common/bits/sdh.h b/include/asm-blackfin/mach-common/bits/sdh.h
new file mode 100644
index 0000000..8c5dd33
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/sdh.h
@@ -0,0 +1,122 @@
+/*
+ * SDH Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_SDH__
+#define __BFIN_PERIPHERAL_SDH__
+
+/* Bit masks for SDH_COMMAND */
+#define                   CMD_IDX  0x3f       /* Command Index */
+#define                   CMD_RSP  0x40       /* Response */
+#define                 CMD_L_RSP  0x80       /* Long Response */
+#define                 CMD_INT_E  0x100      /* Command Interrupt */
+#define                CMD_PEND_E  0x200      /* Command Pending */
+#define                     CMD_E  0x400      /* Command Enable */
+
+/* Bit masks for SDH_PWR_CTL */
+#define                    PWR_ON  0x3        /* Power On */
+#define                 SD_CMD_OD  0x40       /* Open Drain Output */
+#define                   ROD_CTL  0x80       /* Rod Control */
+
+/* Bit masks for SDH_CLK_CTL */
+#define                    CLKDIV  0xff       /* MC_CLK Divisor */
+#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
+#define                  PWR_SV_E  0x200      /* Power Save Enable */
+#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
+#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
+
+/* Bit masks for SDH_RESP_CMD */
+#define                  RESP_CMD  0x3f       /* Response Command */
+
+/* Bit masks for SDH_DATA_CTL */
+#define                     DTX_E  0x1        /* Data Transfer Enable */
+#define                   DTX_DIR  0x2        /* Data Transfer Direction */
+#define                  DTX_MODE  0x4        /* Data Transfer Mode */
+#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
+#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
+
+/* Bit masks for SDH_STATUS */
+#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
+#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
+#define              CMD_TIME_OUT  0x4        /* CMD Time Out */
+#define              DAT_TIME_OUT  0x8        /* Data Time Out */
+#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
+#define                RX_OVERRUN  0x20       /* Receive Overrun */
+#define              CMD_RESP_END  0x40       /* CMD Response End */
+#define                  CMD_SENT  0x80       /* CMD Sent */
+#define                   DAT_END  0x100      /* Data End */
+#define             START_BIT_ERR  0x200      /* Start Bit Error */
+#define               DAT_BLK_END  0x400      /* Data Block End */
+#define                   CMD_ACT  0x800      /* CMD Active */
+#define                    TX_ACT  0x1000     /* Transmit Active */
+#define                    RX_ACT  0x2000     /* Receive Active */
+#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
+#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
+#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
+#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
+#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
+#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
+#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
+#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
+
+/* Bit masks for SDH_STATUS_CLR */
+#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
+#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
+#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
+#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
+#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
+#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
+#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
+#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
+#define              DAT_END_STAT  0x100      /* Data End Status */
+#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
+#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
+
+/* Bit masks for SDH_MASK0 */
+#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
+#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
+#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
+#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
+#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
+#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
+#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
+#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
+#define              DAT_END_MASK  0x100      /* Data End Mask */
+#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
+#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
+#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
+#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
+#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
+#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
+#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
+#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
+#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
+#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
+#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
+#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
+#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
+
+/* Bit masks for SDH_FIFO_CNT */
+#define                FIFO_COUNT  0x7fff     /* FIFO Count */
+
+/* Bit masks for SDH_E_STATUS */
+#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
+#define               SD_CARD_DET  0x10       /* SD Card Detect */
+
+/* Bit masks for SDH_E_MASK */
+#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
+#define                   SCD_MSK  0x40       /* Mask Card Detect */
+
+/* Bit masks for SDH_CFG */
+#define                   CLKS_EN  0x1        /* Clocks Enable */
+#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
+#define                       MWE  0x8        /* Moving Window Enable */
+#define                    SD_RST  0x10       /* SDMMC Reset */
+#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
+#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
+#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
+
+/* Bit masks for SDH_RD_WAIT_EN */
+#define                       RWR  0x1        /* Read Wait Request */
+
+#endif
diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h
deleted file mode 100644
index cb448ad..0000000
--- a/include/asm-blackfin/mem_init.h
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * U-boot - mem_init.h Header file for memory initialization
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75 || \
-	CONFIG_MEM_MT48LC64M4A2FB_7E || \
-	CONFIG_MEM_MT48LC16M8A2TG_75 || \
-	CONFIG_MEM_MT48LC8M16A2TG_7E || \
-	CONFIG_MEM_MT48LC8M32B2B5_7  || \
-	CONFIG_MEM_MT48LC32M8A2_75)
-
-	#if ( CONFIG_SCLK_HZ > 119402985 )
-		#define SDRAM_tRP	TRP_2
-		#define SDRAM_tRP_num	2
-		#define SDRAM_tRAS	TRAS_7
-		#define SDRAM_tRAS_num	7
-		#define SDRAM_tRCD	TRCD_2
-		#define SDRAM_tWR	TWR_2
-	#endif
-	#if ( CONFIG_SCLK_HZ > 104477612 ) && ( CONFIG_SCLK_HZ <= 119402985 )
-		#define SDRAM_tRP	TRP_2
-		#define SDRAM_tRP_num	2
-		#define SDRAM_tRAS	TRAS_6
-		#define SDRAM_tRAS_num	6
-		#define SDRAM_tRCD	TRCD_2
-		#define SDRAM_tWR	TWR_2
-	#endif
-	#if ( CONFIG_SCLK_HZ >  89552239 ) && ( CONFIG_SCLK_HZ <= 104477612 )
-		#define SDRAM_tRP	TRP_2
-		#define SDRAM_tRP_num	2
-		#define SDRAM_tRAS	TRAS_5
-		#define SDRAM_tRAS_num	5
-		#define SDRAM_tRCD	TRCD_2
-		#define SDRAM_tWR	TWR_2
-	#endif
-	#if ( CONFIG_SCLK_HZ >  74626866 ) && ( CONFIG_SCLK_HZ <=  89552239 )
-		#define SDRAM_tRP	TRP_2
-		#define SDRAM_tRP_num	2
-		#define SDRAM_tRAS	TRAS_4
-		#define SDRAM_tRAS_num	4
-		#define SDRAM_tRCD	TRCD_2
-		#define SDRAM_tWR	TWR_2
-	#endif
-	#if ( CONFIG_SCLK_HZ >  66666667 ) && ( CONFIG_SCLK_HZ <= 74626866 )
-		#define SDRAM_tRP	TRP_2
-		#define SDRAM_tRP_num	2
-		#define SDRAM_tRAS	TRAS_3
-		#define SDRAM_tRAS_num	3
-		#define SDRAM_tRCD	TRCD_2
-		#define SDRAM_tWR	TWR_2
-	#endif
-	#if ( CONFIG_SCLK_HZ >  59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 )
-		#define SDRAM_tRP	TRP_1
-		#define SDRAM_tRP_num	1
-		#define SDRAM_tRAS	TRAS_3
-		#define SDRAM_tRAS_num	3
-		#define SDRAM_tRCD	TRCD_1
-		#define SDRAM_tWR	TWR_2
-	#endif
-	#if ( CONFIG_SCLK_HZ >  44776119 ) && ( CONFIG_SCLK_HZ <=  59701493 )
-		#define SDRAM_tRP	TRP_1
-		#define SDRAM_tRP_num	1
-		#define SDRAM_tRAS	TRAS_3
-		#define SDRAM_tRAS_num	3
-		#define SDRAM_tRCD	TRCD_1
-		#define SDRAM_tWR	TWR_2
-	#endif
-	#if ( CONFIG_SCLK_HZ >  29850746 ) && ( CONFIG_SCLK_HZ <=  44776119 )
-		#define SDRAM_tRP	TRP_1
-		#define SDRAM_tRP_num	1
-		#define SDRAM_tRAS	TRAS_2
-		#define SDRAM_tRAS_num	2
-		#define SDRAM_tRCD	TRCD_1
-		#define SDRAM_tWR	TWR_2
-	#endif
-	#if ( CONFIG_SCLK_HZ <=  29850746 )
-		#define SDRAM_tRP	TRP_1
-		#define SDRAM_tRP_num	1
-		#define SDRAM_tRAS	TRAS_1
-		#define SDRAM_tRAS_num	1
-		#define SDRAM_tRCD	TRCD_1
-		#define SDRAM_tWR	TWR_2
-	#endif
-#endif
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75)
-	/*SDRAM INFORMATION: */
-	#define SDRAM_Tref	64	/* Refresh period in milliseconds   */
-	#define SDRAM_NRA	8192	/* Number of row addresses in SDRAM */
-	#define SDRAM_CL	CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
-	/*SDRAM INFORMATION: */
-	#define SDRAM_Tref	64	/* Refresh period in milliseconds   */
-	#define SDRAM_NRA	8192	/* Number of row addresses in SDRAM */
-	#define SDRAM_CL	CL_2
-#endif
-
-#if (CONFIG_MEM_MT48LC16M8A2TG_75)
-	/*SDRAM INFORMATION: */
-	#define SDRAM_Tref      64	/* Refresh period in milliseconds   */
-	#define SDRAM_NRA       4096	/* Number of row addresses in SDRAM */
-	#define SDRAM_CL        CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC32M8A2_75)
-/*SDRAM INFORMATION: */
-#define SDRAM_Tref  64			/* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192		/* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC8M16A2TG_7E)
-	/*SDRAM INFORMATION: */
-	#define SDRAM_Tref	64	/* Refresh period in milliseconds   */
-	#define SDRAM_NRA	4096	/* Number of row addresses in SDRAM */
-	#define SDRAM_CL	CL_2
-#endif
-
-#if (CONFIG_MEM_MT48LC8M32B2B5_7)
-	/*SDRAM INFORMATION: */
-	#define SDRAM_Tref	64	/* Refresh period in milliseconds   */
-	#define SDRAM_NRA	4096	/* Number of row addresses in SDRAM */
-	#define SDRAM_CL	CL_3
-#endif
-
-#if ( CONFIG_MEM_SIZE == 128 )
-	#define SDRAM_SIZE	EBSZ_128
-#endif
-#if ( CONFIG_MEM_SIZE == 64 )
-	#define SDRAM_SIZE	EBSZ_64
-#endif
-#if (  CONFIG_MEM_SIZE == 32 )
-	#define SDRAM_SIZE	EBSZ_32
-#endif
-#if ( CONFIG_MEM_SIZE == 16 )
-	#define SDRAM_SIZE	EBSZ_16
-#endif
-#if ( CONFIG_MEM_ADD_WDTH == 11 )
-	#define SDRAM_WIDTH	EBCAW_11
-#endif
-#if ( CONFIG_MEM_ADD_WDTH == 10 )
-	#define SDRAM_WIDTH	EBCAW_10
-#endif
-#if ( CONFIG_MEM_ADD_WDTH == 9 )
-	#define SDRAM_WIDTH	EBCAW_9
-#endif
-#if ( CONFIG_MEM_ADD_WDTH == 8 )
-	#define SDRAM_WIDTH	EBCAW_8
-#endif
-
-#define mem_SDBCTL	SDRAM_WIDTH | SDRAM_SIZE | EBE
-
-/* Equation from section 17 (p17-46) of BF533 HRM */
-#define mem_SDRRC	((( CONFIG_SCLK_HZ / 1000) * SDRAM_Tref)  / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
-
-/* Enable SCLK Out */
-#define mem_SDGCTL	( SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS )
-
-#define flash_EBIU_AMBCTL_WAT	( ( CONFIG_FLASH_SPEED_BWAT * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
-#define flash_EBIU_AMBCTL_RAT	( ( CONFIG_FLASH_SPEED_BRAT * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
-#define flash_EBIU_AMBCTL_HT	( ( CONFIG_FLASH_SPEED_BHT  * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) )
-#define flash_EBIU_AMBCTL_ST	( ( CONFIG_FLASH_SPEED_BST  * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
-#define flash_EBIU_AMBCTL_TT	( ( CONFIG_FLASH_SPEED_BTT  * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
-
-#if (flash_EBIU_AMBCTL_TT > 3 )
-	#define flash_EBIU_AMBCTL0_TT	B0TT_4
-#endif
-#if (flash_EBIU_AMBCTL_TT == 3 )
-	#define flash_EBIU_AMBCTL0_TT	B0TT_3
-#endif
-#if (flash_EBIU_AMBCTL_TT == 2 )
-	#define flash_EBIU_AMBCTL0_TT	B0TT_2
-#endif
-#if (flash_EBIU_AMBCTL_TT < 2 )
-	#define flash_EBIU_AMBCTL0_TT	B0TT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_ST > 3 )
-	#define flash_EBIU_AMBCTL0_ST	B0ST_4
-#endif
-#if (flash_EBIU_AMBCTL_ST == 3 )
-	#define flash_EBIU_AMBCTL0_ST	B0ST_3
-#endif
-#if (flash_EBIU_AMBCTL_ST == 2 )
-	#define flash_EBIU_AMBCTL0_ST	B0ST_2
-#endif
-#if (flash_EBIU_AMBCTL_ST < 2 )
-	#define flash_EBIU_AMBCTL0_ST	B0ST_1
-#endif
-
-#if (flash_EBIU_AMBCTL_HT > 2 )
-	#define flash_EBIU_AMBCTL0_HT	B0HT_3
-#endif
-#if (flash_EBIU_AMBCTL_HT == 2 )
-	#define flash_EBIU_AMBCTL0_HT	B0HT_2
-#endif
-#if (flash_EBIU_AMBCTL_HT == 1 )
-	#define flash_EBIU_AMBCTL0_HT	B0HT_1
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0  && CONFIG_FLASH_SPEED_BHT == 0)
-	#define flash_EBIU_AMBCTL0_HT	B0HT_0
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0  && CONFIG_FLASH_SPEED_BHT != 0)
-	#define flash_EBIU_AMBCTL0_HT	B0HT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_WAT > 14)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_15
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 14)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_14
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 13)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_13
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 12)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_12
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 11)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_11
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 10)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_10
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 9)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_9
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 8)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_8
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 7)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_7
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 6)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_6
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 5)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_5
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 4)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_4
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 3)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_3
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 2)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_2
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 1)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_RAT > 14)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_15
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 14)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_14
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 13)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_13
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 12)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_12
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 11)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_11
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 10)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_10
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 9)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_9
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 8)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_8
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 7)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_7
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 6)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_6
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 5)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_5
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 4)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_4
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 3)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_3
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 2)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_2
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 1)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_1
-#endif
-
-#define flash_EBIU_AMBCTL0	flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN
diff --git a/include/asm-blackfin/mmc.h b/include/asm-blackfin/mmc.h
new file mode 100644
index 0000000..aa2ac95
--- /dev/null
+++ b/include/asm-blackfin/mmc.h
@@ -0,0 +1 @@
+#include <asm-avr32/arch-at32ap700x/mmc.h>
diff --git a/include/asm-blackfin/posix_types.h b/include/asm-blackfin/posix_types.h
index 39651d2..000ffe5 100644
--- a/include/asm-blackfin/posix_types.h
+++ b/include/asm-blackfin/posix_types.h
@@ -40,15 +40,17 @@ typedef unsigned short __kernel_mode_t;
 typedef unsigned short __kernel_nlink_t;
 typedef long __kernel_off_t;
 typedef int __kernel_pid_t;
-typedef unsigned short __kernel_ipc_pid_t;
-typedef unsigned short __kernel_uid_t;
-typedef unsigned short __kernel_gid_t;
-typedef unsigned int __kernel_size_t;
-typedef int __kernel_ssize_t;
+typedef unsigned int __kernel_ipc_pid_t;
+typedef unsigned int __kernel_uid_t;
+typedef unsigned int __kernel_gid_t;
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
 typedef int __kernel_ptrdiff_t;
 typedef long __kernel_time_t;
 typedef long __kernel_suseconds_t;
 typedef long __kernel_clock_t;
+typedef int __kernel_timer_t;
+typedef int __kernel_clockid_t;
 typedef int __kernel_daddr_t;
 typedef char *__kernel_caddr_t;
 typedef unsigned short __kernel_uid16_t;
@@ -67,14 +69,10 @@ typedef long long __kernel_loff_t;
 #endif
 
 typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
 	int val[2];
-#else				/* !defined(__KERNEL__) && !defined(__USE_ALL) */
-	int __val[2];
-#endif				/* !defined(__KERNEL__) && !defined(__USE_ALL) */
 } __kernel_fsid_t;
 
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+#if defined(__KERNEL__)
 
 #undef	__FD_SET
 #define	__FD_SET(d, set)	((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
@@ -88,6 +86,6 @@ typedef struct {
 #undef	__FD_ZERO
 #define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
 
-#endif	/* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif				/* defined(__KERNEL__) */
 
 #endif
diff --git a/include/asm-i386/config.h b/include/asm-i386/config.h
new file mode 100644
index 0000000..049c44e
--- /dev/null
+++ b/include/asm-i386/config.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
diff --git a/include/asm-i386/global_data.h b/include/asm-i386/global_data.h
index cc30689..3abbf1d 100644
--- a/include/asm-i386/global_data.h
+++ b/include/asm-i386/global_data.h
@@ -30,7 +30,7 @@
  * global variables during system initialization (until we have set
  * up the memory controller so that we can use RAM).
  *
- * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
  */
 
 typedef	struct {
diff --git a/include/asm-i386/ic/pci.h b/include/asm-i386/ic/pci.h
new file mode 100644
index 0000000..bcccdbe
--- /dev/null
+++ b/include/asm-i386/ic/pci.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_IC_SC520_PCI_H_
+#define _ASM_IC_SC520_PCI_H_ 1
+
+/* pin number used for PCI interrupt mappings */
+#define SC520_PCI_INTA 0
+#define SC520_PCI_INTB 1
+#define SC520_PCI_INTC 2
+#define SC520_PCI_INTD 3
+#define SC520_PCI_GPIRQ0 4
+#define SC520_PCI_GPIRQ1 5
+#define SC520_PCI_GPIRQ2 6
+#define SC520_PCI_GPIRQ3 7
+#define SC520_PCI_GPIRQ4 8
+#define SC520_PCI_GPIRQ5 9
+#define SC520_PCI_GPIRQ6 10
+#define SC520_PCI_GPIRQ7 11
+#define SC520_PCI_GPIRQ8 12
+#define SC520_PCI_GPIRQ9 13
+#define SC520_PCI_GPIRQ10 14
+
+extern int sc520_pci_ints[];
+
+void pci_sc520_init(struct pci_controller *hose);
+int pci_sc520_set_irq(int pci_pin, int irq);
+
+#endif
diff --git a/include/asm-i386/ic/sc520.h b/include/asm-i386/ic/sc520.h
index 0f7e7a5..bf39516 100644
--- a/include/asm-i386/ic/sc520.h
+++ b/include/asm-i386/ic/sc520.h
@@ -282,24 +282,6 @@
 #define SC520_IRQ14 9
 #define SC520_IRQ15 10
 
-
-/* pin number used for PCI interrupt mappings */
-#define SC520_PCI_INTA 0
-#define SC520_PCI_INTB 1
-#define SC520_PCI_INTC 2
-#define SC520_PCI_INTD 3
-#define SC520_PCI_GPIRQ0 4
-#define SC520_PCI_GPIRQ1 5
-#define SC520_PCI_GPIRQ2 6
-#define SC520_PCI_GPIRQ3 7
-#define SC520_PCI_GPIRQ4 8
-#define SC520_PCI_GPIRQ5 9
-#define SC520_PCI_GPIRQ6 10
-#define SC520_PCI_GPIRQ7 11
-#define SC520_PCI_GPIRQ8 12
-#define SC520_PCI_GPIRQ9 13
-#define SC520_PCI_GPIRQ10 14
-
 /* utility functions */
 void write_mmcr_byte(u16 mmcr, u8 data);
 void write_mmcr_word(u16 mmcr, u16 data);
@@ -308,11 +290,7 @@ u8 read_mmcr_byte(u16 mmcr);
 u16 read_mmcr_word(u16 mmcr);
 u32 read_mmcr_long(u16 mmcr);
 
-extern int sc520_pci_ints[];
-
 void init_sc520(void);
 unsigned long init_sc520_dram(void);
-void pci_sc520_init(struct pci_controller *hose);
-int pci_sc520_set_irq(int pci_pin, int irq);
 
 #endif
diff --git a/include/asm-i386/interrupt.h b/include/asm-i386/interrupt.h
new file mode 100644
index 0000000..315b400
--- /dev/null
+++ b/include/asm-i386/interrupt.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_INTERRUPT_H_
+#define __ASM_INTERRUPT_H_ 1
+
+void set_vector(int intnum, void *routine);
+
+#endif
diff --git a/include/asm-i386/io.h b/include/asm-i386/io.h
index 2c57140..9b757d4 100644
--- a/include/asm-i386/io.h
+++ b/include/asm-i386/io.h
@@ -229,4 +229,9 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
 
 }
 
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
 #endif
diff --git a/include/asm-m68k/coldfire/ata.h b/include/asm-m68k/coldfire/ata.h
new file mode 100644
index 0000000..3efd03a
--- /dev/null
+++ b/include/asm-m68k/coldfire/ata.h
@@ -0,0 +1,79 @@
+/*
+ * ATA Internal Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ATA_H__
+#define __ATA_H__
+
+/* ATA */
+typedef struct atac {
+	/* PIO */
+	u8 toff;		/* 0x00 */
+	u8 ton;			/* 0x01 */
+	u8 t1;			/* 0x02 */
+	u8 t2w;			/* 0x03 */
+	u8 t2r;			/* 0x04 */
+	u8 ta;			/* 0x05 */
+	u8 trd;			/* 0x06 */
+	u8 t4;			/* 0x07 */
+	u8 t9;			/* 0x08 */
+
+	/* DMA */
+	u8 tm;			/* 0x09 */
+	u8 tn;			/* 0x0A */
+	u8 td;			/* 0x0B */
+	u8 tk;			/* 0x0C */
+	u8 tack;		/* 0x0D */
+	u8 tenv;		/* 0x0E */
+	u8 trp;			/* 0x0F */
+	u8 tzah;		/* 0x10 */
+	u8 tmli;		/* 0x11 */
+	u8 tdvh;		/* 0x12 */
+	u8 tdzfs;		/* 0x13 */
+	u8 tdvs;		/* 0x14 */
+	u8 tcvh;		/* 0x15 */
+	u8 tss;			/* 0x16 */
+	u8 tcyc;		/* 0x17 */
+
+	/* FIFO */
+	u32 fifo32;		/* 0x18 */
+	u16 fifo16;		/* 0x1C */
+	u8 rsvd0[2];
+	u8 ffill;		/* 0x20 */
+	u8 rsvd1[3];
+
+	/* ATA */
+	u8 cr;			/* 0x24 */
+	u8 rsvd2[3];
+	u8 isr;			/* 0x28 */
+	u8 rsvd3[3];
+	u8 ier;			/* 0x2C */
+	u8 rsvd4[3];
+	u8 icr;			/* 0x30 */
+	u8 rsvd5[3];
+	u8 falarm;		/* 0x34 */
+	u8 rsvd6[106];
+} atac_t;
+
+#endif				/* __ATA_H__ */
diff --git a/include/asm-m68k/coldfire/dspi.h b/include/asm-m68k/coldfire/dspi.h
index 8327e1b..4b7d61e 100644
--- a/include/asm-m68k/coldfire/dspi.h
+++ b/include/asm-m68k/coldfire/dspi.h
@@ -46,15 +46,14 @@ typedef struct dspi {
 	u32 dirsr;
 	u32 dtfr;
 	u32 drfr;
-	u32 dtfdr0;
-	u32 dtfdr1;
-	u32 dtfdr2;
-	u32 dtfdr3;
+#ifdef CONFIG_MCF547x_8x
+	u32 dtfdr[4];
 	u8 resv1[0x30];
-	u32 drfdr0;
-	u32 drfdr1;
-	u32 drfdr2;
-	u32 drfdr3;
+	u32 drfdr[4];
+#else
+	u32 dtfdr[16];
+	u32 drfdr[16];
+#endif
 } dspi_t;
 
 /* Bit definitions and macros for DMCR */
diff --git a/include/asm-m68k/coldfire/eport.h b/include/asm-m68k/coldfire/eport.h
new file mode 100644
index 0000000..1d1bf63
--- /dev/null
+++ b/include/asm-m68k/coldfire/eport.h
@@ -0,0 +1,139 @@
+/*
+ * Edge Port Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EPORT_H__
+#define __EPORT_H__
+
+/* Edge Port Module (EPORT) */
+typedef struct eport {
+#ifdef CONFIG_MCF547x_8x
+	u16 par;	/* 0x00 */
+	u16 res0;	/* 0x02 */
+	u8 ddr;		/* 0x04 */
+	u8 ier;		/* 0x05 */
+	u16 res1;	/* 0x06 */
+	u8 dr;		/* 0x08 */
+	u8 pdr;		/* 0x09 */
+	u16 res2;	/* 0x0A */
+	u8 fr;		/* 0x0C */
+	u8 res3[3];	/* 0x0D */
+#else
+	u16 par;	/* 0x00 Pin Assignment */
+	u8 ddr;		/* 0x02 Data Direction */
+	u8 ier;		/* 0x03 Interrupt Enable */
+	u8 dr;		/* 0x04 Data */
+	u8 pdr;		/* 0x05 Pin Data */
+	u8 fr;		/* 0x06 Flag */
+	u8 res0;
+#endif
+} eport_t;
+
+/* EPPAR */
+#define EPORT_PAR_EPPA1(x)		(((x)&0x0003)<<2)
+#define EPORT_PAR_EPPA2(x)		(((x)&0x0003)<<4)
+#define EPORT_PAR_EPPA3(x)		(((x)&0x0003)<<6)
+#define EPORT_PAR_EPPA4(x)		(((x)&0x0003)<<8)
+#define EPORT_PAR_EPPA5(x)		(((x)&0x0003)<<10)
+#define EPORT_PAR_EPPA6(x)		(((x)&0x0003)<<12)
+#define EPORT_PAR_EPPA7(x)		(((x)&0x0003)<<14)
+#define EPORT_PAR_LEVEL			(0)
+#define EPORT_PAR_RISING		(1)
+#define EPORT_PAR_FALLING		(2)
+#define EPORT_PAR_BOTH			(3)
+#define EPORT_PAR_EPPA7_LEVEL		(0x0000)
+#define EPORT_PAR_EPPA7_RISING		(0x4000)
+#define EPORT_PAR_EPPA7_FALLING		(0x8000)
+#define EPORT_PAR_EPPA7_BOTH		(0xC000)
+#define EPORT_PAR_EPPA6_LEVEL		(0x0000)
+#define EPORT_PAR_EPPA6_RISING		(0x1000)
+#define EPORT_PAR_EPPA6_FALLING		(0x2000)
+#define EPORT_PAR_EPPA6_BOTH		(0x3000)
+#define EPORT_PAR_EPPA5_LEVEL		(0x0000)
+#define EPORT_PAR_EPPA5_RISING		(0x0400)
+#define EPORT_PAR_EPPA5_FALLING		(0x0800)
+#define EPORT_PAR_EPPA5_BOTH		(0x0C00)
+#define EPORT_PAR_EPPA4_LEVEL		(0x0000)
+#define EPORT_PAR_EPPA4_RISING		(0x0100)
+#define EPORT_PAR_EPPA4_FALLING		(0x0200)
+#define EPORT_PAR_EPPA4_BOTH		(0x0300)
+#define EPORT_PAR_EPPA3_LEVEL		(0x0000)
+#define EPORT_PAR_EPPA3_RISING		(0x0040)
+#define EPORT_PAR_EPPA3_FALLING		(0x0080)
+#define EPORT_PAR_EPPA3_BOTH		(0x00C0)
+#define EPORT_PAR_EPPA2_LEVEL		(0x0000)
+#define EPORT_PAR_EPPA2_RISING		(0x0010)
+#define EPORT_PAR_EPPA2_FALLING		(0x0020)
+#define EPORT_PAR_EPPA2_BOTH		(0x0030)
+#define EPORT_PAR_EPPA1_LEVEL		(0x0000)
+#define EPORT_PAR_EPPA1_RISING		(0x0004)
+#define EPORT_PAR_EPPA1_FALLING		(0x0008)
+#define EPORT_PAR_EPPA1_BOTH		(0x000C)
+
+/* EPDDR */
+#define EPORT_DDR_EPDD1			(0x02)
+#define EPORT_DDR_EPDD2			(0x04)
+#define EPORT_DDR_EPDD3			(0x08)
+#define EPORT_DDR_EPDD4			(0x10)
+#define EPORT_DDR_EPDD5			(0x20)
+#define EPORT_DDR_EPDD6			(0x40)
+#define EPORT_DDR_EPDD7			(0x80)
+
+/* EPIER */
+#define EPORT_IER_EPIE1			(0x02)
+#define EPORT_IER_EPIE2			(0x04)
+#define EPORT_IER_EPIE3			(0x08)
+#define EPORT_IER_EPIE4			(0x10)
+#define EPORT_IER_EPIE5			(0x20)
+#define EPORT_IER_EPIE6			(0x40)
+#define EPORT_IER_EPIE7			(0x80)
+
+/* EPDR */
+#define EPORT_DR_EPD1			(0x02)
+#define EPORT_DR_EPD2			(0x04)
+#define EPORT_DR_EPD3			(0x08)
+#define EPORT_DR_EPD4			(0x10)
+#define EPORT_DR_EPD5			(0x20)
+#define EPORT_DR_EPD6			(0x40)
+#define EPORT_DR_EPD7			(0x80)
+
+/* EPPDR */
+#define EPORT_PDR_EPPD1			(0x02)
+#define EPORT_PDR_EPPD2			(0x04)
+#define EPORT_PDR_EPPD3			(0x08)
+#define EPORT_PDR_EPPD4			(0x10)
+#define EPORT_PDR_EPPD5			(0x20)
+#define EPORT_PDR_EPPD6			(0x40)
+#define EPORT_PDR_EPPD7			(0x80)
+
+/* EPFR */
+#define EPORT_FR_EPF1			(0x02)
+#define EPORT_FR_EPF2			(0x04)
+#define EPORT_FR_EPF3			(0x08)
+#define EPORT_FR_EPF4			(0x10)
+#define EPORT_FR_EPF5			(0x20)
+#define EPORT_FR_EPF6			(0x40)
+#define EPORT_FR_EPF7			(0x80)
+
+#endif				/* __EPORT_H__ */
diff --git a/include/asm-m68k/coldfire/flexbus.h b/include/asm-m68k/coldfire/flexbus.h
index 1d902c0..51cbbd8 100644
--- a/include/asm-m68k/coldfire/flexbus.h
+++ b/include/asm-m68k/coldfire/flexbus.h
@@ -31,33 +31,36 @@
 *********************************************************************/
 
 typedef struct fbcs {
-	u32 csar0;		/* Chip-select Address Register */
-	u32 csmr0;		/* Chip-select Mask Register */
-	u32 cscr0;		/* Chip-select Control Register */
-	u32 csar1;		/* Chip-select Address Register */
-	u32 csmr1;		/* Chip-select Mask Register */
-	u32 cscr1;		/* Chip-select Control Register */
-	u32 csar2;		/* Chip-select Address Register */
-	u32 csmr2;		/* Chip-select Mask Register */
-	u32 cscr2;		/* Chip-select Control Register */
-	u32 csar3;		/* Chip-select Address Register */
-	u32 csmr3;		/* Chip-select Mask Register */
-	u32 cscr3;		/* Chip-select Control Register */
-	u32 csar4;		/* Chip-select Address Register */
-	u32 csmr4;		/* Chip-select Mask Register */
-	u32 cscr4;		/* Chip-select Control Register */
-	u32 csar5;		/* Chip-select Address Register */
-	u32 csmr5;		/* Chip-select Mask Register */
-	u32 cscr5;		/* Chip-select Control Register */
+	u32 csar0;		/* Chip-select Address */
+	u32 csmr0;		/* Chip-select Mask */
+	u32 cscr0;		/* Chip-select Control */
+	u32 csar1;
+	u32 csmr1;
+	u32 cscr1;
+	u32 csar2;
+	u32 csmr2;
+	u32 cscr2;
+	u32 csar3;
+	u32 csmr3;
+	u32 cscr3;
+	u32 csar4;
+	u32 csmr4;
+	u32 cscr4;
+	u32 csar5;
+	u32 csmr5;
+	u32 cscr5;
+	u32 csar6;
+	u32 csmr6;
+	u32 cscr6;
+	u32 csar7;
+	u32 csmr7;
+	u32 cscr7;
 } fbcs_t;
 
-/* Bit definitions and macros for CSAR group */
-#define FBCS_CSAR_BA(x)			((x)&0xFFFF0000)
+#define FBCS_CSAR_BA(x)			((x) & 0xFFFF0000)
 
-/* Bit definitions and macros for CSMR group */
-#define FBCS_CSMR_V			(0x00000001)	/* Valid bit */
-#define FBCS_CSMR_WP			(0x00000100)	/* Write protect */
-#define FBCS_CSMR_BAM(x)		(((x)&0x0000FFFF)<<16)	/* Base address mask */
+#define FBCS_CSMR_BAM(x)		(((x) & 0xFFFF) << 16)
+#define FBCS_CSMR_BAM_MASK		(0x0000FFFF)
 #define FBCS_CSMR_BAM_4G		(0xFFFF0000)
 #define FBCS_CSMR_BAM_2G		(0x7FFF0000)
 #define FBCS_CSMR_BAM_1G		(0x3FFF0000)
@@ -78,21 +81,40 @@ typedef struct fbcs {
 #define FBCS_CSMR_BAM_128K		(0x00010000)
 #define FBCS_CSMR_BAM_64K		(0x00000000)
 
-/* Bit definitions and macros for CSCR group */
-#define FBCS_CSCR_BSTW			(0x00000008)	/* Burst-write enable */
-#define FBCS_CSCR_BSTR			(0x00000010)	/* Burst-read enable */
-#define FBCS_CSCR_BEM			(0x00000020)	/* Byte-enable mode */
-#define FBCS_CSCR_PS(x)			(((x)&0x00000003)<<6)	/* Port size */
-#define FBCS_CSCR_AA			(0x00000100)	/* Auto-acknowledge */
-#define FBCS_CSCR_WS(x)			(((x)&0x0000003F)<<10)	/* Wait states */
-#define FBCS_CSCR_WRAH(x)		(((x)&0x00000003)<<16)	/* Write address hold or deselect */
-#define FBCS_CSCR_RDAH(x)		(((x)&0x00000003)<<18)	/* Read address hold or deselect */
-#define FBCS_CSCR_ASET(x)		(((x)&0x00000003)<<20)	/* Address setup */
-#define FBCS_CSCR_SWSEN			(0x00800000)	/* Secondary wait state enable */
-#define FBCS_CSCR_SWS(x)		(((x)&0x0000003F)<<26)	/* Secondary wait states */
+#ifdef CONFIG_M5249
+#define FBCS_CSMR_WP			(0x00000080)
+#define FBCS_CSMR_AM			(0x00000040)
+#define FBCS_CSMR_CI			(0x00000020)
+#define FBCS_CSMR_SC			(0x00000010)
+#define FBCS_CSMR_SD			(0x00000008)
+#define FBCS_CSMR_UC			(0x00000004)
+#define FBCS_CSMR_UD			(0x00000002)
+#else
+#define FBCS_CSMR_WP			(0x00000100)
+#endif
+#define FBCS_CSMR_V			(0x00000001)	/* Valid bit */
+
+#define FBCS_CSCR_SWS(x)		(((x) & 0x3F) << 26)
+#define FBCS_CSCR_SWS_MASK		(0x03FFFFFF)
+#define FBCS_CSCR_SWSEN			(0x00800000)
+#define FBCS_CSCR_ASET(x)		(((x) & 0x03) << 20)
+#define FBCS_CSCR_ASET_MASK		(0xFFCFFFFF)
+#define FBCS_CSCR_RDAH(x)		(((x) & 0x03) << 18)
+#define FBCS_CSCR_RDAH_MASK		(0xFFF3FFFF)
+#define FBCS_CSCR_WRAH(x)		(((x) & 0x03) << 16)
+#define FBCS_CSCR_WRAH_MASK		(0xFFFCFFFF)
+#define FBCS_CSCR_WS(x)			(((x) & 0x3F) << 10)
+#define FBCS_CSCR_WS_MASK		(0xFFFF03FF)
+#define FBCS_CSCR_SBM			(0x00000200)
+#define FBCS_CSCR_AA			(0x00000100)
+#define FBCS_CSCR_PS(x)			(((x) & 0x03) << 6)
+#define FBCS_CSCR_PS_MASK		(0xFFFFFF3F)
+#define FBCS_CSCR_BEM			(0x00000020)
+#define FBCS_CSCR_BSTR			(0x00000010)
+#define FBCS_CSCR_BSTW			(0x00000008)
 
-#define FBCS_CSCR_PS_8			(0x00000040)
 #define FBCS_CSCR_PS_16			(0x00000080)
+#define FBCS_CSCR_PS_8			(0x00000040)
 #define FBCS_CSCR_PS_32			(0x00000000)
 
 #endif				/* __FLEXBUS_H */
diff --git a/include/asm-m68k/coldfire/flexcan.h b/include/asm-m68k/coldfire/flexcan.h
new file mode 100644
index 0000000..cafd44f
--- /dev/null
+++ b/include/asm-m68k/coldfire/flexcan.h
@@ -0,0 +1,219 @@
+/*
+ * Flex CAN Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FLEXCAN_H__
+#define __FLEXCAN_H__
+
+/* FlexCan Message Buffer */
+typedef struct can_msgbuf_ctrl {
+#ifdef CONFIG_M5282
+	u8 tmstamp;		/* 0x00 Timestamp */
+	u8 ctrl;		/* 0x01 Control */
+	u16 idh;		/* 0x02 ID High */
+	u16 idl;		/* 0x04 ID High */
+	u8 data[8];		/* 0x06 8 Byte Data Field */
+	u16 res;		/* 0x0E */
+#else
+	u16 ctrl;		/* 0x00 Control/Status */
+	u16 tmstamp;		/* 0x02 Timestamp */
+	u32 id;			/* 0x04 Identifier */
+	u8 data[8];		/* 0x08 8 Byte Data Field */
+#endif
+} can_msg_t;
+
+#ifdef CONFIG_M5282
+/* MSGBUF CTRL */
+#define CAN_MSGBUF_CTRL_CODE(x)		(((x) & 0x0F) << 4)
+#define CAN_MSGBUF_CTRL_CODE_MASK	(0x0F)
+#define CAN_MSGBUF_CTRL_LEN(x)		((x) & 0x0F)
+#define CAN_MSGBUF_CTRL_LEN_MASK	(0xF0)
+
+/* MSGBUF ID */
+#define CAN_MSGBUF_IDH_STD(x)		(((x) & 0x07FF) << 5)
+#define CAN_MSGBUF_IDH_STD_MASK		(0xE003FFFF)
+#define CAN_MSGBUF_IDH_SRR		(0x0010)
+#define CAN_MSGBUF_IDH_IDE		(0x0080)
+#define CAN_MSGBUF_IDH_EXTH(x)		((x) & 0x07)
+#define CAN_MSGBUF_IDH_EXTH_MASK	(0xFFF8)
+#define CAN_MSGBUF_IDL_EXTL(x)		(((x) & 0x7FFF) << 1)
+#define CAN_MSGBUF_IDL_EXTL_MASK		(0xFFFE)
+#define CAN_MSGBUF_IDL_RTR		(0x0001)
+#else
+/* MSGBUF CTRL */
+#define CAN_MSGBUF_CTRL_CODE(x)		(((x) & 0x000F) << 8)
+#define CAN_MSGBUF_CTRL_CODE_MASK	(0xF0FF)
+#define CAN_MSGBUF_CTRL_SRR		(0x0040)
+#define CAN_MSGBUF_CTRL_IDE		(0x0020)
+#define CAN_MSGBUF_CTRL_RTR		(0x0010)
+#define CAN_MSGBUF_CTRL_LEN(x)		((x) & 0x000F)
+#define CAN_MSGBUF_CTRL_LEN_MASK	(0xFFF0)
+
+/* MSGBUF ID */
+#define CAN_MSGBUF_ID_STD(x)		(((x) & 0x000007FF) << 18)
+#define CAN_MSGBUF_ID_STD_MASK		(0xE003FFFF)
+#define CAN_MSGBUF_ID_EXT(x)		((x) & 0x0003FFFF)
+#define CAN_MSGBUF_ID_EXT_MASK		(0xFFFC0000)
+#endif
+
+/* FlexCan module */
+typedef struct can_ctrl {
+	u32 mcr;		/* 0x00 Module Configuration */
+	u32 ctrl;		/* 0x04 Control */
+	u32 timer;		/* 0x08 Free Running Timer */
+	u32 res1;		/* 0x0C */
+	u32 rxgmsk;		/* 0x10 Rx Global Mask */
+	u32 rx14msk;		/* 0x14 RxBuffer 14 Mask */
+	u32 rx15msk;		/* 0x18 RxBuffer 15 Mask */
+#ifdef CONFIG_M5282
+	u32 res2;		/* 0x1C */
+	u16 errstat;		/* 0x20 Error and status */
+	u16 imsk;		/* 0x22 Interrupt Mask */
+	u16 iflag;		/* 0x24 Interrupt Flag */
+	u16 errcnt;		/* 0x26 Error Counter */
+	u32 res3[3];		/* 0x28 - 0x33 */
+#else
+	u16 res2;		/* 0x1C */
+	u16 errcnt;		/* 0x1E Error Counter */
+	u16 res3;		/* 0x20 */
+	u16 errstat;		/* 0x22 Error and status */
+	u32 res4;		/* 0x24 */
+	u32 imsk;		/* 0x28 Interrupt Mask */
+	u32 res5;		/* 0x2C */
+	u16 iflag;		/* 0x30 Interrupt Flag */
+#endif
+	u32 res6[19];		/* 0x34 - 0x7F */
+	void *msgbuf;		/* 0x80 Message Buffer 0-15 */
+} can_t;
+
+/* MCR */
+#define CAN_MCR_MDIS			(0x80000000)
+#define CAN_MCR_FRZ			(0x40000000)
+#define CAN_MCR_HALT			(0x10000000)
+#define CAN_MCR_NORDY			(0x08000000)
+#define CAN_MCF_WAKEMSK			(0x04000000)	/* 5282 */
+#define CAN_MCR_SOFTRST			(0x02000000)
+#define CAN_MCR_FRZACK			(0x01000000)
+#define CAN_MCR_SUPV			(0x00800000)
+#define CAN_MCR_SELFWAKE		(0x00400000)	/* 5282 */
+#define CAN_MCR_APS			(0x00200000)	/* 5282 */
+#define CAN_MCR_LPMACK			(0x00100000)
+#define CAN_MCF_BCC			(0x00010000)
+#define CAN_MCR_MAXMB(x)		((x) & 0x0F)
+#define CAN_MCR_MAXMB_MASK		(0xFFFFFFF0)
+
+/* CTRL */
+#define CAN_CTRL_PRESDIV(x)		(((x) & 0xFF) << 24)
+#define CAN_CTRL_PRESDIV_MASK		(0x00FFFFFF)
+#define CAN_CTRL_RJW(x)			(((x) & 0x03) << 22)
+#define CAN_CTRL_RJW_MASK		(0xFF3FFFFF)
+#define CAN_CTRL_PSEG1(x)		(((x) & 0x07) << 19)
+#define CAN_CTRL_PSEG1_MASK		(0xFFC7FFFF)
+#define CAN_CTRL_PSEG2(x)		(((x) & 0x07) << 16)
+#define CAN_CTRL_PSEG2_MASK		(0xFFF8FFFF)
+#define CAN_CTRL_BOFFMSK		(0x00008000)
+#define CAN_CTRL_ERRMSK			(0x00004000)
+#define CAN_CTRL_CLKSRC			(0x00002000)
+#define CAN_CTRL_LPB			(0x00001000)
+#define CAN_CTRL_RXMODE			(0x00000400)	/* 5282 */
+#define CAN_CTRL_TXMODE(x)		(((x) & 0x03) << 8)	/* 5282 */
+#define CAN_CTRL_TXMODE_MASK		(0xFFFFFCFF)	/* 5282 */
+#define CAN_CTRL_TXMODE_CAN0		(0x00000000)	/* 5282 */
+#define CAN_CTRL_TXMODE_CAN1		(0x00000100)	/* 5282 */
+#define CAN_CTRL_TXMODE_OPEN		(0x00000200)	/* 5282 */
+#define CAN_CTRL_SMP			(0x00000080)
+#define CAN_CTRL_BOFFREC		(0x00000040)
+#define CAN_CTRL_TSYNC			(0x00000020)
+#define CAN_CTRL_LBUF			(0x00000010)
+#define CAN_CTRL_LOM			(0x00000008)
+#define CAN_CTRL_PROPSEG(x)		((x) & 0x07)
+#define CAN_CTRL_PROPSEG_MASK		(0xFFFFFFF8)
+
+/* TIMER */
+/* Note: PRESDIV, RJW, PSG1, and PSG2 are part of timer in 5282 */
+#define CAN_TIMER(x)			((x) & 0xFFFF)
+#define CAN_TIMER_MASK			(0xFFFF0000)
+
+/* RXGMASK */
+#ifdef CONFIG_M5282
+#define CAN_RXGMSK_MI_STD(x)		(((x) & 0x000007FF) << 21)
+#define CAN_RXGMSK_MI_STD_MASK		(0x001FFFFF)
+#define CAN_RXGMSK_MI_EXT(x)		(((x) & 0x0003FFFF) << 1)
+#define CAN_RXGMSK_MI_EXT_MASK		(0xFFF80001)
+#else
+#define CAN_RXGMSK_MI_STD(x)		(((x) & 0x000007FF) << 18)
+#define CAN_RXGMSK_MI_STD_MASK		(0xE003FFFF)
+#define CAN_RXGMSK_MI_EXT(x)		((x) & 0x0003FFFF)
+#define CAN_RXGMSK_MI_EXT_MASK		(0xFFFC0000)
+#endif
+
+/* ERRCNT */
+#define CAN_ERRCNT_RXECTR(x)		(((x) & 0xFF) << 8)
+#define CAN_ERRCNT_RXECTR_MASK		(0x00FF)
+#define CAN_ERRCNT_TXECTR(x)		((x) & 0xFF)
+#define CAN_ERRCNT_TXECTR_MASK		(0xFF00)
+
+/* ERRSTAT */
+#define CAN_ERRSTAT_BITERR1		(0x8000)
+#define CAN_ERRSTAT_BITERR0		(0x4000)
+#define CAN_ERRSTAT_ACKERR		(0x2000)
+#define CAN_ERRSTAT_CRCERR		(0x1000)
+#define CAN_ERRSTAT_FRMERR		(0x0800)
+#define CAN_ERRSTAT_STFERR		(0x0400)
+#define CAN_ERRSTAT_TXWRN		(0x0200)
+#define CAN_ERRSTAT_RXWRN		(0x0100)
+#define CAN_ERRSTAT_IDLE		(0x0080)
+#define CAN_ERRSTAT_TXRX		(0x0040)
+#define CAN_ERRSTAT_FLT_MASK		(0xFFCF)
+#define CAN_ERRSTAT_FLT_BUSOFF		(0x0020)
+#define CAN_ERRSTAT_FLT_PASSIVE		(0x0010)
+#define CAN_ERRSTAT_FLT_ACTIVE		(0x0000)
+#ifdef CONFIG_M5282
+#define CAN_ERRSTAT_BOFFINT		(0x0004)
+#define CAN_ERRSTAT_ERRINT		(0x0002)
+#else
+#define CAN_ERRSTAT_ERRINT		(0x0004)
+#define CAN_ERRSTAT_BOFFINT		(0x0002)
+#define CAN_ERRSTAT_WAKEINT		(0x0001)
+#endif
+
+/* IMASK */
+#ifdef CONFIG_M5253
+#define CAN_IMASK_BUFnM(x)		(1 << (x & 0xFFFFFFFF))
+#define CAN_IMASK_BUFnM_MASKBIT(x)	~CAN_IMASK_BUFnM(x)
+#else
+#define CAN_IMASK_BUFnM(x)		(1 << (x & 0xFFFF))
+#define CAN_IMASK_BUFnM_MASKBIT(x)	~CAN_IMASK_BUFnM(x)
+#endif
+
+/* IFLAG */
+#ifdef CONFIG_M5253
+#define CAN_IFLAG_BUFnM(x)		(1 << (x & 0xFFFFFFFF))
+#define CAN_IFLAG_BUFnM_MASKBIT(x)	~CAN_IFLAG_BUFnM(x)
+#else
+#define CAN_IFLAG_BUFnM(x)		(1 << (x & 0xFFFF))
+#define CAN_IFLAG_BUFnM_MASKBIT(x)	~CAN_IFLAG_BUFnM(x)
+#endif
+
+#endif				/* __FLEXCAN_H__ */
diff --git a/include/asm-m68k/coldfire/intctrl.h b/include/asm-m68k/coldfire/intctrl.h
new file mode 100644
index 0000000..ae82b29
--- /dev/null
+++ b/include/asm-m68k/coldfire/intctrl.h
@@ -0,0 +1,246 @@
+/*
+ * Interrupt Controller Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __INTCTRL_H__
+#define __INTCTRL_H__
+
+#if defined(CONFIG_M5235) || defined(CONFIG_M5271) || \
+    defined(CONFIG_M5275) || defined(CONFIG_M5282) || \
+    defined(CONFIG_M547x) || defined(CONFIG_M548x)
+#	define	CONFIG_SYS_CF_INTC_REG1
+#endif
+
+typedef struct int0_ctrl {
+	/* Interrupt Controller 0 */
+	u32 iprh0;		/* 0x00 Pending High */
+	u32 iprl0;		/* 0x04 Pending Low */
+	u32 imrh0;		/* 0x08 Mask High */
+	u32 imrl0;		/* 0x0C Mask Low */
+	u32 frch0;		/* 0x10 Force High */
+	u32 frcl0;		/* 0x14 Force Low */
+#if defined(CONFIG_SYS_CF_INTC_REG1)
+	u8 irlr;		/* 0x18 */
+	u8 iacklpr;		/* 0x19 */
+	u16 res1[19];		/* 0x1a - 0x3c */
+#else
+	u16 res1;		/* 0x18 - 0x19 */
+	u16 icfg0;		/* 0x1A Configuration */
+	u8 simr0;		/* 0x1C Set Interrupt Mask */
+	u8 cimr0;		/* 0x1D Clear Interrupt Mask */
+	u8 clmask0;		/* 0x1E Current Level Mask */
+	u8 slmask;		/* 0x1F Saved Level Mask */
+	u32 res2[8];		/* 0x20 - 0x3F */
+#endif
+	u8 icr0[64];		/* 0x40 - 0x7F Control registers */
+	u32 res3[24];		/* 0x80 - 0xDF */
+	u8 swiack0;		/* 0xE0 Software Interrupt ack */
+	u8 res4[3];		/* 0xE1 - 0xE3 */
+	u8 L1iack0;		/* 0xE4 Level n interrupt ack */
+	u8 res5[3];		/* 0xE5 - 0xE7 */
+	u8 L2iack0;		/* 0xE8 Level n interrupt ack */
+	u8 res6[3];		/* 0xE9 - 0xEB */
+	u8 L3iack0;		/* 0xEC Level n interrupt ack */
+	u8 res7[3];		/* 0xED - 0xEF */
+	u8 L4iack0;		/* 0xF0 Level n interrupt ack */
+	u8 res8[3];		/* 0xF1 - 0xF3 */
+	u8 L5iack0;		/* 0xF4 Level n interrupt ack */
+	u8 res9[3];		/* 0xF5 - 0xF7 */
+	u8 L6iack0;		/* 0xF8 Level n interrupt ack */
+	u8 resa[3];		/* 0xF9 - 0xFB */
+	u8 L7iack0;		/* 0xFC Level n interrupt ack */
+	u8 resb[3];		/* 0xFD - 0xFF */
+} int0_t;
+
+typedef struct int1_ctrl {
+	/* Interrupt Controller 1 */
+	u32 iprh1;		/* 0x00 Pending High */
+	u32 iprl1;		/* 0x04 Pending Low */
+	u32 imrh1;		/* 0x08 Mask High */
+	u32 imrl1;		/* 0x0C Mask Low */
+	u32 frch1;		/* 0x10 Force High */
+	u32 frcl1;		/* 0x14 Force Low */
+#if defined(CONFIG_SYS_CF_INTC_REG1)
+	u8 irlr;		/* 0x18 */
+	u8 iacklpr;		/* 0x19 */
+	u16 res1[19];		/* 0x1a - 0x3c */
+#else
+	u16 res1;		/* 0x18 */
+	u16 icfg1;		/* 0x1A Configuration */
+	u8 simr1;		/* 0x1C Set Interrupt Mask */
+	u8 cimr1;		/* 0x1D Clear Interrupt Mask */
+	u16 res2;		/* 0x1E - 0x1F */
+	u32 res3[8];		/* 0x20 - 0x3F */
+#endif
+	u8 icr1[64];		/* 0x40 - 0x7F */
+	u32 res4[24];		/* 0x80 - 0xDF */
+	u8 swiack1;		/* 0xE0 Software Interrupt ack */
+	u8 res5[3];		/* 0xE1 - 0xE3 */
+	u8 L1iack1;		/* 0xE4 Level n interrupt ack */
+	u8 res6[3];		/* 0xE5 - 0xE7 */
+	u8 L2iack1;		/* 0xE8 Level n interrupt ack */
+	u8 res7[3];		/* 0xE9 - 0xEB */
+	u8 L3iack1;		/* 0xEC Level n interrupt ack */
+	u8 res8[3];		/* 0xED - 0xEF */
+	u8 L4iack1;		/* 0xF0 Level n interrupt ack */
+	u8 res9[3];		/* 0xF1 - 0xF3 */
+	u8 L5iack1;		/* 0xF4 Level n interrupt ack */
+	u8 resa[3];		/* 0xF5 - 0xF7 */
+	u8 L6iack1;		/* 0xF8 Level n interrupt ack */
+	u8 resb[3];		/* 0xF9 - 0xFB */
+	u8 L7iack1;		/* 0xFC Level n interrupt ack */
+	u8 resc[3];		/* 0xFD - 0xFF */
+} int1_t;
+
+typedef struct intgack_ctrl1 {
+	/* Global IACK Registers */
+	u8 swiack;		/* 0x00 Global Software Interrupt ack */
+	u8 res0[0x3];
+	u8 gl1iack;		/* 0x04 */
+	u8 resv1[0x3];
+	u8 gl2iack;		/* 0x08 */
+	u8 res2[0x3];
+	u8 gl3iack;		/* 0x0C */
+	u8 res3[0x3];
+	u8 gl4iack;		/* 0x10 */
+	u8 res4[0x3];
+	u8 gl5iack;		/* 0x14 */
+	u8 res5[0x3];
+	u8 gl6iack;		/* 0x18 */
+	u8 res6[0x3];
+	u8 gl7iack;		/* 0x1C */
+	u8 res7[0x3];
+} intgack_t;
+
+#define INTC_IPRH_INT63			(0x80000000)
+#define INTC_IPRH_INT62			(0x40000000)
+#define INTC_IPRH_INT61			(0x20000000)
+#define INTC_IPRH_INT60			(0x10000000)
+#define INTC_IPRH_INT59			(0x08000000)
+#define INTC_IPRH_INT58			(0x04000000)
+#define INTC_IPRH_INT57			(0x02000000)
+#define INTC_IPRH_INT56			(0x01000000)
+#define INTC_IPRH_INT55			(0x00800000)
+#define INTC_IPRH_INT54			(0x00400000)
+#define INTC_IPRH_INT53			(0x00200000)
+#define INTC_IPRH_INT52			(0x00100000)
+#define INTC_IPRH_INT51			(0x00080000)
+#define INTC_IPRH_INT50			(0x00040000)
+#define INTC_IPRH_INT49			(0x00020000)
+#define INTC_IPRH_INT48			(0x00010000)
+#define INTC_IPRH_INT47			(0x00008000)
+#define INTC_IPRH_INT46			(0x00004000)
+#define INTC_IPRH_INT45			(0x00002000)
+#define INTC_IPRH_INT44			(0x00001000)
+#define INTC_IPRH_INT43			(0x00000800)
+#define INTC_IPRH_INT42			(0x00000400)
+#define INTC_IPRH_INT41			(0x00000200)
+#define INTC_IPRH_INT40			(0x00000100)
+#define INTC_IPRH_INT39			(0x00000080)
+#define INTC_IPRH_INT38			(0x00000040)
+#define INTC_IPRH_INT37			(0x00000020)
+#define INTC_IPRH_INT36			(0x00000010)
+#define INTC_IPRH_INT35			(0x00000008)
+#define INTC_IPRH_INT34			(0x00000004)
+#define INTC_IPRH_INT33			(0x00000002)
+#define INTC_IPRH_INT32			(0x00000001)
+
+#define INTC_IPRL_INT31			(0x80000000)
+#define INTC_IPRL_INT30			(0x40000000)
+#define INTC_IPRL_INT29			(0x20000000)
+#define INTC_IPRL_INT28			(0x10000000)
+#define INTC_IPRL_INT27			(0x08000000)
+#define INTC_IPRL_INT26			(0x04000000)
+#define INTC_IPRL_INT25			(0x02000000)
+#define INTC_IPRL_INT24			(0x01000000)
+#define INTC_IPRL_INT23			(0x00800000)
+#define INTC_IPRL_INT22			(0x00400000)
+#define INTC_IPRL_INT21			(0x00200000)
+#define INTC_IPRL_INT20			(0x00100000)
+#define INTC_IPRL_INT19			(0x00080000)
+#define INTC_IPRL_INT18			(0x00040000)
+#define INTC_IPRL_INT17			(0x00020000)
+#define INTC_IPRL_INT16			(0x00010000)
+#define INTC_IPRL_INT15			(0x00008000)
+#define INTC_IPRL_INT14			(0x00004000)
+#define INTC_IPRL_INT13			(0x00002000)
+#define INTC_IPRL_INT12			(0x00001000)
+#define INTC_IPRL_INT11			(0x00000800)
+#define INTC_IPRL_INT10			(0x00000400)
+#define INTC_IPRL_INT9			(0x00000200)
+#define INTC_IPRL_INT8			(0x00000100)
+#define INTC_IPRL_INT7			(0x00000080)
+#define INTC_IPRL_INT6			(0x00000040)
+#define INTC_IPRL_INT5			(0x00000020)
+#define INTC_IPRL_INT4			(0x00000010)
+#define INTC_IPRL_INT3			(0x00000008)
+#define INTC_IPRL_INT2			(0x00000004)
+#define INTC_IPRL_INT1			(0x00000002)
+#define INTC_IPRL_INT0			(0x00000001)
+
+#define INTC_IMRLn_MASKALL		(0x00000001)
+
+#define INTC_IRLR(x)			(((x) & 0x7F) << 1)
+#define INTC_IRLR_MASK			(0x01)
+
+#define INTC_IACKLPR_LVL(x)		(((x) & 0x07) << 4)
+#define INTC_IACKLPR_LVL_MASK		(0x8F)
+#define INTC_IACKLPR_PRI(x)		((x) & 0x0F)
+#define INTC_IACKLPR_PRI_MASK		(0xF0)
+
+#if defined(CONFIG_SYS_CF_INTC_REG1)
+#define INTC_ICR_IL(x)			(((x) & 0x07) << 3)
+#define INTC_ICR_IL_MASK		(0xC7)
+#define INTC_ICR_IP(x)			((x) & 0x07)
+#define INTC_ICR_IP_MASK		(0xF8)
+#else
+#define INTC_ICR_IL(x)			((x) & 0x07)
+#define INTC_ICR_IL_MASK		(0xF8)
+#endif
+
+#define INTC_ICONFIG_ELVLPRI_MASK	(0x01FF)
+#define INTC_ICONFIG_ELVLPRI7		(0x8000)
+#define INTC_ICONFIG_ELVLPRI6		(0x4000)
+#define INTC_ICONFIG_ELVLPRI5		(0x2000)
+#define INTC_ICONFIG_ELVLPRI4		(0x1000)
+#define INTC_ICONFIG_ELVLPRI3		(0x0800)
+#define INTC_ICONFIG_ELVLPRI2		(0x0400)
+#define INTC_ICONFIG_ELVLPRI1		(0x0200)
+#define INTC_ICONFIG_EMASK		(0x0020)
+
+#define INTC_SIMR_ALL			(0x40)
+#define INTC_SIMR(x)			((x) & 0x3F)
+#define INTC_SIMR_MASK			(0x80)
+
+#define INTC_CIMR_ALL			(0x40)
+#define INTC_CIMR(x)			((x) & 0x3F)
+#define INTC_CIMR_MASK			(0x80)
+
+#define INTC_CLMASK(x)			((x) & 0x0F)
+#define INTC_CLMASK_MASK		(0xF0)
+
+#define INTC_SLMASK(x)			((x) & 0x0F)
+#define INTC_SLMASK_MASK		(0xF0)
+
+#endif				/* __INTCTRL_H__ */
diff --git a/include/asm-m68k/coldfire/mdha.h b/include/asm-m68k/coldfire/mdha.h
new file mode 100644
index 0000000..b6981363
--- /dev/null
+++ b/include/asm-m68k/coldfire/mdha.h
@@ -0,0 +1,102 @@
+/*
+ * Message Digest Hardware Accelerator Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MDHA_H__
+#define __MDHA_H__
+
+/* Message Digest Hardware Accelerator */
+typedef struct mdha_ctrl {
+	u32 mr;			/* 0x00 MDHA Mode */
+	u32 cr;			/* 0x04 Control */
+	u32 cmd;		/* 0x08 Command */
+	u32 sr;			/* 0x0C Status */
+	u32 isr;		/* 0x10 Interrupt Status */
+	u32 imr;		/* 0x14 Interrupt Mask */
+	u32 dsz;		/* 0x1C Data Size */
+	u32 inp;		/* 0x20 Input FIFO */
+	u32 res1[3];		/* 0x24 - 0x2F */
+	u32 mda0;		/* 0x30 Message Digest AO */
+	u32 mdb0;		/* 0x34 Message Digest BO */
+	u32 mdc0;		/* 0x38 Message Digest CO */
+	u32 mdd0;		/* 0x3C Message Digest DO */
+	u32 mde0;		/* 0x40 Message Digest EO */
+	u32 mdsz;		/* 0x44 Message Data Size */
+	u32 res[10];		/* 0x48 - 0x6F */
+	u32 mda1;		/* 0x70 Message Digest A1 */
+	u32 mdb1;		/* 0x74 Message Digest B1 */
+	u32 mdc1;		/* 0x78 Message Digest C1 */
+	u32 mdd1;		/* 0x7C Message Digest D1 */
+	u32 mde1;		/* 0x80 Message Digest E1 */
+} mdha_t;
+
+#define MDHA_MR_SSL		(0x00000400)
+#define MDHA_MR_MACFUL		(0x00000200)
+#define MDHA_MR_SWAP		(0x00000100)
+#define MDHA_MR_OPAD		(0x00000080)
+#define MDHA_MR_IPAD		(0x00000040)
+#define MDHA_MR_INIT		(0x00000020)
+#define MDHA_MR_MAC(x)		(((x) & 0x03) << 3)
+#define MDHA_MR_MAC_MASK	(0xFFFFFFE7)
+#define MDHA_MR_MAC_EHMAC	(0x00000010)
+#define MDHA_MR_MAC_HMAC	(0x00000008)
+#define MDHA_MR_MAC_NONE	(0x00000000)
+#define MDHA_MR_PDATA		(0x00000004)
+#define MDHA_MR_ALG		(0x00000001)
+
+#define MDHA_CR_DMAL(x)		(((x) & 0x1F) << 16)	/* 532x */
+#define MDHA_CR_DMAL_MASK	(0xFFE0FFFF)		/* 532x */
+#define MDHA_CR_END		(0x00000004)		/* 532x */
+#define MDHA_CR_DMA		(0x00000002)		/* 532x */
+#define MDHA_CR_IE		(0x00000001)
+
+#define MDHA_CMD_GO		(0x00000008)
+#define MDHA_CMD_CI		(0x00000004)
+#define MDHA_CMD_RI		(0x00000001)
+#define MDHA_CMD_SWR		(0x00000001)
+
+#define MDHA_SR_IFL(x)		(((x) & 0xFF) << 16)
+#define MDHA_SR_IFL_MASK	(0xFF00FFFF)
+#define MDHA_SR_APD(x)		(((x) & 0x7) << 13)
+#define MDHA_SR_APD_MASK	(0xFFFF1FFF)
+#define MDHA_SR_FS(x)		(((x) & 0x7) << 8)
+#define MDHA_SR_FS_MASK		(0xFFFFF8FF)
+#define MDHA_SR_GNW		(0x00000080)
+#define MDHA_SR_HSH		(0x00000040)
+#define MDHA_SR_BUSY		(0x00000010)
+#define MDHA_SR_RD		(0x00000008)
+#define MDHA_SR_ERR		(0x00000004)
+#define MDHA_SR_DONE		(0x00000002)
+#define MDHA_SR_INT		(0x00000001)
+
+#define MDHA_ISR_DRL		(0x00000400)		/* 532x */
+#define MDHA_ISR_GTDS		(0x00000200)
+#define MDHA_ISR_ERE		(0x00000100)
+#define MDHA_ISR_RMDP		(0x00000080)
+#define MDHA_ISR_DSE		(0x00000020)
+#define MDHA_ISR_IME		(0x00000010)
+#define MDHA_ISR_NEIF		(0x00000004)
+#define MDHA_ISR_IFO		(0x00000001)
+
+#endif				/* __MDHA_H__ */
diff --git a/include/asm-m68k/coldfire/pwm.h b/include/asm-m68k/coldfire/pwm.h
new file mode 100644
index 0000000..f737d98
--- /dev/null
+++ b/include/asm-m68k/coldfire/pwm.h
@@ -0,0 +1,115 @@
+/*
+ * Pulse Width Modulation Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ATA_H__
+#define __ATA_H__
+
+/* Pulse Width Modulation (PWM) */
+typedef struct pwm_ctrl {
+#ifdef CONFIG_M5272
+	u8 cr0;
+	u8 res1[3];
+	u8 cr1;
+	u8 res2[3];
+	u8 cr2;
+	u8 res3[7];
+	u8 pwr0;
+	u8 res4[3];
+	u8 pwr1;
+	u8 res5[3];
+	u8 pwr2;
+	u8 res6[7];
+#else
+	u8 en;			/* 0x00 PWM Enable */
+	u8 pol;			/* 0x01 Polarity */
+	u8 clk;			/* 0x02 Clock Select */
+	u8 prclk;		/* 0x03 Prescale Clock Select */
+	u8 cae;			/* 0x04 Center Align Enable */
+	u8 ctl;			/* 0x05 Control */
+	u16 res1;		/* 0x06 - 0x07 */
+	u8 scla;		/* 0x08 Scale A */
+	u8 sclb;		/* 0x09 Scale B */
+	u16 res2;		/* 0x0A - 0x0B */
+#ifdef CONFIG_M5275
+	u8 cnt[4];		/* 0x0C Channel n Counter */
+	u16 res3;		/* 0x10 - 0x11 */
+	u8 per[4];		/* 0x14 Channel n Period */
+	u16 res4;		/* 0x16 - 0x17 */
+	u8 dty[4];		/* 0x18 Channel n Duty */
+#else
+	u8 cnt[8];		/* 0x0C Channel n Counter */
+	u8 per[8];		/* 0x14 Channel n Period */
+	u8 dty[8];		/* 0x1C Channel n Duty */
+	u8 sdn;			/* 0x24 Shutdown */
+	u8 res3[3];		/* 0x25 - 0x27 */
+#endif				/* CONFIG_M5275 */
+#endif				/* CONFIG_M5272 */
+} pwm_t;
+
+#ifdef CONFIG_M5272
+
+#define PWM_CR_EN			(0x80)
+#define PWM_CR_FRC1			(0x40)
+#define PWM_CR_LVL			(0x20)
+#define PWM_CR_CLKSEL(x)		((x) & 0x0F)
+#define PWM_CR_CLKSEL_MASK		(0xF0)
+
+#else
+
+#define PWM_EN_PWMEn(x)			(1 << ((x) & 0x07))
+#define PWM_EN_PWMEn_MASK		(0xF0)
+
+#define PWM_POL_PPOLn(x)		(1 << ((x) & 0x07))
+#define PWM_POL_PPOLn_MASK		(0xF0)
+
+#define PWM_CLK_PCLKn(x)		(1 << ((x) & 0x07))
+#define PWM_CLK_PCLKn_MASK		(0xF0)
+
+#define PWM_PRCLK_PCKB(x)		(((x) & 0x07) << 4)
+#define PWM_PRCLK_PCKB_MASK		(0x8F)
+#define PWM_PRCLK_PCKA(x)		((x) & 0x07)
+#define PWM_PRCLK_PCKA_MASK		(0xF8)
+
+#define PWM_CLK_PCLKn(x)		(1 << ((x) & 0x07))
+#define PWM_CLK_PCLKn_MASK		(0xF0)
+
+#define PWM_CTL_CON67			(0x80)
+#define PWM_CTL_CON45			(0x40)
+#define PWM_CTL_CON23			(0x20)
+#define PWM_CTL_CON01			(0x10)
+#define PWM_CTL_PSWAR			(0x08)
+#define PWM_CTL_PFRZ			(0x04)
+
+#define PWM_SDN_IF			(0x80)
+#define PWM_SDN_IE			(0x40)
+#define PWM_SDN_RESTART			(0x20)
+#define PWM_SDN_LVL			(0x10)
+#define PWM_SDN_PWM7IN			(0x04)
+#define PWM_SDN_PWM7IL			(0x02)
+#define PWM_SDN_SDNEN			(0x01)
+
+#endif				/* CONFIG_M5272 */
+
+#endif				/* __ATA_H__ */
diff --git a/include/asm-m68k/coldfire/qspi.h b/include/asm-m68k/coldfire/qspi.h
new file mode 100644
index 0000000..8bcd2e4
--- /dev/null
+++ b/include/asm-m68k/coldfire/qspi.h
@@ -0,0 +1,111 @@
+/*
+ * Queue Serial Peripheral Interface Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __QSPI_H__
+#define __QSPI_H__
+
+/* QSPI module registers */
+typedef struct qspi_ctrl {
+	u16 mr;			/* 0x00 Mode */
+	u16 res1;
+	u16 dlyr;		/* 0x04 Delay */
+	u16 res2;
+	u16 wr;			/* 0x08 Wrap */
+	u16 res3;
+	u16 ir;			/* 0x0C Interrupt */
+	u16 res4;
+	u16 ar;			/* 0x10 Address */
+	u16 res5;
+	u16 dr;			/* 0x14 Data */
+	u16 res6;
+} qspi_t;
+
+/* MR */
+#define QSPI_QMR_MSTR			(0x8000)
+#define QSPI_QMR_DOHIE			(0x4000)
+#define QSPI_QMR_BITS(x)		(((x)&0x000F)<<10)
+#define QSPI_QMR_BITS_MASK		(0xC3FF)
+#define QSPI_QMR_BITS_8			(0x2000)
+#define QSPI_QMR_BITS_9			(0x2400)
+#define QSPI_QMR_BITS_10		(0x2800)
+#define QSPI_QMR_BITS_11		(0x2C00)
+#define QSPI_QMR_BITS_12		(0x3000)
+#define QSPI_QMR_BITS_13		(0x3400)
+#define QSPI_QMR_BITS_14		(0x3800)
+#define QSPI_QMR_BITS_15		(0x3C00)
+#define QSPI_QMR_BITS_16		(0x0000)
+#define QSPI_QMR_CPOL			(0x0200)
+#define QSPI_QMR_CPHA			(0x0100)
+#define QSPI_QMR_BAUD(x)		((x)&0x00FF)
+#define QSPI_QMR_BAUD_MASK		(0xFF00)
+
+/* DLYR */
+#define QSPI_QDLYR_SPE			(0x8000)
+#define QSPI_QDLYR_QCD(x)		(((x)&0x007F)<<8)
+#define QSPI_QDLYR_QCD_MASK		(0x80FF)
+#define QSPI_QDLYR_DTL(x)		((x)&0x00FF)
+#define QSPI_QDLYR_DTL_MASK		(0xFF00)
+
+/* WR */
+#define QSPI_QWR_HALT			(0x8000)
+#define QSPI_QWR_WREN			(0x4000)
+#define QSPI_QWR_WRTO			(0x2000)
+#define QSPI_QWR_CSIV			(0x1000)
+#define QSPI_QWR_ENDQP(x)		(((x)&0x000F)<<8)
+#define QSPI_QWR_ENDQP_MASK		(0xF0FF)
+#define QSPI_QWR_CPTQP(x)		(((x)&0x000F)<<4)
+#define QSPI_QWR_CPTQP_MASK		(0xFF0F)
+#define QSPI_QWR_NEWQP(x)		((x)&0x000F)
+#define QSPI_QWR_NEWQP_MASK		(0xFFF0)
+
+/* IR */
+#define QSPI_QIR_WCEFB			(0x8000)
+#define QSPI_QIR_ABRTB			(0x4000)
+#define QSPI_QIR_ABRTL			(0x1000)
+#define QSPI_QIR_WCEFE			(0x0800)
+#define QSPI_QIR_ABRTE			(0x0400)
+#define QSPI_QIR_SPIFE			(0x0100)
+#define QSPI_QIR_WCEF			(0x0008)
+#define QSPI_QIR_ABRT			(0x0004)
+#define QSPI_QIR_SPIF			(0x0001)
+
+/* AR */
+#define QSPI_QAR_ADDR(x)		((x)&0x003F)
+#define QSPI_QAR_ADDR_MASK		(0xFFC0)
+#define QSPI_QAR_TRANS			(0x0000)
+#define QSPI_QAR_RECV			(0x0010)
+#define QSPI_QAR_CMD			(0x0020)
+
+/* DR */
+#define QSPI_QDR_CONT			(0x8000)
+#define QSPI_QDR_BITSE			(0x4000)
+#define QSPI_QDR_DT			(0x2000)
+#define QSPI_QDR_DSCK			(0x1000)
+#define QSPI_QDR_QSPI_CS3		(0x0800)
+#define QSPI_QDR_QSPI_CS2		(0x0400)
+#define QSPI_QDR_QSPI_CS1		(0x0200)
+#define QSPI_QDR_QSPI_CS0		(0x0100)
+
+#endif				/* __QSPI_H__ */
diff --git a/include/asm-m68k/coldfire/rng.h b/include/asm-m68k/coldfire/rng.h
new file mode 100644
index 0000000..1eefc56
--- /dev/null
+++ b/include/asm-m68k/coldfire/rng.h
@@ -0,0 +1,52 @@
+/*
+ * RNG Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __RNG_H__
+#define __RNG_H__
+
+/* Random Number Generator */
+typedef struct rng_ctrl {
+	u32 cr;			/* 0x00 Control */
+	u32 sr;			/* 0x04 Status */
+	u32 er;			/* 0x08 Entropy */
+	u32 out;		/* 0x0C Output FIFO */
+} rng_t;
+
+#define RNG_CR_SLM		(0x00000010)	/* Sleep mode - 5445x */
+#define RNG_CR_CI		(0x00000008)	/* Clear interrupt */
+#define RNG_CR_IM		(0x00000004)	/* Interrupt mask */
+#define RNG_CR_HA		(0x00000002)	/* High assurance */
+#define RNG_CR_GO		(0x00000001)	/* Go bit */
+
+#define RNG_SR_OFS(x)		(((x) & 0x000000FF) << 16)
+#define RNG_SR_OFS_MASK		(0xFF00FFFF)
+#define RNG_SR_OFL(x)		(((x) & 0x000000FF) << 8)
+#define RNG_SR_OFL_MASK		(0xFFFF00FF)
+#define RNG_SR_EI		(0x00000008)
+#define RNG_SR_FUF		(0x00000004)
+#define RNG_SR_LRS		(0x00000002)
+#define RNG_SR_SV		(0x00000001)
+
+#endif				/* __RNG_H__ */
diff --git a/include/asm-m68k/coldfire/skha.h b/include/asm-m68k/coldfire/skha.h
new file mode 100644
index 0000000..bd6b5af
--- /dev/null
+++ b/include/asm-m68k/coldfire/skha.h
@@ -0,0 +1,121 @@
+/*
+ * Symmetric Key Hardware Accelerator Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SKHA_H__
+#define __SKHA_H__
+
+typedef struct skha_ctrl {
+	u32 mr;			/* 0x00 Mode */
+	u32 cr;			/* 0x04 Control */
+	u32 cmr;		/* 0x08 Command */
+	u32 sr;			/* 0x0C Status */
+	u32 esr;		/* 0x10 Error Status */
+	u32 emr;		/* 0x14 Error Status Mask Register) */
+	u32 ksr;		/* 0x18 Key Size */
+	u32 dsr;		/* 0x1C Data Size */
+	u32 in;			/* 0x20 Input FIFO */
+	u32 out;		/* 0x24 Output FIFO */
+	u32 res1[2];		/* 0x28 - 0x2F */
+	u32 kdr1;		/* 0x30 Key Data 1  */
+	u32 kdr2;		/* 0x34 Key Data 2 */
+	u32 kdr3;		/* 0x38 Key Data 3 */
+	u32 kdr4;		/* 0x3C Key Data 4 */
+	u32 kdr5;		/* 0x40 Key Data 5 */
+	u32 kdr6;		/* 0x44 Key Data 6 */
+	u32 res2[10];		/* 0x48 - 0x6F */
+	u32 c1;			/* 0x70 Context 1 */
+	u32 c2;			/* 0x74 Context 2 */
+	u32 c3;			/* 0x78 Context 3 */
+	u32 c4;			/* 0x7C Context 4 */
+	u32 c5;			/* 0x80 Context 5 */
+	u32 c6;			/* 0x84 Context 6 */
+	u32 c7;			/* 0x88 Context 7 */
+	u32 c8;			/* 0x8C Context 8 */
+	u32 c9;			/* 0x90 Context 9 */
+	u32 c10;		/* 0x94 Context 10 */
+	u32 c11;		/* 0x98 Context 11 */
+	u32 c12;		/* 0x9C Context 12 - 5235, 5271, 5272 */
+} skha_t;
+
+#ifdef CONFIG_MCF532x
+#define	SKHA_MODE_CTRM(x)	(((x) & 0x0F) << 9)
+#define	SKHA_MODE_CTRM_MASK	(0xFFFFE1FF)
+#define	SKHA_MODE_DKP		(0x00000100)
+#else
+#define	SKHA_MODE_CTRM(x)	(((x) & 0x0F) << 8)
+#define	SKHA_MODE_CTRM_MASK	(0xFFFFF0FF)
+#define	SKHA_MODE_DKP		(0x00000080)
+#endif
+#define	SKHA_MODE_CM(x)		(((x) & 0x03) << 3)
+#define	SKHA_MODE_CM_MASK	(0xFFFFFFE7)
+#define	SKHA_MODE_DIR		(0x00000004)
+#define	SKHA_MODE_ALG(x)	((x) & 0x03)
+#define	SKHA_MODE_ALG_MASK	(0xFFFFFFFC)
+
+#define SHKA_CR_ODMAL(x)	(((x) & 0x3F) << 24)
+#define SHKA_CR_ODMAL_MASK	(0xC0FFFFFF)
+#define SHKA_CR_IDMAL(x)	(((x) & 0x3F) << 16)
+#define SHKA_CR_IDMAL_MASK	(0xFFC0FFFF)
+#define SHKA_CR_END		(0x00000008)
+#define SHKA_CR_ODMA		(0x00000004)
+#define SHKA_CR_IDMA		(0x00000002)
+#define	SKHA_CR_IE		(0x00000001)
+
+#define	SKHA_CMR_GO		(0x00000008)
+#define	SKHA_CMR_CI		(0x00000004)
+#define	SKHA_CMR_RI		(0x00000002)
+#define	SKHA_CMR_SWR		(0x00000001)
+
+#define SKHA_SR_OFL(x)		(((x) & 0xFF) << 24)
+#define SKHA_SR_OFL_MASK	(0x00FFFFFF)
+#define SKHA_SR_IFL(x)		(((x) & 0xFF) << 16)
+#define SKHA_SR_IFL_MASK	(0xFF00FFFF)
+#define SKHA_SR_AESES(x)	(((x) & 0x1F) << 11)
+#define SKHA_SR_AESES_MASK	(0xFFFF07FF)
+#define SKHA_SR_DESES(x)	(((x) & 0x7) << 8)
+#define SKHA_SR_DESES_MASK	(0xFFFFF8FF)
+#define SKHA_SR_BUSY		(0x00000010)
+#define SKHA_SR_RD		(0x00000008)
+#define SKHA_SR_ERR		(0x00000004)
+#define SKHA_SR_DONE		(0x00000002)
+#define SKHA_SR_INT		(0x00000001)
+
+#define SHKA_ESE_DRL		(0x00000800)
+#define	SKHA_ESR_KRE		(0x00000400)
+#define	SKHA_ESR_KPE		(0x00000200)
+#define	SKHA_ESR_ERE		(0x00000100)
+#define	SKHA_ESR_RMDP		(0x00000080)
+#define	SKHA_ESR_KSE		(0x00000040)
+#define	SKHA_ESR_DSE		(0x00000020)
+#define	SKHA_ESR_IME		(0x00000010)
+#define	SKHA_ESR_NEOF		(0x00000008)
+#define	SKHA_ESR_NEIF		(0x00000004)
+#define	SKHA_ESR_OFU		(0x00000002)
+#define	SKHA_ESR_IFO		(0x00000001)
+
+#define	SKHA_KSR_SZ(x)		((x) & 0x3F)
+#define	SKHA_KSR_SZ_MASK	(0xFFFFFFC0)
+
+#endif				/* __SKHA_H__ */
diff --git a/include/asm-m68k/coldfire/ssi.h b/include/asm-m68k/coldfire/ssi.h
index 105c475..b3dfbfa 100644
--- a/include/asm-m68k/coldfire/ssi.h
+++ b/include/asm-m68k/coldfire/ssi.h
@@ -26,10 +26,6 @@
 #ifndef __SSI_H__
 #define __SSI_H__
 
-/*********************************************************************
-* Synchronous Serial Interface (SSI)
-*********************************************************************/
-
 typedef struct ssi {
 	u32 tx0;
 	u32 tx1;
@@ -52,14 +48,10 @@ typedef struct ssi {
 	u32 rmask;
 } ssi_t;
 
-/*********************************************************************
-* Synchronous Serial Interface (SSI)
-*********************************************************************/
-
-/* Bit definitions and macros for SSI_CR */
 #define SSI_CR_CIS			(0x00000200)
 #define SSI_CR_TCH			(0x00000100)
 #define SSI_CR_MCE			(0x00000080)
+#define SSI_CR_I2S_MASK			(0xFFFFFF9F)
 #define SSI_CR_I2S_SLAVE		(0x00000040)
 #define SSI_CR_I2S_MASTER		(0x00000020)
 #define SSI_CR_I2S_NORMAL		(0x00000000)
@@ -69,7 +61,6 @@ typedef struct ssi {
 #define SSI_CR_TE			(0x00000002)
 #define SSI_CR_SSI_EN			(0x00000001)
 
-/* Bit definitions and macros for SSI_ISR */
 #define SSI_ISR_CMDAU			(0x00040000)
 #define SSI_ISR_CMDDU			(0x00020000)
 #define SSI_ISR_RXT			(0x00010000)
@@ -90,7 +81,6 @@ typedef struct ssi {
 #define SSI_ISR_TFE1			(0x00000002)
 #define SSI_ISR_TFE0			(0x00000001)
 
-/* Bit definitions and macros for SSI_IER */
 #define SSI_IER_RDMAE			(0x00400000)
 #define SSI_IER_RIE			(0x00200000)
 #define SSI_IER_TDMAE			(0x00100000)
@@ -115,7 +105,6 @@ typedef struct ssi {
 #define SSI_IER_TFE1			(0x00000002)
 #define SSI_IER_TFE0			(0x00000001)
 
-/* Bit definitions and macros for SSI_TCR */
 #define SSI_TCR_TXBIT0			(0x00000200)
 #define SSI_TCR_TFEN1			(0x00000100)
 #define SSI_TCR_TFEN0			(0x00000080)
@@ -127,7 +116,6 @@ typedef struct ssi {
 #define SSI_TCR_TFSL			(0x00000002)
 #define SSI_TCR_TEFS			(0x00000001)
 
-/* Bit definitions and macros for SSI_RCR */
 #define SSI_RCR_RXEXT			(0x00000400)
 #define SSI_RCR_RXBIT0			(0x00000200)
 #define SSI_RCR_RFEN1			(0x00000100)
@@ -138,38 +126,44 @@ typedef struct ssi {
 #define SSI_RCR_RFSL			(0x00000002)
 #define SSI_RCR_REFS			(0x00000001)
 
-/* Bit definitions and macros for SSI_CCR */
 #define SSI_CCR_DIV2			(0x00040000)
 #define SSI_CCR_PSR			(0x00020000)
-#define SSI_CCR_WL(x)			(((x)&0x0000000F)<<13)
-#define SSI_CCR_DC(x)			(((x)&0x0000001F)<<8)
-#define SSI_CCR_PM(x)			((x)&0x000000FF)
-
-/* Bit definitions and macros for SSI_FCSR */
-#define SSI_FCSR_RFCNT1(x)		(((x)&0x0000000F)<<28)
-#define SSI_FCSR_TFCNT1(x)		(((x)&0x0000000F)<<24)
-#define SSI_FCSR_RFWM1(x)		(((x)&0x0000000F)<<20)
-#define SSI_FCSR_TFWM1(x)		(((x)&0x0000000F)<<16)
-#define SSI_FCSR_RFCNT0(x)		(((x)&0x0000000F)<<12)
-#define SSI_FCSR_TFCNT0(x)		(((x)&0x0000000F)<<8)
-#define SSI_FCSR_RFWM0(x)		(((x)&0x0000000F)<<4)
-#define SSI_FCSR_TFWM0(x)		((x)&0x0000000F)
-
-/* Bit definitions and macros for SSI_ACR */
-#define SSI_ACR_FRDIV(x)		(((x)&0x0000003F)<<5)
+#define SSI_CCR_WL(x)			(((x) & 0x0F) << 13)
+#define SSI_CCR_WL_MASK			(0xFFFE1FFF)
+#define SSI_CCR_DC(x)			(((x)& 0x1F) << 8)
+#define SSI_CCR_DC_MASK			(0xFFFFE0FF)
+#define SSI_CCR_PM(x)			((x) & 0xFF)
+#define SSI_CCR_PM_MASK			(0xFFFFFF00)
+
+#define SSI_FCSR_RFCNT1(x)		(((x) & 0x0F) << 28)
+#define SSI_FCSR_RFCNT1_MASK		(0x0FFFFFFF)
+#define SSI_FCSR_TFCNT1(x)		(((x) & 0x0F) << 24)
+#define SSI_FCSR_TFCNT1_MASK		(0xF0FFFFFF)
+#define SSI_FCSR_RFWM1(x)		(((x) & 0x0F) << 20)
+#define SSI_FCSR_RFWM1_MASK		(0xFF0FFFFF)
+#define SSI_FCSR_TFWM1(x)		(((x) & 0x0F) << 16)
+#define SSI_FCSR_TFWM1_MASK		(0xFFF0FFFF)
+#define SSI_FCSR_RFCNT0(x)		(((x) & 0x0F) << 12)
+#define SSI_FCSR_RFCNT0_MASK		(0xFFFF0FFF)
+#define SSI_FCSR_TFCNT0(x)		(((x) & 0x0F) << 8)
+#define SSI_FCSR_TFCNT0_MASK		(0xFFFFF0FF)
+#define SSI_FCSR_RFWM0(x)		(((x) & 0x0F) << 4)
+#define SSI_FCSR_RFWM0_MASK		(0xFFFFFF0F)
+#define SSI_FCSR_TFWM0(x)		((x) & 0x0F)
+#define SSI_FCSR_TFWM0_MASK		(0xFFFFFFF0)
+
+#define SSI_ACR_FRDIV(x)		(((x) & 0x3F) << 5)
+#define SSI_ACR_FRDIV_MASK		(0xFFFFF81F)
 #define SSI_ACR_WR			(0x00000010)
 #define SSI_ACR_RD			(0x00000008)
 #define SSI_ACR_TIF			(0x00000004)
 #define SSI_ACR_FV			(0x00000002)
 #define SSI_ACR_AC97EN			(0x00000001)
 
-/* Bit definitions and macros for SSI_ACADD */
-#define SSI_ACADD_SSI_ACADD(x)		((x)&0x0007FFFF)
+#define SSI_ACADD_SSI_ACADD(x)		((x) & 0x0007FFFF)
 
-/* Bit definitions and macros for SSI_ACDAT */
-#define SSI_ACDAT_SSI_ACDAT(x)		((x)&0x0007FFFF)
+#define SSI_ACDAT_SSI_ACDAT(x)		((x) & 0x0007FFFF)
 
-/* Bit definitions and macros for SSI_ATAG */
-#define SSI_ATAG_DDI_ATAG(x)		((x)&0x0000FFFF)
+#define SSI_ATAG_DDI_ATAG(x)		((x) & 0x0000FFFF)
 
 #endif					/* __SSI_H__ */
diff --git a/include/asm-m68k/config.h b/include/asm-m68k/config.h
new file mode 100644
index 0000000..049c44e
--- /dev/null
+++ b/include/asm-m68k/config.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
diff --git a/include/asm-m68k/fec.h b/include/asm-m68k/fec.h
index e639599..49311e5 100644
--- a/include/asm-m68k/fec.h
+++ b/include/asm-m68k/fec.h
@@ -351,4 +351,16 @@ typedef struct fec {
 #define	FEC_RESET_DELAY			100
 #define FEC_RX_TOUT			100
 
+int fecpin_setclear(struct eth_device *dev, int setclear);
+
+#ifdef CONFIG_SYS_DISCOVER_PHY
+void __mii_init(void);
+uint mii_send(uint mii_cmd);
+int mii_discover_phy(struct eth_device *dev);
+int mcffec_miiphy_read(char *devname, unsigned char addr,
+		       unsigned char reg, unsigned short *value);
+int mcffec_miiphy_write(char *devname, unsigned char addr,
+			unsigned char reg, unsigned short value);
+#endif
+
 #endif				/* fec_h */
diff --git a/include/asm-m68k/fsl_mcdmafec.h b/include/asm-m68k/fsl_mcdmafec.h
index 82da593..7e54056 100644
--- a/include/asm-m68k/fsl_mcdmafec.h
+++ b/include/asm-m68k/fsl_mcdmafec.h
@@ -164,13 +164,4 @@ struct fec_info_dma {
 #define FIFO_CTRL_UFMASK	(0x00100000)
 #define FIFO_CTRL_OFMASK	(0x00080000)
 
-int fecpin_setclear(struct eth_device *dev, int setclear);
-void mii_init(void);
-uint mii_send(uint mii_cmd);
-int mii_discover_phy(struct eth_device *dev);
-int mcffec_miiphy_read(char *devname, unsigned char addr,
-		       unsigned char reg, unsigned short *value);
-int mcffec_miiphy_write(char *devname, unsigned char addr,
-			unsigned char reg, unsigned short value);
-
 #endif				/* fsl_mcdmafec_h */
diff --git a/include/asm-m68k/global_data.h b/include/asm-m68k/global_data.h
index 187618d..413c200 100644
--- a/include/asm-m68k/global_data.h
+++ b/include/asm-m68k/global_data.h
@@ -30,7 +30,7 @@
  * global variables during system initialization (until we have set
  * up the memory controller so that we can use RAM).
  *
- * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
  */
 
 typedef	struct	global_data {
diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h
index b0814f1..93f730f 100644
--- a/include/asm-m68k/immap.h
+++ b/include/asm-m68k/immap.h
@@ -30,84 +30,84 @@
 #include <asm/immap_5227x.h>
 #include <asm/m5227x.h>
 
-#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x4000))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
 
-#define CFG_MCFRTC_BASE		(MMAP_RTC)
+#define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)
 
 #ifdef CONFIG_LCD
-#define	CFG_LCD_BASE		(MMAP_LCD)
+#define	CONFIG_SYS_LCD_BASE		(MMAP_LCD)
 #endif
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CFG_UDELAY_BASE		(MMAP_DTMR0)
-#define CFG_TMR_BASE		(MMAP_DTMR1)
-#define CFG_TMRPND_REG		(((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
-#define CFG_TMRINTR_NO		(INT0_HI_DTMR1)
-#define CFG_TMRINTR_MASK	(INTC_IPRH_INT33)
-#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
-#define CFG_TMRINTR_PRI		(6)
-#define CFG_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT33)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(6)
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
 #ifdef CONFIG_MCFPIT
-#define CFG_UDELAY_BASE		(MMAP_PIT0)
-#define CFG_PIT_BASE		(MMAP_PIT1)
-#define CFG_PIT_PRESCALE	(6)
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
+#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
+#define CONFIG_SYS_PIT_PRESCALE	(6)
 #endif
 
-#define CFG_INTR_BASE		(MMAP_INTC0)
-#define CFG_NUM_IRQS		(128)
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M52277 */
 
 #ifdef CONFIG_M5235
 #include <asm/immap_5235.h>
 #include <asm/m5235.h>
 
-#define CFG_FEC0_IOBASE		(MMAP_FEC)
-#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x40))
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CFG_UDELAY_BASE		(MMAP_DTMR0)
-#define CFG_TMR_BASE		(MMAP_DTMR3)
-#define CFG_TMRPND_REG		(((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
-#define CFG_TMRINTR_NO		(INT0_LO_DTMR3)
-#define CFG_TMRINTR_MASK	(INTC_IPRL_INT22)
-#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
-#define CFG_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
-#define CFG_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
 #ifdef CONFIG_MCFPIT
-#define CFG_UDELAY_BASE		(MMAP_PIT0)
-#define CFG_PIT_BASE		(MMAP_PIT1)
-#define CFG_PIT_PRESCALE	(6)
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
+#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
+#define CONFIG_SYS_PIT_PRESCALE	(6)
 #endif
 
-#define CFG_INTR_BASE		(MMAP_INTC0)
-#define CFG_NUM_IRQS		(128)
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M5235 */
 
 #ifdef CONFIG_M5249
 #include <asm/immap_5249.h>
 #include <asm/m5249.h>
 
-#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
 
-#define CFG_INTR_BASE		(MMAP_INTC)
-#define CFG_NUM_IRQS		(64)
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
+#define CONFIG_SYS_NUM_IRQS		(64)
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CFG_UDELAY_BASE		(MMAP_DTMR0)
-#define CFG_TMR_BASE		(MMAP_DTMR1)
-#define CFG_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
-#define CFG_TMRINTR_NO		(31)
-#define CFG_TMRINTR_MASK	(0x00000400)
-#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
-#define CFG_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
-#define CFG_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
+#define CONFIG_SYS_TMRINTR_NO		(31)
+#define CONFIG_SYS_TMRINTR_MASK	(0x00000400)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
 #endif
 #endif				/* CONFIG_M5249 */
 
@@ -116,21 +116,21 @@
 #include <asm/m5249.h>
 #include <asm/m5253.h>
 
-#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
 
-#define CFG_INTR_BASE		(MMAP_INTC)
-#define CFG_NUM_IRQS		(64)
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
+#define CONFIG_SYS_NUM_IRQS		(64)
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CFG_UDELAY_BASE		(MMAP_DTMR0)
-#define CFG_TMR_BASE		(MMAP_DTMR1)
-#define CFG_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
-#define CFG_TMRINTR_NO		(27)
-#define CFG_TMRINTR_MASK	(0x00000400)
-#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
-#define CFG_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
-#define CFG_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
+#define CONFIG_SYS_TMRINTR_NO		(27)
+#define CONFIG_SYS_TMRINTR_MASK	(0x00000400)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
 #endif
 #endif				/* CONFIG_M5253 */
 
@@ -138,45 +138,45 @@
 #include <asm/immap_5271.h>
 #include <asm/m5271.h>
 
-#define CFG_FEC0_IOBASE		(MMAP_FEC)
-#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x40))
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CFG_UDELAY_BASE		(MMAP_DTMR0)
-#define CFG_TMR_BASE		(MMAP_DTMR3)
-#define CFG_TMRPND_REG		(((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
-#define CFG_TMRINTR_NO		(INT0_LO_DTMR3)
-#define CFG_TMRINTR_MASK	(INTC_IPRL_INT22)
-#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
-#define CFG_TMRINTR_PRI		(0)		/* Level must include inorder to work */
-#define CFG_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(0)		/* Level must include inorder to work */
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#define CFG_INTR_BASE		(MMAP_INTC0)
-#define CFG_NUM_IRQS		(128)
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M5271 */
 
 #ifdef CONFIG_M5272
 #include <asm/immap_5272.h>
 #include <asm/m5272.h>
 
-#define CFG_FEC0_IOBASE		(MMAP_FEC)
-#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x40))
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
 
-#define CFG_INTR_BASE		(MMAP_INTC)
-#define CFG_NUM_IRQS		(64)
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
+#define CONFIG_SYS_NUM_IRQS		(64)
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CFG_UDELAY_BASE		(MMAP_TMR0)
-#define CFG_TMR_BASE		(MMAP_TMR3)
-#define CFG_TMRPND_REG		(((volatile intctrl_t *)(CFG_INTR_BASE))->int_isr)
-#define CFG_TMRINTR_NO		(INT_TMR3)
-#define CFG_TMRINTR_MASK	(INT_ISR_INT24)
-#define CFG_TMRINTR_PEND	(0)
-#define CFG_TMRINTR_PRI		(INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
-#define CFG_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_TMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_TMR3)
+#define CONFIG_SYS_TMRPND_REG		(((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr)
+#define CONFIG_SYS_TMRINTR_NO		(INT_TMR3)
+#define CONFIG_SYS_TMRINTR_MASK	(INT_ISR_INT24)
+#define CONFIG_SYS_TMRINTR_PEND	(0)
+#define CONFIG_SYS_TMRINTR_PRI		(INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 #endif				/* CONFIG_M5272 */
 
@@ -184,23 +184,23 @@
 #include <asm/immap_5275.h>
 #include <asm/m5275.h>
 
-#define CFG_FEC0_IOBASE		(MMAP_FEC0)
-#define CFG_FEC1_IOBASE		(MMAP_FEC1)
-#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x40))
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
+#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
 
-#define CFG_INTR_BASE		(MMAP_INTC0)
-#define CFG_NUM_IRQS		(192)
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(192)
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CFG_UDELAY_BASE		(MMAP_DTMR0)
-#define CFG_TMR_BASE		(MMAP_DTMR3)
-#define CFG_TMRPND_REG		(((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
-#define CFG_TMRINTR_NO		(INT0_LO_DTMR3)
-#define CFG_TMRINTR_MASK	(INTC_IPRL_INT22)
-#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
-#define CFG_TMRINTR_PRI		(0x1E)
-#define CFG_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(0x1E)
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 #endif				/* CONFIG_M5275 */
 
@@ -208,94 +208,126 @@
 #include <asm/immap_5282.h>
 #include <asm/m5282.h>
 
-#define CFG_FEC0_IOBASE		(MMAP_FEC)
-#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x40))
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
 
-#define CFG_INTR_BASE		(MMAP_INTC0)
-#define CFG_NUM_IRQS		(128)
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CFG_UDELAY_BASE		(MMAP_DTMR0)
-#define CFG_TMR_BASE		(MMAP_DTMR3)
-#define CFG_TMRPND_REG		(((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
-#define CFG_TMRINTR_NO		(INT0_LO_DTMR3)
-#define CFG_TMRINTR_MASK	(1 << INT0_LO_DTMR3)
-#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
-#define CFG_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
-#define CFG_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CONFIG_SYS_TMRINTR_MASK	(1 << INT0_LO_DTMR3)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 #endif				/* CONFIG_M5282 */
 
+#if defined(CONFIG_MCF5301x)
+#include <asm/immap_5301x.h>
+#include <asm/m5301x.h>
+
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
+#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+
+#define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CONFIG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
+#define CONFIG_SYS_TMRINTR_PEND		(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(6)
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
+#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
+#define CONFIG_SYS_PIT_PRESCALE	(6)
+#endif
+
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
+#endif				/* CONFIG_M5301x */
+
 #if defined(CONFIG_M5329) || defined(CONFIG_M5373)
 #include <asm/immap_5329.h>
 #include <asm/m5329.h>
 
-#define CFG_FEC0_IOBASE		(MMAP_FEC)
-#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x4000))
-#define CFG_MCFRTC_BASE		(MMAP_RTC)
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+#define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CFG_UDELAY_BASE		(MMAP_DTMR0)
-#define CFG_TMR_BASE		(MMAP_DTMR1)
-#define CFG_TMRPND_REG		(((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
-#define CFG_TMRINTR_NO		(INT0_HI_DTMR1)
-#define CFG_TMRINTR_MASK	(INTC_IPRH_INT33)
-#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
-#define CFG_TMRINTR_PRI		(6)
-#define CFG_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT33)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(6)
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
 #ifdef CONFIG_MCFPIT
-#define CFG_UDELAY_BASE		(MMAP_PIT0)
-#define CFG_PIT_BASE		(MMAP_PIT1)
-#define CFG_PIT_PRESCALE	(6)
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
+#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
+#define CONFIG_SYS_PIT_PRESCALE	(6)
 #endif
 
-#define CFG_INTR_BASE		(MMAP_INTC0)
-#define CFG_NUM_IRQS		(128)
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M5329 && CONFIG_M5373 */
 
 #if defined(CONFIG_M54451) || defined(CONFIG_M54455)
 #include <asm/immap_5445x.h>
 #include <asm/m5445x.h>
 
-#define CFG_FEC0_IOBASE		(MMAP_FEC0)
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
 #if defined(CONFIG_M54455EVB)
-#define CFG_FEC1_IOBASE		(MMAP_FEC1)
+#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
 #endif
 
-#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x4000))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
 
-#define CFG_MCFRTC_BASE		(MMAP_RTC)
+#define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CFG_UDELAY_BASE		(MMAP_DTMR0)
-#define CFG_TMR_BASE		(MMAP_DTMR1)
-#define CFG_TMRPND_REG		(((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
-#define CFG_TMRINTR_NO		(INT0_HI_DTMR1)
-#define CFG_TMRINTR_MASK	(INTC_IPRH_INT33)
-#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
-#define CFG_TMRINTR_PRI		(6)
-#define CFG_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT33)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(6)
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
 #ifdef CONFIG_MCFPIT
-#define CFG_UDELAY_BASE		(MMAP_PIT0)
-#define CFG_PIT_BASE		(MMAP_PIT1)
-#define CFG_PIT_PRESCALE	(6)
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
+#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
+#define CONFIG_SYS_PIT_PRESCALE	(6)
 #endif
 
-#define CFG_INTR_BASE		(MMAP_INTC0)
-#define CFG_NUM_IRQS		(128)
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
 
 #ifdef CONFIG_PCI
-#define CFG_PCI_BAR0		(CFG_MBAR)
-#define CFG_PCI_BAR5		(CFG_SDRAM_BASE)
-#define CFG_PCI_TBATR0		(CFG_MBAR)
-#define CFG_PCI_TBATR5		(CFG_SDRAM_BASE)
+#define CONFIG_SYS_PCI_BAR0		(CONFIG_SYS_MBAR)
+#define CONFIG_SYS_PCI_BAR5		(CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_PCI_TBATR0		(CONFIG_SYS_MBAR)
+#define CONFIG_SYS_PCI_TBATR5		(CONFIG_SYS_SDRAM_BASE)
 #endif
 #endif				/* CONFIG_M54451 || CONFIG_M54455 */
 
@@ -304,8 +336,8 @@
 #include <asm/m547x_8x.h>
 
 #ifdef CONFIG_FSLDMAFEC
-#define CFG_FEC0_IOBASE		(MMAP_FEC0)
-#define CFG_FEC1_IOBASE		(MMAP_FEC1)
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
+#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
 
 #define FEC0_RX_TASK		0
 #define FEC0_TX_TASK		1
@@ -321,27 +353,27 @@
 #define FEC1_TX_INIT		31
 #endif
 
-#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x100))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
 
 #ifdef CONFIG_SLTTMR
-#define CFG_UDELAY_BASE		(MMAP_SLT1)
-#define CFG_TMR_BASE		(MMAP_SLT0)
-#define CFG_TMRPND_REG		(((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
-#define CFG_TMRINTR_NO		(INT0_HI_SLT0)
-#define CFG_TMRINTR_MASK	(INTC_IPRH_INT54)
-#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
-#define CFG_TMRINTR_PRI		(0x1E)
-#define CFG_TIMER_PRESCALER	(gd->bus_clk / 1000000)
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_SLT1)
+#define CONFIG_SYS_TMR_BASE		(MMAP_SLT0)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_SLT0)
+#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT54)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(0x1E)
+#define CONFIG_SYS_TIMER_PRESCALER	(gd->bus_clk / 1000000)
 #endif
 
-#define CFG_INTR_BASE		(MMAP_INTC0)
-#define CFG_NUM_IRQS		(128)
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
 
 #ifdef CONFIG_PCI
-#define CFG_PCI_BAR0		(0x40000000)
-#define CFG_PCI_BAR1		(CFG_SDRAM_BASE)
-#define CFG_PCI_TBATR0		(CFG_MBAR)
-#define CFG_PCI_TBATR1		(CFG_SDRAM_BASE)
+#define CONFIG_SYS_PCI_BAR0		(0x40000000)
+#define CONFIG_SYS_PCI_BAR1		(CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_PCI_TBATR0		(CONFIG_SYS_MBAR)
+#define CONFIG_SYS_PCI_TBATR1		(CONFIG_SYS_SDRAM_BASE)
 #endif
 #endif				/* CONFIG_M547x */
 
@@ -350,8 +382,8 @@
 #include <asm/m547x_8x.h>
 
 #ifdef CONFIG_FSLDMAFEC
-#define CFG_FEC0_IOBASE		(MMAP_FEC0)
-#define CFG_FEC1_IOBASE		(MMAP_FEC1)
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
+#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
 
 #define FEC0_RX_TASK		0
 #define FEC0_TX_TASK		1
@@ -367,28 +399,28 @@
 #define FEC1_TX_INIT		31
 #endif
 
-#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x100))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
 
 /* Timer */
 #ifdef CONFIG_SLTTMR
-#define CFG_UDELAY_BASE		(MMAP_SLT1)
-#define CFG_TMR_BASE		(MMAP_SLT0)
-#define CFG_TMRPND_REG		(((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
-#define CFG_TMRINTR_NO		(INT0_HI_SLT0)
-#define CFG_TMRINTR_MASK	(INTC_IPRH_INT54)
-#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
-#define CFG_TMRINTR_PRI		(0x1E)
-#define CFG_TIMER_PRESCALER	(gd->bus_clk / 1000000)
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_SLT1)
+#define CONFIG_SYS_TMR_BASE		(MMAP_SLT0)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_SLT0)
+#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT54)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(0x1E)
+#define CONFIG_SYS_TIMER_PRESCALER	(gd->bus_clk / 1000000)
 #endif
 
-#define CFG_INTR_BASE		(MMAP_INTC0)
-#define CFG_NUM_IRQS		(128)
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
 
 #ifdef CONFIG_PCI
-#define CFG_PCI_BAR0		(CFG_MBAR)
-#define CFG_PCI_BAR1		(CFG_SDRAM_BASE)
-#define CFG_PCI_TBATR0		(CFG_MBAR)
-#define CFG_PCI_TBATR1		(CFG_SDRAM_BASE)
+#define CONFIG_SYS_PCI_BAR0		(CONFIG_SYS_MBAR)
+#define CONFIG_SYS_PCI_BAR1		(CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_PCI_TBATR0		(CONFIG_SYS_MBAR)
+#define CONFIG_SYS_PCI_TBATR1		(CONFIG_SYS_SDRAM_BASE)
 #endif
 #endif				/* CONFIG_M548x */
 
diff --git a/include/asm-m68k/immap_5227x.h b/include/asm-m68k/immap_5227x.h
index 1d1e6f1..6f65f50 100644
--- a/include/asm-m68k/immap_5227x.h
+++ b/include/asm-m68k/immap_5227x.h
@@ -27,151 +27,56 @@
 #define __IMMAP_5227X__
 
 /* Module Base Addresses */
-#define MMAP_SCM1	(CFG_MBAR + 0x00000000)
-#define MMAP_XBS	(CFG_MBAR + 0x00004000)
-#define MMAP_FBCS	(CFG_MBAR + 0x00008000)
-#define MMAP_CAN	(CFG_MBAR + 0x00020000)
-#define MMAP_RTC	(CFG_MBAR + 0x0003C000)
-#define MMAP_SCM2	(CFG_MBAR + 0x00040010)
-#define MMAP_SCM3	(CFG_MBAR + 0x00040070)
-#define MMAP_EDMA	(CFG_MBAR + 0x00044000)
-#define MMAP_INTC0	(CFG_MBAR + 0x00048000)
-#define MMAP_INTC1	(CFG_MBAR + 0x0004C000)
-#define MMAP_IACK	(CFG_MBAR + 0x00054000)
-#define MMAP_I2C	(CFG_MBAR + 0x00058000)
-#define MMAP_DSPI	(CFG_MBAR + 0x0005C000)
-#define MMAP_UART0	(CFG_MBAR + 0x00060000)
-#define MMAP_UART1	(CFG_MBAR + 0x00064000)
-#define MMAP_UART2	(CFG_MBAR + 0x00068000)
-#define MMAP_DTMR0	(CFG_MBAR + 0x00070000)
-#define MMAP_DTMR1	(CFG_MBAR + 0x00074000)
-#define MMAP_DTMR2	(CFG_MBAR + 0x00078000)
-#define MMAP_DTMR3	(CFG_MBAR + 0x0007C000)
-#define MMAP_PIT0	(CFG_MBAR + 0x00080000)
-#define MMAP_PIT1	(CFG_MBAR + 0x00084000)
-#define MMAP_PWM	(CFG_MBAR + 0x00090000)
-#define MMAP_EPORT	(CFG_MBAR + 0x00094000)
-#define MMAP_RCM	(CFG_MBAR + 0x000A0000)
-#define MMAP_CCM	(CFG_MBAR + 0x000A0004)
-#define MMAP_GPIO	(CFG_MBAR + 0x000A4000)
-#define MMAP_ADC	(CFG_MBAR + 0x000A8000)
-#define MMAP_LCD	(CFG_MBAR + 0x000AC000)
-#define MMAP_LCD_BGLUT	(CFG_MBAR + 0x000AC800)
-#define MMAP_LCD_GWLUT	(CFG_MBAR + 0x000ACC00)
-#define MMAP_USBHW	(CFG_MBAR + 0x000B0000)
-#define MMAP_USBCAPS	(CFG_MBAR + 0x000B0100)
-#define MMAP_USBEHCI	(CFG_MBAR + 0x000B0140)
-#define MMAP_USBOTG	(CFG_MBAR + 0x000B01A0)
-#define MMAP_SDRAM	(CFG_MBAR + 0x000B8000)
-#define MMAP_SSI	(CFG_MBAR + 0x000BC000)
-#define MMAP_PLL	(CFG_MBAR + 0x000C0000)
+#define MMAP_SCM1	(CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_XBS	(CONFIG_SYS_MBAR + 0x00004000)
+#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00008000)
+#define MMAP_CAN	(CONFIG_SYS_MBAR + 0x00020000)
+#define MMAP_RTC	(CONFIG_SYS_MBAR + 0x0003C000)
+#define MMAP_SCM2	(CONFIG_SYS_MBAR + 0x00040010)
+#define MMAP_SCM3	(CONFIG_SYS_MBAR + 0x00040070)
+#define MMAP_EDMA	(CONFIG_SYS_MBAR + 0x00044000)
+#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00048000)
+#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x0004C000)
+#define MMAP_IACK	(CONFIG_SYS_MBAR + 0x00054000)
+#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00058000)
+#define MMAP_DSPI	(CONFIG_SYS_MBAR + 0x0005C000)
+#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00060000)
+#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00064000)
+#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00068000)
+#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00070000)
+#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00074000)
+#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00078000)
+#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x0007C000)
+#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00080000)
+#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00084000)
+#define MMAP_PWM	(CONFIG_SYS_MBAR + 0x00090000)
+#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00094000)
+#define MMAP_RCM	(CONFIG_SYS_MBAR + 0x000A0000)
+#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x000A0004)
+#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x000A4000)
+#define MMAP_ADC	(CONFIG_SYS_MBAR + 0x000A8000)
+#define MMAP_LCD	(CONFIG_SYS_MBAR + 0x000AC000)
+#define MMAP_LCD_BGLUT	(CONFIG_SYS_MBAR + 0x000AC800)
+#define MMAP_LCD_GWLUT	(CONFIG_SYS_MBAR + 0x000ACC00)
+#define MMAP_USBHW	(CONFIG_SYS_MBAR + 0x000B0000)
+#define MMAP_USBCAPS	(CONFIG_SYS_MBAR + 0x000B0100)
+#define MMAP_USBEHCI	(CONFIG_SYS_MBAR + 0x000B0140)
+#define MMAP_USBOTG	(CONFIG_SYS_MBAR + 0x000B01A0)
+#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x000B8000)
+#define MMAP_SSI	(CONFIG_SYS_MBAR + 0x000BC000)
+#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x000C0000)
 
 #include <asm/coldfire/crossbar.h>
 #include <asm/coldfire/dspi.h>
 #include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
 #include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/intctrl.h>
 #include <asm/coldfire/lcd.h>
+#include <asm/coldfire/pwm.h>
 #include <asm/coldfire/ssi.h>
 
-/* Interrupt Controller (INTC) */
-typedef struct int0_ctrl {
-	u32 iprh0;		/* 0x00 Pending Register High */
-	u32 iprl0;		/* 0x04 Pending Register Low */
-	u32 imrh0;		/* 0x08 Mask Register High */
-	u32 imrl0;		/* 0x0C Mask Register Low */
-	u32 frch0;		/* 0x10 Force Register High */
-	u32 frcl0;		/* 0x14 Force Register Low */
-	u16 res1;		/* 0x18 - 0x19 */
-	u16 icfg0;		/* 0x1A Configuration Register */
-	u8 simr0;		/* 0x1C Set Interrupt Mask */
-	u8 cimr0;		/* 0x1D Clear Interrupt Mask */
-	u8 clmask0;		/* 0x1E Current Level Mask */
-	u8 slmask;		/* 0x1F Saved Level Mask */
-	u32 res2[8];		/* 0x20 - 0x3F */
-	u8 icr0[64];		/* 0x40 - 0x7F Control registers */
-	u32 res3[24];		/* 0x80 - 0xDF */
-	u8 swiack0;		/* 0xE0 Software Interrupt ack */
-	u8 res4[3];		/* 0xE1 - 0xE3 */
-	u8 Lniack0_1;		/* 0xE4 Level n interrupt ack */
-	u8 res5[3];		/* 0xE5 - 0xE7 */
-	u8 Lniack0_2;		/* 0xE8 Level n interrupt ack */
-	u8 res6[3];		/* 0xE9 - 0xEB */
-	u8 Lniack0_3;		/* 0xEC Level n interrupt ack */
-	u8 res7[3];		/* 0xED - 0xEF */
-	u8 Lniack0_4;		/* 0xF0 Level n interrupt ack */
-	u8 res8[3];		/* 0xF1 - 0xF3 */
-	u8 Lniack0_5;		/* 0xF4 Level n interrupt ack */
-	u8 res9[3];		/* 0xF5 - 0xF7 */
-	u8 Lniack0_6;		/* 0xF8 Level n interrupt ack */
-	u8 resa[3];		/* 0xF9 - 0xFB */
-	u8 Lniack0_7;		/* 0xFC Level n interrupt ack */
-	u8 resb[3];		/* 0xFD - 0xFF */
-} int0_t;
-
-typedef struct int1_ctrl {
-	/* Interrupt Controller 1 */
-	u32 iprh1;		/* 0x00 Pending Register High */
-	u32 iprl1;		/* 0x04 Pending Register Low */
-	u32 imrh1;		/* 0x08 Mask Register High */
-	u32 imrl1;		/* 0x0C Mask Register Low */
-	u32 frch1;		/* 0x10 Force Register High */
-	u32 frcl1;		/* 0x14 Force Register Low */
-	u16 res1;		/* 0x18 */
-	u16 icfg1;		/* 0x1A Configuration Register */
-	u8 simr1;		/* 0x1C Set Interrupt Mask */
-	u8 cimr1;		/* 0x1D Clear Interrupt Mask */
-	u16 res2;		/* 0x1E - 0x1F */
-	u32 res3[8];		/* 0x20 - 0x3F */
-	u8 icr1[64];		/* 0x40 - 0x7F */
-	u32 res4[24];		/* 0x80 - 0xDF */
-	u8 swiack1;		/* 0xE0 Software Interrupt ack */
-	u8 res5[3];		/* 0xE1 - 0xE3 */
-	u8 Lniack1_1;		/* 0xE4 Level n interrupt ack */
-	u8 res6[3];		/* 0xE5 - 0xE7 */
-	u8 Lniack1_2;		/* 0xE8 Level n interrupt ack */
-	u8 res7[3];		/* 0xE9 - 0xEB */
-	u8 Lniack1_3;		/* 0xEC Level n interrupt ack */
-	u8 res8[3];		/* 0xED - 0xEF */
-	u8 Lniack1_4;		/* 0xF0 Level n interrupt ack */
-	u8 res9[3];		/* 0xF1 - 0xF3 */
-	u8 Lniack1_5;		/* 0xF4 Level n interrupt ack */
-	u8 resa[3];		/* 0xF5 - 0xF7 */
-	u8 Lniack1_6;		/* 0xF8 Level n interrupt ack */
-	u8 resb[3];		/* 0xF9 - 0xFB */
-	u8 Lniack1_7;		/* 0xFC Level n interrupt ack */
-	u8 resc[3];		/* 0xFD - 0xFF */
-} int1_t;
-
-/* Global Interrupt Acknowledge (IACK) */
-typedef struct iack {
-	u8 resv0[0xE0];
-	u8 gswiack;
-	u8 resv1[0x3];
-	u8 gl1iack;
-	u8 resv2[0x3];
-	u8 gl2iack;
-	u8 resv3[0x3];
-	u8 gl3iack;
-	u8 resv4[0x3];
-	u8 gl4iack;
-	u8 resv5[0x3];
-	u8 gl5iack;
-	u8 resv6[0x3];
-	u8 gl6iack;
-	u8 resv7[0x3];
-	u8 gl7iack;
-} iack_t;
-
-/* Edge Port Module (EPORT) */
-typedef struct eport {
-	u16 eppar;
-	u8 epddr;
-	u8 epier;
-	u8 epdr;
-	u8 eppdr;
-	u8 epfr;
-} eport_t;
-
 /* Reset Controller Module (RCM) */
 typedef struct rcm {
 	u8 rcr;
@@ -193,6 +98,12 @@ typedef struct ccm {
 	u16 sbfcr;		/* Serial Boot Control */
 } ccm_t;
 
+typedef struct canex_ctrl {
+	can_msg_t msg[16];	/* 0x00 Message Buffer 0-15 */
+	u32 res0[0x700];	/* 0x100 */
+	can_msg_t rxim[16];	/* 0x800 Rx Individual Mask 0-15 */
+} canex_t;
+
 /* General Purpose I/O Module (GPIO) */
 typedef struct gpio {
 	/* Port Output Data Registers */
diff --git a/include/asm-m68k/immap_5235.h b/include/asm-m68k/immap_5235.h
index 4a03450..f7f35fc 100644
--- a/include/asm-m68k/immap_5235.h
+++ b/include/asm-m68k/immap_5235.h
@@ -26,42 +26,51 @@
 #ifndef __IMMAP_5235__
 #define __IMMAP_5235__
 
-#define MMAP_SCM	(CFG_MBAR + 0x00000000)
-#define MMAP_SDRAM	(CFG_MBAR + 0x00000040)
-#define MMAP_FBCS	(CFG_MBAR + 0x00000080)
-#define MMAP_DMA0	(CFG_MBAR + 0x00000100)
-#define MMAP_DMA1	(CFG_MBAR + 0x00000110)
-#define MMAP_DMA2	(CFG_MBAR + 0x00000120)
-#define MMAP_DMA3	(CFG_MBAR + 0x00000130)
-#define MMAP_UART0	(CFG_MBAR + 0x00000200)
-#define MMAP_UART1	(CFG_MBAR + 0x00000240)
-#define MMAP_UART2	(CFG_MBAR + 0x00000280)
-#define MMAP_I2C	(CFG_MBAR + 0x00000300)
-#define MMAP_QSPI	(CFG_MBAR + 0x00000340)
-#define MMAP_DTMR0	(CFG_MBAR + 0x00000400)
-#define MMAP_DTMR1	(CFG_MBAR + 0x00000440)
-#define MMAP_DTMR2	(CFG_MBAR + 0x00000480)
-#define MMAP_DTMR3	(CFG_MBAR + 0x000004C0)
-#define MMAP_INTC0	(CFG_MBAR + 0x00000C00)
-#define MMAP_INTC1	(CFG_MBAR + 0x00000D00)
-#define MMAP_INTCACK	(CFG_MBAR + 0x00000F00)
-#define MMAP_FEC	(CFG_MBAR + 0x00001000)
-#define MMAP_FECFIFO	(CFG_MBAR + 0x00001400)
-#define MMAP_GPIO	(CFG_MBAR + 0x00100000)
-#define MMAP_CCM	(CFG_MBAR + 0x00110000)
-#define MMAP_PLL	(CFG_MBAR + 0x00120000)
-#define MMAP_EPORT	(CFG_MBAR + 0x00130000)
-#define MMAP_WDOG	(CFG_MBAR + 0x00140000)
-#define MMAP_PIT0	(CFG_MBAR + 0x00150000)
-#define MMAP_PIT1	(CFG_MBAR + 0x00160000)
-#define MMAP_PIT2	(CFG_MBAR + 0x00170000)
-#define MMAP_PIT3	(CFG_MBAR + 0x00180000)
-#define MMAP_MDHA	(CFG_MBAR + 0x00190000)
-#define MMAP_RNG	(CFG_MBAR + 0x001A0000)
-#define MMAP_SKHA	(CFG_MBAR + 0x001B0000)
-#define MMAP_CAN1	(CFG_MBAR + 0x001C0000)
-#define MMAP_ETPU	(CFG_MBAR + 0x001D0000)
-#define MMAP_CAN2	(CFG_MBAR + 0x001F0000)
+#define MMAP_SCM	(CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1	(CONFIG_SYS_MBAR + 0x00000110)
+#define MMAP_DMA2	(CONFIG_SYS_MBAR + 0x00000120)
+#define MMAP_DMA3	(CONFIG_SYS_MBAR + 0x00000130)
+#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC	(CONFIG_SYS_MBAR + 0x00001000)
+#define MMAP_FECFIFO	(CONFIG_SYS_MBAR + 0x00001400)
+#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00100000)
+#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x00110000)
+#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x00180000)
+#define MMAP_MDHA	(CONFIG_SYS_MBAR + 0x00190000)
+#define MMAP_RNG	(CONFIG_SYS_MBAR + 0x001A0000)
+#define MMAP_SKHA	(CONFIG_SYS_MBAR + 0x001B0000)
+#define MMAP_CAN1	(CONFIG_SYS_MBAR + 0x001C0000)
+#define MMAP_ETPU	(CONFIG_SYS_MBAR + 0x001D0000)
+#define MMAP_CAN2	(CONFIG_SYS_MBAR + 0x001F0000)
+
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/mdha.h>
+#include <asm/coldfire/qspi.h>
+#include <asm/coldfire/rng.h>
+#include <asm/coldfire/skha.h>
 
 /* System Control Module register */
 typedef struct scm_ctrl {
@@ -104,141 +113,9 @@ typedef struct sdram_ctrl {
 	u32 dmr1;		/* 0x14 mask register block 1 */
 } sdram_t;
 
-/* Flexbus module Chip select registers */
-typedef struct fbcs_ctrl {
-	u16 csar0;		/* 0x00 Chip-Select Address Register 0 */
-	u16 res0;
-	u32 csmr0;		/* 0x04 Chip-Select Mask Register 0 */
-	u16 res1;		/* 0x08 */
-	u16 cscr0;		/* 0x0A Chip-Select Control Register 0 */
-
-	u16 csar1;		/* 0x0C Chip-Select Address Register 1 */
-	u16 res2;
-	u32 csmr1;		/* 0x10 Chip-Select Mask Register 1 */
-	u16 res3;		/* 0x14 */
-	u16 cscr1;		/* 0x16 Chip-Select Control Register 1 */
-
-	u16 csar2;		/* 0x18 Chip-Select Address Register 2 */
-	u16 res4;
-	u32 csmr2;		/* 0x1C Chip-Select Mask Register 2 */
-	u16 res5;		/* 0x20 */
-	u16 cscr2;		/* 0x22 Chip-Select Control Register 2 */
-
-	u16 csar3;		/* 0x24 Chip-Select Address Register 3 */
-	u16 res6;
-	u32 csmr3;		/* 0x28 Chip-Select Mask Register 3 */
-	u16 res7;		/* 0x2C */
-	u16 cscr3;		/* 0x2E Chip-Select Control Register 3 */
-
-	u16 csar4;		/* 0x30 Chip-Select Address Register 4 */
-	u16 res8;
-	u32 csmr4;		/* 0x34 Chip-Select Mask Register 4 */
-	u16 res9;		/* 0x38 */
-	u16 cscr4;		/* 0x3A Chip-Select Control Register 4 */
-
-	u16 csar5;		/* 0x3C Chip-Select Address Register 5 */
-	u16 res10;
-	u32 csmr5;		/* 0x40 Chip-Select Mask Register 5 */
-	u16 res11;		/* 0x44 */
-	u16 cscr5;		/* 0x46 Chip-Select Control Register 5 */
-
-	u16 csar6;		/* 0x48 Chip-Select Address Register 5 */
-	u16 res12;
-	u32 csmr6;		/* 0x4C Chip-Select Mask Register 5 */
-	u16 res13;		/* 0x50 */
-	u16 cscr6;		/* 0x52 Chip-Select Control Register 5 */
-
-	u16 csar7;		/* 0x54 Chip-Select Address Register 5 */
-	u16 res14;
-	u32 csmr7;		/* 0x58 Chip-Select Mask Register 5 */
-	u16 res15;		/* 0x5C */
-	u16 cscr7;		/* 0x5E Chip-Select Control Register 5 */
-} fbcs_t;
-
-/* QSPI module registers */
-typedef struct qspi_ctrl {
-	u16 qmr;		/* Mode register */
-	u16 res1;
-	u16 qdlyr;		/* Delay register */
-	u16 res2;
-	u16 qwr;		/* Wrap register */
-	u16 res3;
-	u16 qir;		/* Interrupt register */
-	u16 res4;
-	u16 qar;		/* Address register */
-	u16 res5;
-	u16 qdr;		/* Data register */
-	u16 res6;
-} qspi_t;
-
-/* Interrupt module registers */
-typedef struct int0_ctrl {
-	/* Interrupt Controller 0 */
-	u32 iprh0;		/* 0x00 Pending Register High */
-	u32 iprl0;		/* 0x04 Pending Register Low */
-	u32 imrh0;		/* 0x08 Mask Register High */
-	u32 imrl0;		/* 0x0C Mask Register Low */
-	u32 frch0;		/* 0x10 Force Register High */
-	u32 frcl0;		/* 0x14 Force Register Low */
-	u8 irlr;		/* 0x18 */
-	u8 iacklpr;		/* 0x19 */
-	u16 res1[19];		/* 0x1a - 0x3c */
-	u8 icr0[64];		/* 0x40 - 0x7F Control registers */
-	u32 res3[24];		/* 0x80 - 0xDF */
-	u8 swiack0;		/* 0xE0 Software Interrupt Acknowledge */
-	u8 res4[3];		/* 0xE1 - 0xE3 */
-	u8 Lniack0_1;		/* 0xE4 Level n interrupt acknowledge resister */
-	u8 res5[3];		/* 0xE5 - 0xE7 */
-	u8 Lniack0_2;		/* 0xE8 Level n interrupt acknowledge resister */
-	u8 res6[3];		/* 0xE9 - 0xEB */
-	u8 Lniack0_3;		/* 0xEC Level n interrupt acknowledge resister */
-	u8 res7[3];		/* 0xED - 0xEF */
-	u8 Lniack0_4;		/* 0xF0 Level n interrupt acknowledge resister */
-	u8 res8[3];		/* 0xF1 - 0xF3 */
-	u8 Lniack0_5;		/* 0xF4 Level n interrupt acknowledge resister */
-	u8 res9[3];		/* 0xF5 - 0xF7 */
-	u8 Lniack0_6;		/* 0xF8 Level n interrupt acknowledge resister */
-	u8 resa[3];		/* 0xF9 - 0xFB */
-	u8 Lniack0_7;		/* 0xFC Level n interrupt acknowledge resister */
-	u8 resb[3];		/* 0xFD - 0xFF */
-} int0_t;
-
-typedef struct int1_ctrl {
-	/* Interrupt Controller 1 */
-	u32 iprh1;		/* 0x00 Pending Register High */
-	u32 iprl1;		/* 0x04 Pending Register Low */
-	u32 imrh1;		/* 0x08 Mask Register High */
-	u32 imrl1;		/* 0x0C Mask Register Low */
-	u32 frch1;		/* 0x10 Force Register High */
-	u32 frcl1;		/* 0x14 Force Register Low */
-	u8 irlr;		/* 0x18 */
-	u8 iacklpr;		/* 0x19 */
-	u16 res1[19];		/* 0x1a - 0x3c */
-	u8 icr1[64];		/* 0x40 - 0x7F */
-	u32 res4[24];		/* 0x80 - 0xDF */
-	u8 swiack1;		/* 0xE0 Software Interrupt Acknowledge */
-	u8 res5[3];		/* 0xE1 - 0xE3 */
-	u8 Lniack1_1;		/* 0xE4 Level n interrupt acknowledge resister */
-	u8 res6[3];		/* 0xE5 - 0xE7 */
-	u8 Lniack1_2;		/* 0xE8 Level n interrupt acknowledge resister */
-	u8 res7[3];		/* 0xE9 - 0xEB */
-	u8 Lniack1_3;		/* 0xEC Level n interrupt acknowledge resister */
-	u8 res8[3];		/* 0xED - 0xEF */
-	u8 Lniack1_4;		/* 0xF0 Level n interrupt acknowledge resister */
-	u8 res9[3];		/* 0xF1 - 0xF3 */
-	u8 Lniack1_5;		/* 0xF4 Level n interrupt acknowledge resister */
-	u8 resa[3];		/* 0xF5 - 0xF7 */
-	u8 Lniack1_6;		/* 0xF8 Level n interrupt acknowledge resister */
-	u8 resb[3];		/* 0xF9 - 0xFB */
-	u8 Lniack1_7;		/* 0xFC Level n interrupt acknowledge resister */
-	u8 resc[3];		/* 0xFD - 0xFF */
-} int1_t;
-
-typedef struct intgack_ctrl1 {
-	/* Global IACK Registers */
-	u8 swiack;		/* 0xE0 Global Software Interrupt Acknowledge */
-	u8 Lniack[7];		/* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
-} intgack_t;
+typedef struct canex_ctrl {
+	can_msg_t msg[16];	/* 0x00 Message Buffer 0-15 */
+} canex_t;
 
 /* GPIO port registers */
 typedef struct gpio_ctrl {
@@ -356,23 +233,4 @@ typedef struct wdog_ctrl {
 	u16 sr;			/* 0x06 Service register */
 } wdog_t;
 
-/* FlexCan module registers */
-typedef struct can_ctrl {
-	u32 mcr;		/* 0x00 Module Configuration register */
-	u32 ctrl;		/* 0x04 Control register */
-	u32 timer;		/* 0x08 Free Running Timer */
-	u32 res1;		/* 0x0C */
-	u32 rxgmask;		/* 0x10 Rx Global Mask */
-	u32 rx14mask;		/* 0x14 RxBuffer 14 Mask */
-	u32 rx15mask;		/* 0x18 RxBuffer 15 Mask */
-	u32 errcnt;		/* 0x1C Error Counter Register */
-	u32 errstat;		/* 0x20 Error and status Register */
-	u32 res2;		/* 0x24 */
-	u32 imask;		/* 0x28 Interrupt Mask Register */
-	u32 res3;		/* 0x2C */
-	u32 iflag;		/* 0x30 Interrupt Flag Register */
-	u32 res4[19];		/* 0x34 - 0x7F */
-	u32 MB0_15[2048];	/* 0x80 Message Buffer 0-15 */
-} can_t;
-
 #endif				/* __IMMAP_5235__ */
diff --git a/include/asm-m68k/immap_5249.h b/include/asm-m68k/immap_5249.h
index 6c6fbcc..0242086 100644
--- a/include/asm-m68k/immap_5249.h
+++ b/include/asm-m68k/immap_5249.h
@@ -25,11 +25,15 @@
 #ifndef __IMMAP_5249__
 #define __IMMAP_5249__
 
-#define MMAP_INTC		(CFG_MBAR + 0x00000040)
-#define MMAP_DTMR0		(CFG_MBAR + 0x00000140)
-#define MMAP_DTMR1		(CFG_MBAR + 0x00000180)
-#define MMAP_UART0		(CFG_MBAR + 0x000001C0)
-#define MMAP_UART1		(CFG_MBAR + 0x00000200)
-#define MMAP_QSPI		(CFG_MBAR + 0x00000400)
+#define MMAP_INTC		(CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS		(CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_DTMR0		(CONFIG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1		(CONFIG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0		(CONFIG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1		(CONFIG_SYS_MBAR + 0x00000200)
+#define MMAP_QSPI		(CONFIG_SYS_MBAR + 0x00000400)
+
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/qspi.h>
 
 #endif				/* __IMMAP_5249__ */
diff --git a/include/asm-m68k/immap_5253.h b/include/asm-m68k/immap_5253.h
index aafbdd0..b5a4cb5 100644
--- a/include/asm-m68k/immap_5253.h
+++ b/include/asm-m68k/immap_5253.h
@@ -23,73 +23,30 @@
  * MA 02111-1307 USA
  */
 
-#ifndef __IMMAP_5249__
-#define __IMMAP_5249__
-
-#define MMAP_INTC		(CFG_MBAR + 0x00000040)
-#define MMAP_DTMR0		(CFG_MBAR + 0x00000140)
-#define MMAP_DTMR1		(CFG_MBAR + 0x00000180)
-#define MMAP_UART0		(CFG_MBAR + 0x000001C0)
-#define MMAP_UART1		(CFG_MBAR + 0x00000200)
-#define MMAP_I2C0		(CFG_MBAR + 0x00000280)
-#define MMAP_QSPI		(CFG_MBAR + 0x00000400)
-#define MMAP_CAN0		(CFG_MBAR + 0x00010000)
-#define MMAP_CAN1		(CFG_MBAR + 0x00011000)
-
-#define MMAP_I2C1		(CFG_MBAR2 + 0x00000440)
-#define MMAP_UART2		(CFG_MBAR2 + 0x00000C00)
-
-/*********************************************************************
-* ATA Module (ATAC)
-*********************************************************************/
-
-/* Register read/write struct */
-typedef struct atac {
-	/* PIO */
-	u8 toff;		/* 0x00 */
-	u8 ton;			/* 0x01 */
-	u8 t1;			/* 0x02 */
-	u8 t2w;			/* 0x03 */
-	u8 t2r;			/* 0x04 */
-	u8 ta;			/* 0x05 */
-	u8 trd;			/* 0x06 */
-	u8 t4;			/* 0x07 */
-	u8 t9;			/* 0x08 */
-
-	/* DMA */
-	u8 tm;			/* 0x09 */
-	u8 tn;			/* 0x0A */
-	u8 td;			/* 0x0B */
-	u8 tk;			/* 0x0C */
-	u8 tack;		/* 0x0D */
-	u8 tenv;		/* 0x0E */
-	u8 trp;			/* 0x0F */
-	u8 tzah;		/* 0x10 */
-	u8 tmli;		/* 0x11 */
-	u8 tdvh;		/* 0x12 */
-	u8 tdzfs;		/* 0x13 */
-	u8 tdvs;		/* 0x14 */
-	u8 tcvh;		/* 0x15 */
-	u8 tss;			/* 0x16 */
-	u8 tcyc;		/* 0x17 */
-
-	/* FIFO */
-	u32 fifo32;		/* 0x18 */
-	u16 fifo16;		/* 0x1C */
-	u8 rsvd0[2];
-	u8 ffill;		/* 0x20 */
-	u8 rsvd1[3];
-
-	/* ATA */
-	u8 cr;			/* 0x24 */
-	u8 rsvd2[3];
-	u8 isr;			/* 0x28 */
-	u8 rsvd3[3];
-	u8 ier;			/* 0x2C */
-	u8 rsvd4[3];
-	u8 icr;			/* 0x30 */
-	u8 rsvd5[3];
-	u8 falarm;		/* 0x34 */
-} atac_t;
-
-#endif				/* __IMMAP_5249__ */
+#ifndef __IMMAP_5253__
+#define __IMMAP_5253__
+
+#define MMAP_INTC		(CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS		(CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_DTMR0		(CONFIG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1		(CONFIG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0		(CONFIG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1		(CONFIG_SYS_MBAR + 0x00000200)
+#define MMAP_I2C0		(CONFIG_SYS_MBAR + 0x00000280)
+#define MMAP_QSPI		(CONFIG_SYS_MBAR + 0x00000400)
+#define MMAP_CAN0		(CONFIG_SYS_MBAR + 0x00010000)
+#define MMAP_CAN1		(CONFIG_SYS_MBAR + 0x00011000)
+
+#define MMAP_I2C1		(CONFIG_SYS_MBAR2 + 0x00000440)
+#define MMAP_UART2		(CONFIG_SYS_MBAR2 + 0x00000C00)
+
+#include <asm/coldfire/ata.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/qspi.h>
+
+typedef struct canex_ctrl {
+	can_msg_t msg[32];	/* 0x80 Message Buffer 0-31 */
+} canex_t;
+
+#endif				/* __IMMAP_5253__ */
diff --git a/include/asm-m68k/immap_5271.h b/include/asm-m68k/immap_5271.h
index d9dc015..8ddec5c 100644
--- a/include/asm-m68k/immap_5271.h
+++ b/include/asm-m68k/immap_5271.h
@@ -26,73 +26,50 @@
 #ifndef __IMMAP_5271__
 #define __IMMAP_5271__
 
-#define MMAP_SCM	(CFG_MBAR + 0x00000000)
-#define MMAP_SDRAM	(CFG_MBAR + 0x00000040)
-#define MMAP_FBCS	(CFG_MBAR + 0x00000080)
-#define MMAP_DMA0	(CFG_MBAR + 0x00000100)
-#define MMAP_DMA1	(CFG_MBAR + 0x00000110)
-#define MMAP_DMA2	(CFG_MBAR + 0x00000120)
-#define MMAP_DMA3	(CFG_MBAR + 0x00000130)
-#define MMAP_UART0	(CFG_MBAR + 0x00000200)
-#define MMAP_UART1	(CFG_MBAR + 0x00000240)
-#define MMAP_UART2	(CFG_MBAR + 0x00000280)
-#define MMAP_I2C	(CFG_MBAR + 0x00000300)
-#define MMAP_QSPI	(CFG_MBAR + 0x00000340)
-#define MMAP_DTMR0	(CFG_MBAR + 0x00000400)
-#define MMAP_DTMR1	(CFG_MBAR + 0x00000440)
-#define MMAP_DTMR2	(CFG_MBAR + 0x00000480)
-#define MMAP_DTMR3	(CFG_MBAR + 0x000004C0)
-#define MMAP_INTC0	(CFG_MBAR + 0x00000C00)
-#define MMAP_INTC1	(CFG_MBAR + 0x00000D00)
-#define MMAP_INTCACK	(CFG_MBAR + 0x00000F00)
-#define MMAP_FEC	(CFG_MBAR + 0x00001000)
-#define MMAP_FECFIFO	(CFG_MBAR + 0x00001400)
-#define MMAP_GPIO	(CFG_MBAR + 0x00100000)
-#define MMAP_CCM	(CFG_MBAR + 0x00110000)
-#define MMAP_PLL	(CFG_MBAR + 0x00120000)
-#define MMAP_EPORT	(CFG_MBAR + 0x00130000)
-#define MMAP_WDOG	(CFG_MBAR + 0x00140000)
-#define MMAP_PIT0	(CFG_MBAR + 0x00150000)
-#define MMAP_PIT1	(CFG_MBAR + 0x00160000)
-#define MMAP_PIT2	(CFG_MBAR + 0x00170000)
-#define MMAP_PIT3	(CFG_MBAR + 0x00180000)
-#define MMAP_MDHA	(CFG_MBAR + 0x00190000)
-#define MMAP_RNG	(CFG_MBAR + 0x001A0000)
-#define MMAP_SKHA	(CFG_MBAR + 0x001B0000)
-#define MMAP_CAN1	(CFG_MBAR + 0x001C0000)
-#define MMAP_ETPU	(CFG_MBAR + 0x001D0000)
-#define MMAP_CAN2	(CFG_MBAR + 0x001F0000)
+#define MMAP_SCM	(CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1	(CONFIG_SYS_MBAR + 0x00000110)
+#define MMAP_DMA2	(CONFIG_SYS_MBAR + 0x00000120)
+#define MMAP_DMA3	(CONFIG_SYS_MBAR + 0x00000130)
+#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC	(CONFIG_SYS_MBAR + 0x00001000)
+#define MMAP_FECFIFO	(CONFIG_SYS_MBAR + 0x00001400)
+#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00100000)
+#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x00110000)
+#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x00180000)
+#define MMAP_MDHA	(CONFIG_SYS_MBAR + 0x00190000)
+#define MMAP_RNG	(CONFIG_SYS_MBAR + 0x001A0000)
+#define MMAP_SKHA	(CONFIG_SYS_MBAR + 0x001B0000)
+#define MMAP_CAN1	(CONFIG_SYS_MBAR + 0x001C0000)
+#define MMAP_ETPU	(CONFIG_SYS_MBAR + 0x001D0000)
+#define MMAP_CAN2	(CONFIG_SYS_MBAR + 0x001F0000)
+
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/mdha.h>
+#include <asm/coldfire/qspi.h>
+#include <asm/coldfire/rng.h>
+#include <asm/coldfire/skha.h>
 
-/* Interrupt module registers */
-typedef struct int0_ctrl {
-	/* Interrupt Controller 0 */
-	u32 iprh0;		/* 0x00 Pending Register High */
-	u32 iprl0;		/* 0x04 Pending Register Low */
-	u32 imrh0;		/* 0x08 Mask Register High */
-	u32 imrl0;		/* 0x0C Mask Register Low */
-	u32 frch0;		/* 0x10 Force Register High */
-	u32 frcl0;		/* 0x14 Force Register Low */
-	u8 irlr;		/* 0x18 */
-	u8 iacklpr;		/* 0x19 */
-	u16 res1[19];		/* 0x1a - 0x3c */
-	u8 icr0[64];		/* 0x40 - 0x7F Control registers */
-	u32 res3[24];		/* 0x80 - 0xDF */
-	u8 swiack0;		/* 0xE0 Software Interrupt Acknowledge */
-	u8 res4[3];		/* 0xE1 - 0xE3 */
-	u8 Lniack0_1;		/* 0xE4 Level n interrupt acknowledge resister */
-	u8 res5[3];		/* 0xE5 - 0xE7 */
-	u8 Lniack0_2;		/* 0xE8 Level n interrupt acknowledge resister */
-	u8 res6[3];		/* 0xE9 - 0xEB */
-	u8 Lniack0_3;		/* 0xEC Level n interrupt acknowledge resister */
-	u8 res7[3];		/* 0xED - 0xEF */
-	u8 Lniack0_4;		/* 0xF0 Level n interrupt acknowledge resister */
-	u8 res8[3];		/* 0xF1 - 0xF3 */
-	u8 Lniack0_5;		/* 0xF4 Level n interrupt acknowledge resister */
-	u8 res9[3];		/* 0xF5 - 0xF7 */
-	u8 Lniack0_6;		/* 0xF8 Level n interrupt acknowledge resister */
-	u8 resa[3];		/* 0xF9 - 0xFB */
-	u8 Lniack0_7;		/* 0xFC Level n interrupt acknowledge resister */
-	u8 resb[3];		/* 0xFD - 0xFF */
-} int0_t;
 
 #endif				/* __IMMAP_5271__ */
diff --git a/include/asm-m68k/immap_5272.h b/include/asm-m68k/immap_5272.h
index 2ebb140..8d4254b 100644
--- a/include/asm-m68k/immap_5272.h
+++ b/include/asm-m68k/immap_5272.h
@@ -25,24 +25,26 @@
 #ifndef __IMMAP_5272__
 #define __IMMAP_5272__
 
-#define MMAP_CFG	(CFG_MBAR + 0x00000000)
-#define MMAP_INTC	(CFG_MBAR + 0x00000020)
-#define MMAP_FBCS	(CFG_MBAR + 0x00000040)
-#define MMAP_GPIO	(CFG_MBAR + 0x00000080)
-#define MMAP_QSPI	(CFG_MBAR + 0x000000A0)
-#define MMAP_PWM	(CFG_MBAR + 0x000000C0)
-#define MMAP_DMA0	(CFG_MBAR + 0x000000E0)
-#define MMAP_UART0	(CFG_MBAR + 0x00000100)
-#define MMAP_UART1	(CFG_MBAR + 0x00000140)
-#define MMAP_SDRAM	(CFG_MBAR + 0x00000180)
-#define MMAP_TMR0	(CFG_MBAR + 0x00000200)
-#define MMAP_TMR1	(CFG_MBAR + 0x00000220)
-#define MMAP_TMR2	(CFG_MBAR + 0x00000240)
-#define MMAP_TMR3	(CFG_MBAR + 0x00000260)
-#define MMAP_WDOG	(CFG_MBAR + 0x00000280)
-#define MMAP_PLIC	(CFG_MBAR + 0x00000300)
-#define MMAP_FEC	(CFG_MBAR + 0x00000840)
-#define MMAP_USB	(CFG_MBAR + 0x00001000)
+#define MMAP_CFG	(CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_INTC	(CONFIG_SYS_MBAR + 0x00000020)
+#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x000000A0)
+#define MMAP_PWM	(CONFIG_SYS_MBAR + 0x000000C0)
+#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x000000E0)
+#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000100)
+#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000140)
+#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000180)
+#define MMAP_TMR0	(CONFIG_SYS_MBAR + 0x00000200)
+#define MMAP_TMR1	(CONFIG_SYS_MBAR + 0x00000220)
+#define MMAP_TMR2	(CONFIG_SYS_MBAR + 0x00000240)
+#define MMAP_TMR3	(CONFIG_SYS_MBAR + 0x00000260)
+#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00000280)
+#define MMAP_PLIC	(CONFIG_SYS_MBAR + 0x00000300)
+#define MMAP_FEC	(CONFIG_SYS_MBAR + 0x00000840)
+#define MMAP_USB	(CONFIG_SYS_MBAR + 0x00001000)
+
+#include <asm/coldfire/pwm.h>
 
 /* System configuration registers */
 typedef struct sys_ctrl {
@@ -104,38 +106,6 @@ typedef struct gpio_ctrl {
 	uchar res2[4];
 } gpio_t;
 
-/* QSPI module registers */
-typedef struct qspi_ctrl {
-	ushort qspi_qmr;
-	uchar res1[2];
-	ushort qspi_qdlyr;
-	uchar res2[2];
-	ushort qspi_qwr;
-	uchar res3[2];
-	ushort qspi_qir;
-	uchar res4[2];
-	ushort qspi_qar;
-	uchar res5[2];
-	ushort qspi_qdr;
-	uchar res6[10];
-} qspi_t;
-
-/* PWM module registers */
-typedef struct pwm_ctrl {
-	uchar pwm_pwcr0;
-	uchar res1[3];
-	uchar pwm_pwcr1;
-	uchar res2[3];
-	uchar pwm_pwcr2;
-	uchar res3[7];
-	uchar pwm_pwwd0;
-	uchar res4[3];
-	uchar pwm_pwwd1;
-	uchar res5[3];
-	uchar pwm_pwwd2;
-	uchar res6[7];
-} pwm_t;
-
 /* DMA module registers */
 typedef struct dma_ctrl {
 	ulong dma_dmr;
diff --git a/include/asm-m68k/immap_5275.h b/include/asm-m68k/immap_5275.h
index 774866e..46426a3 100644
--- a/include/asm-m68k/immap_5275.h
+++ b/include/asm-m68k/immap_5275.h
@@ -27,44 +27,53 @@
 #ifndef __IMMAP_5275__
 #define __IMMAP_5275__
 
-#define MMAP_SCM	(CFG_MBAR + 0x00000000)
-#define MMAP_SDRAM	(CFG_MBAR + 0x00000040)
-#define MMAP_FBCS	(CFG_MBAR + 0x00000080)
-#define MMAP_DMA0	(CFG_MBAR + 0x00000100)
-#define MMAP_DMA1	(CFG_MBAR + 0x00000110)
-#define MMAP_DMA2	(CFG_MBAR + 0x00000120)
-#define MMAP_DMA3	(CFG_MBAR + 0x00000130)
-#define MMAP_UART0	(CFG_MBAR + 0x00000200)
-#define MMAP_UART1	(CFG_MBAR + 0x00000240)
-#define MMAP_UART2	(CFG_MBAR + 0x00000280)
-#define MMAP_I2C	(CFG_MBAR + 0x00000300)
-#define MMAP_QSPI	(CFG_MBAR + 0x00000340)
-#define MMAP_DTMR0	(CFG_MBAR + 0x00000400)
-#define MMAP_DTMR1	(CFG_MBAR + 0x00000440)
-#define MMAP_DTMR2	(CFG_MBAR + 0x00000480)
-#define MMAP_DTMR3	(CFG_MBAR + 0x000004C0)
-#define MMAP_INTC0	(CFG_MBAR + 0x00000C00)
-#define MMAP_INTC1	(CFG_MBAR + 0x00000D00)
-#define MMAP_INTCACK	(CFG_MBAR + 0x00000F00)
-#define MMAP_FEC0	(CFG_MBAR + 0x00001000)
-#define MMAP_FEC0FIFO	(CFG_MBAR + 0x00001400)
-#define MMAP_FEC1	(CFG_MBAR + 0x00001800)
-#define MMAP_FEC1FIFO	(CFG_MBAR + 0x00001C00)
-#define MMAP_GPIO	(CFG_MBAR + 0x00100000)
-#define MMAP_RCM	(CFG_MBAR + 0x00110000)
-#define MMAP_CCM	(CFG_MBAR + 0x00110004)
-#define MMAP_PLL	(CFG_MBAR + 0x00120000)
-#define MMAP_EPORT	(CFG_MBAR + 0x00130000)
-#define MMAP_WDOG	(CFG_MBAR + 0x00140000)
-#define MMAP_PIT0	(CFG_MBAR + 0x00150000)
-#define MMAP_PIT1	(CFG_MBAR + 0x00160000)
-#define MMAP_PIT2	(CFG_MBAR + 0x00170000)
-#define MMAP_PIT3	(CFG_MBAR + 0x00180000)
-#define MMAP_MDHA	(CFG_MBAR + 0x00190000)
-#define MMAP_RNG	(CFG_MBAR + 0x001A0000)
-#define MMAP_SKHA	(CFG_MBAR + 0x001B0000)
-#define MMAP_USB	(CFG_MBAR + 0x001C0000)
-#define MMAP_PWM0	(CFG_MBAR + 0x001D0000)
+#define MMAP_SCM	(CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1	(CONFIG_SYS_MBAR + 0x00000110)
+#define MMAP_DMA2	(CONFIG_SYS_MBAR + 0x00000120)
+#define MMAP_DMA3	(CONFIG_SYS_MBAR + 0x00000130)
+#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC0	(CONFIG_SYS_MBAR + 0x00001000)
+#define MMAP_FEC0FIFO	(CONFIG_SYS_MBAR + 0x00001400)
+#define MMAP_FEC1	(CONFIG_SYS_MBAR + 0x00001800)
+#define MMAP_FEC1FIFO	(CONFIG_SYS_MBAR + 0x00001C00)
+#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00100000)
+#define MMAP_RCM	(CONFIG_SYS_MBAR + 0x00110000)
+#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x00110004)
+#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x00180000)
+#define MMAP_MDHA	(CONFIG_SYS_MBAR + 0x00190000)
+#define MMAP_RNG	(CONFIG_SYS_MBAR + 0x001A0000)
+#define MMAP_SKHA	(CONFIG_SYS_MBAR + 0x001B0000)
+#define MMAP_USB	(CONFIG_SYS_MBAR + 0x001C0000)
+#define MMAP_PWM0	(CONFIG_SYS_MBAR + 0x001D0000)
+
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/mdha.h>
+#include <asm/coldfire/pwm.h>
+#include <asm/coldfire/qspi.h>
+#include <asm/coldfire/rng.h>
+#include <asm/coldfire/skha.h>
 
 /* System configuration registers
 */
@@ -109,51 +118,6 @@ typedef struct sdram_ctrl {
 	u32 sdbmr1;
 } sdramctrl_t;
 
-/* Chip select module registers, offset: 0x080
-*/
-typedef struct	cs_ctlr {
-	u16 ar0;
-	u16 res1;
-	u32 mr0;
-	u16 res2;
-	u16 cr0;
-	u16 ar1;
-	u16 res3;
-	u32 mr1;
-	u16 res4;
-	u16 cr1;
-	u16 ar2;
-	u16 res5;
-	u32 mr2;
-	u16 res6;
-	u16 cr2;
-	u16 ar3;
-	u16 res7;
-	u32 mr3;
-	u16 res8;
-	u16 cr3;
-	u16 ar4;
-	u16 res9;
-	u32 mr4;
-	u16 res10;
-	u16 cr4;
-	u16 ar5;
-	u16 res11;
-	u32 mr5;
-	u16 res12;
-	u16 cr5;
-	u16 ar6;
-	u16 res13;
-	u32 mr6;
-	u16 res14;
-	u16 cr6;
-	u16 ar7;
-	u16 res15;
-	u32 mr7;
-	u16 res16;
-	u16 cr7;
-} csctrl_t;
-
 /* DMA module registers, offset 0x100
  */
 typedef struct	dma_ctrl {
@@ -163,55 +127,6 @@ typedef struct	dma_ctrl {
 	u32 dcr;
 } dma_t;
 
-/* QSPI module registers, offset 0x340
- */
-typedef struct	qspi_ctrl {
-	u16 qmr;
-	u8 res1[2];
-	u16 qdlyr;
-	u8 res2[2];
-	u16 qwr;
-	u8 res3[2];
-	u16 qir;
-	u8 res4[2];
-	u16 qar;
-	u8 res5[2];
-	u16 qdr;
-	u8 res6[2];
-} qspi_t;
-
-/* Interrupt module registers, offset 0xc00
-*/
-typedef struct int_ctrl {
-	u32 iprh0;
-	u32 iprl0;
-	u32 imrh0;
-	u32 imrl0;
-	u32 frch0;
-	u32 frcl0;
-	u8 irlr;
-	u8 iacklpr;
-	u8 res1[0x26];
-	u8 icr0[64]; /* No ICR0, done this way for readability */
-	u8 res2[0x60];
-	u8 swiack0;
-	u8 res3[3];
-	u8 Lniack0_1;
-	u8 res4[3];
-	u8 Lniack0_2;
-	u8 res5[3];
-	u8 Lniack0_3;
-	u8 res6[3];
-	u8 Lniack0_4;
-	u8 res7[3];
-	u8 Lniack0_5;
-	u8 res8[3];
-	u8 Lniack0_6;
-	u8 res9[3];
-	u8 Lniack0_7;
-	u8 res10[3];
-} int0_t;
-
 /* GPIO port registers
 */
 typedef struct	gpio_ctrl {
@@ -325,23 +240,6 @@ typedef struct	gpio_ctrl {
 } gpio_t;
 
 
-/* PWM module registers
- */
-typedef struct	pwm_ctrl {
-	u8 pwcr0;
-	u8 res1[3];
-	u8 pwcr1;
-	u8 res2[3];
-	u8 pwcr2;
-	u8 res3[7];
-	u8 pwwd0;
-	u8 res4[3];
-	u8 pwwd1;
-	u8 res5[3];
-	u8 pwwd2;
-	u8 res6[7];
-} pwm_t;
-
 /* Watchdog registers
  */
 typedef struct wdog_ctrl {
diff --git a/include/asm-m68k/immap_5282.h b/include/asm-m68k/immap_5282.h
index e82960a..dd526a1 100644
--- a/include/asm-m68k/immap_5282.h
+++ b/include/asm-m68k/immap_5282.h
@@ -25,42 +25,48 @@
 #ifndef __IMMAP_5282__
 #define __IMMAP_5282__
 
-#define MMAP_SCM	(CFG_MBAR + 0x00000000)
-#define MMAP_SDRAMC	(CFG_MBAR + 0x00000040)
-#define MMAP_FBCS	(CFG_MBAR + 0x00000080)
-#define MMAP_DMA0	(CFG_MBAR + 0x00000100)
-#define MMAP_DMA1	(CFG_MBAR + 0x00000140)
-#define MMAP_DMA2	(CFG_MBAR + 0x00000180)
-#define MMAP_DMA3	(CFG_MBAR + 0x000001C0)
-#define MMAP_UART0	(CFG_MBAR + 0x00000200)
-#define MMAP_UART1	(CFG_MBAR + 0x00000240)
-#define MMAP_UART2	(CFG_MBAR + 0x00000280)
-#define MMAP_I2C	(CFG_MBAR + 0x00000300)
-#define MMAP_QSPI	(CFG_MBAR + 0x00000340)
-#define MMAP_DTMR0	(CFG_MBAR + 0x00000400)
-#define MMAP_DTMR1	(CFG_MBAR + 0x00000440)
-#define MMAP_DTMR2	(CFG_MBAR + 0x00000480)
-#define MMAP_DTMR3	(CFG_MBAR + 0x000004C0)
-#define MMAP_INTC0	(CFG_MBAR + 0x00000C00)
-#define MMAP_INTC1	(CFG_MBAR + 0x00000D00)
-#define MMAP_INTCACK	(CFG_MBAR + 0x00000F00)
-#define MMAP_FEC	(CFG_MBAR + 0x00001000)
-#define MMAP_FECFIFO	(CFG_MBAR + 0x00001400)
-#define MMAP_GPIO	(CFG_MBAR + 0x00100000)
-#define MMAP_CCM	(CFG_MBAR + 0x00110000)
-#define MMAP_PLL	(CFG_MBAR + 0x00120000)
-#define MMAP_EPORT	(CFG_MBAR + 0x00130000)
-#define MMAP_WDOG	(CFG_MBAR + 0x00140000)
-#define MMAP_PIT0	(CFG_MBAR + 0x00150000)
-#define MMAP_PIT1	(CFG_MBAR + 0x00160000)
-#define MMAP_PIT2	(CFG_MBAR + 0x00170000)
-#define MMAP_PIT3	(CFG_MBAR + 0x00180000)
-#define MMAP_QADC	(CFG_MBAR + 0x00190000)
-#define MMAP_GPTMRA	(CFG_MBAR + 0x001A0000)
-#define MMAP_GPTMRB	(CFG_MBAR + 0x001B0000)
-#define MMAP_CAN	(CFG_MBAR + 0x001C0000)
-#define MMAP_CFMC	(CFG_MBAR + 0x001D0000)
-#define MMAP_CFMMEM	(CFG_MBAR + 0x04000000)
+#define MMAP_SCM	(CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAMC	(CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1	(CONFIG_SYS_MBAR + 0x00000140)
+#define MMAP_DMA2	(CONFIG_SYS_MBAR + 0x00000180)
+#define MMAP_DMA3	(CONFIG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC	(CONFIG_SYS_MBAR + 0x00001000)
+#define MMAP_FECFIFO	(CONFIG_SYS_MBAR + 0x00001400)
+#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00100000)
+#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x00110000)
+#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x00180000)
+#define MMAP_QADC	(CONFIG_SYS_MBAR + 0x00190000)
+#define MMAP_GPTMRA	(CONFIG_SYS_MBAR + 0x001A0000)
+#define MMAP_GPTMRB	(CONFIG_SYS_MBAR + 0x001B0000)
+#define MMAP_CAN	(CONFIG_SYS_MBAR + 0x001C0000)
+#define MMAP_CFMC	(CONFIG_SYS_MBAR + 0x001D0000)
+#define MMAP_CFMMEM	(CONFIG_SYS_MBAR + 0x04000000)
+
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/qspi.h>
 
 /* System Control Module */
 typedef struct scm_ctrl {
@@ -92,88 +98,9 @@ typedef struct scm_ctrl {
 	u16 res8;
 } scm_t;
 
-/* Flexbus module Chip select registers */
-typedef struct fbcs_ctrl {
-	u16 csar0;		/* 0x00 Chip-Select Address Register 0 */
-	u16 res0;
-	u32 csmr0;		/* 0x04 Chip-Select Mask Register 0 */
-	u16 res1;		/* 0x08 */
-	u16 cscr0;		/* 0x0A Chip-Select Control Register 0 */
-
-	u16 csar1;		/* 0x0C Chip-Select Address Register 1 */
-	u16 res2;
-	u32 csmr1;		/* 0x10 Chip-Select Mask Register 1 */
-	u16 res3;		/* 0x14 */
-	u16 cscr1;		/* 0x16 Chip-Select Control Register 1 */
-
-	u16 csar2;		/* 0x18 Chip-Select Address Register 2 */
-	u16 res4;
-	u32 csmr2;		/* 0x1C Chip-Select Mask Register 2 */
-	u16 res5;		/* 0x20 */
-	u16 cscr2;		/* 0x22 Chip-Select Control Register 2 */
-
-	u16 csar3;		/* 0x24 Chip-Select Address Register 3 */
-	u16 res6;
-	u32 csmr3;		/* 0x28 Chip-Select Mask Register 3 */
-	u16 res7;		/* 0x2C */
-	u16 cscr3;		/* 0x2E Chip-Select Control Register 3 */
-
-	u16 csar4;		/* 0x30 Chip-Select Address Register 4 */
-	u16 res8;
-	u32 csmr4;		/* 0x34 Chip-Select Mask Register 4 */
-	u16 res9;		/* 0x38 */
-	u16 cscr4;		/* 0x3A Chip-Select Control Register 4 */
-
-	u16 csar5;		/* 0x3C Chip-Select Address Register 5 */
-	u16 res10;
-	u32 csmr5;		/* 0x40 Chip-Select Mask Register 5 */
-	u16 res11;		/* 0x44 */
-	u16 cscr5;		/* 0x46 Chip-Select Control Register 5 */
-
-	u16 csar6;		/* 0x48 Chip-Select Address Register 5 */
-	u16 res12;
-	u32 csmr6;		/* 0x4C Chip-Select Mask Register 5 */
-	u16 res13;		/* 0x50 */
-	u16 cscr6;		/* 0x52 Chip-Select Control Register 5 */
-
-	u16 csar7;		/* 0x54 Chip-Select Address Register 5 */
-	u16 res14;
-	u32 csmr7;		/* 0x58 Chip-Select Mask Register 5 */
-	u16 res15;		/* 0x5C */
-	u16 cscr7;		/* 0x5E Chip-Select Control Register 5 */
-} fbcs_t;
-
-/* Interrupt module registers */
-typedef struct int0_ctrl {
-	/* Interrupt Controller 0 */
-	u32 iprh0;		/* 0x00 Pending Register High */
-	u32 iprl0;		/* 0x04 Pending Register Low */
-	u32 imrh0;		/* 0x08 Mask Register High */
-	u32 imrl0;		/* 0x0C Mask Register Low */
-	u32 frch0;		/* 0x10 Force Register High */
-	u32 frcl0;		/* 0x14 Force Register Low */
-	u8 irlr;		/* 0x18 */
-	u8 iacklpr;		/* 0x19 */
-	u16 res1[19];		/* 0x1a - 0x3c */
-	u8 icr0[64];		/* 0x40 - 0x7F Control registers */
-	u32 res3[24];		/* 0x80 - 0xDF */
-	u8 swiack0;		/* 0xE0 Software Interrupt Acknowledge */
-	u8 res4[3];		/* 0xE1 - 0xE3 */
-	u8 Lniack0_1;		/* 0xE4 Level n interrupt acknowledge resister */
-	u8 res5[3];		/* 0xE5 - 0xE7 */
-	u8 Lniack0_2;		/* 0xE8 Level n interrupt acknowledge resister */
-	u8 res6[3];		/* 0xE9 - 0xEB */
-	u8 Lniack0_3;		/* 0xEC Level n interrupt acknowledge resister */
-	u8 res7[3];		/* 0xED - 0xEF */
-	u8 Lniack0_4;		/* 0xF0 Level n interrupt acknowledge resister */
-	u8 res8[3];		/* 0xF1 - 0xF3 */
-	u8 Lniack0_5;		/* 0xF4 Level n interrupt acknowledge resister */
-	u8 res9[3];		/* 0xF5 - 0xF7 */
-	u8 Lniack0_6;		/* 0xF8 Level n interrupt acknowledge resister */
-	u8 resa[3];		/* 0xF9 - 0xFB */
-	u8 Lniack0_7;		/* 0xFC Level n interrupt acknowledge resister */
-	u8 resb[3];		/* 0xFD - 0xFF */
-} int0_t;
+typedef struct canex_ctrl {
+	can_msg_t msg[16];	/* 0x00 Message Buffer 0-15 */
+} canex_t;
 
 /* Clock Module registers */
 typedef struct pll_ctrl {
diff --git a/include/asm-m68k/immap_5301x.h b/include/asm-m68k/immap_5301x.h
new file mode 100644
index 0000000..87ac770
--- /dev/null
+++ b/include/asm-m68k/immap_5301x.h
@@ -0,0 +1,324 @@
+/*
+ * MCF5301x Internal Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5301X__
+#define __IMMAP_5301X__
+
+#define MMAP_SCM1	(CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_XBS	(CONFIG_SYS_MBAR + 0x00004000)
+#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00008000)
+#define MMAP_MPU	(CONFIG_SYS_MBAR + 0x00014000)
+#define MMAP_FEC0	(CONFIG_SYS_MBAR + 0x00030000)
+#define MMAP_FEC1	(CONFIG_SYS_MBAR + 0x00034000)
+#define MMAP_SCM2	(CONFIG_SYS_MBAR + 0x00040000)
+#define MMAP_EDMA	(CONFIG_SYS_MBAR + 0x00044000)
+#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00048000)
+#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x0004C000)
+#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00054000)
+#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00058000)
+#define MMAP_DSPI	(CONFIG_SYS_MBAR + 0x0005C000)
+#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00060000)
+#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00064000)
+#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00068000)
+#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00070000)
+#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00074000)
+#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00078000)
+#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x0007C000)
+#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00080000)
+#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00084000)
+#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00088000)
+#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x0008C000)
+#define MMAP_EPORT0	(CONFIG_SYS_MBAR + 0x00090000)
+#define MMAP_EPORT1	(CONFIG_SYS_MBAR + 0x00094000)
+#define MMAP_VOICOD	(CONFIG_SYS_MBAR + 0x0009C000)
+#define MMAP_RCM	(CONFIG_SYS_MBAR + 0x000A0000)
+#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x000A0004)
+#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x000A4000)
+#define MMAP_RTC	(CONFIG_SYS_MBAR + 0x000A8000)
+#define MMAP_SIM	(CONFIG_SYS_MBAR + 0x000AC000)
+#define MMAP_USBOTG	(CONFIG_SYS_MBAR + 0x000B0000)
+#define MMAP_USBH	(CONFIG_SYS_MBAR + 0x000B4000)
+#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x000B8000)
+#define MMAP_SSI	(CONFIG_SYS_MBAR + 0x000BC000)
+#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x000C0000)
+#define MMAP_RNG	(CONFIG_SYS_MBAR + 0x000C4000)
+#define MMAP_IIM	(CONFIG_SYS_MBAR + 0x000C8000)
+#define MMAP_ESDHC	(CONFIG_SYS_MBAR + 0x000CC000)
+
+#include <asm/coldfire/crossbar.h>
+#include <asm/coldfire/dspi.h>
+#include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/ssi.h>
+#include <asm/coldfire/rng.h>
+#include <asm/rtc.h>
+
+/* System Controller Module */
+typedef struct scm1 {
+	u32 mpr;		/* 0x00 Master Privilege */
+	u32 rsvd1[7];
+	u32 pacra;		/* 0x20 Peripheral Access Ctrl A */
+	u32 pacrb;		/* 0x24 Peripheral Access Ctrl B */
+	u32 pacrc;		/* 0x28 Peripheral Access Ctrl C */
+	u32 pacrd;		/* 0x2C Peripheral Access Ctrl D */
+	u32 rsvd2[4];
+	u32 pacre;		/* 0x40 Peripheral Access Ctrl E */
+	u32 pacrf;		/* 0x44 Peripheral Access Ctrl F */
+	u32 pacrg;		/* 0x48 Peripheral Access Ctrl G */
+} scm1_t;
+
+typedef struct scm2 {
+	u8 rsvd1[19];		/* 0x00 - 0x12 */
+	u8 wcr;			/* 0x13 */
+	u16 rsvd2;		/* 0x14 - 0x15 */
+	u16 cwcr;		/* 0x16 */
+	u8 rsvd3[3];		/* 0x18 - 0x1A */
+	u8 cwsr;		/* 0x1B */
+	u8 rsvd4[3];		/* 0x1C - 0x1E */
+	u8 scmisr;		/* 0x1F */
+	u32 rsvd5;		/* 0x20 - 0x23 */
+	u8 bcr;			/* 0x24 */
+	u8 rsvd6[74];		/* 0x25 - 0x6F */
+	u32 cfadr;		/* 0x70 */
+	u8 rsvd7;		/* 0x74 */
+	u8 cfier;		/* 0x75 */
+	u8 cfloc;		/* 0x76 */
+	u8 cfatr;		/* 0x77 */
+	u32 rsvd8;		/* 0x78 - 0x7B */
+	u32 cfdtr;		/* 0x7C */
+} scm2_t;
+
+/* PWM module */
+typedef struct pwm_ctrl {
+	u8 en;			/* 0x00 PWM Enable */
+	u8 pol;			/* 0x01 Polarity */
+	u8 clk;			/* 0x02 Clock Select */
+	u8 prclk;		/* 0x03 Prescale Clock Select */
+	u8 cae;			/* 0x04 Center Align Enable */
+	u8 ctl;			/* 0x05 Ctrl */
+	u8 res1[2];		/* 0x06 - 0x07 */
+	u8 scla;		/* 0x08 Scale A */
+	u8 sclb;		/* 0x09 Scale B */
+	u8 res2[2];		/* 0x0A - 0x0B */
+	u8 cnt0;		/* 0x0C Channel 0 Counter */
+	u8 cnt1;		/* 0x0D Channel 1 Counter */
+	u8 cnt2;		/* 0x0E Channel 2 Counter */
+	u8 cnt3;		/* 0x0F Channel 3 Counter */
+	u8 cnt4;		/* 0x10 Channel 4 Counter */
+	u8 cnt5;		/* 0x11 Channel 5 Counter */
+	u8 cnt6;		/* 0x12 Channel 6 Counter */
+	u8 cnt7;		/* 0x13 Channel 7 Counter */
+	u8 per0;		/* 0x14 Channel 0 Period */
+	u8 per1;		/* 0x15 Channel 1 Period */
+	u8 per2;		/* 0x16 Channel 2 Period */
+	u8 per3;		/* 0x17 Channel 3 Period */
+	u8 per4;		/* 0x18 Channel 4 Period */
+	u8 per5;		/* 0x19 Channel 5 Period */
+	u8 per6;		/* 0x1A Channel 6 Period */
+	u8 per7;		/* 0x1B Channel 7 Period */
+	u8 dty0;		/* 0x1C Channel 0 Duty */
+	u8 dty1;		/* 0x1D Channel 1 Duty */
+	u8 dty2;		/* 0x1E Channel 2 Duty */
+	u8 dty3;		/* 0x1F Channel 3 Duty */
+	u8 dty4;		/* 0x20 Channel 4 Duty */
+	u8 dty5;		/* 0x21 Channel 5 Duty */
+	u8 dty6;		/* 0x22 Channel 6 Duty */
+	u8 dty7;		/* 0x23 Channel 7 Duty */
+	u8 sdn;			/* 0x24 Shutdown */
+	u8 res3[3];		/* 0x25 - 0x27 */
+} pwm_t;
+
+/* Chip configuration module */
+typedef struct rcm {
+	u8 rcr;
+	u8 rsr;
+} rcm_t;
+
+typedef struct ccm_ctrl {
+	u16 ccr;		/* 0x00 Chip Cfg */
+	u16 res1;		/* 0x02 */
+	u16 rcon;		/* 0x04 Reset Cfg */
+	u16 cir;		/* 0x06 Chip ID */
+	u32 res2;		/* 0x08 */
+	u16 misccr;		/* 0x0A Misc Ctrl */
+	u16 cdr;		/* 0x0C Clock divider */
+	u16 uhcsr;		/* 0x10 USB Host status */
+	u16 uocsr;		/* 0x12 USB On-the-Go Status */
+	u16 res3;		/* 0x14 */
+	u16 codeccr;		/* 0x16 Codec Control */
+	u16 misccr2;		/* 0x18 Misc2 Ctrl */
+} ccm_t;
+
+/* GPIO port */
+typedef struct gpio_ctrl {
+	/* Port Output Data */
+	u8 podr_fbctl;		/* 0x00 */
+	u8 podr_be;		/* 0x01 */
+	u8 podr_cs;		/* 0x02 */
+	u8 podr_dspi;		/* 0x03 */
+	u8 res01;		/* 0x04 */
+	u8 podr_fec0;		/* 0x05 */
+	u8 podr_feci2c;		/* 0x06 */
+	u8 res02[2];		/* 0x07 - 0x08 */
+	u8 podr_simp1;		/* 0x09 */
+	u8 podr_simp0;		/* 0x0A */
+	u8 podr_timer;		/* 0x0B */
+	u8 podr_uart;		/* 0x0C */
+	u8 podr_debug;		/* 0x0D */
+	u8 res03;		/* 0x0E */
+	u8 podr_sdhc;		/* 0x0F */
+	u8 podr_ssi;		/* 0x10 */
+	u8 res04[3];		/* 0x11 - 0x13 */
+
+	/* Port Data Direction */
+	u8 pddr_fbctl;		/* 0x14 */
+	u8 pddr_be;		/* 0x15 */
+	u8 pddr_cs;		/* 0x16 */
+	u8 pddr_dspi;		/* 0x17 */
+	u8 res05;		/* 0x18 */
+	u8 pddr_fec0;		/* 0x19 */
+	u8 pddr_feci2c;		/* 0x1A */
+	u8 res06[2];		/* 0x1B - 0x1C */
+	u8 pddr_simp1;		/* 0x1D */
+	u8 pddr_simp0;		/* 0x1E */
+	u8 pddr_timer;		/* 0x1F */
+	u8 pddr_uart;		/* 0x20 */
+	u8 pddr_debug;		/* 0x21 */
+	u8 res07;		/* 0x22 */
+	u8 pddr_sdhc;		/* 0x23 */
+	u8 pddr_ssi;		/* 0x24 */
+	u8 res08[3];		/* 0x25 - 0x27 */
+
+	/* Port Data Direction */
+	u8 ppdr_fbctl;		/* 0x28 */
+	u8 ppdr_be;		/* 0x29 */
+	u8 ppdr_cs;		/* 0x2A */
+	u8 ppdr_dspi;		/* 0x2B */
+	u8 res09;		/* 0x2C */
+	u8 ppdr_fec0;		/* 0x2D */
+	u8 ppdr_feci2c;		/* 0x2E */
+	u8 res10[2];		/* 0x2F - 0x30 */
+	u8 ppdr_simp1;		/* 0x31 */
+	u8 ppdr_simp0;		/* 0x32 */
+	u8 ppdr_timer;		/* 0x33 */
+	u8 ppdr_uart;		/* 0x34 */
+	u8 ppdr_debug;		/* 0x35 */
+	u8 res11;		/* 0x36 */
+	u8 ppdr_sdhc;		/* 0x37 */
+	u8 ppdr_ssi;		/* 0x38 */
+	u8 res12[3];		/* 0x39 - 0x3B */
+
+	/* Port Clear Output Data */
+	u8 pclrr_fbctl;		/* 0x3C */
+	u8 pclrr_be;		/* 0x3D */
+	u8 pclrr_cs;		/* 0x3E */
+	u8 pclrr_dspi;		/* 0x3F */
+	u8 res13;		/* 0x40 */
+	u8 pclrr_fec0;		/* 0x41 */
+	u8 pclrr_feci2c;	/* 0x42 */
+	u8 res14[2];		/* 0x43 - 0x44 */
+	u8 pclrr_simp1;		/* 0x45 */
+	u8 pclrr_simp0;		/* 0x46 */
+	u8 pclrr_timer;		/* 0x47 */
+	u8 pclrr_uart;		/* 0x48 */
+	u8 pclrr_debug;		/* 0x49 */
+	u8 res15;		/* 0x4A */
+	u8 pclrr_sdhc;		/* 0x4B */
+	u8 pclrr_ssi;		/* 0x4C */
+	u8 res16[3];		/* 0x4D - 0x4F */
+
+	/* Pin Assignment */
+	u8 par_fbctl;		/* 0x50 */
+	u8 par_be;		/* 0x51 */
+	u8 par_cs;		/* 0x52 */
+	u8 res17;		/* 0x53 */
+	u8 par_dspih;		/* 0x54 */
+	u8 par_dspil;		/* 0x55 */
+	u8 par_fec;		/* 0x56 */
+	u8 par_feci2c;		/* 0x57 */
+	u8 par_irq0h;		/* 0x58 */
+	u8 par_irq0l;		/* 0x59 */
+	u8 par_irq1h;		/* 0x5A */
+	u8 par_irq1l;		/* 0x5B */
+	u8 par_simp1h;		/* 0x5C */
+	u8 par_simp1l;		/* 0x5D */
+	u8 par_simp0;		/* 0x5E */
+	u8 par_timer;		/* 0x5F */
+	u8 par_uart;		/* 0x60 */
+	u8 res18;		/* 0x61 */
+	u8 par_debug;		/* 0x62 */
+	u8 par_sdhc;		/* 0x63 */
+	u8 par_ssih;		/* 0x64 */
+	u8 par_ssil;		/* 0x65 */
+	u8 res19[2];		/* 0x66 - 0x67 */
+
+	/* Mode Select Control */
+	/* Drive Strength Control */
+	u8 mscr_mscr1;		/* 0x68 */
+	u8 mscr_mscr2;		/* 0x69 */
+	u8 mscr_mscr3;		/* 0x6A */
+	u8 mscr_mscr45;		/* 0x6B */
+	u8 srcr_dspi;		/* 0x6C */
+	u8 dscr_fec;		/* 0x6D */
+	u8 srcr_i2c;		/* 0x6E */
+	u8 srcr_irq;		/* 0x6F */
+
+	u8 srcr_sim;		/* 0x70 */
+	u8 srcr_timer;		/* 0x71 */
+	u8 srcr_uart;		/* 0x72 */
+	u8 res20;		/* 0x73 */
+	u8 srcr_sdhc;		/* 0x74 */
+	u8 srcr_ssi;		/* 0x75 */
+	u8 res21[2];		/* 0x76 - 0x77 */
+	u8 pcr_pcrh;		/* 0x78 */
+	u8 pcr_pcrl;		/* 0x79 */
+} gpio_t;
+
+/* SDRAM controller */
+typedef struct sdram_ctrl {
+	u32 mode;		/* 0x00 Mode/Extended Mode */
+	u32 ctrl;		/* 0x04 Ctrl */
+	u32 cfg1;		/* 0x08 Cfg 1 */
+	u32 cfg2;		/* 0x0C Cfg 2 */
+	u32 res1[64];		/* 0x10 - 0x10F */
+	u32 cs0;		/* 0x110 Chip Select 0 Cfg */
+	u32 cs1;		/* 0x114 Chip Select 1 Cfg */
+} sdram_t;
+
+/* Clock Module */
+typedef struct pll_ctrl {
+	u32 pcr;		/* 0x00 Ctrl */
+	u32 pdr;		/* 0x04 Divider */
+	u32 psr;		/* 0x08 Status */
+} pll_t;
+
+typedef struct rtcex {
+	u32 rsvd1[3];
+	u32 gocu;
+	u32 gocl;
+} rtcex_t;
+#endif				/* __IMMAP_5301X__ */
diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h
index 7678406..4f255c6 100644
--- a/include/asm-m68k/immap_5329.h
+++ b/include/asm-m68k/immap_5329.h
@@ -70,9 +70,16 @@
 
 #include <asm/coldfire/crossbar.h>
 #include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/qspi.h>
 #include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/intctrl.h>
 #include <asm/coldfire/lcd.h>
+#include <asm/coldfire/mdha.h>
+#include <asm/coldfire/pwm.h>
 #include <asm/coldfire/ssi.h>
+#include <asm/coldfire/skha.h>
 
 /* System control module registers */
 typedef struct scm1_ctrl {
@@ -83,72 +90,6 @@ typedef struct scm1_ctrl {
 	u32 bmt0;		/*0x54 Bus Monitor Timeout 0 */
 } scm1_t;
 
-/* Message Digest Hardware Accelerator */
-typedef struct mdha_ctrl {
-	u32 mdmr;		/* 0x00 MDHA Mode Register */
-	u32 mdcr;		/* 0x04 Control register */
-	u32 mdcmr;		/* 0x08 Command Register */
-	u32 mdsr;		/* 0x0C Status Register */
-	u32 mdisr;		/* 0x10 Interrupt Status Register */
-	u32 mdimr;		/* 0x14 Interrupt Mask Register */
-	u32 mddsr;		/* 0x1C Data Size Register */
-	u32 mdin;		/* 0x20 Input FIFO */
-	u32 res1[3];		/* 0x24 - 0x2F */
-	u32 mdao;		/* 0x30 Message Digest AO Register */
-	u32 mdbo;		/* 0x34 Message Digest BO Register */
-	u32 mdco;		/* 0x38 Message Digest CO Register */
-	u32 mddo;		/* 0x3C Message Digest DO Register */
-	u32 mdeo;		/* 0x40 Message Digest EO Register */
-	u32 mdmds;		/* 0x44 Message Data Size Register */
-	u32 res[10];		/* 0x48 - 0x6F */
-	u32 mda1;		/* 0x70 Message Digest A1 Register */
-	u32 mdb1;		/* 0x74 Message Digest B1 Register */
-	u32 mdc1;		/* 0x78 Message Digest C1 Register */
-	u32 mdd1;		/* 0x7C Message Digest D1 Register */
-	u32 mde1;		/* 0x80 Message Digest E1 Register */
-} mdha_t;
-
-/* Symmetric Key Hardware Accelerator */
-typedef struct skha_ctrl {
-	u32 mr;			/* 0x00 Mode Register */
-	u32 cr;			/* 0x04 Control Register */
-	u32 cmr;		/* 0x08 Command Register */
-	u32 sr;			/* 0x0C Status Register */
-	u32 esr;		/* 0x10 Error Status Register */
-	u32 emr;		/* 0x14 Error Status Mask Register) */
-	u32 ksr;		/* 0x18 Key Size Register */
-	u32 dsr;		/* 0x1C Data Size Register */
-	u32 in;			/* 0x20 Input FIFO */
-	u32 out;		/* 0x24 Output FIFO */
-	u32 res1[2];		/* 0x28 - 0x2F */
-	u32 kdr1;		/* 0x30 Key Data Register 1  */
-	u32 kdr2;		/* 0x34 Key Data Register 2 */
-	u32 kdr3;		/* 0x38 Key Data Register 3 */
-	u32 kdr4;		/* 0x3C Key Data Register 4 */
-	u32 kdr5;		/* 0x40 Key Data Register 5 */
-	u32 kdr6;		/* 0x44 Key Data Register 6 */
-	u32 res2[10];		/* 0x48 - 0x6F */
-	u32 c1;			/* 0x70 Context 1 */
-	u32 c2;			/* 0x74 Context 2 */
-	u32 c3;			/* 0x78 Context 3 */
-	u32 c4;			/* 0x7C Context 4 */
-	u32 c5;			/* 0x80 Context 5 */
-	u32 c6;			/* 0x84 Context 6 */
-	u32 c7;			/* 0x88 Context 7 */
-	u32 c8;			/* 0x8C Context 8 */
-	u32 c9;			/* 0x90 Context 9 */
-	u32 c10;		/* 0x94 Context 10 */
-	u32 c11;		/* 0x98 Context 11 */
-} skha_t;
-
-/* Random Number Generator */
-typedef struct rng_ctrl {
-	u32 rngcr;		/* 0x00 RNG Control Register */
-	u32 rngsr;		/* 0x04 RNG Status Register */
-	u32 rnger;		/* 0x08 RNG Entropy Register */
-	u32 rngout;		/* 0x0C RNG Output FIFO */
-} rng_t;
-
 /* System control module registers 2 */
 typedef struct scm2_ctrl {
 	u32 mpr1;		/* 0x00 Master Privilege Register */
@@ -165,25 +106,6 @@ typedef struct scm2_ctrl {
 	u32 bmt1;		/* 0x54 Bus Monitor Timeout 1 */
 } scm2_t;
 
-/* FlexCan module registers */
-typedef struct can_ctrl {
-	u32 mcr;		/* 0x00 Module Configuration register */
-	u32 ctrl;		/* 0x04 Control register */
-	u32 timer;		/* 0x08 Free Running Timer */
-	u32 res1;		/* 0x0C */
-	u32 rxgmask;		/* 0x10 Rx Global Mask */
-	u32 rx14mask;		/* 0x14 RxBuffer 14 Mask */
-	u32 rx15mask;		/* 0x18 RxBuffer 15 Mask */
-	u32 errcnt;		/* 0x1C Error Counter Register */
-	u32 errstat;		/* 0x20 Error and status Register */
-	u32 res2;		/* 0x24 */
-	u32 imask;		/* 0x28 Interrupt Mask Register */
-	u32 res3;		/* 0x2C */
-	u32 iflag;		/* 0x30 Interrupt Flag Register */
-	u32 res4[19];		/* 0x34 - 0x7F */
-	u32 MB0_15[2048];	/* 0x80 Message Buffer 0-15 */
-} can_t;
-
 /* System Control Module register 3 */
 typedef struct scm3_ctrl {
 	u8 res1[19];		/* 0x00 - 0x12 */
@@ -206,148 +128,9 @@ typedef struct scm3_ctrl {
 	u32 cfdtr;		/* 0x7C Core Fault Data Register */
 } scm3_t;
 
-/* Interrupt module registers */
-typedef struct int0_ctrl {
-	/* Interrupt Controller 0 */
-	u32 iprh0;		/* 0x00 Pending Register High */
-	u32 iprl0;		/* 0x04 Pending Register Low */
-	u32 imrh0;		/* 0x08 Mask Register High */
-	u32 imrl0;		/* 0x0C Mask Register Low */
-	u32 frch0;		/* 0x10 Force Register High */
-	u32 frcl0;		/* 0x14 Force Register Low */
-	u16 res1;		/* 0x18 - 0x19 */
-	u16 icfg0;		/* 0x1A Configuration Register */
-	u8 simr0;		/* 0x1C Set Interrupt Mask */
-	u8 cimr0;		/* 0x1D Clear Interrupt Mask */
-	u8 clmask0;		/* 0x1E Current Level Mask */
-	u8 slmask;		/* 0x1F Saved Level Mask */
-	u32 res2[8];		/* 0x20 - 0x3F */
-	u8 icr0[64];		/* 0x40 - 0x7F Control registers */
-	u32 res3[24];		/* 0x80 - 0xDF */
-	u8 swiack0;		/* 0xE0 Software Interrupt Acknowledge */
-	u8 res4[3];		/* 0xE1 - 0xE3 */
-	u8 Lniack0_1;		/* 0xE4 Level n interrupt acknowledge resister */
-	u8 res5[3];		/* 0xE5 - 0xE7 */
-	u8 Lniack0_2;		/* 0xE8 Level n interrupt acknowledge resister */
-	u8 res6[3];		/* 0xE9 - 0xEB */
-	u8 Lniack0_3;		/* 0xEC Level n interrupt acknowledge resister */
-	u8 res7[3];		/* 0xED - 0xEF */
-	u8 Lniack0_4;		/* 0xF0 Level n interrupt acknowledge resister */
-	u8 res8[3];		/* 0xF1 - 0xF3 */
-	u8 Lniack0_5;		/* 0xF4 Level n interrupt acknowledge resister */
-	u8 res9[3];		/* 0xF5 - 0xF7 */
-	u8 Lniack0_6;		/* 0xF8 Level n interrupt acknowledge resister */
-	u8 resa[3];		/* 0xF9 - 0xFB */
-	u8 Lniack0_7;		/* 0xFC Level n interrupt acknowledge resister */
-	u8 resb[3];		/* 0xFD - 0xFF */
-} int0_t;
-
-typedef struct int1_ctrl {
-	/* Interrupt Controller 1 */
-	u32 iprh1;		/* 0x00 Pending Register High */
-	u32 iprl1;		/* 0x04 Pending Register Low */
-	u32 imrh1;		/* 0x08 Mask Register High */
-	u32 imrl1;		/* 0x0C Mask Register Low */
-	u32 frch1;		/* 0x10 Force Register High */
-	u32 frcl1;		/* 0x14 Force Register Low */
-	u16 res1;		/* 0x18 */
-	u16 icfg1;		/* 0x1A Configuration Register */
-	u8 simr1;		/* 0x1C Set Interrupt Mask */
-	u8 cimr1;		/* 0x1D Clear Interrupt Mask */
-	u16 res2;		/* 0x1E - 0x1F */
-	u32 res3[8];		/* 0x20 - 0x3F */
-	u8 icr1[64];		/* 0x40 - 0x7F */
-	u32 res4[24];		/* 0x80 - 0xDF */
-	u8 swiack1;		/* 0xE0 Software Interrupt Acknowledge */
-	u8 res5[3];		/* 0xE1 - 0xE3 */
-	u8 Lniack1_1;		/* 0xE4 Level n interrupt acknowledge resister */
-	u8 res6[3];		/* 0xE5 - 0xE7 */
-	u8 Lniack1_2;		/* 0xE8 Level n interrupt acknowledge resister */
-	u8 res7[3];		/* 0xE9 - 0xEB */
-	u8 Lniack1_3;		/* 0xEC Level n interrupt acknowledge resister */
-	u8 res8[3];		/* 0xED - 0xEF */
-	u8 Lniack1_4;		/* 0xF0 Level n interrupt acknowledge resister */
-	u8 res9[3];		/* 0xF1 - 0xF3 */
-	u8 Lniack1_5;		/* 0xF4 Level n interrupt acknowledge resister */
-	u8 resa[3];		/* 0xF5 - 0xF7 */
-	u8 Lniack1_6;		/* 0xF8 Level n interrupt acknowledge resister */
-	u8 resb[3];		/* 0xF9 - 0xFB */
-	u8 Lniack1_7;		/* 0xFC Level n interrupt acknowledge resister */
-	u8 resc[3];		/* 0xFD - 0xFF */
-} int1_t;
-
-typedef struct intgack_ctrl1 {
-	/* Global IACK Registers */
-	u8 swiack;		/* 0xE0 Global Software Interrupt Acknowledge */
-	u8 Lniack[7];		/* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
-} intgack_t;
-
-/* QSPI module registers */
-typedef struct qspi_ctrl {
-	u16 qmr;		/* Mode register */
-	u16 res1;
-	u16 qdlyr;		/* Delay register */
-	u16 res2;
-	u16 qwr;		/* Wrap register */
-	u16 res3;
-	u16 qir;		/* Interrupt register */
-	u16 res4;
-	u16 qar;		/* Address register */
-	u16 res5;
-	u16 qdr;		/* Data register */
-	u16 res6;
-} qspi_t;
-
-/* PWM module registers */
-typedef struct pwm_ctrl {
-	u8 en;			/* 0x00 PWM Enable Register */
-	u8 pol;			/* 0x01 Polarity Register */
-	u8 clk;			/* 0x02 Clock Select Register */
-	u8 prclk;		/* 0x03 Prescale Clock Select Register */
-	u8 cae;			/* 0x04 Center Align Enable Register */
-	u8 ctl;			/* 0x05 Control Register */
-	u8 res1[2];		/* 0x06 - 0x07 */
-	u8 scla;		/* 0x08 Scale A register */
-	u8 sclb;		/* 0x09 Scale B register */
-	u8 res2[2];		/* 0x0A - 0x0B */
-	u8 cnt0;		/* 0x0C Channel 0 Counter register */
-	u8 cnt1;		/* 0x0D Channel 1 Counter register */
-	u8 cnt2;		/* 0x0E Channel 2 Counter register */
-	u8 cnt3;		/* 0x0F Channel 3 Counter register */
-	u8 cnt4;		/* 0x10 Channel 4 Counter register */
-	u8 cnt5;		/* 0x11 Channel 5 Counter register */
-	u8 cnt6;		/* 0x12 Channel 6 Counter register */
-	u8 cnt7;		/* 0x13 Channel 7 Counter register */
-	u8 per0;		/* 0x14 Channel 0 Period register */
-	u8 per1;		/* 0x15 Channel 1 Period register */
-	u8 per2;		/* 0x16 Channel 2 Period register */
-	u8 per3;		/* 0x17 Channel 3 Period register */
-	u8 per4;		/* 0x18 Channel 4 Period register */
-	u8 per5;		/* 0x19 Channel 5 Period register */
-	u8 per6;		/* 0x1A Channel 6 Period register */
-	u8 per7;		/* 0x1B Channel 7 Period register */
-	u8 dty0;		/* 0x1C Channel 0 Duty register */
-	u8 dty1;		/* 0x1D Channel 1 Duty register */
-	u8 dty2;		/* 0x1E Channel 2 Duty register */
-	u8 dty3;		/* 0x1F Channel 3 Duty register */
-	u8 dty4;		/* 0x20 Channel 4 Duty register */
-	u8 dty5;		/* 0x21 Channel 5 Duty register */
-	u8 dty6;		/* 0x22 Channel 6 Duty register */
-	u8 dty7;		/* 0x23 Channel 7 Duty register */
-	u8 sdn;			/* 0x24 Shutdown register */
-	u8 res3[3];		/* 0x25 - 0x27 */
-} pwm_t;
-
-/* Edge Port module registers */
-typedef struct eport_ctrl {
-	u16 par;		/* 0x00 Pin Assignment Register */
-	u8 ddar;		/* 0x02 Data Direction Register */
-	u8 ier;			/* 0x03 Interrupt Enable Register */
-	u8 dr;			/* 0x04 Data Register */
-	u8 pdr;			/* 0x05 Pin Data  Register */
-	u8 fr;			/* 0x06 Flag_Register */
-	u8 res1;
-} eport_t;
+typedef struct canex_ctrl {
+	can_msg_t msg[16];	/* 0x00 Message Buffer 0-15 */
+} canex_t;
 
 /* Watchdog registers */
 typedef struct wdog_ctrl {
@@ -593,53 +376,6 @@ typedef struct usb_otg {
 	u32 eptctrl3;		/* 0x1CC Endpoint control 3 */
 } usbotg_t;
 
-/* USB Host module registers */
-typedef struct usb_host {
-	u32 id;			/* 0x000 Identification Register */
-	u32 hwgeneral;		/* 0x004 General HW Parameters */
-	u32 hwhost;		/* 0x008 Host HW Parameters */
-	u32 res1;		/* 0x0C */
-	u32 hwtxbuf;		/* 0x010 TX Buffer HW Parameters */
-	u32 hwrxbuf;		/* 0x014 RX Buffer HW Parameters */
-	u32 res2[58];		/* 0x18 - 0xFF */
-
-	/* Host Controller Capability Register */
-	u8 caplength;		/* 0x100 Capability Register Length */
-	u8 res3;		/* 0x101 */
-	u16 hciver;		/* 0x102 Host Interface Version Number */
-	u32 hcsparams;		/* 0x104 Host Structural Parameters */
-	u32 hccparams;		/* 0x108 Host Capability Parameters */
-	u32 res4[13];		/* 0x10C - 0x13F */
-
-	/* Host Controller Operational Register */
-	u32 cmd;		/* 0x140 USB Command */
-	u32 sts;		/* 0x144 USB Status */
-	u32 intr;		/* 0x148 USB Interrupt Enable */
-	u32 frindex;		/* 0x14C USB Frame Index */
-	u32 res5;		/* 0x150 (ctrl segment register in EHCI spec) */
-	u32 prdlst;		/* 0x154 Periodic Frame List Base Address */
-	u32 aynclst;		/* 0x158 Current Asynchronous List Address */
-	u32 ttctrl;		/* 0x15C Host TT Asynchronous Buffer Control (non-ehci) */
-	u32 burstsize;		/* 0x160 Master Interface Data Burst Size (non-ehci) */
-	u32 txfill;		/* 0x164 Host Transmit FIFO Tuning Control  (non-ehci) */
-	u32 res6[6];		/* 0x168 - 0x17F */
-	u32 cfgflag;		/* 0x180 Configure Flag Register */
-	u32 portsc1;		/* 0x184 Port Status/Control */
-	u32 res7[8];		/* 0x188 - 0x1A7 */
-
-	/* non-ehci registers */
-	u32 mode;		/* 0x1A8 USB mode register */
-	u32 eptsetstat;		/* 0x1AC Endpoint Setup status */
-	u32 eptprime;		/* 0x1B0 Endpoint initialization */
-	u32 eptflush;		/* 0x1B4 Endpoint de-initialize */
-	u32 eptstat;		/* 0x1B8 Endpoint status */
-	u32 eptcomplete;	/* 0x1BC Endpoint Complete */
-	u32 eptctrl0;		/* 0x1C0 Endpoint control 0 */
-	u32 eptctrl1;		/* 0x1C4 Endpoint control 1 */
-	u32 eptctrl2;		/* 0x1C8 Endpoint control 2 */
-	u32 eptctrl3;		/* 0x1CC Endpoint control 3 */
-} usbhost_t;
-
 /* SDRAM controller registers */
 typedef struct sdram_ctrl {
 	u32 mode;		/* 0x00 Mode/Extended Mode register */
diff --git a/include/asm-m68k/immap_5445x.h b/include/asm-m68k/immap_5445x.h
index ef8930e..57cf3ec 100644
--- a/include/asm-m68k/immap_5445x.h
+++ b/include/asm-m68k/immap_5445x.h
@@ -69,161 +69,15 @@
 #define MMAP_USBEHCI	0xFC0B0140
 #define MMAP_USBOTG	0xFC0B01A0
 
+#include <asm/coldfire/ata.h>
 #include <asm/coldfire/crossbar.h>
 #include <asm/coldfire/dspi.h>
 #include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
 #include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/intctrl.h>
 #include <asm/coldfire/ssi.h>
 
-/* ATA */
-typedef struct atac {
-	/* PIO */
-	u8 toff;		/* 0x00 */
-	u8 ton;			/* 0x01 */
-	u8 t1;			/* 0x02 */
-	u8 t2w;			/* 0x03 */
-	u8 t2r;			/* 0x04 */
-	u8 ta;			/* 0x05 */
-	u8 trd;			/* 0x06 */
-	u8 t4;			/* 0x07 */
-	u8 t9;			/* 0x08 */
-
-	/* DMA */
-	u8 tm;			/* 0x09 */
-	u8 tn;			/* 0x0A */
-	u8 td;			/* 0x0B */
-	u8 tk;			/* 0x0C */
-	u8 tack;		/* 0x0D */
-	u8 tenv;		/* 0x0E */
-	u8 trp;			/* 0x0F */
-	u8 tzah;		/* 0x10 */
-	u8 tmli;		/* 0x11 */
-	u8 tdvh;		/* 0x12 */
-	u8 tdzfs;		/* 0x13 */
-	u8 tdvs;		/* 0x14 */
-	u8 tcvh;		/* 0x15 */
-	u8 tss;			/* 0x16 */
-	u8 tcyc;		/* 0x17 */
-
-	/* FIFO */
-	u32 fifo32;		/* 0x18 */
-	u16 fifo16;		/* 0x1C */
-	u8 rsvd0[2];
-	u8 ffill;		/* 0x20 */
-	u8 rsvd1[3];
-
-	/* ATA */
-	u8 cr;			/* 0x24 */
-	u8 rsvd2[3];
-	u8 isr;			/* 0x28 */
-	u8 rsvd3[3];
-	u8 ier;			/* 0x2C */
-	u8 rsvd4[3];
-	u8 icr;			/* 0x30 */
-	u8 rsvd5[3];
-	u8 falarm;		/* 0x34 */
-	u8 rsvd6[106];
-} atac_t;
-
-/* Interrupt Controller (INTC) */
-typedef struct int0_ctrl {
-	u32 iprh0;		/* 0x00 Pending Register High */
-	u32 iprl0;		/* 0x04 Pending Register Low */
-	u32 imrh0;		/* 0x08 Mask Register High */
-	u32 imrl0;		/* 0x0C Mask Register Low */
-	u32 frch0;		/* 0x10 Force Register High */
-	u32 frcl0;		/* 0x14 Force Register Low */
-	u16 res1;		/* 0x18 - 0x19 */
-	u16 icfg0;		/* 0x1A Configuration Register */
-	u8 simr0;		/* 0x1C Set Interrupt Mask */
-	u8 cimr0;		/* 0x1D Clear Interrupt Mask */
-	u8 clmask0;		/* 0x1E Current Level Mask */
-	u8 slmask;		/* 0x1F Saved Level Mask */
-	u32 res2[8];		/* 0x20 - 0x3F */
-	u8 icr0[64];		/* 0x40 - 0x7F Control registers */
-	u32 res3[24];		/* 0x80 - 0xDF */
-	u8 swiack0;		/* 0xE0 Software Interrupt Acknowledge */
-	u8 res4[3];		/* 0xE1 - 0xE3 */
-	u8 Lniack0_1;		/* 0xE4 Level n interrupt acknowledge resister */
-	u8 res5[3];		/* 0xE5 - 0xE7 */
-	u8 Lniack0_2;		/* 0xE8 Level n interrupt acknowledge resister */
-	u8 res6[3];		/* 0xE9 - 0xEB */
-	u8 Lniack0_3;		/* 0xEC Level n interrupt acknowledge resister */
-	u8 res7[3];		/* 0xED - 0xEF */
-	u8 Lniack0_4;		/* 0xF0 Level n interrupt acknowledge resister */
-	u8 res8[3];		/* 0xF1 - 0xF3 */
-	u8 Lniack0_5;		/* 0xF4 Level n interrupt acknowledge resister */
-	u8 res9[3];		/* 0xF5 - 0xF7 */
-	u8 Lniack0_6;		/* 0xF8 Level n interrupt acknowledge resister */
-	u8 resa[3];		/* 0xF9 - 0xFB */
-	u8 Lniack0_7;		/* 0xFC Level n interrupt acknowledge resister */
-	u8 resb[3];		/* 0xFD - 0xFF */
-} int0_t;
-
-typedef struct int1_ctrl {
-	/* Interrupt Controller 1 */
-	u32 iprh1;		/* 0x00 Pending Register High */
-	u32 iprl1;		/* 0x04 Pending Register Low */
-	u32 imrh1;		/* 0x08 Mask Register High */
-	u32 imrl1;		/* 0x0C Mask Register Low */
-	u32 frch1;		/* 0x10 Force Register High */
-	u32 frcl1;		/* 0x14 Force Register Low */
-	u16 res1;		/* 0x18 */
-	u16 icfg1;		/* 0x1A Configuration Register */
-	u8 simr1;		/* 0x1C Set Interrupt Mask */
-	u8 cimr1;		/* 0x1D Clear Interrupt Mask */
-	u16 res2;		/* 0x1E - 0x1F */
-	u32 res3[8];		/* 0x20 - 0x3F */
-	u8 icr1[64];		/* 0x40 - 0x7F */
-	u32 res4[24];		/* 0x80 - 0xDF */
-	u8 swiack1;		/* 0xE0 Software Interrupt Acknowledge */
-	u8 res5[3];		/* 0xE1 - 0xE3 */
-	u8 Lniack1_1;		/* 0xE4 Level n interrupt acknowledge resister */
-	u8 res6[3];		/* 0xE5 - 0xE7 */
-	u8 Lniack1_2;		/* 0xE8 Level n interrupt acknowledge resister */
-	u8 res7[3];		/* 0xE9 - 0xEB */
-	u8 Lniack1_3;		/* 0xEC Level n interrupt acknowledge resister */
-	u8 res8[3];		/* 0xED - 0xEF */
-	u8 Lniack1_4;		/* 0xF0 Level n interrupt acknowledge resister */
-	u8 res9[3];		/* 0xF1 - 0xF3 */
-	u8 Lniack1_5;		/* 0xF4 Level n interrupt acknowledge resister */
-	u8 resa[3];		/* 0xF5 - 0xF7 */
-	u8 Lniack1_6;		/* 0xF8 Level n interrupt acknowledge resister */
-	u8 resb[3];		/* 0xF9 - 0xFB */
-	u8 Lniack1_7;		/* 0xFC Level n interrupt acknowledge resister */
-	u8 resc[3];		/* 0xFD - 0xFF */
-} int1_t;
-
-/* Global Interrupt Acknowledge (IACK) */
-typedef struct iack {
-	u8 resv0[0xE0];
-	u8 gswiack;
-	u8 resv1[0x3];
-	u8 gl1iack;
-	u8 resv2[0x3];
-	u8 gl2iack;
-	u8 resv3[0x3];
-	u8 gl3iack;
-	u8 resv4[0x3];
-	u8 gl4iack;
-	u8 resv5[0x3];
-	u8 gl5iack;
-	u8 resv6[0x3];
-	u8 gl6iack;
-	u8 resv7[0x3];
-	u8 gl7iack;
-} iack_t;
-
-/* Edge Port Module (EPORT) */
-typedef struct eport {
-	u16 eppar;
-	u8 epddr;
-	u8 epier;
-	u8 epdr;
-	u8 eppdr;
-	u8 epfr;
-} eport_t;
-
 /* Watchdog Timer Modules (WTM) */
 typedef struct wtm {
 	u16 wcr;
@@ -387,14 +241,6 @@ typedef struct gpio {
 	u8 dscr_ata;		/* ATA Drive Strength Control Register */
 } gpio_t;
 
-/* Random Number Generator (RNG) */
-typedef struct rng {
-	u32 rngcr;
-	u32 rngsr;
-	u32 rnger;
-	u32 rngout;
-} rng_t;
-
 /* SDRAM Controller (SDRAMC) */
 typedef struct sdramc {
 	u32 sdmr;		/* SDRAM Mode/Extended Mode Register */
diff --git a/include/asm-m68k/immap_547x_8x.h b/include/asm-m68k/immap_547x_8x.h
index 54ef40f..50f8b05d98 100644
--- a/include/asm-m68k/immap_547x_8x.h
+++ b/include/asm-m68k/immap_547x_8x.h
@@ -26,38 +26,42 @@
 #ifndef __IMMAP_547x_8x__
 #define __IMMAP_547x_8x__
 
-#define MMAP_SIU	(CFG_MBAR + 0x00000000)
-#define MMAP_SDRAM	(CFG_MBAR + 0x00000100)
-#define MMAP_XARB	(CFG_MBAR + 0x00000240)
-#define MMAP_FBCS	(CFG_MBAR + 0x00000500)
-#define MMAP_INTC0	(CFG_MBAR + 0x00000700)
-#define MMAP_GPTMR	(CFG_MBAR + 0x00000800)
-#define MMAP_SLT0	(CFG_MBAR + 0x00000900)
-#define MMAP_SLT1	(CFG_MBAR + 0x00000910)
-#define MMAP_GPIO	(CFG_MBAR + 0x00000A00)
-#define MMAP_PCI	(CFG_MBAR + 0x00000B00)
-#define MMAP_PCIARB	(CFG_MBAR + 0x00000C00)
-#define MMAP_EXTDMA	(CFG_MBAR + 0x00000D00)
-#define MMAP_EPORT	(CFG_MBAR + 0x00000F00)
-#define MMAP_CTM	(CFG_MBAR + 0x00007F00)
-#define MMAP_MCDMA	(CFG_MBAR + 0x00008000)
-#define MMAP_SCPCI	(CFG_MBAR + 0x00008400)
-#define MMAP_UART0	(CFG_MBAR + 0x00008600)
-#define MMAP_UART1	(CFG_MBAR + 0x00008700)
-#define MMAP_UART2	(CFG_MBAR + 0x00008800)
-#define MMAP_UART3	(CFG_MBAR + 0x00008900)
-#define MMAP_DSPI	(CFG_MBAR + 0x00008A00)
-#define MMAP_I2C	(CFG_MBAR + 0x00008F00)
-#define MMAP_FEC0	(CFG_MBAR + 0x00009000)
-#define MMAP_FEC1	(CFG_MBAR + 0x00009800)
-#define MMAP_CAN0	(CFG_MBAR + 0x0000A000)
-#define MMAP_CAN1	(CFG_MBAR + 0x0000A800)
-#define MMAP_USBD	(CFG_MBAR + 0x0000B000)
-#define MMAP_SRAM	(CFG_MBAR + 0x00010000)
-#define MMAP_SRAMCFG	(CFG_MBAR + 0x0001FF00)
-#define MMAP_SEC	(CFG_MBAR + 0x00020000)
+#define MMAP_SIU	(CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000100)
+#define MMAP_XARB	(CONFIG_SYS_MBAR + 0x00000240)
+#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000500)
+#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000700)
+#define MMAP_GPTMR	(CONFIG_SYS_MBAR + 0x00000800)
+#define MMAP_SLT0	(CONFIG_SYS_MBAR + 0x00000900)
+#define MMAP_SLT1	(CONFIG_SYS_MBAR + 0x00000910)
+#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00000A00)
+#define MMAP_PCI	(CONFIG_SYS_MBAR + 0x00000B00)
+#define MMAP_PCIARB	(CONFIG_SYS_MBAR + 0x00000C00)
+#define MMAP_EXTDMA	(CONFIG_SYS_MBAR + 0x00000D00)
+#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00000F00)
+#define MMAP_CTM	(CONFIG_SYS_MBAR + 0x00007F00)
+#define MMAP_MCDMA	(CONFIG_SYS_MBAR + 0x00008000)
+#define MMAP_SCPCI	(CONFIG_SYS_MBAR + 0x00008400)
+#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00008600)
+#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00008700)
+#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00008800)
+#define MMAP_UART3	(CONFIG_SYS_MBAR + 0x00008900)
+#define MMAP_DSPI	(CONFIG_SYS_MBAR + 0x00008A00)
+#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00008F00)
+#define MMAP_FEC0	(CONFIG_SYS_MBAR + 0x00009000)
+#define MMAP_FEC1	(CONFIG_SYS_MBAR + 0x00009800)
+#define MMAP_CAN0	(CONFIG_SYS_MBAR + 0x0000A000)
+#define MMAP_CAN1	(CONFIG_SYS_MBAR + 0x0000A800)
+#define MMAP_USBD	(CONFIG_SYS_MBAR + 0x0000B000)
+#define MMAP_SRAM	(CONFIG_SYS_MBAR + 0x00010000)
+#define MMAP_SRAMCFG	(CONFIG_SYS_MBAR + 0x0001FF00)
+#define MMAP_SEC	(CONFIG_SYS_MBAR + 0x00020000)
 
+#include <asm/coldfire/dspi.h>
+#include <asm/coldfire/eport.h>
 #include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/intctrl.h>
 
 typedef struct siu {
 	u32 mbar;		/* 0x00 */
@@ -98,37 +102,6 @@ typedef struct xlb_arb {
 	u32 pri;		/* 0x268 */
 } xlbarb_t;
 
-typedef struct int0_ctrl {
-	u32 iprh0;		/* 0x00 */
-	u32 iprl0;		/* 0x04 */
-	u32 imrh0;		/* 0x08 */
-	u32 imrl0;		/* 0x0C */
-	u32 frch0;		/* 0x10 */
-	u32 frcl0;		/* 0x14 */
-	u8 irlr;		/* 0x18 */
-	u8 iacklpr;		/* 0x19 */
-	u16 res1;		/* 0x1A - 0x1B */
-	u32 res2[9];		/* 0x1C - 0x3F */
-	u8 icr0[64];		/* 0x40 - 0x7F */
-	u32 res3[24];		/* 0x80 - 0xDF */
-	u8 swiack0;		/* 0xE0 */
-	u8 res4[3];		/* 0xE1 - 0xE3 */
-	u8 Lniack0_1;		/* 0xE4 */
-	u8 res5[3];		/* 0xE5 - 0xE7 */
-	u8 Lniack0_2;		/* 0xE8 */
-	u8 res6[3];		/* 0xE9 - 0xEB */
-	u8 Lniack0_3;		/* 0xEC */
-	u8 res7[3];		/* 0xED - 0xEF */
-	u8 Lniack0_4;		/* 0xF0 */
-	u8 res8[3];		/* 0xF1 - 0xF3 */
-	u8 Lniack0_5;		/* 0xF4 */
-	u8 res9[3];		/* 0xF5 - 0xF7 */
-	u8 Lniack0_6;		/* 0xF8 */
-	u8 resa[3];		/* 0xF9 - 0xFB */
-	u8 Lniack0_7;		/* 0xFC */
-	u8 resb[3];		/* 0xFD - 0xFF */
-} int0_t;
-
 typedef struct gptmr {
 	u8 ocpw;
 	u8 octict;
@@ -147,6 +120,11 @@ typedef struct gptmr {
 	u8 intr;		/* Interrupts */
 } gptmr_t;
 
+typedef struct canex_ctrl {
+	can_msg_t msg[16];	/* 0x00 Message Buffer 0-15 */
+} canex_t;
+
+
 typedef struct slt {
 	u32 tcnt;		/* 0x00 */
 	u32 cr;			/* 0x04 */
diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h
index 1fccc12..50ea087 100644
--- a/include/asm-m68k/io.h
+++ b/include/asm-m68k/io.h
@@ -251,4 +251,9 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
 
 }
 
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
 #endif				/* __ASM_M68K_IO_H__ */
diff --git a/include/asm-m68k/m5227x.h b/include/asm-m68k/m5227x.h
index afd31ba..824d333 100644
--- a/include/asm-m68k/m5227x.h
+++ b/include/asm-m68k/m5227x.h
@@ -26,9 +26,7 @@
 #ifndef __MCF5227X__
 #define __MCF5227X__
 
-/*********************************************************************
-* Interrupt Controller (INTC)
-*********************************************************************/
+/* Interrupt Controller (INTC) */
 #define INT0_LO_RSVD0			(0)
 #define INT0_LO_EPORT1			(1)
 #define INT0_LO_EPORT4			(4)
@@ -98,235 +96,6 @@
 #define INT1_HI_TOUCH_ADC		(61)
 #define INT1_HI_PLL_LOCKS		(62)
 
-/* Bit definitions and macros for IPRH */
-#define INTC_IPRH_INT32			(0x00000001)
-#define INTC_IPRH_INT33			(0x00000002)
-#define INTC_IPRH_INT34			(0x00000004)
-#define INTC_IPRH_INT35			(0x00000008)
-#define INTC_IPRH_INT36			(0x00000010)
-#define INTC_IPRH_INT37			(0x00000020)
-#define INTC_IPRH_INT38			(0x00000040)
-#define INTC_IPRH_INT39			(0x00000080)
-#define INTC_IPRH_INT40			(0x00000100)
-#define INTC_IPRH_INT41			(0x00000200)
-#define INTC_IPRH_INT42			(0x00000400)
-#define INTC_IPRH_INT43			(0x00000800)
-#define INTC_IPRH_INT44			(0x00001000)
-#define INTC_IPRH_INT45			(0x00002000)
-#define INTC_IPRH_INT46			(0x00004000)
-#define INTC_IPRH_INT47			(0x00008000)
-#define INTC_IPRH_INT48			(0x00010000)
-#define INTC_IPRH_INT49			(0x00020000)
-#define INTC_IPRH_INT50			(0x00040000)
-#define INTC_IPRH_INT51			(0x00080000)
-#define INTC_IPRH_INT52			(0x00100000)
-#define INTC_IPRH_INT53			(0x00200000)
-#define INTC_IPRH_INT54			(0x00400000)
-#define INTC_IPRH_INT55			(0x00800000)
-#define INTC_IPRH_INT56			(0x01000000)
-#define INTC_IPRH_INT57			(0x02000000)
-#define INTC_IPRH_INT58			(0x04000000)
-#define INTC_IPRH_INT59			(0x08000000)
-#define INTC_IPRH_INT60			(0x10000000)
-#define INTC_IPRH_INT61			(0x20000000)
-#define INTC_IPRH_INT62			(0x40000000)
-#define INTC_IPRH_INT63			(0x80000000)
-
-/* Bit definitions and macros for IPRL */
-#define INTC_IPRL_INT0			(0x00000001)
-#define INTC_IPRL_INT1			(0x00000002)
-#define INTC_IPRL_INT2			(0x00000004)
-#define INTC_IPRL_INT3			(0x00000008)
-#define INTC_IPRL_INT4			(0x00000010)
-#define INTC_IPRL_INT5			(0x00000020)
-#define INTC_IPRL_INT6			(0x00000040)
-#define INTC_IPRL_INT7			(0x00000080)
-#define INTC_IPRL_INT8			(0x00000100)
-#define INTC_IPRL_INT9			(0x00000200)
-#define INTC_IPRL_INT10			(0x00000400)
-#define INTC_IPRL_INT11			(0x00000800)
-#define INTC_IPRL_INT12			(0x00001000)
-#define INTC_IPRL_INT13			(0x00002000)
-#define INTC_IPRL_INT14			(0x00004000)
-#define INTC_IPRL_INT15			(0x00008000)
-#define INTC_IPRL_INT16			(0x00010000)
-#define INTC_IPRL_INT17			(0x00020000)
-#define INTC_IPRL_INT18			(0x00040000)
-#define INTC_IPRL_INT19			(0x00080000)
-#define INTC_IPRL_INT20			(0x00100000)
-#define INTC_IPRL_INT21			(0x00200000)
-#define INTC_IPRL_INT22			(0x00400000)
-#define INTC_IPRL_INT23			(0x00800000)
-#define INTC_IPRL_INT24			(0x01000000)
-#define INTC_IPRL_INT25			(0x02000000)
-#define INTC_IPRL_INT26			(0x04000000)
-#define INTC_IPRL_INT27			(0x08000000)
-#define INTC_IPRL_INT28			(0x10000000)
-#define INTC_IPRL_INT29			(0x20000000)
-#define INTC_IPRL_INT30			(0x40000000)
-#define INTC_IPRL_INT31			(0x80000000)
-
-/* Bit definitions and macros for IMRH */
-#define INTC_IMRH_INT_MASK32		(0x00000001)
-#define INTC_IMRH_INT_MASK33		(0x00000002)
-#define INTC_IMRH_INT_MASK34		(0x00000004)
-#define INTC_IMRH_INT_MASK35		(0x00000008)
-#define INTC_IMRH_INT_MASK36		(0x00000010)
-#define INTC_IMRH_INT_MASK37		(0x00000020)
-#define INTC_IMRH_INT_MASK38		(0x00000040)
-#define INTC_IMRH_INT_MASK39		(0x00000080)
-#define INTC_IMRH_INT_MASK40		(0x00000100)
-#define INTC_IMRH_INT_MASK41		(0x00000200)
-#define INTC_IMRH_INT_MASK42		(0x00000400)
-#define INTC_IMRH_INT_MASK43		(0x00000800)
-#define INTC_IMRH_INT_MASK44		(0x00001000)
-#define INTC_IMRH_INT_MASK45		(0x00002000)
-#define INTC_IMRH_INT_MASK46		(0x00004000)
-#define INTC_IMRH_INT_MASK47		(0x00008000)
-#define INTC_IMRH_INT_MASK48		(0x00010000)
-#define INTC_IMRH_INT_MASK49		(0x00020000)
-#define INTC_IMRH_INT_MASK50		(0x00040000)
-#define INTC_IMRH_INT_MASK51		(0x00080000)
-#define INTC_IMRH_INT_MASK52		(0x00100000)
-#define INTC_IMRH_INT_MASK53		(0x00200000)
-#define INTC_IMRH_INT_MASK54		(0x00400000)
-#define INTC_IMRH_INT_MASK55		(0x00800000)
-#define INTC_IMRH_INT_MASK56		(0x01000000)
-#define INTC_IMRH_INT_MASK57		(0x02000000)
-#define INTC_IMRH_INT_MASK58		(0x04000000)
-#define INTC_IMRH_INT_MASK59		(0x08000000)
-#define INTC_IMRH_INT_MASK60		(0x10000000)
-#define INTC_IMRH_INT_MASK61		(0x20000000)
-#define INTC_IMRH_INT_MASK62		(0x40000000)
-#define INTC_IMRH_INT_MASK63		(0x80000000)
-
-/* Bit definitions and macros for IMRL */
-#define INTC_IMRL_INT_MASK0		(0x00000001)
-#define INTC_IMRL_INT_MASK1		(0x00000002)
-#define INTC_IMRL_INT_MASK2		(0x00000004)
-#define INTC_IMRL_INT_MASK3		(0x00000008)
-#define INTC_IMRL_INT_MASK4		(0x00000010)
-#define INTC_IMRL_INT_MASK5		(0x00000020)
-#define INTC_IMRL_INT_MASK6		(0x00000040)
-#define INTC_IMRL_INT_MASK7		(0x00000080)
-#define INTC_IMRL_INT_MASK8		(0x00000100)
-#define INTC_IMRL_INT_MASK9		(0x00000200)
-#define INTC_IMRL_INT_MASK10		(0x00000400)
-#define INTC_IMRL_INT_MASK11		(0x00000800)
-#define INTC_IMRL_INT_MASK12		(0x00001000)
-#define INTC_IMRL_INT_MASK13		(0x00002000)
-#define INTC_IMRL_INT_MASK14		(0x00004000)
-#define INTC_IMRL_INT_MASK15		(0x00008000)
-#define INTC_IMRL_INT_MASK16		(0x00010000)
-#define INTC_IMRL_INT_MASK17		(0x00020000)
-#define INTC_IMRL_INT_MASK18		(0x00040000)
-#define INTC_IMRL_INT_MASK19		(0x00080000)
-#define INTC_IMRL_INT_MASK20		(0x00100000)
-#define INTC_IMRL_INT_MASK21		(0x00200000)
-#define INTC_IMRL_INT_MASK22		(0x00400000)
-#define INTC_IMRL_INT_MASK23		(0x00800000)
-#define INTC_IMRL_INT_MASK24		(0x01000000)
-#define INTC_IMRL_INT_MASK25		(0x02000000)
-#define INTC_IMRL_INT_MASK26		(0x04000000)
-#define INTC_IMRL_INT_MASK27		(0x08000000)
-#define INTC_IMRL_INT_MASK28		(0x10000000)
-#define INTC_IMRL_INT_MASK29		(0x20000000)
-#define INTC_IMRL_INT_MASK30		(0x40000000)
-#define INTC_IMRL_INT_MASK31		(0x80000000)
-
-/* Bit definitions and macros for INTFRCH */
-#define INTC_INTFRCH_INTFRC32		(0x00000001)
-#define INTC_INTFRCH_INTFRC33		(0x00000002)
-#define INTC_INTFRCH_INTFRC34		(0x00000004)
-#define INTC_INTFRCH_INTFRC35		(0x00000008)
-#define INTC_INTFRCH_INTFRC36		(0x00000010)
-#define INTC_INTFRCH_INTFRC37		(0x00000020)
-#define INTC_INTFRCH_INTFRC38		(0x00000040)
-#define INTC_INTFRCH_INTFRC39		(0x00000080)
-#define INTC_INTFRCH_INTFRC40		(0x00000100)
-#define INTC_INTFRCH_INTFRC41		(0x00000200)
-#define INTC_INTFRCH_INTFRC42		(0x00000400)
-#define INTC_INTFRCH_INTFRC43		(0x00000800)
-#define INTC_INTFRCH_INTFRC44		(0x00001000)
-#define INTC_INTFRCH_INTFRC45		(0x00002000)
-#define INTC_INTFRCH_INTFRC46		(0x00004000)
-#define INTC_INTFRCH_INTFRC47		(0x00008000)
-#define INTC_INTFRCH_INTFRC48		(0x00010000)
-#define INTC_INTFRCH_INTFRC49		(0x00020000)
-#define INTC_INTFRCH_INTFRC50		(0x00040000)
-#define INTC_INTFRCH_INTFRC51		(0x00080000)
-#define INTC_INTFRCH_INTFRC52		(0x00100000)
-#define INTC_INTFRCH_INTFRC53		(0x00200000)
-#define INTC_INTFRCH_INTFRC54		(0x00400000)
-#define INTC_INTFRCH_INTFRC55		(0x00800000)
-#define INTC_INTFRCH_INTFRC56		(0x01000000)
-#define INTC_INTFRCH_INTFRC57		(0x02000000)
-#define INTC_INTFRCH_INTFRC58		(0x04000000)
-#define INTC_INTFRCH_INTFRC59		(0x08000000)
-#define INTC_INTFRCH_INTFRC60		(0x10000000)
-#define INTC_INTFRCH_INTFRC61		(0x20000000)
-#define INTC_INTFRCH_INTFRC62		(0x40000000)
-#define INTC_INTFRCH_INTFRC63		(0x80000000)
-
-/* Bit definitions and macros for INTFRCL */
-#define INTC_INTFRCL_INTFRC0		(0x00000001)
-#define INTC_INTFRCL_INTFRC1		(0x00000002)
-#define INTC_INTFRCL_INTFRC2		(0x00000004)
-#define INTC_INTFRCL_INTFRC3		(0x00000008)
-#define INTC_INTFRCL_INTFRC4		(0x00000010)
-#define INTC_INTFRCL_INTFRC5		(0x00000020)
-#define INTC_INTFRCL_INTFRC6		(0x00000040)
-#define INTC_INTFRCL_INTFRC7		(0x00000080)
-#define INTC_INTFRCL_INTFRC8		(0x00000100)
-#define INTC_INTFRCL_INTFRC9		(0x00000200)
-#define INTC_INTFRCL_INTFRC10		(0x00000400)
-#define INTC_INTFRCL_INTFRC11		(0x00000800)
-#define INTC_INTFRCL_INTFRC12		(0x00001000)
-#define INTC_INTFRCL_INTFRC13		(0x00002000)
-#define INTC_INTFRCL_INTFRC14		(0x00004000)
-#define INTC_INTFRCL_INTFRC15		(0x00008000)
-#define INTC_INTFRCL_INTFRC16		(0x00010000)
-#define INTC_INTFRCL_INTFRC17		(0x00020000)
-#define INTC_INTFRCL_INTFRC18		(0x00040000)
-#define INTC_INTFRCL_INTFRC19		(0x00080000)
-#define INTC_INTFRCL_INTFRC20		(0x00100000)
-#define INTC_INTFRCL_INTFRC21		(0x00200000)
-#define INTC_INTFRCL_INTFRC22		(0x00400000)
-#define INTC_INTFRCL_INTFRC23		(0x00800000)
-#define INTC_INTFRCL_INTFRC24		(0x01000000)
-#define INTC_INTFRCL_INTFRC25		(0x02000000)
-#define INTC_INTFRCL_INTFRC26		(0x04000000)
-#define INTC_INTFRCL_INTFRC27		(0x08000000)
-#define INTC_INTFRCL_INTFRC28		(0x10000000)
-#define INTC_INTFRCL_INTFRC29		(0x20000000)
-#define INTC_INTFRCL_INTFRC30		(0x40000000)
-#define INTC_INTFRCL_INTFRC31		(0x80000000)
-
-/* Bit definitions and macros for ICONFIG */
-#define INTC_ICONFIG_EMASK		(0x0020)
-#define INTC_ICONFIG_ELVLPRI1		(0x0200)
-#define INTC_ICONFIG_ELVLPRI2		(0x0400)
-#define INTC_ICONFIG_ELVLPRI3		(0x0800)
-#define INTC_ICONFIG_ELVLPRI4		(0x1000)
-#define INTC_ICONFIG_ELVLPRI5		(0x2000)
-#define INTC_ICONFIG_ELVLPRI6		(0x4000)
-#define INTC_ICONFIG_ELVLPRI7		(0x8000)
-
-/* Bit definitions and macros for SIMR */
-#define INTC_SIMR_SIMR(x)		(((x)&0x7F))
-
-/* Bit definitions and macros for CIMR */
-#define INTC_CIMR_CIMR(x)		(((x)&0x7F))
-
-/* Bit definitions and macros for CLMASK */
-#define INTC_CLMASK_CLMASK(x)		(((x)&0x0F))
-
-/* Bit definitions and macros for SLMASK */
-#define INTC_SLMASK_SLMASK(x)		(((x)&0x0F))
-
-/* Bit definitions and macros for ICR group */
-#define INTC_ICR_IL(x)			(((x)&0x07))
-
 /*********************************************************************
 * Reset Controller Module (RCM)
 *********************************************************************/
@@ -513,8 +282,8 @@
 
 /* Bit definitions and macros for PAR_DSPI */
 #define GPIO_PAR_DSPI_PCS0_MASK		(0x3F)
-#define GPIO_PAR_DSPI_PCS0_PCS0		(0x80)
-#define GPIO_PAR_DSPI_PCS0_U2RTS	(0x40)
+#define GPIO_PAR_DSPI_PCS0_PCS0		(0xC0)
+#define GPIO_PAR_DSPI_PCS0_U2RTS	(0x80)
 #define GPIO_PAR_DSPI_PCS0_GPIO		(0x00)
 #define GPIO_PAR_DSPI_SIN_MASK		(0xCF)
 #define GPIO_PAR_DSPI_SIN_SIN		(0x30)
diff --git a/include/asm-m68k/m5235.h b/include/asm-m68k/m5235.h
index b98b452..22987ac 100644
--- a/include/asm-m68k/m5235.h
+++ b/include/asm-m68k/m5235.h
@@ -163,94 +163,6 @@
 #define SDRAMC_DMRn_V			(0x00000001)
 
 /*********************************************************************
-* FlexBus Chip Selects (FBCS)
-*********************************************************************/
-/* Bit definitions and macros for FBCS_CSMR */
-#define FBCS_CSMR_BAM(x)		(((x)&0xFFFF)<<16)
-#define FBCS_CSMR_BAM_4G		(0xFFFF0000)
-#define FBCS_CSMR_BAM_2G		(0x7FFF0000)
-#define FBCS_CSMR_BAM_1G		(0x3FFF0000)
-#define FBCS_CSMR_BAM_1024M		(0x3FFF0000)
-#define FBCS_CSMR_BAM_512M		(0x1FFF0000)
-#define FBCS_CSMR_BAM_256M		(0x0FFF0000)
-#define FBCS_CSMR_BAM_128M		(0x07FF0000)
-#define FBCS_CSMR_BAM_64M		(0x03FF0000)
-#define FBCS_CSMR_BAM_32M		(0x01FF0000)
-#define FBCS_CSMR_BAM_16M		(0x00FF0000)
-#define FBCS_CSMR_BAM_8M		(0x007F0000)
-#define FBCS_CSMR_BAM_4M		(0x003F0000)
-#define FBCS_CSMR_BAM_2M		(0x001F0000)
-#define FBCS_CSMR_BAM_1M		(0x000F0000)
-#define FBCS_CSMR_BAM_1024K		(0x000F0000)
-#define FBCS_CSMR_BAM_512K		(0x00070000)
-#define FBCS_CSMR_BAM_256K		(0x00030000)
-#define FBCS_CSMR_BAM_128K		(0x00010000)
-#define FBCS_CSMR_BAM_64K		(0x00000000)
-#define FBCS_CSMR_WP			(0x00000100)
-#define FBCS_CSMR_V			(0x00000001)
-
-/* Bit definitions and macros for FBCS_CSCR */
-#define FBCS_CSCR_SRWS(x)		(((x)&0x03)<<14)
-#define FBCS_CSCR_IWS(x)		(((x)&0x0F)<<10)
-#define FBCS_CSCR_AA			(0x0100)
-#define FBCS_CSCR_PS_MASK		(0x00C0)
-#define FBCS_CSCR_PS_32			(0x0000)
-#define FBCS_CSCR_PS_16			(0x0080)
-#define FBCS_CSCR_PS_8			(0x0040)
-#define FBCS_CSCR_BEM			(0x0020)
-#define FBCS_CSCR_BSTR			(0x0010)
-#define FBCS_CSCR_BSTW			(0x0008)
-#define FBCS_CSCR_SWWS(x)		((x)&0x07)
-
-/*********************************************************************
-* Queued Serial Peripheral Interface (QSPI)
-*********************************************************************/
-/* Bit definitions and macros for QSPI_QMR */
-#define QSPI_QMR_MSTR			(0x8000)
-#define QSPI_QMR_DOHIE			(0x4000)
-#define QSPI_QMR_BITS(x)		(((x)&0x000F)<<10)
-#define QSPI_QMR_CPOL			(0x0200)
-#define QSPI_QMR_CPHA			(0x0100)
-#define QSPI_QMR_BAUD(x)		((x)&0x00FF)
-
-/* Bit definitions and macros for QSPI_QDLYR */
-#define QSPI_QDLYR_SPE			(0x8000)
-#define QSPI_QDLYR_QCD(x)		(((x)&0x007F)<<8)
-#define QSPI_QDLYR_DTL(x)		((x)&0x00FF)
-
-/* Bit definitions and macros for QSPI_QWR */
-#define QSPI_QWR_HALT			(0x8000)
-#define QSPI_QWR_WREN			(0x4000)
-#define QSPI_QWR_WRTO			(0x2000)
-#define QSPI_QWR_CSIV			(0x1000)
-#define QSPI_QWR_ENDQP(x)		(((x)&0x000F)<<8)
-#define QSPI_QWR_NEWQP(x)		((x)&0x000F)
-
-/* Bit definitions and macros for QSPI_QIR */
-#define QSPI_QIR_WCEFB			(0x8000)
-#define QSPI_QIR_ABRTB			(0x4000)
-#define QSPI_QIR_ABRTL			(0x1000)
-#define QSPI_QIR_WCEFE			(0x0800)
-#define QSPI_QIR_ABRTE			(0x0400)
-#define QSPI_QIR_SPIFE			(0x0100)
-#define QSPI_QIR_WCEF			(0x0008)
-#define QSPI_QIR_ABRT			(0x0004)
-#define QSPI_QIR_SPIF			(0x0001)
-
-/* Bit definitions and macros for QSPI_QAR */
-#define QSPI_QAR_ADDR(x)		((x)&0x003F)
-
-/* Bit definitions and macros for QSPI_QDR */
-#define QSPI_QDR_CONT			(0x8000)
-#define QSPI_QDR_BITSE			(0x4000)
-#define QSPI_QDR_DT			(0x2000)
-#define QSPI_QDR_DSCK			(0x1000)
-#define QSPI_QDR_QSPI_CS3		(0x0800)
-#define QSPI_QDR_QSPI_CS2		(0x0400)
-#define QSPI_QDR_QSPI_CS1		(0x0200)
-#define QSPI_QDR_QSPI_CS0		(0x0100)
-
-/*********************************************************************
 * Interrupt Controller (INTC)
 *********************************************************************/
 #define INT0_LO_RSVD0			(0)
@@ -370,85 +282,6 @@
 #define INT1_HI_ETPU_TC31F		(58)
 #define INT1_HI_ETPU_TGIF		(59)
 
-/* Bit definitions and macros for INTC_IPRH */
-#define INTC_IPRH_INT63			(0x80000000)
-#define INTC_IPRH_INT62			(0x40000000)
-#define INTC_IPRH_INT61			(0x20000000)
-#define INTC_IPRH_INT60			(0x10000000)
-#define INTC_IPRH_INT59			(0x08000000)
-#define INTC_IPRH_INT58			(0x04000000)
-#define INTC_IPRH_INT57			(0x02000000)
-#define INTC_IPRH_INT56			(0x01000000)
-#define INTC_IPRH_INT55			(0x00800000)
-#define INTC_IPRH_INT54			(0x00400000)
-#define INTC_IPRH_INT53			(0x00200000)
-#define INTC_IPRH_INT52			(0x00100000)
-#define INTC_IPRH_INT51			(0x00080000)
-#define INTC_IPRH_INT50			(0x00040000)
-#define INTC_IPRH_INT49			(0x00020000)
-#define INTC_IPRH_INT48			(0x00010000)
-#define INTC_IPRH_INT47			(0x00008000)
-#define INTC_IPRH_INT46			(0x00004000)
-#define INTC_IPRH_INT45			(0x00002000)
-#define INTC_IPRH_INT44			(0x00001000)
-#define INTC_IPRH_INT43			(0x00000800)
-#define INTC_IPRH_INT42			(0x00000400)
-#define INTC_IPRH_INT41			(0x00000200)
-#define INTC_IPRH_INT40			(0x00000100)
-#define INTC_IPRH_INT39			(0x00000080)
-#define INTC_IPRH_INT38			(0x00000040)
-#define INTC_IPRH_INT37			(0x00000020)
-#define INTC_IPRH_INT36			(0x00000010)
-#define INTC_IPRH_INT35			(0x00000008)
-#define INTC_IPRH_INT34			(0x00000004)
-#define INTC_IPRH_INT33			(0x00000002)
-#define INTC_IPRH_INT32			(0x00000001)
-
-/* Bit definitions and macros for INTC_IPRL */
-#define INTC_IPRL_INT31			(0x80000000)
-#define INTC_IPRL_INT30			(0x40000000)
-#define INTC_IPRL_INT29			(0x20000000)
-#define INTC_IPRL_INT28			(0x10000000)
-#define INTC_IPRL_INT27			(0x08000000)
-#define INTC_IPRL_INT26			(0x04000000)
-#define INTC_IPRL_INT25			(0x02000000)
-#define INTC_IPRL_INT24			(0x01000000)
-#define INTC_IPRL_INT23			(0x00800000)
-#define INTC_IPRL_INT22			(0x00400000)
-#define INTC_IPRL_INT21			(0x00200000)
-#define INTC_IPRL_INT20			(0x00100000)
-#define INTC_IPRL_INT19			(0x00080000)
-#define INTC_IPRL_INT18			(0x00040000)
-#define INTC_IPRL_INT17			(0x00020000)
-#define INTC_IPRL_INT16			(0x00010000)
-#define INTC_IPRL_INT15			(0x00008000)
-#define INTC_IPRL_INT14			(0x00004000)
-#define INTC_IPRL_INT13			(0x00002000)
-#define INTC_IPRL_INT12			(0x00001000)
-#define INTC_IPRL_INT11			(0x00000800)
-#define INTC_IPRL_INT10			(0x00000400)
-#define INTC_IPRL_INT9			(0x00000200)
-#define INTC_IPRL_INT8			(0x00000100)
-#define INTC_IPRL_INT7			(0x00000080)
-#define INTC_IPRL_INT6			(0x00000040)
-#define INTC_IPRL_INT5			(0x00000020)
-#define INTC_IPRL_INT4			(0x00000010)
-#define INTC_IPRL_INT3			(0x00000008)
-#define INTC_IPRL_INT2			(0x00000004)
-#define INTC_IPRL_INT1			(0x00000002)
-#define INTC_IPRL_INT0			(0x00000001)
-
-/* Bit definitions and macros for INTC_IRLR */
-#define INTC_IRLRn(x)			(((x)&0x7F)<<1)
-
-/* Bit definitions and macros for INTC_IACKLPRn */
-#define INTC_IACKLPRn_LEVEL(x)		(((x)&0x07)<<4)
-#define INTC_IACKLPRn_PRI(x)		((x)&0x0F)
-
-/* Bit definitions and macros for INTC_ICRnx */
-#define INTC_ICRnx_IL(x)		(((x)&0x07)<<3)
-#define INTC_ICRnx_IP(x)		((x)&0x07)
-
 /*********************************************************************
 * General Purpose I/O (GPIO)
 *********************************************************************/
@@ -758,49 +591,6 @@
 #define PLL_SYNSR_CALPASS		(0x00000001)
 
 /*********************************************************************
- * Edge Port
-*********************************************************************/
-#define EPORT_EPPAR_EPPA7(x)		(((x)&0x03)<<14)
-#define EPORT_EPPAR_EPPA6(x)		(((x)&0x03)<<12)
-#define EPORT_EPPAR_EPPA5(x)		(((x)&0x03)<<10)
-#define EPORT_EPPAR_EPPA4(x)		(((x)&0x03)<<8)
-#define EPORT_EPPAR_EPPA3(x)		(((x)&0x03)<<6)
-#define EPORT_EPPAR_EPPA2(x)		(((x)&0x03)<<4)
-#define EPORT_EPPAR_EPPA1(x)		(((x)&0x03)<<2)
-
-#define EPORT_EPDDR_EPDD7(x)		EPORT_EPPAR_EPPA7(x)
-#define EPORT_EPDDR_EPDD6(x)		EPORT_EPPAR_EPPA6(x)
-#define EPORT_EPDDR_EPDD5(x)		EPORT_EPPAR_EPPA5(x)
-#define EPORT_EPDDR_EPDD4(x)		EPORT_EPPAR_EPPA4(x)
-#define EPORT_EPDDR_EPDD3(x)		EPORT_EPPAR_EPPA3(x)
-#define EPORT_EPDDR_EPDD2(x)		EPORT_EPPAR_EPPA2(x)
-#define EPORT_EPDDR_EPDD1(x)		EPORT_EPPAR_EPPA1(x)
-
-#define EPORT_EPIER_EPIE7		(0x80)
-#define EPORT_EPIER_EPIE6		(0x40)
-#define EPORT_EPIER_EPIE5		(0x20)
-#define EPORT_EPIER_EPIE4		(0x10)
-#define EPORT_EPIER_EPIE3		(0x08)
-#define EPORT_EPIER_EPIE2		(0x04)
-#define EPORT_EPIER_EPIE1		(0x02)
-
-#define EPORT_EPDR_EPDR7		EPORT_EPIER_EPIE7
-#define EPORT_EPDR_EPDR6		EPORT_EPIER_EPIE6
-#define EPORT_EPDR_EPDR5		EPORT_EPIER_EPIE5
-#define EPORT_EPDR_EPDR4		EPORT_EPIER_EPIE4
-#define EPORT_EPDR_EPDR3		EPORT_EPIER_EPIE3
-#define EPORT_EPDR_EPDR2		EPORT_EPIER_EPIE2
-#define EPORT_EPDR_EPDR1		EPORT_EPIER_EPIE1
-
-#define EPORT_EPPDR_EPPDR7		EPORT_EPIER_EPIE7
-#define EPORT_EPPDR_EPPDR6		EPORT_EPIER_EPIE6
-#define EPORT_EPPDR_EPPDR5		EPORT_EPIER_EPIE5
-#define EPORT_EPPDR_EPPDR4		EPORT_EPIER_EPIE4
-#define EPORT_EPPDR_EPPDR3		EPORT_EPIER_EPIE3
-#define EPORT_EPPDR_EPPDR2		EPORT_EPIER_EPIE2
-#define EPORT_EPPDR_EPPDR1		EPORT_EPIER_EPIE1
-
-/*********************************************************************
 * Watchdog Timer Modules (WTM)
 *********************************************************************/
 /* Bit definitions and macros for WTM_WCR */
@@ -809,97 +599,4 @@
 #define WTM_WCR_HALTED			(0x0002)
 #define WTM_WCR_EN			(0x0001)
 
-/*********************************************************************
-* FlexCAN Module (CAN)
-*********************************************************************/
-/* Bit definitions and macros for CAN_CANMCR */
-#define CANMCR_MDIS			(0x80000000)
-#define CANMCR_FRZ			(0x40000000)
-#define CANMCR_HALT			(0x10000000)
-#define CANMCR_NORDY			(0x08000000)
-#define CANMCR_SOFTRST			(0x02000000)
-#define CANMCR_FRZACK			(0x01000000)
-#define CANMCR_SUPV			(0x00800000)
-#define CANMCR_LPMACK			(0x00100000)
-#define CANMCR_MAXMB(x)			(((x)&0x0F))
-
-/* Bit definitions and macros for CAN_CANCTRL */
-#define CANCTRL_PRESDIV(x)		(((x)&0xFF)<<24)
-#define CANCTRL_RJW(x)			(((x)&0x03)<<22)
-#define CANCTRL_PSEG1(x)		(((x)&0x07)<<19)
-#define CANCTRL_PSEG2(x)		(((x)&0x07)<<16)
-#define CANCTRL_BOFFMSK			(0x00008000)
-#define CANCTRL_ERRMSK			(0x00004000)
-#define CANCTRL_CLKSRC			(0x00002000)
-#define CANCTRL_LPB			(0x00001000)
-#define CANCTRL_SMP			(0x00000080)
-#define CANCTRL_BOFFREC			(0x00000040)
-#define CANCTRL_TSYNC			(0x00000020)
-#define CANCTRL_LBUF			(0x00000010)
-#define CANCTRL_LOM			(0x00000008)
-#define CANCTRL_PROPSEG(x)		(((x)&0x07))
-
-/* Bit definitions and macros for CAN_TIMER */
-#define TIMER_TIMER(x)			((x)&0xFFFF)
-
-/* Bit definitions and macros for CAN_RXGMASK */
-#define RXGMASK_MI(x)			((x)&0x1FFFFFFF)
-
-/* Bit definitions and macros for CAN_ERRCNT */
-#define ERRCNT_TXECTR(x)		(((x)&0xFF))
-#define ERRCNT_RXECTR(x)		(((x)&0xFF)<<8)
-
-/* Bit definitions and macros for CAN_ERRSTAT */
-#define ERRSTAT_BITERR1			(0x00008000)
-#define ERRSTAT_BITERR0			(0x00004000)
-#define ERRSTAT_ACKERR			(0x00002000)
-#define ERRSTAT_CRCERR			(0x00001000)
-#define ERRSTAT_FRMERR			(0x00000800)
-#define ERRSTAT_STFERR			(0x00000400)
-#define ERRSTAT_TXWRN			(0x00000200)
-#define ERRSTAT_RXWRN			(0x00000100)
-#define ERRSTAT_IDLE			(0x00000080)
-#define ERRSTAT_TXRX			(0x00000040)
-#define ERRSTAT_FLT_BUSOFF		(0x00000020)
-#define ERRSTAT_FLT_PASSIVE		(0x00000010)
-#define ERRSTAT_FLT_ACTIVE		(0x00000000)
-#define ERRSTAT_BOFFINT			(0x00000004)
-#define ERRSTAT_ERRINT			(0x00000002)
-
-/* Bit definitions and macros for CAN_IMASK */
-#define IMASK_BUF15M			(0x00008000)
-#define IMASK_BUF14M			(0x00004000)
-#define IMASK_BUF13M			(0x00002000)
-#define IMASK_BUF12M			(0x00001000)
-#define IMASK_BUF11M			(0x00000800)
-#define IMASK_BUF10M			(0x00000400)
-#define IMASK_BUF9M			(0x00000200)
-#define IMASK_BUF8M			(0x00000100)
-#define IMASK_BUF7M			(0x00000080)
-#define IMASK_BUF6M			(0x00000040)
-#define IMASK_BUF5M			(0x00000020)
-#define IMASK_BUF4M			(0x00000010)
-#define IMASK_BUF3M			(0x00000008)
-#define IMASK_BUF2M			(0x00000004)
-#define IMASK_BUF1M			(0x00000002)
-#define IMASK_BUF0M			(0x00000001)
-
-/* Bit definitions and macros for CAN_IFLAG */
-#define IFLAG_BUF15I			(0x00008000)
-#define IFLAG_BUF14I			(0x00004000)
-#define IFLAG_BUF13I			(0x00002000)
-#define IFLAG_BUF12I			(0x00001000)
-#define IFLAG_BUF11I			(0x00000800)
-#define IFLAG_BUF10I			(0x00000400)
-#define IFLAG_BUF9I			(0x00000200)
-#define IFLAG_BUF8I			(0x00000100)
-#define IFLAG_BUF7I			(0x00000080)
-#define IFLAG_BUF6I			(0x00000040)
-#define IFLAG_BUF5I			(0x00000020)
-#define IFLAG_BUF4I			(0x00000010)
-#define IFLAG_BUF3I			(0x00000008)
-#define IFLAG_BUF2I			(0x00000004)
-#define IFLAG_BUF1I			(0x00000002)
-#define IFLAG_BUF0I			(0x00000001)
-
 #endif				/* mcf5235_h */
diff --git a/include/asm-m68k/m5249.h b/include/asm-m68k/m5249.h
index facf0c9..fa0cb14 100644
--- a/include/asm-m68k/m5249.h
+++ b/include/asm-m68k/m5249.h
@@ -31,14 +31,14 @@
 /*
  * useful definitions for reading/writing MBAR offset memory
  */
-#define mbar_readLong(x)	*((volatile unsigned long *) (CFG_MBAR + x))
-#define mbar_writeLong(x,y)	*((volatile unsigned long *) (CFG_MBAR + x)) = y
-#define mbar_writeShort(x,y)	*((volatile unsigned short *) (CFG_MBAR + x)) = y
-#define mbar_writeByte(x,y)	*((volatile unsigned char *) (CFG_MBAR + x)) = y
-#define mbar2_readLong(x)	*((volatile unsigned long *) (CFG_MBAR2 + x))
-#define mbar2_writeLong(x,y)	*((volatile unsigned long *) (CFG_MBAR2 + x)) = y
-#define mbar2_writeShort(x,y)	*((volatile unsigned short *) (CFG_MBAR2 + x)) = y
-#define mbar2_writeByte(x,y)	*((volatile unsigned char *) (CFG_MBAR2 + x)) = y
+#define mbar_readLong(x)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x))
+#define mbar_writeLong(x,y)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y
+#define mbar_writeShort(x,y)	*((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y
+#define mbar_writeByte(x,y)	*((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y
+#define mbar2_readLong(x)	*((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x))
+#define mbar2_writeLong(x,y)	*((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) = y
+#define mbar2_writeShort(x,y)	*((volatile unsigned short *) (CONFIG_SYS_MBAR2 + x)) = y
+#define mbar2_writeByte(x,y)	*((volatile unsigned char *) (CONFIG_SYS_MBAR2 + x)) = y
 
 /*
  * Size of internal RAM
@@ -77,19 +77,6 @@
 #define MCFSIM_IPR		0x40	/* Interrupt Pend reg (r/w) */
 #define MCFSIM_IMR		0x44	/* Interrupt Mask reg (r/w) */
 
-#define MCFSIM_CSAR0		0x80	/* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0		0x84	/* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0		0x8a	/* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1		0x8c	/* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1		0x90	/* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1		0x96	/* CS 1 Control reg (r/w) */
-#define MCFSIM_CSAR2		0x98	/* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2		0x9c	/* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2		0xa2	/* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3		0xa4	/* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3		0xa8	/* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3		0xae	/* CS 3 Control reg (r/w) */
-
 #define MCFSIM_DCR		0x100	/* DRAM Control reg (r/w) */
 #define MCFSIM_DACR0		0x108	/* DRAM 0 Addr and Ctrl (r/w) */
 #define MCFSIM_DMR0		0x10c	/* DRAM 0 Mask reg (r/w) */
diff --git a/include/asm-m68k/m5271.h b/include/asm-m68k/m5271.h
index be34398..d25261b 100644
--- a/include/asm-m68k/m5271.h
+++ b/include/asm-m68k/m5271.h
@@ -28,17 +28,36 @@
 #ifndef	_MCF5271_H_
 #define	_MCF5271_H_
 
-#define mbar_readLong(x)	*((volatile unsigned long *) (CFG_MBAR + x))
-#define mbar_readShort(x)	*((volatile unsigned short *) (CFG_MBAR + x))
-#define mbar_readByte(x)	*((volatile unsigned char *) (CFG_MBAR + x))
-#define mbar_writeLong(x,y)	*((volatile unsigned long *) (CFG_MBAR + x)) = y
-#define mbar_writeShort(x,y)	*((volatile unsigned short *) (CFG_MBAR + x)) = y
-#define mbar_writeByte(x,y)	*((volatile unsigned char *) (CFG_MBAR + x)) = y
+#define mbar_readLong(x)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x))
+#define mbar_readShort(x)	*((volatile unsigned short *) (CONFIG_SYS_MBAR + x))
+#define mbar_readByte(x)	*((volatile unsigned char *) (CONFIG_SYS_MBAR + x))
+#define mbar_writeLong(x,y)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y
+#define mbar_writeShort(x,y)	*((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y
+#define mbar_writeByte(x,y)	*((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y
 
 #define MCF_FMPLL_SYNCR				0x120000
 #define MCF_FMPLL_SYNSR				0x120004
+
 #define MCF_FMPLL_SYNCR_MFD(x)			((x&0x7)<<24)
+#define MCF_SYNCR_MFD_4X		0x00000000
+#define MCF_SYNCR_MFD_6X		0x01000000
+#define MCF_SYNCR_MFD_8X		0x02000000
+#define MCF_SYNCR_MFD_10X		0x03000000
+#define MCF_SYNCR_MFD_12X		0x04000000
+#define MCF_SYNCR_MFD_14X		0x05000000
+#define MCF_SYNCR_MFD_16X		0x06000000
+#define MCF_SYNCR_MFD_18X		0x07000000
+
 #define MCF_FMPLL_SYNCR_RFD(x)			((x&0x7)<<19)
+#define MCF_SYNCR_RFD_DIV1		0x00000000
+#define MCF_SYNCR_RFD_DIV2		0x00080000
+#define MCF_SYNCR_RFD_DIV4		0x00100000
+#define MCF_SYNCR_RFD_DIV8		0x00180000
+#define MCF_SYNCR_RFD_DIV16		0x00200000
+#define MCF_SYNCR_RFD_DIV32		0x00280000
+#define MCF_SYNCR_RFD_DIV64		0x00300000
+#define MCF_SYNCR_RFD_DIV128		0x00380000
+
 #define MCF_FMPLL_SYNSR_LOCK			0x8
 
 #define MCF_WTM_WCR				0x140000
@@ -50,17 +69,79 @@
 #define MCF_RCM_RCR_FRCRSTOUT			0x40
 #define MCF_RCM_RCR_SOFTRST			0x80
 
+#define MCF_GPIO_PODR_ADDR			0x100000
+#define MCF_GPIO_PODR_DATAH			0x100001
+#define MCF_GPIO_PODR_DATAL			0x100002
+#define MCF_GPIO_PODR_BUSCTL			0x100003
+#define MCF_GPIO_PODR_BS			0x100004
+#define MCF_GPIO_PODR_CS			0x100005
+#define MCF_GPIO_PODR_SDRAM			0x100006
+#define MCF_GPIO_PODR_FECI2C			0x100007
+#define MCF_GPIO_PODR_UARTH			0x100008
+#define MCF_GPIO_PODR_UARTL			0x100009
+#define MCF_GPIO_PODR_QSPI			0x10000A
+#define MCF_GPIO_PODR_TIMER			0x10000B
+
+#define MCF_GPIO_PDDR_ADDR			0x100010
+#define MCF_GPIO_PDDR_DATAH			0x100011
+#define MCF_GPIO_PDDR_DATAL			0x100012
+#define MCF_GPIO_PDDR_BUSCTL			0x100013
+#define MCF_GPIO_PDDR_BS			0x100014
+#define MCF_GPIO_PDDR_CS			0x100015
+#define MCF_GPIO_PDDR_SDRAM			0x100016
+#define MCF_GPIO_PDDR_FECI2C			0x100017
+#define MCF_GPIO_PDDR_UARTH			0x100018
+#define MCF_GPIO_PDDR_UARTL			0x100019
+#define MCF_GPIO_PDDR_QSPI			0x10001A
+#define MCF_GPIO_PDDR_TIMER			0x10001B
+
+#define MCF_GPIO_PPDSDR_ADDR			0x100020
+#define MCF_GPIO_PPDSDR_DATAH			0x100021
+#define MCF_GPIO_PPDSDR_DATAL			0x100022
+#define MCF_GPIO_PPDSDR_BUSCTL			0x100023
+#define MCF_GPIO_PPDSDR_BS			0x100024
+#define MCF_GPIO_PPDSDR_CS			0x100025
+#define MCF_GPIO_PPDSDR_SDRAM			0x100026
+#define MCF_GPIO_PPDSDR_FECI2C			0x100027
+#define MCF_GPIO_PPDSDR_UARTH			0x100028
+#define MCF_GPIO_PPDSDR_UARTL			0x100029
+#define MCF_GPIO_PPDSDR_QSPI			0x10002A
+#define MCF_GPIO_PPDSDR_TIMER			0x10002B
+
+#define MCF_GPIO_PCLRR_ADDR			0x100030
+#define MCF_GPIO_PCLRR_DATAH			0x100031
+#define MCF_GPIO_PCLRR_DATAL			0x100032
+#define MCF_GPIO_PCLRR_BUSCTL			0x100033
+#define MCF_GPIO_PCLRR_BS			0x100034
+#define MCF_GPIO_PCLRR_CS			0x100035
+#define MCF_GPIO_PCLRR_SDRAM			0x100036
+#define MCF_GPIO_PCLRR_FECI2C			0x100037
+#define MCF_GPIO_PCLRR_UARTH			0x100038
+#define MCF_GPIO_PCLRR_UARTL			0x100039
+#define MCF_GPIO_PCLRR_QSPI			0x10003A
+#define MCF_GPIO_PCLRR_TIMER			0x10003B
+
 #define MCF_GPIO_PAR_AD				0x100040
+#define MCF_GPIO_PAR_BUSCTL			0x100042
+#define MCF_GPIO_PAR_BS				0x100044
 #define MCF_GPIO_PAR_CS				0x100045
 #define MCF_GPIO_PAR_SDRAM			0x100046
 #define MCF_GPIO_PAR_FECI2C			0x100047
 #define MCF_GPIO_PAR_UART			0x100048
+#define MCF_GPIO_PAR_QSPI			0x10004A
+#define MCF_GPIO_PAR_TIMER			0x10004C
+
+#define MCF_DSCR_EIM				0x100050
+#define MCF_DCSR_FEC12C 			0x100052
+#define MCF_DCSR_UART				0x100053
+#define MCF_DCSR_QSPI				0x100054
+#define MCF_DCSR_TIMER				0x100055
 
 #define MCF_CCM_CIR				0x11000A
 #define MCF_CCM_CIR_PRN_MASK			0x3F
 #define MCF_CCM_CIR_PIN_LEN			6
-#define MCF_CCM_CIR_PIN_MCF5270			0x2e
-#define MCF_CCM_CIR_PIN_MCF5271			0x80
+#define MCF_CCM_CIR_PIN_MCF5270			0x002e
+#define MCF_CCM_CIR_PIN_MCF5271			0x0032
 
 #define MCF_GPIO_AD_ADDR23			0x80
 #define MCF_GPIO_AD_ADDR22			0x40
@@ -116,9 +197,7 @@
 
 #define MCFSIM_ICR1				0x000C41
 
-/*********************************************************************
-* Interrupt Controller (INTC)
-*********************************************************************/
+/* Interrupt Controller (INTC) */
 #define INT0_LO_RSVD0			(0)
 #define INT0_LO_EPORT1			(1)
 #define INT0_LO_EPORT2			(2)
@@ -182,38 +261,4 @@
 #define INT0_HI_CAN1_BOFFINT		(60)
 /* 60-63 Reserved */
 
-/* Bit definitions and macros for INTC_IPRL */
-#define INTC_IPRL_INT31			(0x80000000)
-#define INTC_IPRL_INT30			(0x40000000)
-#define INTC_IPRL_INT29			(0x20000000)
-#define INTC_IPRL_INT28			(0x10000000)
-#define INTC_IPRL_INT27			(0x08000000)
-#define INTC_IPRL_INT26			(0x04000000)
-#define INTC_IPRL_INT25			(0x02000000)
-#define INTC_IPRL_INT24			(0x01000000)
-#define INTC_IPRL_INT23			(0x00800000)
-#define INTC_IPRL_INT22			(0x00400000)
-#define INTC_IPRL_INT21			(0x00200000)
-#define INTC_IPRL_INT20			(0x00100000)
-#define INTC_IPRL_INT19			(0x00080000)
-#define INTC_IPRL_INT18			(0x00040000)
-#define INTC_IPRL_INT17			(0x00020000)
-#define INTC_IPRL_INT16			(0x00010000)
-#define INTC_IPRL_INT15			(0x00008000)
-#define INTC_IPRL_INT14			(0x00004000)
-#define INTC_IPRL_INT13			(0x00002000)
-#define INTC_IPRL_INT12			(0x00001000)
-#define INTC_IPRL_INT11			(0x00000800)
-#define INTC_IPRL_INT10			(0x00000400)
-#define INTC_IPRL_INT9			(0x00000200)
-#define INTC_IPRL_INT8			(0x00000100)
-#define INTC_IPRL_INT7			(0x00000080)
-#define INTC_IPRL_INT6			(0x00000040)
-#define INTC_IPRL_INT5			(0x00000020)
-#define INTC_IPRL_INT4			(0x00000010)
-#define INTC_IPRL_INT3			(0x00000008)
-#define INTC_IPRL_INT2			(0x00000004)
-#define INTC_IPRL_INT1			(0x00000002)
-#define INTC_IPRL_INT0			(0x00000001)
-
 #endif				/* _MCF5271_H_ */
diff --git a/include/asm-m68k/m5275.h b/include/asm-m68k/m5275.h
index 89c6c92..24dbae2 100644
--- a/include/asm-m68k/m5275.h
+++ b/include/asm-m68k/m5275.h
@@ -30,18 +30,6 @@
  * Define the 5275 SIM register set addresses. These are similar,
  * but not quite identical to the 5282 registers and offsets.
  */
-#define	MCFICM_INTC0		0x0c00		/* Base for Interrupt Ctrl 0 */
-#define	MCFICM_INTC1		0x0d00		/* Base for Interrupt Ctrl 1 */
-#define	MCFINTC_IPRH		0x00		/* Interrupt pending 32-63 */
-#define	MCFINTC_IPRL		0x04		/* Interrupt pending 1-31 */
-#define	MCFINTC_IMRH		0x08		/* Interrupt mask 32-63 */
-#define	MCFINTC_IMRL		0x0c		/* Interrupt mask 1-31 */
-#define	MCFINTC_INTFRCH		0x10		/* Interrupt force 32-63 */
-#define	MCFINTC_INTFRCL		0x14		/* Interrupt force 1-31 */
-#define	MCFINTC_IRLR		0x18		/* */
-#define	MCFINTC_IACKL		0x19		/* */
-#define	MCFINTC_ICR0		0x40		/* Base ICR register */
-
 #define MCF_GPIO_PAR_UART	0x10007c
 #define UART0_ENABLE_MASK	0x000f
 #define UART1_ENABLE_MASK	0x00f0
@@ -198,40 +186,6 @@
 #define INT1_HI_FEC1_BABR	(35)
 /* 36-63 Reserved */
 
-/* Bit definitions and macros for INTC_IPRL */
-#define INTC_IPRL_INT31		(0x80000000)
-#define INTC_IPRL_INT30		(0x40000000)
-#define INTC_IPRL_INT29		(0x20000000)
-#define INTC_IPRL_INT28		(0x10000000)
-#define INTC_IPRL_INT27		(0x08000000)
-#define INTC_IPRL_INT26		(0x04000000)
-#define INTC_IPRL_INT25		(0x02000000)
-#define INTC_IPRL_INT24		(0x01000000)
-#define INTC_IPRL_INT23		(0x00800000)
-#define INTC_IPRL_INT22		(0x00400000)
-#define INTC_IPRL_INT21		(0x00200000)
-#define INTC_IPRL_INT20		(0x00100000)
-#define INTC_IPRL_INT19		(0x00080000)
-#define INTC_IPRL_INT18		(0x00040000)
-#define INTC_IPRL_INT17		(0x00020000)
-#define INTC_IPRL_INT16		(0x00010000)
-#define INTC_IPRL_INT15		(0x00008000)
-#define INTC_IPRL_INT14		(0x00004000)
-#define INTC_IPRL_INT13		(0x00002000)
-#define INTC_IPRL_INT12		(0x00001000)
-#define INTC_IPRL_INT11		(0x00000800)
-#define INTC_IPRL_INT10		(0x00000400)
-#define INTC_IPRL_INT9		(0x00000200)
-#define INTC_IPRL_INT8		(0x00000100)
-#define INTC_IPRL_INT7		(0x00000080)
-#define INTC_IPRL_INT6		(0x00000040)
-#define INTC_IPRL_INT5		(0x00000020)
-#define INTC_IPRL_INT4		(0x00000010)
-#define INTC_IPRL_INT3		(0x00000008)
-#define INTC_IPRL_INT2		(0x00000004)
-#define INTC_IPRL_INT1		(0x00000002)
-#define INTC_IPRL_INT0		(0x00000001)
-
 /* Bit definitions and macros for RCR */
 #define RCM_RCR_FRCRSTOUT	(0x40)
 #define RCM_RCR_SOFTRST		(0x80)
diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h
index f6a6b04..d59a8b2 100644
--- a/include/asm-m68k/m5282.h
+++ b/include/asm-m68k/m5282.h
@@ -125,112 +125,112 @@
 
 /* General Purpose I/O Module GPIO */
 
-#define MCFGPIO_PORTA		(*(vu_char *) (CFG_MBAR+0x100000))
-#define MCFGPIO_PORTB		(*(vu_char *) (CFG_MBAR+0x100001))
-#define MCFGPIO_PORTC		(*(vu_char *) (CFG_MBAR+0x100002))
-#define MCFGPIO_PORTD		(*(vu_char *) (CFG_MBAR+0x100003))
-#define MCFGPIO_PORTE		(*(vu_char *) (CFG_MBAR+0x100004))
-#define MCFGPIO_PORTF		(*(vu_char *) (CFG_MBAR+0x100005))
-#define MCFGPIO_PORTG		(*(vu_char *) (CFG_MBAR+0x100006))
-#define MCFGPIO_PORTH		(*(vu_char *) (CFG_MBAR+0x100007))
-#define MCFGPIO_PORTJ		(*(vu_char *) (CFG_MBAR+0x100008))
-#define MCFGPIO_PORTDD		(*(vu_char *) (CFG_MBAR+0x100009))
-#define MCFGPIO_PORTEH		(*(vu_char *) (CFG_MBAR+0x10000A))
-#define MCFGPIO_PORTEL		(*(vu_char *) (CFG_MBAR+0x10000B))
-#define MCFGPIO_PORTAS		(*(vu_char *) (CFG_MBAR+0x10000C))
-#define MCFGPIO_PORTQS		(*(vu_char *) (CFG_MBAR+0x10000D))
-#define MCFGPIO_PORTSD		(*(vu_char *) (CFG_MBAR+0x10000E))
-#define MCFGPIO_PORTTC		(*(vu_char *) (CFG_MBAR+0x10000F))
-#define MCFGPIO_PORTTD		(*(vu_char *) (CFG_MBAR+0x100010))
-#define MCFGPIO_PORTUA		(*(vu_char *) (CFG_MBAR+0x100011))
-
-#define MCFGPIO_DDRA		(*(vu_char *) (CFG_MBAR+0x100014))
-#define MCFGPIO_DDRB		(*(vu_char *) (CFG_MBAR+0x100015))
-#define MCFGPIO_DDRC		(*(vu_char *) (CFG_MBAR+0x100016))
-#define MCFGPIO_DDRD		(*(vu_char *) (CFG_MBAR+0x100017))
-#define MCFGPIO_DDRE		(*(vu_char *) (CFG_MBAR+0x100018))
-#define MCFGPIO_DDRF		(*(vu_char *) (CFG_MBAR+0x100019))
-#define MCFGPIO_DDRG		(*(vu_char *) (CFG_MBAR+0x10001A))
-#define MCFGPIO_DDRH		(*(vu_char *) (CFG_MBAR+0x10001B))
-#define MCFGPIO_DDRJ		(*(vu_char *) (CFG_MBAR+0x10001C))
-#define MCFGPIO_DDRDD		(*(vu_char *) (CFG_MBAR+0x10001D))
-#define MCFGPIO_DDREH		(*(vu_char *) (CFG_MBAR+0x10001E))
-#define MCFGPIO_DDREL		(*(vu_char *) (CFG_MBAR+0x10001F))
-#define MCFGPIO_DDRAS		(*(vu_char *) (CFG_MBAR+0x100020))
-#define MCFGPIO_DDRQS		(*(vu_char *) (CFG_MBAR+0x100021))
-#define MCFGPIO_DDRSD		(*(vu_char *) (CFG_MBAR+0x100022))
-#define MCFGPIO_DDRTC		(*(vu_char *) (CFG_MBAR+0x100023))
-#define MCFGPIO_DDRTD		(*(vu_char *) (CFG_MBAR+0x100024))
-#define MCFGPIO_DDRUA		(*(vu_char *) (CFG_MBAR+0x100025))
-
-#define MCFGPIO_PORTAP		(*(vu_char *) (CFG_MBAR+0x100028))
-#define MCFGPIO_PORTBP		(*(vu_char *) (CFG_MBAR+0x100029))
-#define MCFGPIO_PORTCP		(*(vu_char *) (CFG_MBAR+0x10002A))
-#define MCFGPIO_PORTDP		(*(vu_char *) (CFG_MBAR+0x10002B))
-#define MCFGPIO_PORTEP		(*(vu_char *) (CFG_MBAR+0x10002C))
-#define MCFGPIO_PORTFP		(*(vu_char *) (CFG_MBAR+0x10002D))
-#define MCFGPIO_PORTGP		(*(vu_char *) (CFG_MBAR+0x10002E))
-#define MCFGPIO_PORTHP		(*(vu_char *) (CFG_MBAR+0x10002F))
-#define MCFGPIO_PORTJP		(*(vu_char *) (CFG_MBAR+0x100030))
-#define MCFGPIO_PORTDDP		(*(vu_char *) (CFG_MBAR+0x100031))
-#define MCFGPIO_PORTEHP		(*(vu_char *) (CFG_MBAR+0x100032))
-#define MCFGPIO_PORTELP		(*(vu_char *) (CFG_MBAR+0x100033))
-#define MCFGPIO_PORTASP		(*(vu_char *) (CFG_MBAR+0x100034))
-#define MCFGPIO_PORTQSP		(*(vu_char *) (CFG_MBAR+0x100035))
-#define MCFGPIO_PORTSDP		(*(vu_char *) (CFG_MBAR+0x100036))
-#define MCFGPIO_PORTTCP		(*(vu_char *) (CFG_MBAR+0x100037))
-#define MCFGPIO_PORTTDP		(*(vu_char *) (CFG_MBAR+0x100038))
-#define MCFGPIO_PORTUAP		(*(vu_char *) (CFG_MBAR+0x100039))
-
-#define MCFGPIO_SETA		(*(vu_char *) (CFG_MBAR+0x100028))
-#define MCFGPIO_SETB		(*(vu_char *) (CFG_MBAR+0x100029))
-#define MCFGPIO_SETC		(*(vu_char *) (CFG_MBAR+0x10002A))
-#define MCFGPIO_SETD		(*(vu_char *) (CFG_MBAR+0x10002B))
-#define MCFGPIO_SETE		(*(vu_char *) (CFG_MBAR+0x10002C))
-#define MCFGPIO_SETF		(*(vu_char *) (CFG_MBAR+0x10002D))
-#define MCFGPIO_SETG		(*(vu_char *) (CFG_MBAR+0x10002E))
-#define MCFGPIO_SETH		(*(vu_char *) (CFG_MBAR+0x10002F))
-#define MCFGPIO_SETJ		(*(vu_char *) (CFG_MBAR+0x100030))
-#define MCFGPIO_SETDD		(*(vu_char *) (CFG_MBAR+0x100031))
-#define MCFGPIO_SETEH		(*(vu_char *) (CFG_MBAR+0x100032))
-#define MCFGPIO_SETEL		(*(vu_char *) (CFG_MBAR+0x100033))
-#define MCFGPIO_SETAS		(*(vu_char *) (CFG_MBAR+0x100034))
-#define MCFGPIO_SETQS		(*(vu_char *) (CFG_MBAR+0x100035))
-#define MCFGPIO_SETSD		(*(vu_char *) (CFG_MBAR+0x100036))
-#define MCFGPIO_SETTC		(*(vu_char *) (CFG_MBAR+0x100037))
-#define MCFGPIO_SETTD		(*(vu_char *) (CFG_MBAR+0x100038))
-#define MCFGPIO_SETUA		(*(vu_char *) (CFG_MBAR+0x100039))
-
-#define MCFGPIO_CLRA		(*(vu_char *) (CFG_MBAR+0x10003C))
-#define MCFGPIO_CLRB		(*(vu_char *) (CFG_MBAR+0x10003D))
-#define MCFGPIO_CLRC		(*(vu_char *) (CFG_MBAR+0x10003E))
-#define MCFGPIO_CLRD		(*(vu_char *) (CFG_MBAR+0x10003F))
-#define MCFGPIO_CLRE		(*(vu_char *) (CFG_MBAR+0x100040))
-#define MCFGPIO_CLRF		(*(vu_char *) (CFG_MBAR+0x100041))
-#define MCFGPIO_CLRG		(*(vu_char *) (CFG_MBAR+0x100042))
-#define MCFGPIO_CLRH		(*(vu_char *) (CFG_MBAR+0x100043))
-#define MCFGPIO_CLRJ		(*(vu_char *) (CFG_MBAR+0x100044))
-#define MCFGPIO_CLRDD		(*(vu_char *) (CFG_MBAR+0x100045))
-#define MCFGPIO_CLREH		(*(vu_char *) (CFG_MBAR+0x100046))
-#define MCFGPIO_CLREL		(*(vu_char *) (CFG_MBAR+0x100047))
-#define MCFGPIO_CLRAS		(*(vu_char *) (CFG_MBAR+0x100048))
-#define MCFGPIO_CLRQS		(*(vu_char *) (CFG_MBAR+0x100049))
-#define MCFGPIO_CLRSD		(*(vu_char *) (CFG_MBAR+0x10004A))
-#define MCFGPIO_CLRTC		(*(vu_char *) (CFG_MBAR+0x10004B))
-#define MCFGPIO_CLRTD		(*(vu_char *) (CFG_MBAR+0x10004C))
-#define MCFGPIO_CLRUA		(*(vu_char *) (CFG_MBAR+0x10004D))
-
-#define MCFGPIO_PBCDPAR	(*(vu_char *) (CFG_MBAR+0x100050))
-#define MCFGPIO_PFPAR		(*(vu_char *) (CFG_MBAR+0x100051))
-#define MCFGPIO_PEPAR		(*(vu_short *)(CFG_MBAR+0x100052))
-#define MCFGPIO_PJPAR		(*(vu_char *) (CFG_MBAR+0x100054))
-#define MCFGPIO_PSDPAR		(*(vu_char *) (CFG_MBAR+0x100055))
-#define MCFGPIO_PASPAR		(*(vu_short *)(CFG_MBAR+0x100056))
-#define MCFGPIO_PEHLPAR		(*(vu_char *) (CFG_MBAR+0x100058))
-#define MCFGPIO_PQSPAR		(*(vu_char *) (CFG_MBAR+0x100059))
-#define MCFGPIO_PTCPAR		(*(vu_char *) (CFG_MBAR+0x10005A))
-#define MCFGPIO_PTDPAR		(*(vu_char *) (CFG_MBAR+0x10005B))
-#define MCFGPIO_PUAPAR		(*(vu_char *) (CFG_MBAR+0x10005C))
+#define MCFGPIO_PORTA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100000))
+#define MCFGPIO_PORTB		(*(vu_char *) (CONFIG_SYS_MBAR+0x100001))
+#define MCFGPIO_PORTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x100002))
+#define MCFGPIO_PORTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100003))
+#define MCFGPIO_PORTE		(*(vu_char *) (CONFIG_SYS_MBAR+0x100004))
+#define MCFGPIO_PORTF		(*(vu_char *) (CONFIG_SYS_MBAR+0x100005))
+#define MCFGPIO_PORTG		(*(vu_char *) (CONFIG_SYS_MBAR+0x100006))
+#define MCFGPIO_PORTH		(*(vu_char *) (CONFIG_SYS_MBAR+0x100007))
+#define MCFGPIO_PORTJ		(*(vu_char *) (CONFIG_SYS_MBAR+0x100008))
+#define MCFGPIO_PORTDD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100009))
+#define MCFGPIO_PORTEH		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000A))
+#define MCFGPIO_PORTEL		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000B))
+#define MCFGPIO_PORTAS		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000C))
+#define MCFGPIO_PORTQS		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000D))
+#define MCFGPIO_PORTSD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000E))
+#define MCFGPIO_PORTTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000F))
+#define MCFGPIO_PORTTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100010))
+#define MCFGPIO_PORTUA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100011))
+
+#define MCFGPIO_DDRA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100014))
+#define MCFGPIO_DDRB		(*(vu_char *) (CONFIG_SYS_MBAR+0x100015))
+#define MCFGPIO_DDRC		(*(vu_char *) (CONFIG_SYS_MBAR+0x100016))
+#define MCFGPIO_DDRD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100017))
+#define MCFGPIO_DDRE		(*(vu_char *) (CONFIG_SYS_MBAR+0x100018))
+#define MCFGPIO_DDRF		(*(vu_char *) (CONFIG_SYS_MBAR+0x100019))
+#define MCFGPIO_DDRG		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001A))
+#define MCFGPIO_DDRH		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001B))
+#define MCFGPIO_DDRJ		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001C))
+#define MCFGPIO_DDRDD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001D))
+#define MCFGPIO_DDREH		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001E))
+#define MCFGPIO_DDREL		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001F))
+#define MCFGPIO_DDRAS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100020))
+#define MCFGPIO_DDRQS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100021))
+#define MCFGPIO_DDRSD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100022))
+#define MCFGPIO_DDRTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x100023))
+#define MCFGPIO_DDRTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100024))
+#define MCFGPIO_DDRUA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100025))
+
+#define MCFGPIO_PORTAP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100028))
+#define MCFGPIO_PORTBP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100029))
+#define MCFGPIO_PORTCP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002A))
+#define MCFGPIO_PORTDP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002B))
+#define MCFGPIO_PORTEP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002C))
+#define MCFGPIO_PORTFP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002D))
+#define MCFGPIO_PORTGP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002E))
+#define MCFGPIO_PORTHP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002F))
+#define MCFGPIO_PORTJP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100030))
+#define MCFGPIO_PORTDDP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100031))
+#define MCFGPIO_PORTEHP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100032))
+#define MCFGPIO_PORTELP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100033))
+#define MCFGPIO_PORTASP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100034))
+#define MCFGPIO_PORTQSP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100035))
+#define MCFGPIO_PORTSDP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100036))
+#define MCFGPIO_PORTTCP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100037))
+#define MCFGPIO_PORTTDP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100038))
+#define MCFGPIO_PORTUAP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100039))
+
+#define MCFGPIO_SETA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100028))
+#define MCFGPIO_SETB		(*(vu_char *) (CONFIG_SYS_MBAR+0x100029))
+#define MCFGPIO_SETC		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002A))
+#define MCFGPIO_SETD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002B))
+#define MCFGPIO_SETE		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002C))
+#define MCFGPIO_SETF		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002D))
+#define MCFGPIO_SETG		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002E))
+#define MCFGPIO_SETH		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002F))
+#define MCFGPIO_SETJ		(*(vu_char *) (CONFIG_SYS_MBAR+0x100030))
+#define MCFGPIO_SETDD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100031))
+#define MCFGPIO_SETEH		(*(vu_char *) (CONFIG_SYS_MBAR+0x100032))
+#define MCFGPIO_SETEL		(*(vu_char *) (CONFIG_SYS_MBAR+0x100033))
+#define MCFGPIO_SETAS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100034))
+#define MCFGPIO_SETQS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100035))
+#define MCFGPIO_SETSD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100036))
+#define MCFGPIO_SETTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x100037))
+#define MCFGPIO_SETTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100038))
+#define MCFGPIO_SETUA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100039))
+
+#define MCFGPIO_CLRA		(*(vu_char *) (CONFIG_SYS_MBAR+0x10003C))
+#define MCFGPIO_CLRB		(*(vu_char *) (CONFIG_SYS_MBAR+0x10003D))
+#define MCFGPIO_CLRC		(*(vu_char *) (CONFIG_SYS_MBAR+0x10003E))
+#define MCFGPIO_CLRD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10003F))
+#define MCFGPIO_CLRE		(*(vu_char *) (CONFIG_SYS_MBAR+0x100040))
+#define MCFGPIO_CLRF		(*(vu_char *) (CONFIG_SYS_MBAR+0x100041))
+#define MCFGPIO_CLRG		(*(vu_char *) (CONFIG_SYS_MBAR+0x100042))
+#define MCFGPIO_CLRH		(*(vu_char *) (CONFIG_SYS_MBAR+0x100043))
+#define MCFGPIO_CLRJ		(*(vu_char *) (CONFIG_SYS_MBAR+0x100044))
+#define MCFGPIO_CLRDD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100045))
+#define MCFGPIO_CLREH		(*(vu_char *) (CONFIG_SYS_MBAR+0x100046))
+#define MCFGPIO_CLREL		(*(vu_char *) (CONFIG_SYS_MBAR+0x100047))
+#define MCFGPIO_CLRAS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100048))
+#define MCFGPIO_CLRQS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100049))
+#define MCFGPIO_CLRSD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10004A))
+#define MCFGPIO_CLRTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x10004B))
+#define MCFGPIO_CLRTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10004C))
+#define MCFGPIO_CLRUA		(*(vu_char *) (CONFIG_SYS_MBAR+0x10004D))
+
+#define MCFGPIO_PBCDPAR	(*(vu_char *) (CONFIG_SYS_MBAR+0x100050))
+#define MCFGPIO_PFPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100051))
+#define MCFGPIO_PEPAR		(*(vu_short *)(CONFIG_SYS_MBAR+0x100052))
+#define MCFGPIO_PJPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100054))
+#define MCFGPIO_PSDPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100055))
+#define MCFGPIO_PASPAR		(*(vu_short *)(CONFIG_SYS_MBAR+0x100056))
+#define MCFGPIO_PEHLPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100058))
+#define MCFGPIO_PQSPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100059))
+#define MCFGPIO_PTCPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x10005A))
+#define MCFGPIO_PTDPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x10005B))
+#define MCFGPIO_PUAPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x10005C))
 
 /* Bit level definitions and macros */
 #define MCFGPIO_PORT7			(0x80)
@@ -327,25 +327,25 @@
 
 /* System Conrol Module SCM */
 
-#define MCFSCM_RAMBAR		(*(vu_long *) (CFG_MBAR+0x00000008))
-#define MCFSCM_CRSR		(*(vu_char *) (CFG_MBAR+0x00000010))
-#define MCFSCM_CWCR		(*(vu_char *) (CFG_MBAR+0x00000011))
-#define MCFSCM_LPICR		(*(vu_char *) (CFG_MBAR+0x00000012))
-#define MCFSCM_CWSR		(*(vu_char *) (CFG_MBAR+0x00000013))
-
-#define MCFSCM_MPARK		(*(vu_long *) (CFG_MBAR+0x0000001C))
-#define MCFSCM_MPR		(*(vu_char *) (CFG_MBAR+0x00000020))
-#define MCFSCM_PACR0		(*(vu_char *) (CFG_MBAR+0x00000024))
-#define MCFSCM_PACR1		(*(vu_char *) (CFG_MBAR+0x00000025))
-#define MCFSCM_PACR2		(*(vu_char *) (CFG_MBAR+0x00000026))
-#define MCFSCM_PACR3		(*(vu_char *) (CFG_MBAR+0x00000027))
-#define MCFSCM_PACR4		(*(vu_char *) (CFG_MBAR+0x00000028))
-#define MCFSCM_PACR5		(*(vu_char *) (CFG_MBAR+0x0000002A))
-#define MCFSCM_PACR6		(*(vu_char *) (CFG_MBAR+0x0000002B))
-#define MCFSCM_PACR7		(*(vu_char *) (CFG_MBAR+0x0000002C))
-#define MCFSCM_PACR8		(*(vu_char *) (CFG_MBAR+0x0000002E))
-#define MCFSCM_GPACR0		(*(vu_char *) (CFG_MBAR+0x00000030))
-#define MCFSCM_GPACR1		(*(vu_char *) (CFG_MBAR+0x00000031))
+#define MCFSCM_RAMBAR		(*(vu_long *) (CONFIG_SYS_MBAR+0x00000008))
+#define MCFSCM_CRSR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000010))
+#define MCFSCM_CWCR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000011))
+#define MCFSCM_LPICR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000012))
+#define MCFSCM_CWSR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000013))
+
+#define MCFSCM_MPARK		(*(vu_long *) (CONFIG_SYS_MBAR+0x0000001C))
+#define MCFSCM_MPR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000020))
+#define MCFSCM_PACR0		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000024))
+#define MCFSCM_PACR1		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000025))
+#define MCFSCM_PACR2		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000026))
+#define MCFSCM_PACR3		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000027))
+#define MCFSCM_PACR4		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000028))
+#define MCFSCM_PACR5		(*(vu_char *) (CONFIG_SYS_MBAR+0x0000002A))
+#define MCFSCM_PACR6		(*(vu_char *) (CONFIG_SYS_MBAR+0x0000002B))
+#define MCFSCM_PACR7		(*(vu_char *) (CONFIG_SYS_MBAR+0x0000002C))
+#define MCFSCM_PACR8		(*(vu_char *) (CONFIG_SYS_MBAR+0x0000002E))
+#define MCFSCM_GPACR0		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000030))
+#define MCFSCM_GPACR1		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000031))
 
 #define MCFSCM_CRSR_EXT		(0x80)
 #define MCFSCM_CRSR_CWDR	(0x20)
@@ -354,8 +354,8 @@
 
 /* Reset Controller Module RCM */
 
-#define MCFRESET_RCR		(*(vu_char *) (CFG_MBAR+0x00110000))
-#define MCFRESET_RSR		(*(vu_char *) (CFG_MBAR+0x00110001))
+#define MCFRESET_RCR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00110000))
+#define MCFRESET_RSR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00110001))
 
 #define MCFRESET_RCR_SOFTRST	(0x80)
 #define MCFRESET_RCR_FRCRSTOUT	(0x40)
@@ -377,9 +377,9 @@
 
 /* Chip Configuration Module CCM */
 
-#define MCFCCM_CCR		(*(vu_short *)(CFG_MBAR+0x00110004))
-#define MCFCCM_RCON		(*(vu_short *)(CFG_MBAR+0x00110008))
-#define MCFCCM_CIR		(*(vu_short *)(CFG_MBAR+0x0011000A))
+#define MCFCCM_CCR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00110004))
+#define MCFCCM_RCON		(*(vu_short *)(CONFIG_SYS_MBAR+0x00110008))
+#define MCFCCM_CIR		(*(vu_short *)(CONFIG_SYS_MBAR+0x0011000A))
 
 /* Bit level definitions and macros */
 #define MCFCCM_CCR_LOAD		(0x8000)
@@ -394,18 +394,18 @@
 
 /* Clock Module */
 
-#define MCFCLOCK_SYNCR		(*(vu_short *)(CFG_MBAR+0x120000))
-#define MCFCLOCK_SYNSR		(*(vu_char *) (CFG_MBAR+0x120002))
+#define MCFCLOCK_SYNCR		(*(vu_short *)(CONFIG_SYS_MBAR+0x120000))
+#define MCFCLOCK_SYNSR		(*(vu_char *) (CONFIG_SYS_MBAR+0x120002))
 
 #define MCFCLOCK_SYNCR_MFD(x)	(((x)&0x0007)<<12)
 #define MCFCLOCK_SYNCR_RFD(x)	(((x)&0x0007)<<8)
 #define MCFCLOCK_SYNSR_LOCK	0x08
 
-#define MCFSDRAMC_DCR		(*(vu_short *)(CFG_MBAR+0x00000040))
-#define MCFSDRAMC_DACR0		(*(vu_long *) (CFG_MBAR+0x00000048))
-#define MCFSDRAMC_DMR0		(*(vu_long *) (CFG_MBAR+0x0000004c))
-#define MCFSDRAMC_DACR1		(*(vu_long *) (CFG_MBAR+0x00000050))
-#define MCFSDRAMC_DMR1		(*(vu_long *) (CFG_MBAR+0x00000054))
+#define MCFSDRAMC_DCR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00000040))
+#define MCFSDRAMC_DACR0		(*(vu_long *) (CONFIG_SYS_MBAR+0x00000048))
+#define MCFSDRAMC_DMR0		(*(vu_long *) (CONFIG_SYS_MBAR+0x0000004c))
+#define MCFSDRAMC_DACR1		(*(vu_long *) (CONFIG_SYS_MBAR+0x00000050))
+#define MCFSDRAMC_DMR1		(*(vu_long *) (CONFIG_SYS_MBAR+0x00000054))
 
 #define MCFSDRAMC_DCR_NAM	(0x2000)
 #define MCFSDRAMC_DCR_COC	(0x1000)
@@ -435,83 +435,60 @@
 #define MCFSDRAMC_DMR_UD	(0x00000002)
 #define MCFSDRAMC_DMR_V		(0x00000001)
 
-#define MCFWTM_WCR		(*(vu_short *)(CFG_MBAR+0x00140000))
-#define MCFWTM_WMR		(*(vu_short *)(CFG_MBAR+0x00140002))
-#define MCFWTM_WCNTR		(*(vu_short *)(CFG_MBAR+0x00140004))
-#define MCFWTM_WSR		(*(vu_short *)(CFG_MBAR+0x00140006))
-
-/*  Chip SELECT Module CSM */
-#define MCFCSM_CSAR0		(*(vu_short *)(CFG_MBAR+0x00000080))
-#define MCFCSM_CSMR0		(*(vu_long *) (CFG_MBAR+0x00000084))
-#define MCFCSM_CSCR0		(*(vu_short *)(CFG_MBAR+0x0000008a))
-#define MCFCSM_CSAR1		(*(vu_short *)(CFG_MBAR+0x0000008C))
-#define MCFCSM_CSMR1		(*(vu_long *) (CFG_MBAR+0x00000090))
-#define MCFCSM_CSCR1		(*(vu_short *)(CFG_MBAR+0x00000096))
-#define MCFCSM_CSAR2		(*(vu_short *)(CFG_MBAR+0x00000098))
-#define MCFCSM_CSMR2		(*(vu_long *) (CFG_MBAR+0x0000009C))
-#define MCFCSM_CSCR2		(*(vu_short *)(CFG_MBAR+0x000000A2))
-#define MCFCSM_CSAR3		(*(vu_short *)(CFG_MBAR+0x000000A4))
-#define MCFCSM_CSMR3		(*(vu_long *) (CFG_MBAR+0x000000A8))
-#define MCFCSM_CSCR3		(*(vu_short *)(CFG_MBAR+0x000000AE))
-
-#define MCFCSM_CSMR_BAM(x)	((x) & 0xFFFF0000)
-#define MCFCSM_CSMR_WP		(1<<8)
-#define MCFCSM_CSMR_V		(0x01)
-#define MCFCSM_CSCR_WS(x)	((x & 0x0F)<<10)
-#define MCFCSM_CSCR_AA		(0x0100)
-#define MCFCSM_CSCR_PS_32	(0x0000)
-#define MCFCSM_CSCR_PS_8	(0x0040)
-#define MCFCSM_CSCR_PS_16	(0x0080)
+#define MCFWTM_WCR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00140000))
+#define MCFWTM_WMR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00140002))
+#define MCFWTM_WCNTR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00140004))
+#define MCFWTM_WSR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00140006))
 
 /*********************************************************************
 * General Purpose Timer (GPT) Module
 *********************************************************************/
 
-#define MCFGPTA_GPTIOS		(*(vu_char *)(CFG_MBAR+0x1A0000))
-#define MCFGPTA_GPTCFORC	(*(vu_char *)(CFG_MBAR+0x1A0001))
-#define MCFGPTA_GPTOC3M		(*(vu_char *)(CFG_MBAR+0x1A0002))
-#define MCFGPTA_GPTOC3D		(*(vu_char *)(CFG_MBAR+0x1A0003))
-#define MCFGPTA_GPTCNT		(*(vu_short *)(CFG_MBAR+0x1A0004))
-#define MCFGPTA_GPTSCR1		(*(vu_char *)(CFG_MBAR+0x1A0006))
-#define MCFGPTA_GPTTOV		(*(vu_char *)(CFG_MBAR+0x1A0008))
-#define MCFGPTA_GPTCTL1		(*(vu_char *)(CFG_MBAR+0x1A0009))
-#define MCFGPTA_GPTCTL2		(*(vu_char *)(CFG_MBAR+0x1A000B))
-#define MCFGPTA_GPTIE		(*(vu_char *)(CFG_MBAR+0x1A000C))
-#define MCFGPTA_GPTSCR2		(*(vu_char *)(CFG_MBAR+0x1A000D))
-#define MCFGPTA_GPTFLG1		(*(vu_char *)(CFG_MBAR+0x1A000E))
-#define MCFGPTA_GPTFLG2		(*(vu_char *)(CFG_MBAR+0x1A000F))
-#define MCFGPTA_GPTC0		(*(vu_short *)(CFG_MBAR+0x1A0010))
-#define MCFGPTA_GPTC1		(*(vu_short *)(CFG_MBAR+0x1A0012))
-#define MCFGPTA_GPTC2		(*(vu_short *)(CFG_MBAR+0x1A0014))
-#define MCFGPTA_GPTC3		(*(vu_short *)(CFG_MBAR+0x1A0016))
-#define MCFGPTA_GPTPACTL	(*(vu_char *)(CFG_MBAR+0x1A0018))
-#define MCFGPTA_GPTPAFLG	(*(vu_char *)(CFG_MBAR+0x1A0019))
-#define MCFGPTA_GPTPACNT	(*(vu_short *)(CFG_MBAR+0x1A001A))
-#define MCFGPTA_GPTPORT		(*(vu_char *)(CFG_MBAR+0x1A001D))
-#define MCFGPTA_GPTDDR		(*(vu_char *)(CFG_MBAR+0x1A001E))
-
-#define MCFGPTB_GPTIOS		(*(vu_char *)(CFG_MBAR+0x1B0000))
-#define MCFGPTB_GPTCFORC	(*(vu_char *)(CFG_MBAR+0x1B0001))
-#define MCFGPTB_GPTOC3M		(*(vu_char *)(CFG_MBAR+0x1B0002))
-#define MCFGPTB_GPTOC3D		(*(vu_char *)(CFG_MBAR+0x1B0003))
-#define MCFGPTB_GPTCNT		(*(vu_short *)(CFG_MBAR+0x1B0004))
-#define MCFGPTB_GPTSCR1		(*(vu_char *)(CFG_MBAR+0x1B0006))
-#define MCFGPTB_GPTTOV		(*(vu_char *)(CFG_MBAR+0x1B0008))
-#define MCFGPTB_GPTCTL1		(*(vu_char *)(CFG_MBAR+0x1B0009))
-#define MCFGPTB_GPTCTL2		(*(vu_char *)(CFG_MBAR+0x1B000B))
-#define MCFGPTB_GPTIE		(*(vu_char *)(CFG_MBAR+0x1B000C))
-#define MCFGPTB_GPTSCR2		(*(vu_char *)(CFG_MBAR+0x1B000D))
-#define MCFGPTB_GPTFLG1		(*(vu_char *)(CFG_MBAR+0x1B000E))
-#define MCFGPTB_GPTFLG2		(*(vu_char *)(CFG_MBAR+0x1B000F))
-#define MCFGPTB_GPTC0		(*(vu_short *)(CFG_MBAR+0x1B0010))
-#define MCFGPTB_GPTC1		(*(vu_short *)(CFG_MBAR+0x1B0012))
-#define MCFGPTB_GPTC2		(*(vu_short *)(CFG_MBAR+0x1B0014))
-#define MCFGPTB_GPTC3		(*(vu_short *)(CFG_MBAR+0x1B0016))
-#define MCFGPTB_GPTPACTL	(*(vu_char *)(CFG_MBAR+0x1B0018))
-#define MCFGPTB_GPTPAFLG	(*(vu_char *)(CFG_MBAR+0x1B0019))
-#define MCFGPTB_GPTPACNT	(*(vu_short *)(CFG_MBAR+0x1B001A))
-#define MCFGPTB_GPTPORT		(*(vu_char *)(CFG_MBAR+0x1B001D))
-#define MCFGPTB_GPTDDR		(*(vu_char *)(CFG_MBAR+0x1B001E))
+#define MCFGPTA_GPTIOS		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0000))
+#define MCFGPTA_GPTCFORC	(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0001))
+#define MCFGPTA_GPTOC3M		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0002))
+#define MCFGPTA_GPTOC3D		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0003))
+#define MCFGPTA_GPTCNT		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0004))
+#define MCFGPTA_GPTSCR1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0006))
+#define MCFGPTA_GPTTOV		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0008))
+#define MCFGPTA_GPTCTL1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0009))
+#define MCFGPTA_GPTCTL2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000B))
+#define MCFGPTA_GPTIE		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000C))
+#define MCFGPTA_GPTSCR2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000D))
+#define MCFGPTA_GPTFLG1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000E))
+#define MCFGPTA_GPTFLG2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000F))
+#define MCFGPTA_GPTC0		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0010))
+#define MCFGPTA_GPTC1		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0012))
+#define MCFGPTA_GPTC2		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0014))
+#define MCFGPTA_GPTC3		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0016))
+#define MCFGPTA_GPTPACTL	(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0018))
+#define MCFGPTA_GPTPAFLG	(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0019))
+#define MCFGPTA_GPTPACNT	(*(vu_short *)(CONFIG_SYS_MBAR+0x1A001A))
+#define MCFGPTA_GPTPORT		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A001D))
+#define MCFGPTA_GPTDDR		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A001E))
+
+#define MCFGPTB_GPTIOS		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0000))
+#define MCFGPTB_GPTCFORC	(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0001))
+#define MCFGPTB_GPTOC3M		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0002))
+#define MCFGPTB_GPTOC3D		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0003))
+#define MCFGPTB_GPTCNT		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0004))
+#define MCFGPTB_GPTSCR1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0006))
+#define MCFGPTB_GPTTOV		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0008))
+#define MCFGPTB_GPTCTL1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0009))
+#define MCFGPTB_GPTCTL2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000B))
+#define MCFGPTB_GPTIE		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000C))
+#define MCFGPTB_GPTSCR2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000D))
+#define MCFGPTB_GPTFLG1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000E))
+#define MCFGPTB_GPTFLG2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000F))
+#define MCFGPTB_GPTC0		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0010))
+#define MCFGPTB_GPTC1		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0012))
+#define MCFGPTB_GPTC2		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0014))
+#define MCFGPTB_GPTC3		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0016))
+#define MCFGPTB_GPTPACTL	(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0018))
+#define MCFGPTB_GPTPAFLG	(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0019))
+#define MCFGPTB_GPTPACNT	(*(vu_short *)(CONFIG_SYS_MBAR+0x1B001A))
+#define MCFGPTB_GPTPORT		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B001D))
+#define MCFGPTB_GPTDDR		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B001E))
 
 /* Bit level definitions and macros */
 #define MCFGPT_GPTIOS_IOS3		(0x08)
@@ -596,7 +573,7 @@
 
 /* Coldfire Flash Module CFM */
 
-#define MCFCFM_MCR			(*(vu_short *)(CFG_MBAR+0x1D0000))
+#define MCFCFM_MCR			(*(vu_short *)(CONFIG_SYS_MBAR+0x1D0000))
 #define MCFCFM_MCR_LOCK			(0x0400)
 #define MCFCFM_MCR_PVIE			(0x0200)
 #define MCFCFM_MCR_AEIE			(0x0100)
@@ -604,23 +581,23 @@
 #define MCFCFM_MCR_CCIE			(0x0040)
 #define MCFCFM_MCR_KEYACC		(0x0020)
 
-#define MCFCFM_CLKD			(*(vu_char *)(CFG_MBAR+0x1D0002))
+#define MCFCFM_CLKD			(*(vu_char *)(CONFIG_SYS_MBAR+0x1D0002))
 
-#define MCFCFM_SEC			(*(vu_long*) (CFG_MBAR+0x1D0008))
+#define MCFCFM_SEC			(*(vu_long*) (CONFIG_SYS_MBAR+0x1D0008))
 #define MCFCFM_SEC_KEYEN		(0x80000000)
 #define MCFCFM_SEC_SECSTAT		(0x40000000)
 
-#define MCFCFM_PROT			(*(vu_long*) (CFG_MBAR+0x1D0010))
-#define MCFCFM_SACC			(*(vu_long*) (CFG_MBAR+0x1D0014))
-#define MCFCFM_DACC			(*(vu_long*) (CFG_MBAR+0x1D0018))
-#define MCFCFM_USTAT			(*(vu_char*) (CFG_MBAR+0x1D0020))
+#define MCFCFM_PROT			(*(vu_long*) (CONFIG_SYS_MBAR+0x1D0010))
+#define MCFCFM_SACC			(*(vu_long*) (CONFIG_SYS_MBAR+0x1D0014))
+#define MCFCFM_DACC			(*(vu_long*) (CONFIG_SYS_MBAR+0x1D0018))
+#define MCFCFM_USTAT			(*(vu_char*) (CONFIG_SYS_MBAR+0x1D0020))
 #define MCFCFM_USTAT_CBEIF		0x80
 #define MCFCFM_USTAT_CCIF		0x40
 #define MCFCFM_USTAT_PVIOL		0x20
 #define MCFCFM_USTAT_ACCERR		0x10
 #define MCFCFM_USTAT_BLANK		0x04
 
-#define MCFCFM_CMD			(*(vu_char*) (CFG_MBAR+0x1D0024))
+#define MCFCFM_CMD			(*(vu_char*) (CONFIG_SYS_MBAR+0x1D0024))
 #define MCFCFM_CMD_ERSVER		0x05
 #define MCFCFM_CMD_PGERSVER		0x06
 #define MCFCFM_CMD_PGM			0x20
diff --git a/include/asm-m68k/m5301x.h b/include/asm-m68k/m5301x.h
new file mode 100644
index 0000000..52bbb87
--- /dev/null
+++ b/include/asm-m68k/m5301x.h
@@ -0,0 +1,604 @@
+/*
+ * m5301x.h -- Definitions for Freescale Coldfire 5301x
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef m5301x_h
+#define m5301x_h
+
+/* *** System Control Module (SCM) *** */
+#define SCM_MPR_MPROT0(x)		(((x) & 0x0F) << 28)
+#define SCM_MPR_MPROT1(x)		(((x) & 0x0F) << 24)
+#define SCM_MPR_MPROT2(x)		(((x) & 0x0F) << 20)
+#define SCM_MPR_MPROT4(x)		(((x) & 0x0F) << 12)
+#define SCM_MPR_MPROT5(x)		(((x) & 0x0F) << 8)
+#define SCM_MPR_MPROT6(x)		(((x) & 0x0F) << 4)
+#define MPROT_MTR			4
+#define MPROT_MTW			2
+#define MPROT_MPL			1
+
+#define SCM_PACRA_PACR0(x)		(((x) & 0x0F) << 28)
+#define SCM_PACRA_PACR1(x)		(((x) & 0x0F) << 24)
+#define SCM_PACRA_PACR2(x)		(((x) & 0x0F) << 20)
+#define SCM_PACRA_PACR5(x)		(((x) & 0x0F) << 8)
+
+#define SCM_PACRB_PACR12(x)		(((x) & 0x0F) << 12)
+#define SCM_PACRB_PACR13(x)		(((x) & 0x0F) << 8)
+
+#define SCM_PACRC_PACR16(x)		(((x) & 0x0F) << 28)
+#define SCM_PACRC_PACR17(x)		(((x) & 0x0F) << 24)
+#define SCM_PACRC_PACR18(x)		(((x) & 0x0F) << 20)
+#define SCM_PACRC_PACR19(x)		(((x) & 0x0F) << 16)
+#define SCM_PACRC_PACR21(x)		(((x) & 0x0F) << 8)
+#define SCM_PACRC_PACR22(x)		(((x) & 0x0F) << 4)
+#define SCM_PACRC_PACR23(x)		((x) & 0x0F)
+
+#define SCM_PACRD_PACR24(x)		(((x) & 0x0F) << 28)
+#define SCM_PACRD_PACR25(x)		(((x) & 0x0F) << 24)
+#define SCM_PACRD_PACR26(x)		(((x) & 0x0F) << 20)
+#define SCM_PACRD_PACR28(x)		(((x) & 0x0F) << 12)
+#define SCM_PACRD_PACR29(x)		(((x) & 0x0F) << 8)
+#define SCM_PACRD_PACR30(x)		(((x) & 0x0F) << 4)
+#define SCM_PACRD_PACR31(x)		((x) & 0x0F)
+
+#define SCM_PACRE_PACR32(x)		(((x) & 0x0F) << 28)
+#define SCM_PACRE_PACR33(x)		(((x) & 0x0F) << 24)
+#define SCM_PACRE_PACR34(x)		(((x) & 0x0F) << 20)
+#define SCM_PACRE_PACR35(x)		(((x) & 0x0F) << 16)
+#define SCM_PACRE_PACR36(x)		(((x) & 0x0F) << 12)
+#define SCM_PACRE_PACR37(x)		(((x) & 0x0F) << 8)
+#define SCM_PACRE_PACR39(x)		((x) & 0x0F)
+
+#define SCM_PACRF_PACR40(x)		(((x) & 0x0F) << 28)
+#define SCM_PACRF_PACR41(x)		(((x) & 0x0F) << 24)
+#define SCM_PACRF_PACR42(x)		(((x) & 0x0F) << 20)
+#define SCM_PACRF_PACR43(x)		(((x) & 0x0F) << 16)
+#define SCM_PACRF_PACR44(x)		(((x) & 0x0F) << 12)
+#define SCM_PACRF_PACR45(x)		(((x) & 0x0F) << 8)
+#define SCM_PACRF_PACR46(x)		(((x) & 0x0F) << 4)
+#define SCM_PACRF_PACR47(x)		((x) & 0x0F)
+
+#define SCM_PACRG_PACR48(x)		(((x) & 0x0F) << 28)
+#define SCM_PACRG_PACR49(x)		(((x) & 0x0F) << 24)
+#define SCM_PACRG_PACR50(x)		(((x) & 0x0F) << 20)
+#define SCM_PACRG_PACR51(x)		(((x) & 0x0F) << 16)
+
+#define PACR_SP	4
+#define PACR_WP	2
+#define PACR_TP	1
+
+#define SCM_CWCR_RO			(0x8000)
+#define SCM_CWCR_CWR_WH			(0x0100)
+#define SCM_CWCR_CWE			(0x0080)
+#define SCM_CWCR_CWRI_WINDOW		(0x0060)
+#define SCM_CWCR_CWRI_RESET		(0x0040)
+#define SCM_CWCR_CWRI_INT_RESET		(0x0020)
+#define SCM_CWCR_CWRI_INT		(0x0000)
+#define SCM_CWCR_CWT(x)			(((x) & 0x001F))
+
+#define SCM_ISR_CFEI			(0x02)
+#define SCM_ISR_CWIC			(0x01)
+
+#define BCR_GBR				(0x00000200)
+#define BCR_GBW				(0x00000100)
+#define BCR_S7				(0x00000080)
+#define BCR_S6				(0x00000040)
+#define BCR_S4				(0x00000010)
+#define BCR_S1				(0x00000002)
+
+#define SCM_CFIER_ECFEI			(0x01)
+
+#define SCM_CFLOC_LOC			(0x80)
+
+#define SCM_CFATR_WRITE			(0x80)
+#define SCM_CFATR_SZ32			(0x20)
+#define SCM_CFATR_SZ16			(0x10)
+#define SCM_CFATR_SZ08			(0x00)
+#define SCM_CFATR_CACHE			(0x08)
+#define SCM_CFATR_MODE			(0x02)
+#define SCM_CFATR_TYPE			(0x01)
+
+/* *** Interrupt Controller (INTC) *** */
+#define INT0_LO_RSVD0			(0)
+#define INT0_LO_EPORT1			(1)
+#define INT0_LO_EPORT2			(2)
+#define INT0_LO_EPORT3			(3)
+#define INT0_LO_EPORT4			(4)
+#define INT0_LO_EPORT5			(5)
+#define INT0_LO_EPORT6			(6)
+#define INT0_LO_EPORT7			(7)
+#define INT0_LO_EDMA_00			(8)
+#define INT0_LO_EDMA_01			(9)
+#define INT0_LO_EDMA_02			(10)
+#define INT0_LO_EDMA_03			(11)
+#define INT0_LO_EDMA_04			(12)
+#define INT0_LO_EDMA_05			(13)
+#define INT0_LO_EDMA_06			(14)
+#define INT0_LO_EDMA_07			(15)
+#define INT0_LO_EDMA_08			(16)
+#define INT0_LO_EDMA_09			(17)
+#define INT0_LO_EDMA_10			(18)
+#define INT0_LO_EDMA_11			(19)
+#define INT0_LO_EDMA_12			(20)
+#define INT0_LO_EDMA_13			(21)
+#define INT0_LO_EDMA_14			(22)
+#define INT0_LO_EDMA_15			(23)
+#define INT0_LO_EDMA_ERR		(24)
+#define INT0_LO_SCM_CWIC		(25)
+#define INT0_LO_UART0			(26)
+#define INT0_LO_UART1			(27)
+#define INT0_LO_UART2			(28)
+#define INT0_LO_RSVD1			(29)
+#define INT0_LO_I2C			(30)
+#define INT0_LO_DSPI			(31)
+#define INT0_HI_DTMR0			(32)
+#define INT0_HI_DTMR1			(33)
+#define INT0_HI_DTMR2			(34)
+#define INT0_HI_DTMR3			(35)
+#define INT0_HI_FEC0_TXF		(36)
+#define INT0_HI_FEC0_TXB		(37)
+#define INT0_HI_FEC0_UN			(38)
+#define INT0_HI_FEC0_RL			(39)
+#define INT0_HI_FEC0_RXF		(40)
+#define INT0_HI_FEC0_RXB		(41)
+#define INT0_HI_FEC0_MII		(42)
+#define INT0_HI_FEC0_LC			(43)
+#define INT0_HI_FEC0_HBERR		(44)
+#define INT0_HI_FEC0_GRA		(45)
+#define INT0_HI_FEC0_EBERR		(46)
+#define INT0_HI_FEC0_BABT		(47)
+#define INT0_HI_FEC0_BABR		(48)
+#define INT0_HI_FEC1_TXF		(49)
+#define INT0_HI_FEC1_TXB		(50)
+#define INT0_HI_FEC1_UN			(51)
+#define INT0_HI_FEC1_RL			(52)
+#define INT0_HI_FEC1_RXF		(53)
+#define INT0_HI_FEC1_RXB		(54)
+#define INT0_HI_FEC1_MII		(55)
+#define INT0_HI_FEC1_LC			(56)
+#define INT0_HI_FEC1_HBERR		(57)
+#define INT0_HI_FEC1_GRA		(58)
+#define INT0_HI_FEC1_EBERR		(59)
+#define INT0_HI_FEC1_BABT		(60)
+#define INT0_HI_FEC1_BABR		(61)
+#define INT0_HI_SCM_CFEI		(62)
+
+/* 0 - 24 reserved */
+#define INT1_LO_EPORT1_FLAG0		(25)
+#define INT1_LO_EPORT1_FLAG1		(26)
+#define INT1_LO_EPORT1_FLAG2		(27)
+#define INT1_LO_EPORT1_FLAG3		(28)
+#define INT1_LO_EPORT1_FLAG4		(29)
+#define INT1_LO_EPORT1_FLAG5		(30)
+#define INT1_LO_EPORT1_FLAG6		(31)
+#define INT1_LO_EPORT1_FLAG7		(32)
+#define INT1_HI_DSPI_EOQF		(33)
+#define INT1_HI_DSPI_TFFF		(34)
+#define INT1_HI_DSPI_TCF		(35)
+#define INT1_HI_DSPI_TFUF		(36)
+#define INT1_HI_DSPI_RFDF		(37)
+#define INT1_HI_DSPI_RFOF		(38)
+#define INT1_HI_DSPI_RFOF_TFUF		(39)
+#define INT1_HI_RNG_EI			(40)
+#define INT1_HI_PLL_LOCF		(41)
+#define INT1_HI_PLL_LOLF		(42)
+#define INT1_HI_PIT0			(43)
+#define INT1_HI_PIT1			(44)
+#define INT1_HI_PIT2			(45)
+#define INT1_HI_PIT3			(46)
+#define INT1_HI_USBOTG_STS		(47)
+#define INT1_HI_USBHOST_STS		(48)
+#define INT1_HI_SSI			(49)
+/* 50 - 51 reserved */
+#define INT1_HI_RTC			(52)
+#define INT1_HI_CCM_USBSTAT		(53)
+#define INT1_HI_CODEC_OR		(54)
+#define INT1_HI_CODEC_RF_TE		(55)
+#define INT1_HI_CODEC_ROE		(56)
+#define INT1_HI_CODEC_TUE		(57)
+/* 58 reserved */
+#define INT1_HI_SIM1_DATA		(59)
+#define INT1_HI_SIM1_GENERAL		(60)
+/* 61 - 62 reserved */
+#define INT1_HI_SDHC			(63)
+
+/* *** Reset Controller Module (RCM) *** */
+#define RCM_RCR_SOFTRST			(0x80)
+#define RCM_RCR_FRCRSTOUT		(0x40)
+
+#define RCM_RSR_SOFT			(0x20)
+#define RCM_RSR_LOC			(0x10)
+#define RCM_RSR_POR			(0x08)
+#define RCM_RSR_EXT			(0x04)
+#define RCM_RSR_WDR_CORE		(0x02)
+#define RCM_RSR_LOL			(0x01)
+
+/* *** Chip Configuration Module (CCM) *** */
+#define CCM_CCR_CSC			(0x0020)
+#define CCM_CCR_BOOTPS			(0x0010)
+#define CCM_CCR_LOAD			(0x0008)
+#define CCM_CCR_OSC_MODE		(0x0004)
+#define CCM_CCR_SDR_MODE		(0x0002)
+#define CCM_CCR_RESERVED		(0x0001)
+
+#define CCM_RCON_SDR_32BIT_UNIFIED	(0x0012)
+#define CCM_RCON_DDR_8BIT_SPLIT		(0x0010)
+#define CCM_RCON_SDR_16BIT_UNIFIED	(0x0002)
+#define CCM_RCON_DDR_16BIT_SPLIT	(0x0000)
+
+#define CCM_CIR_PIN(x)			(((x) & 0x03FF) << 6)
+#define CCM_CIR_PRN(x)			((x) & 0x003F)
+
+#define CCM_MISCCR_FECM			(0x8000)
+#define CCM_MISCCR_CDCSRC		(0x4000)
+#define CCM_MISCCR_PLL_LOCK		(0x2000)
+#define CCM_MISCCR_LIMP			(0x1000)
+#define CCM_MISCCR_BME			(0x8000)
+#define CCM_MISCCR_BMT_MASK		(0xF8FF)
+#define CCM_MISCCR_BMT(x)		(((x) & 0x0007) << 8)
+#define CCM_MISCCR_BMT_512		(0x0700)
+#define CCM_MISCCR_BMT_1024		(0x0600)
+#define CCM_MISCCR_BMT_2048		(0x0500)
+#define CCM_MISCCR_BMT_4096		(0x0400)
+#define CCM_MISCCR_BMT_8192		(0x0300)
+#define CCM_MISCCR_BMT_16384		(0x0200)
+#define CCM_MISCCR_BMT_32768		(0x0100)
+#define CCM_MISCCR_BMT_65536		(0x0000)
+#define CCM_MISCCR_TIM_DMA		(0x0020)
+#define CCM_MISCCR_SSI_SRC		(0x0010)
+#define CCM_MISCCR_USBH_OC		(0x0008)
+#define CCM_MISCCR_USBO_OC		(0x0004)
+#define CCM_MISCCR_USB_PUE		(0x0002)
+#define CCM_MISCCR_USB_SRC		(0x0001)
+
+#define CCM_CDR_LPDIV(x)		(((x) & 0x0F) << 8)
+#define CCM_CDR_SSIDIV(x)		((x) & 0xFF)
+
+#define CCM_UOCSR_DPPD			(0x2000)
+#define CCM_UOCSR_DMPD			(0x1000)
+#define CCM_UOCSR_DRV_VBUS		(0x0800)
+#define CCM_UOCSR_CRG_VBUS		(0x0400)
+#define CCM_UOCSR_DCR_VBUS		(0x0200)
+#define CCM_UOCSR_DPPU			(0x0100)
+#define CCM_UOCSR_AVLD			(0x0080)
+#define CCM_UOCSR_BVLD			(0x0040)
+#define CCM_UOCSR_VVLD			(0x0020)
+#define CCM_UOCSR_SEND			(0x0010)
+#define CCM_UOCSR_PWRFLT		(0x0008)
+#define CCM_UOCSR_WKUP			(0x0004)
+#define CCM_UOCSR_UOMIE			(0x0002)
+#define CCM_UOCSR_XPDE			(0x0001)
+
+#define CCM_UHCSR_PORTIND(x)		(((x) & 0x0003) << 14)
+#define CCM_UHCSR_DRV_VBUS		(0x0010)
+#define CCM_UHCSR_PWRFLT		(0x0008)
+#define CCM_UHCSR_WKUP			(0x0004)
+#define CCM_UHCSR_UHMIE			(0x0002)
+#define CCM_UHCSR_XPDE			(0x0001)
+
+#define CCM_CODCR_BGREN			(0x8000)
+#define CCM_CODCR_REGEN			(0x0080)
+
+#define CCM_MISC2_IGNLL			(0x0008)
+#define CCM_MISC2_DPS			(0x0001)
+
+/* *** General Purpose I/O (GPIO) *** */
+#define GPIO_PDR_FBCTL			((x) & 0x0F)
+#define GPIO_PDR_BE			((x) & 0x0F)
+#define GPIO_PDR_CS32			(((x) & 0x03) << 4)
+#define GPIO_PDR_CS10			(((x) & 0x03) << 4)
+#define GPIO_PDR_DSPI			((x) & 0x7F)
+#define GPIO_PDR_FEC0			((x) & 0x7F)
+#define GPIO_PDR_FECI2C			((x) & 0x3F)
+#define GPIO_PDR_SIMP1			((x) & 0x1F)
+#define GPIO_PDR_SIMP0			((x) & 0x1F)
+#define GPIO_PDR_TIMER			((x) & 0x0F)
+#define GPIO_PDR_UART			((x) & 0x3F)
+#define GPIO_PDR_DEBUG			(0x01)
+#define GPIO_PDR_SDHC			((x) & 0x3F)
+#define GPIO_PDR_SSI			((x) & 0x1F)
+
+#define GPIO_PAR_FBCTL_OE		(0x80)
+#define GPIO_PAR_FBCTL_TA		(0x40)
+#define GPIO_PAR_FBCTL_RWB		(0x20)
+#define GPIO_PAR_FBCTL_TS		(0x18)
+
+#define GPIO_PAR_BE3			(0x40)
+#define GPIO_PAR_BE2			(0x10)
+#define GPIO_PAR_BE1			(0x04)
+#define GPIO_PAR_BE0			(0x01)
+
+#define GPIO_PAR_CS5			(0x40)
+#define GPIO_PAR_CS4			(0x10)
+#define GPIO_PAR_CS1_MASK		(0xF3)
+#define GPIO_PAR_CS1_CS1		(0x0C)
+#define GPIO_PAR_CS1_SDCS1		(0x08)
+#define GPIO_PAR_CS0_MASK		(0xFC)
+#define GPIO_PAR_CS0_CS0		(0x03)
+#define GPIO_PAR_CS0_CS4		(0x02)
+
+#define GPIO_PAR_DSPIH_SIN_MASK		(0x3F)
+#define GPIO_PAR_DSPIH_SIN		(0xC0)
+#define GPIO_PAR_DSPIH_SIN_U2RXD	(0x80)
+#define GPIO_PAR_DSPIH_SOUT_MASK	(0xCF)
+#define GPIO_PAR_DSPIH_SOUT		(0x30)
+#define GPIO_PAR_DSPIH_SOUT_U2TXD	(0x20)
+#define GPIO_PAR_DSPIH_SCK_MASK		(0xF3)
+#define GPIO_PAR_DSPIH_SCK		(0x0C)
+#define GPIO_PAR_DSPIH_SCK_U2CTS	(0x08)
+#define GPIO_PAR_DSPIH_PCS0_MASK	(0xFC)
+#define GPIO_PAR_DSPIH_PCS0		(0x03)
+#define GPIO_PAR_DSPIH_PCS0_U2RTS	(0x02)
+
+#define GPIO_PAR_DSPIL_PCS1_MASK	(0x3F)
+#define GPIO_PAR_DSPIL_PCS1		(0xC0)
+#define GPIO_PAR_DSPIL_PCS2_MASK	(0xCF)
+#define GPIO_PAR_DSPIL_PCS2		(0x30)
+#define GPIO_PAR_DSPIL_PCS2_USBH_OC	(0x20)
+#define GPIO_PAR_DSPIL_PCS3_MASK	(0xF3)
+#define GPIO_PAR_DSPIL_PCS3		(0x0C)
+#define GPIO_PAR_DSPIL_PCS3_USBH_EN	(0x08)
+
+#define GPIO_PAR_FEC1_7W_FEC		(0x40)
+#define GPIO_PAR_FEC1_RMII_FEC		(0x10)
+#define GPIO_PAR_FEC0_7W_FEC		(0x04)
+#define GPIO_PAR_FEC0_RMII_FEC		(0x01)
+
+/* GPIO_PAR_FECI2C */
+#define GPIO_PAR_FECI2C_RMII0_MASK	(0x3F)
+#define GPIO_PAR_FECI2C_MDC0		(0x80)
+#define GPIO_PAR_FECI2C_MDIO0		(0x40)
+#define GPIO_PAR_FECI2C_RMII1_MASK	(0xCF)
+#define GPIO_PAR_FECI2C_MDC1		(0x20)
+#define GPIO_PAR_FECI2C_MDIO1		(0x10)
+#define GPIO_PAR_FECI2C_SDA_MASK	(0xF3)
+#define GPIO_PAR_FECI2C_SDA(x)		(((x) & 0x03) << 2)
+#define GPIO_PAR_FECI2C_SDA_SDA		(0x0C)
+#define GPIO_PAR_FECI2C_SDA_U2TXD	(0x08)
+#define GPIO_PAR_FECI2C_SDA_MDIO1	(0x04)
+#define GPIO_PAR_FECI2C_SCL_MASK	(0xFC)
+#define GPIO_PAR_FECI2C_SCL(x)		((x) & 0x03)
+#define GPIO_PAR_FECI2C_SCL_SCL		(0x03)
+#define GPIO_PAR_FECI2C_SCL_U2RXD	(0x02)
+#define GPIO_PAR_FECI2C_SCL_MDC1	(0x01)
+
+#define GPIO_PAR_IRQ0H_IRQ07_MASK	(0x3F)
+#define GPIO_PAR_IRQ0H_IRQ06_MASK	(0xCF)
+#define GPIO_PAR_IRQ0H_IRQ06_USBCLKIN	(0x10)
+#define GPIO_PAR_IRQ0H_IRQ04_MASK	(0xFC)
+#define GPIO_PAR_IRQ0H_IRQ04_DREQ0	(0x02)
+
+#define GPIO_PAR_IRQ0L_IRQ01_MASK	(0xF3)
+#define GPIO_PAR_IRQ0L_IRQ01_DREQ1	(0x08)
+
+#define GPIO_PAR_IRQ1H_IRQ17_DDATA3	(0x40)
+#define GPIO_PAR_IRQ1H_IRQ16_DDATA2	(0x10)
+#define GPIO_PAR_IRQ1H_IRQ15_DDATA1	(0x04)
+#define GPIO_PAR_IRQ1H_IRQ14_DDATA0	(0x01)
+
+#define GPIO_PAR_IRQ1L_IRQ13_PST3	(0x40)
+#define GPIO_PAR_IRQ1L_IRQ12_PST2	(0x10)
+#define GPIO_PAR_IRQ1L_IRQ11_PST1	(0x04)
+#define GPIO_PAR_IRQ1L_IRQ10_PST0	(0x01)
+
+#define GPIO_PAR_SIMP1H_DATA1_MASK	(0x3F)
+#define GPIO_PAR_SIMP1H_DATA1_SIMDATA1	(0xC0)
+#define GPIO_PAR_SIMP1H_DATA1_SSITXD	(0x80)
+#define GPIO_PAR_SIMP1H_DATA1_U1TXD	(0x40)
+#define GPIO_PAR_SIMP1H_VEN1_MASK	(0xCF)
+#define GPIO_PAR_SIMP1H_VEN1_SIMVEN1	(0x30)
+#define GPIO_PAR_SIMP1H_VEN1_SSIRXD	(0x20)
+#define GPIO_PAR_SIMP1H_VEN1_U1RXD	(0x10)
+#define GPIO_PAR_SIMP1H_RST1_MASK	(0xF3)
+#define GPIO_PAR_SIMP1H_RST1_SIMRST1	(0x0C)
+#define GPIO_PAR_SIMP1H_RST1_SSIFS	(0x08)
+#define GPIO_PAR_SIMP1H_RST1_U1RTS	(0x04)
+#define GPIO_PAR_SIMP1H_PD1_MASK	(0xFC)
+#define GPIO_PAR_SIMP1H_PD1_SIMPD1	(0x03)
+#define GPIO_PAR_SIMP1H_PD1_SSIBCLK	(0x02)
+#define GPIO_PAR_SIMP1H_PD1_U1CTS	(0x01)
+
+#define GPIO_PAR_SIMP1L_CLK_MASK	(0x3F)
+#define GPIO_PAR_SIMP1L_CLK_CLK1	(0xC0)
+#define GPIO_PAR_SIMP1L_CLK_SSIMCLK	(0x80)
+
+#define GPIO_PAR_SIMP0_DATA0		(0x10)
+#define GPIO_PAR_SIMP0_VEN0		(0x08)
+#define GPIO_PAR_SIMP0_RST0		(0x04)
+#define GPIO_PAR_SIMP0_PD0		(0x02)
+#define GPIO_PAR_SIMP0_CLK0		(0x01)
+
+#define GPIO_PAR_TIN3(x)		(((x) & 0x03) << 6)
+#define GPIO_PAR_TIN2(x)		(((x) & 0x03) << 4)
+#define GPIO_PAR_TIN1(x)		(((x) & 0x03) << 2)
+#define GPIO_PAR_TIN0(x)		((x) & 0x03)
+#define GPIO_PAR_TIN3_MASK		(0x3F)
+#define GPIO_PAR_TIN3_TIN3		(0xC0)
+#define GPIO_PAR_TIN3_TOUT3		(0x80)
+#define GPIO_PAR_TIN3_IRQ03		(0x40)
+#define GPIO_PAR_TIN2_MASK		(0xCF)
+#define GPIO_PAR_TIN2_TIN2		(0x30)
+#define GPIO_PAR_TIN2_TOUT2		(0x20)
+#define GPIO_PAR_TIN2_IRQ02		(0x10)
+#define GPIO_PAR_TIN1_MASK		(0xF3)
+#define GPIO_PAR_TIN1_TIN1		(0x0C)
+#define GPIO_PAR_TIN1_TOUT1		(0x08)
+#define GPIO_PAR_TIN1_DACK1		(0x04)
+#define GPIO_PAR_TIN0_MASK		(0xFC)
+#define GPIO_PAR_TIN0_TIN0		(0x03)
+#define GPIO_PAR_TIN0_TOUT0		(0x02)
+#define GPIO_PAR_TIN0_CODEC_ALTCLK	(0x01)
+
+#define GPIO_PAR_UART_U2TXD		(0x80)
+#define GPIO_PAR_UART_U2RXD		(0x40)
+#define GPIO_PAR_UART_U0TXD		(0x20)
+#define GPIO_PAR_UART_U0RXD		(0x10)
+#define GPIO_PAR_UART_RTS0(x)		(((x) & 0x03) << 2)
+#define GPIO_PAR_UART_CTS0(x)		((x) & 0x03)
+#define GPIO_PAR_UART_RTS0_MASK		(0xF3)
+#define GPIO_PAR_UART_RTS0_U0RTS	(0x0C)
+#define GPIO_PAR_UART_RTS0_USBO_VBOC	(0x08)
+#define GPIO_PAR_UART_CTS0_MASK		(0xFC)
+#define GPIO_PAR_UART_CTS0_U0CTS	(0x03)
+#define GPIO_PAR_UART_CTS0_USB0_VBEN	(0x02)
+#define GPIO_PAR_UART_CTS0_USB_PULLUP	(0x01)
+
+#define GPIO_PAR_DEBUG_ALLPST		(0x80)
+
+#define GPIO_PAR_SDHC_DATA3		(0x20)
+#define GPIO_PAR_SDHC_DATA2		(0x10)
+#define GPIO_PAR_SDHC_DATA1		(0x08)
+#define GPIO_PAR_SDHC_DATA0		(0x04)
+#define GPIO_PAR_SDHC_CMD		(0x02)
+#define GPIO_PAR_SDHC_CLK		(0x01)
+
+#define GPIO_PAR_SSIH_RXD(x)		(((x) & 0x03) << 6)
+#define GPIO_PAR_SSIH_TXD(x)		(((x) & 0x03) << 4)
+#define GPIO_PAR_SSIH_FS(x)		(((x) & 0x03) << 2)
+#define GPIO_PAR_SSIH_MCLK(x)		((x) & 0x03)
+#define GPIO_PAR_SSIH_RXD_MASK		(0x3F)
+#define GPIO_PAR_SSIH_RXD_SSIRXD	(0xC0)
+#define GPIO_PAR_SSIH_RXD_U1RXD		(0x40)
+#define GPIO_PAR_SSIH_TXD_MASK		(0xCF)
+#define GPIO_PAR_SSIH_TXD_SSIRXD	(0x30)
+#define GPIO_PAR_SSIH_TXD_U1TXD		(0x10)
+#define GPIO_PAR_SSIH_FS_MASK		(0xF3)
+#define GPIO_PAR_SSIH_FS_SSIFS		(0x0C)
+#define GPIO_PAR_SSIH_FS_U1RTS		(0x04)
+#define GPIO_PAR_SSIH_MCLK_MASK		(0xFC)
+#define GPIO_PAR_SSIH_MCLK_SSIMCLK	(0x03)
+#define GPIO_PAR_SSIH_MCLK_SSICLKIN	(0x01)
+
+#define GPIO_PAR_SSIL_MASK		(0x3F)
+#define GPIO_PAR_SSIL_BCLK		(0xC0)
+#define GPIO_PAR_SSIL_U1CTS		(0x40)
+
+#define GPIO_MSCR_MSCR1(x)		(((x) & 0x07) << 5)
+#define GPIO_MSCR_MSCR2(x)		(((x) & 0x07) << 5)
+#define GPIO_MSCR_MSCR3(x)		(((x) & 0x07) << 5)
+#define GPIO_MSCR_MSCR4(x)		(((x) & 0x07) << 5)
+#define GPIO_MSCR_MSCRn_MASK		(0x1F)
+#define GPIO_MSCR_MSCRn_SDR		(0xE0)
+#define GPIO_MSCR_MSCRn_25VDDR		(0x60)
+#define GPIO_MSCR_MSCRn_18VDDR_FULL	(0x20)
+#define GPIO_MSCR_MSCRn_18VDDR_HALF	(0x00)
+
+#define GPIO_MSCR_MSCR5(x)		(((x) & 0x07) << 2)
+#define GPIO_MSCR_MSCR5_MASK		(0xE3)
+#define GPIO_MSCR_MSCR5_SDR		(0x1C)
+#define GPIO_MSCR_MSCR5_25VDDR		(0x0C)
+#define GPIO_MSCR_MSCR5_18VDDR_FULL	(0x04)
+#define GPIO_MSCR_MSCR5_18VDDR_HALF	(0x00)
+
+#define GPIO_SRCR_DSPI_MASK		(0xFC)
+#define GPIO_SRCR_DSPI(x)		((x) & 0x03)
+#define GPIO_SRCR_I2C_MASK		(0xFC)
+#define GPIO_SRCR_I2C(x)		((x) & 0x03)
+#define GPIO_SRCR_IRQ_IRQ0_MASK		(0xF3)
+#define GPIO_SRCR_IRQ_IRQ0(x)		(((x) & 0x03) << 2)
+#define GPIO_SRCR_IRQ_IRQ1DBG_MASK	(0xFC)
+#define GPIO_SRCR_IRQ_IRQ1DBG(x)	((x) & 0x03)
+#define GPIO_SRCR_SIM_SIMP0_MASK	(0xF3)
+#define GPIO_SRCR_SIM_SIMP0(x)		(((x) & 0x03) << 2)
+#define GPIO_SRCR_SIM_SIMP1_MASK	(0xFC)
+#define GPIO_SRCR_SIM_SIMP1(x)		((x) & 0x03)
+#define GPIO_SRCR_TIMER_MASK		(0xFC)
+#define GPIO_SRCR_TIMER(x)		((x) & 0x03)
+#define GPIO_SRCR_UART2_MASK		(0xF3)
+#define GPIO_SRCR_UART2(x)		(((x) & 0x03) << 2)
+#define GPIO_SRCR_UART0_MASK		(0xFC)
+#define GPIO_SRCR_UART0(x)		((x) & 0x03)
+#define GPIO_SRCR_SDHC_MASK		(0xFC)
+#define GPIO_SRCR_SDHC(x)		((x) & 0x03)
+#define GPIO_SRCR_SSI_MASK		(0xFC)
+#define GPIO_SRCR_SSI(x)		((x) & 0x03)
+
+#define SRCR_HIGHEST			(0x03)
+#define SRCR_HIGH			(0x02)
+#define SRCR_LOW			(0x01)
+#define SRCR_LOWEST			(0x00)
+
+#define GPIO_DSCR_FEC_RMIICLK_MASK	(0xCF)
+#define GPIO_DSCR_FEC_RMIICLK(x)	(((x) & 0x03) << 4)
+#define GPIO_DSCR_FEC_RMII0_MASK	(0xF3)
+#define GPIO_DSCR_FEC_RMII0(x)		(((x) & 0x03) << 2)
+#define GPIO_DSCR_FEC_RMII1_MASK	(0xFC)
+#define GPIO_DSCR_FEC_RMII1(x)		((x) & 0x03)
+
+#define DSCR_50PF			(0x03)
+#define DSCR_30PF			(0x02)
+#define DSCR_20PF			(0x01)
+#define DSCR_10PF			(0x00)
+
+#define GPIO_PCRH_DSPI_PCS0_PULLUP_EN	(0x80)
+#define GPIO_PCRH_SIM_VEN1_PULLUP_EN	(0x40)
+#define GPIO_PCRH_SIM_VEN1_PULLUP	(0x20)
+#define GPIO_PCRH_SIM_DATA1_PULLUP_EN	(0x10)
+#define GPIO_PCRH_SIM_DATA1_PULLUP	(0x08)
+#define GPIO_PCRH_SSI_PULLUP_EN		(0x02)
+#define GPIO_PCRH_SSI_PULLUP		(0x01)
+
+#define GPIO_PCRL_SDHC_DATA3_PULLUP_EN	(0x80)
+#define GPIO_PCRL_SDHC_DATA3_PULLUP	(0x40)
+#define GPIO_PCRL_SDHC_DATA2_PULLUP_EN	(0x20)
+#define GPIO_PCRL_SDHC_DATA1_PULLUP_EN	(0x10)
+#define GPIO_PCRL_SDHC_DATA0_PULLUP_EN	(0x08)
+#define GPIO_PCRL_SDHC_CMD_PULLUP_EN	(0x04)
+
+/* *** Phase Locked Loop (PLL) *** */
+#define PLL_PCR_LOC_IRQ			(0x00040000)
+#define PLL_PCR_LOC_RE			(0x00020000)
+#define PLL_PCR_LOC_EN			(0x00010000)
+#define PLL_PCR_LOL_IRQ			(0x00004000)
+#define PLL_PCR_LOL_RE			(0x00002000)
+#define PLL_PCR_LOL_EN			(0x00001000)
+#define PLL_PCR_REFDIV_MASK		(0xFFFFF8FF)
+#define PLL_PCR_REFDIV(x)		(((x) & 0x07) << 8)
+#define PLL_PCR_FBDIV_MASK		(0xFFFFFFC0)
+#define PLL_PCR_FBDIV(x)		((x) & 0x3F)
+
+#define PLL_PDR_OUTDIV4_MASK		(0x0FFF)
+#define PLL_PDR_OUTDIV4(x)		(((x) & 0x0000000F) << 12)
+#define PLL_PDR_OUTDIV3_MASK		(0xF0FF)
+#define PLL_PDR_OUTDIV3(x)		(((x) & 0x0000000F) << 8)
+#define PLL_PDR_OUTDIV2_MASK		(0xFF0F)
+#define PLL_PDR_OUTDIV2(x)		(((x) & 0x0000000F) << 4)
+#define PLL_PDR_OUTDIV1_MASK		(0xFFF0)
+#define PLL_PDR_OUTDIV1(x)		((x) & 0x0000000F)
+#define PLL_PDR_USB(x)			PLL_PDR_OUTDIV4(x)
+#define PLL_PDR_SDRAM(x)		PLL_PDR_OUTDIV3(x)
+#define PLL_PDR_FB(x)			PLL_PDR_OUTDIV2(x)
+#define PLL_PDR_CPU(x)			PLL_PDR_OUTDIV1(x)
+
+#define PLL_PSR_LOCF			(0x00000200)
+#define PLL_PSR_LOC			(0x00000100)
+#define PLL_PSR_LOLF			(0x00000040)
+#define PLL_PSR_LOCKS			(0x00000020)
+#define PLL_PSR_LOCK			(0x00000010)
+#define PLL_PSR_MODE(x)			((x) & 0x07)
+
+/* *** Real Time Clock *** */
+#define RTC_OCEN_OSCBYP			(0x00000010)
+#define RTC_OCEN_CLKEN			(0x00000008)
+
+#endif				/* m5301x_h */
diff --git a/include/asm-m68k/m5329.h b/include/asm-m68k/m5329.h
index c1669dc..c7ebed1 100644
--- a/include/asm-m68k/m5329.h
+++ b/include/asm-m68k/m5329.h
@@ -187,65 +187,6 @@
 #define CFATR_TYPE			(0x01)
 
 /*********************************************************************
-* FlexBus Chip Selects (FBCS)
-*********************************************************************/
-/* Bit definitions and macros for FBCS_CSAR */
-#define CSAR_BA(x)			(((x)&0xFFFF)<<16)
-
-/* Bit definitions and macros for FBCS_CSMR */
-#define CSMR_BAM(x)			(((x)&0xFFFF)<<16)
-#define CSMR_BAM_4G			(0xFFFF0000)
-#define CSMR_BAM_2G			(0x7FFF0000)
-#define CSMR_BAM_1G			(0x3FFF0000)
-#define CSMR_BAM_1024M			(0x3FFF0000)
-#define CSMR_BAM_512M			(0x1FFF0000)
-#define CSMR_BAM_256M			(0x0FFF0000)
-#define CSMR_BAM_128M			(0x07FF0000)
-#define CSMR_BAM_64M			(0x03FF0000)
-#define CSMR_BAM_32M			(0x01FF0000)
-#define CSMR_BAM_16M			(0x00FF0000)
-#define CSMR_BAM_8M			(0x007F0000)
-#define CSMR_BAM_4M			(0x003F0000)
-#define CSMR_BAM_2M			(0x001F0000)
-#define CSMR_BAM_1M			(0x000F0000)
-#define CSMR_BAM_1024K			(0x000F0000)
-#define CSMR_BAM_512K			(0x00070000)
-#define CSMR_BAM_256K			(0x00030000)
-#define CSMR_BAM_128K			(0x00010000)
-#define CSMR_BAM_64K			(0x00000000)
-#define CSMR_WP				(0x00000100)
-#define CSMR_V				(0x00000001)
-
-/* Bit definitions and macros for FBCS_CSCR */
-#define CSCR_SWS(x)			(((x)&0x3F)<<26)
-#define CSCR_ASET(x)			(((x)&0x03)<<20)
-#define CSCR_SWSEN			(0x00800000)
-#define CSCR_ASET_4CLK			(0x00300000)
-#define CSCR_ASET_3CLK			(0x00200000)
-#define CSCR_ASET_2CLK			(0x00100000)
-#define CSCR_ASET_1CLK			(0x00000000)
-#define CSCR_RDAH(x)			(((x)&0x03)<<18)
-#define CSCR_RDAH_4CYC			(0x000C0000)
-#define CSCR_RDAH_3CYC			(0x00080000)
-#define CSCR_RDAH_2CYC			(0x00040000)
-#define CSCR_RDAH_1CYC			(0x00000000)
-#define CSCR_WRAH(x)			(((x)&0x03)<<16)
-#define CSCR_WDAH_4CYC			(0x00003000)
-#define CSCR_WDAH_3CYC			(0x00002000)
-#define CSCR_WDAH_2CYC			(0x00001000)
-#define CSCR_WDAH_1CYC			(0x00000000)
-#define CSCR_WS(x)			(((x)&0x3F)<<10)
-#define CSCR_SBM			(0x00000200)
-#define CSCR_AA				(0x00000100)
-#define CSCR_PS_MASK			(0x000000C0)
-#define CSCR_PS_32			(0x00000000)
-#define CSCR_PS_16			(0x00000080)
-#define CSCR_PS_8			(0x00000040)
-#define CSCR_BEM			(0x00000020)
-#define CSCR_BSTR			(0x00000010)
-#define CSCR_BSTW			(0x00000008)
-
-/*********************************************************************
 * Reset Controller Module (RCM)
 *********************************************************************/
 
@@ -261,100 +202,6 @@
 #define RCM_RSR_SOFT			(0x20)
 
 /*********************************************************************
-* FlexCAN Module (CAN)
-*********************************************************************/
-/* Bit definitions and macros for CAN_CANMCR */
-#define CANMCR_MDIS			(0x80000000)
-#define CANMCR_FRZ			(0x40000000)
-#define CANMCR_HALT			(0x10000000)
-#define CANMCR_NORDY			(0x08000000)
-#define CANMCR_SOFTRST			(0x02000000)
-#define CANMCR_FRZACK			(0x01000000)
-#define CANMCR_SUPV			(0x00800000)
-#define CANMCR_LPMACK			(0x00100000)
-#define CANMCR_MAXMB(x)			(((x)&0x0F))
-
-/* Bit definitions and macros for CAN_CANCTRL */
-#define CANCTRL_PRESDIV(x)		(((x)&0xFF)<<24)
-#define CANCTRL_RJW(x)			(((x)&0x03)<<22)
-#define CANCTRL_PSEG1(x)		(((x)&0x07)<<19)
-#define CANCTRL_PSEG2(x)		(((x)&0x07)<<16)
-#define CANCTRL_BOFFMSK			(0x00008000)
-#define CANCTRL_ERRMSK			(0x00004000)
-#define CANCTRL_CLKSRC			(0x00002000)
-#define CANCTRL_LPB			(0x00001000)
-#define CANCTRL_SMP			(0x00000080)
-#define CANCTRL_BOFFREC			(0x00000040)
-#define CANCTRL_TSYNC			(0x00000020)
-#define CANCTRL_LBUF			(0x00000010)
-#define CANCTRL_LOM			(0x00000008)
-#define CANCTRL_PROPSEG(x)		(((x)&0x07))
-
-/* Bit definitions and macros for CAN_TIMER */
-#define TIMER_TIMER(x)			((x)&0xFFFF)
-
-/* Bit definitions and macros for CAN_RXGMASK */
-#define RXGMASK_MI(x)			((x)&0x1FFFFFFF)
-
-/* Bit definitions and macros for CAN_ERRCNT */
-#define ERRCNT_TXECTR(x)		(((x)&0xFF))
-#define ERRCNT_RXECTR(x)		(((x)&0xFF)<<8)
-
-/* Bit definitions and macros for CAN_ERRSTAT */
-#define ERRSTAT_BITERR1			(0x00008000)
-#define ERRSTAT_BITERR0			(0x00004000)
-#define ERRSTAT_ACKERR			(0x00002000)
-#define ERRSTAT_CRCERR			(0x00001000)
-#define ERRSTAT_FRMERR			(0x00000800)
-#define ERRSTAT_STFERR			(0x00000400)
-#define ERRSTAT_TXWRN			(0x00000200)
-#define ERRSTAT_RXWRN			(0x00000100)
-#define ERRSTAT_IDLE			(0x00000080)
-#define ERRSTAT_TXRX			(0x00000040)
-#define ERRSTAT_FLT_BUSOFF		(0x00000020)
-#define ERRSTAT_FLT_PASSIVE		(0x00000010)
-#define ERRSTAT_FLT_ACTIVE		(0x00000000)
-#define ERRSTAT_BOFFINT			(0x00000004)
-#define ERRSTAT_ERRINT			(0x00000002)
-#define ERRSTAT_WAKINT			(0x00000001)
-
-/* Bit definitions and macros for CAN_IMASK */
-#define IMASK_BUF15M			(0x00008000)
-#define IMASK_BUF14M			(0x00004000)
-#define IMASK_BUF13M			(0x00002000)
-#define IMASK_BUF12M			(0x00001000)
-#define IMASK_BUF11M			(0x00000800)
-#define IMASK_BUF10M			(0x00000400)
-#define IMASK_BUF9M			(0x00000200)
-#define IMASK_BUF8M			(0x00000100)
-#define IMASK_BUF7M			(0x00000080)
-#define IMASK_BUF6M			(0x00000040)
-#define IMASK_BUF5M			(0x00000020)
-#define IMASK_BUF4M			(0x00000010)
-#define IMASK_BUF3M			(0x00000008)
-#define IMASK_BUF2M			(0x00000004)
-#define IMASK_BUF1M			(0x00000002)
-#define IMASK_BUF0M			(0x00000001)
-
-/* Bit definitions and macros for CAN_IFLAG */
-#define IFLAG_BUF15I			(0x00008000)
-#define IFLAG_BUF14I			(0x00004000)
-#define IFLAG_BUF13I			(0x00002000)
-#define IFLAG_BUF12I			(0x00001000)
-#define IFLAG_BUF11I			(0x00000800)
-#define IFLAG_BUF10I			(0x00000400)
-#define IFLAG_BUF9I			(0x00000200)
-#define IFLAG_BUF8I			(0x00000100)
-#define IFLAG_BUF7I			(0x00000080)
-#define IFLAG_BUF6I			(0x00000040)
-#define IFLAG_BUF5I			(0x00000020)
-#define IFLAG_BUF4I			(0x00000010)
-#define IFLAG_BUF3I			(0x00000008)
-#define IFLAG_BUF2I			(0x00000004)
-#define IFLAG_BUF1I			(0x00000002)
-#define IFLAG_BUF0I			(0x00000001)
-
-/*********************************************************************
 * Interrupt Controller (INTC)
 *********************************************************************/
 #define INTC0_EPORT			INTC_IPRL_INT1
@@ -411,200 +258,6 @@
 /* 49 - 61 Reserved */
 #define INT0_HI_SCM			(62)
 
-/* Bit definitions and macros for INTC_IPRH */
-#define INTC_IPRH_INT63			(0x80000000)
-#define INTC_IPRH_INT62			(0x40000000)
-#define INTC_IPRH_INT61			(0x20000000)
-#define INTC_IPRH_INT60			(0x10000000)
-#define INTC_IPRH_INT59			(0x08000000)
-#define INTC_IPRH_INT58			(0x04000000)
-#define INTC_IPRH_INT57			(0x02000000)
-#define INTC_IPRH_INT56			(0x01000000)
-#define INTC_IPRH_INT55			(0x00800000)
-#define INTC_IPRH_INT54			(0x00400000)
-#define INTC_IPRH_INT53			(0x00200000)
-#define INTC_IPRH_INT52			(0x00100000)
-#define INTC_IPRH_INT51			(0x00080000)
-#define INTC_IPRH_INT50			(0x00040000)
-#define INTC_IPRH_INT49			(0x00020000)
-#define INTC_IPRH_INT48			(0x00010000)
-#define INTC_IPRH_INT47			(0x00008000)
-#define INTC_IPRH_INT46			(0x00004000)
-#define INTC_IPRH_INT45			(0x00002000)
-#define INTC_IPRH_INT44			(0x00001000)
-#define INTC_IPRH_INT43			(0x00000800)
-#define INTC_IPRH_INT42			(0x00000400)
-#define INTC_IPRH_INT41			(0x00000200)
-#define INTC_IPRH_INT40			(0x00000100)
-#define INTC_IPRH_INT39			(0x00000080)
-#define INTC_IPRH_INT38			(0x00000040)
-#define INTC_IPRH_INT37			(0x00000020)
-#define INTC_IPRH_INT36			(0x00000010)
-#define INTC_IPRH_INT35			(0x00000008)
-#define INTC_IPRH_INT34			(0x00000004)
-#define INTC_IPRH_INT33			(0x00000002)
-#define INTC_IPRH_INT32			(0x00000001)
-
-/* Bit definitions and macros for INTC_IPRL */
-#define INTC_IPRL_INT31			(0x80000000)
-#define INTC_IPRL_INT30			(0x40000000)
-#define INTC_IPRL_INT29			(0x20000000)
-#define INTC_IPRL_INT28			(0x10000000)
-#define INTC_IPRL_INT27			(0x08000000)
-#define INTC_IPRL_INT26			(0x04000000)
-#define INTC_IPRL_INT25			(0x02000000)
-#define INTC_IPRL_INT24			(0x01000000)
-#define INTC_IPRL_INT23			(0x00800000)
-#define INTC_IPRL_INT22			(0x00400000)
-#define INTC_IPRL_INT21			(0x00200000)
-#define INTC_IPRL_INT20			(0x00100000)
-#define INTC_IPRL_INT19			(0x00080000)
-#define INTC_IPRL_INT18			(0x00040000)
-#define INTC_IPRL_INT17			(0x00020000)
-#define INTC_IPRL_INT16			(0x00010000)
-#define INTC_IPRL_INT15			(0x00008000)
-#define INTC_IPRL_INT14			(0x00004000)
-#define INTC_IPRL_INT13			(0x00002000)
-#define INTC_IPRL_INT12			(0x00001000)
-#define INTC_IPRL_INT11			(0x00000800)
-#define INTC_IPRL_INT10			(0x00000400)
-#define INTC_IPRL_INT9			(0x00000200)
-#define INTC_IPRL_INT8			(0x00000100)
-#define INTC_IPRL_INT7			(0x00000080)
-#define INTC_IPRL_INT6			(0x00000040)
-#define INTC_IPRL_INT5			(0x00000020)
-#define INTC_IPRL_INT4			(0x00000010)
-#define INTC_IPRL_INT3			(0x00000008)
-#define INTC_IPRL_INT2			(0x00000004)
-#define INTC_IPRL_INT1			(0x00000002)
-#define INTC_IPRL_INT0			(0x00000001)
-
-/* Bit definitions and macros for INTC_ICONFIG */
-#define INTC_ICFG_ELVLPRI7		(0x8000)
-#define INTC_ICFG_ELVLPRI6		(0x4000)
-#define INTC_ICFG_ELVLPRI5		(0x2000)
-#define INTC_ICFG_ELVLPRI4		(0x1000)
-#define INTC_ICFG_ELVLPRI3		(0x0800)
-#define INTC_ICFG_ELVLPRI2		(0x0400)
-#define INTC_ICFG_ELVLPRI1		(0x0200)
-#define INTC_ICFG_EMASK			(0x0020)
-
-/* Bit definitions and macros for INTC_SIMR */
-#define INTC_SIMR_SALL			(0x40)
-#define INTC_SIMR_SIMR(x)		((x)&0x3F)
-
-/* Bit definitions and macros for INTC_CIMR */
-#define INTC_CIMR_CALL			(0x40)
-#define INTC_CIMR_CIMR(x)		((x)&0x3F)
-
-/* Bit definitions and macros for INTC_CLMASK */
-#define INTC_CLMASK_CLMASK(x)		((x)&0x0F)
-
-/* Bit definitions and macros for INTC_SLMASK */
-#define INTC_SLMASK_SLMASK(x)		((x)&0x0F)
-
-/* Bit definitions and macros for INTC_ICR */
-#define INTC_ICR_IL(x)			((x)&0x07)
-
-/*********************************************************************
-* Queued Serial Peripheral Interface (QSPI)
-*********************************************************************/
-/* Bit definitions and macros for QSPI_QMR */
-#define QSPI_QMR_MSTR			(0x8000)
-#define QSPI_QMR_DOHIE			(0x4000)
-#define QSPI_QMR_BITS(x)		(((x)&0x000F)<<10)
-#define QSPI_QMR_CPOL			(0x0200)
-#define QSPI_QMR_CPHA			(0x0100)
-#define QSPI_QMR_BAUD(x)		((x)&0x00FF)
-
-/* Bit definitions and macros for QSPI_QDLYR */
-#define QSPI_QDLYR_SPE			(0x8000)
-#define QSPI_QDLYR_QCD(x)		(((x)&0x007F)<<8)
-#define QSPI_QDLYR_DTL(x)		((x)&0x00FF)
-
-/* Bit definitions and macros for QSPI_QWR */
-#define QSPI_QWR_NEWQP(x)		((x)&0x000F)
-#define QSPI_QWR_ENDQP(x)		(((x)&0x000F)<<8)
-#define QSPI_QWR_CSIV			(0x1000)
-#define QSPI_QWR_WRTO			(0x2000)
-#define QSPI_QWR_WREN			(0x4000)
-#define QSPI_QWR_HALT			(0x8000)
-
-/* Bit definitions and macros for QSPI_QIR */
-#define QSPI_QIR_WCEFB			(0x8000)
-#define QSPI_QIR_ABRTB			(0x4000)
-#define QSPI_QIR_ABRTL			(0x1000)
-#define QSPI_QIR_WCEFE			(0x0800)
-#define QSPI_QIR_ABRTE			(0x0400)
-#define QSPI_QIR_SPIFE			(0x0100)
-#define QSPI_QIR_WCEF			(0x0008)
-#define QSPI_QIR_ABRT			(0x0004)
-#define QSPI_QIR_SPIF			(0x0001)
-
-/* Bit definitions and macros for QSPI_QAR */
-#define QSPI_QAR_ADDR(x)		((x)&0x003F)
-#define QSPI_QAR_TRANS			(0x0000)
-#define QSPI_QAR_RECV			(0x0010)
-#define QSPI_QAR_CMD			(0x0020)
-
-/* Bit definitions and macros for QSPI_QDR */
-#define QSPI_QDR_CONT			(0x8000)
-#define QSPI_QDR_BITSE			(0x4000)
-#define QSPI_QDR_DT			(0x2000)
-#define QSPI_QDR_DSCK			(0x1000)
-#define QSPI_QDR_QSPI_CS3		(0x0800)
-#define QSPI_QDR_QSPI_CS2		(0x0400)
-#define QSPI_QDR_QSPI_CS1		(0x0200)
-#define QSPI_QDR_QSPI_CS0		(0x0100)
-
-/*********************************************************************
-* Pulse Width Modulation (PWM)
-*********************************************************************/
-/* Bit definitions and macros for PWM_E */
-#define PWM_EN_PWME7			(0x80)
-#define PWM_EN_PWME5			(0x20)
-#define PWM_EN_PWME3			(0x08)
-#define PWM_EN_PWME1			(0x02)
-
-/* Bit definitions and macros for PWM_POL */
-#define PWM_POL_PPOL7			(0x80)
-#define PWM_POL_PPOL5			(0x20)
-#define PWM_POL_PPOL3			(0x08)
-#define PWM_POL_PPOL1			(0x02)
-
-/* Bit definitions and macros for PWM_CLK */
-#define PWM_CLK_PCLK7			(0x80)
-#define PWM_CLK_PCLK5			(0x20)
-#define PWM_CLK_PCLK3			(0x08)
-#define PWM_CLK_PCLK1			(0x02)
-
-/* Bit definitions and macros for PWM_PRCLK */
-#define PWM_PRCLK_PCKB(x)		(((x)&0x07)<<4)
-#define PWM_PRCLK_PCKA(x)		((x)&0x07)
-
-/* Bit definitions and macros for PWM_CAE */
-#define PWM_CAE_CAE7			(0x80)
-#define PWM_CAE_CAE5			(0x20)
-#define PWM_CAE_CAE3			(0x08)
-#define PWM_CAE_CAE1			(0x02)
-
-/* Bit definitions and macros for PWM_CTL */
-#define PWM_CTL_CON67			(0x80)
-#define PWM_CTL_CON45			(0x40)
-#define PWM_CTL_CON23			(0x20)
-#define PWM_CTL_CON01			(0x10)
-#define PWM_CTL_PSWAR			(0x08)
-#define PWM_CTL_PFRZ			(0x04)
-
-/* Bit definitions and macros for PWM_SDN */
-#define PWM_SDN_IF			(0x80)
-#define PWM_SDN_IE			(0x40)
-#define PWM_SDN_RESTART			(0x20)
-#define PWM_SDN_LVL			(0x10)
-#define PWM_SDN_PWM7IN			(0x04)
-#define PWM_SDN_PWM7IL			(0x02)
-#define PWM_SDN_SDNEN			(0x01)
-
 /*********************************************************************
 * Watchdog Timer Modules (WTM)
 *********************************************************************/
diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h
index 7fcf4ef..5966621 100644
--- a/include/asm-m68k/m5445x.h
+++ b/include/asm-m68k/m5445x.h
@@ -114,325 +114,6 @@
 #define INT1_HI_PCI_ASR			(56)
 #define INT1_HI_PLL_LOCKS		(57)
 
-/* Bit definitions and macros for IPRH */
-#define INTC_IPRH_INT32			(0x00000001)
-#define INTC_IPRH_INT33			(0x00000002)
-#define INTC_IPRH_INT34			(0x00000004)
-#define INTC_IPRH_INT35			(0x00000008)
-#define INTC_IPRH_INT36			(0x00000010)
-#define INTC_IPRH_INT37			(0x00000020)
-#define INTC_IPRH_INT38			(0x00000040)
-#define INTC_IPRH_INT39			(0x00000080)
-#define INTC_IPRH_INT40			(0x00000100)
-#define INTC_IPRH_INT41			(0x00000200)
-#define INTC_IPRH_INT42			(0x00000400)
-#define INTC_IPRH_INT43			(0x00000800)
-#define INTC_IPRH_INT44			(0x00001000)
-#define INTC_IPRH_INT45			(0x00002000)
-#define INTC_IPRH_INT46			(0x00004000)
-#define INTC_IPRH_INT47			(0x00008000)
-#define INTC_IPRH_INT48			(0x00010000)
-#define INTC_IPRH_INT49			(0x00020000)
-#define INTC_IPRH_INT50			(0x00040000)
-#define INTC_IPRH_INT51			(0x00080000)
-#define INTC_IPRH_INT52			(0x00100000)
-#define INTC_IPRH_INT53			(0x00200000)
-#define INTC_IPRH_INT54			(0x00400000)
-#define INTC_IPRH_INT55			(0x00800000)
-#define INTC_IPRH_INT56			(0x01000000)
-#define INTC_IPRH_INT57			(0x02000000)
-#define INTC_IPRH_INT58			(0x04000000)
-#define INTC_IPRH_INT59			(0x08000000)
-#define INTC_IPRH_INT60			(0x10000000)
-#define INTC_IPRH_INT61			(0x20000000)
-#define INTC_IPRH_INT62			(0x40000000)
-#define INTC_IPRH_INT63			(0x80000000)
-
-/* Bit definitions and macros for IPRL */
-#define INTC_IPRL_INT0			(0x00000001)
-#define INTC_IPRL_INT1			(0x00000002)
-#define INTC_IPRL_INT2			(0x00000004)
-#define INTC_IPRL_INT3			(0x00000008)
-#define INTC_IPRL_INT4			(0x00000010)
-#define INTC_IPRL_INT5			(0x00000020)
-#define INTC_IPRL_INT6			(0x00000040)
-#define INTC_IPRL_INT7			(0x00000080)
-#define INTC_IPRL_INT8			(0x00000100)
-#define INTC_IPRL_INT9			(0x00000200)
-#define INTC_IPRL_INT10			(0x00000400)
-#define INTC_IPRL_INT11			(0x00000800)
-#define INTC_IPRL_INT12			(0x00001000)
-#define INTC_IPRL_INT13			(0x00002000)
-#define INTC_IPRL_INT14			(0x00004000)
-#define INTC_IPRL_INT15			(0x00008000)
-#define INTC_IPRL_INT16			(0x00010000)
-#define INTC_IPRL_INT17			(0x00020000)
-#define INTC_IPRL_INT18			(0x00040000)
-#define INTC_IPRL_INT19			(0x00080000)
-#define INTC_IPRL_INT20			(0x00100000)
-#define INTC_IPRL_INT21			(0x00200000)
-#define INTC_IPRL_INT22			(0x00400000)
-#define INTC_IPRL_INT23			(0x00800000)
-#define INTC_IPRL_INT24			(0x01000000)
-#define INTC_IPRL_INT25			(0x02000000)
-#define INTC_IPRL_INT26			(0x04000000)
-#define INTC_IPRL_INT27			(0x08000000)
-#define INTC_IPRL_INT28			(0x10000000)
-#define INTC_IPRL_INT29			(0x20000000)
-#define INTC_IPRL_INT30			(0x40000000)
-#define INTC_IPRL_INT31			(0x80000000)
-
-/* Bit definitions and macros for IMRH */
-#define INTC_IMRH_INT_MASK32		(0x00000001)
-#define INTC_IMRH_INT_MASK33		(0x00000002)
-#define INTC_IMRH_INT_MASK34		(0x00000004)
-#define INTC_IMRH_INT_MASK35		(0x00000008)
-#define INTC_IMRH_INT_MASK36		(0x00000010)
-#define INTC_IMRH_INT_MASK37		(0x00000020)
-#define INTC_IMRH_INT_MASK38		(0x00000040)
-#define INTC_IMRH_INT_MASK39		(0x00000080)
-#define INTC_IMRH_INT_MASK40		(0x00000100)
-#define INTC_IMRH_INT_MASK41		(0x00000200)
-#define INTC_IMRH_INT_MASK42		(0x00000400)
-#define INTC_IMRH_INT_MASK43		(0x00000800)
-#define INTC_IMRH_INT_MASK44		(0x00001000)
-#define INTC_IMRH_INT_MASK45		(0x00002000)
-#define INTC_IMRH_INT_MASK46		(0x00004000)
-#define INTC_IMRH_INT_MASK47		(0x00008000)
-#define INTC_IMRH_INT_MASK48		(0x00010000)
-#define INTC_IMRH_INT_MASK49		(0x00020000)
-#define INTC_IMRH_INT_MASK50		(0x00040000)
-#define INTC_IMRH_INT_MASK51		(0x00080000)
-#define INTC_IMRH_INT_MASK52		(0x00100000)
-#define INTC_IMRH_INT_MASK53		(0x00200000)
-#define INTC_IMRH_INT_MASK54		(0x00400000)
-#define INTC_IMRH_INT_MASK55		(0x00800000)
-#define INTC_IMRH_INT_MASK56		(0x01000000)
-#define INTC_IMRH_INT_MASK57		(0x02000000)
-#define INTC_IMRH_INT_MASK58		(0x04000000)
-#define INTC_IMRH_INT_MASK59		(0x08000000)
-#define INTC_IMRH_INT_MASK60		(0x10000000)
-#define INTC_IMRH_INT_MASK61		(0x20000000)
-#define INTC_IMRH_INT_MASK62		(0x40000000)
-#define INTC_IMRH_INT_MASK63		(0x80000000)
-
-/* Bit definitions and macros for IMRL */
-#define INTC_IMRL_INT_MASK0		(0x00000001)
-#define INTC_IMRL_INT_MASK1		(0x00000002)
-#define INTC_IMRL_INT_MASK2		(0x00000004)
-#define INTC_IMRL_INT_MASK3		(0x00000008)
-#define INTC_IMRL_INT_MASK4		(0x00000010)
-#define INTC_IMRL_INT_MASK5		(0x00000020)
-#define INTC_IMRL_INT_MASK6		(0x00000040)
-#define INTC_IMRL_INT_MASK7		(0x00000080)
-#define INTC_IMRL_INT_MASK8		(0x00000100)
-#define INTC_IMRL_INT_MASK9		(0x00000200)
-#define INTC_IMRL_INT_MASK10		(0x00000400)
-#define INTC_IMRL_INT_MASK11		(0x00000800)
-#define INTC_IMRL_INT_MASK12		(0x00001000)
-#define INTC_IMRL_INT_MASK13		(0x00002000)
-#define INTC_IMRL_INT_MASK14		(0x00004000)
-#define INTC_IMRL_INT_MASK15		(0x00008000)
-#define INTC_IMRL_INT_MASK16		(0x00010000)
-#define INTC_IMRL_INT_MASK17		(0x00020000)
-#define INTC_IMRL_INT_MASK18		(0x00040000)
-#define INTC_IMRL_INT_MASK19		(0x00080000)
-#define INTC_IMRL_INT_MASK20		(0x00100000)
-#define INTC_IMRL_INT_MASK21		(0x00200000)
-#define INTC_IMRL_INT_MASK22		(0x00400000)
-#define INTC_IMRL_INT_MASK23		(0x00800000)
-#define INTC_IMRL_INT_MASK24		(0x01000000)
-#define INTC_IMRL_INT_MASK25		(0x02000000)
-#define INTC_IMRL_INT_MASK26		(0x04000000)
-#define INTC_IMRL_INT_MASK27		(0x08000000)
-#define INTC_IMRL_INT_MASK28		(0x10000000)
-#define INTC_IMRL_INT_MASK29		(0x20000000)
-#define INTC_IMRL_INT_MASK30		(0x40000000)
-#define INTC_IMRL_INT_MASK31		(0x80000000)
-
-/* Bit definitions and macros for INTFRCH */
-#define INTC_INTFRCH_INTFRC32		(0x00000001)
-#define INTC_INTFRCH_INTFRC33		(0x00000002)
-#define INTC_INTFRCH_INTFRC34		(0x00000004)
-#define INTC_INTFRCH_INTFRC35		(0x00000008)
-#define INTC_INTFRCH_INTFRC36		(0x00000010)
-#define INTC_INTFRCH_INTFRC37		(0x00000020)
-#define INTC_INTFRCH_INTFRC38		(0x00000040)
-#define INTC_INTFRCH_INTFRC39		(0x00000080)
-#define INTC_INTFRCH_INTFRC40		(0x00000100)
-#define INTC_INTFRCH_INTFRC41		(0x00000200)
-#define INTC_INTFRCH_INTFRC42		(0x00000400)
-#define INTC_INTFRCH_INTFRC43		(0x00000800)
-#define INTC_INTFRCH_INTFRC44		(0x00001000)
-#define INTC_INTFRCH_INTFRC45		(0x00002000)
-#define INTC_INTFRCH_INTFRC46		(0x00004000)
-#define INTC_INTFRCH_INTFRC47		(0x00008000)
-#define INTC_INTFRCH_INTFRC48		(0x00010000)
-#define INTC_INTFRCH_INTFRC49		(0x00020000)
-#define INTC_INTFRCH_INTFRC50		(0x00040000)
-#define INTC_INTFRCH_INTFRC51		(0x00080000)
-#define INTC_INTFRCH_INTFRC52		(0x00100000)
-#define INTC_INTFRCH_INTFRC53		(0x00200000)
-#define INTC_INTFRCH_INTFRC54		(0x00400000)
-#define INTC_INTFRCH_INTFRC55		(0x00800000)
-#define INTC_INTFRCH_INTFRC56		(0x01000000)
-#define INTC_INTFRCH_INTFRC57		(0x02000000)
-#define INTC_INTFRCH_INTFRC58		(0x04000000)
-#define INTC_INTFRCH_INTFRC59		(0x08000000)
-#define INTC_INTFRCH_INTFRC60		(0x10000000)
-#define INTC_INTFRCH_INTFRC61		(0x20000000)
-#define INTC_INTFRCH_INTFRC62		(0x40000000)
-#define INTC_INTFRCH_INTFRC63		(0x80000000)
-
-/* Bit definitions and macros for INTFRCL */
-#define INTC_INTFRCL_INTFRC0		(0x00000001)
-#define INTC_INTFRCL_INTFRC1		(0x00000002)
-#define INTC_INTFRCL_INTFRC2		(0x00000004)
-#define INTC_INTFRCL_INTFRC3		(0x00000008)
-#define INTC_INTFRCL_INTFRC4		(0x00000010)
-#define INTC_INTFRCL_INTFRC5		(0x00000020)
-#define INTC_INTFRCL_INTFRC6		(0x00000040)
-#define INTC_INTFRCL_INTFRC7		(0x00000080)
-#define INTC_INTFRCL_INTFRC8		(0x00000100)
-#define INTC_INTFRCL_INTFRC9		(0x00000200)
-#define INTC_INTFRCL_INTFRC10		(0x00000400)
-#define INTC_INTFRCL_INTFRC11		(0x00000800)
-#define INTC_INTFRCL_INTFRC12		(0x00001000)
-#define INTC_INTFRCL_INTFRC13		(0x00002000)
-#define INTC_INTFRCL_INTFRC14		(0x00004000)
-#define INTC_INTFRCL_INTFRC15		(0x00008000)
-#define INTC_INTFRCL_INTFRC16		(0x00010000)
-#define INTC_INTFRCL_INTFRC17		(0x00020000)
-#define INTC_INTFRCL_INTFRC18		(0x00040000)
-#define INTC_INTFRCL_INTFRC19		(0x00080000)
-#define INTC_INTFRCL_INTFRC20		(0x00100000)
-#define INTC_INTFRCL_INTFRC21		(0x00200000)
-#define INTC_INTFRCL_INTFRC22		(0x00400000)
-#define INTC_INTFRCL_INTFRC23		(0x00800000)
-#define INTC_INTFRCL_INTFRC24		(0x01000000)
-#define INTC_INTFRCL_INTFRC25		(0x02000000)
-#define INTC_INTFRCL_INTFRC26		(0x04000000)
-#define INTC_INTFRCL_INTFRC27		(0x08000000)
-#define INTC_INTFRCL_INTFRC28		(0x10000000)
-#define INTC_INTFRCL_INTFRC29		(0x20000000)
-#define INTC_INTFRCL_INTFRC30		(0x40000000)
-#define INTC_INTFRCL_INTFRC31		(0x80000000)
-
-/* Bit definitions and macros for ICONFIG */
-#define INTC_ICONFIG_EMASK		(0x0020)
-#define INTC_ICONFIG_ELVLPRI1		(0x0200)
-#define INTC_ICONFIG_ELVLPRI2		(0x0400)
-#define INTC_ICONFIG_ELVLPRI3		(0x0800)
-#define INTC_ICONFIG_ELVLPRI4		(0x1000)
-#define INTC_ICONFIG_ELVLPRI5		(0x2000)
-#define INTC_ICONFIG_ELVLPRI6		(0x4000)
-#define INTC_ICONFIG_ELVLPRI7		(0x8000)
-
-/* Bit definitions and macros for SIMR */
-#define INTC_SIMR_SIMR(x)		(((x)&0x7F))
-
-/* Bit definitions and macros for CIMR */
-#define INTC_CIMR_CIMR(x)		(((x)&0x7F))
-
-/* Bit definitions and macros for CLMASK */
-#define INTC_CLMASK_CLMASK(x)		(((x)&0x0F))
-
-/* Bit definitions and macros for SLMASK */
-#define INTC_SLMASK_SLMASK(x)		(((x)&0x0F))
-
-/* Bit definitions and macros for ICR group */
-#define INTC_ICR_IL(x)			(((x)&0x07))
-
-/*********************************************************************
-* Edge Port Module (EPORT)
-*********************************************************************/
-
-/* Bit definitions and macros for EPPAR */
-#define EPORT_EPPAR_EPPA1(x)		(((x)&0x0003)<<2)
-#define EPORT_EPPAR_EPPA2(x)		(((x)&0x0003)<<4)
-#define EPORT_EPPAR_EPPA3(x)		(((x)&0x0003)<<6)
-#define EPORT_EPPAR_EPPA4(x)		(((x)&0x0003)<<8)
-#define EPORT_EPPAR_EPPA5(x)		(((x)&0x0003)<<10)
-#define EPORT_EPPAR_EPPA6(x)		(((x)&0x0003)<<12)
-#define EPORT_EPPAR_EPPA7(x)		(((x)&0x0003)<<14)
-#define EPORT_EPPAR_LEVEL		(0)
-#define EPORT_EPPAR_RISING		(1)
-#define EPORT_EPPAR_FALLING		(2)
-#define EPORT_EPPAR_BOTH		(3)
-#define EPORT_EPPAR_EPPA7_LEVEL		(0x0000)
-#define EPORT_EPPAR_EPPA7_RISING	(0x4000)
-#define EPORT_EPPAR_EPPA7_FALLING	(0x8000)
-#define EPORT_EPPAR_EPPA7_BOTH		(0xC000)
-#define EPORT_EPPAR_EPPA6_LEVEL		(0x0000)
-#define EPORT_EPPAR_EPPA6_RISING	(0x1000)
-#define EPORT_EPPAR_EPPA6_FALLING	(0x2000)
-#define EPORT_EPPAR_EPPA6_BOTH		(0x3000)
-#define EPORT_EPPAR_EPPA5_LEVEL		(0x0000)
-#define EPORT_EPPAR_EPPA5_RISING	(0x0400)
-#define EPORT_EPPAR_EPPA5_FALLING	(0x0800)
-#define EPORT_EPPAR_EPPA5_BOTH		(0x0C00)
-#define EPORT_EPPAR_EPPA4_LEVEL		(0x0000)
-#define EPORT_EPPAR_EPPA4_RISING	(0x0100)
-#define EPORT_EPPAR_EPPA4_FALLING	(0x0200)
-#define EPORT_EPPAR_EPPA4_BOTH		(0x0300)
-#define EPORT_EPPAR_EPPA3_LEVEL		(0x0000)
-#define EPORT_EPPAR_EPPA3_RISING	(0x0040)
-#define EPORT_EPPAR_EPPA3_FALLING	(0x0080)
-#define EPORT_EPPAR_EPPA3_BOTH		(0x00C0)
-#define EPORT_EPPAR_EPPA2_LEVEL		(0x0000)
-#define EPORT_EPPAR_EPPA2_RISING	(0x0010)
-#define EPORT_EPPAR_EPPA2_FALLING	(0x0020)
-#define EPORT_EPPAR_EPPA2_BOTH		(0x0030)
-#define EPORT_EPPAR_EPPA1_LEVEL		(0x0000)
-#define EPORT_EPPAR_EPPA1_RISING	(0x0004)
-#define EPORT_EPPAR_EPPA1_FALLING	(0x0008)
-#define EPORT_EPPAR_EPPA1_BOTH		(0x000C)
-
-/* Bit definitions and macros for EPDDR */
-#define EPORT_EPDDR_EPDD1		(0x02)
-#define EPORT_EPDDR_EPDD2		(0x04)
-#define EPORT_EPDDR_EPDD3		(0x08)
-#define EPORT_EPDDR_EPDD4		(0x10)
-#define EPORT_EPDDR_EPDD5		(0x20)
-#define EPORT_EPDDR_EPDD6		(0x40)
-#define EPORT_EPDDR_EPDD7		(0x80)
-
-/* Bit definitions and macros for EPIER */
-#define EPORT_EPIER_EPIE1		(0x02)
-#define EPORT_EPIER_EPIE2		(0x04)
-#define EPORT_EPIER_EPIE3		(0x08)
-#define EPORT_EPIER_EPIE4		(0x10)
-#define EPORT_EPIER_EPIE5		(0x20)
-#define EPORT_EPIER_EPIE6		(0x40)
-#define EPORT_EPIER_EPIE7		(0x80)
-
-/* Bit definitions and macros for EPDR */
-#define EPORT_EPDR_EPD1			(0x02)
-#define EPORT_EPDR_EPD2			(0x04)
-#define EPORT_EPDR_EPD3			(0x08)
-#define EPORT_EPDR_EPD4			(0x10)
-#define EPORT_EPDR_EPD5			(0x20)
-#define EPORT_EPDR_EPD6			(0x40)
-#define EPORT_EPDR_EPD7			(0x80)
-
-/* Bit definitions and macros for EPPDR */
-#define EPORT_EPPDR_EPPD1		(0x02)
-#define EPORT_EPPDR_EPPD2		(0x04)
-#define EPORT_EPPDR_EPPD3		(0x08)
-#define EPORT_EPPDR_EPPD4		(0x10)
-#define EPORT_EPPDR_EPPD5		(0x20)
-#define EPORT_EPPDR_EPPD6		(0x40)
-#define EPORT_EPPDR_EPPD7		(0x80)
-
-/* Bit definitions and macros for EPFR */
-#define EPORT_EPFR_EPF1			(0x02)
-#define EPORT_EPFR_EPF2			(0x04)
-#define EPORT_EPFR_EPF3			(0x08)
-#define EPORT_EPFR_EPF4			(0x10)
-#define EPORT_EPFR_EPF5			(0x20)
-#define EPORT_EPFR_EPF6			(0x40)
-#define EPORT_EPFR_EPF7			(0x80)
-
 /*********************************************************************
 * Watchdog Timer Modules (WTM)
 *********************************************************************/
@@ -1040,24 +721,6 @@
 #define GPIO_DSCR_ATA_ATA_LOAD_10PF	(0x00)
 
 /*********************************************************************
-* Random Number Generator (RNG)
-*********************************************************************/
-
-/* Bit definitions and macros for RNGCR */
-#define RNG_RNGCR_GO			(0x00000001)
-#define RNG_RNGCR_HA			(0x00000002)
-#define RNG_RNGCR_IM			(0x00000004)
-#define RNG_RNGCR_CI			(0x00000008)
-
-/* Bit definitions and macros for RNGSR */
-#define RNG_RNGSR_SV			(0x00000001)
-#define RNG_RNGSR_LRS			(0x00000002)
-#define RNG_RNGSR_FUF			(0x00000004)
-#define RNG_RNGSR_EI			(0x00000008)
-#define RNG_RNGSR_OFL(x)		(((x)&0x000000FF)<<8)
-#define RNG_RNGSR_OFS(x)		(((x)&0x000000FF)<<16)
-
-/*********************************************************************
 * SDRAM Controller (SDRAMC)
 *********************************************************************/
 
diff --git a/include/asm-m68k/m547x_8x.h b/include/asm-m68k/m547x_8x.h
index 2db8df2..23cee8e 100644
--- a/include/asm-m68k/m547x_8x.h
+++ b/include/asm-m68k/m547x_8x.h
@@ -305,74 +305,6 @@
 #define INT0_HI_GPT1			(61)
 #define INT0_HI_GPT0			(62)
 
-/* Bit definitions and macros for IPRH */
-#define INTC_IPRH_INT32			(0x00000001)
-#define INTC_IPRH_INT33			(0x00000002)
-#define INTC_IPRH_INT34			(0x00000004)
-#define INTC_IPRH_INT35			(0x00000008)
-#define INTC_IPRH_INT36			(0x00000010)
-#define INTC_IPRH_INT37			(0x00000020)
-#define INTC_IPRH_INT38			(0x00000040)
-#define INTC_IPRH_INT39			(0x00000080)
-#define INTC_IPRH_INT40			(0x00000100)
-#define INTC_IPRH_INT41			(0x00000200)
-#define INTC_IPRH_INT42			(0x00000400)
-#define INTC_IPRH_INT43			(0x00000800)
-#define INTC_IPRH_INT44			(0x00001000)
-#define INTC_IPRH_INT45			(0x00002000)
-#define INTC_IPRH_INT46			(0x00004000)
-#define INTC_IPRH_INT47			(0x00008000)
-#define INTC_IPRH_INT48			(0x00010000)
-#define INTC_IPRH_INT49			(0x00020000)
-#define INTC_IPRH_INT50			(0x00040000)
-#define INTC_IPRH_INT51			(0x00080000)
-#define INTC_IPRH_INT52			(0x00100000)
-#define INTC_IPRH_INT53			(0x00200000)
-#define INTC_IPRH_INT54			(0x00400000)
-#define INTC_IPRH_INT55			(0x00800000)
-#define INTC_IPRH_INT56			(0x01000000)
-#define INTC_IPRH_INT57			(0x02000000)
-#define INTC_IPRH_INT58			(0x04000000)
-#define INTC_IPRH_INT59			(0x08000000)
-#define INTC_IPRH_INT60			(0x10000000)
-#define INTC_IPRH_INT61			(0x20000000)
-#define INTC_IPRH_INT62			(0x40000000)
-#define INTC_IPRH_INT63			(0x80000000)
-
-/* Bit definitions and macros for IPRL */
-#define INTC_IPRL_INT0			(0x00000001)
-#define INTC_IPRL_INT1			(0x00000002)
-#define INTC_IPRL_INT2			(0x00000004)
-#define INTC_IPRL_INT3			(0x00000008)
-#define INTC_IPRL_INT4			(0x00000010)
-#define INTC_IPRL_INT5			(0x00000020)
-#define INTC_IPRL_INT6			(0x00000040)
-#define INTC_IPRL_INT7			(0x00000080)
-#define INTC_IPRL_INT8			(0x00000100)
-#define INTC_IPRL_INT9			(0x00000200)
-#define INTC_IPRL_INT10			(0x00000400)
-#define INTC_IPRL_INT11			(0x00000800)
-#define INTC_IPRL_INT12			(0x00001000)
-#define INTC_IPRL_INT13			(0x00002000)
-#define INTC_IPRL_INT14			(0x00004000)
-#define INTC_IPRL_INT15			(0x00008000)
-#define INTC_IPRL_INT16			(0x00010000)
-#define INTC_IPRL_INT17			(0x00020000)
-#define INTC_IPRL_INT18			(0x00040000)
-#define INTC_IPRL_INT19			(0x00080000)
-#define INTC_IPRL_INT20			(0x00100000)
-#define INTC_IPRL_INT21			(0x00200000)
-#define INTC_IPRL_INT22			(0x00400000)
-#define INTC_IPRL_INT23			(0x00800000)
-#define INTC_IPRL_INT24			(0x01000000)
-#define INTC_IPRL_INT25			(0x02000000)
-#define INTC_IPRL_INT26			(0x04000000)
-#define INTC_IPRL_INT27			(0x08000000)
-#define INTC_IPRL_INT28			(0x10000000)
-#define INTC_IPRL_INT29			(0x20000000)
-#define INTC_IPRL_INT30			(0x40000000)
-#define INTC_IPRL_INT31			(0x80000000)
-
 /*********************************************************************
 * General Purpose Timers (GPTMR)
 *********************************************************************/
diff --git a/include/asm-microblaze/config.h b/include/asm-microblaze/config.h
new file mode 100644
index 0000000..049c44e
--- /dev/null
+++ b/include/asm-microblaze/config.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
diff --git a/include/asm-microblaze/global_data.h b/include/asm-microblaze/global_data.h
index 013c56a..3f49c34 100644
--- a/include/asm-microblaze/global_data.h
+++ b/include/asm-microblaze/global_data.h
@@ -31,7 +31,7 @@
  * global variables during system initialization (until we have set
  * up the memory controller so that we can use RAM).
  *
- * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
  */
 
 typedef	struct	global_data {
diff --git a/include/asm-microblaze/io.h b/include/asm-microblaze/io.h
index 8804724..7e190d1 100644
--- a/include/asm-microblaze/io.h
+++ b/include/asm-microblaze/io.h
@@ -155,4 +155,9 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
 
 }
 
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
 #endif /* __MICROBLAZE_IO_H__ */
diff --git a/include/asm-mips/config.h b/include/asm-mips/config.h
new file mode 100644
index 0000000..049c44e
--- /dev/null
+++ b/include/asm-mips/config.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
diff --git a/include/asm-mips/global_data.h b/include/asm-mips/global_data.h
index 7cf2a00..b2c4891 100644
--- a/include/asm-mips/global_data.h
+++ b/include/asm-mips/global_data.h
@@ -33,7 +33,7 @@
  * global variables during system initialization (until we have set
  * up the memory controller so that we can use RAM).
  *
- * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
  */
 
 typedef	struct	global_data {
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 3a0f33f..025012a 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -118,7 +118,7 @@ static inline void set_io_port_base(unsigned long base)
  * Change virtual addresses to physical addresses and vv.
  * These are trivial on the 1:1 Linux/MIPS mapping
  */
-extern inline unsigned long virt_to_phys(volatile void * address)
+extern inline phys_addr_t virt_to_phys(volatile void * address)
 {
 	return CPHYSADDR(address);
 }
diff --git a/include/asm-nios/config.h b/include/asm-nios/config.h
new file mode 100644
index 0000000..049c44e
--- /dev/null
+++ b/include/asm-nios/config.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
diff --git a/include/asm-nios/io.h b/include/asm-nios/io.h
index 8b78806..899682c 100644
--- a/include/asm-nios/io.h
+++ b/include/asm-nios/io.h
@@ -133,4 +133,9 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
 
 }
 
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
 #endif /* __ASM_NIOS_IO_H_ */
diff --git a/include/asm-nios2/config.h b/include/asm-nios2/config.h
new file mode 100644
index 0000000..049c44e
--- /dev/null
+++ b/include/asm-nios2/config.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h
index 2f1ec26..01d11ef 100644
--- a/include/asm-nios2/io.h
+++ b/include/asm-nios2/io.h
@@ -53,6 +53,11 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
 
 }
 
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
 extern unsigned char inb (unsigned char *port);
 extern unsigned short inw (unsigned short *port);
 extern unsigned inl (unsigned port);
diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h
index a7cf1e8..a0e88de 100644
--- a/include/asm-ppc/4xx_pcie.h
+++ b/include/asm-ppc/4xx_pcie.h
@@ -18,9 +18,9 @@
 #define DCRN_SDR0_CFGDATA	0x00f
 
 #if defined(CONFIG_440SPE)
-#define CFG_PCIE_NR_PORTS	3
+#define CONFIG_SYS_PCIE_NR_PORTS	3
 
-#define CFG_PCIE_ADDR_HIGH	0x0000000d
+#define CONFIG_SYS_PCIE_ADDR_HIGH	0x0000000d
 
 #define DCRN_PCIE0_BASE		0x100
 #define DCRN_PCIE1_BASE		0x120
@@ -32,9 +32,9 @@
 #endif
 
 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define CFG_PCIE_NR_PORTS	2
+#define CONFIG_SYS_PCIE_NR_PORTS	2
 
-#define CFG_PCIE_ADDR_HIGH	0x0000000d
+#define CONFIG_SYS_PCIE_ADDR_HIGH	0x0000000d
 
 #define DCRN_PCIE0_BASE		0x100
 #define DCRN_PCIE1_BASE		0x120
@@ -44,9 +44,9 @@
 #endif
 
 #if defined(CONFIG_405EX)
-#define CFG_PCIE_NR_PORTS	2
+#define CONFIG_SYS_PCIE_NR_PORTS	2
 
-#define CFG_PCIE_ADDR_HIGH	0x00000000
+#define CONFIG_SYS_PCIE_ADDR_HIGH	0x00000000
 
 #define	DCRN_PCIE0_BASE		0x040
 #define	DCRN_PCIE1_BASE		0x060
@@ -406,7 +406,7 @@ static inline u32 sdr_base(int port)
 		return PCIE0_SDR;
 	case 1:
 		return PCIE1_SDR;
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
 	case 2:
 		return PCIE2_SDR;
 #endif
diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h
index 9d9b971..53e8d05 100644
--- a/include/asm-ppc/cache.h
+++ b/include/asm-ppc/cache.h
@@ -12,6 +12,8 @@
 #define	L1_CACHE_SHIFT	4
 #elif defined(CONFIG_PPC64BRIDGE)
 #define L1_CACHE_SHIFT	7
+#elif defined(CONFIG_E500MC)
+#define L1_CACHE_SHIFT	6
 #else
 #define	L1_CACHE_SHIFT	5
 #endif
@@ -19,10 +21,10 @@
 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
 
 /*
- * For compatibility reasons support the CFG_CACHELINE_SIZE too
+ * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
  */
-#ifndef CFG_CACHELINE_SIZE
-#define CFG_CACHELINE_SIZE	L1_CACHE_BYTES
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE	L1_CACHE_BYTES
 #endif
 
 #define	L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
@@ -44,9 +46,10 @@ extern void clean_dcache_range(unsigned long start, unsigned long stop);
 extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
 extern void flush_dcache(void);
 extern void invalidate_dcache(void);
-#ifdef CFG_INIT_RAM_LOCK
+extern void invalidate_icache(void);
+#ifdef CONFIG_SYS_INIT_RAM_LOCK
 extern void unlock_ram_in_cache(void);
-#endif /* CFG_INIT_RAM_LOCK */
+#endif /* CONFIG_SYS_INIT_RAM_LOCK */
 #endif /* __ASSEMBLY__ */
 
 /* prep registers for L2 */
diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h
new file mode 100644
index 0000000..275a7c8
--- /dev/null
+++ b/include/asm-ppc/config.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#ifndef CONFIG_MAX_MEM_MAPPED
+#if defined(CONFIG_4xx) || defined(CONFIG_E500)
+#define CONFIG_MAX_MEM_MAPPED	((phys_size_t)2 << 30)
+#else
+#define CONFIG_MAX_MEM_MAPPED	(256 << 20)
+#endif
+#endif
+
+#endif
diff --git a/include/asm-ppc/cpm_8260.h b/include/asm-ppc/cpm_8260.h
index 2a9774a..8302404 100644
--- a/include/asm-ppc/cpm_8260.h
+++ b/include/asm-ppc/cpm_8260.h
@@ -141,16 +141,16 @@ typedef struct cpm_buf_desc {
 
 /* Parameter RAM offsets from the base.
 */
-#ifndef CFG_CPM_POST_WORD_ADDR
+#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
 #define CPM_POST_WORD_ADDR      0x80FC	/* steal a long at the end of SCC1 */
 #else
-#define CPM_POST_WORD_ADDR	CFG_CPM_POST_WORD_ADDR
+#define CPM_POST_WORD_ADDR	CONFIG_SYS_CPM_POST_WORD_ADDR
 #endif
 
-#ifndef CFG_CPM_BOOTCOUNT_ADDR
+#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
 #define CPM_BOOTCOUNT_ADDR	(CPM_POST_WORD_ADDR - 2*sizeof(ulong))
 #else
-#define CPM_BOOTCOUNT_ADDR	CFG_CPM_BOOTCOUNT_ADDR
+#define CPM_BOOTCOUNT_ADDR	CONFIG_SYS_CPM_BOOTCOUNT_ADDR
 #endif
 
 #define PROFF_SCC1		((uint)0x8000)
@@ -546,6 +546,34 @@ typedef struct scc_trans {
 
 #define BD_SCC_TX_LAST		((ushort)0x0800)
 
+/*  SCC as HDLC controller - taken from commproc.h
+ */
+typedef struct scc_hdlc {
+	sccp_t  sh_genscc;
+	/*
+	* HDLC specific parameter RAM
+	*/
+	uchar   res[4];         /* reserved */
+	ulong   sh_cmask;       /* CRC constant */
+	ulong   sh_cpres;       /* CRC preset */
+	ushort  sh_disfc;       /* discarded frame counter */
+	ushort  sh_crcec;       /* CRC error counter */
+	ushort  sh_abtsc;       /* abort sequence counter */
+	ushort  sh_nmarc;       /* nonmatching address rx cnt */
+	ushort  sh_retrc;       /* frame retransmission cnt */
+	ushort  sh_mflr;        /* maximum frame length reg */
+	ushort  sh_maxcnt;      /* maximum length counter */
+	ushort  sh_rfthr;       /* received frames threshold */
+	ushort  sh_rfcnt;       /* received frames count */
+	ushort  sh_hmask;       /* user defined frm addr mask */
+	ushort  sh_haddr1;      /* user defined frm address 1 */
+	ushort  sh_haddr2;      /* user defined frm address 2 */
+	ushort  sh_haddr3;      /* user defined frm address 3 */
+	ushort  sh_haddr4;      /* user defined frm address 4 */
+	ushort  tmp;            /* temp */
+	ushort  tmp_mb;         /* temp */
+} scc_hdlc_t;
+
 /* How about some FCCs.....
 */
 #define FCC_GFMR_DIAG_NORM	((uint)0x00000000)
diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h
index 05db0de..bfef4df 100644
--- a/include/asm-ppc/e300.h
+++ b/include/asm-ppc/e300.h
@@ -88,39 +88,4 @@
 #define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */
 #define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
 
-
-/* BAT (block address translation */
-#define BATU_BEPI_MSK		0xfffe0000
-#define BATU_BL_MSK		0x00001ffc
-
-#define BATU_BL_128K		0x00000000
-#define BATU_BL_256K		0x00000004
-#define BATU_BL_512K		0x0000000c
-#define BATU_BL_1M		0x0000001c
-#define BATU_BL_2M		0x0000003c
-#define BATU_BL_4M		0x0000007c
-#define BATU_BL_8M		0x000000fc
-#define BATU_BL_16M		0x000001fc
-#define BATU_BL_32M		0x000003fc
-#define BATU_BL_64M		0x000007fc
-#define BATU_BL_128M		0x00000ffc
-#define BATU_BL_256M		0x00001ffc
-
-#define BATU_VS			0x00000002
-#define BATU_VP			0x00000001
-
-#define BATL_BRPN_MSK		0xfffe0000
-#define BATL_WIMG_MSK		0x00000078
-
-#define BATL_WRITETHROUGH	0x00000040
-#define BATL_CACHEINHIBIT	0x00000020
-#define BATL_MEMCOHERENCE	0x00000010
-#define BATL_GUARDEDSTORAGE	0x00000008
-
-#define BATL_PP_MSK		0x00000003
-#define BATL_PP_00		0x00000000 /* No access */
-#define BATL_PP_01		0x00000001 /* Read-only */
-#define BATL_PP_10		0x00000002 /* Read-write */
-#define BATL_PP_11		0x00000003
-
 #endif	/* __E300_H__ */
diff --git a/include/asm-ppc/fsl_ddr_dimm_params.h b/include/asm-ppc/fsl_ddr_dimm_params.h
new file mode 100644
index 0000000..c794eed
--- /dev/null
+++ b/include/asm-ppc/fsl_ddr_dimm_params.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef DDR2_DIMM_PARAMS_H
+#define DDR2_DIMM_PARAMS_H
+
+/* Parameters for a DDR2 dimm computed from the SPD */
+typedef struct dimm_params_s {
+
+	/* DIMM organization parameters */
+	char mpart[19];		/* guaranteed null terminated */
+
+	unsigned int n_ranks;
+	unsigned long long rank_density;
+	unsigned long long capacity;
+	unsigned int data_width;
+	unsigned int primary_sdram_width;
+	unsigned int ec_sdram_width;
+	unsigned int registered_dimm;
+
+	/* SDRAM device parameters */
+	unsigned int n_row_addr;
+	unsigned int n_col_addr;
+	unsigned int edc_config;	/* 0 = none, 1 = parity, 2 = ECC */
+	unsigned int n_banks_per_sdram_device;
+	unsigned int burst_lengths_bitmask;	/* BL=4 bit 2, BL=8 = bit 3 */
+	unsigned int row_density;
+
+	/* used in computing base address of DIMMs */
+	unsigned long long base_address;
+
+	/* DIMM timing parameters */
+
+	/*
+	 * SDRAM clock periods
+	 * The range for these are 1000-10000 so a short should be sufficient
+	 */
+	unsigned int tCKmin_X_ps;
+	unsigned int tCKmin_X_minus_1_ps;
+	unsigned int tCKmin_X_minus_2_ps;
+	unsigned int tCKmax_ps;
+
+	/* SPD-defined CAS latencies */
+	unsigned int caslat_X;
+	unsigned int caslat_X_minus_1;
+	unsigned int caslat_X_minus_2;
+
+	unsigned int caslat_lowest_derated;	/* Derated CAS latency */
+
+	/* basic timing parameters */
+	unsigned int tRCD_ps;
+	unsigned int tRP_ps;
+	unsigned int tRAS_ps;
+
+	unsigned int tWR_ps;	/* maximum = 63750 ps */
+	unsigned int tWTR_ps;	/* maximum = 63750 ps */
+	unsigned int tRFC_ps;   /* max = 255 ns + 256 ns + .75 ns
+				       = 511750 ps */
+
+	unsigned int tRRD_ps;	/* maximum = 63750 ps */
+	unsigned int tRC_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
+
+	unsigned int refresh_rate_ps;
+
+	unsigned int tIS_ps;	/* byte 32, spd->ca_setup */
+	unsigned int tIH_ps;	/* byte 33, spd->ca_hold */
+	unsigned int tDS_ps;	/* byte 34, spd->data_setup */
+	unsigned int tDH_ps;	/* byte 35, spd->data_hold */
+	unsigned int tRTP_ps;	/* byte 38, spd->trtp */
+	unsigned int tDQSQ_max_ps;	/* byte 44, spd->tdqsq */
+	unsigned int tQHS_ps;	/* byte 45, spd->tqhs */
+} dimm_params_t;
+
+extern unsigned int ddr_compute_dimm_parameters(
+					 const generic_spd_eeprom_t *spd,
+					 dimm_params_t *pdimm,
+					 unsigned int dimm_number);
+
+#endif
diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h
index 8adde34..6e3b255 100644
--- a/include/asm-ppc/fsl_ddr_sdram.h
+++ b/include/asm-ppc/fsl_ddr_sdram.h
@@ -34,7 +34,39 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
 #elif defined(CONFIG_FSL_DDR3)
 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)	/* FIXME */
 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
+#ifndef CONFIG_FSL_SDRAM_TYPE
+#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR3
 #endif
+#endif	/* #if defined(CONFIG_FSL_DDR1) */
+
+/* define bank(chip select) interleaving mode */
+#define FSL_DDR_CS0_CS1			0x40
+#define FSL_DDR_CS2_CS3			0x20
+#define FSL_DDR_CS0_CS1_AND_CS2_CS3	(FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
+#define FSL_DDR_CS0_CS1_CS2_CS3		(FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
+
+/* define memory controller interleaving mode */
+#define FSL_DDR_CACHE_LINE_INTERLEAVING	0x0
+#define FSL_DDR_PAGE_INTERLEAVING	0x1
+#define FSL_DDR_BANK_INTERLEAVING	0x2
+#define FSL_DDR_SUPERBANK_INTERLEAVING	0x3
+
+/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
+ */
+#define SDRAM_CFG_MEM_EN		0x80000000
+#define SDRAM_CFG_SREN			0x40000000
+#define SDRAM_CFG_ECC_EN		0x20000000
+#define SDRAM_CFG_RD_EN			0x10000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR1	0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR2	0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_MASK	0x07000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
+#define SDRAM_CFG_DYN_PWR		0x00200000
+#define SDRAM_CFG_32_BE			0x00080000
+#define SDRAM_CFG_8_BE			0x00040000
+#define SDRAM_CFG_NCAP			0x00020000
+#define SDRAM_CFG_2T_EN			0x00008000
+#define SDRAM_CFG_BI			0x00000001
 
 /* Record of register values computed */
 typedef struct fsl_ddr_cfg_regs_s {
@@ -131,6 +163,10 @@ typedef struct memctl_options_s {
 	unsigned int bstopre;
 	unsigned int tCKE_clock_pulse_width_ps;	/* tCKE */
 	unsigned int tFAW_window_four_activates_ps;	/* tFAW --  FOUR_ACT */
+
+	/* Automatic self refresh */
+	unsigned int auto_self_refresh_en;
+	unsigned int sr_it;
 } memctl_options_t;
 
 extern phys_size_t fsl_ddr_sdram(void);
diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h
index 5bba08d..e06a1a6 100644
--- a/include/asm-ppc/fsl_law.h
+++ b/include/asm-ppc/fsl_law.h
@@ -42,7 +42,7 @@ enum law_trgt_if {
 #ifndef CONFIG_MPC8641
 	LAW_TRGT_IF_PCIE_1 = 0x02,
 #endif
-#ifndef CONFIG_MPC8572
+#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
 	LAW_TRGT_IF_PCIE_3 = 0x03,
 #endif
 	LAW_TRGT_IF_LBC = 0x04,
@@ -61,7 +61,7 @@ enum law_trgt_if {
 #define LAW_TRGT_IF_PCIE_1	LAW_TRGT_IF_PCI
 #endif
 
-#ifdef CONFIG_MPC8572
+#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
 #define LAW_TRGT_IF_PCIE_3	LAW_TRGT_IF_PCI
 #endif
 
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index ea49ddc..9fa0b65 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -28,6 +28,8 @@
 
 #define BR_BA				0xFFFF8000
 #define BR_BA_SHIFT			15
+#define BR_XBA				0x00006000
+#define BR_XBA_SHIFT			13
 #define BR_PS				0x00001800
 #define BR_PS_SHIFT			11
 #define BR_PS_8				0x00000800	/* Port Size 8 bit */
@@ -69,6 +71,14 @@
 #define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
 #endif
 
+/* Convert an address into the right format for the BR registers */
+#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
+#define BR_PHYS_ADDR(x)	((unsigned long)((x & 0x0ffff8000ULL) | \
+					 ((x & 0x300000000ULL) >> 19)))
+#else
+#define BR_PHYS_ADDR(x) (x & 0xffff8000)
+#endif
+
 /* OR - Option Registers
  */
 #define OR0				0x5004		/* Register offset to immr */
@@ -82,6 +92,8 @@
 
 #define OR_GPCM_AM			0xFFFF8000
 #define OR_GPCM_AM_SHIFT		15
+#define OR_GPCM_XAM			0x00006000
+#define OR_GPCM_XAM_SHIFT		13
 #define OR_GPCM_BCTLD			0x00001000
 #define OR_GPCM_BCTLD_SHIFT		12
 #define OR_GPCM_CSNT			0x00000800
@@ -124,6 +136,8 @@
 
 #define OR_FCM_AM			0xFFFF8000
 #define OR_FCM_AM_SHIFT				15
+#define OR_FCM_XAM			0x00006000
+#define OR_FCM_XAM_SHIFT		13
 #define OR_FCM_BCTLD			0x00001000
 #define OR_FCM_BCTLD_SHIFT			12
 #define OR_FCM_PGS			0x00000400
@@ -292,7 +306,10 @@
 #define LCRR_EADC_2			0x00020000
 #define LCRR_EADC_3			0x00030000
 #define LCRR_EADC_4			0x00000000
-#define LCRR_CLKDIV			0x0000000F
+/* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit
+ * should always be zero on older parts that have a four bit CLKDIV.
+ */
+#define LCRR_CLKDIV			0x0000001F
 #define LCRR_CLKDIV_SHIFT		0
 #define LCRR_CLKDIV_2			0x00000002
 #define LCRR_CLKDIV_4			0x00000004
@@ -307,4 +324,134 @@
 #define LTEDR_RAWA	0x00400000 /* Read-after-write-atomic error checking disable	*/
 #define LTEDR_CSD	0x00080000 /* Chip select error checking disable		*/
 
+/* FMR - Flash Mode Register
+ */
+#define FMR_CWTO               0x0000F000
+#define FMR_CWTO_SHIFT         12
+#define FMR_BOOT               0x00000800
+#define FMR_ECCM               0x00000100
+#define FMR_AL                 0x00000030
+#define FMR_AL_SHIFT           4
+#define FMR_OP                 0x00000003
+#define FMR_OP_SHIFT           0
+
+/* FIR - Flash Instruction Register
+ */
+#define FIR_OP0                        0xF0000000
+#define FIR_OP0_SHIFT          28
+#define FIR_OP1                        0x0F000000
+#define FIR_OP1_SHIFT          24
+#define FIR_OP2                        0x00F00000
+#define FIR_OP2_SHIFT          20
+#define FIR_OP3                        0x000F0000
+#define FIR_OP3_SHIFT          16
+#define FIR_OP4                        0x0000F000
+#define FIR_OP4_SHIFT          12
+#define FIR_OP5                        0x00000F00
+#define FIR_OP5_SHIFT          8
+#define FIR_OP6                        0x000000F0
+#define FIR_OP6_SHIFT          4
+#define FIR_OP7                        0x0000000F
+#define FIR_OP7_SHIFT          0
+#define FIR_OP_NOP             0x0 /* No operation and end of sequence */
+#define FIR_OP_CA              0x1 /* Issue current column address */
+#define FIR_OP_PA              0x2 /* Issue current block+page address */
+#define FIR_OP_UA              0x3 /* Issue user defined address */
+#define FIR_OP_CM0             0x4 /* Issue command from FCR[CMD0] */
+#define FIR_OP_CM1             0x5 /* Issue command from FCR[CMD1] */
+#define FIR_OP_CM2             0x6 /* Issue command from FCR[CMD2] */
+#define FIR_OP_CM3             0x7 /* Issue command from FCR[CMD3] */
+#define FIR_OP_WB              0x8 /* Write FBCR bytes from FCM buffer */
+#define FIR_OP_WS              0x9 /* Write 1 or 2 bytes from MDR[AS] */
+#define FIR_OP_RB              0xA /* Read FBCR bytes to FCM buffer */
+#define FIR_OP_RS              0xB /* Read 1 or 2 bytes to MDR[AS] */
+#define FIR_OP_CW0             0xC /* Wait then issue FCR[CMD0] */
+#define FIR_OP_CW1             0xD /* Wait then issue FCR[CMD1] */
+#define FIR_OP_RBW             0xE /* Wait then read FBCR bytes */
+#define FIR_OP_RSW             0xF /* Wait then read 1 or 2 bytes */
+
+/* FCR - Flash Command Register
+ */
+#define FCR_CMD0               0xFF000000
+#define FCR_CMD0_SHIFT         24
+#define FCR_CMD1               0x00FF0000
+#define FCR_CMD1_SHIFT         16
+#define FCR_CMD2               0x0000FF00
+#define FCR_CMD2_SHIFT         8
+#define FCR_CMD3               0x000000FF
+#define FCR_CMD3_SHIFT         0
+/* FBAR - Flash Block Address Register
+ */
+#define FBAR_BLK               0x00FFFFFF
+
+/* FPAR - Flash Page Address Register
+ */
+#define FPAR_SP_PI             0x00007C00
+#define FPAR_SP_PI_SHIFT       10
+#define FPAR_SP_MS             0x00000200
+#define FPAR_SP_CI             0x000001FF
+#define FPAR_SP_CI_SHIFT       0
+#define FPAR_LP_PI             0x0003F000
+#define FPAR_LP_PI_SHIFT       12
+#define FPAR_LP_MS             0x00000800
+#define FPAR_LP_CI             0x000007FF
+#define FPAR_LP_CI_SHIFT       0
+
+/* LTESR - Transfer Error Status Register
+ */
+#define LTESR_BM               0x80000000
+#define LTESR_FCT              0x40000000
+#define LTESR_PAR              0x20000000
+#define LTESR_WP               0x04000000
+#define LTESR_ATMW             0x00800000
+#define LTESR_ATMR             0x00400000
+#define LTESR_CS               0x00080000
+#define LTESR_CC               0x00000001
+
+#ifndef __ASSEMBLY__
+/*
+ * Local Bus Controller Registers.
+ */
+typedef struct lbus_bank {
+	u32 br;                 /* Base Register */
+	u32 or;                 /* Option Register */
+} lbus_bank_t;
+
+typedef struct fsl_lbus {
+	lbus_bank_t bank[8];
+	u8 res0[0x28];
+	u32 mar;                /* UPM Address Register */
+	u8 res1[0x4];
+	u32 mamr;               /* UPMA Mode Register */
+	u32 mbmr;               /* UPMB Mode Register */
+	u32 mcmr;               /* UPMC Mode Register */
+	u8 res2[0x8];
+	u32 mrtpr;              /* Memory Refresh Timer Prescaler Register */
+	u32 mdr;                /* UPM Data Register */
+	u8 res3[0x4];
+	u32 lsor;               /* Special Operation Initiation Register */
+	u32 lsdmr;              /* SDRAM Mode Register */
+	u8 res4[0x8];
+	u32 lurt;               /* UPM Refresh Timer */
+	u32 lsrt;               /* SDRAM Refresh Timer */
+	u8 res5[0x8];
+	u32 ltesr;              /* Transfer Error Status Register */
+	u32 ltedr;              /* Transfer Error Disable Register */
+	u32 lteir;              /* Transfer Error Interrupt Register */
+	u32 lteatr;             /* Transfer Error Attributes Register */
+	u32 ltear;               /* Transfer Error Address Register */
+	u8 res6[0xC];
+	u32 lbcr;               /* Configuration Register */
+	u32 lcrr;               /* Clock Ratio Register */
+	u8 res7[0x8];
+	u32 fmr;                /* Flash Mode Register */
+	u32 fir;                /* Flash Instruction Register */
+	u32 fcr;                /* Flash Command Register */
+	u32 fbar;               /* Flash Block Addr Register */
+	u32 fpar;               /* Flash Page Addr Register */
+	u32 fbcr;               /* Flash Byte Count Register */
+	u8 res8[0xF08];
+} fsl_lbus_t;
+#endif /* __ASSEMBLY__ */
+
 #endif /* __ASM_PPC_FSL_LBC_H */
diff --git a/include/asm-ppc/fsl_serdes.h b/include/asm-ppc/fsl_serdes.h
index 733f919..6da4b6f 100644
--- a/include/asm-ppc/fsl_serdes.h
+++ b/include/asm-ppc/fsl_serdes.h
@@ -3,9 +3,9 @@
 
 #include <config.h>
 
-#define FSL_SERDES_CLK_100		0
-#define FSL_SERDES_CLK_125		1
-#define FSL_SERDES_CLK_150		3
+#define FSL_SERDES_CLK_100		(0 << 28)
+#define FSL_SERDES_CLK_125		(1 << 28)
+#define FSL_SERDES_CLK_150		(3 << 28)
 #define FSL_SERDES_PROTO_SATA		0
 #define FSL_SERDES_PROTO_PEX		1
 #define FSL_SERDES_PROTO_PEX_X2		2
@@ -13,9 +13,9 @@
 #define FSL_SERDES_VDD_1V		1
 
 #ifdef CONFIG_FSL_SERDES
-extern void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd);
+extern void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd);
 #else
-static void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd) {}
+static void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) {}
 #endif /* CONFIG_FSL_SERDES */
 
 #endif /* __FSL_SERDES_H */
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 4331a15..e5a3b2c 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -33,7 +33,7 @@
  * global variables during system initialization (until we have set
  * up the memory controller so that we can use RAM).
  *
- * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
  */
 
 typedef	struct	global_data {
@@ -75,7 +75,7 @@ typedef	struct	global_data {
 	u32 lbiu_clk;
 	u32 lclk_clk;
 	u32 pci_clk;
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC831X)
 	u32 pciexp1_clk;
 	u32 pciexp2_clk;
 #endif
@@ -89,6 +89,9 @@ typedef	struct	global_data {
 #if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8536)
 	u32 sdhc_clk;
 #endif
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+	u32 lbc_clk;
+#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
 #if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
 	u32 i2c1_clk;
 	u32 i2c2_clk;
@@ -129,14 +132,14 @@ typedef	struct	global_data {
 	unsigned long	env_addr;	/* Address  of Environment struct	*/
 	unsigned long	env_valid;	/* Checksum of Environment valid?	*/
 	unsigned long	have_console;	/* serial_init() was called		*/
-#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_CPM2)
+#if defined(CONFIG_SYS_ALLOC_DPRAM) || defined(CONFIG_CPM2)
 	unsigned int	dp_alloc_base;
 	unsigned int	dp_alloc_top;
 #endif
 #if defined(CONFIG_4xx)
 	u32  uart_clk;
 #endif /* CONFIG_4xx */
-#if defined(CFG_GT_6426x)
+#if defined(CONFIG_SYS_GT_6426x)
 	unsigned int	mirror_hack[16];
 #endif
 #if defined(CONFIG_A3000)	|| \
diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h
index cd90945..8087869 100644
--- a/include/asm-ppc/immap_512x.h
+++ b/include/asm-ppc/immap_512x.h
@@ -415,7 +415,25 @@ typedef struct ioctrl512x {
  * IIM
  */
 typedef struct iim512x {
-	u8 fixme[0x1000];
+	u32 stat;		/* IIM status register */
+	u32 statm;		/* IIM status IRQ mask */
+	u32 err;		/* IIM errors register */
+	u32 emask;		/* IIM error IRQ mask  */
+	u32 fctl;		/* IIM fuse control register */
+	u32 ua;			/* IIM upper address register */
+	u32 la;			/* IIM lower address register */
+	u32 sdat;		/* IIM explicit sense data */
+	u8 res0[0x08];
+	u32 prg_p;		/* IIM program protection register */
+	u8 res1[0x10];
+	u32 divide;		/* IIM divide factor register */
+	u8 res2[0x7c0];
+	u32 fbac0;		/* IIM fuse bank 0 prot (for Freescale use) */
+	u32 fb0w0[0x1f];	/* IIM fuse bank 0 data (for Freescale use) */
+	u8 res3[0x380];
+	u32 fbac1;		/* IIM fuse bank 1 protection */
+	u32 fb1w1[0x01f];	/* IIM fuse bank 1 data */
+	u8 res4[0x380];
 } iim512x_t;
 
 /*
@@ -451,7 +469,34 @@ typedef struct lpc512x {
  * PATA
  */
 typedef struct pata512x {
-	u8 fixme[0x100];
+	/* LOCAL Registers */
+	u32 pata_time1;		/* Time register 1: PIO and tx timing parameter */
+	u32 pata_time2;		/* Time register 2: PIO timing parameter */
+	u32 pata_time3;		/* Time register 3: PIO and MDMA timing parameter */
+	u32 pata_time4;		/* Time register 4: MDMA and UDMA timing parameter */
+	u32 pata_time5;		/* Time register 5: UDMA timing parameter */
+	u32 pata_time6;		/* Time register 6: UDMA timing parameter */
+	u32 pata_fifo_data32;   /* 32bit wide dataport to/from FIFO */
+	u32 pata_fifo_data16;   /* 16bit wide dataport to/from FIFO */
+	u32 pata_fifo_fill;	/* FIFO filling in halfwords (READONLY)*/
+	u32 pata_ata_control;   /* ATA Interface control register */
+	u32 pata_irq_pending;   /* Interrupt pending register (READONLY) */
+	u32 pata_irq_enable;	/* Interrupt enable register */
+	u32 pata_irq_clear;	/* Interrupt clear register (WRITEONLY)*/
+	u32 pata_fifo_alarm;	/* fifo alarm threshold */
+	u32 res1[0x1A];
+	/* DRIVE Registers */
+	u32 pata_drive_data;	/* drive data register*/
+	u32 pata_drive_features;/* drive features register */
+	u32 pata_drive_sectcnt; /* drive sector count register */
+	u32 pata_drive_sectnum; /* drive sector number register */
+	u32 pata_drive_cyllow;  /* drive cylinder low register */
+	u32 pata_drive_cylhigh; /* drive cylinder high register */
+	u32 pata_drive_dev_head;/* drive device head register */
+	u32 pata_drive_command; /* write = drive command, read = drive status reg */
+	u32 res2[0x06];
+	u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */
+	u32 res3[0x09];
 } pata512x_t;
 
 /*
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index ff18303..7b847f8 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -31,6 +31,7 @@
 #include <asm/types.h>
 #include <asm/fsl_i2c.h>
 #include <asm/mpc8xxx_spi.h>
+#include <asm/fsl_lbc.h>
 
 /*
  * Local Access Window
@@ -51,23 +52,28 @@ typedef struct sysconf83xx {
 	law83xx_t lblaw[4];	/* LBIU local access window */
 	u8 res2[0x20];
 	law83xx_t pcilaw[2];	/* PCI local access window */
-	u8 res3[0x30];
+	u8 res3[0x10];
+	law83xx_t pcielaw[2];	/* PCI Express local access window */
+	u8 res4[0x10];
 	law83xx_t ddrlaw[2];	/* DDR local access window */
-	u8 res4[0x50];
+	u8 res5[0x50];
 	u32 sgprl;		/* System General Purpose Register Low */
 	u32 sgprh;		/* System General Purpose Register High */
 	u32 spridr;		/* System Part and Revision ID Register */
-	u8 res5[0x04];
+	u8 res6[0x04];
 	u32 spcr;		/* System Priority Configuration Register */
 	u32 sicrl;		/* System I/O Configuration Register Low */
 	u32 sicrh;		/* System I/O Configuration Register High */
-	u8 res6[0x04];
+	u8 res7[0x04];
 	u32 sidcr0;		/* System I/O Delay Configuration Register 0 */
 	u32 sidcr1;		/* System I/O Delay Configuration Register 1 */
 	u32 ddrcdr;		/* DDR Control Driver Register */
 	u32 ddrdsr;		/* DDR Debug Status Register */
 	u32 obir;		/* Output Buffer Impedance Register */
-	u8 res7[0xCC];
+	u8 res8[0xC];
+	u32 pecr1;		/* PCI Express control register 1 */
+	u32 pecr2;		/* PCI Express control register 2 */
+	u8 res9[0xB8];
 } sysconf83xx_t;
 
 /*
@@ -343,50 +349,6 @@ typedef struct duart83xx {
 } duart83xx_t;
 
 /*
- * Local Bus Controller Registers
- */
-typedef struct lbus_bank {
-	u32 br;			/* Base Register */
-	u32 or;			/* Option Register */
-} lbus_bank_t;
-
-typedef struct lbus83xx {
-	lbus_bank_t bank[8];
-	u8 res0[0x28];
-	u32 mar;		/* UPM Address Register */
-	u8 res1[0x4];
-	u32 mamr;		/* UPMA Mode Register */
-	u32 mbmr;		/* UPMB Mode Register */
-	u32 mcmr;		/* UPMC Mode Register */
-	u8 res2[0x8];
-	u32 mrtpr;		/* Memory Refresh Timer Prescaler Register */
-	u32 mdr;		/* UPM Data Register */
-	u8 res3[0x4];
-	u32 lsor;		/* Special Operation Initiation Register */
-	u32 lsdmr;		/* SDRAM Mode Register */
-	u8 res4[0x8];
-	u32 lurt;		/* UPM Refresh Timer */
-	u32 lsrt;		/* SDRAM Refresh Timer */
-	u8 res5[0x8];
-	u32 ltesr;		/* Transfer Error Status Register */
-	u32 ltedr;		/* Transfer Error Disable Register */
-	u32 lteir;		/* Transfer Error Interrupt Register */
-	u32 lteatr;		/* Transfer Error Attributes Register */
-	u32 ltear;		/* Transfer Error Address Register */
-	u8 res6[0xC];
-	u32 lbcr;		/* Configuration Register */
-	u32 lcrr;		/* Clock Ratio Register */
-	u8 res7[0x8];
-	u32 fmr;		/* Flash Mode Register */
-	u32 fir;		/* Flash Instruction Register */
-	u32 fcr;		/* Flash Command Register */
-	u32 fbar;		/* Flash Block Addr Register */
-	u32 fpar;		/* Flash Page Addr Register */
-	u32 fbcr;		/* Flash Byte Count Register */
-	u8 res8[0xF08];
-} lbus83xx_t;
-
-/*
  * DMA/Messaging Unit
  */
 typedef struct dma83xx {
@@ -546,8 +508,110 @@ typedef struct security83xx {
 /*
  *  PCI Express
  */
+struct pex_inbound_window {
+	u32 ar;
+	u32 tar;
+	u32 barl;
+	u32 barh;
+};
+
+struct pex_outbound_window {
+	u32 ar;
+	u32 bar;
+	u32 tarl;
+	u32 tarh;
+};
+
+struct pex_csb_bridge {
+	u32 pex_csb_ver;
+	u32 pex_csb_cab;
+	u32 pex_csb_ctrl;
+	u8 res0[8];
+	u32 pex_dms_dstmr;
+	u8 res1[4];
+	u32 pex_cbs_stat;
+	u8 res2[0x20];
+	u32 pex_csb_obctrl;
+	u32 pex_csb_obstat;
+	u8 res3[0x98];
+	u32 pex_csb_ibctrl;
+	u32 pex_csb_ibstat;
+	u8 res4[0xb8];
+	u32 pex_wdma_ctrl;
+	u32 pex_wdma_addr;
+	u32 pex_wdma_stat;
+	u8 res5[0x94];
+	u32 pex_rdma_ctrl;
+	u32 pex_rdma_addr;
+	u32 pex_rdma_stat;
+	u8 res6[0xd4];
+	u32 pex_ombcr;
+	u32 pex_ombdr;
+	u8 res7[0x38];
+	u32 pex_imbcr;
+	u32 pex_imbdr;
+	u8 res8[0x38];
+	u32 pex_int_enb;
+	u32 pex_int_stat;
+	u32 pex_int_apio_vec1;
+	u32 pex_int_apio_vec2;
+	u8 res9[0x10];
+	u32 pex_int_ppio_vec1;
+	u32 pex_int_ppio_vec2;
+	u32 pex_int_wdma_vec1;
+	u32 pex_int_wdma_vec2;
+	u32 pex_int_rdma_vec1;
+	u32 pex_int_rdma_vec2;
+	u32 pex_int_misc_vec;
+	u8 res10[4];
+	u32 pex_int_axi_pio_enb;
+	u32 pex_int_axi_wdma_enb;
+	u32 pex_int_axi_rdma_enb;
+	u32 pex_int_axi_misc_enb;
+	u32 pex_int_axi_pio_stat;
+	u32 pex_int_axi_wdma_stat;
+	u32 pex_int_axi_rdma_stat;
+	u32 pex_int_axi_misc_stat;
+	u8 res11[0xa0];
+	struct pex_outbound_window pex_outbound_win[4];
+	u8 res12[0x100];
+	u32 pex_epiwtar0;
+	u32 pex_epiwtar1;
+	u32 pex_epiwtar2;
+	u32 pex_epiwtar3;
+	u8 res13[0x70];
+	struct pex_inbound_window pex_inbound_win[4];
+};
+
 typedef struct pex83xx {
-	u8 fixme[0x1000];
+	u8 pex_cfg_header[0x404];
+	u32 pex_ltssm_stat;
+	u8 res0[0x30];
+	u32 pex_ack_replay_timeout;
+	u8 res1[4];
+	u32 pex_gclk_ratio;
+	u8 res2[0xc];
+	u32 pex_pm_timer;
+	u32 pex_pme_timeout;
+	u8 res3[4];
+	u32 pex_aspm_req_timer;
+	u8 res4[0x18];
+	u32 pex_ssvid_update;
+	u8 res5[0x34];
+	u32 pex_cfg_ready;
+	u8 res6[0x24];
+	u32 pex_bar_sizel;
+	u8 res7[4];
+	u32 pex_bar_sel;
+	u8 res8[0x20];
+	u32 pex_bar_pf;
+	u8 res9[0x88];
+	u32 pex_pme_to_ack_tor;
+	u8 res10[0xc];
+	u32 pex_ss_intr_mask;
+	u8 res11[0x25c];
+	struct pex_csb_bridge bridge;
+	u8 res12[0x160];
 } pex83xx_t;
 
 /*
@@ -614,7 +678,7 @@ typedef struct immap {
 	u8			res2[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res3[0x900];
-	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
 	u8			res4[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */
@@ -648,7 +712,7 @@ typedef struct immap {
 	u8			res1[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res2[0x900];
-	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
 	u8			res3[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */
@@ -683,7 +747,7 @@ typedef struct immap {
 	u8			res1[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res2[0x900];
-	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
 	u8			res3[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */
@@ -728,7 +792,7 @@ typedef struct immap {
 	u8			res1[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res2[0x900];
-	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
 	u8			res3[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */
@@ -778,7 +842,7 @@ typedef struct immap {
 	u8			res4[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res5[0x900];
-	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
 	u8			res6[0x2000];
 	dma83xx_t		dma;		/* DMA */
 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
@@ -817,7 +881,7 @@ typedef struct immap {
 	u8			res3[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res4[0x900];
-	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
 	u8			res5[0x2000];
 	dma83xx_t		dma;		/* DMA */
 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
@@ -831,4 +895,6 @@ typedef struct immap {
 } immap_t;
 #endif
 
+#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET	(0x2e000)
+#define CONFIG_SYS_MPC83xx_ESDHC_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
 #endif				/* __IMMAP_83xx__ */
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 559d6ea..7b97fe0 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -13,6 +13,7 @@
 
 #include <asm/types.h>
 #include <asm/fsl_i2c.h>
+#include <asm/fsl_lbc.h>
 
 /*
  * Local-Access Registers and ECM Registers(0x0000-0x2000)
@@ -57,7 +58,23 @@ typedef struct ccsr_local_ecm {
 	uint	lawbar7;	/* 0xce8 - Local Access Window 7 Base Address Register */
 	char	res19[4];
 	uint	lawar7;		/* 0xcf0 - Local Access Window 7 Attributes Register */
-	char	res20[780];	/* XXX: LAW 8, LAW9 for 8572 */
+	char	res19_8a[20];
+	uint	lawbar8;	/* 0xd08 - Local Access Window 8 Base Address Register */
+	char	res19_8b[4];
+	uint	lawar8;		/* 0xd10 - Local Access Window 8 Attributes Register */
+	char	res19_9a[20];
+	uint	lawbar9;	/* 0xd28 - Local Access Window 9 Base Address Register */
+	char	res19_9b[4];
+	uint	lawar9;		/* 0xd30 - Local Access Window 9 Attributes Register */
+	char	res19_10a[20];
+	uint	lawbar10;	/* 0xd48 - Local Access Window 10 Base Address Register */
+	char	res19_10b[4];
+	uint	lawar10;	/* 0xd50 - Local Access Window 10 Attributes Register */
+	char	res19_11a[20];
+	uint	lawbar11;	/* 0xd68 - Local Access Window 11 Base Address Register */
+	char	res19_11b[4];
+	uint	lawar11;	/* 0xd70 - Local Access Window 11 Attributes Register */
+	char	res20[652];
 	uint	eebacr;		/* 0x1000 - ECM CCB Address Configuration Register */
 	char	res21[12];
 	uint	eebpcr;		/* 0x1010 - ECM CCB Port Configuration Register */
@@ -118,7 +135,12 @@ typedef struct ccsr_ddr {
 	uint	ddr_sr_cntr;		/* 0x217C - DDR self refresh counter */
 	uint	ddr_sdram_rcw_1;	/* 0x2180 - DDR Register Control Words 1 */
 	uint	ddr_sdram_rcw_2;	/* 0x2184 - DDR Register Control Words 2 */
-	char	res8_1b[2672];
+	char	res8_1b[2456];
+	uint	ddr_dsr1;		/* 0x2B20 - DDR Debug Status Register 1	*/
+	uint	ddr_dsr2;		/* 0x2B24 - DDR Debug Status Register 2	*/
+	uint	ddr_cdr1;		/* 0x2B28 - DDR Control Driver Register 1 */
+	uint	ddr_cdr2;		/* 0x2B2C - DDR Control Driver Register 2 */
+	char	res8_1c[200];
 	uint	ip_rev1;		/* 0x2BF8 - DDR IP Block Revision 1 */
 	uint	ip_rev2;		/* 0x2BFC - DDR IP Block Revision 2 */
 	char	res8_2[512];
@@ -1552,6 +1574,13 @@ typedef struct par_io {
  */
 typedef struct ccsr_gur {
 	uint	porpllsr;	/* 0xe0000 - POR PLL ratio status register */
+#ifdef CONFIG_MPC8536
+#define MPC85xx_PORPLLSR_DDR_RATIO	0x3e000000
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	25
+#else
+#define MPC85xx_PORPLLSR_DDR_RATIO	0x00003e00
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	9
+#endif
 	uint	porbmsr;	/* 0xe0004 - POR boot mode status register */
 #define MPC85xx_PORBMSR_HA		0x00070000
 	uint	porimpscr;	/* 0xe0008 - POR I/O impedance status and control register */
@@ -1561,7 +1590,8 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_SGMII3_DIS	0x08000000
 #define MPC85xx_PORDEVSR_SGMII4_DIS	0x04000000
 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL   0x38000000
-#define MPC85xx_PORDEVSR_IO_SEL		0x00380000
+#define MPC85xx_PORDEVSR_PCI1		0x00800000
+#define MPC85xx_PORDEVSR_IO_SEL		0x00780000
 #define MPC85xx_PORDEVSR_PCI2_ARB	0x00040000
 #define MPC85xx_PORDEVSR_PCI1_ARB	0x00020000
 #define MPC85xx_PORDEVSR_PCI1_PCI32	0x00010000
@@ -1572,7 +1602,8 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_RIO_DEV_ID	0x00000007
 	uint	pordbgmsr;	/* 0xe0010 - POR debug mode status register */
 	uint	pordevsr2;	/* 0xe0014 - POR I/O device status regsiter 2 */
-#define MPC85xx_PORDEVSR2_SEC_CFG	0x00000020
+/* The 8544 RM says this is bit 26, but it's really bit 24 */
+#define MPC85xx_PORDEVSR2_SEC_CFG	0x00000080
 	char	res1[8];
 	uint	gpporcr;	/* 0xe0020 - General-purpose POR configuration register */
 	char	res2[12];
@@ -1583,6 +1614,9 @@ typedef struct ccsr_gur {
 	uint	gpindr;		/* 0xe0050 - General-purpose input data register */
 	char	res5[12];
 	uint	pmuxcr;		/* 0xe0060 - Alternate function signal multiplex control */
+#define MPC85xx_PMUXCR_SD_DATA		0x80000000
+#define MPC85xx_PMUXCR_SDHC_CD		0x40000000
+#define MPC85xx_PMUXCR_SDHC_WP		0x20000000
 	char	res6[12];
 	uint	devdisr;	/* 0xe0070 - Device disable control */
 #define MPC85xx_DEVDISR_PCI1		0x80000000
@@ -1638,39 +1672,37 @@ typedef struct ccsr_gur {
 	char	res15[61648];	/* 0xe0f30 to 0xefffff */
 } ccsr_gur_t;
 
-#define PORDEVSR_PCI	(0x00800000)	/* PCI Mode */
-
-#define CFG_MPC85xx_GUTS_OFFSET	(0xE0000)
-#define CFG_MPC85xx_GUTS_ADDR	(CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET)
-#define CFG_MPC85xx_ECM_OFFSET	(0x0000)
-#define CFG_MPC85xx_ECM_ADDR	(CFG_IMMR + CFG_MPC85xx_ECM_OFFSET)
-#define CFG_MPC85xx_DDR_OFFSET	(0x2000)
-#define CFG_MPC85xx_DDR_ADDR	(CFG_IMMR + CFG_MPC85xx_DDR_OFFSET)
-#define CFG_MPC85xx_DDR2_OFFSET	(0x6000)
-#define CFG_MPC85xx_DDR2_ADDR	(CFG_IMMR + CFG_MPC85xx_DDR2_OFFSET)
-#define CFG_MPC85xx_LBC_OFFSET	(0x5000)
-#define CFG_MPC85xx_LBC_ADDR	(CFG_IMMR + CFG_MPC85xx_LBC_OFFSET)
-#define CFG_MPC85xx_PCIX_OFFSET	(0x8000)
-#define CFG_MPC85xx_PCIX_ADDR	(CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET)
-#define CFG_MPC85xx_PCIX2_OFFSET	(0x9000)
-#define CFG_MPC85xx_PCIX2_ADDR	(CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET)
-#define CFG_MPC85xx_SATA1_OFFSET	(0x18000)
-#define CFG_MPC85xx_SATA1_ADDR	(CFG_IMMR + CFG_MPC85xx_SATA1_OFFSET)
-#define CFG_MPC85xx_SATA2_OFFSET	(0x19000)
-#define CFG_MPC85xx_SATA2_ADDR	(CFG_IMMR + CFG_MPC85xx_SATA2_OFFSET)
-#define CFG_MPC85xx_L2_OFFSET	(0x20000)
-#define CFG_MPC85xx_L2_ADDR	(CFG_IMMR + CFG_MPC85xx_L2_OFFSET)
-#define CFG_MPC85xx_DMA_OFFSET	(0x21000)
-#define CFG_MPC85xx_DMA_ADDR	(CFG_IMMR + CFG_MPC85xx_DMA_OFFSET)
-#define CFG_MPC85xx_ESDHC_OFFSET	(0x2e000)
-#define CFG_MPC85xx_ESDHC_ADDR	(CFG_IMMR + CFG_MPC85xx_ESDHC_OFFSET)
-#define CFG_MPC85xx_PIC_OFFSET	(0x40000)
-#define CFG_MPC85xx_PIC_ADDR	(CFG_IMMR + CFG_MPC85xx_PIC_OFFSET)
-#define CFG_MPC85xx_CPM_OFFSET	(0x80000)
-#define CFG_MPC85xx_CPM_ADDR	(CFG_IMMR + CFG_MPC85xx_CPM_OFFSET)
-#define CFG_MPC85xx_SERDES1_OFFSET	(0xE3000)
-#define CFG_MPC85xx_SERDES1_ADDR	(CFG_IMMR + CFG_MPC85xx_SERDES2_OFFSET)
-#define CFG_MPC85xx_SERDES2_OFFSET	(0xE3100)
-#define CFG_MPC85xx_SERDES2_ADDR	(CFG_IMMR + CFG_MPC85xx_SERDES2_OFFSET)
+#define CONFIG_SYS_MPC85xx_GUTS_OFFSET	(0xE0000)
+#define CONFIG_SYS_MPC85xx_GUTS_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
+#define CONFIG_SYS_MPC85xx_ECM_OFFSET	(0x0000)
+#define CONFIG_SYS_MPC85xx_ECM_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
+#define CONFIG_SYS_MPC85xx_DDR_OFFSET	(0x2000)
+#define CONFIG_SYS_MPC85xx_DDR_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
+#define CONFIG_SYS_MPC85xx_DDR2_OFFSET	(0x6000)
+#define CONFIG_SYS_MPC85xx_DDR2_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
+#define CONFIG_SYS_MPC85xx_LBC_OFFSET	(0x5000)
+#define CONFIG_SYS_MPC85xx_LBC_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
+#define CONFIG_SYS_MPC85xx_PCIX_OFFSET	(0x8000)
+#define CONFIG_SYS_MPC85xx_PCIX_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
+#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET	(0x9000)
+#define CONFIG_SYS_MPC85xx_PCIX2_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
+#define CONFIG_SYS_MPC85xx_SATA1_OFFSET	(0x18000)
+#define CONFIG_SYS_MPC85xx_SATA1_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
+#define CONFIG_SYS_MPC85xx_SATA2_OFFSET	(0x19000)
+#define CONFIG_SYS_MPC85xx_SATA2_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
+#define CONFIG_SYS_MPC85xx_L2_OFFSET	(0x20000)
+#define CONFIG_SYS_MPC85xx_L2_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
+#define CONFIG_SYS_MPC85xx_DMA_OFFSET	(0x21000)
+#define CONFIG_SYS_MPC85xx_DMA_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
+#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET	(0x2e000)
+#define CONFIG_SYS_MPC85xx_ESDHC_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
+#define CONFIG_SYS_MPC85xx_PIC_OFFSET	(0x40000)
+#define CONFIG_SYS_MPC85xx_PIC_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
+#define CONFIG_SYS_MPC85xx_CPM_OFFSET	(0x80000)
+#define CONFIG_SYS_MPC85xx_CPM_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
+#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET	(0xE3000)
+#define CONFIG_SYS_MPC85xx_SERDES1_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
+#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET	(0xE3100)
+#define CONFIG_SYS_MPC85xx_SERDES2_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
 
 #endif /*__IMMAP_85xx__*/
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index 03a25c7..470385f 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -1289,22 +1289,35 @@ typedef struct ccsr_gur {
 	uint	powmgtcsr;	/* 0xe0080 - Power management status and control register */
 	char	res8[12];
 	uint	mcpsumr;	/* 0xe0090 - Machine check summary register */
-	char	res9[12];
+	uint	rstrscr;	/* 0xe0094 - Reset request status and control register */
+	char	res9[8];
 	uint	pvr;		/* 0xe00a0 - Processor version register */
 	uint	svr;		/* 0xe00a4 - System version register */
-	char	res10a[1880];
+	char	res10a[8];
+	uint	rstcr;		/* 0xe00b0 - Reset control register */
+#define MPC86xx_RSTCR_HRST_REQ	0x00000002
+	char	res10b[1868];
 	uint	clkdvdr;	/* 0xe0800 - Clock Divide register */
-	char	res10b[1532];
+	char	res10c[796];
+	uint	ddr1clkdr;	/* 0xe0b20 - DDRC1 Clock Disable register */
+	char	res10d[4];
+	uint	ddr2clkdr;	/* 0xe0b28 - DDRC2 Clock Disable register */
+	char	res10e[724];
 	uint	clkocr;		/* 0xe0e00 - Clock out select register */
 	char	res11[12];
 	uint	ddrdllcr;	/* 0xe0e10 - DDR DLL control register */
 	char	res12[12];
 	uint	lbcdllcr;	/* 0xe0e20 - LBC DLL control register */
-	int	res13[57];
-	uint    lynxdcr1;        /* 0xe0f08 - Lynx debug control register 1*/
-	int     res14[6];
-	uint    ddrioovcr;      /* 0xe0f24 - DDR IO Overdrive Control register */
-	char	res15[216];
+	char	res13a[224];
+	uint	srds1cr0;	/* 0xe0f04 - SerDes1 control register 0 */
+	char	res13b[4];
+	uint	srds1cr1;	/* 0xe0f08 - SerDes1 control register 1 */
+	char	res14[24];
+	uint	ddrioovcr;	/* 0xe0f24 - DDR IO Overdrive Control register */
+	char	res15a[24];
+	uint	srds2cr0;	/* 0xe0f40 - SerDes2 control register 0 */
+	uint	srds2cr1;	/* 0xe0f44 - SerDes2 control register 1 */
+	char	res16[184];
 } ccsr_gur_t;
 
 /*
@@ -1348,9 +1361,9 @@ typedef struct immap {
 
 extern immap_t  *immr;
 
-#define CFG_MPC86xx_DDR_OFFSET	(0x2000)
-#define CFG_MPC86xx_DDR_ADDR	(CFG_IMMR + CFG_MPC86xx_DDR_OFFSET)
-#define CFG_MPC86xx_DDR2_OFFSET	(0x6000)
-#define CFG_MPC86xx_DDR2_ADDR	(CFG_IMMR + CFG_MPC86xx_DDR2_OFFSET)
+#define CONFIG_SYS_MPC86xx_DDR_OFFSET	(0x2000)
+#define CONFIG_SYS_MPC86xx_DDR_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET)
+#define CONFIG_SYS_MPC86xx_DDR2_OFFSET	(0x6000)
+#define CONFIG_SYS_MPC86xx_DDR2_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET)
 
 #endif /*__IMMAP_86xx__*/
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index c349681..4ddad26 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -10,6 +10,10 @@
 #include <linux/config.h>
 #include <asm/byteorder.h>
 
+#ifdef CONFIG_ADDR_MAP
+#include <addr_map.h>
+#endif
+
 #define SIO_CONFIG_RA   0x398
 #define SIO_CONFIG_RD   0x399
 
@@ -287,7 +291,11 @@ extern inline void out_be32(volatile unsigned __iomem *addr, int val)
 static inline void *
 map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
 {
+#ifdef CONFIG_ADDR_MAP
+	return (void *)(addrmap_phys_to_virt(paddr));
+#else
 	return (void *)((unsigned long)paddr);
+#endif
 }
 
 /*
@@ -298,4 +306,13 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
 
 }
 
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+#ifdef CONFIG_ADDR_MAP
+	return addrmap_virt_to_phys(vaddr);
+#else
+	return (phys_addr_t)((unsigned long)vaddr);
+#endif
+}
+
 #endif
diff --git a/include/asm-ppc/iopin_8260.h b/include/asm-ppc/iopin_8260.h
index 21ed8c2..619f3a8 100644
--- a/include/asm-ppc/iopin_8260.h
+++ b/include/asm-ppc/iopin_8260.h
@@ -26,140 +26,140 @@ iopin_t;
 extern __inline__ void
 iopin_set_high(iopin_t *iopin)
 {
-    volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata;
+    volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
     datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
 extern __inline__ void
 iopin_set_low(iopin_t *iopin)
 {
-    volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata;
+    volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
     datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
 extern __inline__ uint
 iopin_is_high(iopin_t *iopin)
 {
-    volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata;
+    volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
     return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
 extern __inline__ uint
 iopin_is_low(iopin_t *iopin)
 {
-    volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata;
+    volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
     return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
 }
 
 extern __inline__ void
 iopin_set_out(iopin_t *iopin)
 {
-    volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira;
+    volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
     dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
 extern __inline__ void
 iopin_set_in(iopin_t *iopin)
 {
-    volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira;
+    volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
     dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
 extern __inline__ uint
 iopin_is_out(iopin_t *iopin)
 {
-    volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira;
+    volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
     return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
 extern __inline__ uint
 iopin_is_in(iopin_t *iopin)
 {
-    volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira;
+    volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
     return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
 }
 
 extern __inline__ void
 iopin_set_odr(iopin_t *iopin)
 {
-    volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra;
+    volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
     odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
 extern __inline__ void
 iopin_set_act(iopin_t *iopin)
 {
-    volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra;
+    volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
     odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
 extern __inline__ uint
 iopin_is_odr(iopin_t *iopin)
 {
-    volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra;
+    volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
     return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
 extern __inline__ uint
 iopin_is_act(iopin_t *iopin)
 {
-    volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra;
+    volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
     return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
 }
 
 extern __inline__ void
 iopin_set_ded(iopin_t *iopin)
 {
-    volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara;
+    volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
     parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
 extern __inline__ void
 iopin_set_gen(iopin_t *iopin)
 {
-    volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara;
+    volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
     parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
 extern __inline__ uint
 iopin_is_ded(iopin_t *iopin)
 {
-    volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara;
+    volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
     return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
 extern __inline__ uint
 iopin_is_gen(iopin_t *iopin)
 {
-    volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara;
+    volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
     return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
 }
 
 extern __inline__ void
 iopin_set_opt2(iopin_t *iopin)
 {
-    volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora;
+    volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
     sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
 extern __inline__ void
 iopin_set_opt1(iopin_t *iopin)
 {
-    volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora;
+    volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
     sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
 extern __inline__ uint
 iopin_is_opt2(iopin_t *iopin)
 {
-    volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora;
+    volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
     return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
 extern __inline__ uint
 iopin_is_opt1(iopin_t *iopin)
 {
-    volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora;
+    volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
     return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
 }
 
diff --git a/include/asm-ppc/iopin_85xx.h b/include/asm-ppc/iopin_85xx.h
index daddb55..0f07ba3 100644
--- a/include/asm-ppc/iopin_85xx.h
+++ b/include/asm-ppc/iopin_85xx.h
@@ -23,121 +23,121 @@ typedef struct {
 
 extern __inline__ void iopin_set_high (iopin_t * iopin)
 {
-	volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
+	volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
 	datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
 extern __inline__ void iopin_set_low (iopin_t * iopin)
 {
-	volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
+	volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
 	datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
 extern __inline__ uint iopin_is_high (iopin_t * iopin)
 {
-	volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
+	volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
 	return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
 extern __inline__ uint iopin_is_low (iopin_t * iopin)
 {
-	volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
+	volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
 	return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
 }
 
 extern __inline__ void iopin_set_out (iopin_t * iopin)
 {
-	volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
+	volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
 	dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
 extern __inline__ void iopin_set_in (iopin_t * iopin)
 {
-	volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
+	volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
 	dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
 extern __inline__ uint iopin_is_out (iopin_t * iopin)
 {
-	volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
+	volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
 	return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
 extern __inline__ uint iopin_is_in (iopin_t * iopin)
 {
-	volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
+	volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
 	return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
 }
 
 extern __inline__ void iopin_set_odr (iopin_t * iopin)
 {
-	volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
+	volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
 	odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
 extern __inline__ void iopin_set_act (iopin_t * iopin)
 {
-	volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
+	volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
 	odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
 extern __inline__ uint iopin_is_odr (iopin_t * iopin)
 {
-	volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
+	volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
 	return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
 extern __inline__ uint iopin_is_act (iopin_t * iopin)
 {
-	volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
+	volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
 	return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
 }
 
 extern __inline__ void iopin_set_ded (iopin_t * iopin)
 {
-	volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
+	volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
 	parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
 extern __inline__ void iopin_set_gen (iopin_t * iopin)
 {
-	volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
+	volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
 	parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
 extern __inline__ uint iopin_is_ded (iopin_t * iopin)
 {
-	volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
+	volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
 	return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
 extern __inline__ uint iopin_is_gen (iopin_t * iopin)
 {
-	volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
+	volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
 	return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
 }
 
 extern __inline__ void iopin_set_opt2 (iopin_t * iopin)
 {
-	volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
+	volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
 	sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
 }
 
 extern __inline__ void iopin_set_opt1 (iopin_t * iopin)
 {
-	volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
+	volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
 	sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
 }
 
 extern __inline__ uint iopin_is_opt2 (iopin_t * iopin)
 {
-	volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
+	volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
 	return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
 }
 
 extern __inline__ uint iopin_is_opt1 (iopin_t * iopin)
 {
-	volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
+	volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
 	return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
 }
 
diff --git a/include/asm-ppc/iopin_8xx.h b/include/asm-ppc/iopin_8xx.h
index 1946eb2..3a2a682 100644
--- a/include/asm-ppc/iopin_8xx.h
+++ b/include/asm-ppc/iopin_8xx.h
@@ -46,16 +46,16 @@ extern __inline__ void
 iopin_set_high(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat;
+		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
 		*datp |= (1 << (15 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat;
+		volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
 		*datp |= (1 << (31 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat;
+		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
 		*datp |= (1 << (15 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat;
+		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
 		*datp |= (1 << (15 - iopin->pin));
 	}
 }
@@ -64,16 +64,16 @@ extern __inline__ void
 iopin_set_low(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat;
+		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
 		*datp &= ~(1 << (15 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat;
+		volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
 		*datp &= ~(1 << (31 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat;
+		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
 		*datp &= ~(1 << (15 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat;
+		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
 		*datp &= ~(1 << (15 - iopin->pin));
 	}
 }
@@ -82,16 +82,16 @@ extern __inline__ uint
 iopin_is_high(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat;
+		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
 		return (*datp >> (15 - iopin->pin)) & 1;
 	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat;
+		volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
 		return (*datp >> (31 - iopin->pin)) & 1;
 	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat;
+		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
 		return (*datp >> (15 - iopin->pin)) & 1;
 	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat;
+		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
 		return (*datp >> (15 - iopin->pin)) & 1;
 	}
 	return 0;
@@ -101,16 +101,16 @@ extern __inline__ uint
 iopin_is_low(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat;
+		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
 		return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
 	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat;
+		volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
 		return ((*datp >> (31 - iopin->pin)) & 1) ^ 1;
 	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat;
+		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
 		return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
 	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat;
+		volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
 		return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
 	}
 	return 0;
@@ -120,16 +120,16 @@ extern __inline__ void
 iopin_set_out(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir;
+		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
 		*dirp |= (1 << (15 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir;
+		volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
 		*dirp |= (1 << (31 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir;
+		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
 		*dirp |= (1 << (15 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir;
+		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
 		*dirp |= (1 << (15 - iopin->pin));
 	}
 }
@@ -138,16 +138,16 @@ extern __inline__ void
 iopin_set_in(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir;
+		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
 		*dirp &= ~(1 << (15 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir;
+		volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
 		*dirp &= ~(1 << (31 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir;
+		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
 		*dirp &= ~(1 << (15 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir;
+		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
 		*dirp &= ~(1 << (15 - iopin->pin));
 	}
 }
@@ -156,16 +156,16 @@ extern __inline__ uint
 iopin_is_out(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir;
+		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
 		return (*dirp >> (15 - iopin->pin)) & 1;
 	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir;
+		volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
 		return (*dirp >> (31 - iopin->pin)) & 1;
 	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir;
+		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
 		return (*dirp >> (15 - iopin->pin)) & 1;
 	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir;
+		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
 		return (*dirp >> (15 - iopin->pin)) & 1;
 	}
 	return 0;
@@ -175,16 +175,16 @@ extern __inline__ uint
 iopin_is_in(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir;
+		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
 		return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
 	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir;
+		volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
 		return ((*dirp >> (31 - iopin->pin)) & 1) ^ 1;
 	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir;
+		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
 		return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
 	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir;
+		volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
 		return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
 	}
 	return 0;
@@ -194,10 +194,10 @@ extern __inline__ void
 iopin_set_odr(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr;
+		volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
 		*odrp |= (1 << (15 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTB) {
-		volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr;
+		volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
 		*odrp |= (1 << (31 - iopin->pin));
 	}
 }
@@ -206,10 +206,10 @@ extern __inline__ void
 iopin_set_act(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr;
+		volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
 		*odrp &= ~(1 << (15 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTB) {
-		volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr;
+		volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
 		*odrp &= ~(1 << (31 - iopin->pin));
 	}
 }
@@ -218,10 +218,10 @@ extern __inline__ uint
 iopin_is_odr(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr;
+		volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
 		return (*odrp >> (15 - iopin->pin)) & 1;
 	} else if (iopin->port == IOPIN_PORTB) {
-		volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr;
+		volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
 		return (*odrp >> (31 - iopin->pin)) & 1;
 	}
 	return 0;
@@ -231,10 +231,10 @@ extern __inline__ uint
 iopin_is_act(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr;
+		volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
 		return ((*odrp >> (15 - iopin->pin)) & 1) ^ 1;
 	} else if (iopin->port == IOPIN_PORTB) {
-		volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr;
+		volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
 		return ((*odrp >> (31 - iopin->pin)) & 1) ^ 1;
 	}
 	return 0;
@@ -244,16 +244,16 @@ extern __inline__ void
 iopin_set_ded(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar;
+		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
 		*parp |= (1 << (15 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar;
+		volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
 		*parp |= (1 << (31 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar;
+		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
 		*parp |= (1 << (15 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar;
+		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
 		*parp |= (1 << (15 - iopin->pin));
 	}
 }
@@ -262,16 +262,16 @@ extern __inline__ void
 iopin_set_gen(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar;
+		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
 		*parp &= ~(1 << (15 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar;
+		volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
 		*parp &= ~(1 << (31 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar;
+		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
 		*parp &= ~(1 << (15 - iopin->pin));
 	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar;
+		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
 		*parp &= ~(1 << (15 - iopin->pin));
 	}
 }
@@ -280,16 +280,16 @@ extern __inline__ uint
 iopin_is_ded(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar;
+		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
 		return (*parp >> (15 - iopin->pin)) & 1;
 	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar;
+		volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
 		return (*parp >> (31 - iopin->pin)) & 1;
 	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar;
+		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
 		return (*parp >> (15 - iopin->pin)) & 1;
 	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar;
+		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
 		return (*parp >> (15 - iopin->pin)) & 1;
 	}
 	return 0;
@@ -299,16 +299,16 @@ extern __inline__ uint
 iopin_is_gen(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTA) {
-		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar;
+		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
 		return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
 	} else if (iopin->port == IOPIN_PORTB) {
-		volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar;
+		volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
 		return ((*parp >> (31 - iopin->pin)) & 1) ^ 1;
 	} else if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar;
+		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
 		return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
 	} else if (iopin->port == IOPIN_PORTD) {
-		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar;
+		volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
 		return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
 	}
 	return 0;
@@ -318,7 +318,7 @@ extern __inline__ void
 iopin_set_opt2(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso;
+		volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
 		*sorp |= (1 << (15 - iopin->pin));
 	}
 }
@@ -327,7 +327,7 @@ extern __inline__ void
 iopin_set_opt1(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso;
+		volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
 		*sorp &= ~(1 << (15 - iopin->pin));
 	}
 }
@@ -336,7 +336,7 @@ extern __inline__ uint
 iopin_is_opt2(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso;
+		volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
 		return (*sorp >> (15 - iopin->pin)) & 1;
 	}
 	return 0;
@@ -346,7 +346,7 @@ extern __inline__ uint
 iopin_is_opt1(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso;
+		volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
 		return ((*sorp >> (15 - iopin->pin)) & 1) ^ 1;
 	}
 	return 0;
@@ -356,7 +356,7 @@ extern __inline__ void
 iopin_set_falledge(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint;
+		volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
 		*intp |= (1 << (15 - iopin->pin));
 	}
 }
@@ -365,7 +365,7 @@ extern __inline__ void
 iopin_set_anyedge(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint;
+		volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
 		*intp &= ~(1 << (15 - iopin->pin));
 	}
 }
@@ -374,7 +374,7 @@ extern __inline__ uint
 iopin_is_falledge(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint;
+		volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
 		return (*intp >> (15 - iopin->pin)) & 1;
 	}
 	return 0;
@@ -384,7 +384,7 @@ extern __inline__ uint
 iopin_is_anyedge(iopin_t *iopin)
 {
 	if (iopin->port == IOPIN_PORTC) {
-		volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint;
+		volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
 		return ((*intp >> (15 - iopin->pin)) & 1) ^ 1;
 	}
 	return 0;
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 8975e6c..fa92b90 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -138,6 +138,10 @@ typedef struct _MMU_context {
 extern void _tlbie(unsigned long va);	/* invalidate a TLB entry */
 extern void _tlbia(void);		/* invalidate all TLB entries */
 
+#ifdef CONFIG_ADDR_MAP
+extern void init_addr_map(void);
+#endif
+
 typedef enum {
 	IBAT0 = 0, IBAT1, IBAT2, IBAT3,
 	DBAT0, DBAT1, DBAT2, DBAT3,
@@ -153,25 +157,64 @@ extern void print_bats(void);
 
 #endif /* __ASSEMBLY__ */
 
-/* Block size masks */
-#define BL_128K	0x000
-#define BL_256K 0x001
-#define BL_512K 0x003
-#define BL_1M   0x007
-#define BL_2M   0x00F
-#define BL_4M   0x01F
-#define BL_8M   0x03F
-#define BL_16M  0x07F
-#define BL_32M  0x0FF
-#define BL_64M  0x1FF
-#define BL_128M 0x3FF
-#define BL_256M 0x7FF
+#define BATU_VS                 0x00000002
+#define BATU_VP                 0x00000001
+#define BATU_INVALID            0x00000000
+
+#define BATL_WRITETHROUGH       0x00000040
+#define BATL_CACHEINHIBIT       0x00000020
+#define BATL_MEMCOHERENCE	0x00000010
+#define BATL_GUARDEDSTORAGE     0x00000008
+#define BATL_NO_ACCESS		0x00000000
+
+#define BATL_PP_MSK		0x00000003
+#define BATL_PP_00		0x00000000 /* No access */
+#define BATL_PP_01		0x00000001 /* Read-only */
+#define BATL_PP_10		0x00000002 /* Read-write */
+#define BATL_PP_11		0x00000003
+
+#define BATL_PP_NO_ACCESS	BATL_PP_00
+#define BATL_PP_RO		BATL_PP_01
+#define BATL_PP_RW		BATL_PP_10
+
+/* BAT Block size values */
+#define BATU_BL_128K            0x00000000
+#define BATU_BL_256K            0x00000004
+#define BATU_BL_512K            0x0000000c
+#define BATU_BL_1M              0x0000001c
+#define BATU_BL_2M              0x0000003c
+#define BATU_BL_4M              0x0000007c
+#define BATU_BL_8M              0x000000fc
+#define BATU_BL_16M             0x000001fc
+#define BATU_BL_32M             0x000003fc
+#define BATU_BL_64M             0x000007fc
+#define BATU_BL_128M            0x00000ffc
+#define BATU_BL_256M            0x00001ffc
+
+/* Block lengths for processors that support extended block length */
+#ifdef HID0_XBSEN
+#define BATU_BL_512M            0x00003ffc
+#define BATU_BL_1G              0x00007ffc
+#define BATU_BL_2G              0x0000fffc
+#define BATU_BL_4G              0x0001fffc
+#define BATU_BL_MAX		BATU_BL_4G
+#else
+#define BATU_BL_MAX		BATU_BL_256M
+#endif
 
 /* BAT Access Protection */
 #define BPP_XX	0x00		/* No access */
 #define BPP_RX	0x01		/* Read only */
 #define BPP_RW	0x02		/* Read/write */
 
+/* Macros to get values from BATs, once data is in the BAT register format */
+#define BATU_VALID(x) (x & 0x3)
+#define BATU_VADDR(x) (x & 0xfffe0000)
+#define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000)		\
+				     | ((x & 0x0e00ULL) << 24)	\
+				     | ((x & 0x04ULL) << 30)))
+#define BATU_SIZE(x) (1UL << (fls((x & BATU_BL_MAX) >> 2) + 17))
+
 /* Used to set up SDR1 register */
 #define HASH_TABLE_SIZE_64K	0x00010000
 #define HASH_TABLE_SIZE_128K	0x00020000
@@ -431,6 +474,7 @@ extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
 extern void disable_tlb(u8 esel);
 extern void invalidate_tlb(u8 tlb);
 extern void init_tlbs(void);
+
 extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
 
 #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
diff --git a/include/asm-ppc/ppc4xx-ebc.h b/include/asm-ppc/ppc4xx-ebc.h
index d180e04..9680f70 100644
--- a/include/asm-ppc/ppc4xx-ebc.h
+++ b/include/asm-ppc/ppc4xx-ebc.h
@@ -35,7 +35,38 @@
 #define CONFIG_EBC_PPC4xx_IBM_VER1
 #endif
 
+/*
+ * Define the max number of EBC banks (chip selects)
+ */
+#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
+    defined(CONFIG_405EZ) || \
+    defined(CONFIG_440GP) || defined(CONFIG_440GX)
+#define EBC_NUM_BANKS	8
+#endif
+
+#if defined(CONFIG_405EP)
+#define EBC_NUM_BANKS	5
+#endif
+
+#if defined(CONFIG_405EX) || \
+    defined(CONFIG_460SX)
+#define EBC_NUM_BANKS	4
+#endif
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define EBC_NUM_BANKS	6
+#endif
+
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#define EBC_NUM_BANKS	3
+#endif
+
 /* Bank Configuration Register */
+#define EBC_BXCR(n)		(n)
+#define EBC_BXCR_BANK_SIZE(n)	(0x100000 << (((n) & EBC_BXCR_BS_MASK) >> 17))
+
 #define	EBC_BXCR_BAS_MASK	PPC_REG_VAL(11, 0xFFF)
 #define EBC_BXCR_BAS_ENCODE(n)	(((static_cast(u32, n)) & EBC_BXCR_BAS_MASK))
 #define EBC_BXCR_BS_MASK	PPC_REG_VAL(14, 0x7)
diff --git a/include/asm-ppc/ppc4xx-isram.h b/include/asm-ppc/ppc4xx-isram.h
new file mode 100644
index 0000000..d6d17ac
--- /dev/null
+++ b/include/asm-ppc/ppc4xx-isram.h
@@ -0,0 +1,75 @@
+
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC4xx_ISRAM_H_
+#define _PPC4xx_ISRAM_H_
+
+/*
+ * Internal SRAM
+ */
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define ISRAM0_DCR_BASE 0x380
+#else
+#define ISRAM0_DCR_BASE 0x020
+#endif
+#define ISRAM0_SB0CR	(ISRAM0_DCR_BASE+0x00)	/* SRAM bank config 0*/
+#define ISRAM0_SB1CR	(ISRAM0_DCR_BASE+0x01)	/* SRAM bank config 1*/
+#define ISRAM0_SB2CR	(ISRAM0_DCR_BASE+0x02)	/* SRAM bank config 2*/
+#define ISRAM0_SB3CR	(ISRAM0_DCR_BASE+0x03)	/* SRAM bank config 3*/
+#define ISRAM0_BEAR	(ISRAM0_DCR_BASE+0x04)	/* SRAM bus error addr reg */
+#define ISRAM0_BESR0	(ISRAM0_DCR_BASE+0x05)	/* SRAM bus error status reg 0 */
+#define ISRAM0_BESR1	(ISRAM0_DCR_BASE+0x06)	/* SRAM bus error status reg 1 */
+#define ISRAM0_PMEG	(ISRAM0_DCR_BASE+0x07)	/* SRAM power management */
+#define ISRAM0_CID	(ISRAM0_DCR_BASE+0x08)	/* SRAM bus core id reg */
+#define ISRAM0_REVID	(ISRAM0_DCR_BASE+0x09)	/* SRAM bus revision id reg */
+#define ISRAM0_DPC	(ISRAM0_DCR_BASE+0x0a)	/* SRAM data parity check reg */
+
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define ISRAM1_DCR_BASE 0x0B0
+#define ISRAM1_SB0CR	(ISRAM1_DCR_BASE+0x00)	/* SRAM1 bank config 0*/
+#define ISRAM1_BEAR	(ISRAM1_DCR_BASE+0x04)	/* SRAM1 bus error addr reg */
+#define ISRAM1_BESR0	(ISRAM1_DCR_BASE+0x05)	/* SRAM1 bus error status reg 0 */
+#define ISRAM1_BESR1	(ISRAM1_DCR_BASE+0x06)	/* SRAM1 bus error status reg 1 */
+#define ISRAM1_PMEG	(ISRAM1_DCR_BASE+0x07)	/* SRAM1 power management */
+#define ISRAM1_CID	(ISRAM1_DCR_BASE+0x08)	/* SRAM1 bus core id reg */
+#define ISRAM1_REVID	(ISRAM1_DCR_BASE+0x09)	/* SRAM1 bus revision id reg */
+#define ISRAM1_DPC	(ISRAM1_DCR_BASE+0x0a)	/* SRAM1 data parity check reg */
+#endif /* CONFIG_460EX || CONFIG_460GT */
+
+/*
+ * L2 Cache
+ */
+#if defined (CONFIG_440GX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_460SX)
+#define L2_CACHE_BASE	0x030
+#define L2_CACHE_CFG	(L2_CACHE_BASE+0x00)	/* L2 Cache Config      */
+#define L2_CACHE_CMD	(L2_CACHE_BASE+0x01)	/* L2 Cache Command     */
+#define L2_CACHE_ADDR	(L2_CACHE_BASE+0x02)	/* L2 Cache Address     */
+#define L2_CACHE_DATA	(L2_CACHE_BASE+0x03)	/* L2 Cache Data        */
+#define L2_CACHE_STAT	(L2_CACHE_BASE+0x04)	/* L2 Cache Status      */
+#define L2_CACHE_CVER	(L2_CACHE_BASE+0x05)	/* L2 Cache Revision ID */
+#define L2_CACHE_SNP0	(L2_CACHE_BASE+0x06)	/* L2 Cache Snoop reg 0 */
+#define L2_CACHE_SNP1	(L2_CACHE_BASE+0x07)	/* L2 Cache Snoop reg 1 */
+#endif /* CONFIG_440GX */
+
+#endif /* _PPC4xx_ISRAM_H_ */
diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h
index 8efa557..992a3d2 100644
--- a/include/asm-ppc/ppc4xx-sdram.h
+++ b/include/asm-ppc/ppc4xx-sdram.h
@@ -272,8 +272,11 @@
 #define SDRAM_CONF1HB_PRPD	0x00080000	/* PLB Read pipeline Disable - Bit 12 */
 #define SDRAM_CONF1HB_PWPD	0x00040000	/* PLB Write pipeline Disable - Bit 13 */
 #define SDRAM_CONF1HB_PRW	0x00020000	/* PLB Read Wait - Bit 14 */
+#define SDRAM_CONF1HB_RPLM	0x00001000	/* Read Passing Limit 1 - Bits 16..19 */
 #define SDRAM_CONF1HB_RPEN	0x00000800	/* Read Passing Enable - Bit 20 */
 #define SDRAM_CONF1HB_RFTE	0x00000400	/* Read Flow Through Enable - Bit 21 */
+#define SDRAM_CONF1HB_WRCL	0x00000080	/* MCIF Cycle Limit 1 - Bits 22..24 */
+#define SDRAM_CONF1HB_MASK	0x0000F380	/* RPLM & WRCL mask */
 
 #define SDRAM_ERRSTATHB		(SDRAMQ_DCR_BASE+0x7)	/* error status HB             */
 #define SDRAM_ERRADDUHB		(SDRAMQ_DCR_BASE+0x8)	/* error address upper 32 HB   */
@@ -284,8 +287,10 @@
 #define SDRAM_CONF1LL_PRPD	0x00080000		/* PLB Read pipeline Disable - Bit 12 */
 #define SDRAM_CONF1LL_PWPD	0x00040000		/* PLB Write pipeline Disable - Bit 13 */
 #define SDRAM_CONF1LL_PRW	0x00020000		/* PLB Read Wait - Bit 14 */
+#define SDRAM_CONF1LL_RPLM	0x00001000		/* Read Passing Limit 1 - Bits 16..19 */
 #define SDRAM_CONF1LL_RPEN	0x00000800		/* Read Passing Enable - Bit 20 */
 #define SDRAM_CONF1LL_RFTE	0x00000400		/* Read Flow Through Enable - Bit 21 */
+#define SDRAM_CONF1LL_MASK	0x0000F000		/* RPLM mask */
 
 #define SDRAM_ERRSTATLL		(SDRAMQ_DCR_BASE+0xC)	/* error status LL             */
 #define SDRAM_ERRADDULL		(SDRAMQ_DCR_BASE+0xD)	/* error address upper 32 LL   */
@@ -561,6 +566,8 @@
 #define SDRAM_RDCC_RSAE_MASK		0x00000001
 #define SDRAM_RDCC_RSAE_DISABLE		0x00000001
 #define SDRAM_RDCC_RSAE_ENABLE		0x00000000
+#define SDRAM_RDCC_RDSS_ENCODE(n)	((((u32)(n))&0x03)<<30)
+#define SDRAM_RDCC_RDSS_DECODE(n)	((((u32)(n))>>30)&0x03)
 
 /*
  * SDRAM Read Feedback Delay Control Register
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index e07e5d3..5b29de0 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -451,6 +451,8 @@
 #define   L2CSR0_L2LO		0x00000020	/* L2 Cache Lock Overflow */
 #define SPRN_L2CSR1	0x3fa	/* L2 Data Cache Control and Status Register 1 */
 
+#define SPRN_TLB0CFG	0x2B0	/* TLB 0 Config Register */
+#define SPRN_TLB1CFG	0x2B1	/* TLB 1 Config Register */
 #define SPRN_MMUCSR0	0x3f4	/* MMU control and status register 0 */
 #define SPRN_MAS0	0x270	/* MMU Assist Register 0 */
 #define SPRN_MAS1	0x271	/* MMU Assist Register 1 */
@@ -777,6 +779,13 @@
 #define PVR_MAJ(pvr)	(((pvr) >>  4) & 0xF)	/* Major revision field */
 #define PVR_MIN(pvr)	(((pvr) >>  0) & 0xF)	/* Minor revision field */
 
+/* e600 core PVR fields */
+
+#define PVR_E600_VER(pvr)	(((pvr) >> 15) & 0xFFFF) /* Version/type */
+#define PVR_E600_TECH(pvr)	(((pvr) >> 12) & 0xF)	 /* Technology */
+#define PVR_E600_MAJ(pvr)	(((pvr) >> 8) & 0xF)	 /* Major revision */
+#define PVR_E600_MIN(pvr)	(((pvr) >> 0) & 0xFF)	 /* Minor revision */
+
 /* Processor Version Numbers */
 
 #define PVR_403GA	0x00200000
@@ -857,7 +866,6 @@
 #define PVR_85xx_REV2	(PVR_85xx | 0x0020)
 
 #define PVR_86xx	0x80040000
-#define PVR_86xx_REV1	(PVR_86xx | 0x0010)
 
 #define PVR_VIRTEX5     0x7ff21912
 
@@ -949,6 +957,8 @@
 #define SVR_8568_E	0x807D00
 #define SVR_8572	0x80E000
 #define SVR_8572_E	0x80E800
+#define SVR_P2020	0x80E200
+#define SVR_P2020_E	0x80EA00
 
 #define SVR_8610	0x80A000
 #define SVR_8641	0x809000
diff --git a/include/asm-ppc/status_led.h b/include/asm-ppc/status_led.h
index eb81f37..0375709 100644
--- a/include/asm-ppc/status_led.h
+++ b/include/asm-ppc/status_led.h
@@ -24,7 +24,7 @@ typedef unsigned long led_id_t;
 
 static inline void __led_init (led_id_t mask, int state)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 #ifdef STATUS_LED_PAR
 	immr->STATUS_LED_PAR &= ~mask;
@@ -51,12 +51,12 @@ static inline void __led_init (led_id_t mask, int state)
 
 static inline void __led_toggle (led_id_t mask)
 {
-	((immap_t *) CFG_IMMR)->STATUS_LED_DAT ^= mask;
+	((immap_t *) CONFIG_SYS_IMMR)->STATUS_LED_DAT ^= mask;
 }
 
 static inline void __led_set (led_id_t mask, int state)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 #if (STATUS_LED_ACTIVE == 0)
 	if (state == STATUS_LED_ON)
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index 54ac01d..7451905 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -111,6 +111,12 @@ typedef struct bd_info {
 #ifdef CONFIG_HAS_ETH3
 	unsigned char   bi_enet3addr[6];
 #endif
+#ifdef CONFIG_HAS_ETH4
+	unsigned char   bi_enet4addr[6];
+#endif
+#ifdef CONFIG_HAS_ETH5
+	unsigned char   bi_enet5addr[6];
+#endif
 
 #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
     defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
diff --git a/include/asm-sh/config.h b/include/asm-sh/config.h
new file mode 100644
index 0000000..049c44e
--- /dev/null
+++ b/include/asm-sh/config.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
diff --git a/include/asm-sh/cpu_sh4.h b/include/asm-sh/cpu_sh4.h
index b6cc6cf..d2dbfcd 100644
--- a/include/asm-sh/cpu_sh4.h
+++ b/include/asm-sh/cpu_sh4.h
@@ -26,8 +26,15 @@
 #define CCR_CACHE_ICI    0x00000800
 
 #define CACHE_OC_ADDRESS_ARRAY	0xf4000000
+
+#if defined (CONFIG_CPU_SH7750) || \
+	defined(CONFIG_CPU_SH7751)
 #define CACHE_OC_WAY_SHIFT	14
 #define CACHE_OC_NUM_ENTRIES	512
+#else
+#define CACHE_OC_WAY_SHIFT	13
+#define CACHE_OC_NUM_ENTRIES	256
+#endif
 #define CACHE_OC_ENTRY_SHIFT	5
 
 #if defined (CONFIG_CPU_SH7750) || \
diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h
index adc3f81..ca598a6 100644
--- a/include/asm-sh/io.h
+++ b/include/asm-sh/io.h
@@ -261,5 +261,10 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
 
 }
 
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
 #endif	/* __KERNEL__ */
 #endif	/* __ASM_SH_IO_H */
diff --git a/include/asm-sh/macro.h b/include/asm-sh/macro.h
new file mode 100644
index 0000000..61f792a
--- /dev/null
+++ b/include/asm-sh/macro.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MACRO_H__
+#define __MACRO_H__
+#ifdef __ASSEMBLY__
+
+.macro	write32, addr, data
+	mov.l \addr ,r1
+	mov.l \data ,r0
+	mov.l r0, @r1
+.endm
+
+.macro	write16, addr, data
+	mov.l \addr ,r1
+	mov.l \data ,r0
+	mov.w r0, @r1
+.endm
+
+.macro	write8, addr, data
+	mov.l \addr ,r1
+	mov.l \data ,r0
+	mov.b r0, @r1
+.endm
+
+.macro	wait_timer, time
+	mov.l	\time ,r3
+1:
+	nop
+	tst	r3, r3
+	bf/s	1b
+	dt	r3
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __MACRO_H__ */
diff --git a/include/asm-sparc/asmmacro.h b/include/asm-sparc/asmmacro.h
index 0c4cefd..aeb87ee 100644
--- a/include/asm-sparc/asmmacro.h
+++ b/include/asm-sparc/asmmacro.h
@@ -33,8 +33,8 @@
  * c-code can be called.
  */
 #define SAVE_ALL_HEAD \
-	sethi	%hi(trap_setup+(CFG_RELOC_MONITOR_BASE-TEXT_BASE)), %l4; \
-	jmpl	%l4 + %lo(trap_setup+(CFG_RELOC_MONITOR_BASE-TEXT_BASE)), %l6;
+	sethi	%hi(trap_setup+(CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE)), %l4; \
+	jmpl	%l4 + %lo(trap_setup+(CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE)), %l6;
 #define SAVE_ALL \
 	SAVE_ALL_HEAD \
 	nop;
diff --git a/include/asm-sparc/config.h b/include/asm-sparc/config.h
new file mode 100644
index 0000000..049c44e
--- /dev/null
+++ b/include/asm-sparc/config.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
diff --git a/include/asm-sparc/global_data.h b/include/asm-sparc/global_data.h
index eeb35d0..dea2857 100644
--- a/include/asm-sparc/global_data.h
+++ b/include/asm-sparc/global_data.h
@@ -36,7 +36,7 @@
  * global variables during system initialization (until we have set
  * up the memory controller so that we can use RAM).
  *
- * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
  */
 
 typedef struct global_data {
diff --git a/include/asm-sparc/io.h b/include/asm-sparc/io.h
index ede0b1a..0c5d86c 100644
--- a/include/asm-sparc/io.h
+++ b/include/asm-sparc/io.h
@@ -32,7 +32,7 @@
  * over and over again resulting in a hang (until an IRQ if lucky)
  *
  */
-#ifndef CFG_HAS_NO_CACHE
+#ifndef CONFIG_SYS_HAS_NO_CACHE
 #define READ_BYTE(var)  SPARC_NOCACHE_READ_BYTE((unsigned int)(var))
 #define READ_HWORD(var) SPARC_NOCACHE_READ_HWORD((unsigned int)(var))
 #define READ_WORD(var)  SPARC_NOCACHE_READ((unsigned int)(var))
@@ -90,4 +90,9 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
 
 }
 
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
 #endif
diff --git a/include/ata.h b/include/ata.h
index 2396769..b51475d 100644
--- a/include/ata.h
+++ b/include/ata.h
@@ -39,13 +39,13 @@
  * 8-bit (register) and 16-bit (data) accesses might use different
  * address spaces. This is implemented by the following definitions.
  */
-#ifndef CFG_ATA_STRIDE
-#define CFG_ATA_STRIDE	1
+#ifndef CONFIG_SYS_ATA_STRIDE
+#define CONFIG_SYS_ATA_STRIDE	1
 #endif
 
-#define ATA_IO_DATA(x)	(CFG_ATA_DATA_OFFSET+((x) * CFG_ATA_STRIDE))
-#define ATA_IO_REG(x)	(CFG_ATA_REG_OFFSET +((x) * CFG_ATA_STRIDE))
-#define ATA_IO_ALT(x)	(CFG_ATA_ALT_OFFSET +((x) * CFG_ATA_STRIDE))
+#define ATA_IO_DATA(x)	(CONFIG_SYS_ATA_DATA_OFFSET+((x) * CONFIG_SYS_ATA_STRIDE))
+#define ATA_IO_REG(x)	(CONFIG_SYS_ATA_REG_OFFSET +((x) * CONFIG_SYS_ATA_STRIDE))
+#define ATA_IO_ALT(x)	(CONFIG_SYS_ATA_ALT_OFFSET +((x) * CONFIG_SYS_ATA_STRIDE))
 
 /*
  * I/O Register Descriptions
diff --git a/include/command.h b/include/command.h
index f92383d..d7321af 100644
--- a/include/command.h
+++ b/include/command.h
@@ -33,6 +33,11 @@
 #define NULL	0
 #endif
 
+/* Default to a width of 8 characters for help message command width */
+#ifndef CONFIG_SYS_HELP_CMD_WIDTH
+#define CONFIG_SYS_HELP_CMD_WIDTH	8
+#endif
+
 #ifndef	__ASSEMBLY__
 /*
  * Monitor Command Table
@@ -45,7 +50,7 @@ struct cmd_tbl_s {
 					/* Implementation function	*/
 	int		(*cmd)(struct cmd_tbl_s *, int, int, char *[]);
 	char		*usage;		/* Usage message	(short)	*/
-#ifdef	CFG_LONGHELP
+#ifdef	CONFIG_SYS_LONGHELP
 	char		*help;		/* Help  message	(long)	*/
 #endif
 #ifdef CONFIG_AUTO_COMPLETE
@@ -62,6 +67,9 @@ extern cmd_tbl_t  __u_boot_cmd_end;
 
 /* common/command.c */
 cmd_tbl_t *find_cmd(const char *cmd);
+cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len);
+
+extern void cmd_usage(cmd_tbl_t *cmdtp);
 
 #ifdef CONFIG_AUTO_COMPLETE
 extern void install_auto_complete(void);
@@ -97,16 +105,22 @@ extern int cmd_get_data_size(char* arg, int default_size);
 
 #define Struct_Section  __attribute__ ((unused,section (".u_boot_cmd")))
 
-#ifdef  CFG_LONGHELP
+#ifdef  CONFIG_SYS_LONGHELP
 
 #define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
 cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage, help}
 
+#define U_BOOT_CMD_MKENT(name,maxargs,rep,cmd,usage,help) \
+{#name, maxargs, rep, cmd, usage, help}
+
 #else	/* no long help info */
 
 #define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
 cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage}
 
-#endif	/* CFG_LONGHELP */
+#define U_BOOT_CMD_MKENT(name,maxargs,rep,cmd,usage,help) \
+{#name, maxargs, rep, cmd, usage}
+
+#endif	/* CONFIG_SYS_LONGHELP */
 
 #endif	/* __COMMAND_H */
diff --git a/include/common.h b/include/common.h
index 33c6e10..afee188 100644
--- a/include/common.h
+++ b/include/common.h
@@ -177,6 +177,9 @@ typedef void (interrupt_handler_t)(void *);
 	({ typeof (X) __x = (X), __y = (Y);	\
 		(__x > __y) ? __x : __y; })
 
+#define MIN(x, y)  min(x, y)
+#define MAX(x, y)  max(x, y)
+
 
 /**
  * container_of - cast a member of a structure out to the containing structure
@@ -276,10 +279,10 @@ void	pciinfo	      (int, int);
 #endif
 
 #if defined(CONFIG_PCI) && (defined(CONFIG_440) || defined(CONFIG_405EX))
-#   if defined(CFG_PCI_TARGET_INIT)
+#   if defined(CONFIG_SYS_PCI_TARGET_INIT)
 	void	pci_target_init	     (struct pci_controller *);
 #   endif
-#   if defined(CFG_PCI_MASTER_INIT)
+#   if defined(CONFIG_SYS_PCI_MASTER_INIT)
 	void	pci_master_init	     (struct pci_controller *);
 #   endif
     int	    is_pci_host		(struct pci_controller *);
@@ -322,11 +325,11 @@ extern void  pic_write (uchar reg, uchar val);
  * Set this up regardless of board
  * type, to prevent errors.
  */
-#if defined(CONFIG_SPI) || !defined(CFG_I2C_EEPROM_ADDR)
-# define CFG_DEF_EEPROM_ADDR 0
+#if defined(CONFIG_SPI) || !defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+# define CONFIG_SYS_DEF_EEPROM_ADDR 0
 #else
-# define CFG_DEF_EEPROM_ADDR CFG_I2C_EEPROM_ADDR
-#endif /* CONFIG_SPI || !defined(CFG_I2C_EEPROM_ADDR) */
+# define CONFIG_SYS_DEF_EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR
+#endif /* CONFIG_SPI || !defined(CONFIG_SYS_I2C_EEPROM_ADDR) */
 
 #if defined(CONFIG_SPI)
 extern void spi_init_f (void);
@@ -376,9 +379,9 @@ int board_postclk_init (void); /* after clocks/timebase, before env/serial */
 int board_early_init_r (void);
 void board_poweroff (void);
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram(void);
-#endif /* CFG_DRAM_TEST */
+#endif /* CONFIG_SYS_DRAM_TEST */
 
 /* $(CPU)/start.S */
 #if defined(CONFIG_5xx) || \
@@ -594,6 +597,8 @@ ulong	video_setmem (ulong);
 
 /* lib_$(ARCH)/cache.c */
 void	flush_cache   (unsigned long, unsigned long);
+void	flush_dcache_range(unsigned long start, unsigned long stop);
+void	invalidate_dcache_range(unsigned long start, unsigned long stop);
 
 
 /* lib_$(ARCH)/ticks.S */
@@ -608,7 +613,7 @@ int	init_timebase (void);
 
 /* lib_generic/vsprintf.c */
 ulong	simple_strtoul(const char *cp,char **endp,unsigned int base);
-#ifdef CFG_64BIT_VSPRINTF
+#ifdef CONFIG_SYS_64BIT_VSPRINTF
 unsigned long long	simple_strtoull(const char *cp,char **endp,unsigned int base);
 #endif
 long	simple_strtol(const char *cp,char **endp,unsigned int base);
@@ -675,6 +680,13 @@ void	fputc(int file, const char c);
 int	ftstc(int file);
 int	fgetc(int file);
 
+/*
+ * CONSOLE multiplexing.
+ */
+#ifdef CONFIG_CONSOLE_MUX
+#include <iomux.h>
+#endif
+
 int	pcmcia_init (void);
 
 #ifdef CONFIG_STATUS_LED
@@ -692,8 +704,9 @@ void __attribute__((weak)) show_boot_progress (int val);
 
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 
-#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
-#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
+#define DIV_ROUND(n,d)		(((n) + ((d)/2)) / (d))
+#define DIV_ROUND_UP(n,d)	(((n) + (d) - 1) / (d))
+#define roundup(x, y)		((((x) + ((y) - 1)) / (y)) * (y))
 
 #define ALIGN(x,a)		__ALIGN_MASK((x),(typeof(x))(a)-1)
 #define __ALIGN_MASK(x,mask)	(((x)+(mask))&~(mask))
diff --git a/include/commproc.h b/include/commproc.h
index 0a4e817..12decfe 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -62,7 +62,7 @@
  * as data ram for buffer descriptors, which is all we use right now.
  * Currently the first 512 and last 256 bytes are used for microcode.
  */
-#ifdef  CFG_ALLOC_DPRAM
+#ifdef  CONFIG_SYS_ALLOC_DPRAM
 
 #define CPM_DATAONLY_BASE	((uint)0x0800)
 #define CPM_DATAONLY_SIZE	((uint)0x0700)
@@ -81,16 +81,16 @@
 
 #endif
 
-#ifndef CFG_CPM_POST_WORD_ADDR
+#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
 #define CPM_POST_WORD_ADDR	0x07FC
 #else
-#define CPM_POST_WORD_ADDR	CFG_CPM_POST_WORD_ADDR
+#define CPM_POST_WORD_ADDR	CONFIG_SYS_CPM_POST_WORD_ADDR
 #endif
 
-#ifndef CFG_CPM_BOOTCOUNT_ADDR
+#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
 #define CPM_BOOTCOUNT_ADDR	(CPM_POST_WORD_ADDR - 2*sizeof(ulong))
 #else
-#define CPM_BOOTCOUNT_ADDR	CFG_CPM_BOOTCOUNT_ADDR
+#define CPM_BOOTCOUNT_ADDR	CONFIG_SYS_CPM_BOOTCOUNT_ADDR
 #endif
 
 #define BD_IIC_START	((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h
index d771696..205dd1f 100644
--- a/include/config_cmd_all.h
+++ b/include/config_cmd_all.h
@@ -33,7 +33,7 @@
 #define CONFIG_CMD_ECHO		/* echo arguments		*/
 #define CONFIG_CMD_EEPROM	/* EEPROM read/write support	*/
 #define CONFIG_CMD_ELF		/* ELF (VxWorks) load/boot cmd	*/
-#define CONFIG_CMD_ENV		/* saveenv			*/
+#define CONFIG_CMD_SAVEENV	/* saveenv			*/
 #define CONFIG_CMD_EXT2		/* EXT2 Support			*/
 #define CONFIG_CMD_FAT		/* FAT support			*/
 #define CONFIG_CMD_FDC		/* Floppy Disk Support		*/
diff --git a/include/config_cmd_default.h b/include/config_cmd_default.h
index b556706..3667602 100644
--- a/include/config_cmd_default.h
+++ b/include/config_cmd_default.h
@@ -21,11 +21,13 @@
 #define CONFIG_CMD_BOOTD	/* bootd			*/
 #define CONFIG_CMD_CONSOLE	/* coninfo			*/
 #define CONFIG_CMD_ECHO		/* echo arguments		*/
-#define CONFIG_CMD_ENV		/* saveenv			*/
+#define CONFIG_CMD_SAVEENV	/* saveenv			*/
 #define CONFIG_CMD_FLASH	/* flinfo, erase, protect	*/
 #define CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
 #define CONFIG_CMD_IMI		/* iminfo			*/
+#ifndef CONFIG_SYS_NO_FLASH
 #define CONFIG_CMD_IMLS		/* List all found images	*/
+#endif
 #define CONFIG_CMD_ITEST	/* Integer (and string) test	*/
 #define CONFIG_CMD_LOADB	/* loadb			*/
 #define CONFIG_CMD_LOADS	/* loads			*/
diff --git a/include/configs/A3000.h b/include/configs/A3000.h
index cee5560..6d8870c 100644
--- a/include/configs/A3000.h
+++ b/include/configs/A3000.h
@@ -48,7 +48,7 @@
 
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		9600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_BOOTDELAY	5
 
@@ -71,16 +71,16 @@
 /*
  * Miscellaneous configurable options
  */
-#undef CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"A3000> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#undef CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"A3000> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 
 /* Print Buffer Size
  */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS	8		/* Max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00400000	/* Default load address		*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	8		/* Max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x00400000	/* Default load address		*/
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -88,8 +88,8 @@
  */
 #define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
 #undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -118,64 +118,64 @@
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE			0x00000000
+#define CONFIG_SYS_SDRAM_BASE			0x00000000
 
-#define CFG_FLASH_BASE0_PRELIM		0xFF000000	/* FLASH bank on RCS#0 */
-#define CFG_FLASH_BASE1_PRELIM		0xFF000000	/* FLASH bank on RCS#1 */
-#define CFG_FLASH_BASE			CFG_FLASH_BASE0_PRELIM
-#define CFG_FLASH_BANKS			{ CFG_FLASH_BASE0_PRELIM }
+#define CONFIG_SYS_FLASH_BASE0_PRELIM		0xFF000000	/* FLASH bank on RCS#0 */
+#define CONFIG_SYS_FLASH_BASE1_PRELIM		0xFF000000	/* FLASH bank on RCS#1 */
+#define CONFIG_SYS_FLASH_BASE			CONFIG_SYS_FLASH_BASE0_PRELIM
+#define CONFIG_SYS_FLASH_BANKS			{ CONFIG_SYS_FLASH_BASE0_PRELIM }
 
 /* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
  * reset vector is actually located at FFB00100, but the 8245
  * takes care of us.
  */
-#define CFG_RESET_ADDRESS   0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 
-#define CFG_EUMB_ADDR	    0xFC000000
+#define CONFIG_SYS_EUMB_ADDR	    0xFC000000
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
 
-#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
 
 	/* Maximum amount of RAM.
 	 */
-#define CFG_MAX_RAM_SIZE    0x04000000	/* 0 .. 128 MB of (S)DRAM */
+#define CONFIG_SYS_MAX_RAM_SIZE    0x04000000	/* 0 .. 128 MB of (S)DRAM */
 
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#undef CFG_RAMBOOT
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#undef CONFIG_SYS_RAMBOOT
 #else
-#define CFG_RAMBOOT
+#define CONFIG_SYS_RAMBOOT
 #endif
 
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
 
-#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_REG_SIZE	1
 
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
-#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_EUMB_ADDR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4600)
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area
  */
 
-/* #define CFG_MONITOR_BASE	   TEXT_BASE */
-/*#define CFG_GBL_DATA_SIZE    256*/
-#define CFG_GBL_DATA_SIZE      128
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+/* #define CONFIG_SYS_MONITOR_BASE	   TEXT_BASE */
+/*#define CONFIG_SYS_GBL_DATA_SIZE    256*/
+#define CONFIG_SYS_GBL_DATA_SIZE      128
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_END      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 
 /*
@@ -186,41 +186,41 @@
  */
 
 #define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
-#define CFG_HZ		     1000
+#define CONFIG_SYS_HZ		     1000
 
 	/* Bit-field values for MCCR1.
 	 */
-#define CFG_ROMNAL	    7
-#define CFG_ROMFAL	    11
-#define CFG_DBUS_SIZE	    0x3
+#define CONFIG_SYS_ROMNAL	    7
+#define CONFIG_SYS_ROMFAL	    11
+#define CONFIG_SYS_DBUS_SIZE	    0x3
 
 	/* Bit-field values for MCCR2.
 	 */
-#define CFG_TSWAIT	    0x5		    /* Transaction Start Wait States timer */
-#define CFG_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
+#define CONFIG_SYS_TSWAIT	    0x5		    /* Transaction Start Wait States timer */
+#define CONFIG_SYS_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
 
 	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 	 */
-#define CFG_BSTOPRE	    121
+#define CONFIG_SYS_BSTOPRE	    121
 
 	/* Bit-field values for MCCR3.
 	 */
-#define CFG_REFREC	    8	    /* Refresh to activate interval */
+#define CONFIG_SYS_REFREC	    8	    /* Refresh to activate interval */
 
 	/* Bit-field values for MCCR4.
 	 */
-#define CFG_PRETOACT	    3	    /* Precharge to activate interval FIXME: was 2	*/
-#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval FIXME: was 5	*/
-#define CFG_ACTORW	    3		/* FIXME was 2 */
-#define CFG_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
-#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
-#define CFG_REGISTERD_TYPE_BUFFER 1
-#define CFG_EXTROM	    1
-#define CFG_REGDIMM	    0
+#define CONFIG_SYS_PRETOACT	    3	    /* Precharge to activate interval FIXME: was 2	*/
+#define CONFIG_SYS_ACTTOPRE	    5	    /* Activate to Precharge interval FIXME: was 5	*/
+#define CONFIG_SYS_ACTORW	    3		/* FIXME was 2 */
+#define CONFIG_SYS_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
+#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
+#define CONFIG_SYS_EXTROM	    1
+#define CONFIG_SYS_REGDIMM	    0
 
-#define CFG_PGMAX	    0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
+#define CONFIG_SYS_PGMAX	    0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
 
-#define CFG_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
+#define CONFIG_SYS_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
 
 /* Memory bank settings.
  * Only bits 20-29 are actually used from these vales to set the
@@ -229,69 +229,69 @@
  * address. Refer to the MPC8240 book.
  */
 
-#define CFG_BANK0_START	    0x00000000
-#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START	    0x3ff00000
-#define CFG_BANK1_END	    0x3fffffff
-#define CFG_BANK1_ENABLE    0
-#define CFG_BANK2_START	    0x3ff00000
-#define CFG_BANK2_END	    0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START	    0x3ff00000
-#define CFG_BANK3_END	    0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START	    0x3ff00000
-#define CFG_BANK4_END	    0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START	    0x3ff00000
-#define CFG_BANK5_END	    0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START	    0x3ff00000
-#define CFG_BANK6_END	    0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START	    0x3ff00000
-#define CFG_BANK7_END	    0x3fffffff
-#define CFG_BANK7_ENABLE    0
-
-#define CFG_ODCR	    0xff
-
-#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L  CFG_IBAT0L
-#define CFG_DBAT0U  CFG_IBAT0U
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-#define CFG_DBAT2L  CFG_IBAT2L
-#define CFG_DBAT2U  CFG_IBAT2U
-#define CFG_DBAT3L  CFG_IBAT3L
-#define CFG_DBAT3U  CFG_IBAT3U
+#define CONFIG_SYS_BANK0_START	    0x00000000
+#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE    1
+#define CONFIG_SYS_BANK1_START	    0x3ff00000
+#define CONFIG_SYS_BANK1_END	    0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE    0
+#define CONFIG_SYS_BANK2_START	    0x3ff00000
+#define CONFIG_SYS_BANK2_END	    0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE    0
+#define CONFIG_SYS_BANK3_START	    0x3ff00000
+#define CONFIG_SYS_BANK3_END	    0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE    0
+#define CONFIG_SYS_BANK4_START	    0x3ff00000
+#define CONFIG_SYS_BANK4_END	    0x3fffffff
+#define CONFIG_SYS_BANK4_ENABLE    0
+#define CONFIG_SYS_BANK5_START	    0x3ff00000
+#define CONFIG_SYS_BANK5_END	    0x3fffffff
+#define CONFIG_SYS_BANK5_ENABLE    0
+#define CONFIG_SYS_BANK6_START	    0x3ff00000
+#define CONFIG_SYS_BANK6_END	    0x3fffffff
+#define CONFIG_SYS_BANK6_ENABLE    0
+#define CONFIG_SYS_BANK7_START	    0x3ff00000
+#define CONFIG_SYS_BANK7_END	    0x3fffffff
+#define CONFIG_SYS_BANK7_ENABLE    0
+
+#define CONFIG_SYS_ODCR	    0xff
+
+#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT	128	/* Max number of sectors per flash	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* Max number of sectors per flash	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
 
 
 	/* Warining: environment is not EMBEDDED in the U-Boot code.
@@ -305,9 +305,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SIZE	32
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /*
diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h
index cc7eddc..d8303f3 100644
--- a/include/configs/ADCIOP.h
+++ b/include/configs/ADCIOP.h
@@ -50,7 +50,7 @@
 #undef	CONFIG_BOOTARGS
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -82,91 +82,91 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
-#define CFG_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
+#define CONFIG_SYS_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFD0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFD0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x0AA9	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x0556	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x0AA9	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x0556	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0002	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0000	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0004	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0002	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0000	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0004	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 1 /* Use NVRAM for environment variables */
 /*-----------------------------------------------------------------------
  * NVRAM organization
  */
 #define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#define CFG_NVRAM_BASE_ADDR	0x10000000		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0x10000000		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
 #define CONFIG_ENV_SIZE		0x0400		/* Size of Environment vars	*/
 #define CONFIG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
-#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x7800) /* VxWorks eth-addr*/
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
+#define CONFIG_SYS_VXWORKS_MAC_PTR     (CONFIG_SYS_NVRAM_BASE_ADDR+0x7800) /* VxWorks eth-addr*/
 
 #else /* Use FLASH for environment variables */
 
@@ -188,8 +188,8 @@
 
 #define CONFIG_TULIP
 
-#define CFG_ETH_DEV_FN	     0x0000
-#define CFG_ETH_IOBASE	     0x0fff0000
+#define CONFIG_SYS_ETH_DEV_FN	     0x0000
+#define CONFIG_SYS_ETH_IOBASE	     0x0fff0000
 
 /*
  * Init Memory Controller:
diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h
index 9b84d1f..e61a3e1 100644
--- a/include/configs/ADNPESC1.h
+++ b/include/configs/ADNPESC1.h
@@ -34,7 +34,7 @@
 #if	defined(CONFIG_NIOS_BASE_32)
 #include <configs/ADNPESC1_base_32.h>
 #else
-#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
+#error *** CONFIG_SYS_ERROR: you have to setup right NIOS CPU configuration
 #endif
 
 /*------------------------------------------------------------------------
@@ -42,36 +42,36 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_NIOS		1		/* NIOS-32 core		*/
 #define	CONFIG_ADNPESC1		1		/* SSV ADNP/ESC1 board	*/
-#define CONFIG_SYS_CLK_FREQ	CFG_NIOS_CPU_CLK/* 50 MHz core clock	*/
-#define	CFG_HZ			1000		/* 1 msec time tick	*/
-#undef  CFG_CLKS_IN_HZ
+#define CONFIG_SYS_CLK_FREQ	CONFIG_SYS_NIOS_CPU_CLK/* 50 MHz core clock	*/
+#define	CONFIG_SYS_HZ			1000		/* 1 msec time tick	*/
+#undef  CONFIG_SYS_CLKS_IN_HZ
 #define	CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
 
 /*------------------------------------------------------------------------
  * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_SDRAM_SIZE != 0)
+#if	(CONFIG_SYS_NIOS_CPU_SDRAM_SIZE != 0)
 
-#define CFG_SDRAM_BASE		CFG_NIOS_CPU_SDRAM_BASE
-#define CFG_SDRAM_SIZE		CFG_NIOS_CPU_SDRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_NIOS_CPU_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		CONFIG_SYS_NIOS_CPU_SDRAM_SIZE
 
 #else
-#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
+#error *** CONFIG_SYS_ERROR: you have to setup any SDRAM in NIOS CPU config
 #endif
 
-#if	defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE)
+#if	defined(CONFIG_SYS_NIOS_CPU_SRAM_BASE) && defined(CONFIG_SYS_NIOS_CPU_SRAM_SIZE)
 
-#define	CFG_SRAM_BASE		CFG_NIOS_CPU_SRAM_BASE
-#define	CFG_SRAM_SIZE		CFG_NIOS_CPU_SRAM_SIZE
+#define	CONFIG_SYS_SRAM_BASE		CONFIG_SYS_NIOS_CPU_SRAM_BASE
+#define	CONFIG_SYS_SRAM_SIZE		CONFIG_SYS_NIOS_CPU_SRAM_SIZE
 
 #else
 
-#undef	CFG_SRAM_BASE
-#undef	CFG_SRAM_SIZE
+#undef	CONFIG_SYS_SRAM_BASE
+#undef	CONFIG_SYS_SRAM_SIZE
 
 #endif
 
-#define CFG_VECT_BASE		CFG_NIOS_CPU_VEC_BASE
+#define CONFIG_SYS_VECT_BASE		CONFIG_SYS_NIOS_CPU_VEC_BASE
 
 /*------------------------------------------------------------------------
  * MEMORY ORGANIZATION - For the most part, you can put things pretty
@@ -85,44 +85,44 @@
  *	-Global data is placed below the heap.
  *	-The stack is placed below global data (&grows down).
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
-#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
 
 /*------------------------------------------------------------------------
  * FLASH (AM29LV065D)
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)
+#if	(CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0)
 
-#define CFG_FLASH_BASE		CFG_NIOS_CPU_FLASH_BASE
-#define CFG_FLASH_SIZE		CFG_NIOS_CPU_FLASH_SIZE
-#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
-#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
-#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
-#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size	*/
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_NIOS_CPU_FLASH_BASE
+#define CONFIG_SYS_FLASH_SIZE		CONFIG_SYS_NIOS_CPU_FLASH_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size	*/
 
 #else
-#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
+#error *** CONFIG_SYS_ERROR: you have to setup any Flash memory in NIOS CPU config
 #endif
 
 /*------------------------------------------------------------------------
  * ENVIRONMENT
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)
+#if	(CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0)
 
 #define	CONFIG_ENV_IS_IN_FLASH	1		/* Environment in flash */
 
 /* Mem addr of environment */
 #if	defined(CONFIG_NIOS_BASE_32)
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 #else
-#error *** CFG_ERROR: you have to setup the environment base address CONFIG_ENV_ADDR
+#error *** CONFIG_SYS_ERROR: you have to setup the environment base address CONFIG_ENV_ADDR
 #endif
 
 #define CONFIG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
@@ -136,26 +136,26 @@
  * NIOS APPLICATION CODE BASE AREA
  *----------------------------------------------------------------------*/
 #if	((CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) == 0x1050000)
-#define	CFG_ADNPESC1_UPDATE_LOAD_ADDR	"0x2000100"
-#define CFG_ADNPESC1_NIOS_APPL_ENTRY	"0x1050000"
-#define CFG_ADNPESC1_NIOS_APPL_IDENT	"0x105000c"
-#define	CFG_ADNPESC1_NIOS_APPL_END	"0x11fffff"
-#define CFG_ADNPESC1_FILESYSTEM_BASE	"0x1200000"
-#define	CFG_ADNPESC1_FILESYSTEM_END	"0x17fffff"
+#define	CONFIG_SYS_ADNPESC1_UPDATE_LOAD_ADDR	"0x2000100"
+#define CONFIG_SYS_ADNPESC1_NIOS_APPL_ENTRY	"0x1050000"
+#define CONFIG_SYS_ADNPESC1_NIOS_APPL_IDENT	"0x105000c"
+#define	CONFIG_SYS_ADNPESC1_NIOS_APPL_END	"0x11fffff"
+#define CONFIG_SYS_ADNPESC1_FILESYSTEM_BASE	"0x1200000"
+#define	CONFIG_SYS_ADNPESC1_FILESYSTEM_END	"0x17fffff"
 #else
-#error *** CFG_ERROR: missing right appl.code base configuration, expand your config.h
+#error *** CONFIG_SYS_ERROR: missing right appl.code base configuration, expand your config.h
 #endif
-#define CFG_ADNPESC1_NIOS_IDENTIFIER	"Nios"
+#define CONFIG_SYS_ADNPESC1_NIOS_IDENTIFIER	"Nios"
 
 /*------------------------------------------------------------------------
  * BOOT ENVIRONMENT
  *----------------------------------------------------------------------*/
 #ifdef	CONFIG_DNPEVA2			/* DNP/EVA2 base board */
-#define	CFG_ADNPESC1_SLED_BOOT_OFF	"sled boot off; "
-#define	CFG_ADNPESC1_SLED_RED_BLINK	"sled red blink; "
+#define	CONFIG_SYS_ADNPESC1_SLED_BOOT_OFF	"sled boot off; "
+#define	CONFIG_SYS_ADNPESC1_SLED_RED_BLINK	"sled red blink; "
 #else
-#define	CFG_ADNPESC1_SLED_BOOT_OFF
-#define	CFG_ADNPESC1_SLED_RED_BLINK
+#define	CONFIG_SYS_ADNPESC1_SLED_BOOT_OFF
+#define	CONFIG_SYS_ADNPESC1_SLED_RED_BLINK
 #endif
 
 #define	CONFIG_BOOTDELAY	5
@@ -163,10 +163,10 @@
 	"if itest.s *$appl_ident_addr == \"$appl_ident_str\"; "		\
 	"then "								\
 		"wd off; "						\
-		CFG_ADNPESC1_SLED_BOOT_OFF				\
+		CONFIG_SYS_ADNPESC1_SLED_BOOT_OFF				\
 		"go $appl_entry_addr; "					\
 	"else "								\
-		CFG_ADNPESC1_SLED_RED_BLINK				\
+		CONFIG_SYS_ADNPESC1_SLED_RED_BLINK				\
 		"echo *** missing \"$appl_ident_str\" at $appl_ident_addr; "\
 		"echo *** invalid application at $appl_entry_addr; "	\
 		"echo *** stop bootup...; "				\
@@ -176,45 +176,45 @@
  * EXTRA ENVIRONMENT
  *----------------------------------------------------------------------*/
 #ifdef	CONFIG_DNPEVA2			/* DNP/EVA2 base board */
-#define	CFG_ADNPESC1_SLED_YELLO_ON	"sled yellow on; "
-#define	CFG_ADNPESC1_SLED_YELLO_OFF	"sled yellow off; "
+#define	CONFIG_SYS_ADNPESC1_SLED_YELLO_ON	"sled yellow on; "
+#define	CONFIG_SYS_ADNPESC1_SLED_YELLO_OFF	"sled yellow off; "
 #else
-#define	CFG_ADNPESC1_SLED_YELLO_ON
-#define	CFG_ADNPESC1_SLED_YELLO_OFF
+#define	CONFIG_SYS_ADNPESC1_SLED_YELLO_ON
+#define	CONFIG_SYS_ADNPESC1_SLED_YELLO_OFF
 #endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"update_allowed=0\0"						\
-	"update_load_addr="	CFG_ADNPESC1_UPDATE_LOAD_ADDR	"\0"	\
-	"appl_entry_addr="	CFG_ADNPESC1_NIOS_APPL_ENTRY	"\0"	\
-	"appl_end_addr="	CFG_ADNPESC1_NIOS_APPL_END	"\0"	\
-	"appl_ident_addr="	CFG_ADNPESC1_NIOS_APPL_IDENT	"\0"	\
-	"appl_ident_str="	CFG_ADNPESC1_NIOS_IDENTIFIER	"\0"	\
+	"update_load_addr="	CONFIG_SYS_ADNPESC1_UPDATE_LOAD_ADDR	"\0"	\
+	"appl_entry_addr="	CONFIG_SYS_ADNPESC1_NIOS_APPL_ENTRY	"\0"	\
+	"appl_end_addr="	CONFIG_SYS_ADNPESC1_NIOS_APPL_END	"\0"	\
+	"appl_ident_addr="	CONFIG_SYS_ADNPESC1_NIOS_APPL_IDENT	"\0"	\
+	"appl_ident_str="	CONFIG_SYS_ADNPESC1_NIOS_IDENTIFIER	"\0"	\
 	"appl_name=ADNPESC1/base32/linux.bin\0"				\
 	"appl_update="							\
 		"if itest.b $update_allowed != 0; "			\
 		"then "							\
-			CFG_ADNPESC1_SLED_YELLO_ON			\
+			CONFIG_SYS_ADNPESC1_SLED_YELLO_ON			\
 			"tftp $update_load_addr $appl_name; "		\
 			"protect off $appl_entry_addr $appl_end_addr; "	\
 			"era $appl_entry_addr $appl_end_addr; "		\
 			"cp.b $update_load_addr $appl_entry_addr $filesize; "\
-			CFG_ADNPESC1_SLED_YELLO_OFF			\
+			CONFIG_SYS_ADNPESC1_SLED_YELLO_OFF			\
 		"else "							\
 			"echo *** update not allowed (update_allowed=$update_allowed); "\
 		"fi\0"							\
-	"fs_base_addr="		CFG_ADNPESC1_FILESYSTEM_BASE	"\0"	\
-	"fs_end_addr="		CFG_ADNPESC1_FILESYSTEM_END	"\0"	\
+	"fs_base_addr="		CONFIG_SYS_ADNPESC1_FILESYSTEM_BASE	"\0"	\
+	"fs_end_addr="		CONFIG_SYS_ADNPESC1_FILESYSTEM_END	"\0"	\
 	"fs_name=ADNPESC1/base32/romfs.img\0"				\
 	"fs_update="							\
 		"if itest.b $update_allowed != 0; "			\
 		"then "							\
-			CFG_ADNPESC1_SLED_YELLO_ON			\
+			CONFIG_SYS_ADNPESC1_SLED_YELLO_ON			\
 			"tftp $update_load_addr $fs_name; "		\
 			"protect off $fs_base_addr $fs_end_addr; "	\
 			"era $fs_base_addr $fs_end_addr; "		\
 			"cp.b $update_load_addr $fs_base_addr $filesize; "\
-			CFG_ADNPESC1_SLED_YELLO_OFF			\
+			CONFIG_SYS_ADNPESC1_SLED_YELLO_OFF			\
 		"else "							\
 			"echo *** update not allowed (update_allowed=$update_allowed); "\
 		"fi\0"							\
@@ -222,7 +222,7 @@
 	"uboot_loadnrun="						\
 		"if ping $serverip; "					\
 		"then "							\
-			CFG_ADNPESC1_SLED_YELLO_ON			\
+			CONFIG_SYS_ADNPESC1_SLED_YELLO_ON			\
 			"tftp $update_load_addr $uboot_name; "		\
 			"wd off; "					\
 			"go $update_load_addr; "			\
@@ -234,92 +234,92 @@
 /*------------------------------------------------------------------------
  * CONSOLE
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_UART_NUMS != 0)
+#if	(CONFIG_SYS_NIOS_CPU_UART_NUMS != 0)
 
-#define CFG_NIOS_CONSOLE	CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
+#define CONFIG_SYS_NIOS_CONSOLE	CONFIG_SYS_NIOS_CPU_UART0 /* 1st UART is Cons. */
 
-#if	(CFG_NIOS_CPU_UART0_BR != 0)
-#define CFG_NIOS_FIXEDBAUD	1		   /* Baudrate is fixed	*/
-#define CONFIG_BAUDRATE		CFG_NIOS_CPU_UART0_BR
+#if	(CONFIG_SYS_NIOS_CPU_UART0_BR != 0)
+#define CONFIG_SYS_NIOS_FIXEDBAUD	1		   /* Baudrate is fixed	*/
+#define CONFIG_BAUDRATE		CONFIG_SYS_NIOS_CPU_UART0_BR
 #else
-#undef	CFG_NIOS_FIXEDBAUD
+#undef	CONFIG_SYS_NIOS_FIXEDBAUD
 #define CONFIG_BAUDRATE		115200
 #endif
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #else
-#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
+#error *** CONFIG_SYS_ERROR: you have to setup at least one UART in NIOS CPU config
 #endif
 
 /*------------------------------------------------------------------------
  * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc  PIT,
  * so an avalon bus timer is required.
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER)
+#if	(CONFIG_SYS_NIOS_CPU_TIMER_NUMS != 0) && defined(CONFIG_SYS_NIOS_CPU_TICK_TIMER)
 
-#if	(CFG_NIOS_CPU_TICK_TIMER == 0)
+#if	(CONFIG_SYS_NIOS_CPU_TICK_TIMER == 0)
 
-#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick	*/
-#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER0_IRQ
+#define CONFIG_SYS_NIOS_TMRBASE	CONFIG_SYS_NIOS_CPU_TIMER0 /* TIMER0 as tick	*/
+#define CONFIG_SYS_NIOS_TMRIRQ		CONFIG_SYS_NIOS_CPU_TIMER0_IRQ
 
-#if	(CFG_NIOS_CPU_TIMER0_FP == 1)		    /* fixed period */
+#if	(CONFIG_SYS_NIOS_CPU_TIMER0_FP == 1)		    /* fixed period */
 
-#if	(CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
-#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
+#if	(CONFIG_SYS_NIOS_CPU_TIMER0_PER >= CONFIG_SYS_HZ)
+#define CONFIG_SYS_NIOS_TMRMS		(CONFIG_SYS_NIOS_CPU_TIMER0_PER / CONFIG_SYS_HZ)
 #else
-#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
+#error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ
 #endif
 
-#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */
+#undef	CONFIG_SYS_NIOS_TMRCNT	/* no preloadable counter value */
 
-#elif	(CFG_NIOS_CPU_TIMER0_FP == 0)		    /* variable period */
+#elif	(CONFIG_SYS_NIOS_CPU_TIMER0_FP == 0)		    /* variable period */
 
-#if	(CFG_HZ <= 1000)
-#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
+#if	(CONFIG_SYS_HZ <= 1000)
+#define CONFIG_SYS_NIOS_TMRMS		(1000 / CONFIG_SYS_HZ)
 #else
-#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
+#error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000
 #endif
 
-#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)
+#define	CONFIG_SYS_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ)
 
 #else
-#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
+#error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER0_FP correct
 #endif
 
-#elif	(CFG_NIOS_CPU_TICK_TIMER == 1)
+#elif	(CONFIG_SYS_NIOS_CPU_TICK_TIMER == 1)
 
-#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick	*/
-#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER1_IRQ
+#define CONFIG_SYS_NIOS_TMRBASE	CONFIG_SYS_NIOS_CPU_TIMER1 /* TIMER1 as tick	*/
+#define CONFIG_SYS_NIOS_TMRIRQ		CONFIG_SYS_NIOS_CPU_TIMER1_IRQ
 
-#if	(CFG_NIOS_CPU_TIMER1_FP == 1)		    /* fixed period */
+#if	(CONFIG_SYS_NIOS_CPU_TIMER1_FP == 1)		    /* fixed period */
 
-#if	(CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
-#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
+#if	(CONFIG_SYS_NIOS_CPU_TIMER1_PER >= CONFIG_SYS_HZ)
+#define CONFIG_SYS_NIOS_TMRMS		(CONFIG_SYS_NIOS_CPU_TIMER1_PER / CONFIG_SYS_HZ)
 #else
-#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
+#error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ
 #endif
 
-#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */
+#undef	CONFIG_SYS_NIOS_TMRCNT	/* no preloadable counter value */
 
-#elif	(CFG_NIOS_CPU_TIMER1_FP == 0)		    /* variable period */
+#elif	(CONFIG_SYS_NIOS_CPU_TIMER1_FP == 0)		    /* variable period */
 
-#if	(CFG_HZ <= 1000)
-#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
+#if	(CONFIG_SYS_HZ <= 1000)
+#define CONFIG_SYS_NIOS_TMRMS		(1000 / CONFIG_SYS_HZ)
 #else
-#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
+#error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000
 #endif
 
-#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)
+#define	CONFIG_SYS_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ)
 
 #else
-#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
+#error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER1_FP correct
 #endif
 
-#endif	/* CFG_NIOS_CPU_TICK_TIMER */
+#endif	/* CONFIG_SYS_NIOS_CPU_TICK_TIMER */
 
 #else
-#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
+#error *** CONFIG_SYS_ERROR: you have to setup at least one TIMER in NIOS CPU config
 #endif
 
 /*------------------------------------------------------------------------
@@ -330,53 +330,53 @@
 #ifdef	CONFIG_HW_WATCHDOG
 
 /* MAX823 supervisor -- watchdog enable port at: */
-#if	(CFG_NIOS_CPU_WDENA_PIO == 0)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO0	/* PIO0		*/
-#elif	(CFG_NIOS_CPU_WDENA_PIO == 1)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO1	/* PIO1		*/
-#elif	(CFG_NIOS_CPU_WDENA_PIO == 2)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO2	/* PIO2		*/
-#elif	(CFG_NIOS_CPU_WDENA_PIO == 3)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO3	/* PIO3		*/
-#elif	(CFG_NIOS_CPU_WDENA_PIO == 4)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO4	/* PIO4		*/
-#elif	(CFG_NIOS_CPU_WDENA_PIO == 5)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO5	/* PIO5		*/
-#elif	(CFG_NIOS_CPU_WDENA_PIO == 6)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO6	/* PIO6		*/
-#elif	(CFG_NIOS_CPU_WDENA_PIO == 7)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO7	/* PIO7		*/
-#elif	(CFG_NIOS_CPU_WDENA_PIO == 8)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO8	/* PIO8		*/
-#elif	(CFG_NIOS_CPU_WDENA_PIO == 9)
-#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO9	/* PIO9		*/
-#else
-#error *** CFG_ERROR: you have to setup at least one WDENA_PIO in NIOS CPU config
+#if	(CONFIG_SYS_NIOS_CPU_WDENA_PIO == 0)
+#define	CONFIG_HW_WDENA_BASE	CONFIG_SYS_NIOS_CPU_PIO0	/* PIO0		*/
+#elif	(CONFIG_SYS_NIOS_CPU_WDENA_PIO == 1)
+#define	CONFIG_HW_WDENA_BASE	CONFIG_SYS_NIOS_CPU_PIO1	/* PIO1		*/
+#elif	(CONFIG_SYS_NIOS_CPU_WDENA_PIO == 2)
+#define	CONFIG_HW_WDENA_BASE	CONFIG_SYS_NIOS_CPU_PIO2	/* PIO2		*/
+#elif	(CONFIG_SYS_NIOS_CPU_WDENA_PIO == 3)
+#define	CONFIG_HW_WDENA_BASE	CONFIG_SYS_NIOS_CPU_PIO3	/* PIO3		*/
+#elif	(CONFIG_SYS_NIOS_CPU_WDENA_PIO == 4)
+#define	CONFIG_HW_WDENA_BASE	CONFIG_SYS_NIOS_CPU_PIO4	/* PIO4		*/
+#elif	(CONFIG_SYS_NIOS_CPU_WDENA_PIO == 5)
+#define	CONFIG_HW_WDENA_BASE	CONFIG_SYS_NIOS_CPU_PIO5	/* PIO5		*/
+#elif	(CONFIG_SYS_NIOS_CPU_WDENA_PIO == 6)
+#define	CONFIG_HW_WDENA_BASE	CONFIG_SYS_NIOS_CPU_PIO6	/* PIO6		*/
+#elif	(CONFIG_SYS_NIOS_CPU_WDENA_PIO == 7)
+#define	CONFIG_HW_WDENA_BASE	CONFIG_SYS_NIOS_CPU_PIO7	/* PIO7		*/
+#elif	(CONFIG_SYS_NIOS_CPU_WDENA_PIO == 8)
+#define	CONFIG_HW_WDENA_BASE	CONFIG_SYS_NIOS_CPU_PIO8	/* PIO8		*/
+#elif	(CONFIG_SYS_NIOS_CPU_WDENA_PIO == 9)
+#define	CONFIG_HW_WDENA_BASE	CONFIG_SYS_NIOS_CPU_PIO9	/* PIO9		*/
+#else
+#error *** CONFIG_SYS_ERROR: you have to setup at least one WDENA_PIO in NIOS CPU config
 #endif
 
 /* MAX823 supervisor -- watchdog trigger port at: */
-#if	(CFG_NIOS_CPU_WDTOG_PIO == 0)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO0	/* PIO0		*/
-#elif	(CFG_NIOS_CPU_WDTOG_PIO == 1)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO1	/* PIO1		*/
-#elif	(CFG_NIOS_CPU_WDTOG_PIO == 2)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO2	/* PIO2		*/
-#elif	(CFG_NIOS_CPU_WDTOG_PIO == 3)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO3	/* PIO3		*/
-#elif	(CFG_NIOS_CPU_WDTOG_PIO == 4)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO4	/* PIO4		*/
-#elif	(CFG_NIOS_CPU_WDTOG_PIO == 5)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO5	/* PIO5		*/
-#elif	(CFG_NIOS_CPU_WDTOG_PIO == 6)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO6	/* PIO6		*/
-#elif	(CFG_NIOS_CPU_WDTOG_PIO == 7)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO7	/* PIO7		*/
-#elif	(CFG_NIOS_CPU_WDTOG_PIO == 8)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO8	/* PIO8		*/
-#elif	(CFG_NIOS_CPU_WDTOG_PIO == 9)
-#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO9	/* PIO9		*/
-#else
-#error *** CFG_ERROR: you have to setup at least one WDTOG_PIO in NIOS CPU config
+#if	(CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 0)
+#define	CONFIG_HW_WDTOG_BASE	CONFIG_SYS_NIOS_CPU_PIO0	/* PIO0		*/
+#elif	(CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 1)
+#define	CONFIG_HW_WDTOG_BASE	CONFIG_SYS_NIOS_CPU_PIO1	/* PIO1		*/
+#elif	(CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 2)
+#define	CONFIG_HW_WDTOG_BASE	CONFIG_SYS_NIOS_CPU_PIO2	/* PIO2		*/
+#elif	(CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 3)
+#define	CONFIG_HW_WDTOG_BASE	CONFIG_SYS_NIOS_CPU_PIO3	/* PIO3		*/
+#elif	(CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 4)
+#define	CONFIG_HW_WDTOG_BASE	CONFIG_SYS_NIOS_CPU_PIO4	/* PIO4		*/
+#elif	(CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 5)
+#define	CONFIG_HW_WDTOG_BASE	CONFIG_SYS_NIOS_CPU_PIO5	/* PIO5		*/
+#elif	(CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 6)
+#define	CONFIG_HW_WDTOG_BASE	CONFIG_SYS_NIOS_CPU_PIO6	/* PIO6		*/
+#elif	(CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 7)
+#define	CONFIG_HW_WDTOG_BASE	CONFIG_SYS_NIOS_CPU_PIO7	/* PIO7		*/
+#elif	(CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 8)
+#define	CONFIG_HW_WDTOG_BASE	CONFIG_SYS_NIOS_CPU_PIO8	/* PIO8		*/
+#elif	(CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 9)
+#define	CONFIG_HW_WDTOG_BASE	CONFIG_SYS_NIOS_CPU_PIO9	/* PIO9		*/
+#else
+#error *** CONFIG_SYS_ERROR: you have to setup at least one WDTOG_PIO in NIOS CPU config
 #endif
 
 #if	defined(CONFIG_NIOS_BASE_32)		/* NIOS CPU specifics	*/
@@ -384,7 +384,7 @@
 #define	CONFIG_HW_WDTOG_BIT		0	/* WD trigger @ Bit 0	*/
 #define	CONFIG_HW_WDPORT_WRONLY	1	/* each WD port wr/only*/
 #else
-#error *** CFG_ERROR: missing watchdog bit configuration, expand your config.h
+#error *** CONFIG_SYS_ERROR: missing watchdog bit configuration, expand your config.h
 #endif
 
 #endif	/* CONFIG_HW_WATCHDOG */
@@ -392,14 +392,14 @@
 /*------------------------------------------------------------------------
  * SERIAL PERIPHAREL INTERFACE
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_SPI_NUMS == 1)
+#if	(CONFIG_SYS_NIOS_CPU_SPI_NUMS == 1)
 
 #define	CONFIG_NIOS_SPI		1		/* SPI support active	*/
-#define	CFG_NIOS_SPIBASE	CFG_NIOS_CPU_SPI0
-#define	CFG_NIOS_SPIBITS	CFG_NIOS_CPU_SPI0_BITS
+#define	CONFIG_SYS_NIOS_SPIBASE	CONFIG_SYS_NIOS_CPU_SPI0
+#define	CONFIG_SYS_NIOS_SPIBITS	CONFIG_SYS_NIOS_CPU_SPI0_BITS
 
 #define	CONFIG_RTC_DS1306	1	/* Dallas 1306 real time clock	*/
-#define CFG_SPI_RTC_DEVID	0	/*        as 1st SPI device	*/
+#define CONFIG_SYS_SPI_RTC_DEVID	0	/*        as 1st SPI device	*/
 
 #else
 #undef	CONFIG_NIOS_SPI				/* NO SPI support	*/
@@ -408,29 +408,29 @@
 /*------------------------------------------------------------------------
  * Ethernet -- needs work!
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_LAN_NUMS == 1)
+#if	(CONFIG_SYS_NIOS_CPU_LAN_NUMS == 1)
 
-#if	(CFG_NIOS_CPU_LAN0_TYPE == 0)		/* LAN91C111		*/
+#if	(CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 0)		/* LAN91C111		*/
 
 #define	CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
 #undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
-#define	CONFIG_SMC91111_BASE	(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
+#define	CONFIG_SMC91111_BASE	(CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS)
 
-#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
+#if	(CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32)
 #define	CONFIG_SMC_USE_32_BIT	1
 #else	/* no */
 #undef	CONFIG_SMC_USE_32_BIT
 #endif
 
-#elif	(CFG_NIOS_CPU_LAN0_TYPE == 1)		/* CS8900A		*/
+#elif	(CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 1)		/* CS8900A		*/
 
 	/********************************************/
 	/* !!! CS8900 is __not__ tested on NIOS !!! */
 	/********************************************/
 #define	CONFIG_DRIVER_CS8900			/* Using CS8900		*/
-#define	CS8900_BASE		(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
+#define	CS8900_BASE		(CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS)
 
-#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
+#if	(CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32)
 #undef	CS8900_BUS16
 #define	CS8900_BUS32		1
 #else	/* no */
@@ -439,7 +439,7 @@
 #endif
 
 #else
-#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
+#error *** CONFIG_SYS_ERROR: invalid LAN0 chip type, check your NIOS CPU config
 #endif
 
 #define CONFIG_ETHADDR		02:80:ae:20:60:6f
@@ -448,80 +448,80 @@
 #define CONFIG_SERVERIP		192.168.161.85
 
 #else
-#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
+#error *** CONFIG_SYS_ERROR: you have to setup just one LAN only or expand your config.h
 #endif
 
 /*------------------------------------------------------------------------
  * STATUS LEDs
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO)
+#if	(CONFIG_SYS_NIOS_CPU_PIO_NUMS != 0) && defined(CONFIG_SYS_NIOS_CPU_LED_PIO)
 
-#if	(CFG_NIOS_CPU_LED_PIO == 0)
+#if	(CONFIG_SYS_NIOS_CPU_LED_PIO == 0)
 
-#define	STATUS_LED_BASE			CFG_NIOS_CPU_PIO0
-#define	STATUS_LED_BITS			CFG_NIOS_CPU_PIO0_BITS
+#define	STATUS_LED_BASE			CONFIG_SYS_NIOS_CPU_PIO0
+#define	STATUS_LED_BITS			CONFIG_SYS_NIOS_CPU_PIO0_BITS
 #define	STATUS_LED_ACTIVE		1 /* LED on for bit == 1 */
 
-#if	(CFG_NIOS_CPU_PIO0_TYPE == 1)
+#if	(CONFIG_SYS_NIOS_CPU_PIO0_TYPE == 1)
 #define	STATUS_LED_WRONLY		1
 #else
 #undef	STATUS_LED_WRONLY
 #endif
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 1)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 1)
 
-#define	STATUS_LED_BASE			CFG_NIOS_CPU_PIO1
-#define	STATUS_LED_BITS			CFG_NIOS_CPU_PIO1_BITS
+#define	STATUS_LED_BASE			CONFIG_SYS_NIOS_CPU_PIO1
+#define	STATUS_LED_BITS			CONFIG_SYS_NIOS_CPU_PIO1_BITS
 #define	STATUS_LED_ACTIVE		1 /* LED on for bit == 1 */
 
-#if	(CFG_NIOS_CPU_PIO1_TYPE == 1)
+#if	(CONFIG_SYS_NIOS_CPU_PIO1_TYPE == 1)
 #define	STATUS_LED_WRONLY		1
 #else
 #undef	STATUS_LED_WRONLY
 #endif
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 2)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 2)
 
-#define	STATUS_LED_BASE			CFG_NIOS_CPU_PIO2
-#define	STATUS_LED_BITS			CFG_NIOS_CPU_PIO2_BITS
+#define	STATUS_LED_BASE			CONFIG_SYS_NIOS_CPU_PIO2
+#define	STATUS_LED_BITS			CONFIG_SYS_NIOS_CPU_PIO2_BITS
 #define	STATUS_LED_ACTIVE		1 /* LED on for bit == 1 */
 
-#if	(CFG_NIOS_CPU_PIO2_TYPE == 1)
+#if	(CONFIG_SYS_NIOS_CPU_PIO2_TYPE == 1)
 #define	STATUS_LED_WRONLY		1
 #else
 #undef	STATUS_LED_WRONLY
 #endif
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 3)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 3)
 
-#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO3 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 4)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 4)
 
-#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO4 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 5)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 5)
 
-#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO5 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 6)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 6)
 
-#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO6 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 7)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 7)
 
-#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO7 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 8)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 8)
 
-#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO8 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 9)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 9)
 
-#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO9 not supported, expand your config.h
 
 #else
-#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
+#error *** CONFIG_SYS_ERROR: you have to set CONFIG_SYS_NIOS_CPU_LED_PIO in right case
 #endif
 
 #define	CONFIG_STATUS_LED		1 /* enable status led driver */
@@ -529,39 +529,39 @@
 #define	STATUS_LED_BIT			(1 << 0)	/* LED[0] */
 #define	STATUS_LED_STATE		STATUS_LED_BLINKING
 #define	STATUS_LED_BOOT_STATE		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD		(CFG_HZ / 2)	/* ca. 1 Hz */
+#define	STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)	/* ca. 1 Hz */
 #define	STATUS_LED_BOOT			0		/* boot LED */
 
 #if	(STATUS_LED_BITS > 1)
 #define	STATUS_LED_BIT1			(1 << 1)	/* LED[1] */
 #define	STATUS_LED_STATE1		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD1		(CFG_HZ / 10)	/* ca. 5 Hz */
+#define	STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 10)	/* ca. 5 Hz */
 #define	STATUS_LED_RED			1		/* fail LED */
 #endif
 
 #if	(STATUS_LED_BITS > 2)
 #define	STATUS_LED_BIT2			(1 << 2)	/* LED[2] */
 #define	STATUS_LED_STATE2		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD2		(CFG_HZ / 2)	/* ca. 1 Hz */
+#define	STATUS_LED_PERIOD2		(CONFIG_SYS_HZ / 2)	/* ca. 1 Hz */
 #define	STATUS_LED_YELLOW		2		/* info LED */
 #endif
 
 #if	(STATUS_LED_BITS > 3)
 #define	STATUS_LED_BIT3			(1 << 3)	/* LED[3] */
 #define	STATUS_LED_STATE3		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD3		(CFG_HZ / 2)	/* ca. 1 Hz */
+#define	STATUS_LED_PERIOD3		(CONFIG_SYS_HZ / 2)	/* ca. 1 Hz */
 #define	STATUS_LED_GREEN		3		/* info LED */
 #endif
 
 #define	STATUS_LED_PAR			1 /* makes status_led.h happy */
 
-#endif	/* CFG_NIOS_CPU_PIO_NUMS */
+#endif	/* CONFIG_SYS_NIOS_CPU_PIO_NUMS */
 
 /*------------------------------------------------------------------------
  * Diagnostics / Power On Self Tests
  *----------------------------------------------------------------------*/
-#define	CONFIG_POST			CFG_POST_RTC
-#define	CFG_NIOS_POST_WORD_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define	CONFIG_POST			CONFIG_SYS_POST_RTC
+#define	CONFIG_SYS_NIOS_POST_WORD_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 
 /*
  * BOOTP options
@@ -595,7 +595,7 @@
 #undef CONFIG_CMD_NFS
 #undef CONFIG_CMD_XIMG
 
-#if (CFG_NIOS_CPU_SPI_NUMS == 1)
+#if (CONFIG_SYS_NIOS_CPU_SPI_NUMS == 1)
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_SPI
 #endif
@@ -610,62 +610,62 @@
 /*------------------------------------------------------------------------
  * MISC
  *----------------------------------------------------------------------*/
-#define	CFG_LONGHELP			    /* undef to save memory	*/
-#define	CFG_HUSH_PARSER		1	    /* use "hush" command parser
+#define	CONFIG_SYS_LONGHELP			    /* undef to save memory	*/
+#define	CONFIG_SYS_HUSH_PARSER		1	    /* use "hush" command parser
 					       undef to save memory	*/
-#define	CFG_PROMPT		"ADNPESC1 > " /* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		1024	    /* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		64	    /* max number of command args*/
-#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size */
+#define	CONFIG_SYS_PROMPT		"ADNPESC1 > " /* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		1024	    /* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		64	    /* max number of command args*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
 
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"[]> "
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"[]> "
 #endif
 
 /* Default load address	*/
-#if	(CFG_SRAM_SIZE != 0)
+#if	(CONFIG_SYS_SRAM_SIZE != 0)
 
 /* default in SRAM */
-#define	CFG_LOAD_ADDR		CFG_SRAM_BASE
+#define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SRAM_BASE
 
-#elif	(CFG_SDRAM_SIZE != 0)
+#elif	(CONFIG_SYS_SDRAM_SIZE != 0)
 
 /* default in SDRAM */
-#if	(CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
+#if	(CONFIG_SYS_SDRAM_BASE == CONFIG_SYS_NIOS_CPU_VEC_BASE)
 #if 1
-#define	CFG_LOAD_ADDR		(CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
+#define	CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_NIOS_CPU_VEC_SIZE)
 #else
-#define	CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 0x400000)
+#define	CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x400000)
 #endif
 #else
-#define	CFG_LOAD_ADDR		CFG_SDRAM_BASE
+#define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
 #endif
 
 #else
-#undef	CFG_LOAD_ADDR		/* force error break */
+#undef	CONFIG_SYS_LOAD_ADDR		/* force error break */
 #endif
 
 /* MEM test area */
-#if	(CFG_SDRAM_SIZE != 0)
+#if	(CONFIG_SYS_SDRAM_SIZE != 0)
 
 /* SDRAM begin to stack area (1MB stack) */
-#if	(CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
+#if	(CONFIG_SYS_SDRAM_BASE == CONFIG_SYS_NIOS_CPU_VEC_BASE)
 #if 0
-#define	CFG_MEMTEST_START	(CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
+#define	CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_NIOS_CPU_VEC_SIZE)
 #else
-#define	CFG_MEMTEST_START	(CFG_SDRAM_BASE + 0x400000)
+#define	CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0x400000)
 #endif
 #else
-#define	CFG_MEMTEST_START	CFG_SDRAM_BASE
+#define	CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
 #endif
 
-#define	CFG_MEMTEST_END		(CFG_INIT_SP - (1024 * 1024))
-#define	CFG_MEMTEST_END		(CFG_INIT_SP - (1024 * 1024))
+#define	CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - (1024 * 1024))
+#define	CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - (1024 * 1024))
 
 #else
-#undef	CFG_MEMTEST_START	/* force error break */
-#undef	CFG_MEMTEST_END
+#undef	CONFIG_SYS_MEMTEST_START	/* force error break */
+#undef	CONFIG_SYS_MEMTEST_END
 #endif
 
 /*
diff --git a/include/configs/ADNPESC1_base_32.h b/include/configs/ADNPESC1_base_32.h
index c8428b4..1fe8d09 100644
--- a/include/configs/ADNPESC1_base_32.h
+++ b/include/configs/ADNPESC1_base_32.h
@@ -30,402 +30,402 @@
  * Here we must define CPU dependencies. Any unsupported option have to
  * be undefined or defined with zero, example CPU without data cache / OCI:
  *
- *	#define	CFG_NIOS_CPU_ICACHE	4096
- *	#define	CFG_NIOS_CPU_DCACHE	0
- *	#undef	CFG_NIOS_CPU_OCI_BASE
- *	#undef	CFG_NIOS_CPU_OCI_SIZE
+ *	#define	CONFIG_SYS_NIOS_CPU_ICACHE	4096
+ *	#define	CONFIG_SYS_NIOS_CPU_DCACHE	0
+ *	#undef	CONFIG_SYS_NIOS_CPU_OCI_BASE
+ *	#undef	CONFIG_SYS_NIOS_CPU_OCI_SIZE
  */
 
 /* CPU core */
-#define	CFG_NIOS_CPU_CLK	50000000	/* NIOS CPU clock	*/
-#define	CFG_NIOS_CPU_ICACHE	(0)		/* instruction cache	*/
-#define	CFG_NIOS_CPU_DCACHE	(0)		/* data cache		*/
-#define	CFG_NIOS_CPU_REG_NUMS	512		/* number of register	*/
-#define	CFG_NIOS_CPU_MUL	0		/* 16x16 MUL:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_CLK	50000000	/* NIOS CPU clock	*/
+#define	CONFIG_SYS_NIOS_CPU_ICACHE	(0)		/* instruction cache	*/
+#define	CONFIG_SYS_NIOS_CPU_DCACHE	(0)		/* data cache		*/
+#define	CONFIG_SYS_NIOS_CPU_REG_NUMS	512		/* number of register	*/
+#define	CONFIG_SYS_NIOS_CPU_MUL	0		/* 16x16 MUL:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_MSTEP	1		/* 16x16 MSTEP:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_MSTEP	1		/* 16x16 MSTEP:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_STACK	0x03000000	/* stack top	addr	*/
-#define	CFG_NIOS_CPU_VEC_BASE	0x02000000	/* IRQ vectors	addr	*/
-#define	CFG_NIOS_CPU_VEC_SIZE	256		/*		size	*/
-#define	CFG_NIOS_CPU_VEC_NUMS	64		/*		numbers	*/
-#define	CFG_NIOS_CPU_RST_VECT	0x00000000	/* RESET vector	addr	*/
-#define	CFG_NIOS_CPU_DBG_CORE	0		/* CPU debug:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_STACK	0x03000000	/* stack top	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_VEC_BASE	0x02000000	/* IRQ vectors	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_VEC_SIZE	256		/*		size	*/
+#define	CONFIG_SYS_NIOS_CPU_VEC_NUMS	64		/*		numbers	*/
+#define	CONFIG_SYS_NIOS_CPU_RST_VECT	0x00000000	/* RESET vector	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_DBG_CORE	0		/* CPU debug:	no(0)	*/
 						/*		yes(1)	*/
 
 /* The offset address in flash to check for the Nios signature "Ni".
  * (see GM_FlashExec in germs_monitor.s) */
-#define	CFG_NIOS_CPU_EXES_OFFS	0x0C
+#define	CONFIG_SYS_NIOS_CPU_EXES_OFFS	0x0C
 
 /* on-chip extensions */
-#undef	CFG_NIOS_CPU_RAM_BASE			/* on chip RAM	addr	*/
-#undef	CFG_NIOS_CPU_RAM_SIZE			/* 64 KB	size	*/
+#undef	CONFIG_SYS_NIOS_CPU_RAM_BASE			/* on chip RAM	addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_RAM_SIZE			/* 64 KB	size	*/
 
-#define	CFG_NIOS_CPU_ROM_BASE	0x00000000	/* on chip ROM	addr	*/
-#define	CFG_NIOS_CPU_ROM_SIZE	(2 * 1024)	/*  2 KB	size	*/
+#define	CONFIG_SYS_NIOS_CPU_ROM_BASE	0x00000000	/* on chip ROM	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_ROM_SIZE	(2 * 1024)	/*  2 KB	size	*/
 
-#undef	CFG_NIOS_CPU_OCI_BASE			/* OCI core	addr	*/
-#undef	CFG_NIOS_CPU_OCI_SIZE			/*		size	*/
+#undef	CONFIG_SYS_NIOS_CPU_OCI_BASE			/* OCI core	addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_OCI_SIZE			/*		size	*/
 
 /* timer */
-#define	CFG_NIOS_CPU_TIMER_NUMS	1		/* number of timer	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER_NUMS	1		/* number of timer	*/
 
-#define	CFG_NIOS_CPU_TIMER0	0x00000840	/* TIMER0	addr	*/
-#define	CFG_NIOS_CPU_TIMER0_IRQ	16		/*		IRQ	*/
-#define	CFG_NIOS_CPU_TIMER0_PER	1000		/*  periode	usec	*/
-#define	CFG_NIOS_CPU_TIMER0_AR	0		/*  always run:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0	0x00000840	/* TIMER0	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_IRQ	16		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_PER	1000		/*  periode	usec	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_AR	0		/*  always run:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER0_FP	0		/*  fixed per:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_FP	0		/*  fixed per:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER0_SS	1		/*  snaphot:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_SS	1		/*  snaphot:	no(0)	*/
 						/*		yes(1)	*/
 
 /* serial i/o */
-#define	CFG_NIOS_CPU_UART_NUMS	2		/* number of uarts	*/
-
-#define	CFG_NIOS_CPU_UART0	0x00000800	/* UART0	addr	*/
-#define	CFG_NIOS_CPU_UART0_IRQ	17		/*		IRQ	*/
-#define	CFG_NIOS_CPU_UART0_BR	115200		/*  baudrate	var(0)	*/
-#define	CFG_NIOS_CPU_UART0_DB	8		/*  data bit		*/
-#define	CFG_NIOS_CPU_UART0_SB	1		/*  stop bit		*/
-#define	CFG_NIOS_CPU_UART0_PA	0		/*  parity	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART_NUMS	2		/* number of uarts	*/
+
+#define	CONFIG_SYS_NIOS_CPU_UART0	0x00000800	/* UART0	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_IRQ	17		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_BR	115200		/*  baudrate	var(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_DB	8		/*  data bit		*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_SB	1		/*  stop bit		*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_PA	0		/*  parity	none(0)	*/
 						/*		odd(1)	*/
 						/*		even(2)	*/
-#define	CFG_NIOS_CPU_UART0_HS	1		/*  handshake:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_HS	1		/*  handshake:	no(0)	*/
 						/*		crts(1)	*/
-#define	CFG_NIOS_CPU_UART0_EOP	0		/*  eop reg:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_EOP	0		/*  eop reg:	no(0)	*/
 						/*		yes(1)	*/
 
-#define	CFG_NIOS_CPU_UART1	0x00000820	/* UART1	addr	*/
-#define	CFG_NIOS_CPU_UART1_IRQ	18		/*		IRQ	*/
-#define	CFG_NIOS_CPU_UART1_BR	115200		/*  baudrate	var(0)	*/
-#define	CFG_NIOS_CPU_UART1_DB	8		/*  data bit		*/
-#define	CFG_NIOS_CPU_UART1_SB	1		/*  stop bit		*/
-#define	CFG_NIOS_CPU_UART1_PA	0		/*  parity	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART1	0x00000820	/* UART1	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_UART1_IRQ	18		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_UART1_BR	115200		/*  baudrate	var(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART1_DB	8		/*  data bit		*/
+#define	CONFIG_SYS_NIOS_CPU_UART1_SB	1		/*  stop bit		*/
+#define	CONFIG_SYS_NIOS_CPU_UART1_PA	0		/*  parity	none(0)	*/
 						/*		odd(1)	*/
 						/*		even(2)	*/
-#define	CFG_NIOS_CPU_UART1_HS	0		/*  handshake:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART1_HS	0		/*  handshake:	no(0)	*/
 						/*		crts(1)	*/
-#define	CFG_NIOS_CPU_UART1_EOP	0		/*  eop reg:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART1_EOP	0		/*  eop reg:	no(0)	*/
 						/*		yes(1)	*/
 
 /* serial peripheral i/o */
-#define	CFG_NIOS_CPU_SPI_NUMS	1		/* number of spis	*/
+#define	CONFIG_SYS_NIOS_CPU_SPI_NUMS	1		/* number of spis	*/
 
-#define	CFG_NIOS_CPU_SPI0	0x000008c0	/* SPI0		addr	*/
-#define	CFG_NIOS_CPU_SPI0_IRQ	25		/*		IRQ	*/
-#define	CFG_NIOS_CPU_SPI0_BITS	16		/*  data bit		*/
-#define	CFG_NIOS_CPU_SPI0_MA	1		/*  is master:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_SPI0	0x000008c0	/* SPI0		addr	*/
+#define	CONFIG_SYS_NIOS_CPU_SPI0_IRQ	25		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_SPI0_BITS	16		/*  data bit		*/
+#define	CONFIG_SYS_NIOS_CPU_SPI0_MA	1		/*  is master:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_SPI0_SLN	1		/*  num slaves		*/
-#define	CFG_NIOS_CPU_SPI0_TCLK	250000		/*  clock (Hz)		*/
-#define	CFG_NIOS_CPU_SPI0_TDELAY 2		/*  delay (usec)	*/
-#define	CFG_NIOS_CPU_SPI0_FB	0		/*  first bit	msb(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_SPI0_SLN	1		/*  num slaves		*/
+#define	CONFIG_SYS_NIOS_CPU_SPI0_TCLK	250000		/*  clock (Hz)		*/
+#define	CONFIG_SYS_NIOS_CPU_SPI0_TDELAY 2		/*  delay (usec)	*/
+#define	CONFIG_SYS_NIOS_CPU_SPI0_FB	0		/*  first bit	msb(0)	*/
 						/*		lsb(1)	*/
 
 /* parallel i/o */
-#define	CFG_NIOS_CPU_PIO_NUMS	14		/* number of parports	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO_NUMS	14		/* number of parports	*/
 
-#define	CFG_NIOS_CPU_PIO0	0x00000860	/* PIO0		addr	*/
-#undef	CFG_NIOS_CPU_PIO0_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO0_BITS	8		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO0_TYPE	0		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0	0x00000860	/* PIO0		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO0_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_BITS	8		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_TYPE	0		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO0_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO0_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO0_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO1	0x00000870	/* PIO1		addr	*/
-#undef	CFG_NIOS_CPU_PIO1_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO1_BITS	8		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO1_TYPE	0		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1	0x00000870	/* PIO1		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO1_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_BITS	8		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_TYPE	0		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO1_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO1_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO1_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO2	0x00000880	/* PIO2		addr	*/
-#undef	CFG_NIOS_CPU_PIO2_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO2_BITS	4		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO2_TYPE	0		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO2	0x00000880	/* PIO2		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO2_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO2_BITS	4		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO2_TYPE	0		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO2_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO2_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO2_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO2_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO2_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO2_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO3	0x00000890	/* PIO3		addr	*/
-#undef	CFG_NIOS_CPU_PIO3_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO3_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO3_TYPE	2		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3	0x00000890	/* PIO3		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO3_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_TYPE	2		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO3_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO3_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO3_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO3	0x00000890	/* PIO3		addr	*/
-#undef	CFG_NIOS_CPU_PIO3_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO3_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO3_TYPE	2		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3	0x00000890	/* PIO3		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO3_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_TYPE	2		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO3_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO3_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO3_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO4	0x000008a0	/* PIO4		addr	*/
-#undef	CFG_NIOS_CPU_PIO4_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO4_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO4_TYPE	1		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO4	0x000008a0	/* PIO4		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO4_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO4_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO4_TYPE	1		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO4_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO4_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO4_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO4_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO4_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO4_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO5	0x000008b0	/* PIO5		addr	*/
-#undef	CFG_NIOS_CPU_PIO5_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO5_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO5_TYPE	1		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5	0x000008b0	/* PIO5		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO5_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5_TYPE	1		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO5_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO5_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO5_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO6	0x00000900	/* PIO6		addr	*/
-#define	CFG_NIOS_CPU_PIO6_IRQ	20		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO6_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO6_TYPE	2		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO6	0x00000900	/* PIO6		addr	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO6_IRQ	20		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO6_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO6_TYPE	2		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO6_CAP	1		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO6_CAP	1		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO6_EDGE	2		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO6_EDGE	2		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO6_ITYPE	1		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO6_ITYPE	1		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO7	0x00000910	/* PIO7		addr	*/
-#define	CFG_NIOS_CPU_PIO7_IRQ	31		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO7_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO7_TYPE	2		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO7	0x00000910	/* PIO7		addr	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO7_IRQ	31		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO7_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO7_TYPE	2		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO7_CAP	1		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO7_CAP	1		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO7_EDGE	2		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO7_EDGE	2		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO7_ITYPE	1		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO7_ITYPE	1		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO8	0x00000920	/* PIO8		addr	*/
-#define	CFG_NIOS_CPU_PIO8_IRQ	32		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO8_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO8_TYPE	2		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO8	0x00000920	/* PIO8		addr	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO8_IRQ	32		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO8_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO8_TYPE	2		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO8_CAP	1		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO8_CAP	1		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO8_EDGE	2		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO8_EDGE	2		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO8_ITYPE	1		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO8_ITYPE	1		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO9	0x00000930	/* PIO9		addr	*/
-#define	CFG_NIOS_CPU_PIO9_IRQ	33		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO9_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO9_TYPE	2		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO9	0x00000930	/* PIO9		addr	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO9_IRQ	33		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO9_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO9_TYPE	2		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO9_CAP	1		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO9_CAP	1		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO9_EDGE	2		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO9_EDGE	2		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO9_ITYPE	1		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO9_ITYPE	1		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO10	0x00000940	/* PIO10	addr	*/
-#define	CFG_NIOS_CPU_PIO10_IRQ	34		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO10_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO10_TYPE	2		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO10	0x00000940	/* PIO10	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO10_IRQ	34		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO10_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO10_TYPE	2		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO10_CAP	1		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO10_CAP	1		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO10_EDGE	2		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO10_EDGE	2		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO10_ITYPE 1		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO10_ITYPE 1		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO11	0x00000950	/* PIO11	addr	*/
-#define	CFG_NIOS_CPU_PIO11_IRQ	35		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO11_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO11_TYPE	2		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO11	0x00000950	/* PIO11	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO11_IRQ	35		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO11_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO11_TYPE	2		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO11_CAP	1		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO11_CAP	1		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO11_EDGE	2		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO11_EDGE	2		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO11_ITYPE 1		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO11_ITYPE 1		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO12	0x00000960	/* PIO12	addr	*/
-#define	CFG_NIOS_CPU_PIO12_IRQ	36		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO12_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO12_TYPE	2		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO12	0x00000960	/* PIO12	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO12_IRQ	36		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO12_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO12_TYPE	2		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO12_CAP	1		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO12_CAP	1		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO12_EDGE	2		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO12_EDGE	2		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO12_ITYPE 1		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO12_ITYPE 1		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO13	0x00000970	/* PIO113	addr	*/
-#define	CFG_NIOS_CPU_PIO13_IRQ	37		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO13_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO13_TYPE	2		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO13	0x00000970	/* PIO113	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO13_IRQ	37		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO13_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO13_TYPE	2		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO13_CAP	1		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO13_CAP	1		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO13_EDGE	2		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO13_EDGE	2		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO13_ITYPE 1		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO13_ITYPE 1		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
 /* IDE i/f */
-#define	CFG_NIOS_CPU_IDE_NUMS	2		/* number of IDE contr.	*/
+#define	CONFIG_SYS_NIOS_CPU_IDE_NUMS	2		/* number of IDE contr.	*/
 
-#define	CFG_NIOS_CPU_IDE0	0x00001000	/* IDE0		addr	*/
-#define	CFG_NIOS_CPU_IDE0_IRQ	36		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_IDE0	0x00001000	/* IDE0		addr	*/
+#define	CONFIG_SYS_NIOS_CPU_IDE0_IRQ	36		/*		IRQ	*/
 
-#define	CFG_NIOS_CPU_IDE1	0x00001020	/* IDE1		addr	*/
-#define	CFG_NIOS_CPU_IDE1_IRQ	37		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_IDE1	0x00001020	/* IDE1		addr	*/
+#define	CONFIG_SYS_NIOS_CPU_IDE1_IRQ	37		/*		IRQ	*/
 
 /* memory accessibility */
-#undef	CFG_NIOS_CPU_SRAM_BASE			/* board SRAM	addr	*/
-#undef	CFG_NIOS_CPU_SRAM_SIZE			/*  1 MB	size	*/
+#undef	CONFIG_SYS_NIOS_CPU_SRAM_BASE			/* board SRAM	addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_SRAM_SIZE			/*  1 MB	size	*/
 
-#define	CFG_NIOS_CPU_SDRAM_BASE	0x02000000	/* board SDRAM	addr	*/
-#define	CFG_NIOS_CPU_SDRAM_SIZE	(16*1024*1024)	/* 16 MB	size	*/
+#define	CONFIG_SYS_NIOS_CPU_SDRAM_BASE	0x02000000	/* board SDRAM	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_SDRAM_SIZE	(16*1024*1024)	/* 16 MB	size	*/
 
-#define	CFG_NIOS_CPU_FLASH_BASE	0x01000000	/* board Flash	addr	*/
-#define	CFG_NIOS_CPU_FLASH_SIZE	(8*1024*1024)	/*  8 MB	size	*/
+#define	CONFIG_SYS_NIOS_CPU_FLASH_BASE	0x01000000	/* board Flash	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_FLASH_SIZE	(8*1024*1024)	/*  8 MB	size	*/
 
 /* LAN */
-#define	CFG_NIOS_CPU_LAN_NUMS	1		/* number of LAN i/f	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN_NUMS	1		/* number of LAN i/f	*/
 
-#define	CFG_NIOS_CPU_LAN0_BASE	0x00010000	/* LAN0		addr	*/
-#define	CFG_NIOS_CPU_LAN0_OFFS	(0)		/*		offset	*/
-#define	CFG_NIOS_CPU_LAN0_IRQ	20		/*		IRQ	*/
-#define	CFG_NIOS_CPU_LAN0_BUSW	16		/*	        buswidth*/
-#define	CFG_NIOS_CPU_LAN0_TYPE	0		/*	smc91111(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_BASE	0x00010000	/* LAN0		addr	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_OFFS	(0)		/*		offset	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_IRQ	20		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_BUSW	16		/*	        buswidth*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_TYPE	0		/*	smc91111(0)	*/
 						/*	cs8900(1)	*/
 						/* ex:	openmac(2)	*/
 						/* ex:	alteramac(3)	*/
 
 /* external extension */
-#define	CFG_NIOS_CPU_CS0_BASE	0x40000000	/* board EXT0	addr	*/
-#define	CFG_NIOS_CPU_CS0_SIZE	(16*1024*1024)	/*  max. 16 MB	size	*/
+#define	CONFIG_SYS_NIOS_CPU_CS0_BASE	0x40000000	/* board EXT0	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_CS0_SIZE	(16*1024*1024)	/*  max. 16 MB	size	*/
 
-#define	CFG_NIOS_CPU_CS1_BASE	0x41000000	/* board EXT1	addr	*/
-#define	CFG_NIOS_CPU_CS1_SIZE	(16*1024*1024)	/*  max. 16 MB	size	*/
+#define	CONFIG_SYS_NIOS_CPU_CS1_BASE	0x41000000	/* board EXT1	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_CS1_SIZE	(16*1024*1024)	/*  max. 16 MB	size	*/
 
-#define	CFG_NIOS_CPU_CS2_BASE	0x42000000	/* board EXT2	addr	*/
-#define	CFG_NIOS_CPU_CS2_SIZE	(16*1024*1024)	/*  max. 16 MB	size	*/
+#define	CONFIG_SYS_NIOS_CPU_CS2_BASE	0x42000000	/* board EXT2	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_CS2_SIZE	(16*1024*1024)	/*  max. 16 MB	size	*/
 
-#define	CFG_NIOS_CPU_CS3_BASE	0x43000000	/* board EXT3	addr	*/
-#define	CFG_NIOS_CPU_CS3_SIZE	(16*1024*1024)	/*  max. 16 MB	size	*/
+#define	CONFIG_SYS_NIOS_CPU_CS3_BASE	0x43000000	/* board EXT3	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_CS3_SIZE	(16*1024*1024)	/*  max. 16 MB	size	*/
 
 /* symbolic redefinition (undef, if not present) */
-#define	CFG_NIOS_CPU_TICK_TIMER		0	/* TIMER0: tick (needed)*/
-#undef	CFG_NIOS_CPU_USER_TIMER			/* TIMERx: users choice	*/
+#define	CONFIG_SYS_NIOS_CPU_TICK_TIMER		0	/* TIMER0: tick (needed)*/
+#undef	CONFIG_SYS_NIOS_CPU_USER_TIMER			/* TIMERx: users choice	*/
 
-#define	CFG_NIOS_CPU_PORTA_PIO		0	/* PIO0: Port A		*/
-#define	CFG_NIOS_CPU_PORTB_PIO		1	/* PIO1: Port D		*/
-#define	CFG_NIOS_CPU_PORTC_PIO		2	/* PIO2: Port C		*/
-#define	CFG_NIOS_CPU_RCM_PIO		3	/* PIO3: RCM jumper	*/
-#define	CFG_NIOS_CPU_WDENA_PIO		4	/* PIO4: watchdog enable*/
-#define	CFG_NIOS_CPU_WDTOG_PIO		5	/* PIO5: watchdog trigg.*/
+#define	CONFIG_SYS_NIOS_CPU_PORTA_PIO		0	/* PIO0: Port A		*/
+#define	CONFIG_SYS_NIOS_CPU_PORTB_PIO		1	/* PIO1: Port D		*/
+#define	CONFIG_SYS_NIOS_CPU_PORTC_PIO		2	/* PIO2: Port C		*/
+#define	CONFIG_SYS_NIOS_CPU_RCM_PIO		3	/* PIO3: RCM jumper	*/
+#define	CONFIG_SYS_NIOS_CPU_WDENA_PIO		4	/* PIO4: watchdog enable*/
+#define	CONFIG_SYS_NIOS_CPU_WDTOG_PIO		5	/* PIO5: watchdog trigg.*/
 
 /* PIOx: LED bar */
 #ifdef	CONFIG_DNPEVA2			/* DNP/EVA2 base board */
-#define	CFG_NIOS_CPU_LED_PIO		CFG_NIOS_CPU_PORTA_PIO
+#define	CONFIG_SYS_NIOS_CPU_LED_PIO		CONFIG_SYS_NIOS_CPU_PORTA_PIO
 #else
-#undef	CFG_NIOS_CPU_LED_PIO			/* no LED bar		*/
+#undef	CONFIG_SYS_NIOS_CPU_LED_PIO			/* no LED bar		*/
 #endif
 
 #endif	/* __CONFIG_ADNPESC1_BASE_32_H */
diff --git a/include/configs/ADS860.h b/include/configs/ADS860.h
index f677b9c..688e77a 100644
--- a/include/configs/ADS860.h
+++ b/include/configs/ADS860.h
@@ -27,12 +27,12 @@
 #define CONFIG_BAUDRATE		38400	/* Console baudrate */
 
 #if 0
-#define CFG_8XX_FACT		1526	/* 32.768 kHz crystal on XTAL/EXTAL */
+#define CONFIG_SYS_8XX_FACT		1526	/* 32.768 kHz crystal on XTAL/EXTAL */
 #else
-#define CFG_8XX_FACT		12	/* 4 MHz oscillator on EXTCLK */
+#define CONFIG_SYS_8XX_FACT		12	/* 4 MHz oscillator on EXTCLK */
 #endif
 
-#define CFG_PLPRCR  (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+#define CONFIG_SYS_PLPRCR  (((CONFIG_SYS_8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
 		PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 #define CONFIG_DRAM_50MHZ		1
@@ -53,6 +53,6 @@
 
 #include "../../board/fads/fads.h"
 
-#define CFG_PC_IDE_RESET	((ushort)0x0008)    /* PC 12	*/
+#define CONFIG_SYS_PC_IDE_RESET	((ushort)0x0008)    /* PC 12	*/
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/AMX860.h b/include/configs/AMX860.h
index 343123b..6e2907e 100644
--- a/include/configs/AMX860.h
+++ b/include/configs/AMX860.h
@@ -101,25 +101,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0200000	/* 1 ... 4 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0200000	/* 1 ... 4 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x00100000
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -130,31 +130,31 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR			0xFF000000
+#define CONFIG_SYS_IMMR			0xFF000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
 #if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * U-Boot for AMX board supports two types of memory extension
@@ -186,18 +186,18 @@
  * (CONFIG_AMX_RAM_EXT)
  */
 #ifdef CONFIG_AMX_RAM_EXT
-# define	CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/
+# define	CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/
 #else
-# define	CFG_BOOTMAPSZ	(4 << 20)	/* Initial Memory map for Linux	*/
+# define	CONFIG_SYS_BOOTMAPSZ	(4 << 20)	/* Initial Memory map for Linux	*/
 #endif
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	35	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	35	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
@@ -206,9 +206,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -218,10 +218,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -229,28 +229,28 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control					11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
  *-----------------------------------------------------------------------
  * set the PLL, the low-power modes and the reset control (15-29)
  */
-#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
 				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
@@ -260,9 +260,9 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
+#define CONFIG_SYS_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
 
-#define CFG_DER		0
+#define CONFIG_SYS_DER		0
 
 /*
  * Init Memory Controller:
@@ -275,27 +275,27 @@
 #define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #1	*/
 #endif
 
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFFC00000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFFC00000	/* OR addr mask */
 
 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
 /*				 0x00000800	0x00000400 0x00000100 0x00000030     0x00000004 */
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_TRLX)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 
-#define CFG_OR0_PRELIM	0xFFC00954	/* Real values for the board */
-#define CFG_BR0_PRELIM	0x40000001	/* Real values for the board */
+#define CONFIG_SYS_OR0_PRELIM	0xFFC00954	/* Real values for the board */
+#define CONFIG_SYS_BR0_PRELIM	0x40000001	/* Real values for the board */
 
 #ifndef CONFIG_AMX_RAM_EXT
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	0xFFC00954	/* Real values for the board */
-#define CFG_BR1_PRELIM	0x60000001	/* Real values for the board */
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	0xFFC00954	/* Real values for the board */
+#define CONFIG_SYS_BR1_PRELIM	0x60000001	/* Real values for the board */
 #endif
 
 /* DSP ("Glue") Xilinx */
-#define CFG_OR6_PRELIM	0xFFFF8000	/* 32kB, 15 waits, cs after addr, no bursts */
-#define CFG_BR6_PRELIM	0x60000401	/* use GPCM for CS generation, 8 bit port */
+#define CONFIG_SYS_OR6_PRELIM	0xFFFF8000	/* 32kB, 15 waits, cs after addr, no bursts */
+#define CONFIG_SYS_BR6_PRELIM	0x60000401	/* use GPCM for CS generation, 8 bit port */
 
 /*
  * Internal Definitions
diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h
index 63d4003..ec982bd 100644
--- a/include/configs/AP1000.h
+++ b/include/configs/AP1000.h
@@ -29,16 +29,16 @@
 
 #define CONFIG_PCI	1
 
-#define CFG_HUSH_PARSER 1		/* use "hush" command parser	*/
-#define CFG_PROMPT		"0> "
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER 1		/* use "hush" command parser	*/
+#define CONFIG_SYS_PROMPT		"0> "
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 #define CONFIG_COMMAND_EDIT	1
 #define CONFIG_COMMAND_HISTORY	1
 #define CONFIG_COMPLETE_ADDRESSES 1
 
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CFG_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 #ifdef CONFIG_ENV_IS_IN_NVRAM
 #undef CONFIG_ENV_IS_IN_FLASH
@@ -62,7 +62,7 @@
 #define CONFIG_BOOTARGS		"console=ttyS0,57600"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 
 /*
@@ -96,82 +96,82 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-/* usually: (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) */
-#define CFG_PBSIZE	(CFG_CBSIZE+4+16)	/* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+/* usually: (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+4+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_ALT_MEMTEST		1
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on */
-#define CFG_MEMTEST_END		0x01000000	/* 4 ... 16 MB in DRAM	*/
+#define CONFIG_SYS_ALT_MEMTEST		1
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x01000000	/* 4 ... 16 MB in DRAM	*/
 
 /*
- * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
  * The Linux BASE_BAUD define should match this configuration.
  *    baseBaud = cpuClock/(uartDivisor*16)
- * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  * set Linux BASE_BAUD to 403200.
  */
-#undef	CFG_EXT_SERIAL_CLOCK		/* external serial clock */
-#undef	CFG_405_UART_ERRATA_59		/* 405GP/CR Rev. D silicon */
-
-#define CFG_NS16550_CLK		40000000
-#define CFG_DUART_CHAN		0
-#define CFG_NS16550_COM1	(0x4C000000 + 0x1000)
-#define CFG_NS16550_COM2	(0x4C800000 + 0x1000)
-#define CFG_NS16550_REG_SIZE	4
-#define CFG_NS16550		1
-#define CFG_INIT_CHAN1		1
-#define CFG_INIT_CHAN2		0
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK		/* external serial clock */
+#undef	CONFIG_SYS_405_UART_ERRATA_59		/* 405GP/CR Rev. D silicon */
+
+#define CONFIG_SYS_NS16550_CLK		40000000
+#define CONFIG_SYS_DUART_CHAN		0
+#define CONFIG_SYS_NS16550_COM1	(0x4C000000 + 0x1000)
+#define CONFIG_SYS_NS16550_COM2	(0x4C800000 + 0x1000)
+#define CONFIG_SYS_NS16550_REG_SIZE	4
+#define CONFIG_SYS_NS16550		1
+#define CONFIG_SYS_INIT_CHAN1		1
+#define CONFIG_SYS_INIT_CHAN2		0
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
-#define CFG_LOAD_ADDR		0x00200000	/* default load address */
-#define CFG_EXTBDINFO		1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x00200000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO		1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x20000000
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_FLASH_CFI		1
-#define CFG_PROGFLASH_BASE	CFG_FLASH_BASE
-#define CFG_CONFFLASH_BASE	0x24000000
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_SYS_PROGFLASH_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CONFFLASH_BASE	0x24000000
 
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	    */
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	    */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_PROTECTION	1	/* use hardware protection	    */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware protection	    */
 
 /* BEG ENVIRONNEMENT FLASH */
 #ifdef CONFIG_ENV_IS_IN_FLASH
@@ -183,13 +183,13 @@
 /*-----------------------------------------------------------------------
  * NVRAM organization
  */
-#define CFG_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
 
 #ifdef CONFIG_ENV_IS_IN_NVRAM
 #define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars */
 #define CONFIG_ENV_ADDR	    \
-    (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
+    (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
 #endif
 
 /*
@@ -198,7 +198,7 @@
  * BR0/1 and OR0/1 (FLASH)
  */
 
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	*/
 #define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
 
 /* Configuration Port location */
@@ -208,11 +208,11 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 
-#define CFG_INIT_RAM_ADDR	0x400000  /* inside of SDRAM			 */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x400000  /* inside of SDRAM			 */
+#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for Serial Presence Detect EEPROM address
@@ -235,15 +235,15 @@
 
 /* JFFS2 stuff */
 
-#define CFG_JFFS2_FIRST_BANK	0
-#define CFG_JFFS2_NUM_BANKS	1
-#define CFG_JFFS2_FIRST_SECTOR	1
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR	1
 
 #define CONFIG_NET_MULTI
 #define CONFIG_E1000
 
-#define CFG_ETH_DEV_FN		0x0800
-#define CFG_ETH_IOBASE		0x31000000
-#define CFG_ETH_MEMBASE		0x32000000
+#define CONFIG_SYS_ETH_DEV_FN		0x0800
+#define CONFIG_SYS_ETH_IOBASE		0x31000000
+#define CONFIG_SYS_ETH_MEMBASE		0x32000000
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/APC405.h b/include/configs/APC405.h
index fa7798e..7453518 100644
--- a/include/configs/APC405.h
+++ b/include/configs/APC405.h
@@ -52,14 +52,14 @@
 
 #undef	CONFIG_BOOTARGS
 
-#define CFG_USB_LOAD_COMMAND	"fatload usb 0 200000 pImage;"		\
+#define CONFIG_SYS_USB_LOAD_COMMAND	"fatload usb 0 200000 pImage;"		\
 				"fatload usb 0 300000 pImage.initrd"
-#define CFG_USB_SELF_COMMAND	"usb start;run usb_load;usb stop;"	\
+#define CONFIG_SYS_USB_SELF_COMMAND	"usb start;run usb_load;usb stop;"	\
 				"run ramargs addip addcon usbargs;"	\
 				"bootm 200000 300000"
-#define CFG_USB_ARGS		"setenv bootargs $(bootargs) usbboot=1"
-#define CFG_BOOTLIMIT		"3"
-#define CFG_ALT_BOOTCOMMAND	"run usb_self;reset"
+#define CONFIG_SYS_USB_ARGS		"setenv bootargs $(bootargs) usbboot=1"
+#define CONFIG_SYS_BOOTLIMIT		"3"
+#define CONFIG_SYS_ALT_BOOTCOMMAND	"run usb_self;reset"
 
 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 	"hostname=abg405\0"                                             \
@@ -88,18 +88,18 @@
 	"netmask=255.255.0.0\0"                                         \
 	"serverip=10.0.0.190\0"						\
 	"splashimage=ffe80000\0"                                        \
-	"usb_load="CFG_USB_LOAD_COMMAND"\0"				\
-	"usb_self="CFG_USB_SELF_COMMAND"\0"				\
-	"usbargs="CFG_USB_ARGS"\0"					\
-	"bootlimit="CFG_BOOTLIMIT"\0"					\
-	"altbootcmd="CFG_ALT_BOOTCOMMAND"\0"				\
+	"usb_load="CONFIG_SYS_USB_LOAD_COMMAND"\0"				\
+	"usb_self="CONFIG_SYS_USB_SELF_COMMAND"\0"				\
+	"usbargs="CONFIG_SYS_USB_ARGS"\0"					\
+	"bootlimit="CONFIG_SYS_BOOTLIMIT"\0"					\
+	"altbootcmd="CONFIG_SYS_ALT_BOOTCOMMAND"\0"				\
 	""
 #define CONFIG_BOOTCOMMAND	"run flash_self;reset"
 
 #define CONFIG_ETHADDR		00:02:27:8e:00:00
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_NET_MULTI	1
 #undef  CONFIG_HAS_ETH1
@@ -148,44 +148,44 @@
 #undef  CONFIG_WATCHDOG			/* watchdog disabled */
 
 #define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
+#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device */
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device */
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
 
-#define CFG_EXT_SERIAL_CLOCK    14745600 /* use external serial clock   */
+#define CONFIG_SYS_EXT_SERIAL_CLOCK    14745600 /* use external serial clock   */
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CONFIG_SYS_BAUDRATE_TABLE      \
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
@@ -200,7 +200,7 @@
 
 #define CONFIG_VERSION_VARIABLE	1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*
  * PCI stuff
@@ -216,15 +216,15 @@
 
 #define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup  */
 #define CONFIG_PCI_SKIP_HOST_BRIDGE 1
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 
 /*
  * IDE/ATA stuff
@@ -233,32 +233,32 @@
 #undef  CONFIG_IDE_LED			/* no led for ide supported */
 #define CONFIG_IDE_RESET	1	/* reset for ide supported */
 
-#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses */
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS) /* max. 1 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses */
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS) /* max. 1 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR	0xF0100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
-#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register access */
-#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register access */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers */
 
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MONITOR_BASE	0xFFF80000
-#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor */
-#define CFG_MALLOC_LEN		(2*1024*1024)	/* Reserve 2MB for malloc() */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_BASE	0xFFF80000
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(2*1024*1024)	/* Reserve 2MB for malloc() */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Init. Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Init. Memory map for Linux */
 
 /*
  * FLASH organization
@@ -267,26 +267,26 @@
 extern int flash_banks;
 #endif
 
-#define CFG_FLASH_BASE		0xFE000000
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
-#define CFG_MAX_FLASH_BANKS	flash_banks /* max num of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	flash_banks /* max num of flash banks */
 					    /* updated in board_early_init_r */
-#define CFG_MAX_FLASH_BANKS_DETECT 2
-#define CFG_FLASH_QUIET_TEST	1
-#define CFG_FLASH_INCREMENT	0x01000000
-#define CFG_FLASH_PROTECTION	1	/* use hardware protection */
-#define CFG_FLASH_AUTOPROTECT_LIST { \
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
+#define CONFIG_SYS_FLASH_QUIET_TEST	1
+#define CONFIG_SYS_FLASH_INCREMENT	0x01000000
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware protection */
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { \
 				{0xfe000000, 0x500000}, \
 				{0xffe80000, 0x180000} \
 				}
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
-#define CFG_FLASH_BANKS_LIST	{ \
-				CFG_FLASH_BASE, \
-				CFG_FLASH_BASE + CFG_FLASH_INCREMENT \
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ \
+				CONFIG_SYS_FLASH_BASE, \
+				CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT \
 				}
-#define CFG_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
 
 /*
  * Environment Variable setup
@@ -297,31 +297,30 @@ extern int flash_banks;
 #define CONFIG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
 #define CONFIG_ENV_OVERWRITE	1	/* allow overwriting vendor vars */
 
-#define CFG_NVRAM_BASE_ADDR	0xF0000500	/* NVRAM base address */
-#define CFG_NVRAM_SIZE		242		/* NVRAM size */
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500	/* NVRAM base address */
+#define CONFIG_SYS_NVRAM_SIZE		242		/* NVRAM size */
 
 /*
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08 */
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address */
 /* mask of address bits that overflow into the "EEPROM chip address" */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has */
 					/* 16 byte page write mode using*/
 					/* last	4 bits of the address */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10 /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10 /* and takes up to 10 msec */
 
 /*
  * External Bus Controller (EBC) Setup
  */
-#define FLASH0_BA       (CFG_FLASH_BASE + CFG_FLASH_INCREMENT) /* FLASH 0 BA */
-#define FLASH1_BA       CFG_FLASH_BASE      /* FLASH 1 Base Address          */
+#define FLASH0_BA       (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT) /* FLASH 0 BA */
+#define FLASH1_BA       CONFIG_SYS_FLASH_BASE      /* FLASH 1 Base Address          */
 #define CAN_BA          0xF0000000          /* CAN Base Address              */
 #define DUART0_BA       0xF0000400          /* DUART Base Address            */
 #define DUART1_BA       0xF0000408          /* DUART Base Address            */
@@ -334,97 +333,97 @@ extern int flash_banks;
 #define PCMCIA2_BA      0x28000000          /* PCMCIA Slot 2 Base Address    */
 #define VGA_BA          0xF1000000          /* Epson VGA Base Address        */
 
-#define CFG_FPGA_BASE_ADDR      FPGA_BA     /* FPGA internal Base Address    */
+#define CONFIG_SYS_FPGA_BASE_ADDR      FPGA_BA     /* FPGA internal Base Address    */
 
 /* Memory Bank 0 (Flash Bank 0) initialization                               */
-#define CFG_EBC_PB0AP   0x92015480
-#define CFG_EBC_PB0CR   FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
-#define CFG_EBC_PB0AP_HWREV8 CFG_EBC_PB0AP
-#define CFG_EBC_PB0CR_HWREV8 FLASH1_BA | 0xBA000 /* BS=32MB */
+#define CONFIG_SYS_EBC_PB0AP   0x92015480
+#define CONFIG_SYS_EBC_PB0CR   FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB0AP_HWREV8 CONFIG_SYS_EBC_PB0AP
+#define CONFIG_SYS_EBC_PB0CR_HWREV8 FLASH1_BA | 0xBA000 /* BS=32MB */
 
 /* Memory Bank 1 (Flash Bank 1) initialization                               */
-#define CFG_EBC_PB1AP   0x92015480
-#define CFG_EBC_PB1CR   FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB1AP   0x92015480
+#define CONFIG_SYS_EBC_PB1CR   FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
 
 /* Memory Bank 2 (CAN0, 1, RTC, Duart) initialization                           */
-#define CFG_EBC_PB2AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR   CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+#define CONFIG_SYS_EBC_PB2AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR   CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 
 /* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization               */
-#define CFG_EBC_PB3AP   0x010059C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR   CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3AP   0x010059C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR   CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 4 (PCMCIA Slot 1) initialization                                 */
-#define CFG_EBC_PB4AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB4CR   PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB4AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB4CR   PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/
 
 /* Memory Bank 5 (Epson VGA) initialization                                     */
-#define CFG_EBC_PB5AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
-#define CFG_EBC_PB5CR   VGA_BA | 0x5A000    /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB5AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
+#define CONFIG_SYS_EBC_PB5CR   VGA_BA | 0x5A000    /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 6 (PCMCIA Slot 2) initialization                                 */
-#define CFG_EBC_PB6AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB6CR   PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB6AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB6CR   PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/
 
 /*
  * FPGA stuff
  */
 
 /* FPGA internal regs */
-#define CFG_FPGA_CTRL           0x008
-#define CFG_FPGA_CTRL2          0x00a
+#define CONFIG_SYS_FPGA_CTRL           0x008
+#define CONFIG_SYS_FPGA_CTRL2          0x00a
 
 /* FPGA Control Reg */
-#define CFG_FPGA_CTRL_CF_RESET  0x0001
-#define CFG_FPGA_CTRL_WDI       0x0002
-#define CFG_FPGA_CTRL_PS2_RESET 0x0020
+#define CONFIG_SYS_FPGA_CTRL_CF_RESET  0x0001
+#define CONFIG_SYS_FPGA_CTRL_WDI       0x0002
+#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
 
-#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE       80*1024     /* 80kByte is enough for XC2S50  */
+#define CONFIG_SYS_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE       80*1024     /* 80kByte is enough for XC2S50  */
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
+#define CONFIG_SYS_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
 
 /*
  * LCD Setup
  */
-#define CFG_LCD_BIG_MEM		(VGA_BA + 0x200000) /* S1D13806 Mem Base */
-#define CFG_LCD_BIG_REG		VGA_BA /* S1D13806 Reg Base */
+#define CONFIG_SYS_LCD_BIG_MEM		(VGA_BA + 0x200000) /* S1D13806 Mem Base */
+#define CONFIG_SYS_LCD_BIG_REG		VGA_BA /* S1D13806 Reg Base */
 
 #define CONFIG_LCD_BIG		2 /* Epson S1D13806 used */
 
 /* Image information... */
 #define CONFIG_LCD_USED		CONFIG_LCD_BIG
 
-#define CFG_LCD_MEM		CFG_LCD_BIG_MEM
-#define CFG_LCD_REG		CFG_LCD_BIG_REG
+#define CONFIG_SYS_LCD_MEM		CONFIG_SYS_LCD_BIG_MEM
+#define CONFIG_SYS_LCD_REG		CONFIG_SYS_LCD_BIG_REG
 
-#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20)
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20)
 
 /*
  * Definitions for initial stack pointer and data area (in data cache)
  */
 
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	1
+#define CONFIG_SYS_TEMP_STACK_OCM	1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM */
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE	128 /* reserved bytes for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	128 /* reserved bytes for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 /* reserve some memory for BOOT limit info */
-#define CFG_INIT_SP_OFFSET	(CFG_GBL_DATA_OFFSET - 16)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 16)
 
 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
-#define CFG_BOOTCOUNT_ADDR (CFG_GBL_DATA_OFFSET - 8)
+#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 8)
 #endif
 
 /*
@@ -440,10 +439,10 @@ extern int flash_banks;
  */
 #define CONFIG_USB_OHCI_NEW	1
 #define CONFIG_PCI_OHCI		1
-#define CFG_OHCI_SWAP_REG_ACCESS 1
-#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
-#define CFG_USB_OHCI_SLOT_NAME	"ohci_pci"
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ohci_pci"
 #define CONFIG_USB_STORAGE	1
-#define CFG_USB_OHCI_BOARD_INIT 1
+#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/AR405.h b/include/configs/AR405.h
index 18ca122..9f19269 100644
--- a/include/configs/AR405.h
+++ b/include/configs/AR405.h
@@ -65,8 +65,9 @@
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
@@ -102,39 +103,39 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
 #define CONFIG_LOOPW            1       /* enable loopw command         */
 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_EXT_SERIAL_CLOCK	14745600 /* use external serial clock	*/
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	14745600 /* use external serial clock	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
@@ -157,53 +158,53 @@
 
 #define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0403	/* PCI Device ID: ARISTO405	*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xfff00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xfff00001	/* 1MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0403	/* PCI Device ID: ARISTO405	*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xfff00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xfff00001	/* 1MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		0xFFFB0000	/* Address of Environment Sector*/
@@ -226,39 +227,39 @@
  */
 
 /* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (CAN0, 1, 2, 3) initialization					*/
-#define CFG_EBC_PB1AP		0x01000380  /* enable Ready, BEM=0		*/
-#define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB1AP		0x01000380  /* enable Ready, BEM=0		*/
+#define CONFIG_SYS_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 2 (Expension Bus) initialization					*/
-#define CFG_EBC_PB2AP		0x01000280  /* disable Ready, BEM=0		*/
-#define CFG_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2AP		0x01000280  /* disable Ready, BEM=0		*/
+#define CONFIG_SYS_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 3 (16552) initialization						*/
-#define CFG_EBC_PB3AP		0x01000380  /* enable Ready, BEM=0		*/
-#define CFG_EBC_PB3CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB3AP		0x01000380  /* enable Ready, BEM=0		*/
+#define CONFIG_SYS_EBC_PB3CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 4 (FPGA regs) initialization					*/
-#define CFG_EBC_PB4AP		0x01005380  /* enable Ready, BEM=0		*/
-#define CFG_EBC_PB4CR		0xF031C000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */
+#define CONFIG_SYS_EBC_PB4AP		0x01005380  /* enable Ready, BEM=0		*/
+#define CONFIG_SYS_EBC_PB4CR		0xF031C000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */
 
 /* Memory Bank 5 (Flash Bank 1/DUMMY) initialization				*/
-#define CFG_EBC_PB5AP		0x92015480
-#define CFG_EBC_PB5CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB5AP		0x92015480
+#define CONFIG_SYS_EBC_PB5CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
-#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
 
-#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Internal Definitions
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index 2285714..2ee4f80 100644
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -51,11 +51,12 @@
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_NET_MULTI	1
 #undef  CONFIG_HAS_ETH1
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
@@ -92,74 +93,72 @@
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
+#define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
 #undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*-----------------------------------------------------------------------
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
-#define NAND_MAX_CHIPS          1
-#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
 #define NAND_BIG_DELAY_US	25
 
-#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
-#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
-#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
-#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
+#define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
-#define CFG_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
-#define CFG_NAND_QUIET          1
+#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
+#define CONFIG_SYS_NAND_QUIET          1
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -176,58 +175,58 @@
 
 #undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -238,25 +237,24 @@
 #define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */
 
-#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 /*
  * Init Memory Controller:
@@ -271,21 +269,21 @@
  */
 
 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x92015480
-/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+/*#define CONFIG_SYS_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
-#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
 #define CAN_BA		0xF0000000	    /* CAN Base Address			*/
 #define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
@@ -293,36 +291,36 @@
 #define DUART2_BA	0xF0000410	    /* DUART Base Address		*/
 #define DUART3_BA	0xF0000418	    /* DUART Base Address		*/
 #define RTC_BA		0xF0000500	    /* RTC Base Address			*/
-#define CFG_NAND_BASE	0xF4000000
+#define CONFIG_SYS_NAND_BASE	0xF4000000
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
 
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup (PPC405EP specific)
@@ -336,15 +334,15 @@
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  */
-#define CFG_GPIO0_OSRH		0x40000550
-#define CFG_GPIO0_OSRL		0x00000110
-#define CFG_GPIO0_ISR1H		0x00000000
-#define CFG_GPIO0_ISR1L		0x15555445
-#define CFG_GPIO0_TSRH		0x00000000
-#define CFG_GPIO0_TSRL		0x00000000
-#define CFG_GPIO0_TCR		0xF7FE0014
-
-#define CFG_DUART_RST		(0x80000000 >> 14)
+#define CONFIG_SYS_GPIO0_OSRH		0x40000550
+#define CONFIG_SYS_GPIO0_OSRL		0x00000110
+#define CONFIG_SYS_GPIO0_ISR1H		0x00000000
+#define CONFIG_SYS_GPIO0_ISR1L		0x15555445
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0xF7FE0014
+
+#define CONFIG_SYS_DUART_RST		(0x80000000 >> 14)
 
 /*
  * Internal Definitions
diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
index 8efea00..7ee05e5 100644
--- a/include/configs/ATUM8548.h
+++ b/include/configs/ATUM8548.h
@@ -67,7 +67,6 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 #define CONFIG_CLEAR_LAW0		/* Clear LAW0 in cpu_init_r */
 
 /*
@@ -79,23 +78,23 @@
 
 #define CONFIG_CMD_SDRAM		1	/* SDRAM DIMM SPD info printout */
 #define CONFIG_ENABLE_36BIT_PHYS	1
-#undef	CFG_DRAM_TEST
-#define CFG_MEMTEST_START	0x00200000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00400000
+#undef	CONFIG_SYS_DRAM_TEST
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
 
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
-#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
 #define PCI_SPEED		33333000        /* CPLD currenlty does not have PCI setup info */
-#define CFG_PCI1_ADDR	(CFG_CCSRBAR+0x8000)
-#define CFG_PCI2_ADDR	(CFG_CCSRBAR+0x9000)
-#define CFG_PCIE1_ADDR	(CFG_CCSRBAR+0xa000)
+#define CONFIG_SYS_PCI1_ADDR	(CONFIG_SYS_CCSRBAR+0x8000)
+#define CONFIG_SYS_PCI2_ADDR	(CONFIG_SYS_CCSRBAR+0x9000)
+#define CONFIG_SYS_PCIE1_ADDR	(CONFIG_SYS_CCSRBAR+0xa000)
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR2
@@ -107,8 +106,8 @@
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_VERY_BIG_RAM
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
@@ -119,15 +118,15 @@
 #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
 
 /* Manually set up DDR parameters */
-#define CFG_SDRAM_SIZE	1024		/* DDR is 1024MB */
-#define CFG_DDR_CS0_BNDS	0x0000000f	/* 0-1024 */
-#define CFG_DDR_CS0_CONFIG	0x80000102
-#define CFG_DDR_TIMING_0	0x00260802
-#define CFG_DDR_TIMING_1	0x38355322
-#define CFG_DDR_TIMING_2	0x039048c7
-#define CFG_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
-#define CFG_DDR_MODE	0x00000432
-#define CFG_DDR_INTERVAL	0x05150100
+#define CONFIG_SYS_SDRAM_SIZE	1024		/* DDR is 1024MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000f	/* 0-1024 */
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000102
+#define CONFIG_SYS_DDR_TIMING_0	0x00260802
+#define CONFIG_SYS_DDR_TIMING_1	0x38355322
+#define CONFIG_SYS_DDR_TIMING_2	0x039048c7
+#define CONFIG_SYS_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_MODE	0x00000432
+#define CONFIG_SYS_DDR_INTERVAL	0x05150100
 #define DDR_SDRAM_CFG	0x43000000
 
 #undef CONFIG_CLOCKS_IN_MHZ
@@ -164,63 +163,63 @@
  * 1111 1000 0000 0000 0000 1110 0110 0101 = f8000E65    ORx
  */
 
-#define CFG_BOOT_BLOCK		0xf8000000	/* boot TLB block */
-#define CFG_FLASH_BASE		CFG_BOOT_BLOCK	/* start of FLASH 128M */
+#define CONFIG_SYS_BOOT_BLOCK		0xf8000000	/* boot TLB block */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_BOOT_BLOCK	/* start of FLASH 128M */
 
-#define CFG_BR0_PRELIM		0xf8001001
+#define CONFIG_SYS_BR0_PRELIM		0xf8001001
 
-#define	CFG_OR0_PRELIM		0xf8000E65
+#define	CONFIG_SYS_OR0_PRELIM		0xf8000E65
 
-#define CFG_MAX_FLASH_BANKS	1		/* number of banks	*/
-#define CFG_MAX_FLASH_SECT	1024		/* sectors per device */
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	512000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	8000	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	512000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	8000	/* Flash Write Timeout (ms) */
 
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #define CONFIG_FLASH_CFI_DRIVER    1
-#define CFG_FLASH_CFI           1
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI           1
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 /*
  * Flash on the LocalBus
  */
-#define CFG_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable	 */
+#define CONFIG_SYS_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable	 */
 
 /* Memory */
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_INIT_L2_ADDR	0xf8f80000	/* relocate boot L2SRAM */
+#define CONFIG_SYS_INIT_L2_ADDR	0xf8f80000	/* relocate boot L2SRAM */
 
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE \
+#define CONFIG_SYS_BAUDRATE_TABLE \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* pass open firmware flat tree */
@@ -233,41 +232,41 @@
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_EEPROM_ADDR	0x57
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
 
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CFG_PCI_PHYS		0x80000000	/* 1G PCI TLB */
+#define CONFIG_SYS_PCI_PHYS		0x80000000	/* 1G PCI TLB */
 
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xe2000000
-#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
 
 #ifdef CONFIG_PCI2
-#define CFG_PCI2_MEM_BASE	0xC0000000
-#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI2_IO_BASE	0x00000000
-#define CFG_PCI2_IO_PHYS	0xe2800000
-#define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCI2_MEM_BASE	0xC0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS	0xe2800000
+#define CONFIG_SYS_PCI2_IO_SIZE	0x00100000	/* 1M */
 #endif
 
 #ifdef CONFIG_PCIE1
-#define CFG_PCIE1_MEM_BASE	0xa0000000
-#define CFG_PCIE1_MEM_PHYS	CFG_PCIE1_MEM_BASE
-#define CFG_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCIE1_IO_BASE	0x00000000
-#define CFG_PCIE1_IO_PHYS	0xe3000000
-#define CFG_PCIE1_IO_SIZE	0x00100000	/*   1M */
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/*   1M */
 #endif
 
 
@@ -287,11 +286,6 @@
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 
-/* PCI view of System Memory */
-#define CFG_PCI_MEMORY_BUS	0x00000000
-#define CFG_PCI_MEMORY_PHYS	0x00000000
-#define CFG_PCI_MEMORY_SIZE	0x80000000
-
 #endif	/* CONFIG_PCI */
 
 #if defined(CONFIG_TSEC_ENET)
@@ -334,12 +328,12 @@
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
 #define CONFIG_ENV_SIZE		0x2000
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -369,25 +363,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	*/
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/Adder.h b/include/configs/Adder.h
index fcac647..e4d30a1 100644
--- a/include/configs/Adder.h
+++ b/include/configs/Adder.h
@@ -41,18 +41,18 @@
 #define CONFIG_HAS_ETH1
 
 #if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
-#define CFG_DISCOVER_PHY
+#define CONFIG_SYS_DISCOVER_PHY
 #define CONFIG_MII_INIT		1
 #define FEC_ENET
 #endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */
 
 #define CONFIG_8xx_OSCLK		10000000 /* 10 MHz oscillator on EXTCLK */
 #define CONFIG_8xx_CPUCLK_DEFAULT	50000000
-#define CFG_8xx_CPUCLK_MIN		40000000
+#define CONFIG_SYS_8xx_CPUCLK_MIN		40000000
 #ifdef CONFIG_MPC852T
-#define CFG_8xx_CPUCLK_MAX		50000000
+#define CONFIG_SYS_8xx_CPUCLK_MAX		50000000
 #else
-#define CFG_8xx_CPUCLK_MAX		133000000
+#define CONFIG_SYS_8xx_CPUCLK_MAX		133000000
 #endif /* CONFIG_MPC852T */
 
 
@@ -86,28 +86,28 @@
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  */
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#define CFG_LONGHELP				/* #undef to save memory	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)  /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* Max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP				/* #undef to save memory	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)  /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* Max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_LOAD_ADDR		0x400000	/* Default load address		*/
+#define CONFIG_SYS_LOAD_ADDR		0x400000	/* Default load address		*/
 
-#define CFG_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
+#define CONFIG_SYS_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
- * RAM configuration (note that CFG_SDRAM_BASE must be zero)
+ * RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero)
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_MAX_SIZE	0x01000000	/* Up to 16 Mbyte		*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_MAX_SIZE	0x01000000	/* Up to 16 Mbyte		*/
 
-#define CFG_MAMR		0x00002114
+#define CONFIG_SYS_MAMR		0x00002114
 
 /*
  * 4096	Up to 4096 SDRAM rows
@@ -116,96 +116,96 @@
  * 4	Number of refresh cycles per period
  * 64	Refresh cycle in ms per number of rows
  */
-#define CFG_PTA_PER_CLK		((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_PTA_PER_CLK		((4096 * 32 * 1000) / (4 * 64))
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x00500000	/* 1 ... 5 MB in SDRAM		*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x00500000	/* 1 ... 5 MB in SDRAM		*/
 
-#define CFG_RESET_ADDRESS	0x09900000
+#define CONFIG_SYS_RESET_ADDRESS	0x09900000
 
 /*-----------------------------------------------------------------------
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for Monitor   */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for Monitor   */
 #ifdef CONFIG_BZIP2
-#define CFG_MALLOC_LEN		(2500 << 10)	/* Reserve ~2.5 MB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN		(2500 << 10)	/* Reserve ~2.5 MB for malloc() */
 #else
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()  */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()  */
 #endif /* CONFIG_BZIP2 */
 
 /*-----------------------------------------------------------------------
  * Flash organisation
  */
-#define CFG_FLASH_BASE		0xFE000000
-#define CFG_FLASH_CFI				/* The flash is CFI compatible  */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible  */
 #define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
-#define CFG_MAX_FLASH_BANKS	1		/* Max number of flash banks	*/
-#define CFG_MAX_FLASH_SECT	128		/* Max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max number of flash banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* Max num of sects on one chip */
 
 /* Environment is in flash */
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x10000		/* We use one complete sector	*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 
 #define CONFIG_ENV_OVERWRITE
 
-#define CFG_OR0_PRELIM		0xFF000774
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM		0xFF000774
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V)
 
-#define	CFG_DIRECT_FLASH_TFTP
+#define	CONFIG_SYS_DIRECT_FLASH_TFTP
 
 /*-----------------------------------------------------------------------
  * Internal Memory Map Register
  */
-#define CFG_IMMR		0xFF000000
+#define CONFIG_SYS_IMMR		0xFF000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00		/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128  /* Size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00		/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* Size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Configuration registers
  */
 #ifdef CONFIG_WATCHDOG
-#define CFG_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
+#define CONFIG_SYS_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
 				 SYPCR_SWF  | SYPCR_SWE | SYPCR_SWRI | \
 				 SYPCR_SWP)
 #else
-#define CFG_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
+#define CONFIG_SYS_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
 				 SYPCR_SWF  | SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
-#define CFG_SIUMCR		(SIUMCR_MLRC01 | SIUMCR_DBGC11)
+#define CONFIG_SYS_SIUMCR		(SIUMCR_MLRC01 | SIUMCR_DBGC11)
 
 /* TBSCR - Time Base Status and Control Register */
-#define CFG_TBSCR		(TBSCR_TBF | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR		(TBSCR_TBF | TBSCR_TBE)
 
 /* PISCR - Periodic Interrupt Status and Control */
-#define CFG_PISCR		(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR		(PISCR_PS | PISCR_PITF)
 
 /* PLPRCR - PLL, Low-Power, and Reset Control Register */
-/* #define CFG_PLPRCR		PLPRCR_TEXPS */
+/* #define CONFIG_SYS_PLPRCR		PLPRCR_TEXPS */
 
 /* SCCR - System Clock and reset Control Register */
 #define SCCR_MASK		SCCR_EBDF11
-#define CFG_SCCR		SCCR_RTSEL
+#define CONFIG_SYS_SCCR		SCCR_RTSEL
 
-#define CFG_DER			0
+#define CONFIG_SYS_DER			0
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx chips			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx chips			*/
 
 /*-----------------------------------------------------------------------
  * Internal Definitions
diff --git a/include/configs/AdderUSB.h b/include/configs/AdderUSB.h
index a4f7f9a..e4c1c9c 100644
--- a/include/configs/AdderUSB.h
+++ b/include/configs/AdderUSB.h
@@ -31,9 +31,9 @@
 
 #define CONFIG_USB_DEVICE		/* Include UDC driver */
 #define CONFIG_USB_TTY			/* Bind the TTY driver to UDC */
-#define CFG_USB_EXTC_CLK 0x02		/* Oscillator on EXTC_CLK 2 */
-#define CFG_USB_BRG_CLK	0x04		/* or use Baud rate generator 0x04 */
-#define CFG_CONSOLE_IS_IN_ENV		/* Console is in env */
+#define CONFIG_SYS_USB_EXTC_CLK 0x02		/* Oscillator on EXTC_CLK 2 */
+#define CONFIG_SYS_USB_BRG_CLK	0x04		/* or use Baud rate generator 0x04 */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV		/* Console is in env */
 
 /* If you have a USB-IF assigned VendorID then you may wish to define
  * your own vendor specific values either in BoardName.h or directly in
diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h
index 431ed4e..2581fdf 100644
--- a/include/configs/Alaska8220.h
+++ b/include/configs/Alaska8220.h
@@ -35,8 +35,8 @@
 
 /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
    determine the CPU speed. */
-#define CFG_MPC8220_CLKIN	30000000/* ... running at 30MHz */
-#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
+#define CONFIG_SYS_MPC8220_CLKIN	30000000/* ... running at 30MHz */
+#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	*/
@@ -53,16 +53,16 @@
 
 #ifdef CONFIG_EXTUART_CONSOLE
 #   define CONFIG_CONS_INDEX	1
-#   define CFG_NS16550_SERIAL
-#   define CFG_NS16550
-#   define CFG_NS16550_REG_SIZE 1
-#   define CFG_NS16550_COM1	(CFG_CPLD_BASE + 0x1008)
-#   define CFG_NS16550_CLK	18432000
+#   define CONFIG_SYS_NS16550_SERIAL
+#   define CONFIG_SYS_NS16550
+#   define CONFIG_SYS_NS16550_REG_SIZE 1
+#   define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CPLD_BASE + 0x1008)
+#   define CONFIG_SYS_NS16550_CLK	18432000
 #endif
 
 #define CONFIG_BAUDRATE		115200	    /* ... at 115200 bps */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #define CONFIG_TIMESTAMP			/* Print image info with timestamp */
 
@@ -120,104 +120,104 @@
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1
-#define CFG_I2C_MODULE		1
+#define CONFIG_SYS_I2C_MODULE		1
 
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration
  */
-#define CFG_I2C_EEPROM_ADDR		0x52	/* 1011000xb */
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x52	/* 1011000xb */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
 /*
 #define CONFIG_ENV_IS_IN_EEPROM	1
 #define CONFIG_ENV_OFFSET		0
 #define CONFIG_ENV_SIZE		256
 */
 
-/* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
+/* If CONFIG_SYS_AMD_BOOT is defined, the the system will boot from AMD.
    else undefined it will boot from Intel Strata flash */
-#define CFG_AMD_BOOT		1
+#define CONFIG_SYS_AMD_BOOT		1
 
 /*
  * Flexbus Chipselect configuration
  */
-#if defined (CFG_AMD_BOOT)
-#define CFG_CS0_BASE		0xfff0
-#define CFG_CS0_MASK		0x00080000  /* 512 KB */
-#define CFG_CS0_CTRL		0x003f0d40
-
-#define CFG_CS1_BASE		0xfe00
-#define CFG_CS1_MASK		0x01000000  /* 16 MB */
-#define CFG_CS1_CTRL		0x003f1540
+#if defined (CONFIG_SYS_AMD_BOOT)
+#define CONFIG_SYS_CS0_BASE		0xfff0
+#define CONFIG_SYS_CS0_MASK		0x00080000  /* 512 KB */
+#define CONFIG_SYS_CS0_CTRL		0x003f0d40
+
+#define CONFIG_SYS_CS1_BASE		0xfe00
+#define CONFIG_SYS_CS1_MASK		0x01000000  /* 16 MB */
+#define CONFIG_SYS_CS1_CTRL		0x003f1540
 #else
-#define CFG_CS0_BASE		0xff00
-#define CFG_CS0_MASK		0x01000000  /* 16 MB */
-#define CFG_CS0_CTRL		0x003f1540
+#define CONFIG_SYS_CS0_BASE		0xff00
+#define CONFIG_SYS_CS0_MASK		0x01000000  /* 16 MB */
+#define CONFIG_SYS_CS0_CTRL		0x003f1540
 
-#define CFG_CS1_BASE		0xfe08
-#define CFG_CS1_MASK		0x00080000  /* 512 KB */
-#define CFG_CS1_CTRL		0x003f0d40
+#define CONFIG_SYS_CS1_BASE		0xfe08
+#define CONFIG_SYS_CS1_MASK		0x00080000  /* 512 KB */
+#define CONFIG_SYS_CS1_CTRL		0x003f0d40
 #endif
 
-#define CFG_CS2_BASE		0xf100
-#define CFG_CS2_MASK		0x00040000
-#define CFG_CS2_CTRL		0x003f1140
+#define CONFIG_SYS_CS2_BASE		0xf100
+#define CONFIG_SYS_CS2_MASK		0x00040000
+#define CONFIG_SYS_CS2_CTRL		0x003f1140
 
-#define CFG_CS3_BASE		0xf200
-#define CFG_CS3_MASK		0x00040000
-#define CFG_CS3_CTRL		0x003f1100
+#define CONFIG_SYS_CS3_BASE		0xf200
+#define CONFIG_SYS_CS3_MASK		0x00040000
+#define CONFIG_SYS_CS3_CTRL		0x003f1100
 
 
-#define CFG_FLASH0_BASE		(CFG_CS0_BASE << 16)
-#define CFG_FLASH1_BASE		(CFG_CS1_BASE << 16)
+#define CONFIG_SYS_FLASH0_BASE		(CONFIG_SYS_CS0_BASE << 16)
+#define CONFIG_SYS_FLASH1_BASE		(CONFIG_SYS_CS1_BASE << 16)
 
-#if defined (CFG_AMD_BOOT)
-#define CFG_AMD_BASE		CFG_FLASH0_BASE
-#define CFG_INTEL_BASE		CFG_FLASH1_BASE + 0xf00000
-#define CFG_FLASH_BASE		CFG_AMD_BASE
+#if defined (CONFIG_SYS_AMD_BOOT)
+#define CONFIG_SYS_AMD_BASE		CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_INTEL_BASE		CONFIG_SYS_FLASH1_BASE + 0xf00000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_AMD_BASE
 #else
-#define CFG_INTEL_BASE		CFG_FLASH0_BASE + 0xf00000
-#define CFG_AMD_BASE		CFG_FLASH1_BASE
-#define CFG_FLASH_BASE		CFG_INTEL_BASE
+#define CONFIG_SYS_INTEL_BASE		CONFIG_SYS_FLASH0_BASE + 0xf00000
+#define CONFIG_SYS_AMD_BASE		CONFIG_SYS_FLASH1_BASE
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_INTEL_BASE
 #endif
 
-#define CFG_CPLD_BASE		(CFG_CS2_BASE << 16)
-#define CFG_FPGA_BASE		(CFG_CS3_BASE << 16)
+#define CONFIG_SYS_CPLD_BASE		(CONFIG_SYS_CS2_BASE << 16)
+#define CONFIG_SYS_FPGA_BASE		(CONFIG_SYS_CS3_BASE << 16)
 
 
-#define CFG_MAX_FLASH_BANKS	4	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	4	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
-#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
 
 #define PHYS_AMD_SECT_SIZE	0x00010000 /*  64 KB sectors (x2) */
 #define PHYS_INTEL_SECT_SIZE	0x00020000 /* 128 KB sectors (x2) */
 
-#define CFG_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_CHECKSUM
 /*
  * Environment settings
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#if defined (CFG_AMD_BOOT)
-#define CONFIG_ENV_ADDR		(CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
+#if defined (CONFIG_SYS_AMD_BOOT)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_AMD_SECT_SIZE)
 #define CONFIG_ENV_SIZE		PHYS_AMD_SECT_SIZE
 #define CONFIG_ENV_SECT_SIZE	PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV1_ADDR		(CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
+#define CONFIG_ENV1_ADDR		(CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_INTEL_SECT_SIZE)
 #define CONFIG_ENV1_SIZE		PHYS_INTEL_SECT_SIZE
 #define CONFIG_ENV1_SECT_SIZE	PHYS_INTEL_SECT_SIZE
 #else
-#define CONFIG_ENV_ADDR		(CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_INTEL_SECT_SIZE)
 #define CONFIG_ENV_SIZE		PHYS_INTEL_SECT_SIZE
 #define CONFIG_ENV_SECT_SIZE	PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV1_ADDR		(CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
+#define CONFIG_ENV1_ADDR		(CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_AMD_SECT_SIZE)
 #define CONFIG_ENV1_SIZE		PHYS_AMD_SECT_SIZE
 #define CONFIG_ENV1_SECT_SIZE	PHYS_AMD_SECT_SIZE
 #endif
@@ -238,37 +238,37 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
-#define CFG_SRAM_BASE		(CFG_MBAR + 0x20000)
-#define CFG_SRAM_SIZE		0x8000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_SRAM_BASE		(CONFIG_SYS_MBAR + 0x20000)
+#define CONFIG_SYS_SRAM_SIZE		0x8000
 
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	(CFG_MBAR + 0x20000)
-#define CFG_INIT_RAM_END	0x8000	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MBAR + 0x20000)
+#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in DPRAM */
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10) /* Reserve 256 kB for Monitor   */
-#define CFG_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
-#define CFG_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10) /* Reserve 256 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
 
 /* SDRAM configuration */
-#define CFG_SDRAM_TOTAL_BANKS		2
-#define CFG_SDRAM_SPD_I2C_ADDR		0x51		/* 7bit */
-#define CFG_SDRAM_SPD_SIZE		0x40
-#define CFG_SDRAM_CAS_LATENCY		4		/* (CL=2)x2 */
+#define CONFIG_SYS_SDRAM_TOTAL_BANKS		2
+#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR		0x51		/* 7bit */
+#define CONFIG_SYS_SDRAM_SPD_SIZE		0x40
+#define CONFIG_SYS_SDRAM_CAS_LATENCY		4		/* (CL=2)x2 */
 
 /* SDRAM drive strength register */
-#define CFG_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_LOW  << SDRAMDS_SBE_SHIFT) | \
+#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_LOW  << SDRAMDS_SBE_SHIFT) | \
 					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
 					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBA_SHIFT) | \
 					 (DRIVE_STRENGTH_OFF  << SDRAMDS_SBS_SHIFT) | \
@@ -285,34 +285,34 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			    /* undef to save memory	*/
-#define CFG_PROMPT		"=> "	    /* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			    /* undef to save memory	*/
+#define CONFIG_SYS_PROMPT		"=> "	    /* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	    /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		1024	    /* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE		256	    /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		256	    /* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	    /* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size    */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	    /* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START	0x00100000  /* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000  /* 1 ... 15 MB in DRAM  */
+#define CONFIG_SYS_MEMTEST_START	0x00100000  /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000  /* 1 ... 15 MB in DRAM  */
 
-#define CFG_LOAD_ADDR		0x100000    /* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000    /* default load address */
 
-#define CFG_HZ			1000	    /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	    /* decrementer freq: 1 ms ticks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5   /* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5   /* log base 2 of the above value */
 #endif
 
 /*
  * Various low-level settings
  */
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 
 /*
  * JFFS2 partitions
diff --git a/include/configs/AmigaOneG3SE.h b/include/configs/AmigaOneG3SE.h
index a6e9228..b71da1f 100644
--- a/include/configs/AmigaOneG3SE.h
+++ b/include/configs/AmigaOneG3SE.h
@@ -50,7 +50,7 @@
 
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		9600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #undef CONFIG_CLOCKS_IN_MHZ		/* clocks passed to Linux in Hz */
 
@@ -100,52 +100,52 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"] "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"] "		/* Monitor Command Prompt	*/
 
-#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-/* #undef CFG_HUSH_PARSER */
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
+/* #undef CONFIG_SYS_HUSH_PARSER */
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 
 /* Print Buffer Size
  */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 
-#define CFG_MAXARGS	64		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00500000	/* Default load address		*/
+#define CONFIG_SYS_MAXARGS	64		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x00500000	/* Default load address		*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE	    0x00000000
-#define CFG_FLASH_BASE	    0xFFF00000
-#define CFG_FLASH_MAX_SIZE  0x00080000
+#define CONFIG_SYS_SDRAM_BASE	    0x00000000
+#define CONFIG_SYS_FLASH_BASE	    0xFFF00000
+#define CONFIG_SYS_FLASH_MAX_SIZE  0x00080000
 /* Maximum amount of RAM.
  */
-#define CFG_MAX_RAM_SIZE    0x80000000	/* 2G			*/
+#define CONFIG_SYS_MAX_RAM_SIZE    0x80000000	/* 2G			*/
 
-#define CFG_RESET_ADDRESS   0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 
-#define CFG_MONITOR_BASE    TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
 
-#define CFG_MONITOR_LEN	    (768 << 10) /* Reserve 512 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (2500 << 10) /* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_MONITOR_LEN	    (768 << 10) /* Reserve 512 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN	    (2500 << 10) /* Reserve 128 kB for malloc() */
 
-#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \
-    CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE
-#define CFG_RAMBOOT
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \
+    CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef CFG_RAMBOOT
+#undef CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MEMTEST_START	0x00004000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00004000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM	*/
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area
@@ -154,88 +154,88 @@
 /* Size in bytes reserved for initial data
  */
 /* HJF: used to be 0x400000 */
-#define CFG_INIT_RAM_ADDR	0x40000000
-#define CFG_INIT_RAM_END	0x8000
-#define CFG_GBL_DATA_SIZE	128
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_END	0x8000
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_LOCK
 
 /*
  * Temporary buffer for serial data until the real serial driver
  * is initialised (memtest will destroy this buffer)
  */
-#define CFG_SCONSOLE_ADDR     CFG_INIT_RAM_ADDR
-#define CFG_SCONSOLE_SIZE     0x0002000
+#define CONFIG_SYS_SCONSOLE_ADDR     CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_SCONSOLE_SIZE     0x0002000
 
 /* SDRAM 0 - 256MB
  */
 
-/*HJF: #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_4M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_DBAT0U CFG_IBAT0U*/
+/*HJF: #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U*/
 
-#define CFG_DBAT0L	      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_DBAT0U	      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L	      (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT0U	      (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U      (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 /* PCI Range
  */
-#define CFG_DBAT1L	 (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT1U	 (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT1L	 (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT1U	 (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L	 (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1U	 (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	 (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1U	 (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 /* HJF:
-#define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW)
-#define CFG_IBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW )
-#define CFG_DBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_INIT_RAM_ADDR) | BATL_PP_RW)
+#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_INIT_RAM_ADDR) | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L ((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW )
+#define CONFIG_SYS_DBAT1U ((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_INIT_RAM_ADDR + 0x20000) | BATU_BL_256M | BATU_VS | BATU_VP)
 */
 
 /* Init RAM in the CPU DCache (no backing memory)
  */
-#define CFG_DBAT2L	(CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_DBAT2U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 /* This used to be commented out */
-#define CFG_IBAT2L	  CFG_DBAT2L
+#define CONFIG_SYS_IBAT2L	  CONFIG_SYS_DBAT2L
 /* This here too */
-#define CFG_IBAT2U	  CFG_DBAT2U
+#define CONFIG_SYS_IBAT2U	  CONFIG_SYS_DBAT2U
 
 
 /* I/O and PCI memory at 0xf0000000
  */
-#define CFG_DBAT3L	(0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U	(0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L	(0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U	(0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
-#define CFG_IBAT3L	(0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
  */
-#define CFG_HZ		1000
-#define CFG_BUS_HZ	133000000 /* bus speed - 100 mhz		*/
-#define CFG_CPU_CLK	133000000
-#define CFG_BUS_CLK	133000000
+#define CONFIG_SYS_HZ		1000
+#define CONFIG_SYS_BUS_HZ	133000000 /* bus speed - 100 mhz		*/
+#define CONFIG_SYS_CPU_CLK	133000000
+#define CONFIG_SYS_BUS_CLK	133000000
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20) /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT	8	/* Max number of sectors in one bank	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* Max number of sectors in one bank	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
 /*
  * Environment is stored in NVRAM.
@@ -247,22 +247,22 @@
 					    */
 #define CONFIG_ENV_SIZE		0x8000	   /* Size of the Environment. See comment above */
 
-#define CFG_CONSOLE_IS_IN_ENV	1 /* stdin/stdout/stderr are in environment */
-#define CFG_CONSOLE_OVERWRITE_ROUTINE	1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1 /* stdin/stdout/stderr are in environment */
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE	1
 #define CONFIG_ENV_OVERWRITE 1
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SIZE	32
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /*
  * L2 cache
  */
-#define CFG_L2
+#define CONFIG_SYS_L2
 #define L2_INIT	  (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 		   L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 #define L2_ENABLE (L2_INIT | L2CR_L2E)
@@ -281,26 +281,26 @@
  */
 
 #define CONFIG_ATAPI		1
-#define CFG_IDE_MAXBUS		2
-#define CFG_IDE_MAXDEVICE	4
+#define CONFIG_SYS_IDE_MAXBUS		2
+#define CONFIG_SYS_IDE_MAXDEVICE	4
 #define CONFIG_ISO_PARTITION	1
 
-#define CFG_ATA_BASE_ADDR	0xFE000000  /* was: via_get_base_addr() */
-#define CFG_ATA_IDE0_OFFSET	0x1F0
-#define CFG_ATA_IDE1_OFFSET	0x170
+#define CONFIG_SYS_ATA_BASE_ADDR	0xFE000000  /* was: via_get_base_addr() */
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x1F0
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0x170
 
-#define CFG_ATA_REG_OFFSET	0
-#define CFG_ATA_DATA_OFFSET	0
-#define CFG_ATA_ALT_OFFSET	0x0200
+#define CONFIG_SYS_ATA_REG_OFFSET	0
+#define CONFIG_SYS_ATA_DATA_OFFSET	0
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0200
 
 /*-----------------------------------------------------------------------
  * Disk-On-Chip configuration
  */
 
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
+#define CONFIG_SYS_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
 
-#define CFG_DOC_SUPPORT_2000
-#undef CFG_DOC_SUPPORT_MILLENNIUM
+#define CONFIG_SYS_DOC_SUPPORT_2000
+#undef CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
 
 /*-----------------------------------------------------------------------
   RTC
@@ -311,16 +311,16 @@
  * NS16550 Configuration
  */
 
-#define CFG_NS16550
+#define CONFIG_SYS_NS16550
 
-#define CFG_NS16550_COM1 0xFE0003F8
-#define CFG_NS16550_COM2 0xFE0002F8
+#define CONFIG_SYS_NS16550_COM1 0xFE0003F8
+#define CONFIG_SYS_NS16550_COM2 0xFE0002F8
 
-#define CFG_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_REG_SIZE 1
 
 /* base address for ISA I/O
  */
-#define CFG_ISA_IO_BASE_ADDRESS 0xFE000000
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xFE000000
 
 /* ISA Interrupt stuff (taken from JWL) */
 
@@ -346,7 +346,7 @@
  */
 
 #define CONFIG_NET_MULTI
-#define CFG_BOARD_ASM_INIT
+#define CONFIG_SYS_BOARD_ASM_INIT
 #define CONFIG_LAST_STAGE_INIT
 
 /* #define CONFIG_ETHADDR	00:09:D2:10:00:76 */
@@ -363,7 +363,7 @@
 #define CONFIG_USB_UHCI		1
 #define CONFIG_USB_STORAGE	1
 #define CONFIG_USB_KEYBOARD	1
-#define CFG_DEVICE_DEREGISTER	1 /* needed by CONFIG_USB_KEYBOARD */
+#define CONFIG_SYS_DEVICE_DEREGISTER	1 /* needed by CONFIG_USB_KEYBOARD */
 
 /*
  * Autoboot stuff
diff --git a/include/configs/B2.h b/include/configs/B2.h
index 1a8114b..c77ea1f 100644
--- a/include/configs/B2.h
+++ b/include/configs/B2.h
@@ -48,10 +48,10 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
 #define CONFIG_ENV_SIZE		1024		/* 1024 bytes may be used for env vars*/
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024 )
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024 )
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -106,24 +106,24 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"=>  "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=>  "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0C400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C800000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0C400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C800000	/* 4 ... 8 MB in DRAM	*/
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0x0c700000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x0c700000	/* default load address	*/
 
-#define	CFG_HZ				1000		/* 1 kHz */
+#define	CONFIG_SYS_HZ				1000		/* 1 kHz */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -146,7 +146,7 @@
 #define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
 #define PHYS_FLASH_SIZE		0x00400000 /* 4 MB */
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
@@ -154,24 +154,24 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 /*-----------------------------------------------------------------------
  * Environment Variable setup
@@ -183,24 +183,23 @@
  * I2C EEPROM (STM24C02W6) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0xFE
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0xFE
 
-#define CFG_I2C_EEPROM_ADDR	0xA8	/* EEPROM STM24C02W6		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0xA8	/* EEPROM STM24C02W6		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07*/
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 /* Flash banks JFFS2 should use */
 /*
-#define CFG_JFFS2_FIRST_BANK    0
-#define CFG_JFFS2_FIRST_SECTOR	2
-#define CFG_JFFS2_NUM_BANKS     1
+#define CONFIG_SYS_JFFS2_FIRST_BANK    0
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR	2
+#define CONFIG_SYS_JFFS2_NUM_BANKS     1
 */
 
 /*
diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h
index bfbda52..1910b34 100644
--- a/include/configs/BAB7xx.h
+++ b/include/configs/BAB7xx.h
@@ -63,7 +63,7 @@
     "bootm"
 
 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
-#define CFG_LOADS_BAUD_CHANGE           /* allow baudrate changes */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE           /* allow baudrate changes */
 
 /*
  * BOOTP options
@@ -93,8 +93,8 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP                    /* undef to save memory */
-#define CFG_PROMPT              "=> "   /* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP                    /* undef to save memory */
+#define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt */
 
 /*
  * choose between COM1 and COM2 as serial console
@@ -102,105 +102,105 @@
 #define CONFIG_CONS_INDEX       1
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE              1024        /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE              1024        /* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE              256         /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE              256         /* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS             16          /* max number of command args    */
-#define CFG_BARGSIZE            CFG_CBSIZE  /* Boot Argument Buffer Size    */
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS             16          /* max number of command args    */
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START       0x00000000  /* memtest works on    */
-#define CFG_MEMTEST_END         0x04000000  /* 0 ... 64 MB in DRAM    */
+#define CONFIG_SYS_MEMTEST_START       0x00000000  /* memtest works on    */
+#define CONFIG_SYS_MEMTEST_END         0x04000000  /* 0 ... 64 MB in DRAM    */
 
-#define CFG_LOAD_ADDR           0x1000000   /* default load address    */
+#define CONFIG_SYS_LOAD_ADDR           0x1000000   /* default load address    */
 
-#define CFG_HZ                  1000        /* dec. freq: 1 ms ticks */
+#define CONFIG_SYS_HZ                  1000        /* dec. freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
  * You should know what you are doing if you make changes here.
  */
-#define CFG_BOARD_ASM_INIT
+#define CONFIG_SYS_BOARD_ASM_INIT
 #define CONFIG_MISC_INIT_R
 
 /*
  * Choose the address mapping scheme for the MPC106 mem controller.
  * Default is mapping B (CHRP), set this define to choose mapping A (PReP).
  */
-#define CFG_ADDRESS_MAP_A
-#ifdef  CFG_ADDRESS_MAP_A
+#define CONFIG_SYS_ADDRESS_MAP_A
+#ifdef  CONFIG_SYS_ADDRESS_MAP_A
 
-#define CFG_PCI_MEMORY_BUS      0x80000000
-#define CFG_PCI_MEMORY_PHYS     0x00000000
-#define CFG_PCI_MEMORY_SIZE     0x80000000
+#define CONFIG_SYS_PCI_MEMORY_BUS      0x80000000
+#define CONFIG_SYS_PCI_MEMORY_PHYS     0x00000000
+#define CONFIG_SYS_PCI_MEMORY_SIZE     0x80000000
 
-#define CFG_PCI_MEM_BUS         0x00000000
-#define CFG_PCI_MEM_PHYS        0xc0000000
-#define CFG_PCI_MEM_SIZE        0x3f000000
+#define CONFIG_SYS_PCI_MEM_BUS         0x00000000
+#define CONFIG_SYS_PCI_MEM_PHYS        0xc0000000
+#define CONFIG_SYS_PCI_MEM_SIZE        0x3f000000
 
-#define CFG_ISA_MEM_BUS         0
-#define CFG_ISA_MEM_PHYS        0
-#define CFG_ISA_MEM_SIZE        0
+#define CONFIG_SYS_ISA_MEM_BUS         0
+#define CONFIG_SYS_ISA_MEM_PHYS        0
+#define CONFIG_SYS_ISA_MEM_SIZE        0
 
-#define CFG_PCI_IO_BUS          0x1000
-#define CFG_PCI_IO_PHYS         0x81000000
-#define CFG_PCI_IO_SIZE         0x01000000-CFG_PCI_IO_BUS
+#define CONFIG_SYS_PCI_IO_BUS          0x1000
+#define CONFIG_SYS_PCI_IO_PHYS         0x81000000
+#define CONFIG_SYS_PCI_IO_SIZE         0x01000000-CONFIG_SYS_PCI_IO_BUS
 
-#define CFG_ISA_IO_BUS          0x00000000
-#define CFG_ISA_IO_PHYS         0x80000000
-#define CFG_ISA_IO_SIZE         0x00800000
+#define CONFIG_SYS_ISA_IO_BUS          0x00000000
+#define CONFIG_SYS_ISA_IO_PHYS         0x80000000
+#define CONFIG_SYS_ISA_IO_SIZE         0x00800000
 
 #else
 
-#define CFG_PCI_MEMORY_BUS      0x00000000
-#define CFG_PCI_MEMORY_PHYS     0x00000000
-#define CFG_PCI_MEMORY_SIZE     0x40000000
+#define CONFIG_SYS_PCI_MEMORY_BUS      0x00000000
+#define CONFIG_SYS_PCI_MEMORY_PHYS     0x00000000
+#define CONFIG_SYS_PCI_MEMORY_SIZE     0x40000000
 
-#define CFG_PCI_MEM_BUS         0x80000000
-#define CFG_PCI_MEM_PHYS        0x80000000
-#define CFG_PCI_MEM_SIZE        0x7d000000
+#define CONFIG_SYS_PCI_MEM_BUS         0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS        0x80000000
+#define CONFIG_SYS_PCI_MEM_SIZE        0x7d000000
 
-#define CFG_ISA_MEM_BUS         0x00000000
-#define CFG_ISA_MEM_PHYS        0xfd000000
-#define CFG_ISA_MEM_SIZE        0x01000000
+#define CONFIG_SYS_ISA_MEM_BUS         0x00000000
+#define CONFIG_SYS_ISA_MEM_PHYS        0xfd000000
+#define CONFIG_SYS_ISA_MEM_SIZE        0x01000000
 
-#define CFG_PCI_IO_BUS          0x00800000
-#define CFG_PCI_IO_PHYS         0xfe800000
-#define CFG_PCI_IO_SIZE         0x00400000
+#define CONFIG_SYS_PCI_IO_BUS          0x00800000
+#define CONFIG_SYS_PCI_IO_PHYS         0xfe800000
+#define CONFIG_SYS_PCI_IO_SIZE         0x00400000
 
-#define CFG_ISA_IO_BUS          0x00000000
-#define CFG_ISA_IO_PHYS         0xfe000000
-#define CFG_ISA_IO_SIZE         0x00800000
+#define CONFIG_SYS_ISA_IO_BUS          0x00000000
+#define CONFIG_SYS_ISA_IO_PHYS         0xfe000000
+#define CONFIG_SYS_ISA_IO_SIZE         0x00800000
 
-#endif /*CFG_ADDRESS_MAP_A */
+#endif /*CONFIG_SYS_ADDRESS_MAP_A */
 
-#define CFG_60X_PCI_MEM_OFFSET  0x00000000
+#define CONFIG_SYS_60X_PCI_MEM_OFFSET  0x00000000
 
 /* driver defines FDC,IDE,... */
-#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
-#define CFG_ISA_IO              CFG_ISA_IO_PHYS
-#define CFG_60X_PCI_IO_OFFSET   CFG_ISA_IO_PHYS
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
+#define CONFIG_SYS_ISA_IO              CONFIG_SYS_ISA_IO_PHYS
+#define CONFIG_SYS_60X_PCI_IO_OFFSET   CONFIG_SYS_ISA_IO_PHYS
 
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE          0x00000000
-#define CFG_FLASH_BASE          0xfff00000
+#define CONFIG_SYS_SDRAM_BASE          0x00000000
+#define CONFIG_SYS_FLASH_BASE          0xfff00000
 
 /*
  * Definitions for initial stack pointer and data area
  */
-#define CFG_INIT_RAM_ADDR       0x00fd0000  /* above the memtest region */
-#define CFG_INIT_RAM_END        0x4000
-#define CFG_GBL_DATA_SIZE       64          /* size in bytes reserved for init data */
-#define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR       0x00fd0000  /* above the memtest region */
+#define CONFIG_SYS_INIT_RAM_END        0x4000
+#define CONFIG_SYS_GBL_DATA_SIZE       64          /* size in bytes reserved for init data */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Flash mapping/organization on the MPC10x.
@@ -208,11 +208,11 @@
 #define FLASH_BASE0_PRELIM      0xff800000
 #define FLASH_BASE1_PRELIM      0xffc00000
 
-#define CFG_MAX_FLASH_BANKS     2           /* max number of memory banks    */
-#define CFG_MAX_FLASH_SECT      67          /* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS     2           /* max number of memory banks    */
+#define CONFIG_SYS_MAX_FLASH_SECT      67          /* max number of sectors on one chip */
 
-#define CFG_FLASH_ERASE_TOUT    120000      /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT    500         /* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT    120000      /* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500         /* Timeout for Flash Write (in ms) */
 
 /*
  * JFFS2 partitions
@@ -234,36 +234,36 @@
 #define MTDPARTS_DEFAULT	"mtdparts=bab7xx-0:-(jffs2)"
 */
 
-#define CFG_MONITOR_BASE        CFG_FLASH_BASE
-#define CFG_MONITOR_LEN         0x40000     /* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN          0x20000     /* Reserve 128 kB for malloc() */
-#undef  CFG_MEMTEST
+#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN         0x40000     /* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN          0x20000     /* Reserve 128 kB for malloc() */
+#undef  CONFIG_SYS_MEMTEST
 
 /*
  * Environment settings
  */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_ENV_IS_IN_NVRAM     1           /* use NVRAM for environment vars */
-#define CFG_NVRAM_SIZE          0x1ff0      /* NVRAM size (8kB), we must protect the clock data (16 bytes) */
+#define CONFIG_SYS_NVRAM_SIZE          0x1ff0      /* NVRAM size (8kB), we must protect the clock data (16 bytes) */
 #define CONFIG_ENV_SIZE            0x400       /* Size of Environment vars (1kB) */
 /*
  * We store the environment and an image of revision eeprom in the upper part of the NVRAM. Thus,
  * user applications can use the remaining space for other purposes.
  */
-#define CONFIG_ENV_ADDR            (CFG_NVRAM_SIZE +0x10 -0x800)
-#define CFG_NV_SROM_COPY_ADDR   (CFG_NVRAM_SIZE +0x10 -0x400)
-#define CFG_NVRAM_ACCESS_ROUTINE            /* This board needs a special routine to access the NVRAM */
-#define CFG_SROM_SIZE           0x100       /* shadow of revision info is in nvram */
+#define CONFIG_ENV_ADDR            (CONFIG_SYS_NVRAM_SIZE +0x10 -0x800)
+#define CONFIG_SYS_NV_SROM_COPY_ADDR   (CONFIG_SYS_NVRAM_SIZE +0x10 -0x400)
+#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE            /* This board needs a special routine to access the NVRAM */
+#define CONFIG_SYS_SROM_SIZE           0x100       /* shadow of revision info is in nvram */
 
 /*
  * Serial devices
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
-#define CFG_NS16550_CLK         1843200
-#define CFG_NS16550_COM1        (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
-#define CFG_NS16550_COM2        (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK         1843200
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
 
 /*
  * PCI stuff
@@ -284,7 +284,7 @@
 #define CONFIG_CONSOLE_TIME
 #define CONFIG_CONSOLE_EXTRA_INFO
 #define CONFIG_CONSOLE_CURSOR
-#define CFG_CONSOLE_BLINK_COUNT         30000    /* approx. 2 HZ */
+#define CONFIG_SYS_CONSOLE_BLINK_COUNT         30000    /* approx. 2 HZ */
 
 /*
  * IDE/SCSI globals
@@ -302,15 +302,15 @@ extern unsigned char   scsi_sym53c8xx_ccf;
  * ATAPI Support (experimental)
  */
 #define CONFIG_ATAPI
-#define CFG_IDE_MAXBUS          1                       /* max. 2 IDE busses    */
-#define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*2)      /* max. 2 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS          1                       /* max. 2 IDE busses    */
+#define CONFIG_SYS_IDE_MAXDEVICE       (CONFIG_SYS_IDE_MAXBUS*2)      /* max. 2 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR       CFG_60X_PCI_IO_OFFSET   /* base address */
-#define CFG_ATA_IDE0_OFFSET     0x1F0                   /* default ide0 offste */
-#define CFG_ATA_IDE1_OFFSET     0x170                   /* default ide1 offset */
-#define CFG_ATA_DATA_OFFSET     0                       /* data reg offset    */
-#define CFG_ATA_REG_OFFSET      0                       /* reg offset */
-#define CFG_ATA_ALT_OFFSET      0x200                   /* alternate register offset */
+#define CONFIG_SYS_ATA_BASE_ADDR       CONFIG_SYS_60X_PCI_IO_OFFSET   /* base address */
+#define CONFIG_SYS_ATA_IDE0_OFFSET     0x1F0                   /* default ide0 offste */
+#define CONFIG_SYS_ATA_IDE1_OFFSET     0x170                   /* default ide1 offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET     0                       /* data reg offset    */
+#define CONFIG_SYS_ATA_REG_OFFSET      0                       /* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET      0x200                   /* alternate register offset */
 
 #define ATA_RESET_TIME          (ata_reset_time)
 
@@ -322,11 +322,11 @@ extern unsigned char   scsi_sym53c8xx_ccf;
  */
 #define CONFIG_SCSI_SYM53C8XX
 #define CONFIG_SCSI_DEV_ID      (scsi_dev_id)           /* 875 or 860 */
-#define CFG_SCSI_SYM53C8XX_CCF  (scsi_sym53c8xx_ccf)    /* value for none 40 mhz clocks */
-#define CFG_SCSI_MAX_LUN        8                       /* number of supported LUNs */
-#define CFG_SCSI_MAX_SCSI_ID    (scsi_max_scsi_id)      /* max SCSI ID (0-6) */
-#define CFG_SCSI_MAX_DEVICE     (15 * CFG_SCSI_MAX_LUN) /* max. Target devices */
-#define CFG_SCSI_SPIN_UP_TIME   (scsi_reset_time)
+#define CONFIG_SYS_SCSI_SYM53C8XX_CCF  (scsi_sym53c8xx_ccf)    /* value for none 40 mhz clocks */
+#define CONFIG_SYS_SCSI_MAX_LUN        8                       /* number of supported LUNs */
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID    (scsi_max_scsi_id)      /* max SCSI ID (0-6) */
+#define CONFIG_SYS_SCSI_MAX_DEVICE     (15 * CONFIG_SYS_SCSI_MAX_LUN) /* max. Target devices */
+#define CONFIG_SYS_SCSI_SPIN_UP_TIME   (scsi_reset_time)
 
 /*
  * Partion suppport
@@ -339,40 +339,40 @@ extern unsigned char   scsi_sym53c8xx_ccf;
  * Winbond Configuration
  */
 #define CONFIG_WINBOND_83C553      1                       /* has a winbond bridge */
-#define CFG_USE_WINBOND_IDE     0                       /* use winbond 83c553 internal ide */
-#define CFG_WINBOND_ISA_CFG_ADDR    0x80005800          /* pci-isa bridge config addr */
-#define CFG_WINBOND_IDE_CFG_ADDR    0x80005900          /* ide config addr */
+#define CONFIG_SYS_USE_WINBOND_IDE     0                       /* use winbond 83c553 internal ide */
+#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR    0x80005800          /* pci-isa bridge config addr */
+#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR    0x80005900          /* ide config addr */
 
 /*
  * NS87308 Configuration
  */
 #define CONFIG_NS87308                    /* Nat Semi super-io cntr on ISA bus */
-#define CFG_NS87308_BADDR_10    1
-#define CFG_NS87308_DEVS        (CFG_NS87308_UART1   | \
-				 CFG_NS87308_UART2   | \
-				 CFG_NS87308_KBC1    | \
-				 CFG_NS87308_MOUSE   | \
-				 CFG_NS87308_FDC     | \
-				 CFG_NS87308_RARP    | \
-				 CFG_NS87308_GPIO    | \
-				 CFG_NS87308_POWRMAN | \
-				 CFG_NS87308_RTC_APC )
-
-#define CFG_NS87308_PS2MOD
-#define CFG_NS87308_GPIO_BASE   0x0220
-#define CFG_NS87308_PWMAN_BASE  0x0460
-#define CFG_NS87308_PMC2        0x00        /* SuperI/O clock source is 24MHz via X1 */
+#define CONFIG_SYS_NS87308_BADDR_10    1
+#define CONFIG_SYS_NS87308_DEVS        (CONFIG_SYS_NS87308_UART1   | \
+				 CONFIG_SYS_NS87308_UART2   | \
+				 CONFIG_SYS_NS87308_KBC1    | \
+				 CONFIG_SYS_NS87308_MOUSE   | \
+				 CONFIG_SYS_NS87308_FDC     | \
+				 CONFIG_SYS_NS87308_RARP    | \
+				 CONFIG_SYS_NS87308_GPIO    | \
+				 CONFIG_SYS_NS87308_POWRMAN | \
+				 CONFIG_SYS_NS87308_RTC_APC )
+
+#define CONFIG_SYS_NS87308_PS2MOD
+#define CONFIG_SYS_NS87308_GPIO_BASE   0x0220
+#define CONFIG_SYS_NS87308_PWMAN_BASE  0x0460
+#define CONFIG_SYS_NS87308_PMC2        0x00        /* SuperI/O clock source is 24MHz via X1 */
 
 /*
  * set up the NVRAM access registers
  * NVRAM's controlled by the configurable CS line from the 87308
  */
-#define CFG_NS87308_CS0_BASE    0x0076
-#define CFG_NS87308_CS0_CONF    0x40
-#define CFG_NS87308_CS1_BASE    0x0070
-#define CFG_NS87308_CS1_CONF    0x1C
-#define CFG_NS87308_CS2_BASE    0x0071
-#define CFG_NS87308_CS2_CONF    0x1C
+#define CONFIG_SYS_NS87308_CS0_BASE    0x0076
+#define CONFIG_SYS_NS87308_CS0_CONF    0x40
+#define CONFIG_SYS_NS87308_CS1_BASE    0x0070
+#define CONFIG_SYS_NS87308_CS1_CONF    0x1C
+#define CONFIG_SYS_NS87308_CS2_BASE    0x0071
+#define CONFIG_SYS_NS87308_CS2_CONF    0x1C
 
 #define CONFIG_RTC_MK48T59
 
@@ -381,51 +381,51 @@ extern unsigned char   scsi_sym53c8xx_ccf;
  */
 #if 1
 
-#define CFG_IBAT0L 0
-#define CFG_IBAT0U 0
-#define CFG_DBAT0L CFG_IBAT1L
-#define CFG_DBAT0U CFG_IBAT1U
+#define CONFIG_SYS_IBAT0L 0
+#define CONFIG_SYS_IBAT0U 0
+#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
 
-#define CFG_IBAT1L 0
-#define CFG_IBAT1U 0
-#define CFG_DBAT1L CFG_IBAT1L
-#define CFG_DBAT1U CFG_IBAT1U
+#define CONFIG_SYS_IBAT1L 0
+#define CONFIG_SYS_IBAT1U 0
+#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
 
-#define CFG_IBAT2L 0
-#define CFG_IBAT2U 0
-#define CFG_DBAT2L CFG_IBAT2L
-#define CFG_DBAT2U CFG_IBAT2U
+#define CONFIG_SYS_IBAT2L 0
+#define CONFIG_SYS_IBAT2U 0
+#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
 
-#define CFG_IBAT3L 0
-#define CFG_IBAT3U 0
-#define CFG_DBAT3L CFG_IBAT3L
-#define CFG_DBAT3U CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L 0
+#define CONFIG_SYS_IBAT3U 0
+#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 
 #else
 
 /* SDRAM */
-#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW)
-#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L CFG_IBAT1L
-#define CFG_DBAT0U CFG_IBAT1U
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_RW)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
 
 /* address range for flashes */
-#define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L CFG_IBAT1L
-#define CFG_DBAT1U CFG_IBAT1U
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
 
 /* ISA IO space */
-#define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_DBAT2L CFG_IBAT2L
-#define CFG_DBAT2U CFG_IBAT2U
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
 
 /* ISA memory space */
-#define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_DBAT3L CFG_IBAT3L
-#define CFG_DBAT3U CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 
 #endif
 
@@ -436,35 +436,35 @@ extern unsigned char   scsi_sym53c8xx_ccf;
 extern  unsigned long           bab7xx_get_bus_freq (void);
 extern  unsigned long           bab7xx_get_gclk_freq (void);
 #endif
-#define CFG_BUS_HZ              bab7xx_get_bus_freq()
-#define CFG_BUS_CLK             CFG_BUS_HZ
-#define CFG_CPU_CLK             bab7xx_get_gclk_freq()
+#define CONFIG_SYS_BUS_HZ              bab7xx_get_bus_freq()
+#define CONFIG_SYS_BUS_CLK             CONFIG_SYS_BUS_HZ
+#define CONFIG_SYS_CPU_CLK             bab7xx_get_gclk_freq()
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ           (8 << 20)           /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ           (8 << 20)           /* Initial Memory map for Linux */
 
 /*
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE        32    /* For all MPC74xx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE        32    /* For all MPC74xx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT        5    /* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT        5    /* log base 2 of the above value */
 #endif
 
 /*
  * L2 Cache Configuration is board specific for BAB740/BAB750
  * Init values read from revision srom.
  */
-#undef  CFG_L2
+#undef  CONFIG_SYS_L2
 #define L2_INIT     (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 		     L2CR_L2OH_5   | L2CR_L2CTL   | L2CR_L2WT)
 #define L2_ENABLE   (L2_INIT | L2CR_L2E)
 
-#define CFG_L2_BAB7xx
+#define CONFIG_SYS_L2_BAB7xx
 
 /*
  * Internal Definitions
diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h
index 7fd6490..bced118 100644
--- a/include/configs/BC3450.h
+++ b/include/configs/BC3450.h
@@ -56,7 +56,7 @@
 #define CONFIG_BC3450_FP	1	/*  + enable FP O/P		    */
 #undef CONFIG_BC3450_CRT		/*  + enable CRT O/P (Debug only!)  */
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz	    */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz	    */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot		    */
@@ -68,7 +68,7 @@
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1		*/
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps		*/
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*
  * AT-PS/2 Multiplexer
@@ -77,7 +77,7 @@
 # define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
 # define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
 # define CONFIG_PS2SERIAL	6		/* .. on PSC6		*/
-# define CONFIG_PS2MULT_DELAY	(CFG_HZ/2)	/* Initial delay	*/
+# define CONFIG_PS2MULT_DELAY	(CONFIG_SYS_HZ/2)	/* Initial delay	*/
 # define CONFIG_BOARD_EARLY_INIT_R
 #endif /* CONFIG_BC3450_PS2 */
 
@@ -101,7 +101,7 @@
 
 #define CONFIG_NET_MULTI	1
 /*#define CONFIG_EEPRO100	XXX - FIXME: conflicts when CONFIG_MII is enabled */
-#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
+#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
 #define CONFIG_NS8382X		1
 
 /*
@@ -116,7 +116,7 @@
 # define CONFIG_CONSOLE_EXTRA_INFO	/* display Board/Device-Infos */
 # define CONFIG_VIDEO_SW_CURSOR
 # define CONFIG_SPLASH_SCREEN
-# define CFG_CONSOLE_IS_IN_ENV
+# define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
 /*
  * Partitions
@@ -136,9 +136,9 @@
 /*
  * POST support
  */
-#define CONFIG_POST		(CFG_POST_MEMORY   | \
-				 CFG_POST_CPU	   | \
-				 CFG_POST_I2C)
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_I2C)
 
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
@@ -208,7 +208,7 @@
 #define CONFIG_TIMESTAMP		/* display image timestamps */
 
 #if (TEXT_BASE == 0xFC000000)		/* Boot low */
-#   define CFG_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT		1
 #endif
 
 /*
@@ -268,24 +268,24 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
  *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
-# define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
+#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
+# define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
 
 /*
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		2	/* Select I2C module #2 */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #2 */
 
 /*
  * I2C clock frequency
@@ -293,11 +293,11 @@
  * Please notice, that the resulting clock frequency could differ from the
  * configured value. This is because the I2C clock is derived from system
  * clock over a frequency divider with only a few divider values. U-boot
- * calculates the best approximation for CFG_I2C_SPEED. However the calculated
+ * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
  * approximation allways lies below the configured value, never above.
  */
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration for I²C EEPROM M24C32
@@ -305,17 +305,17 @@
  *
  * The TQM5200 module may hold an EEPROM at address 0x50.
  */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x (TQM) */
-#define CFG_I2C_EEPROM_ADDR_LEN		2
-#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x (TQM) */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
 
 /*
  * RTC configuration
  */
 #if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
 # define CONFIG_RTC_M41T11	1
-# define CFG_I2C_RTC_ADDR	0x68
+# define CONFIG_SYS_I2C_RTC_ADDR	0x68
 #else
 # define CONFIG_RTC_MPC5200	1	/* use MPC5200 internal RTC */
 # define CONFIG_BOARD_EARLY_INIT_R
@@ -324,26 +324,26 @@
 /*
  * Flash configuration
  */
-#define CFG_FLASH_BASE		TEXT_BASE /* 0xFC000000 */
+#define CONFIG_SYS_FLASH_BASE		TEXT_BASE /* 0xFC000000 */
 
 /* use CFI flash driver if no module variant is spezified */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
-#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
-#undef CFG_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
-
-#if !defined(CFG_LOWBOOT)
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00760000 + 0x00800000)
-#else	/* CFG_LOWBOOT */
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
-#endif	/* CFG_LOWBOOT */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_BOOTCS_START }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MByte */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
+
+#if !defined(CONFIG_SYS_LOWBOOT)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
+#else	/* CONFIG_SYS_LOWBOOT */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
+#endif	/* CONFIG_SYS_LOWBOOT */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
 					   (= chip selects) */
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
 
 /* Dynamic MTD partition support */
 #define CONFIG_JFFS2_CMDLINE
@@ -367,39 +367,40 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /* Use ON-Chip SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-# define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+# define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
 #else
-# define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+# define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
 #endif /*CONFIG_POST*/
 
-#define CFG_GBL_DATA_SIZE	128	/* Bytes reserved for initial data  */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* Bytes reserved for initial data  */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(384 << 10) /* Reserve 384 kB for Monitor   */
-#define CFG_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
-#define CFG_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10) /* Reserve 384 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
  *
- * Define CONFIG_FEC10MBIT to force FEC at 10MBIT
+ * Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT
  */
 #define CONFIG_MPC5xxx_FEC	1
-#undef CONFIG_FEC_10MBIT
+#define CONFIG_MPC5xxx_FEC_MII100
+#undef CONFIG_MPC5xxx_MII10
 #define CONFIG_PHY_ADDR		0x00
 
 /*
@@ -426,38 +427,38 @@
  *  I2C:    CAN1 / I²C2		  [0x bxxxxxxx]
  */
 #ifdef CONFIG_BC3450_AC97
-# define CFG_GPS_PORT_CONFIG	0xb1502124
+# define CONFIG_SYS_GPS_PORT_CONFIG	0xb1502124
 #else /* PSC2=UART2 */
-# define CFG_GPS_PORT_CONFIG	0xb1502144
+# define CONFIG_SYS_GPS_PORT_CONFIG	0xb1502144
 #endif
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory	    */
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size  */
-#define CFG_MAXARGS		16		/* max no of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Arg. Buffer Size    */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size  */
+#define CONFIG_SYS_MAXARGS		16		/* max no of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Arg. Buffer Size    */
 
-#define CFG_ALT_MEMTEST				/* Enable an alternative,   */
+#define CONFIG_SYS_ALT_MEMTEST				/* Enable an alternative,   */
 						/*  more extensive mem test */
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	    */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	    */
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	    */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	    */
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address	    */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	    */
 
-#define CFG_HZ			1000		/* dec freq: 1ms ticks	    */
+#define CONFIG_SYS_HZ			1000		/* dec freq: 1ms ticks	    */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs		    */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs		    */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value    */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value    */
 #endif
 
 /*
@@ -469,22 +470,22 @@
  * Various low-level settings
  */
 #if defined(CONFIG_MPC5200)
-# define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-# define CFG_HID0_FINAL		HID0_ICE
+# define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+# define CONFIG_SYS_HID0_FINAL		HID0_ICE
 #else
-# define CFG_HID0_INIT		0
-# define CFG_HID0_FINAL		0
+# define CONFIG_SYS_HID0_INIT		0
+# define CONFIG_SYS_HID0_FINAL		0
 #endif
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
-# define CFG_BOOTCS_CFG		0x0008DF30	/* for pci_clk	= 66 MHz */
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
+# define CONFIG_SYS_BOOTCS_CFG		0x0008DF30	/* for pci_clk	= 66 MHz */
 #else
-# define CFG_BOOTCS_CFG		0x0004DF30	/* for pci_clk = 33 MHz	 */
+# define CONFIG_SYS_BOOTCS_CFG		0x0004DF30	/* for pci_clk = 33 MHz	 */
 #endif
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
 /* automatic configuration of chip selects */
 #ifdef CONFIG_TQM5200
@@ -496,9 +497,9 @@
  * for SDRAM autosizing.
  */
 #ifdef CONFIG_TQM5200
-# define CFG_CS2_START		0xE5000000
-# define CFG_CS2_SIZE		0x100000	/* 1 MByte */
-# define CFG_CS2_CFG		0x0004D930
+# define CONFIG_SYS_CS2_START		0xE5000000
+# define CONFIG_SYS_CS2_SIZE		0x100000	/* 1 MByte */
+# define CONFIG_SYS_CS2_CFG		0x0004D930
 #endif /* CONFIG_TQM5200 */
 
 /*
@@ -507,17 +508,17 @@
  */
 #ifdef CONFIG_TQM5200
 # define SM501_FB_BASE		0xE0000000
-# define CFG_CS1_START		(SM501_FB_BASE)
-# define CFG_CS1_SIZE		0x4000000	/* 64 MByte */
-# define CFG_CS1_CFG		0x8F48FF70
-# define SM501_MMIO_BASE	CFG_CS1_START + 0x03E00000
+# define CONFIG_SYS_CS1_START		(SM501_FB_BASE)
+# define CONFIG_SYS_CS1_SIZE		0x4000000	/* 64 MByte */
+# define CONFIG_SYS_CS1_CFG		0x8F48FF70
+# define SM501_MMIO_BASE	CONFIG_SYS_CS1_START + 0x03E00000
 #endif /* CONFIG_TQM5200 */
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for	*/
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for	*/
 						/*  flash and SM501	*/
 
-#define CFG_RESET_ADDRESS	0xff000000
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
 
 /*
  * USB stuff
@@ -536,23 +537,23 @@
 #define CONFIG_IDE_RESET		/* reset for ide      supported */
 #define CONFIG_IDE_PREINIT
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
 
 /* Offset for data I/O */
-#define CFG_ATA_DATA_OFFSET	(0x0060)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
 
 /* Offset for normal register accesses */
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
 
 /* Offset for alternate registers */
-#define CFG_ATA_ALT_OFFSET	(0x005C)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
 
 /* Interval between registers */
-#define CFG_ATA_STRIDE		4
+#define CONFIG_SYS_ATA_STRIDE		4
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/BMW.h b/include/configs/BMW.h
index d5a398d..24ffb00 100644
--- a/include/configs/BMW.h
+++ b/include/configs/BMW.h
@@ -52,18 +52,18 @@
 
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		9600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz	*/
 
 #define CONFIG_BOOTCOMMAND	"bootm FF820000"	/* autoboot command	*/
 #define CONFIG_BOOTDELAY	5
 
-#define CFG_MAX_DOC_DEVICE      1 /* Only use Onboard TSOP-16MB device */
+#define CONFIG_SYS_MAX_DOC_DEVICE      1 /* Only use Onboard TSOP-16MB device */
 #define DOC_PASSIVE_PROBE       1
-#define CFG_DOC_SUPPORT_2000    1
-#define CFG_DOC_SUPPORT_MILLENNIUM 1
-#define CFG_DOC_SHORT_TIMEOUT    1
+#define CONFIG_SYS_DOC_SUPPORT_2000    1
+#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM 1
+#define CONFIG_SYS_DOC_SHORT_TIMEOUT    1
 
 
 /*
@@ -96,66 +96,66 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=>"	        /* Monitor Command Prompt	*/
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=>"	        /* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 
 /* Print Buffer Size
  */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 
-#define CFG_MAXARGS	8		/* Max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
+#define CONFIG_SYS_MAXARGS	8		/* Max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE	    0x00000000
+#define CONFIG_SYS_SDRAM_BASE	    0x00000000
 
-#define CFG_FLASH_BASE0_PRELIM      0xFFF00000      /* FLASH bank on RCS#0 */
-#define CFG_FLASH_BASE1_PRELIM      0xFF800000      /* FLASH bank on RCS#1 */
-#define CFG_FLASH_BASE  CFG_MONITOR_BASE
-#define CFG_FLASH_BANKS		{ CFG_FLASH_BASE0_PRELIM , CFG_FLASH_BASE1_PRELIM }
+#define CONFIG_SYS_FLASH_BASE0_PRELIM      0xFFF00000      /* FLASH bank on RCS#0 */
+#define CONFIG_SYS_FLASH_BASE1_PRELIM      0xFF800000      /* FLASH bank on RCS#1 */
+#define CONFIG_SYS_FLASH_BASE  CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_FLASH_BANKS		{ CONFIG_SYS_FLASH_BASE0_PRELIM , CONFIG_SYS_FLASH_BASE1_PRELIM }
 
 /* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
  * reset vector is actually located at FFB00100, but the 8245
  * takes care of us.
  */
-#define CFG_RESET_ADDRESS   0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 
-#define CFG_EUMB_ADDR	    0xFC000000
+#define CONFIG_SYS_EUMB_ADDR	    0xFC000000
 
-#define CFG_MONITOR_BASE    TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
 
-#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (2048 << 10) /* Reserve 2MB for malloc()	*/
+#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN	    (2048 << 10) /* Reserve 2MB for malloc()	*/
 
-#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END	    0x04000000	/* 0 ... 32 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END	    0x04000000	/* 0 ... 32 MB in DRAM		*/
 
 	/* Maximum amount of RAM.
 	 */
-#define CFG_MAX_RAM_SIZE    0x04000000	/* 0 .. 64 MB of (S)DRAM */
+#define CONFIG_SYS_MAX_RAM_SIZE    0x04000000	/* 0 .. 64 MB of (S)DRAM */
 
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#undef CFG_RAMBOOT
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#undef CONFIG_SYS_RAMBOOT
 #else
-#define CFG_RAMBOOT
+#define CONFIG_SYS_RAMBOOT
 #endif
 
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area
  */
-#define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN
-#define CFG_INIT_RAM_END   0x2F00  /* End of used area in DPRAM  */
-#define CFG_GBL_DATA_SIZE  128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET  CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
+#define CONFIG_SYS_INIT_RAM_END   0x2F00  /* End of used area in DPRAM  */
+#define CONFIG_SYS_GBL_DATA_SIZE  128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Low Level Configuration Settings
@@ -165,43 +165,43 @@
  */
 
 #define CONFIG_SYS_CLK_FREQ  33000000	/* external frequency to pll */
-#define CFG_HZ		     1000
+#define CONFIG_SYS_HZ		     1000
 
-#define CFG_ETH_DEV_FN	     0x7800
-#define CFG_ETH_IOBASE	     0x00104000
+#define CONFIG_SYS_ETH_DEV_FN	     0x7800
+#define CONFIG_SYS_ETH_IOBASE	     0x00104000
 
 	/* Bit-field values for MCCR1.
 	 */
-#define CFG_ROMNAL	    0xf
-#define CFG_ROMFAL	    0x1f
-#define CFG_DBUS_SIZE       0x3
+#define CONFIG_SYS_ROMNAL	    0xf
+#define CONFIG_SYS_ROMFAL	    0x1f
+#define CONFIG_SYS_DBUS_SIZE       0x3
 
 	/* Bit-field values for MCCR2.
 	 */
-#define CFG_TSWAIT	    0x5		    /* Transaction Start Wait States timer */
-#define CFG_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
+#define CONFIG_SYS_TSWAIT	    0x5		    /* Transaction Start Wait States timer */
+#define CONFIG_SYS_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
 
 	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 	 */
-#define CFG_BSTOPRE	    0		/* FIXME: was 192 */
+#define CONFIG_SYS_BSTOPRE	    0		/* FIXME: was 192 */
 
 	/* Bit-field values for MCCR3.
 	 */
-#define CFG_REFREC	    2	    /* Refresh to activate interval */
+#define CONFIG_SYS_REFREC	    2	    /* Refresh to activate interval */
 
 	/* Bit-field values for MCCR4.
 	 */
-#define CFG_PRETOACT	    2	    /* Precharge to activate interval FIXME: was 2	*/
-#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval FIXME: was 5	*/
-#define CFG_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
-#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
-#define CFG_SDMODE_BURSTLEN 3	    /* SDMODE Burst length */
-#define CFG_ACTORW	    0xa		/* FIXME was 2 */
-#define CFG_REGISTERD_TYPE_BUFFER 1
+#define CONFIG_SYS_PRETOACT	    2	    /* Precharge to activate interval FIXME: was 2	*/
+#define CONFIG_SYS_ACTTOPRE	    5	    /* Activate to Precharge interval FIXME: was 5	*/
+#define CONFIG_SYS_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
+#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
+#define CONFIG_SYS_SDMODE_BURSTLEN 3	    /* SDMODE Burst length */
+#define CONFIG_SYS_ACTORW	    0xa		/* FIXME was 2 */
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
 
-#define CFG_PGMAX           0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
+#define CONFIG_SYS_PGMAX           0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
 
-#define CFG_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
+#define CONFIG_SYS_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
 
 /* Memory bank settings.
  * Only bits 20-29 are actually used from these vales to set the
@@ -210,32 +210,32 @@
  * address. Refer to the MPC8240 book.
  */
 
-#define CFG_BANK0_START	    0x00000000
-#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START	    0x3ff00000
-#define CFG_BANK1_END	    0x3fffffff
-#define CFG_BANK1_ENABLE    0
-#define CFG_BANK2_START	    0x3ff00000
-#define CFG_BANK2_END	    0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START	    0x3ff00000
-#define CFG_BANK3_END	    0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START	    0x3ff00000
-#define CFG_BANK4_END	    0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START	    0x3ff00000
-#define CFG_BANK5_END	    0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START	    0x3ff00000
-#define CFG_BANK6_END	    0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START	    0x3ff00000
-#define CFG_BANK7_END	    0x3fffffff
-#define CFG_BANK7_ENABLE    0
-
-#define CFG_ODCR	    0xff
+#define CONFIG_SYS_BANK0_START	    0x00000000
+#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE    1
+#define CONFIG_SYS_BANK1_START	    0x3ff00000
+#define CONFIG_SYS_BANK1_END	    0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE    0
+#define CONFIG_SYS_BANK2_START	    0x3ff00000
+#define CONFIG_SYS_BANK2_END	    0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE    0
+#define CONFIG_SYS_BANK3_START	    0x3ff00000
+#define CONFIG_SYS_BANK3_END	    0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE    0
+#define CONFIG_SYS_BANK4_START	    0x3ff00000
+#define CONFIG_SYS_BANK4_END	    0x3fffffff
+#define CONFIG_SYS_BANK4_ENABLE    0
+#define CONFIG_SYS_BANK5_START	    0x3ff00000
+#define CONFIG_SYS_BANK5_END	    0x3fffffff
+#define CONFIG_SYS_BANK5_ENABLE    0
+#define CONFIG_SYS_BANK6_START	    0x3ff00000
+#define CONFIG_SYS_BANK6_END	    0x3fffffff
+#define CONFIG_SYS_BANK6_ENABLE    0
+#define CONFIG_SYS_BANK7_START	    0x3ff00000
+#define CONFIG_SYS_BANK7_END	    0x3fffffff
+#define CONFIG_SYS_BANK7_ENABLE    0
+
+#define CONFIG_SYS_ODCR	    0xff
 
 #define CONFIG_PCI              1 /* Include PCI support */
 #undef CONFIG_PCI_PNP
@@ -248,42 +248,42 @@
 #include "../board/bmw/bmw.h"
 
 /* BAT configuration */
-#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
-#define CFG_IBAT1L  (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT1U  (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L  (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1U  (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
-#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
-#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
-#define CFG_DBAT0L  CFG_IBAT0L
-#define CFG_DBAT0U  CFG_IBAT0U
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-#define CFG_DBAT2L  CFG_IBAT2L
-#define CFG_DBAT2U  CFG_IBAT2U
-#define CFG_DBAT3L  CFG_IBAT3L
-#define CFG_DBAT3U  CFG_IBAT3U
+#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	0	/* Max number of flash banks	    */
-#define CFG_MAX_FLASH_SECT	64	/* Max number of sectors per  flash */
+#define CONFIG_SYS_MAX_FLASH_BANKS	0	/* Max number of flash banks	    */
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* Max number of sectors per  flash */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
 
 /*
  * Warining: environment is not EMBEDDED in the U-Boot code.
@@ -291,7 +291,7 @@
  */
 #define CONFIG_ENV_IS_IN_NVRAM      1
 #define CONFIG_ENV_OVERWRITE     1
-#define CFG_NVRAM_ACCESS_ROUTINE 1
+#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
 #define CONFIG_ENV_ADDR		0x7c004000 /* right at the start of NVRAM  */
 #define CONFIG_ENV_SIZE		0x1ff0	/* Size of the Environment - 8K	   */
 #define CONFIG_ENV_OFFSET		0	/* starting right at the beginning */
@@ -299,9 +299,9 @@
 /*
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SIZE	32
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value   */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value   */
 #endif
 
 /*
diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h
index be58838..e3e6e75 100644
--- a/include/configs/CANBT.h
+++ b/include/configs/CANBT.h
@@ -50,7 +50,7 @@
 	"bootm ffe00000 ffe80000"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/
 
@@ -84,74 +84,74 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_EXT_SERIAL_CLOCK	14745600 /* use external serial clock	*/
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	14745600 /* use external serial clock	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFE0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(128 * 1024)	/* Reserve 128 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFE0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)	/* Reserve 128 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* Use FLASH for environment variables */
 
@@ -173,13 +173,13 @@
  * I2C EEPROM (CAT24WC08) for environment
  */
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
 
 /*
  * Init Memory Controller:
@@ -195,29 +195,29 @@
  */
 
 /* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (CAN/USB) initialization					*/
-#define CFG_EBC_PB1AP		0x010053C0  /* enable Ready, BEM=1		*/
-#define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB1AP		0x010053C0  /* enable Ready, BEM=1		*/
+#define CONFIG_SYS_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 2 (Misc-IO/LEDs) initialization					*/
-#define CFG_EBC_PB2AP		0x000004c0  /* no Ready, BEM=1			*/
-#define CFG_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2AP		0x000004c0  /* no Ready, BEM=1			*/
+#define CONFIG_SYS_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 3 (CAN Features) initialization					*/
-#define CFG_EBC_PB3AP		0x80000040  /* no Ready, BEM=1			*/
-#define CFG_EBC_PB3CR		0xF021C000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */
+#define CONFIG_SYS_EBC_PB3AP		0x80000040  /* no Ready, BEM=1			*/
+#define CONFIG_SYS_EBC_PB3CR		0xF021C000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in RAM)
  */
-#define CFG_INIT_RAM_ADDR	0x00ef0000 /* inside of SDRAM			*/
-#define CFG_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x00ef0000 /* inside of SDRAM			*/
+#define CONFIG_SYS_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 
 /*
diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
index 8862898..fa9fc23 100644
--- a/include/configs/CATcenter.h
+++ b/include/configs/CATcenter.h
@@ -63,7 +63,7 @@
 #define __DISABLE_MACHINE_EXCEPTION__
 
 #ifdef __DEBUG_START_FROM_SRAM__
-#define CFG_DUMMY_FLASH_SIZE		1024*1024*4
+#define CONFIG_SYS_DUMMY_FLASH_SIZE		1024*1024*4
 #endif
 
 /*
@@ -102,7 +102,7 @@
 #define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 
 #undef CONFIG_EXT_PHY
@@ -152,50 +152,49 @@
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
+#define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
-#define	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK		/* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD		691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK		/* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD		691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
@@ -203,13 +202,13 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_NAND0_BASE 0xFF400000
-#define CFG_NAND1_BASE 0xFF000000
-#define CFG_NAND_BASE_LIST	{ CFG_NAND0_BASE }
+#define CONFIG_SYS_NAND0_BASE 0xFF400000
+#define CONFIG_SYS_NAND1_BASE 0xFF000000
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND0_BASE }
 #define NAND_BIG_DELAY_US	25
 
 /* For CATcenter there is only NAND on the module */
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
 #define SECTORSIZE 512
 #define NAND_NO_RB
 
@@ -219,28 +218,27 @@
 
 #define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
 
-#define CFG_NAND0_CE  (0x80000000 >> 1)	 /* our CE is GPIO1 */
-#define CFG_NAND0_CLE (0x80000000 >> 2)	 /* our CLE is GPIO2 */
-#define CFG_NAND0_ALE (0x80000000 >> 3)	 /* our ALE is GPIO3 */
-#define CFG_NAND0_RDY (0x80000000 >> 4)	 /* our RDY is GPIO4 */
+#define CONFIG_SYS_NAND0_CE  (0x80000000 >> 1)	 /* our CE is GPIO1 */
+#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2)	 /* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3)	 /* our ALE is GPIO3 */
+#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4)	 /* our RDY is GPIO4 */
 
-#define CFG_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
-#define CFG_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
-#define CFG_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
-#define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
+#define CONFIG_SYS_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
+#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
+#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
+#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
 
 
 #define MACRO_NAND_DISABLE_CE(nandptr) do \
 { \
 	switch((unsigned long)nandptr) \
 	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
 		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
 		break; \
 	} \
 } while(0)
@@ -249,11 +247,11 @@
 { \
 	switch((unsigned long)nandptr) \
 	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
 		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
 		break; \
 	} \
 } while(0)
@@ -262,11 +260,11 @@
 { \
 	switch((unsigned long)nandptr) \
 	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
 		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
 		break; \
 	} \
 } while(0)
@@ -275,11 +273,11 @@
 { \
 	switch((unsigned long)nandptr) \
 	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
 		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
 		break; \
 	} \
 } while(0)
@@ -288,22 +286,22 @@
 { \
 	switch((unsigned long)nandptr) \
 	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
 		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
 		break; \
 	} \
 } while(0)
 
 #define MACRO_NAND_CTL_SETCLE(nandptr) do { \
 	switch((unsigned long)nandptr) { \
-	case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
+	case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
 		break; \
-	case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
+	case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
 		break; \
 	} \
 } while(0)
@@ -339,56 +337,56 @@
 
 #define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* PCI Vendor ID: IBM	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: ---	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* PCI Vendor ID: IBM	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: ---	*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
 
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 #endif	/* No PCI */
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 /*-----------------------------------------------------------------------
  * Environment Variable setup
@@ -399,36 +397,35 @@
 #define CONFIG_ENV_ADDR_REDUND	0xFFFFA000
 #define CONFIG_ENV_SIZE_REDUND	0x2000
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
-#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07*/
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+#define CONFIG_SYS_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
 					/* have only 8kB, 16kB is save here	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* ...			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /*
@@ -444,21 +441,21 @@
  */
 
 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (External SRAM) initialization					*/
 /* Since this must replace NOR Flash, we use the same settings for CS0		*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization			*/
-#define CFG_EBC_PB2AP		0x92015480
-#define CFG_EBC_PB2CR		0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2AP		0x92015480
+#define CONFIG_SYS_EBC_PB2CR		0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization			*/
-#define CFG_EBC_PB3AP		0x92015480
-#define CFG_EBC_PB3CR		0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB3AP		0x92015480
+#define CONFIG_SYS_EBC_PB3CR		0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit	*/
 
 #ifdef CONFIG_PPCHAMELEON_SMI712
 /*
@@ -472,66 +469,66 @@
 #define CONFIG_CONSOLE_EXTRA_INFO
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
-#define CFG_ISA_IO 0xE8000000
+#define CONFIG_SYS_ISA_IO 0xE8000000
 /* see also drivers/video/videomodes.c */
-#define CFG_DEFAULT_VIDEO_MODE 0x303
+#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
 #endif
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
 /* FPGA internal regs */
-#define CFG_FPGA_MODE		0x00
-#define CFG_FPGA_STATUS		0x02
-#define CFG_FPGA_TS		0x04
-#define CFG_FPGA_TS_LOW		0x06
-#define CFG_FPGA_TS_CAP0	0x10
-#define CFG_FPGA_TS_CAP0_LOW	0x12
-#define CFG_FPGA_TS_CAP1	0x14
-#define CFG_FPGA_TS_CAP1_LOW	0x16
-#define CFG_FPGA_TS_CAP2	0x18
-#define CFG_FPGA_TS_CAP2_LOW	0x1a
-#define CFG_FPGA_TS_CAP3	0x1c
-#define CFG_FPGA_TS_CAP3_LOW	0x1e
+#define CONFIG_SYS_FPGA_MODE		0x00
+#define CONFIG_SYS_FPGA_STATUS		0x02
+#define CONFIG_SYS_FPGA_TS		0x04
+#define CONFIG_SYS_FPGA_TS_LOW		0x06
+#define CONFIG_SYS_FPGA_TS_CAP0	0x10
+#define CONFIG_SYS_FPGA_TS_CAP0_LOW	0x12
+#define CONFIG_SYS_FPGA_TS_CAP1	0x14
+#define CONFIG_SYS_FPGA_TS_CAP1_LOW	0x16
+#define CONFIG_SYS_FPGA_TS_CAP2	0x18
+#define CONFIG_SYS_FPGA_TS_CAP2_LOW	0x1a
+#define CONFIG_SYS_FPGA_TS_CAP3	0x1c
+#define CONFIG_SYS_FPGA_TS_CAP3_LOW	0x1e
 
 /* FPGA Mode Reg */
-#define CFG_FPGA_MODE_CF_RESET	0x0001
-#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
-#define CFG_FPGA_MODE_TS_CLEAR	0x2000
+#define CONFIG_SYS_FPGA_MODE_CF_RESET	0x0001
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CONFIG_SYS_FPGA_MODE_TS_CLEAR	0x2000
 
 /* FPGA Status Reg */
-#define CFG_FPGA_STATUS_DIP0	0x0001
-#define CFG_FPGA_STATUS_DIP1	0x0002
-#define CFG_FPGA_STATUS_DIP2	0x0004
-#define CFG_FPGA_STATUS_FLASH	0x0008
-#define CFG_FPGA_STATUS_TS_IRQ	0x1000
+#define CONFIG_SYS_FPGA_STATUS_DIP0	0x0001
+#define CONFIG_SYS_FPGA_STATUS_DIP1	0x0002
+#define CONFIG_SYS_FPGA_STATUS_DIP2	0x0004
+#define CONFIG_SYS_FPGA_STATUS_FLASH	0x0008
+#define CONFIG_SYS_FPGA_STATUS_TS_IRQ	0x1000
 
-#define CFG_FPGA_SPARTAN2	1		/* using Xilinx Spartan 2 now	*/
-#define CFG_FPGA_MAX_SIZE	128*1024	/* 128kByte is enough for XC2S50E*/
+#define CONFIG_SYS_FPGA_SPARTAN2	1		/* using Xilinx Spartan 2 now	*/
+#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024	/* 128kByte is enough for XC2S50E*/
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000	/* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000	/* FPGA clk pin (ppc output)	*/
-#define CFG_FPGA_DATA		0x01000000	/* FPGA data pin (ppc output)	*/
-#define CFG_FPGA_INIT		0x00010000	/* FPGA init pin (ppc input)	*/
-#define CFG_FPGA_DONE		0x00008000	/* FPGA done pin (ppc input)	*/
+#define CONFIG_SYS_FPGA_PRG		0x04000000	/* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000	/* FPGA clk pin (ppc output)	*/
+#define CONFIG_SYS_FPGA_DATA		0x01000000	/* FPGA data pin (ppc output)	*/
+#define CONFIG_SYS_FPGA_INIT		0x00010000	/* FPGA init pin (ppc input)	*/
+#define CONFIG_SYS_FPGA_DONE		0x00008000	/* FPGA done pin (ppc input)	*/
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	1
+#define CONFIG_SYS_TEMP_STACK_OCM	1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
 
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup (PPC405EP specific)
@@ -546,14 +543,14 @@
  * GPIO0[30]	- EMAC0 input
  * GPIO0[31]	- EMAC1 reject packet as output
  */
-#define CFG_GPIO0_OSRH		0x40000550
-#define CFG_GPIO0_OSRL		0x00000110
-#define CFG_GPIO0_ISR1H		0x00000000
-/*#define CFG_GPIO0_ISR1L	0x15555445*/
-#define CFG_GPIO0_ISR1L		0x15555444
-#define CFG_GPIO0_TSRH		0x00000000
-#define CFG_GPIO0_TSRL		0x00000000
-#define CFG_GPIO0_TCR		0xF7FF8014
+#define CONFIG_SYS_GPIO0_OSRH		0x40000550
+#define CONFIG_SYS_GPIO0_OSRL		0x00000110
+#define CONFIG_SYS_GPIO0_ISR1H		0x00000000
+/*#define CONFIG_SYS_GPIO0_ISR1L	0x15555445*/
+#define CONFIG_SYS_GPIO0_ISR1L		0x15555444
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0xF7FF8014
 
 /*
  * Internal Definitions
@@ -761,17 +758,17 @@
 /* Model HI */
 #define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_333_111_37_55_55
 #define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_333_111_37_55_55
-#define CFG_OPB_FREQ	55555555
+#define CONFIG_SYS_OPB_FREQ	55555555
 /* Model ME */
 #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
 #define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_266_133_33_66_33
 #define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_266_133_33_66_33
-#define CFG_OPB_FREQ	66666666
+#define CONFIG_SYS_OPB_FREQ	66666666
 #else
 /* Model BA (default) */
 #define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_133_133_33_66_33
 #define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_133_133_33_66_33
-#define CFG_OPB_FREQ	66666666
+#define CONFIG_SYS_OPB_FREQ	66666666
 #endif
 
 #endif /* CONFIG_NO_SERIAL_EEPROM */
diff --git a/include/configs/CCM.h b/include/configs/CCM.h
index 435e8ec..d1c293f 100644
--- a/include/configs/CCM.h
+++ b/include/configs/CCM.h
@@ -65,7 +65,7 @@
 				"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE	/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE	/* don't allow baudrate change	*/
 
 #define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/
 
@@ -86,9 +86,9 @@
  * far enough from the start of the data area (as well as from the
  * stack pointer).
  * ---------------------------------------------------------------- */
-#define CFG_SPI_INIT_OFFSET		0xB00
+#define CONFIG_SYS_SPI_INIT_OFFSET		0xB00
 
-#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 32-byte page size	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 32-byte page size	*/
 
 
 #define CONFIG_MAC_PARTITION		/* nod used yet			*/
@@ -120,46 +120,46 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address	*/
 
 /* Ethernet hardware configuration done using port pins */
-#define CFG_PA_ETH_RESET	0x0200		/* PA  6	*/
-#define CFG_PA_ETH_MDDIS	0x4000		/* PA  1	*/
-#define CFG_PB_ETH_POWERDOWN	0x00000800	/* PB 20	*/
-#define CFG_PB_ETH_CFG1		0x00000400	/* PB 21	*/
-#define CFG_PB_ETH_CFG2		0x00000200	/* PB 22	*/
-#define CFG_PB_ETH_CFG3		0x00000100	/* PB 23	*/
+#define CONFIG_SYS_PA_ETH_RESET	0x0200		/* PA  6	*/
+#define CONFIG_SYS_PA_ETH_MDDIS	0x4000		/* PA  1	*/
+#define CONFIG_SYS_PB_ETH_POWERDOWN	0x00000800	/* PB 20	*/
+#define CONFIG_SYS_PB_ETH_CFG1		0x00000400	/* PB 21	*/
+#define CONFIG_SYS_PB_ETH_CFG2		0x00000200	/* PB 22	*/
+#define CONFIG_SYS_PB_ETH_CFG3		0x00000100	/* PB 23	*/
 
 /* Ethernet settings:
  * MDIO not disabled, autonegotiation, 10/100Mbps, half/full duplex
  */
-#define CFG_ETH_MDDIS_VALUE	0
-#define CFG_ETH_CFG1_VALUE	1
-#define CFG_ETH_CFG2_VALUE	1
-#define CFG_ETH_CFG3_VALUE	1
+#define CONFIG_SYS_ETH_MDDIS_VALUE	0
+#define CONFIG_SYS_ETH_CFG1_VALUE	1
+#define CONFIG_SYS_ETH_CFG2_VALUE	1
+#define CONFIG_SYS_ETH_CFG3_VALUE	1
 
 /* PUMA configuration */
-#define CFG_PC_PUMA_PROG	0x0200		/* PC  6        */
-#define CFG_PC_PUMA_DONE	0x0008		/* PC 12	*/
-#define CFG_PC_PUMA_INIT	0x0004		/* PC 13	*/
+#define CONFIG_SYS_PC_PUMA_PROG	0x0200		/* PC  6        */
+#define CONFIG_SYS_PC_PUMA_DONE	0x0008		/* PC 12	*/
+#define CONFIG_SYS_PC_PUMA_INIT	0x0004		/* PC 13	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -169,52 +169,52 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR		0xF0000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Address accessed to reset the board - must not be mapped/assigned
  */
-#define	CFG_RESET_ADDRESS	0xFEFFFFFF
+#define	CONFIG_SYS_RESET_ADDRESS	0xFEFFFFFF
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
 #if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #if 1
 /* Start port with environment in flash; switch to SPI EEPROM later */
@@ -235,15 +235,15 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control				11-9
@@ -252,10 +252,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 						  SYPCR_SWP)
 #endif
 
@@ -264,27 +264,27 @@
  *-----------------------------------------------------------------------
  * we must activate GPL5 in the SIUMCR for CAN
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -295,10 +295,10 @@
  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  */
 #ifdef	CCM_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_PLPRCR							\
+#define CONFIG_SYS_PLPRCR							\
 		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
 #else			/* up to 50 MHz we use a 1:1 clock */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 #endif	/* CCM_80MHz */
 
 /*-----------------------------------------------------------------------
@@ -309,12 +309,12 @@
  */
 #define SCCR_MASK	SCCR_EBDF11
 #ifdef	CCM_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_SCCR	(/* SCCR_TBS  | */ \
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS  | */ \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 #else			/* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -325,14 +325,14 @@
  * Interrupt Levels
  *-----------------------------------------------------------------------
  */
-#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
+#define CONFIG_SYS_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -347,20 +347,20 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
 				 OR_SCY_5_CLK | OR_EHTR)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2 and OR2 (SDRAM)
@@ -371,18 +371,18 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /*
  * BR3 and OR3 (CAN Controller)
  */
-#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 
 /*
@@ -409,8 +409,8 @@
 #define PUMA_CONF_BR_READ	((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 #define PUMA_CONF_OR_READ	(PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
 
-#define CFG_BR4_PRELIM		PUMA_CONF_BR_READ
-#define CFG_OR4_PRELIM		PUMA_CONF_OR_READ
+#define CONFIG_SYS_BR4_PRELIM		PUMA_CONF_BR_READ
+#define CONFIG_SYS_OR4_PRELIM		PUMA_CONF_OR_READ
 
 /*
  * BR5/OR5: PUMA: SMA Bus 8 Bit
@@ -420,8 +420,8 @@
 #define PUMA_SMA8_OR_AM		0xFFE00000	/* 2 MB */
 #define PUMA_SMA8_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)
 
-#define CFG_BR5_PRELIM		((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CFG_OR5_PRELIM		(PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
+#define CONFIG_SYS_BR5_PRELIM		((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR5_PRELIM		(PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
 
 /*
  * BR6/OR6: PUMA: SMA Bus 16 Bit
@@ -431,8 +431,8 @@
 #define PUMA_SMA16_OR_AM	0xFFE00000	/* 2 MB */
 #define PUMA_SMA16_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)
 
-#define CFG_BR6_PRELIM		((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CFG_OR6_PRELIM		(PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
+#define CONFIG_SYS_BR6_PRELIM		((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR6_PRELIM		(PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
 
 /*
  * BR7/OR7: PUMA: external Flash
@@ -442,8 +442,8 @@
 #define PUMA_FLASH_OR_AM	0xFE000000	/* 32 MB */
 #define PUMA_FLASH_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)
 
-#define CFG_BR7_PRELIM		((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CFG_OR7_PRELIM		(PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
+#define CONFIG_SYS_BR7_PRELIM		((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR7_PRELIM		(PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
 
 
 /*
@@ -451,26 +451,26 @@
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
index 7c5efc2..40fef88 100644
--- a/include/configs/CMS700.h
+++ b/include/configs/CMS700.h
@@ -50,8 +50,9 @@
 
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_NET_MULTI	1
 #undef  CONFIG_HAS_ETH1
 
@@ -99,74 +100,72 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
 #define	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*-----------------------------------------------------------------------
  * RTC stuff
  *-----------------------------------------------------------------------
  */
 #define CONFIG_RTC_DS1337
-#define CFG_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
 
 /*-----------------------------------------------------------------------
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
-#define NAND_MAX_CHIPS          1
-#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
 #define NAND_BIG_DELAY_US	25
 
-#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
-#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
-#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
-#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
+#define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
-#define CFG_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
-#define CFG_NAND_QUIET          1
+#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
+#define CONFIG_SYS_NAND_QUIET          1
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -183,66 +182,66 @@
 
 #undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
 #endif
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-
-#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CFG_RAMBOOT		1
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CONFIG_SYS_RAMBOOT		1
 #else
-# undef CFG_RAMBOOT
+# undef CONFIG_SYS_RAMBOOT
 #endif
 
 /*-----------------------------------------------------------------------
@@ -257,67 +256,66 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
-#define CFG_EEPROM_WREN         1
+#define CONFIG_SYS_EEPROM_WREN         1
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  */
-#define CFG_PLD_BASE            0xf0000000
-#define CFG_NAND_BASE	        0xF4000000  /* NAND FLASH Base Address		*/
+#define CONFIG_SYS_PLD_BASE            0xf0000000
+#define CONFIG_SYS_NAND_BASE	        0xF4000000  /* NAND FLASH Base Address		*/
 
 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
-#define CFG_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
-#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
+#define CONFIG_SYS_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
+#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
-#define CFG_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
-#define CFG_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
-#define CFG_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
 
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup (PPC405EP specific)
@@ -335,16 +333,16 @@
 /* GPIO Output:		OSR=00, ISR=00, TSR=00, TCR=1 */
 /* Alt. Funtion Input:	OSR=00, ISR=01, TSR=00, TCR=0 */
 /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
-#define CFG_GPIO0_OSRH		0x40000500  /*	0 ... 15 */
-#define CFG_GPIO0_OSRL		0x00000110  /* 16 ... 31 */
-#define CFG_GPIO0_ISR1H		0x00000000  /*	0 ... 15 */
-#define CFG_GPIO0_ISR1L		0x14000045  /* 16 ... 31 */
-#define CFG_GPIO0_TSRH		0x00000000  /*	0 ... 15 */
-#define CFG_GPIO0_TSRL		0x00000000  /* 16 ... 31 */
-#define CFG_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */
-
-#define CFG_EEPROM_WP		(0x80000000 >> 8)    /* GPIO8 */
-#define CFG_PLD_RESET		(0x80000000 >> 12)   /* GPIO12 */
+#define CONFIG_SYS_GPIO0_OSRH		0x40000500  /*	0 ... 15 */
+#define CONFIG_SYS_GPIO0_OSRL		0x00000110  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_ISR1H		0x00000000  /*	0 ... 15 */
+#define CONFIG_SYS_GPIO0_ISR1L		0x14000045  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000  /*	0 ... 15 */
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */
+
+#define CONFIG_SYS_EEPROM_WP		(0x80000000 >> 8)    /* GPIO8 */
+#define CONFIG_SYS_PLD_RESET		(0x80000000 >> 12)   /* GPIO12 */
 
 /*
  * Internal Definitions
diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h
index a338af0..91d262a 100644
--- a/include/configs/CPC45.h
+++ b/include/configs/CPC45.h
@@ -48,7 +48,7 @@
 
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		9600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
 
@@ -89,60 +89,60 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 
 #if 1
-#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
 #endif
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 /* Print Buffer Size
  */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
 
-#define CFG_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
 
 #if defined(CONFIG_BOOT_ROM)
-#define CFG_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
 #else
-#define CFG_FLASH_BASE		0xFF800000
+#define CONFIG_SYS_FLASH_BASE		0xFF800000
 #endif
 
-#define CFG_RESET_ADDRESS	0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
 
-#define CFG_EUMB_ADDR		0xFCE00000
+#define CONFIG_SYS_EUMB_ADDR		0xFCE00000
 
-#define CFG_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
-#define CFG_MEMTEST_START	0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START	0x00004000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM		*/
 
 /* Maximum amount of RAM.
  */
-#define CFG_MAX_RAM_SIZE	0x10000000
+#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000
 
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#undef CFG_RAMBOOT
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#undef CONFIG_SYS_RAMBOOT
 #else
-#define CFG_RAMBOOT
+#define CONFIG_SYS_RAMBOOT
 #endif
 
 
@@ -152,48 +152,48 @@
 
 /* Size in bytes reserved for initial data
  */
-#define CFG_GBL_DATA_SIZE	128
+#define CONFIG_SYS_GBL_DATA_SIZE	128
 
-#define CFG_INIT_RAM_ADDR	0x40000000
-#define CFG_INIT_RAM_END	0x1000
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
 
-#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_REG_SIZE	1
 
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
-#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4600)
-#define DUART_DCR		(CFG_EUMB_ADDR + 0x4511)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_EUMB_ADDR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4600)
+#define DUART_DCR		(CONFIG_SYS_EUMB_ADDR + 0x4511)
 
 /*
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
 
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * RTC configuration
  */
 #define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR	0x51
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51
 
 /*
  * EEPROM configuration
  */
-#define CFG_I2C_EEPROM_ADDR		0x58
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
 
 /*
  * Low Level Configuration Settings
@@ -203,48 +203,48 @@
  */
 
 #define CONFIG_SYS_CLK_FREQ	33000000
-#define CFG_HZ			1000
+#define CONFIG_SYS_HZ			1000
 
 
 /* Bit-field values for MCCR1.
  */
-#define CFG_ROMNAL		0
-#define CFG_ROMFAL		8
-
-#define CFG_BANK0_ROW		0	/* SDRAM bank 7-0 row address */
-#define CFG_BANK1_ROW		0
-#define CFG_BANK2_ROW		0
-#define CFG_BANK3_ROW		0
-#define CFG_BANK4_ROW		0
-#define CFG_BANK5_ROW		0
-#define CFG_BANK6_ROW		0
-#define CFG_BANK7_ROW		0
+#define CONFIG_SYS_ROMNAL		0
+#define CONFIG_SYS_ROMFAL		8
+
+#define CONFIG_SYS_BANK0_ROW		0	/* SDRAM bank 7-0 row address */
+#define CONFIG_SYS_BANK1_ROW		0
+#define CONFIG_SYS_BANK2_ROW		0
+#define CONFIG_SYS_BANK3_ROW		0
+#define CONFIG_SYS_BANK4_ROW		0
+#define CONFIG_SYS_BANK5_ROW		0
+#define CONFIG_SYS_BANK6_ROW		0
+#define CONFIG_SYS_BANK7_ROW		0
 
 /* Bit-field values for MCCR2.
  */
 
-#define CFG_REFINT		0x2ec
+#define CONFIG_SYS_REFINT		0x2ec
 
 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
  */
-#define CFG_BSTOPRE		160
+#define CONFIG_SYS_BSTOPRE		160
 
 /* Bit-field values for MCCR3.
  */
-#define CFG_REFREC		2	/* Refresh to activate interval		*/
-#define CFG_RDLAT		0	/* Data latancy from read command	*/
+#define CONFIG_SYS_REFREC		2	/* Refresh to activate interval		*/
+#define CONFIG_SYS_RDLAT		0	/* Data latancy from read command	*/
 
 /* Bit-field values for MCCR4.
  */
-#define CFG_PRETOACT		2	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
-#define CFG_SDMODE_CAS_LAT	2	/* SDMODE CAS latancy			*/
-#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
-#define CFG_SDMODE_BURSTLEN	2	/* SDMODE Burst length			*/
-#define CFG_ACTORW		2
-#define CFG_REGISTERD_TYPE_BUFFER 1
-#define CFG_EXTROM		0
-#define CFG_REGDIMM		0
+#define CONFIG_SYS_PRETOACT		2	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	2	/* SDMODE CAS latancy			*/
+#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* SDMODE Burst length			*/
+#define CONFIG_SYS_ACTORW		2
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
+#define CONFIG_SYS_EXTROM		0
+#define CONFIG_SYS_REGDIMM		0
 
 /* Memory bank settings.
  * Only bits 20-29 are actually used from these vales to set the
@@ -253,79 +253,79 @@
  * address. Refer to the MPC8240 book.
  */
 
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x3ff00000
-#define CFG_BANK1_END		0x3fffffff
-#define CFG_BANK1_ENABLE	0
-#define CFG_BANK2_START		0x3ff00000
-#define CFG_BANK2_END		0x3fffffff
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x3ff00000
-#define CFG_BANK3_END		0x3fffffff
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x3ff00000
-#define CFG_BANK4_END		0x3fffffff
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x3ff00000
-#define CFG_BANK5_END		0x3fffffff
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x3ff00000
-#define CFG_BANK6_END		0x3fffffff
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x3ff00000
-#define CFG_BANK7_END		0x3fffffff
-#define CFG_BANK7_ENABLE	0
-
-#define CFG_ODCR		0xff
-#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x3ff00000
+#define CONFIG_SYS_BANK1_END		0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE	0
+#define CONFIG_SYS_BANK2_START		0x3ff00000
+#define CONFIG_SYS_BANK2_END		0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x3ff00000
+#define CONFIG_SYS_BANK3_END		0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x3ff00000
+#define CONFIG_SYS_BANK4_END		0x3fffffff
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x3ff00000
+#define CONFIG_SYS_BANK5_END		0x3fffffff
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x3ff00000
+#define CONFIG_SYS_BANK6_END		0x3fffffff
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x3ff00000
+#define CONFIG_SYS_BANK7_END		0x3fffffff
+#define CONFIG_SYS_BANK7_ENABLE	0
+
+#define CONFIG_SYS_ODCR		0xff
+#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
 					/* currently accessed page in memory	*/
 					/* see 8240 book for details		*/
 
-#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 
-#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
-#define CFG_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
 
-#define CFG_DBAT0L  CFG_IBAT0L
-#define CFG_DBAT0U  CFG_IBAT0U
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-#define CFG_DBAT2L  CFG_IBAT2L
-#define CFG_DBAT2U  CFG_IBAT2U
-#define CFG_DBAT3L  CFG_IBAT3L
-#define CFG_DBAT3U  CFG_IBAT3U
+#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT	39	/* Max number of sectors in one bank	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	39	/* Max number of sectors in one bank	*/
 #define INTEL_ID_28F160F3T	0x88F388F3	/*  16M = 1M x 16 top boot sector	*/
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 	/* Warining: environment is not EMBEDDED in the ppcboot code.
 	 * It's stored in flash separately.
 	 */
 #define CONFIG_ENV_IS_IN_FLASH	    1
 
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x7F8000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x7F8000)
 #define CONFIG_ENV_SIZE		0x4000	/* Size of the Environment		*/
 #define CONFIG_ENV_OFFSET		0	/* starting right at the beginning	*/
 #define CONFIG_ENV_SECT_SIZE	0x8000 /* Size of the Environment Sector	*/
@@ -333,9 +333,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SIZE	32
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /*
@@ -472,7 +472,7 @@
 #define CONFIG_NET_MULTI		/* Multi ethernet cards support		*/
 
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
+#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
 
 #define PCI_ENET0_IOADDR	0x82000000
 #define PCI_ENET0_MEMADDR	0x82000000
@@ -486,8 +486,8 @@
 
 #define CONFIG_I82365
 
-#define CFG_PCMCIA_MEM_ADDR	PCMCIA_MEM_BASE
-#define CFG_PCMCIA_MEM_SIZE	0x1000
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	PCMCIA_MEM_BASE
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	0x1000
 
 #define CONFIG_PCMCIA_SLOT_A
 
@@ -502,20 +502,20 @@
 #undef	CONFIG_IDE_RESET		/* reset for IDE not supported	*/
 #define	CONFIG_IDE_LED			/* LED   for IDE is  supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
-#define CFG_ATA_DATA_OFFSET	CFG_PCMCIA_MEM_SIZE
+#define CONFIG_SYS_ATA_DATA_OFFSET	CONFIG_SYS_PCMCIA_MEM_SIZE
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x400)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x400)
 
 #define CONFIG_DOS_PARTITION
 
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
index bd627e1..5c88c47 100644
--- a/include/configs/CPCI2DP.h
+++ b/include/configs/CPCI2DP.h
@@ -49,7 +49,7 @@
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
@@ -85,46 +85,45 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
 #define CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_LOOPW            1       /* enable loopw command         */
 
@@ -132,7 +131,7 @@
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -153,52 +152,52 @@
 
 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x040b  /* PCI Device ID: CPCI-2DP      */
-#define CFG_PCI_CLASSCODE       0x0280	/* PCI Class Code: Network/Other*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x040b  /* PCI Device ID: CPCI-2DP      */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0280	/* PCI Class Code: Network/Other*/
 
-#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
-#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA	0xef000000	/* point to internal regs + PB0/1 */
-#define CFG_PCI_PTM2MS  0xff000001      /* 16MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA	0xef000000	/* point to internal regs + PB0/1 */
+#define CONFIG_SYS_PCI_PTM2MS  0xff000001      /* 16MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
 #define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
@@ -208,20 +207,19 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
-#define CFG_EEPROM_WREN         1
+#define CONFIG_SYS_EEPROM_WREN         1
 
 /*
  * Init Memory Controller:
@@ -236,35 +234,35 @@
  */
 
 /* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 2 (PB0) initialization					*/
-#define CFG_EBC_PB2AP		0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
-#define CFG_EBC_PB2CR		0xEF018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2AP		0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xEF018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 3 (PB1) initialization				*/
-#define CFG_EBC_PB3AP		0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
-#define CFG_EBC_PB3CR		0xEF118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB3AP		0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xEF118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
-#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
 
-#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE       128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_SIZE       128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * GPIO definitions
  */
-#define CFG_EEPROM_WP		(0x80000000 >> 13)   /* GPIO13 */
-#define CFG_SELF_RST		(0x80000000 >> 14)   /* GPIO14 */
-#define CFG_PB_LED		(0x80000000 >> 16)   /* GPIO16 */
-#define CFG_INTA_FAKE		(0x80000000 >> 23)   /* GPIO23 */
+#define CONFIG_SYS_EEPROM_WP		(0x80000000 >> 13)   /* GPIO13 */
+#define CONFIG_SYS_SELF_RST		(0x80000000 >> 14)   /* GPIO14 */
+#define CONFIG_SYS_PB_LED		(0x80000000 >> 16)   /* GPIO16 */
+#define CONFIG_SYS_INTA_FAKE		(0x80000000 >> 23)   /* GPIO23 */
 
 /*
  * Internal Definitions
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index 8523134..f032a8d 100644
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -50,8 +50,9 @@
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
@@ -99,43 +100,42 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_LOOPW            1       /* enable loopw command         */
 
@@ -160,16 +160,16 @@
 
 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
-#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
@@ -179,58 +179,58 @@
 #undef	CONFIG_IDE_LED			/* no led for ide supported	*/
 #undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
 
-#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR	0xF0100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFD0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CONFIG_SYS_VXWORKS_MAC_PTR     (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
 
 #if 1 /* Use NVRAM for environment variables */
 /*-----------------------------------------------------------------------
@@ -239,7 +239,7 @@
 #define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
 #define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
 #define CONFIG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
 
 #else /* Use EEPROM for environment variables */
 
@@ -253,18 +253,17 @@
  * I2C EEPROM (CAT24WC08) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 /*
  * Init Memory Controller:
@@ -280,54 +279,54 @@
  */
 
 /* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (Flash Bank 1) initialization					*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization			*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 3 (CompactFlash IDE) initialization				*/
-#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 4 (NVRAM) initialization						*/
-#define CFG_EBC_PB4AP		0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1	*/
-#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB4AP		0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1	*/
+#define CONFIG_SYS_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 5 (Quart) initialization						*/
-#define CFG_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
-#define CFG_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CONFIG_SYS_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00400000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00800000  /* FPGA done pin (ppc input)     */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00400000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00800000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 #if 1 /* test-only */
-#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
 
-#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
 #else
-#define CFG_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
+#define CONFIG_SYS_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
 #endif
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 
 /*
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index 228821a..2677cfb 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -52,8 +52,9 @@
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
@@ -106,45 +107,44 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_CMDLINE_EDITING		/* add command line history	*/
 
@@ -154,7 +154,7 @@
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -175,16 +175,16 @@
 
 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
-#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
@@ -194,33 +194,35 @@
 #undef	CONFIG_IDE_LED			/* no led for ide supported	*/
 #define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
 
-#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR	0xF0100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+#define CONFIG_PRAM		0	/* use pram variable to overwrite */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 #define CONFIG_OF_LIBFDT
 #define CONFIG_OF_BOARD_SETUP
@@ -228,24 +230,24 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* Use NVRAM for environment variables */
 /*-----------------------------------------------------------------------
@@ -254,7 +256,7 @@
 #define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
 #define CONFIG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
 #define CONFIG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))	/* Env	*/
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))	/* Env	*/
 
 #else /* Use EEPROM for environment variables */
 
@@ -264,26 +266,25 @@
 				   /* total size of a CAT24WC16 is 2048 bytes */
 #endif
 
-#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CONFIG_SYS_VXWORKS_MAC_PTR     (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 /*
  * Init Memory Controller:
@@ -299,88 +300,88 @@
  */
 
 /* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (Flash Bank 1) initialization					*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 2 (CAN0, 1) initialization					*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-#define CFG_LED_ADDR		0xF0000380
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_LED_ADDR		0xF0000380
 
 /* Memory Bank 3 (CompactFlash IDE) initialization				*/
-#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 4 (NVRAM/RTC) initialization					*/
-/*#define CFG_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
-#define CFG_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
-#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+/*#define CONFIG_SYS_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
+#define CONFIG_SYS_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
+#define CONFIG_SYS_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 5 (optional Quart) initialization				*/
-#define CFG_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
-#define CFG_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CONFIG_SYS_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 6 (FPGA internal) initialization					*/
-#define CFG_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-#define CFG_FPGA_BASE_ADDR	0xF0400000
+#define CONFIG_SYS_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_FPGA_BASE_ADDR	0xF0400000
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
 /* FPGA internal regs */
-#define CFG_FPGA_MODE		0x00
-#define CFG_FPGA_STATUS		0x02
-#define CFG_FPGA_TS		0x04
-#define CFG_FPGA_TS_LOW		0x06
-#define CFG_FPGA_TS_CAP0	0x10
-#define CFG_FPGA_TS_CAP0_LOW	0x12
-#define CFG_FPGA_TS_CAP1	0x14
-#define CFG_FPGA_TS_CAP1_LOW	0x16
-#define CFG_FPGA_TS_CAP2	0x18
-#define CFG_FPGA_TS_CAP2_LOW	0x1a
-#define CFG_FPGA_TS_CAP3	0x1c
-#define CFG_FPGA_TS_CAP3_LOW	0x1e
+#define CONFIG_SYS_FPGA_MODE		0x00
+#define CONFIG_SYS_FPGA_STATUS		0x02
+#define CONFIG_SYS_FPGA_TS		0x04
+#define CONFIG_SYS_FPGA_TS_LOW		0x06
+#define CONFIG_SYS_FPGA_TS_CAP0	0x10
+#define CONFIG_SYS_FPGA_TS_CAP0_LOW	0x12
+#define CONFIG_SYS_FPGA_TS_CAP1	0x14
+#define CONFIG_SYS_FPGA_TS_CAP1_LOW	0x16
+#define CONFIG_SYS_FPGA_TS_CAP2	0x18
+#define CONFIG_SYS_FPGA_TS_CAP2_LOW	0x1a
+#define CONFIG_SYS_FPGA_TS_CAP3	0x1c
+#define CONFIG_SYS_FPGA_TS_CAP3_LOW	0x1e
 
 /* FPGA Mode Reg */
-#define CFG_FPGA_MODE_CF_RESET	    0x0001
-#define CFG_FPGA_MODE_DUART_RESET   0x0002
-#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
-#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
-#define CFG_FPGA_MODE_TS_CLEAR	    0x2000
+#define CONFIG_SYS_FPGA_MODE_CF_RESET	    0x0001
+#define CONFIG_SYS_FPGA_MODE_DUART_RESET   0x0002
+#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CONFIG_SYS_FPGA_MODE_TS_CLEAR	    0x2000
 
 /* FPGA Status Reg */
-#define CFG_FPGA_STATUS_DIP0	0x0001
-#define CFG_FPGA_STATUS_DIP1	0x0002
-#define CFG_FPGA_STATUS_DIP2	0x0004
-#define CFG_FPGA_STATUS_FLASH	0x0008
-#define CFG_FPGA_STATUS_TS_IRQ	0x1000
+#define CONFIG_SYS_FPGA_STATUS_DIP0	0x0001
+#define CONFIG_SYS_FPGA_STATUS_DIP1	0x0002
+#define CONFIG_SYS_FPGA_STATUS_DIP2	0x0004
+#define CONFIG_SYS_FPGA_STATUS_FLASH	0x0008
+#define CONFIG_SYS_FPGA_STATUS_TS_IRQ	0x1000
 
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
-#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
 
-#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 
 /*
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index 065b855..aae0d73 100644
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -52,8 +52,9 @@
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 
 #undef	CONFIG_LOADS_ECHO		/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
@@ -91,6 +92,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
 #define CONFIG_CMD_EEPROM
 
 
@@ -106,43 +108,42 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_CMDLINE_EDITING		/* add command line history	*/
 
@@ -150,7 +151,7 @@
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -171,16 +172,16 @@
 
 #define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
-#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
-#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A	*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
@@ -190,33 +191,35 @@
 #undef	CONFIG_IDE_LED			/* no led for ide supported	*/
 #define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
 
-#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR	0xF0100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+#define CONFIG_PRAM		0	/* use pram variable to overwrite */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 #define CONFIG_OF_LIBFDT
 #define CONFIG_OF_BOARD_SETUP
@@ -224,42 +227,41 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC32) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC32		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC32		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
-#define CFG_I2C_MULTI_EEPROMS   1       /* more than one eeprom used!   */
-#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x01
+#define CONFIG_SYS_I2C_MULTI_EEPROMS   1       /* more than one eeprom used!   */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
 					/* 32 byte page write mode using*/
 					/* last 5 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 /* Use EEPROM for environment variables */
 
@@ -268,9 +270,9 @@
 #define CONFIG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC32 is 4096 bytes */
 
-#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CONFIG_SYS_VXWORKS_MAC_PTR     (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
 
 /*
  * Init Memory Controller:
@@ -286,92 +288,92 @@
  */
 
 /* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (Flash Bank 1) initialization					*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 2 (CAN0, 1) initialization					*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-#define CFG_LED_ADDR		0xF0000380
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_LED_ADDR		0xF0000380
 
 /* Memory Bank 3 (CompactFlash IDE) initialization				*/
-#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 4 (NVRAM/RTC) initialization					*/
-/*#define CFG_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
-#define CFG_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
-#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+/*#define CONFIG_SYS_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
+#define CONFIG_SYS_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
+#define CONFIG_SYS_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 5 (optional Quart) initialization				*/
-#define CFG_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
-#define CFG_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CONFIG_SYS_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 6 (FPGA internal) initialization					*/
-#define CFG_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-#define CFG_FPGA_BASE_ADDR	0xF0400000
+#define CONFIG_SYS_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_FPGA_BASE_ADDR	0xF0400000
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
 /* FPGA internal regs */
-#define CFG_FPGA_MODE		0x00
-#define CFG_FPGA_STATUS		0x02
-#define CFG_FPGA_TS		0x04
-#define CFG_FPGA_TS_LOW		0x06
-#define CFG_FPGA_TS_CAP0	0x10
-#define CFG_FPGA_TS_CAP0_LOW	0x12
-#define CFG_FPGA_TS_CAP1	0x14
-#define CFG_FPGA_TS_CAP1_LOW	0x16
-#define CFG_FPGA_TS_CAP2	0x18
-#define CFG_FPGA_TS_CAP2_LOW	0x1a
-#define CFG_FPGA_TS_CAP3	0x1c
-#define CFG_FPGA_TS_CAP3_LOW	0x1e
+#define CONFIG_SYS_FPGA_MODE		0x00
+#define CONFIG_SYS_FPGA_STATUS		0x02
+#define CONFIG_SYS_FPGA_TS		0x04
+#define CONFIG_SYS_FPGA_TS_LOW		0x06
+#define CONFIG_SYS_FPGA_TS_CAP0	0x10
+#define CONFIG_SYS_FPGA_TS_CAP0_LOW	0x12
+#define CONFIG_SYS_FPGA_TS_CAP1	0x14
+#define CONFIG_SYS_FPGA_TS_CAP1_LOW	0x16
+#define CONFIG_SYS_FPGA_TS_CAP2	0x18
+#define CONFIG_SYS_FPGA_TS_CAP2_LOW	0x1a
+#define CONFIG_SYS_FPGA_TS_CAP3	0x1c
+#define CONFIG_SYS_FPGA_TS_CAP3_LOW	0x1e
 
 /* FPGA Mode Reg */
-#define CFG_FPGA_MODE_CF_RESET	    0x0001
-#define CFG_FPGA_MODE_DUART_RESET   0x0002
-#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
-#define CFG_FPGA_MODE_1WIRE_DIR     0x0100     /* dir=1 -> output */
-#define CFG_FPGA_MODE_SIM_OK_DIR    0x0200
-#define CFG_FPGA_MODE_TESTRIG_FAIL_DIR 0x0400
-#define CFG_FPGA_MODE_1WIRE         0x1000
-#define CFG_FPGA_MODE_SIM_OK        0x2000     /* wired-or net from all devices */
-#define CFG_FPGA_MODE_TESTRIG_FAIL  0x4000
+#define CONFIG_SYS_FPGA_MODE_CF_RESET	    0x0001
+#define CONFIG_SYS_FPGA_MODE_DUART_RESET   0x0002
+#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
+#define CONFIG_SYS_FPGA_MODE_1WIRE_DIR     0x0100     /* dir=1 -> output */
+#define CONFIG_SYS_FPGA_MODE_SIM_OK_DIR    0x0200
+#define CONFIG_SYS_FPGA_MODE_TESTRIG_FAIL_DIR 0x0400
+#define CONFIG_SYS_FPGA_MODE_1WIRE         0x1000
+#define CONFIG_SYS_FPGA_MODE_SIM_OK        0x2000     /* wired-or net from all devices */
+#define CONFIG_SYS_FPGA_MODE_TESTRIG_FAIL  0x4000
 
 /* FPGA Status Reg */
-#define CFG_FPGA_STATUS_DIP0    0x0001
-#define CFG_FPGA_STATUS_DIP1    0x0002
-#define CFG_FPGA_STATUS_DIP2    0x0004
-#define CFG_FPGA_STATUS_FLASH   0x0008
-#define CFG_FPGA_STATUS_1WIRE   0x1000
-#define CFG_FPGA_STATUS_SIM_OK  0x2000
+#define CONFIG_SYS_FPGA_STATUS_DIP0    0x0001
+#define CONFIG_SYS_FPGA_STATUS_DIP1    0x0002
+#define CONFIG_SYS_FPGA_STATUS_DIP2    0x0004
+#define CONFIG_SYS_FPGA_STATUS_FLASH   0x0008
+#define CONFIG_SYS_FPGA_STATUS_1WIRE   0x1000
+#define CONFIG_SYS_FPGA_STATUS_SIM_OK  0x2000
 
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S30 */
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S30 */
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
-#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
 
-#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 
 /*
diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
index ffbe036..2333208 100644
--- a/include/configs/CPCI405DT.h
+++ b/include/configs/CPCI405DT.h
@@ -51,8 +51,9 @@
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
@@ -107,45 +108,44 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_LOOPW            1       /* enable loopw command         */
 
@@ -161,7 +161,7 @@
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -182,16 +182,16 @@
 
 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
-#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
@@ -201,54 +201,54 @@
 #undef	CONFIG_IDE_LED			/* no led for ide supported	*/
 #define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
 
-#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR	0xF0100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* Use NVRAM for environment variables */
 /*-----------------------------------------------------------------------
@@ -257,7 +257,7 @@
 #define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
 #define CONFIG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
 #define CONFIG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))	/* Env	*/
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))	/* Env	*/
 
 #else /* Use EEPROM for environment variables */
 
@@ -267,26 +267,25 @@
 				   /* total size of a CAT24WC16 is 2048 bytes */
 #endif
 
-#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CONFIG_SYS_VXWORKS_MAC_PTR     (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 /*
  * Init Memory Controller:
@@ -302,88 +301,88 @@
  */
 
 /* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (Flash Bank 1) initialization					*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 2 (CAN0, 1) initialization					*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-#define CFG_LED_ADDR		0xF0000380
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_LED_ADDR		0xF0000380
 
 /* Memory Bank 3 (CompactFlash IDE) initialization				*/
-#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 4 (NVRAM/RTC) initialization					*/
-/*#define CFG_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
-#define CFG_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
-#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+/*#define CONFIG_SYS_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
+#define CONFIG_SYS_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
+#define CONFIG_SYS_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 5 (optional Quart) initialization				*/
-#define CFG_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
-#define CFG_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CONFIG_SYS_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 6 (FPGA internal) initialization					*/
-#define CFG_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-#define CFG_FPGA_BASE_ADDR	0xF0400000
+#define CONFIG_SYS_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_FPGA_BASE_ADDR	0xF0400000
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
 /* FPGA internal regs */
-#define CFG_FPGA_MODE		0x00
-#define CFG_FPGA_STATUS		0x02
-#define CFG_FPGA_TS		0x04
-#define CFG_FPGA_TS_LOW		0x06
-#define CFG_FPGA_TS_CAP0	0x10
-#define CFG_FPGA_TS_CAP0_LOW	0x12
-#define CFG_FPGA_TS_CAP1	0x14
-#define CFG_FPGA_TS_CAP1_LOW	0x16
-#define CFG_FPGA_TS_CAP2	0x18
-#define CFG_FPGA_TS_CAP2_LOW	0x1a
-#define CFG_FPGA_TS_CAP3	0x1c
-#define CFG_FPGA_TS_CAP3_LOW	0x1e
+#define CONFIG_SYS_FPGA_MODE		0x00
+#define CONFIG_SYS_FPGA_STATUS		0x02
+#define CONFIG_SYS_FPGA_TS		0x04
+#define CONFIG_SYS_FPGA_TS_LOW		0x06
+#define CONFIG_SYS_FPGA_TS_CAP0	0x10
+#define CONFIG_SYS_FPGA_TS_CAP0_LOW	0x12
+#define CONFIG_SYS_FPGA_TS_CAP1	0x14
+#define CONFIG_SYS_FPGA_TS_CAP1_LOW	0x16
+#define CONFIG_SYS_FPGA_TS_CAP2	0x18
+#define CONFIG_SYS_FPGA_TS_CAP2_LOW	0x1a
+#define CONFIG_SYS_FPGA_TS_CAP3	0x1c
+#define CONFIG_SYS_FPGA_TS_CAP3_LOW	0x1e
 
 /* FPGA Mode Reg */
-#define CFG_FPGA_MODE_CF_RESET	    0x0001
-#define CFG_FPGA_MODE_DUART_RESET   0x0002
-#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
-#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
-#define CFG_FPGA_MODE_TS_CLEAR	    0x2000
+#define CONFIG_SYS_FPGA_MODE_CF_RESET	    0x0001
+#define CONFIG_SYS_FPGA_MODE_DUART_RESET   0x0002
+#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CONFIG_SYS_FPGA_MODE_TS_CLEAR	    0x2000
 
 /* FPGA Status Reg */
-#define CFG_FPGA_STATUS_DIP0	0x0001
-#define CFG_FPGA_STATUS_DIP1	0x0002
-#define CFG_FPGA_STATUS_DIP2	0x0004
-#define CFG_FPGA_STATUS_FLASH	0x0008
-#define CFG_FPGA_STATUS_TS_IRQ	0x1000
+#define CONFIG_SYS_FPGA_STATUS_DIP0	0x0001
+#define CONFIG_SYS_FPGA_STATUS_DIP1	0x0002
+#define CONFIG_SYS_FPGA_STATUS_DIP2	0x0004
+#define CONFIG_SYS_FPGA_STATUS_FLASH	0x0008
+#define CONFIG_SYS_FPGA_STATUS_TS_IRQ	0x1000
 
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
-#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
 
-#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Internal Definitions
diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h
index 46f80d1..8494faa 100644
--- a/include/configs/CPCI750.h
+++ b/include/configs/CPCI750.h
@@ -68,18 +68,18 @@
 #define CONFIG_BOARD_PRE_INIT
 #define CONFIG_BOARD_EARLY_INIT_F 1
 
-#define CFG_BOARD_NAME		"CPCI750"
+#define CONFIG_SYS_BOARD_NAME		"CPCI750"
 #define CONFIG_IDENT_STRING	"Marvell 64360 + IBM750FX"
 
-/*#define CFG_HUSH_PARSER*/
-#define CFG_HUSH_PARSER
+/*#define CONFIG_SYS_HUSH_PARSER*/
+#define CONFIG_SYS_HUSH_PARSER
 
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 #define CONFIG_AUTO_COMPLETE 1
 
 /* Define which ETH port will be used for connecting the network */
-#define CFG_ETH_PORT		ETH_0
+#define CONFIG_SYS_ETH_PORT		ETH_0
 
 /*
  * The following defines let you select what serial you want to use
@@ -87,7 +87,7 @@
  *
  * what to do:
  * to use the DUART, undef CONFIG_MPSC.	 If you have hacked a serial
- * cable onto the second DUART channel, change the CFG_DUART port from 1
+ * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
  * to 0 below.
  *
  * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
@@ -130,7 +130,7 @@
 
 
 #define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
-#define CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 #undef	CONFIG_ALTIVEC			/* undef to disable		*/
@@ -175,75 +175,75 @@
 #define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_I8042_KBD
-#define CFG_ISA_IO 0
+#define CONFIG_SYS_ISA_IO 0
 #endif
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_I2C_EEPROM_ADDR_LEN 2
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_SPEED	80000		/* I2C speed default */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_SPEED	80000		/* I2C speed default */
 
-#define CFG_GT_DUAL_CPU			/* also for JTAG even with one cpu */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_GT_DUAL_CPU			/* also for JTAG even with one cpu */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-/*#define CFG_MEMTEST_START	0x00400000*/	/* memtest works on	*/
-/*#define CFG_MEMTEST_END		0x00C00000*/	/* 4 ... 12 MB in DRAM	*/
-/*#define CFG_MEMTEST_END		0x07c00000*/	/* 4 ... 124 MB in DRAM */
+/*#define CONFIG_SYS_MEMTEST_START	0x00400000*/	/* memtest works on	*/
+/*#define CONFIG_SYS_MEMTEST_END		0x00C00000*/	/* 4 ... 12 MB in DRAM	*/
+/*#define CONFIG_SYS_MEMTEST_END		0x07c00000*/	/* 4 ... 124 MB in DRAM */
 
 /*
-#define CFG_DRAM_TEST
+#define CONFIG_SYS_DRAM_TEST
  * DRAM tests
- *   CFG_DRAM_TEST - enables the following tests.
+ *   CONFIG_SYS_DRAM_TEST - enables the following tests.
  *
- *   CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
+ *   CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
  *			  Environment variable 'test_dram_data' must be
  *			  set to 'y'.
- *   CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
+ *   CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
  *			  addressable. Environment variable
  *			  'test_dram_address' must be set to 'y'.
- *   CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
+ *   CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
  *			  This test takes about 6 minutes to test 64 MB.
  *			  Environment variable 'test_dram_walk' must be
  *			  set to 'y'.
  */
-#define CFG_DRAM_TEST
-#if defined(CFG_DRAM_TEST)
-#define CFG_MEMTEST_START		0x00400000	/* memtest works on	*/
-/*#define CFG_MEMTEST_END		0x00C00000*/	/* 4 ... 12 MB in DRAM	*/
-#define CFG_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
-#define CFG_DRAM_TEST_DATA
-#define CFG_DRAM_TEST_ADDRESS
-#define CFG_DRAM_TEST_WALK
-#endif /* CFG_DRAM_TEST */
+#define CONFIG_SYS_DRAM_TEST
+#if defined(CONFIG_SYS_DRAM_TEST)
+#define CONFIG_SYS_MEMTEST_START		0x00400000	/* memtest works on	*/
+/*#define CONFIG_SYS_MEMTEST_END		0x00C00000*/	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
+#define CONFIG_SYS_DRAM_TEST_DATA
+#define CONFIG_SYS_DRAM_TEST_ADDRESS
+#define CONFIG_SYS_DRAM_TEST_WALK
+#endif /* CONFIG_SYS_DRAM_TEST */
 
 #define CONFIG_DISPLAY_MEMMAP		/* at the end of the bootprocess show the memory map */
-#undef CFG_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
+#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
 
-#define CFG_LOAD_ADDR		0x00300000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x00300000	/* default load address */
 
-#define CFG_HZ			1000		/* decr freq: 1ms ticks */
-#define CFG_BUS_HZ		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
-#define CFG_BUS_CLK		CFG_BUS_HZ
+#define CONFIG_SYS_HZ			1000		/* decr freq: 1ms ticks */
+#define CONFIG_SYS_BUS_HZ		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
+#define CONFIG_SYS_BUS_CLK		CONFIG_SYS_BUS_HZ
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#define CFG_TCLK		133000000
+#define CONFIG_SYS_TCLK		133000000
 
-/*#define CFG_750FX_HID0		0x8000c084*/
-#define CFG_750FX_HID0		0x80008484
-#define CFG_750FX_HID1		0x54800000
-#define CFG_750FX_HID2		0x00000000
+/*#define CONFIG_SYS_750FX_HID0		0x8000c084*/
+#define CONFIG_SYS_750FX_HID0		0x80008484
+#define CONFIG_SYS_750FX_HID1		0x54800000
+#define CONFIG_SYS_750FX_HID2		0x00000000
 
 /*
  * Low Level Configuration Settings
@@ -256,63 +256,63 @@
  */
 
  /*
- * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
+ * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
  * To an unused memory region. The stack will remain in cache until RAM
  * is initialized
 */
-#undef	  CFG_INIT_RAM_LOCK
-/* #define CFG_INIT_RAM_ADDR	0x40000000*/ /* unused memory region */
-/* #define CFG_INIT_RAM_ADDR	0xfba00000*/ /* unused memory region */
-#define CFG_INIT_RAM_ADDR	0xf1080000 /* unused memory region */
-#define CFG_INIT_RAM_END	0x1000
-#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#undef	  CONFIG_SYS_INIT_RAM_LOCK
+/* #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000*/ /* unused memory region */
+/* #define CONFIG_SYS_INIT_RAM_ADDR	0xfba00000*/ /* unused memory region */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xf1080000 /* unused memory region */
+#define CONFIG_SYS_INIT_RAM_END	0x1000
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 #define RELOCATE_INTERNAL_RAM_ADDR
 #ifdef RELOCATE_INTERNAL_RAM_ADDR
-/*#define CFG_INTERNAL_RAM_ADDR 0xfba00000*/
-#define CFG_INTERNAL_RAM_ADDR	0xf1080000
+/*#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xfba00000*/
+#define CONFIG_SYS_INTERNAL_RAM_ADDR	0xf1080000
 #endif
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
 /* Dummies for BAT 4-7 */
-#define CFG_SDRAM1_BASE		0x10000000	/* each 256 MByte */
-#define CFG_SDRAM2_BASE		0x20000000
-#define CFG_SDRAM3_BASE		0x30000000
-#define CFG_SDRAM4_BASE		0x40000000
-#define CFG_RESET_ADDRESS	0xfff00100
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MONITOR_BASE	0xfff00000
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 256 kB for malloc */
+#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* each 256 MByte */
+#define CONFIG_SYS_SDRAM2_BASE		0x20000000
+#define CONFIG_SYS_SDRAM3_BASE		0x30000000
+#define CONFIG_SYS_SDRAM4_BASE		0x40000000
+#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	0xfff00000
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 256 kB for malloc */
 
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI		1	   /* Flash is CFI conformant		*/
-#define CFG_FLASH_PROTECTION	1	   /* use hardware protection		*/
-#define CFG_FLASH_USE_BUFFER_WRITE 1	   /* use buffered writes (20x faster)	*/
-#define CFG_FLASH_BASE		0xfc000000 /* start of flash banks		*/
-#define CFG_MAX_FLASH_BANKS	4	   /* max number of memory banks	*/
-#define CFG_FLASH_INCREMENT	0x01000000 /* size of  flash bank		*/
-#define CFG_MAX_FLASH_SECT	128	   /* max number of sectors on one chip */
-#define CFG_FLASH_BANKS_LIST  { CFG_FLASH_BASE,				   \
-				CFG_FLASH_BASE + 1*CFG_FLASH_INCREMENT,	   \
-				CFG_FLASH_BASE + 2*CFG_FLASH_INCREMENT,	   \
-				CFG_FLASH_BASE + 3*CFG_FLASH_INCREMENT }
-#define CFG_FLASH_EMPTY_INFO	1	   /* show if bank is empty		*/
+#define CONFIG_SYS_FLASH_CFI		1	   /* Flash is CFI conformant		*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	   /* use hardware protection		*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	   /* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_BASE		0xfc000000 /* start of flash banks		*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	4	   /* max number of memory banks	*/
+#define CONFIG_SYS_FLASH_INCREMENT	0x01000000 /* size of  flash bank		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	   /* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST  { CONFIG_SYS_FLASH_BASE,				   \
+				CONFIG_SYS_FLASH_BASE + 1*CONFIG_SYS_FLASH_INCREMENT,	   \
+				CONFIG_SYS_FLASH_BASE + 2*CONFIG_SYS_FLASH_INCREMENT,	   \
+				CONFIG_SYS_FLASH_BASE + 3*CONFIG_SYS_FLASH_INCREMENT }
+#define CONFIG_SYS_FLASH_EMPTY_INFO	1	   /* show if bank is empty		*/
 
 /* areas to map different things with the GT in physical space */
-#define CFG_DRAM_BANKS		4
+#define CONFIG_SYS_DRAM_BANKS		4
 
 /* What to put in the bats. */
-#define CFG_MISC_REGION_BASE	0xf0000000
+#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
 
 /* Peripheral Device section */
 
@@ -326,37 +326,37 @@
 /* Data flash on external device module		       */
 /* Boot flash on external device module		       */
 /*******************************************************/
-#define CFG_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
-#define	 CFG_CPCI750_RESET_ADDR 0x14000000				/* After power on Reset the CPCI750 is here */
+#define CONFIG_SYS_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
+#define	 CONFIG_SYS_CPCI750_RESET_ADDR 0x14000000				/* After power on Reset the CPCI750 is here */
 
 #undef	MARVEL_STANDARD_CFG
 #ifndef		MARVEL_STANDARD_CFG
 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-#define CFG_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
-/*#define CFG_DEV_BASE		0xfc000000*/				/* GT Devices CS start here */
-#define CFG_INT_SRAM_BASE	0xf1080000				/* GT offers 256k internal fast SRAM */
-
-#define CFG_BOOT_SPACE		0xff000000				/* BOOT_CS0 flash 0    */
-#define CFG_DEV0_SPACE		0xfc000000				/* DEV_CS0 flash 1     */
-#define CFG_DEV1_SPACE		0xfd000000				/* DEV_CS1 flash 2     */
-#define CFG_DEV2_SPACE		0xfe000000				/* DEV_CS2 flash 3     */
-#define CFG_DEV3_SPACE		0xf0000000				/* DEV_CS3 nvram/can   */
-
-#define CFG_BOOT_SIZE		_16M					/* cpci750 flash 0     */
-#define CFG_DEV0_SIZE		_16M					/* cpci750 flash 1     */
-#define CFG_DEV1_SIZE		_16M					/* cpci750 flash 2     */
-#define CFG_DEV2_SIZE		_16M					/* cpci750 flash 3     */
-#define CFG_DEV3_SIZE		_16M					/* cpci750 nvram/can   */
+#define CONFIG_SYS_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
+/*#define CONFIG_SYS_DEV_BASE		0xfc000000*/				/* GT Devices CS start here */
+#define CONFIG_SYS_INT_SRAM_BASE	0xf1080000				/* GT offers 256k internal fast SRAM */
+
+#define CONFIG_SYS_BOOT_SPACE		0xff000000				/* BOOT_CS0 flash 0    */
+#define CONFIG_SYS_DEV0_SPACE		0xfc000000				/* DEV_CS0 flash 1     */
+#define CONFIG_SYS_DEV1_SPACE		0xfd000000				/* DEV_CS1 flash 2     */
+#define CONFIG_SYS_DEV2_SPACE		0xfe000000				/* DEV_CS2 flash 3     */
+#define CONFIG_SYS_DEV3_SPACE		0xf0000000				/* DEV_CS3 nvram/can   */
+
+#define CONFIG_SYS_BOOT_SIZE		_16M					/* cpci750 flash 0     */
+#define CONFIG_SYS_DEV0_SIZE		_16M					/* cpci750 flash 1     */
+#define CONFIG_SYS_DEV1_SIZE		_16M					/* cpci750 flash 2     */
+#define CONFIG_SYS_DEV2_SIZE		_16M					/* cpci750 flash 3     */
+#define CONFIG_SYS_DEV3_SIZE		_16M					/* cpci750 nvram/can   */
 
 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
 #endif
 
 /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
-#define CFG_DEV0_PAR		0x8FDFFFFF				/* 16 bit flash */
-#define CFG_DEV1_PAR		0x8FDFFFFF				/* 16 bit flash */
-#define CFG_DEV2_PAR		0x8FDFFFFF				/* 16 bit flash */
-#define CFG_DEV3_PAR		0x8FCFFFFF				/* nvram/can	*/
-#define CFG_BOOT_PAR		0x8FDFFFFF				/* 16 bit flash */
+#define CONFIG_SYS_DEV0_PAR		0x8FDFFFFF				/* 16 bit flash */
+#define CONFIG_SYS_DEV1_PAR		0x8FDFFFFF				/* 16 bit flash */
+#define CONFIG_SYS_DEV2_PAR		0x8FDFFFFF				/* 16 bit flash */
+#define CONFIG_SYS_DEV3_PAR		0x8FCFFFFF				/* nvram/can	*/
+#define CONFIG_SYS_BOOT_PAR		0x8FDFFFFF				/* 16 bit flash */
 
 	/*   c	  4    a      8	    2	  4    1      c		*/
 	/* 33 22|2222|22 22|111 1|11 11|1 1  |	  |		*/
@@ -366,18 +366,18 @@
 
 
 /* MPP Control MV64360 Appendix P P. 632*/
-#define CFG_MPP_CONTROL_0	0x00002222	/*				     */
-#define CFG_MPP_CONTROL_1	0x11110000	/*				     */
-#define CFG_MPP_CONTROL_2	0x11111111	/*				     */
-#define CFG_MPP_CONTROL_3	0x00001111	/*				     */
-/* #define CFG_SERIAL_PORT_MUX	0x00000102*/	/*				     */
+#define CONFIG_SYS_MPP_CONTROL_0	0x00002222	/*				     */
+#define CONFIG_SYS_MPP_CONTROL_1	0x11110000	/*				     */
+#define CONFIG_SYS_MPP_CONTROL_2	0x11111111	/*				     */
+#define CONFIG_SYS_MPP_CONTROL_3	0x00001111	/*				     */
+/* #define CONFIG_SYS_SERIAL_PORT_MUX	0x00000102*/	/*				     */
 
 
-#define CFG_GPP_LEVEL_CONTROL	0xffffffff	/* 1111 1111 1111 1111 1111 1111 1111 1111*/
+#define CONFIG_SYS_GPP_LEVEL_CONTROL	0xffffffff	/* 1111 1111 1111 1111 1111 1111 1111 1111*/
 
 /* setup new config_value for MV64360 DDR-RAM To_do !! */
-/*# define CFG_SDRAM_CONFIG	0xd8e18200*/	/* 0x448 */
-/*# define CFG_SDRAM_CONFIG	0xd8e14400*/	/* 0x1400 */
+/*# define CONFIG_SYS_SDRAM_CONFIG	0xd8e18200*/	/* 0x448 */
+/*# define CONFIG_SYS_SDRAM_CONFIG	0xd8e14400*/	/* 0x1400 */
 				/* GB has high prio.
 				   idma has low prio
 				   MPSC has low prio
@@ -393,7 +393,7 @@
 				   virtual interleaving enable */
 				/* 15 14 13:0 */
 				/* 0  1	 0x400 */
-# define CFG_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
+# define CONFIG_SYS_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
 
 
 /*-----------------------------------------------------------------------
@@ -411,31 +411,31 @@
 #define CONFIG_PCI_SCAN_SHOW		/* show devices on bus		*/
 
 /* PCI MEMORY MAP section */
-#define CFG_PCI0_MEM_BASE	0x80000000
-#define CFG_PCI0_MEM_SIZE	_128M
-#define CFG_PCI1_MEM_BASE	0x88000000
-#define CFG_PCI1_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
 
-#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
-#define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
+#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
+#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
 
 /* PCI I/O MAP section */
-#define CFG_PCI0_IO_BASE	0xfa000000
-#define CFG_PCI0_IO_SIZE	_16M
-#define CFG_PCI1_IO_BASE	0xfb000000
-#define CFG_PCI1_IO_SIZE	_16M
+#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
+#define CONFIG_SYS_PCI0_IO_SIZE	_16M
+#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
+#define CONFIG_SYS_PCI1_IO_SIZE	_16M
 
-#define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
-#define CFG_PCI0_IO_SPACE_PCI	0x00000000
-#define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
-#define CFG_PCI1_IO_SPACE_PCI	0x00000000
+#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
+#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000
+#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
+#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000
 
-#define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE)
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
 
 #if defined (CONFIG_750CX)
-#define CFG_PCI_IDSEL 0x0
+#define CONFIG_SYS_PCI_IDSEL 0x0
 #else
-#define CFG_PCI_IDSEL 0x30
+#define CONFIG_SYS_PCI_IDSEL 0x30
 #endif
 
 /*-----------------------------------------------------------------------
@@ -447,16 +447,16 @@
 #define CONFIG_IDE_RESET		/* no reset for ide supported	*/
 #define CONFIG_IDE_PREINIT		/* check for units		*/
 
-#define CFG_IDE_MAXBUS		2		/* max. 1 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		2		/* max. 1 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR	0
-#define CFG_ATA_IDE0_OFFSET	0
-#define CFG_ATA_IDE1_OFFSET	0
+#define CONFIG_SYS_ATA_BASE_ADDR	0
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0
 
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
 
 
 /*----------------------------------------------------------------------
@@ -469,28 +469,28 @@
  */
 
 /* SDRAM */
-#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT0U CFG_IBAT0U
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
 
 /* init ram */
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 
 /* PCI0, PCI1 in one BAT */
-#define CFG_IBAT2L BATL_NO_ACCESS
-#define CFG_IBAT2U CFG_DBAT2U
-#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
+#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* GT regs, bootrom, all the devices, PCI I/O */
-#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 
 /*
  * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7)
@@ -501,52 +501,52 @@
 /*#define SETUP_HIGH_BATS_FX750*/		/* initialize BATS 4-7 */
 
 #ifdef SETUP_HIGH_BATS_FX750
-#define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT4U CFG_IBAT4U
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
 
 /* IBAT5 and DBAT5 */
-#define CFG_IBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT5U (CFG_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT5U CFG_IBAT5U
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
 
 /* IBAT6 and DBAT6 */
-#define CFG_IBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT6U (CFG_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT6U CFG_IBAT6U
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
 
 /* IBAT7 and DBAT7 */
-#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT7U CFG_IBAT7U
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
 
 #else		/* set em out of range for Linux !!!!!!!!!!! */
-#define CFG_IBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT4U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT4U CFG_IBAT4U
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
 
 /* IBAT5 and DBAT5 */
-#define CFG_IBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT5U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT5U CFG_IBAT4U
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT4U
 
 /* IBAT6 and DBAT6 */
-#define CFG_IBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT6U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT6U CFG_IBAT4U
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT4U
 
 /* IBAT7 and DBAT7 */
-#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT7U CFG_IBAT4U
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT4U
 
 #endif
 /* FIXME: ingo end: disable BATs for Linux Kernel */
@@ -560,42 +560,42 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_BOOT_FLASH_WIDTH	2	/* 16 bit */
+#define CONFIG_SYS_BOOT_FLASH_WIDTH	2	/* 16 bit */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
 
 #if 0
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #define CONFIG_ENV_ADDR		0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
-/* #define CONFIG_ENV_ADDR	   (CFG_FLASH_BASE+CFG_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
+/* #define CONFIG_ENV_ADDR	   (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
 #endif
 
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_EEPROM_PAGE_WRITE_BITS 5
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CFG_I2C_EEPROM_ADDR	0x050
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x050
 #define CONFIG_ENV_OFFSET		0x200	/* environment starts at the beginning of the EEPROM */
 #define CONFIG_ENV_SIZE		0x600	/* 2048 bytes may be used for env vars*/
 
-#define CFG_NVRAM_BASE_ADDR	0xf0000000		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-#define CFG_VXWORKS_MAC_PTR	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40)
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0000000		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CONFIG_SYS_VXWORKS_MAC_PTR	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-0x40)
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -603,8 +603,8 @@
  * look in include/mpc74xx.h for the defines used here
  */
 
-/*#define CFG_L2*/
-#undef CFG_L2
+/*#define CONFIG_SYS_L2*/
+#undef CONFIG_SYS_L2
 
 /*    #ifdef CONFIG_750CX*/
 #if defined (CONFIG_750CX) || defined (CONFIG_750FX)
@@ -624,6 +624,6 @@
 #define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02		/* Software reboot		    */
 
-#define CFG_BOARD_ASM_INIT	1
+#define CONFIG_SYS_BOARD_ASM_INIT	1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h
index bfb4242..3263712 100644
--- a/include/configs/CPCIISER4.h
+++ b/include/configs/CPCIISER4.h
@@ -48,8 +48,9 @@
 #define CONFIG_BOOTCOMMAND	"bootm fff00000"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
@@ -92,33 +93,33 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_EXT_SERIAL_CLOCK	1843200	 /* use external serial clock	*/
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	1843200	 /* use external serial clock	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
@@ -135,70 +136,69 @@
 #define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
 					/* resource configuration	*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0404	/* PCI Device ID: CPCI-ISER4	*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffe00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404	/* PCI Device ID: CPCI-ISER4	*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffe00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC08) for environment
  */
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
 #define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
@@ -219,30 +219,30 @@
  */
 
 /* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (Uart 8bit) initialization					*/
-#define CFG_EBC_PB1AP		0x01000480  /* TWT=2,TH=2,no Ready,BEM=0,SOR=1	*/
-#define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB1AP		0x01000480  /* TWT=2,TH=2,no Ready,BEM=0,SOR=1	*/
+#define CONFIG_SYS_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 2 (Uart 32bit) initialization					*/
-#define CFG_EBC_PB2AP		0x000004c0  /* no Ready, BEM=1			*/
-#define CFG_EBC_PB2CR		0xF011C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
+#define CONFIG_SYS_EBC_PB2AP		0x000004c0  /* no Ready, BEM=1			*/
+#define CONFIG_SYS_EBC_PB2CR		0xF011C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
 
 /* Memory Bank 3 (FPGA Reset) initialization					*/
-#define CFG_EBC_PB3AP		0x010004C0  /* no Ready, BEM=1			*/
-#define CFG_EBC_PB3CR		0xF021A000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3AP		0x010004C0  /* no Ready, BEM=1			*/
+#define CONFIG_SYS_EBC_PB3CR		0xF021A000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
-#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Internal Definitions
diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
index 5f4e0c7..cf21fd9 100644
--- a/include/configs/CPU86.h
+++ b/include/configs/CPU86.h
@@ -83,10 +83,10 @@
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 
@@ -96,10 +96,10 @@
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 
@@ -125,8 +125,8 @@
  */
 #define	CONFIG_SOFT_I2C			/* Software I2C support enabled	*/
 
-# define CFG_I2C_SPEED		50000
-# define CFG_I2C_SLAVE		0xFE
+# define CONFIG_SYS_I2C_SPEED		50000
+# define CONFIG_SYS_I2C_SLAVE		0xFE
 /*
  * Software (bit-bang) I2C driver configuration
  */
@@ -141,7 +141,7 @@
 #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
 
 #define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR	0x51
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -149,17 +149,17 @@
  * Disk-On-Chip configuration
  */
 
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
+#define CONFIG_SYS_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
 
-#define CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
+#define CONFIG_SYS_DOC_SUPPORT_2000
+#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
 
 /*-----------------------------------------------------------------------
  * Miscellaneous configuration options
  */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 /*
  * BOOTP options
@@ -189,156 +189,156 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define	CFG_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
+#define	CONFIG_SYS_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * Flash configuration
  */
 
-#define CFG_BOOTROM_BASE	0xFF800000
-#define CFG_BOOTROM_SIZE	0x00080000
-#define CFG_FLASH_BASE		0xFF000000
-#define CFG_FLASH_SIZE		0x00800000
+#define CONFIG_SYS_BOOTROM_BASE	0xFF800000
+#define CONFIG_SYS_BOOTROM_SIZE	0x00080000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks      */
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
 
 /*-----------------------------------------------------------------------
  * Other areas to be mapped
  */
 
 /* CS3: Dual ported SRAM */
-#define CFG_DPSRAM_BASE		0x40000000
-#define CFG_DPSRAM_SIZE		0x00020000
+#define CONFIG_SYS_DPSRAM_BASE		0x40000000
+#define CONFIG_SYS_DPSRAM_SIZE		0x00020000
 
 /* CS4: DiskOnChip */
-#define CFG_DOC_BASE		0xF4000000
-#define CFG_DOC_SIZE		0x00100000
+#define CONFIG_SYS_DOC_BASE		0xF4000000
+#define CONFIG_SYS_DOC_SIZE		0x00100000
 
 /* CS5: FDC37C78 controller */
-#define CFG_FDC37C78_BASE	0xF1000000
-#define CFG_FDC37C78_SIZE	0x00100000
+#define CONFIG_SYS_FDC37C78_BASE	0xF1000000
+#define CONFIG_SYS_FDC37C78_SIZE	0x00100000
 
 /* CS6: Board configuration registers */
-#define CFG_BCRS_BASE		0xF2000000
-#define CFG_BCRS_SIZE		0x00010000
+#define CONFIG_SYS_BCRS_BASE		0xF2000000
+#define CONFIG_SYS_BCRS_SIZE		0x00010000
 
 /* CS7: VME Extended Access Range */
-#define CFG_VMEEAR_BASE		0x80000000
-#define CFG_VMEEAR_SIZE		0x01000000
+#define CONFIG_SYS_VMEEAR_BASE		0x80000000
+#define CONFIG_SYS_VMEEAR_SIZE		0x01000000
 
 /* CS8: VME Standard Access Range */
-#define CFG_VMESAR_BASE		0xFE000000
-#define CFG_VMESAR_SIZE		0x01000000
+#define CONFIG_SYS_VMESAR_BASE		0xFE000000
+#define CONFIG_SYS_VMESAR_SIZE		0x01000000
 
 /* CS9: VME Short I/O Access Range */
-#define CFG_VMESIOAR_BASE	0xFD000000
-#define CFG_VMESIOAR_SIZE	0x01000000
+#define CONFIG_SYS_VMESIOAR_BASE	0xFD000000
+#define CONFIG_SYS_VMESIOAR_SIZE	0x01000000
 
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  *
- * if you change bits in the HRCW, you must also change the CFG_*
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
  * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
  */
 #if defined(CONFIG_BOOT_ROM)
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
 				 HRCW_BPS01 | HRCW_CS10PC01)
 #else
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
 #endif
 
 /* no slaves so just fill with zeros */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR		0xF0000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  *
- * 60x SDRAM is mapped at CFG_SDRAM_BASE.
+ * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-# define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT
 #endif
 
 #if 0
 /* environment is in Flash */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #ifdef CONFIG_BOOT_ROM
-# define CONFIG_ENV_ADDR		(CFG_FLASH_BASE+0x70000)
+# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x70000)
 # define CONFIG_ENV_SIZE		0x10000
 # define CONFIG_ENV_SECT_SIZE	0x10000
 #endif
 #else
 /* environment is in EEPROM */
 #define CONFIG_ENV_IS_IN_EEPROM	1
-#define CFG_I2C_EEPROM_ADDR	0x58	/* EEPROM X24C16		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x58	/* EEPROM X24C16		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 /* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 #define CONFIG_ENV_OFFSET		512
 #define CONFIG_ENV_SIZE		(2048 - 512)
 #endif
@@ -355,9 +355,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 #if defined(CONFIG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -370,30 +370,30 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
+#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
 			 HID0_DCI|HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
-#define CFG_HID2        0
+#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2        0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register                                     5-5
  *-----------------------------------------------------------------------
  * turn on Checkstop Reset Enable
  */
-#define CFG_RMR         RMR_CSRE
+#define CONFIG_SYS_RMR         RMR_CSRE
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration                                       4-25
  *-----------------------------------------------------------------------
  */
 #define BCR_APD01	0x10000000
-#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration                             4-31
  *-----------------------------------------------------------------------
  */
-#define CFG_SIUMCR      (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
+#define CONFIG_SYS_SIUMCR      (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
 			 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
 
 /*-----------------------------------------------------------------------
@@ -403,10 +403,10 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
@@ -416,7 +416,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control                 4-42
@@ -424,33 +424,33 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control                                   9-8
  *-----------------------------------------------------------------------
  * Ensure DFBRG is Divide by 16
  */
-#define CFG_SCCR        SCCR_DFBRG01
+#define CONFIG_SYS_SCCR        SCCR_DFBRG01
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration                         13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR        0
+#define CONFIG_SYS_RCCR        0
 
-#define CFG_MIN_AM_MASK	0xC0000000
+#define CONFIG_SYS_MIN_AM_MASK	0xC0000000
 /*-----------------------------------------------------------------------
  * MPTPR - Memory Refresh Timer Prescaler Register              10-18
  *-----------------------------------------------------------------------
  */
-#define CFG_MPTPR       0x1F00
+#define CONFIG_SYS_MPTPR       0x1F00
 
 /*-----------------------------------------------------------------------
  * PSRT - Refresh Timer Register                                10-16
  *-----------------------------------------------------------------------
  */
-#define CFG_PSRT        0x0f
+#define CONFIG_SYS_PSRT        0x0f
 
 /*-----------------------------------------------------------------------
  * PSRT - SDRAM Mode Register                                   10-10
@@ -459,12 +459,12 @@
 
 	/* SDRAM initialization values for 8-column chips
 	 */
-#define CFG_OR2_8COL	(CFG_MIN_AM_MASK		|\
+#define CONFIG_SYS_OR2_8COL	(CONFIG_SYS_MIN_AM_MASK		|\
 			 ORxS_BPD_4			|\
 			 ORxS_ROWST_PBI0_A9		|\
 			 ORxS_NUMR_12)
 
-#define CFG_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
+#define CONFIG_SYS_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
 			 PSDMR_BSMA_A14_A16		|\
 			 PSDMR_SDA10_PBI0_A10		|\
 			 PSDMR_RFRC_7_CLK		|\
@@ -476,12 +476,12 @@
 
 	/* SDRAM initialization values for 9-column chips
 	 */
-#define CFG_OR2_9COL	(CFG_MIN_AM_MASK		|\
+#define CONFIG_SYS_OR2_9COL	(CONFIG_SYS_MIN_AM_MASK		|\
 			 ORxS_BPD_4			|\
 			 ORxS_ROWST_PBI0_A7		|\
 			 ORxS_NUMR_13)
 
-#define CFG_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
+#define CONFIG_SYS_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
 			 PSDMR_BSMA_A13_A15		|\
 			 PSDMR_SDA10_PBI0_A9		|\
 			 PSDMR_RFRC_7_CLK		|\
@@ -502,17 +502,17 @@
  *
  */
 
-#define CFG_MRS_OFFS	0x00000000
+#define CONFIG_SYS_MRS_OFFS	0x00000000
 
 #ifdef CONFIG_BOOT_ROM
 /* Bank 0 - Boot ROM
  */
-#define CFG_BR0_PRELIM  ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 			 BRx_PS_8                       |\
 			 BRx_MS_GPCM_P                  |\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_BOOTROM_SIZE)   |\
+#define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)   |\
 			 ORxG_CSNT                      |\
 			 ORxG_ACS_DIV1                  |\
 			 ORxG_SCY_3_CLK                 |\
@@ -520,12 +520,12 @@
 
 /* Bank 1 - FLASH
  */
-#define CFG_BR1_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_64                      |\
 			 BRx_MS_GPCM_P                  |\
 			 BRx_V)
 
-#define CFG_OR1_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)     |\
+#define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
 			 ORxG_CSNT                      |\
 			 ORxG_ACS_DIV1                  |\
 			 ORxG_SCY_3_CLK                 |\
@@ -534,12 +534,12 @@
 #else /* CONFIG_BOOT_ROM */
 /* Bank 0 - FLASH
  */
-#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_64                      |\
 			 BRx_MS_GPCM_P                  |\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)     |\
+#define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
 			 ORxG_CSNT                      |\
 			 ORxG_ACS_DIV1                  |\
 			 ORxG_SCY_3_CLK                 |\
@@ -547,12 +547,12 @@
 
 /* Bank 1 - Boot ROM
  */
-#define CFG_BR1_PRELIM  ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 			 BRx_PS_8                       |\
 			 BRx_MS_GPCM_P                  |\
 			 BRx_V)
 
-#define CFG_OR1_PRELIM  (P2SZ_TO_AM(CFG_BOOTROM_SIZE)   |\
+#define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)   |\
 			 ORxG_CSNT                      |\
 			 ORxG_ACS_DIV1                  |\
 			 ORxG_SCY_3_CLK                 |\
@@ -563,25 +563,25 @@
 
 /* Bank 2 - 60x bus SDRAM
  */
-#ifndef CFG_RAMBOOT
-#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_64                      |\
 			 BRx_MS_SDRAM_P                 |\
 			 BRx_V)
 
-#define CFG_OR2_PRELIM	 CFG_OR2_9COL
+#define CONFIG_SYS_OR2_PRELIM	 CONFIG_SYS_OR2_9COL
 
-#define CFG_PSDMR	 CFG_PSDMR_9COL
-#endif /* CFG_RAMBOOT */
+#define CONFIG_SYS_PSDMR	 CONFIG_SYS_PSDMR_9COL
+#endif /* CONFIG_SYS_RAMBOOT */
 
 /* Bank 3 - Dual Ported SRAM
  */
-#define CFG_BR3_PRELIM  ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR3_PRELIM  ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
 			 BRx_PS_16                      |\
 			 BRx_MS_GPCM_P                  |\
 			 BRx_V)
 
-#define CFG_OR3_PRELIM  (P2SZ_TO_AM(CFG_DPSRAM_SIZE)    |\
+#define CONFIG_SYS_OR3_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE)    |\
 			 ORxG_CSNT                      |\
 			 ORxG_ACS_DIV1                  |\
 			 ORxG_SCY_5_CLK                 |\
@@ -589,47 +589,47 @@
 
 /* Bank 4 - DiskOnChip
  */
-#define CFG_BR4_PRELIM  ((CFG_DOC_BASE & BRx_BA_MSK)    |\
+#define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)    |\
 			 BRx_PS_8                       |\
 			 BRx_MS_GPCM_P                  |\
 			 BRx_V)
 
-#define CFG_OR4_PRELIM  (P2SZ_TO_AM(CFG_DOC_SIZE)       |\
+#define CONFIG_SYS_OR4_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)       |\
 			 ORxG_ACS_DIV2                  |\
 			 ORxG_SCY_5_CLK                 |\
 			 ORxU_EHTR_8IDLE)
 
 /* Bank 5 - FDC37C78 controller
  */
-#define CFG_BR5_PRELIM  ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR5_PRELIM  ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
 			 BRx_PS_8                         |\
 			 BRx_MS_GPCM_P                    |\
 			 BRx_V)
 
-#define CFG_OR5_PRELIM  (P2SZ_TO_AM(CFG_FDC37C78_SIZE)    |\
+#define CONFIG_SYS_OR5_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE)    |\
 			 ORxG_ACS_DIV2                    |\
 			 ORxG_SCY_8_CLK                   |\
 			 ORxU_EHTR_8IDLE)
 
 /* Bank 6 - Board control registers
  */
-#define CFG_BR6_PRELIM  ((CFG_BCRS_BASE & BRx_BA_MSK)   |\
+#define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK)   |\
 			 BRx_PS_8                       |\
 			 BRx_MS_GPCM_P                  |\
 			 BRx_V)
 
-#define CFG_OR6_PRELIM  (P2SZ_TO_AM(CFG_BCRS_SIZE)      |\
+#define CONFIG_SYS_OR6_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE)      |\
 			 ORxG_CSNT                      |\
 			 ORxG_SCY_5_CLK)
 
 /* Bank 7 - VME Extended Access Range
  */
-#define CFG_BR7_PRELIM  ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR7_PRELIM  ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
 			 BRx_PS_32                      |\
 			 BRx_MS_GPCM_P                  |\
 			 BRx_V)
 
-#define CFG_OR7_PRELIM  (P2SZ_TO_AM(CFG_VMEEAR_SIZE)    |\
+#define CONFIG_SYS_OR7_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE)    |\
 			 ORxG_CSNT                      |\
 			 ORxG_ACS_DIV1                  |\
 			 ORxG_SCY_5_CLK                 |\
@@ -637,12 +637,12 @@
 
 /* Bank 8 - VME Standard Access Range
  */
-#define CFG_BR8_PRELIM  ((CFG_VMESAR_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR8_PRELIM  ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
 			 BRx_PS_16                      |\
 			 BRx_MS_GPCM_P                  |\
 			 BRx_V)
 
-#define CFG_OR8_PRELIM  (P2SZ_TO_AM(CFG_VMESAR_SIZE)    |\
+#define CONFIG_SYS_OR8_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE)    |\
 			 ORxG_CSNT                      |\
 			 ORxG_ACS_DIV1                  |\
 			 ORxG_SCY_5_CLK                 |\
@@ -650,12 +650,12 @@
 
 /* Bank 9 - VME Short I/O Access Range
  */
-#define CFG_BR9_PRELIM  ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR9_PRELIM  ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
 			 BRx_PS_16                        |\
 			 BRx_MS_GPCM_P                    |\
 			 BRx_V)
 
-#define CFG_OR9_PRELIM  (P2SZ_TO_AM(CFG_VMESIOAR_SIZE)    |\
+#define CONFIG_SYS_OR9_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE)    |\
 			 ORxG_CSNT                        |\
 			 ORxG_ACS_DIV1                    |\
 			 ORxG_SCY_5_CLK                   |\
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index e087624..489378a 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -87,10 +87,10 @@
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 
@@ -100,10 +100,10 @@
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 
@@ -129,8 +129,8 @@
  */
 #define CONFIG_SOFT_I2C			/* Software I2C support enabled */
 
-# define CFG_I2C_SPEED		50000
-# define CFG_I2C_SLAVE		0xFE
+# define CONFIG_SYS_I2C_SPEED		50000
+# define CONFIG_SYS_I2C_SLAVE		0xFE
 /*
  * Software (bit-bang) I2C driver configuration
  */
@@ -145,7 +145,7 @@
 #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
 
 #define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR	0x51
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -153,17 +153,17 @@
  * Disk-On-Chip configuration
  */
 
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
+#define CONFIG_SYS_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
 
-#define CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
+#define CONFIG_SYS_DOC_SUPPORT_2000
+#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
 
 /*-----------------------------------------------------------------------
  * Miscellaneous configuration options
  */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 /*
  * BOOTP options
@@ -196,27 +196,27 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END 0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END 0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define CFG_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
+#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
 
 #define CONFIG_LOOPW
 
@@ -225,135 +225,135 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * Flash configuration
  */
 
-#define CFG_BOOTROM_BASE	0xFF800000
-#define CFG_BOOTROM_SIZE	0x00080000
-#define CFG_FLASH_BASE		0xFF000000
-#define CFG_FLASH_SIZE		0x00800000
+#define CONFIG_SYS_BOOTROM_BASE	0xFF800000
+#define CONFIG_SYS_BOOTROM_SIZE	0x00080000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	135	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	135	/* max num of sects on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
 
 /*-----------------------------------------------------------------------
  * Other areas to be mapped
  */
 
 /* CS3: Dual ported SRAM */
-#define CFG_DPSRAM_BASE		0x40000000
-#define CFG_DPSRAM_SIZE		0x00100000
+#define CONFIG_SYS_DPSRAM_BASE		0x40000000
+#define CONFIG_SYS_DPSRAM_SIZE		0x00100000
 
 /* CS4: DiskOnChip */
-#define CFG_DOC_BASE		0xF4000000
-#define CFG_DOC_SIZE		0x00100000
+#define CONFIG_SYS_DOC_BASE		0xF4000000
+#define CONFIG_SYS_DOC_SIZE		0x00100000
 
 /* CS5: FDC37C78 controller */
-#define CFG_FDC37C78_BASE	0xF1000000
-#define CFG_FDC37C78_SIZE	0x00100000
+#define CONFIG_SYS_FDC37C78_BASE	0xF1000000
+#define CONFIG_SYS_FDC37C78_SIZE	0x00100000
 
 /* CS6: Board configuration registers */
-#define CFG_BCRS_BASE		0xF2000000
-#define CFG_BCRS_SIZE		0x00010000
+#define CONFIG_SYS_BCRS_BASE		0xF2000000
+#define CONFIG_SYS_BCRS_SIZE		0x00010000
 
 /* CS7: VME Extended Access Range */
-#define CFG_VMEEAR_BASE		0x60000000
-#define CFG_VMEEAR_SIZE		0x01000000
+#define CONFIG_SYS_VMEEAR_BASE		0x60000000
+#define CONFIG_SYS_VMEEAR_SIZE		0x01000000
 
 /* CS8: VME Standard Access Range */
-#define CFG_VMESAR_BASE		0xFE000000
-#define CFG_VMESAR_SIZE		0x01000000
+#define CONFIG_SYS_VMESAR_BASE		0xFE000000
+#define CONFIG_SYS_VMESAR_SIZE		0x01000000
 
 /* CS9: VME Short I/O Access Range */
-#define CFG_VMESIOAR_BASE	0xFD000000
-#define CFG_VMESIOAR_SIZE	0x01000000
+#define CONFIG_SYS_VMESIOAR_BASE	0xFD000000
+#define CONFIG_SYS_VMESIOAR_SIZE	0x01000000
 
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  *
- * if you change bits in the HRCW, you must also change the CFG_*
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
  * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
  */
 #if defined(CONFIG_BOOT_ROM)
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
 				 HRCW_BPS01 | HRCW_CS10PC01)
 #else
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
 #endif
 
 /* no slaves so just fill with zeros */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR		0xF0000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  *
- * 60x SDRAM is mapped at CFG_SDRAM_BASE.
+ * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-# define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT
 #endif
 
 #ifdef	CONFIG_PCI
 #define CONFIG_PCI_PNP
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
+#define CONFIG_SYS_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
 #endif
 
 #if 0
 /* environment is in Flash */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #ifdef CONFIG_BOOT_ROM
-# define CONFIG_ENV_ADDR		(CFG_FLASH_BASE+0x70000)
+# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x70000)
 # define CONFIG_ENV_SIZE		0x10000
 # define CONFIG_ENV_SECT_SIZE	0x10000
 #endif
 #else
 /* environment is in EEPROM */
 #define CONFIG_ENV_IS_IN_EEPROM	1
-#define CFG_I2C_EEPROM_ADDR	0x58	/* EEPROM X24C16		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x58	/* EEPROM X24C16		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 #define CONFIG_ENV_OFFSET		512
 #define CONFIG_ENV_SIZE		(2048 - 512)
 #endif
@@ -370,9 +370,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
 #if defined(CONFIG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -385,30 +385,30 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|\
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|\
 			 HID0_DCI|HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL	(HID0_IFEM|HID0_ABE)
-#define CFG_HID2	0
+#define CONFIG_SYS_HID0_FINAL	(HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2	0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register					 5-5
  *-----------------------------------------------------------------------
  * turn on Checkstop Reset Enable
  */
-#define CFG_RMR		RMR_CSRE
+#define CONFIG_SYS_RMR		RMR_CSRE
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration					 4-25
  *-----------------------------------------------------------------------
  */
 #define BCR_APD01	0x10000000
-#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration				 4-31
  *-----------------------------------------------------------------------
  */
-#define CFG_SIUMCR	(SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
+#define CONFIG_SYS_SIUMCR	(SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
 			 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
 
 /*-----------------------------------------------------------------------
@@ -418,10 +418,10 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
@@ -431,7 +431,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		 4-42
@@ -439,22 +439,22 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control					 9-8
  *-----------------------------------------------------------------------
  * Ensure DFBRG is Divide by 16
  */
-#define CFG_SCCR	SCCR_DFBRG01
+#define CONFIG_SYS_SCCR	SCCR_DFBRG01
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration				13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR	0
+#define CONFIG_SYS_RCCR	0
 
-#define CFG_MIN_AM_MASK 0xC0000000
+#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
 
 /*
  * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
@@ -465,13 +465,13 @@
  * MPTPR - Memory Refresh Timer Prescaler Register		10-18
  *-----------------------------------------------------------------------
  */
-#define CFG_MPTPR	0x2000
+#define CONFIG_SYS_MPTPR	0x2000
 
 /*-----------------------------------------------------------------------
  * PSRT - Refresh Timer Register				10-16
  *-----------------------------------------------------------------------
  */
-#define CFG_PSRT	0x16
+#define CONFIG_SYS_PSRT	0x16
 
 /*-----------------------------------------------------------------------
  * PSRT - SDRAM Mode Register					10-10
@@ -480,12 +480,12 @@
 
 	/* SDRAM initialization values for 8-column chips
 	 */
-#define CFG_OR2_8COL	(CFG_MIN_AM_MASK		|\
+#define CONFIG_SYS_OR2_8COL	(CONFIG_SYS_MIN_AM_MASK		|\
 			 ORxS_BPD_4			|\
 			 ORxS_ROWST_PBI0_A9		|\
 			 ORxS_NUMR_12)
 
-#define CFG_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
+#define CONFIG_SYS_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
 			 PSDMR_BSMA_A14_A16		|\
 			 PSDMR_SDA10_PBI0_A10		|\
 			 PSDMR_RFRC_7_CLK		|\
@@ -497,12 +497,12 @@
 
 	/* SDRAM initialization values for 9-column chips
 	 */
-#define CFG_OR2_9COL	(CFG_MIN_AM_MASK		|\
+#define CONFIG_SYS_OR2_9COL	(CONFIG_SYS_MIN_AM_MASK		|\
 			 ORxS_BPD_4			|\
 			 ORxS_ROWST_PBI0_A7		|\
 			 ORxS_NUMR_13)
 
-#define CFG_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
+#define CONFIG_SYS_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
 			 PSDMR_BSMA_A13_A15		|\
 			 PSDMR_SDA10_PBI0_A9		|\
 			 PSDMR_RFRC_7_CLK		|\
@@ -514,12 +514,12 @@
 
 	/* SDRAM initialization values for 10-column chips
 	 */
-#define CFG_OR2_10COL	(CFG_MIN_AM_MASK		|\
+#define CONFIG_SYS_OR2_10COL	(CONFIG_SYS_MIN_AM_MASK		|\
 			 ORxS_BPD_4			|\
 			 ORxS_ROWST_PBI1_A4		|\
 			 ORxS_NUMR_13)
 
-#define CFG_PSDMR_10COL	(PSDMR_PBI			|\
+#define CONFIG_SYS_PSDMR_10COL	(PSDMR_PBI			|\
 			 PSDMR_SDAM_A17_IS_A5		|\
 			 PSDMR_BSMA_A13_A15		|\
 			 PSDMR_SDA10_PBI1_A6		|\
@@ -541,17 +541,17 @@
  *
  */
 
-#define CFG_MRS_OFFS	0x00000000
+#define CONFIG_SYS_MRS_OFFS	0x00000000
 
 #ifdef CONFIG_BOOT_ROM
 /* Bank 0 - Boot ROM
  */
-#define CFG_BR0_PRELIM	((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 			 BRx_PS_8			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_BOOTROM_SIZE)	|\
+#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_5_CLK			|\
@@ -559,12 +559,12 @@
 
 /* Bank 1 - FLASH
  */
-#define CFG_BR1_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_64			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
+#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_5_CLK			|\
@@ -573,12 +573,12 @@
 #else /* CONFIG_BOOT_ROM */
 /* Bank 0 - FLASH
  */
-#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_64			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
+#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_5_CLK			|\
@@ -586,12 +586,12 @@
 
 /* Bank 1 - Boot ROM
  */
-#define CFG_BR1_PRELIM	((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 			 BRx_PS_8			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_BOOTROM_SIZE)	|\
+#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_5_CLK			|\
@@ -602,25 +602,25 @@
 
 /* Bank 2 - 60x bus SDRAM
  */
-#ifndef CFG_RAMBOOT
-#define CFG_BR2_PRELIM	((CFG_SDRAM_BASE & BRx_BA_MSK)	|\
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_64			|\
 			 BRx_MS_SDRAM_P			|\
 			 BRx_V)
 
-#define CFG_OR2_PRELIM	 CFG_OR2_8COL
+#define CONFIG_SYS_OR2_PRELIM	 CONFIG_SYS_OR2_8COL
 
-#define CFG_PSDMR	 CFG_PSDMR_8COL
-#endif /* CFG_RAMBOOT */
+#define CONFIG_SYS_PSDMR	 CONFIG_SYS_PSDMR_8COL
+#endif /* CONFIG_SYS_RAMBOOT */
 
 /* Bank 3 - Dual Ported SRAM
  */
-#define CFG_BR3_PRELIM	((CFG_DPSRAM_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
 			 BRx_PS_16			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR3_PRELIM	(P2SZ_TO_AM(CFG_DPSRAM_SIZE)	|\
+#define CONFIG_SYS_OR3_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_7_CLK			|\
@@ -628,12 +628,12 @@
 
 /* Bank 4 - DiskOnChip
  */
-#define CFG_BR4_PRELIM	((CFG_DOC_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_BR4_PRELIM	((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_8			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR4_PRELIM	(P2SZ_TO_AM(CFG_DOC_SIZE)	|\
+#define CONFIG_SYS_OR4_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV2			|\
 			 ORxG_SCY_9_CLK			|\
@@ -641,35 +641,35 @@
 
 /* Bank 5 - FDC37C78 controller
  */
-#define CFG_BR5_PRELIM	((CFG_FDC37C78_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR5_PRELIM	((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
 			 BRx_PS_8			  |\
 			 BRx_MS_GPCM_P			  |\
 			 BRx_V)
 
-#define CFG_OR5_PRELIM	(P2SZ_TO_AM(CFG_FDC37C78_SIZE)	  |\
+#define CONFIG_SYS_OR5_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE)	  |\
 			 ORxG_ACS_DIV2			  |\
 			 ORxG_SCY_10_CLK		  |\
 			 ORxU_EHTR_8IDLE)
 
 /* Bank 6 - Board control registers
  */
-#define CFG_BR6_PRELIM	((CFG_BCRS_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_BR6_PRELIM	((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_8			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR6_PRELIM	(P2SZ_TO_AM(CFG_BCRS_SIZE)	|\
+#define CONFIG_SYS_OR6_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_SCY_7_CLK)
 
 /* Bank 7 - VME Extended Access Range
  */
-#define CFG_BR7_PRELIM	((CFG_VMEEAR_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR7_PRELIM	((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
 			 BRx_PS_32			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR7_PRELIM	(P2SZ_TO_AM(CFG_VMEEAR_SIZE)	|\
+#define CONFIG_SYS_OR7_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_7_CLK			|\
@@ -677,12 +677,12 @@
 
 /* Bank 8 - VME Standard Access Range
  */
-#define CFG_BR8_PRELIM	((CFG_VMESAR_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR8_PRELIM	((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
 			 BRx_PS_16			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR8_PRELIM	(P2SZ_TO_AM(CFG_VMESAR_SIZE)	|\
+#define CONFIG_SYS_OR8_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_7_CLK			|\
@@ -690,12 +690,12 @@
 
 /* Bank 9 - VME Short I/O Access Range
  */
-#define CFG_BR9_PRELIM	((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR9_PRELIM	((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
 			 BRx_PS_16			  |\
 			 BRx_MS_GPCM_P			  |\
 			 BRx_V)
 
-#define CFG_OR9_PRELIM	(P2SZ_TO_AM(CFG_VMESIOAR_SIZE)	  |\
+#define CONFIG_SYS_OR9_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE)	  |\
 			 ORxG_CSNT			  |\
 			 ORxG_ACS_DIV1			  |\
 			 ORxG_SCY_7_CLK			  |\
diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h
index 4639d30..527c846 100644
--- a/include/configs/CRAYL1.h
+++ b/include/configs/CRAYL1.h
@@ -39,6 +39,8 @@
 #define CONFIG_SYS_CLK_FREQ 25000000
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		    1	/* MII PHY management */
 #define	CONFIG_PHY_ADDR		1	/* PHY address; handling of ENET */
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* early setup for 405gp */
@@ -53,7 +55,7 @@
 
 /* Bootcmd is overridden by the bootscript in board/cray/L1
  */
-#define	CFG_AUTOLOAD		"no"
+#define	CONFIG_SYS_AUTOLOAD		"no"
 #define CONFIG_BOOTCOMMAND	"dhcp"
 
 /*
@@ -63,15 +65,15 @@
  */
 #define CONFIG_HARD_I2C         1		/* hardware support for i2c */
 #define CONFIG_SDRAM_BANK0		1
-#define CFG_I2C_SPEED		    400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		    0x7F
-#define CFG_I2C_EEPROM_ADDR     0x57
-#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_SPEED		    400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		    0x7F
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 #define CONFIG_IDENT_STRING     "Cray L1"
 #define CONFIG_ENV_OVERWRITE     1
-#define	CFG_HZ		             1000	/* decrementer freq: 1 ms ticks	*/
-#define CFG_HUSH_PARSER			1
-#define CFG_PROMPT_HUSH_PS2		"> "
+#define	CONFIG_SYS_HZ		             1000	/* decrementer freq: 1 ms ticks	*/
+#define CONFIG_SYS_HUSH_PARSER			1
+#define CONFIG_SYS_PROMPT_HUSH_PS2		"> "
 #define CONFIG_AUTOSCRIPT		1
 
 
@@ -84,7 +86,7 @@
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_NET
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_CONSOLE
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_ECHO
@@ -123,50 +125,50 @@
  * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn
  * drives the system clock.
  */
-#define CFG_BASE_BAUD       403225
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BASE_BAUD       403225
+#define CONFIG_SYS_BAUDRATE_TABLE  \
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_PROMPT	"=> "				/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE	256				/* Console I/O Buffer Size	*/
-#define CFG_BARGSIZE	CFG_CBSIZE			/* Boot Argument Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS	16				/* max number of command args	*/
+#define CONFIG_SYS_PROMPT	"=> "				/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE	256				/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE			/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16				/* max number of command args	*/
 
 
-#define CFG_LOAD_ADDR		0x100000	/* where to load what we get from TFTP */
-#define CFG_TFTP_LOADADDR	CFG_LOAD_ADDR
-#define CFG_EXTBDINFO		1		/* To use extended board_into (bd_t) */
-#define CFG_DRAM_TEST		1
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* where to load what we get from TFTP */
+#define CONFIG_SYS_TFTP_LOADADDR	CONFIG_SYS_LOAD_ADDR
+#define CONFIG_SYS_EXTBDINFO		1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_DRAM_TEST		1
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFC00000
-#define CFG_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFC00000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 
 
-#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	 1		/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	 64		/* max number of sectors on one chip	*/
-#define CFG_FLASH_ERASE_TOUT 120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT 500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	 1		/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	 64		/* max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500	/* Timeout for Flash Write (in ms)	*/
 
 /* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector  */
 #define CONFIG_ENV_OFFSET		0x3c8000
@@ -177,19 +179,19 @@
 /* Memory tests: U-BOOT relocates itself to the top of Ram, so its at
  * 32meg-(128k+some_malloc_space+copy-of-ENV sector)..
  */
-#define CFG_SDRAM_SIZE		32		/* megs of ram */
-#define CFG_MEMTEST_START	0x2000  /* memtest works from the end of */
+#define CONFIG_SYS_SDRAM_SIZE		32		/* megs of ram */
+#define CONFIG_SYS_MEMTEST_START	0x2000  /* memtest works from the end of */
 									/* the exception vector table */
 									/* to the end of the DRAM  */
 									/* less monitor and malloc area */
-#define CFG_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
-#define CFG_MALLOC_LEN		(128 << 10)	/* 128k for malloc space */
-#define CFG_MEM_END_USAGE	( CFG_MONITOR_LEN \
-				+ CFG_MALLOC_LEN \
+#define CONFIG_SYS_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* 128k for malloc space */
+#define CONFIG_SYS_MEM_END_USAGE	( CONFIG_SYS_MONITOR_LEN \
+				+ CONFIG_SYS_MALLOC_LEN \
 				+ CONFIG_ENV_SECT_SIZE \
-				+ CFG_STACK_USAGE )
+				+ CONFIG_SYS_STACK_USAGE )
 
-#define CFG_MEMTEST_END		(CFG_SDRAM_SIZE * 1024 * 1024 - CFG_MEM_END_USAGE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 - CONFIG_SYS_MEM_END_USAGE)
 /* END ENVIRONNEMENT FLASH */
 
 /*
@@ -198,7 +200,7 @@
  * BR0/1 and OR0/1 (FLASH)
  */
 
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	*/
 
 
 /*-----------------------------------------------------------------------
@@ -206,23 +208,23 @@
  */
 #if 1
 /* On Chip Memory location */
-#define CFG_TEMP_STACK_OCM	1
-#define CFG_OCM_DATA_ADDR	0xF0000000
-#define CFG_OCM_DATA_SIZE	0x1000
-
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE      256  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE      256  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 #else
-#define CFG_OCM_DATA_ADDR	0xF0000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE	/* End of On Chip SRAM	     */
-#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE	/* End of On Chip SRAM	     */
+#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #endif
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/CU824.h b/include/configs/CU824.h
index a40df76..4a3f2bc 100644
--- a/include/configs/CU824.h
+++ b/include/configs/CU824.h
@@ -48,7 +48,7 @@
 
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		9600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
 
@@ -83,54 +83,54 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 
 #if 1
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
 #endif
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 /* Print Buffer Size
  */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE	    0x00000000
-#define CFG_FLASH_BASE	    0xFF000000
+#define CONFIG_SYS_SDRAM_BASE	    0x00000000
+#define CONFIG_SYS_FLASH_BASE	    0xFF000000
 
-#define CFG_RESET_ADDRESS   0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 
-#define CFG_EUMB_ADDR	    0xFCE00000
+#define CONFIG_SYS_EUMB_ADDR	    0xFCE00000
 
-#define CFG_MONITOR_BASE    TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
 
-#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
 
-#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
 
 	/* Maximum amount of RAM.
 	 */
-#define CFG_MAX_RAM_SIZE    0x10000000
+#define CONFIG_SYS_MAX_RAM_SIZE    0x10000000
 
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#undef CFG_RAMBOOT
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#undef CONFIG_SYS_RAMBOOT
 #else
-#define CFG_RAMBOOT
+#define CONFIG_SYS_RAMBOOT
 #endif
 
 
@@ -140,24 +140,24 @@
 
 	/* Size in bytes reserved for initial data
 	 */
-#define CFG_GBL_DATA_SIZE    128
+#define CONFIG_SYS_GBL_DATA_SIZE    128
 
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_END      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
 
-#define CFG_NS16550_REG_SIZE	4
+#define CONFIG_SYS_NS16550_REG_SIZE	4
 
-#define CFG_NS16550_CLK		(14745600 / 2)
+#define CONFIG_SYS_NS16550_CLK		(14745600 / 2)
 
-#define CFG_NS16550_COM1	0xFE800080
-#define CFG_NS16550_COM2	0xFE8000C0
+#define CONFIG_SYS_NS16550_COM1	0xFE800080
+#define CONFIG_SYS_NS16550_COM2	0xFE8000C0
 
 /*
  * Low Level Configuration Settings
@@ -167,35 +167,35 @@
  */
 
 #define CONFIG_SYS_CLK_FREQ  33000000
-#define CFG_HZ		     1000
+#define CONFIG_SYS_HZ		     1000
 
 	/* Bit-field values for MCCR1.
 	 */
-#define CFG_ROMNAL	    0
-#define CFG_ROMFAL	    7
+#define CONFIG_SYS_ROMNAL	    0
+#define CONFIG_SYS_ROMFAL	    7
 
 	/* Bit-field values for MCCR2.
 	 */
-#define CFG_REFINT	    430	    /* Refresh interval			*/
+#define CONFIG_SYS_REFINT	    430	    /* Refresh interval			*/
 
 	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 	 */
-#define CFG_BSTOPRE	    192
+#define CONFIG_SYS_BSTOPRE	    192
 
 	/* Bit-field values for MCCR3.
 	 */
-#define CFG_REFREC	    2	    /* Refresh to activate interval	*/
-#define CFG_RDLAT	    3	    /* Data latancy from read command	*/
+#define CONFIG_SYS_REFREC	    2	    /* Refresh to activate interval	*/
+#define CONFIG_SYS_RDLAT	    3	    /* Data latancy from read command	*/
 
 	/* Bit-field values for MCCR4.
 	 */
-#define CFG_PRETOACT	    2	    /* Precharge to activate interval	*/
-#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval	*/
-#define CFG_SDMODE_CAS_LAT  2	    /* SDMODE CAS latancy		*/
-#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type			*/
-#define CFG_SDMODE_BURSTLEN 2	    /* SDMODE Burst length		*/
-#define CFG_ACTORW	    2
-#define CFG_REGISTERD_TYPE_BUFFER 1
+#define CONFIG_SYS_PRETOACT	    2	    /* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE	    5	    /* Activate to Precharge interval	*/
+#define CONFIG_SYS_SDMODE_CAS_LAT  2	    /* SDMODE CAS latancy		*/
+#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type			*/
+#define CONFIG_SYS_SDMODE_BURSTLEN 2	    /* SDMODE Burst length		*/
+#define CONFIG_SYS_ACTORW	    2
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
 
 /* Memory bank settings.
  * Only bits 20-29 are actually used from these vales to set the
@@ -204,69 +204,69 @@
  * address. Refer to the MPC8240 book.
  */
 
-#define CFG_BANK0_START	    0x00000000
-#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START	    0x3ff00000
-#define CFG_BANK1_END	    0x3fffffff
-#define CFG_BANK1_ENABLE    0
-#define CFG_BANK2_START	    0x3ff00000
-#define CFG_BANK2_END	    0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START	    0x3ff00000
-#define CFG_BANK3_END	    0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START	    0x3ff00000
-#define CFG_BANK4_END	    0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START	    0x3ff00000
-#define CFG_BANK5_END	    0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START	    0x3ff00000
-#define CFG_BANK6_END	    0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START	    0x3ff00000
-#define CFG_BANK7_END	    0x3fffffff
-#define CFG_BANK7_ENABLE    0
-
-#define CFG_ODCR	    0xff
-
-#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L  CFG_IBAT0L
-#define CFG_DBAT0U  CFG_IBAT0U
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-#define CFG_DBAT2L  CFG_IBAT2L
-#define CFG_DBAT2U  CFG_IBAT2U
-#define CFG_DBAT3L  CFG_IBAT3L
-#define CFG_DBAT3U  CFG_IBAT3U
+#define CONFIG_SYS_BANK0_START	    0x00000000
+#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE    1
+#define CONFIG_SYS_BANK1_START	    0x3ff00000
+#define CONFIG_SYS_BANK1_END	    0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE    0
+#define CONFIG_SYS_BANK2_START	    0x3ff00000
+#define CONFIG_SYS_BANK2_END	    0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE    0
+#define CONFIG_SYS_BANK3_START	    0x3ff00000
+#define CONFIG_SYS_BANK3_END	    0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE    0
+#define CONFIG_SYS_BANK4_START	    0x3ff00000
+#define CONFIG_SYS_BANK4_END	    0x3fffffff
+#define CONFIG_SYS_BANK4_ENABLE    0
+#define CONFIG_SYS_BANK5_START	    0x3ff00000
+#define CONFIG_SYS_BANK5_END	    0x3fffffff
+#define CONFIG_SYS_BANK5_ENABLE    0
+#define CONFIG_SYS_BANK6_START	    0x3ff00000
+#define CONFIG_SYS_BANK6_END	    0x3fffffff
+#define CONFIG_SYS_BANK6_ENABLE    0
+#define CONFIG_SYS_BANK7_START	    0x3ff00000
+#define CONFIG_SYS_BANK7_END	    0x3fffffff
+#define CONFIG_SYS_BANK7_ENABLE    0
+
+#define CONFIG_SYS_ODCR	    0xff
+
+#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT	39	/* Max number of sectors in one bank	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* Max number of flash banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	39	/* Max number of sectors in one bank	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 	/* Warining: environment is not EMBEDDED in the U-Boot code.
 	 * It's stored in flash separately.
@@ -285,9 +285,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SIZE	32
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /*
@@ -310,11 +310,11 @@
 #define CONFIG_TULIP
 #define CONFIG_TULIP_USE_IO
 
-#define CFG_ETH_DEV_FN	     0x7800
-#define CFG_ETH_IOBASE	     0x00104000
+#define CONFIG_SYS_ETH_DEV_FN	     0x7800
+#define CONFIG_SYS_ETH_IOBASE	     0x00104000
 
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
 #define PCI_ENET0_IOADDR	0x00104000
 #define PCI_ENET0_MEMADDR	0x80000000
 #endif	/* __CONFIG_H */
diff --git a/include/configs/DASA_SIM.h b/include/configs/DASA_SIM.h
index 3ddf1bf..61704d0 100644
--- a/include/configs/DASA_SIM.h
+++ b/include/configs/DASA_SIM.h
@@ -50,7 +50,7 @@
 #undef	CONFIG_BOOTARGS
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -78,84 +78,84 @@
 #if 0 /* Does not appear to be used?!  If it is used, needs to be fixed */
 #define CONFIG_SOFT_I2C			/* Software I2C support enabled */
 #endif
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
-#define CFG_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
+#define CONFIG_SYS_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFD0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 128 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFD0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 128 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x0AA9	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x0556	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x0AA9	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x0556	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0002	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0000	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0004	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0002	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0000	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0004	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector */
@@ -177,10 +177,10 @@
 
 #define CONFIG_TULIP
 
-#define CFG_ETH_DEV_FN	     0x0000
-#define CFG_ETH_IOBASE	     0x0fff0000
-#define CFG_PCI9054_DEV_FN   0x0800
-#define CFG_PCI9054_IOBASE   0x0eff0000
+#define CONFIG_SYS_ETH_DEV_FN	     0x0000
+#define CONFIG_SYS_ETH_IOBASE	     0x0fff0000
+#define CONFIG_SYS_PCI9054_DEV_FN   0x0800
+#define CONFIG_SYS_PCI9054_IOBASE   0x0eff0000
 
 /*
  * Init Memory Controller:
diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h
index 0edd51a..daed934 100644
--- a/include/configs/DB64360.h
+++ b/include/configs/DB64360.h
@@ -132,13 +132,13 @@ if we use PCI it has its own MAC addr */
 #define CONFIG_MISC_INIT_R     /* initialize the icache L1 */
 #define CONFIG_BOARD_EARLY_INIT_F
 
-#define CFG_BOARD_NAME		"DB64360"
+#define CONFIG_SYS_BOARD_NAME		"DB64360"
 #define CONFIG_IDENT_STRING	"Marvell DB64360 (1.1)"
 
-/*#define CFG_HUSH_PARSER */
-#undef CFG_HUSH_PARSER
+/*#define CONFIG_SYS_HUSH_PARSER */
+#undef CONFIG_SYS_HUSH_PARSER
 
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 /*
  * The following defines let you select what serial you want to use
@@ -146,7 +146,7 @@ if we use PCI it has its own MAC addr */
  *
  * what to do:
  * to use the DUART, undef CONFIG_MPSC.	 If you have hacked a serial
- * cable onto the second DUART channel, change the CFG_DUART port from 1
+ * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
  * to 0 below.
  *
  * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
@@ -210,7 +210,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 /* --------------------------------------------------------------------------------------------------------------- */
 
 #define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
-#define CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 #undef	CONFIG_ALTIVEC			/* undef to disable		*/
@@ -265,74 +265,74 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 /*
  * Miscellaneous configurable options
  */
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_SPEED	40000		/* I2C speed default */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_SPEED	40000		/* I2C speed default */
 
-/* #define CFG_GT_DUAL_CPU	 also for JTAG even with one cpu */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+/* #define CONFIG_SYS_GT_DUAL_CPU	 also for JTAG even with one cpu */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-/*#define CFG_MEMTEST_START	0x00400000	 memtest works on	*/
-/*#define CFG_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
-/*#define CFG_MEMTEST_END		0x07c00000	 4 ... 124 MB in DRAM	*/
+/*#define CONFIG_SYS_MEMTEST_START	0x00400000	 memtest works on	*/
+/*#define CONFIG_SYS_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
+/*#define CONFIG_SYS_MEMTEST_END		0x07c00000	 4 ... 124 MB in DRAM	*/
 
 /*
-#define CFG_DRAM_TEST
+#define CONFIG_SYS_DRAM_TEST
  * DRAM tests
- *   CFG_DRAM_TEST - enables the following tests.
+ *   CONFIG_SYS_DRAM_TEST - enables the following tests.
  *
- *   CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
+ *   CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
  *			  Environment variable 'test_dram_data' must be
  *			  set to 'y'.
- *   CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
+ *   CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
  *			  addressable. Environment variable
  *			  'test_dram_address' must be set to 'y'.
- *   CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
+ *   CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
  *			  This test takes about 6 minutes to test 64 MB.
  *			  Environment variable 'test_dram_walk' must be
  *			  set to 'y'.
  */
-#define CFG_DRAM_TEST
-#if defined(CFG_DRAM_TEST)
-#define CFG_MEMTEST_START		0x00400000	/* memtest works on	*/
-/* #define CFG_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
-#define CFG_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
-#define CFG_DRAM_TEST_DATA
-#define CFG_DRAM_TEST_ADDRESS
-#define CFG_DRAM_TEST_WALK
-#endif /* CFG_DRAM_TEST */
+#define CONFIG_SYS_DRAM_TEST
+#if defined(CONFIG_SYS_DRAM_TEST)
+#define CONFIG_SYS_MEMTEST_START		0x00400000	/* memtest works on	*/
+/* #define CONFIG_SYS_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
+#define CONFIG_SYS_DRAM_TEST_DATA
+#define CONFIG_SYS_DRAM_TEST_ADDRESS
+#define CONFIG_SYS_DRAM_TEST_WALK
+#endif /* CONFIG_SYS_DRAM_TEST */
 
 #undef CONFIG_DISPLAY_MEMMAP		/* at the end of the bootprocess show the memory map */
-#undef CFG_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
+#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
 
-#define CFG_LOAD_ADDR		0x00400000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x00400000	/* default load address */
 
-#define CFG_HZ			1000		/* decr freq: 1ms ticks */
+#define CONFIG_SYS_HZ			1000		/* decr freq: 1ms ticks */
 /*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
-#define CFG_BUS_HZ		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
-#define CFG_BUS_CLK		CFG_BUS_HZ
+#define CONFIG_SYS_BUS_HZ		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
+#define CONFIG_SYS_BUS_CLK		CONFIG_SYS_BUS_HZ
 
-#define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
-#define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */
+#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
+#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */
 
 /*ronen - this is the Tclk (MV64360 core) */
-#define CFG_TCLK		133000000
+#define CONFIG_SYS_TCLK		133000000
 
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#define CFG_750FX_HID0		0x8000c084
-#define CFG_750FX_HID1		0x54800000
-#define CFG_750FX_HID2		0x00000000
+#define CONFIG_SYS_750FX_HID0		0x8000c084
+#define CONFIG_SYS_750FX_HID1		0x54800000
+#define CONFIG_SYS_750FX_HID2		0x00000000
 
 /*
  * Low Level Configuration Settings
@@ -345,51 +345,51 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
  */
 
 /*
- * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
+ * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
  * To an unused memory region. The stack will remain in cache until RAM
  * is initialized
 */
-#define CFG_INIT_RAM_LOCK
-#define CFG_INIT_RAM_ADDR	0x40000000 /* unused memory region */
-#define CFG_INIT_RAM_END	0x1000
-#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000 /* unused memory region */
+#define CONFIG_SYS_INIT_RAM_END	0x1000
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 #define RELOCATE_INTERNAL_RAM_ADDR
 #ifdef RELOCATE_INTERNAL_RAM_ADDR
-	#define CFG_INTERNAL_RAM_ADDR	0xf8000000
+	#define CONFIG_SYS_INTERNAL_RAM_ADDR	0xf8000000
 #endif
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
 /* Dummies for BAT 4-7 */
-#define CFG_SDRAM1_BASE		0x10000000	/* each 256 MByte */
-#define CFG_SDRAM2_BASE		0x20000000
-#define CFG_SDRAM3_BASE		0x30000000
-#define CFG_SDRAM4_BASE		0x40000000
-#define CFG_FLASH_BASE			0xfff00000
+#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* each 256 MByte */
+#define CONFIG_SYS_SDRAM2_BASE		0x20000000
+#define CONFIG_SYS_SDRAM3_BASE		0x30000000
+#define CONFIG_SYS_SDRAM4_BASE		0x40000000
+#define CONFIG_SYS_FLASH_BASE			0xfff00000
 
-#define CFG_DFL_BOOTCS_BASE	0xff800000
+#define CONFIG_SYS_DFL_BOOTCS_BASE	0xff800000
 #define CONFIG_VERY_BIG_RAM		/* we will use up to 256M memory for cause we are short of BATS*/
 
 #define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
 #define UART_BASE_BOOTM	      0xfbb00000 /* in order to be sync with the kernel parameters. */
 #define PCI0_IO_BASE_BOOTM    0xfd000000
 
-#define CFG_RESET_ADDRESS		0xfff00100
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MONITOR_BASE		CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+#define CONFIG_SYS_RESET_ADDRESS		0xfff00100
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
 
 /* areas to map different things with the GT in physical space */
-#define CFG_DRAM_BANKS		4
+#define CONFIG_SYS_DRAM_BANKS		4
 
 /* What to put in the bats. */
-#define CFG_MISC_REGION_BASE	0xf0000000
+#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
 
 /* Peripheral Device section */
 
@@ -403,30 +403,30 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 /* Data flash on external device module		    */
 /* Boot flash on external device module		    */
 /*******************************************************/
-#define CFG_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
-#define	 CFG_DB64360_RESET_ADDR 0x14000000				/* After power on Reset the DB64360 is here */
+#define CONFIG_SYS_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
+#define	 CONFIG_SYS_DB64360_RESET_ADDR 0x14000000				/* After power on Reset the DB64360 is here */
 
 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-#define CFG_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
-#define CFG_DEV_BASE		0xfc000000				/* GT Devices CS start here */
-
-#define CFG_DEV0_SPACE		CFG_DEV_BASE				/* DEV_CS0 device modul sram */
-#define CFG_DEV1_SPACE		(CFG_DEV0_SPACE + CFG_DEV0_SIZE)	/* DEV_CS1 device modul real time clock (rtc) */
-#define CFG_DEV2_SPACE		(CFG_DEV1_SPACE + CFG_DEV1_SIZE)	/* DEV_CS2 device modul doubel uart (duart) */
-#define CFG_DEV3_SPACE		(CFG_DEV2_SPACE + CFG_DEV2_SIZE)	/* DEV_CS3 device modul large flash */
-
-#define CFG_DEV0_SIZE		 _8M					/* db64360 sram	 @ 0xfc00.0000 */
-#define CFG_DEV1_SIZE		 _8M					/* db64360 rtc	 @ 0xfc80.0000 */
-#define CFG_DEV2_SIZE		_16M					/* db64360 duart @ 0xfd00.0000 */
-#define CFG_DEV3_SIZE		_16M					/* db64360 flash @ 0xfe00.0000 */
+#define CONFIG_SYS_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
+#define CONFIG_SYS_DEV_BASE		0xfc000000				/* GT Devices CS start here */
+
+#define CONFIG_SYS_DEV0_SPACE		CONFIG_SYS_DEV_BASE				/* DEV_CS0 device modul sram */
+#define CONFIG_SYS_DEV1_SPACE		(CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)	/* DEV_CS1 device modul real time clock (rtc) */
+#define CONFIG_SYS_DEV2_SPACE		(CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)	/* DEV_CS2 device modul doubel uart (duart) */
+#define CONFIG_SYS_DEV3_SPACE		(CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)	/* DEV_CS3 device modul large flash */
+
+#define CONFIG_SYS_DEV0_SIZE		 _8M					/* db64360 sram	 @ 0xfc00.0000 */
+#define CONFIG_SYS_DEV1_SIZE		 _8M					/* db64360 rtc	 @ 0xfc80.0000 */
+#define CONFIG_SYS_DEV2_SIZE		_16M					/* db64360 duart @ 0xfd00.0000 */
+#define CONFIG_SYS_DEV3_SIZE		_16M					/* db64360 flash @ 0xfe00.0000 */
 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
 
 /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
-#define CFG_DEV0_PAR		0x8FEFFFFF				/* 32Bit  sram */
-#define CFG_DEV1_PAR		0x8FCFFFFF				/* 8Bit	 rtc */
-#define CFG_DEV2_PAR		0x8FCFFFFF				/* 8Bit duart */
-#define CFG_8BIT_BOOT_PAR	0x8FCFFFFF				/* 8Bit flash */
-#define CFG_32BIT_BOOT_PAR	0x8FEFFFFF				/* 32Bit flash */
+#define CONFIG_SYS_DEV0_PAR		0x8FEFFFFF				/* 32Bit  sram */
+#define CONFIG_SYS_DEV1_PAR		0x8FCFFFFF				/* 8Bit	 rtc */
+#define CONFIG_SYS_DEV2_PAR		0x8FCFFFFF				/* 8Bit duart */
+#define CONFIG_SYS_8BIT_BOOT_PAR	0x8FCFFFFF				/* 8Bit flash */
+#define CONFIG_SYS_32BIT_BOOT_PAR	0x8FEFFFFF				/* 32Bit flash */
 
 	/*   c	  4    a      8	    2	  4    1      c		*/
 	/* 33 22|2222|22 22|111 1|11 11|1 1  |	  |		*/
@@ -436,28 +436,28 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 
 
 /* ronen - update MPP Control MV64360*/
-#define CFG_MPP_CONTROL_0	0x02222222
-#define CFG_MPP_CONTROL_1	0x11333011
-#define CFG_MPP_CONTROL_2	0x40431111
-#define CFG_MPP_CONTROL_3	0x00000044
+#define CONFIG_SYS_MPP_CONTROL_0	0x02222222
+#define CONFIG_SYS_MPP_CONTROL_1	0x11333011
+#define CONFIG_SYS_MPP_CONTROL_2	0x40431111
+#define CONFIG_SYS_MPP_CONTROL_3	0x00000044
 
-/*# define CFG_SERIAL_PORT_MUX	0x00000102	 0=hiZ	1=MPSC0 2=ETH 0 and 2 RMII */
+/*# define CONFIG_SYS_SERIAL_PORT_MUX	0x00000102	 0=hiZ	1=MPSC0 2=ETH 0 and 2 RMII */
 
 
-# define CFG_GPP_LEVEL_CONTROL	0x2c600000	/* 1111 1001 0000 1111 1100 0000 0000 0000*/
+# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x2c600000	/* 1111 1001 0000 1111 1100 0000 0000 0000*/
 							/* gpp[31]		gpp[30]		gpp[29]		gpp[28] */
 				/* gpp[27]			gpp[24]*/
 							/* gpp[19:14] */
 
 /* setup new config_value for MV64360 DDR-RAM !! */
-# define CFG_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
+# define CONFIG_SYS_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
 
-#define CFG_DUART_IO		CFG_DEV2_SPACE
-#define CFG_DUART_CHAN		1		/* channel to use for console */
-#define CFG_INIT_CHAN1
-#define CFG_INIT_CHAN2
+#define CONFIG_SYS_DUART_IO		CONFIG_SYS_DEV2_SPACE
+#define CONFIG_SYS_DUART_CHAN		1		/* channel to use for console */
+#define CONFIG_SYS_INIT_CHAN1
+#define CONFIG_SYS_INIT_CHAN2
 
-#define SRAM_BASE		CFG_DEV0_SPACE
+#define SRAM_BASE		CONFIG_SYS_DEV0_SPACE
 #define SRAM_SIZE		0x00100000		/* 1 MB of sram */
 
 
@@ -476,29 +476,29 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 #define CONFIG_EEPRO100			/* ronen - Support for Intel 82557/82559/82559ER chips */
 
 /* PCI MEMORY MAP section */
-#define CFG_PCI0_MEM_BASE	0x80000000
-#define CFG_PCI0_MEM_SIZE	_128M
-#define CFG_PCI1_MEM_BASE	0x88000000
-#define CFG_PCI1_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
 
-#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
-#define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
+#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
+#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
 
 /* PCI I/O MAP section */
-#define CFG_PCI0_IO_BASE	0xfa000000
-#define CFG_PCI0_IO_SIZE	_16M
-#define CFG_PCI1_IO_BASE	0xfb000000
-#define CFG_PCI1_IO_SIZE	_16M
+#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
+#define CONFIG_SYS_PCI0_IO_SIZE	_16M
+#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
+#define CONFIG_SYS_PCI1_IO_SIZE	_16M
 
-#define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
-#define CFG_PCI0_IO_SPACE_PCI	(CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
-#define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
-#define CFG_PCI1_IO_SPACE_PCI	(CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
+#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
+#define CONFIG_SYS_PCI0_IO_SPACE_PCI	(CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
+#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
+#define CONFIG_SYS_PCI1_IO_SPACE_PCI	(CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
 
 #if defined (CONFIG_750CX)
-#define CFG_PCI_IDSEL 0x0
+#define CONFIG_SYS_PCI_IDSEL 0x0
 #else
-#define CFG_PCI_IDSEL 0x30
+#define CONFIG_SYS_PCI_IDSEL 0x30
 #endif
 /*----------------------------------------------------------------------
  * Initial BAT mappings
@@ -510,28 +510,28 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
  */
 
 /* SDRAM */
-#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT0U CFG_IBAT0U
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
 
 /* init ram */
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 
 /* PCI0, PCI1 in one BAT */
-#define CFG_IBAT2L BATL_NO_ACCESS
-#define CFG_IBAT2U CFG_DBAT2U
-#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
+#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* GT regs, bootrom, all the devices, PCI I/O */
-#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 
 /* I2C addresses for the two DIMM SPD chips */
 #define DIMM0_I2C_ADDR	0x56
@@ -542,35 +542,35 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
 
-#define CFG_EXTRA_FLASH_DEVICE	DEVICE3 /* extra flash at device 3 */
-#define CFG_EXTRA_FLASH_WIDTH	4	/* 32 bit */
-#define CFG_BOOT_FLASH_WIDTH	1	/* 8 bit */
+#define CONFIG_SYS_EXTRA_FLASH_DEVICE	DEVICE3 /* extra flash at device 3 */
+#define CONFIG_SYS_EXTRA_FLASH_WIDTH	4	/* 32 bit */
+#define CONFIG_SYS_BOOT_FLASH_WIDTH	1	/* 8 bit */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
-#define CFG_FLASH_CFI		1
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
+#define CONFIG_SYS_FLASH_CFI		1
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #define CONFIG_ENV_ADDR	      0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
-/* #define CONFIG_ENV_ADDR	   (CFG_FLASH_BASE+CFG_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
+/* #define CONFIG_ENV_ADDR	   (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -578,7 +578,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
  * look in include/mpc74xx.h for the defines used here
  */
 
-#define CFG_L2
+#define CONFIG_SYS_L2
 
 
 #if defined (CONFIG_750CX) || defined (CONFIG_750FX)
@@ -602,6 +602,6 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 #define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02		/* Software reboot		    */
 
-#define CFG_BOARD_ASM_INIT	1
+#define CONFIG_SYS_BOARD_ASM_INIT	1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h
index 30615a4..604fd45 100644
--- a/include/configs/DB64460.h
+++ b/include/configs/DB64460.h
@@ -70,13 +70,13 @@
 #define CONFIG_MISC_INIT_R     /* initialize the icache L1 */
 #define CONFIG_BOARD_EARLY_INIT_F
 
-#define CFG_BOARD_NAME		"DB64460"
+#define CONFIG_SYS_BOARD_NAME		"DB64460"
 #define CONFIG_IDENT_STRING	"Marvell DB64460 (1.0)"
 
-/*#define CFG_HUSH_PARSER */
-#undef CFG_HUSH_PARSER
+/*#define CONFIG_SYS_HUSH_PARSER */
+#undef CONFIG_SYS_HUSH_PARSER
 
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 /*
  * The following defines let you select what serial you want to use
@@ -84,7 +84,7 @@
  *
  * what to do:
  * to use the DUART, undef CONFIG_MPSC.	 If you have hacked a serial
- * cable onto the second DUART channel, change the CFG_DUART port from 1
+ * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
  * to 0 below.
  *
  * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
@@ -148,7 +148,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 /* --------------------------------------------------------------------------------------------------------------- */
 
 #define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
-#define CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 #undef	CONFIG_ALTIVEC			/* undef to disable		*/
@@ -203,74 +203,74 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 /*
  * Miscellaneous configurable options
  */
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_SPEED	40000		/* I2C speed default */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_SPEED	40000		/* I2C speed default */
 
-/* #define CFG_GT_DUAL_CPU	 also for JTAG even with one cpu */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+/* #define CONFIG_SYS_GT_DUAL_CPU	 also for JTAG even with one cpu */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-/*#define CFG_MEMTEST_START	0x00400000	 memtest works on	*/
-/*#define CFG_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
-/*#define CFG_MEMTEST_END		0x07c00000	 4 ... 124 MB in DRAM	*/
+/*#define CONFIG_SYS_MEMTEST_START	0x00400000	 memtest works on	*/
+/*#define CONFIG_SYS_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
+/*#define CONFIG_SYS_MEMTEST_END		0x07c00000	 4 ... 124 MB in DRAM	*/
 
 /*
-#define CFG_DRAM_TEST
+#define CONFIG_SYS_DRAM_TEST
  * DRAM tests
- *   CFG_DRAM_TEST - enables the following tests.
+ *   CONFIG_SYS_DRAM_TEST - enables the following tests.
  *
- *   CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
+ *   CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
  *			  Environment variable 'test_dram_data' must be
  *			  set to 'y'.
- *   CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
+ *   CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
  *			  addressable. Environment variable
  *			  'test_dram_address' must be set to 'y'.
- *   CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
+ *   CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
  *			  This test takes about 6 minutes to test 64 MB.
  *			  Environment variable 'test_dram_walk' must be
  *			  set to 'y'.
  */
-#define CFG_DRAM_TEST
-#if defined(CFG_DRAM_TEST)
-#define CFG_MEMTEST_START		0x00400000	/* memtest works on	*/
-/* #define CFG_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
-#define CFG_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
-#define CFG_DRAM_TEST_DATA
-#define CFG_DRAM_TEST_ADDRESS
-#define CFG_DRAM_TEST_WALK
-#endif /* CFG_DRAM_TEST */
+#define CONFIG_SYS_DRAM_TEST
+#if defined(CONFIG_SYS_DRAM_TEST)
+#define CONFIG_SYS_MEMTEST_START		0x00400000	/* memtest works on	*/
+/* #define CONFIG_SYS_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
+#define CONFIG_SYS_DRAM_TEST_DATA
+#define CONFIG_SYS_DRAM_TEST_ADDRESS
+#define CONFIG_SYS_DRAM_TEST_WALK
+#endif /* CONFIG_SYS_DRAM_TEST */
 
 #undef CONFIG_DISPLAY_MEMMAP		/* at the end of the bootprocess show the memory map */
-#undef CFG_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
+#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
 
-#define CFG_LOAD_ADDR		0x00400000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x00400000	/* default load address */
 
-#define CFG_HZ			1000		/* decr freq: 1ms ticks */
+#define CONFIG_SYS_HZ			1000		/* decr freq: 1ms ticks */
 /*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
-#define CFG_BUS_HZ		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
-#define CFG_BUS_CLK		CFG_BUS_HZ
+#define CONFIG_SYS_BUS_HZ		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
+#define CONFIG_SYS_BUS_CLK		CONFIG_SYS_BUS_HZ
 
-#define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
-#define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */
+#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
+#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */
 
 /*ronen - this is the Tclk (MV64460 core) */
-#define CFG_TCLK		133000000
+#define CONFIG_SYS_TCLK		133000000
 
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#define CFG_750FX_HID0		0x8000c084
-#define CFG_750FX_HID1		0x54800000
-#define CFG_750FX_HID2		0x00000000
+#define CONFIG_SYS_750FX_HID0		0x8000c084
+#define CONFIG_SYS_750FX_HID1		0x54800000
+#define CONFIG_SYS_750FX_HID2		0x00000000
 
 /*
  * Low Level Configuration Settings
@@ -283,51 +283,51 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
  */
 
 /*
- * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
+ * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
  * To an unused memory region. The stack will remain in cache until RAM
  * is initialized
 */
-#define CFG_INIT_RAM_LOCK
-#define CFG_INIT_RAM_ADDR	0x40000000 /* unused memory region */
-#define CFG_INIT_RAM_END	0x1000
-#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000 /* unused memory region */
+#define CONFIG_SYS_INIT_RAM_END	0x1000
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 #define RELOCATE_INTERNAL_RAM_ADDR
 #ifdef RELOCATE_INTERNAL_RAM_ADDR
-	#define CFG_INTERNAL_RAM_ADDR	0xf8000000
+	#define CONFIG_SYS_INTERNAL_RAM_ADDR	0xf8000000
 #endif
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
 /* Dummies for BAT 4-7 */
-#define CFG_SDRAM1_BASE		0x10000000	/* each 256 MByte */
-#define CFG_SDRAM2_BASE		0x20000000
-#define CFG_SDRAM3_BASE		0x30000000
-#define CFG_SDRAM4_BASE		0x40000000
-#define CFG_FLASH_BASE			0xfff00000
+#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* each 256 MByte */
+#define CONFIG_SYS_SDRAM2_BASE		0x20000000
+#define CONFIG_SYS_SDRAM3_BASE		0x30000000
+#define CONFIG_SYS_SDRAM4_BASE		0x40000000
+#define CONFIG_SYS_FLASH_BASE			0xfff00000
 
-#define CFG_DFL_BOOTCS_BASE	0xff800000
+#define CONFIG_SYS_DFL_BOOTCS_BASE	0xff800000
 #define CONFIG_VERY_BIG_RAM		/* we will use up to 256M memory for cause we are short of BATS*/
 
 #define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
 #define UART_BASE_BOOTM	      0xfbb00000 /* in order to be sync with the kernel parameters. */
 #define PCI0_IO_BASE_BOOTM    0xfd000000
 
-#define CFG_RESET_ADDRESS		0xfff00100
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MONITOR_BASE		CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+#define CONFIG_SYS_RESET_ADDRESS		0xfff00100
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
 
 /* areas to map different things with the GT in physical space */
-#define CFG_DRAM_BANKS		4
+#define CONFIG_SYS_DRAM_BANKS		4
 
 /* What to put in the bats. */
-#define CFG_MISC_REGION_BASE	0xf0000000
+#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
 
 /* Peripheral Device section */
 
@@ -341,30 +341,30 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 /* Data flash on external device module		    */
 /* Boot flash on external device module		    */
 /*******************************************************/
-#define CFG_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
-#define	 CFG_DB64460_RESET_ADDR 0x14000000				/* After power on Reset the DB64460 is here */
+#define CONFIG_SYS_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
+#define	 CONFIG_SYS_DB64460_RESET_ADDR 0x14000000				/* After power on Reset the DB64460 is here */
 
 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-#define CFG_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
-#define CFG_DEV_BASE		0xfc000000				/* GT Devices CS start here */
-
-#define CFG_DEV0_SPACE		CFG_DEV_BASE				/* DEV_CS0 device modul sram */
-#define CFG_DEV1_SPACE		(CFG_DEV0_SPACE + CFG_DEV0_SIZE)	/* DEV_CS1 device modul real time clock (rtc) */
-#define CFG_DEV2_SPACE		(CFG_DEV1_SPACE + CFG_DEV1_SIZE)	/* DEV_CS2 device modul doubel uart (duart) */
-#define CFG_DEV3_SPACE		(CFG_DEV2_SPACE + CFG_DEV2_SIZE)	/* DEV_CS3 device modul large flash */
-
-#define CFG_DEV0_SIZE		 _8M					/* db64460 sram	 @ 0xfc00.0000 */
-#define CFG_DEV1_SIZE		 _8M					/* db64460 rtc	 @ 0xfc80.0000 */
-#define CFG_DEV2_SIZE		_16M					/* db64460 duart @ 0xfd00.0000 */
-#define CFG_DEV3_SIZE		_16M					/* db64460 flash @ 0xfe00.0000 */
+#define CONFIG_SYS_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
+#define CONFIG_SYS_DEV_BASE		0xfc000000				/* GT Devices CS start here */
+
+#define CONFIG_SYS_DEV0_SPACE		CONFIG_SYS_DEV_BASE				/* DEV_CS0 device modul sram */
+#define CONFIG_SYS_DEV1_SPACE		(CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)	/* DEV_CS1 device modul real time clock (rtc) */
+#define CONFIG_SYS_DEV2_SPACE		(CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)	/* DEV_CS2 device modul doubel uart (duart) */
+#define CONFIG_SYS_DEV3_SPACE		(CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)	/* DEV_CS3 device modul large flash */
+
+#define CONFIG_SYS_DEV0_SIZE		 _8M					/* db64460 sram	 @ 0xfc00.0000 */
+#define CONFIG_SYS_DEV1_SIZE		 _8M					/* db64460 rtc	 @ 0xfc80.0000 */
+#define CONFIG_SYS_DEV2_SIZE		_16M					/* db64460 duart @ 0xfd00.0000 */
+#define CONFIG_SYS_DEV3_SIZE		_16M					/* db64460 flash @ 0xfe00.0000 */
 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
 
 /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
-#define CFG_DEV0_PAR		0x8FEFFFFF				/* 32Bit  sram */
-#define CFG_DEV1_PAR		0x8FCFFFFF				/* 8Bit	 rtc */
-#define CFG_DEV2_PAR		0x8FCFFFFF				/* 8Bit duart */
-#define CFG_8BIT_BOOT_PAR	0x8FCFFFFF				/* 8Bit flash */
-#define CFG_32BIT_BOOT_PAR	0x8FEFFFFF				/* 32Bit flash */
+#define CONFIG_SYS_DEV0_PAR		0x8FEFFFFF				/* 32Bit  sram */
+#define CONFIG_SYS_DEV1_PAR		0x8FCFFFFF				/* 8Bit	 rtc */
+#define CONFIG_SYS_DEV2_PAR		0x8FCFFFFF				/* 8Bit duart */
+#define CONFIG_SYS_8BIT_BOOT_PAR	0x8FCFFFFF				/* 8Bit flash */
+#define CONFIG_SYS_32BIT_BOOT_PAR	0x8FEFFFFF				/* 32Bit flash */
 
 	/*   c	  4    a      8	    2	  4    1      c		*/
 	/* 33 22|2222|22 22|111 1|11 11|1 1  |	  |		*/
@@ -374,28 +374,28 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 
 
 /* ronen - update MPP Control MV64460*/
-#define CFG_MPP_CONTROL_0	0x02222222
-#define CFG_MPP_CONTROL_1	0x11333011
-#define CFG_MPP_CONTROL_2	0x40431111
-#define CFG_MPP_CONTROL_3	0x00000044
+#define CONFIG_SYS_MPP_CONTROL_0	0x02222222
+#define CONFIG_SYS_MPP_CONTROL_1	0x11333011
+#define CONFIG_SYS_MPP_CONTROL_2	0x40431111
+#define CONFIG_SYS_MPP_CONTROL_3	0x00000044
 
-/*# define CFG_SERIAL_PORT_MUX	0x00000102	 0=hiZ	1=MPSC0 2=ETH 0 and 2 RMII */
+/*# define CONFIG_SYS_SERIAL_PORT_MUX	0x00000102	 0=hiZ	1=MPSC0 2=ETH 0 and 2 RMII */
 
 
-# define CFG_GPP_LEVEL_CONTROL	0x2c600000	/* 1111 1001 0000 1111 1100 0000 0000 0000*/
+# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x2c600000	/* 1111 1001 0000 1111 1100 0000 0000 0000*/
 							/* gpp[31]		gpp[30]		gpp[29]		gpp[28] */
 				/* gpp[27]			gpp[24]*/
 							/* gpp[19:14] */
 
 /* setup new config_value for MV64460 DDR-RAM !! */
-# define CFG_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
+# define CONFIG_SYS_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
 
-#define CFG_DUART_IO		CFG_DEV2_SPACE
-#define CFG_DUART_CHAN		1		/* channel to use for console */
-#define CFG_INIT_CHAN1
-#define CFG_INIT_CHAN2
+#define CONFIG_SYS_DUART_IO		CONFIG_SYS_DEV2_SPACE
+#define CONFIG_SYS_DUART_CHAN		1		/* channel to use for console */
+#define CONFIG_SYS_INIT_CHAN1
+#define CONFIG_SYS_INIT_CHAN2
 
-#define SRAM_BASE		CFG_DEV0_SPACE
+#define SRAM_BASE		CONFIG_SYS_DEV0_SPACE
 #define SRAM_SIZE		0x00100000		/* 1 MB of sram */
 
 
@@ -414,29 +414,29 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 #define CONFIG_EEPRO100			/* ronen - Support for Intel 82557/82559/82559ER chips */
 
 /* PCI MEMORY MAP section */
-#define CFG_PCI0_MEM_BASE	0x80000000
-#define CFG_PCI0_MEM_SIZE	_128M
-#define CFG_PCI1_MEM_BASE	0x88000000
-#define CFG_PCI1_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
 
-#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
-#define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
+#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
+#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
 
 /* PCI I/O MAP section */
-#define CFG_PCI0_IO_BASE	0xfa000000
-#define CFG_PCI0_IO_SIZE	_16M
-#define CFG_PCI1_IO_BASE	0xfb000000
-#define CFG_PCI1_IO_SIZE	_16M
+#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
+#define CONFIG_SYS_PCI0_IO_SIZE	_16M
+#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
+#define CONFIG_SYS_PCI1_IO_SIZE	_16M
 
-#define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
-#define CFG_PCI0_IO_SPACE_PCI	(CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
-#define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
-#define CFG_PCI1_IO_SPACE_PCI	(CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
+#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
+#define CONFIG_SYS_PCI0_IO_SPACE_PCI	(CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
+#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
+#define CONFIG_SYS_PCI1_IO_SPACE_PCI	(CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
 
 #if defined (CONFIG_750CX)
-#define CFG_PCI_IDSEL 0x0
+#define CONFIG_SYS_PCI_IDSEL 0x0
 #else
-#define CFG_PCI_IDSEL 0x30
+#define CONFIG_SYS_PCI_IDSEL 0x30
 #endif
 /*----------------------------------------------------------------------
  * Initial BAT mappings
@@ -448,28 +448,28 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
  */
 
 /* SDRAM */
-#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT0U CFG_IBAT0U
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
 
 /* init ram */
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 
 /* PCI0, PCI1 in one BAT */
-#define CFG_IBAT2L BATL_NO_ACCESS
-#define CFG_IBAT2U CFG_DBAT2U
-#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
+#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* GT regs, bootrom, all the devices, PCI I/O */
-#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 
 /* I2C addresses for the two DIMM SPD chips */
 #define DIMM0_I2C_ADDR	0x56
@@ -480,35 +480,35 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
 
-#define CFG_EXTRA_FLASH_DEVICE	DEVICE3 /* extra flash at device 3 */
-#define CFG_EXTRA_FLASH_WIDTH	4	/* 32 bit */
-#define CFG_BOOT_FLASH_WIDTH	1	/* 8 bit */
+#define CONFIG_SYS_EXTRA_FLASH_DEVICE	DEVICE3 /* extra flash at device 3 */
+#define CONFIG_SYS_EXTRA_FLASH_WIDTH	4	/* 32 bit */
+#define CONFIG_SYS_BOOT_FLASH_WIDTH	1	/* 8 bit */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
-#define CFG_FLASH_CFI		1
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
+#define CONFIG_SYS_FLASH_CFI		1
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #define CONFIG_ENV_ADDR	      0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
-/* #define CONFIG_ENV_ADDR	   (CFG_FLASH_BASE+CFG_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
+/* #define CONFIG_ENV_ADDR	   (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -516,7 +516,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
  * look in include/mpc74xx.h for the defines used here
  */
 
-#define CFG_L2
+#define CONFIG_SYS_L2
 
 
 #if defined (CONFIG_750CX) || defined (CONFIG_750FX)
@@ -540,6 +540,6 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 #define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02		/* Software reboot		    */
 
-#define CFG_BOARD_ASM_INIT	1
+#define CONFIG_SYS_BOARD_ASM_INIT	1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h
index 3e1fc0a..6fdc566 100644
--- a/include/configs/DK1C20.h
+++ b/include/configs/DK1C20.h
@@ -40,7 +40,7 @@
 #elif	defined(CONFIG_NIOS_STANDARD_32)
 #include <configs/DK1C20_standard_32.h>
 #else
-#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
+#error *** CONFIG_SYS_ERROR: you have to setup right NIOS CPU configuration
 #endif
 
 /*------------------------------------------------------------------------
@@ -48,26 +48,26 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_NIOS		1		/* NIOS-32 core		*/
 #define	CONFIG_DK1C20		1		/* Cyclone DK-1C20 board*/
-#define CONFIG_SYS_CLK_FREQ	CFG_NIOS_CPU_CLK/* 50 MHz core clock	*/
-#define	CFG_HZ			1000		/* 1 msec time tick	*/
-#undef  CFG_CLKS_IN_HZ
+#define CONFIG_SYS_CLK_FREQ	CONFIG_SYS_NIOS_CPU_CLK/* 50 MHz core clock	*/
+#define	CONFIG_SYS_HZ			1000		/* 1 msec time tick	*/
+#undef  CONFIG_SYS_CLKS_IN_HZ
 #define	CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
 
 /*------------------------------------------------------------------------
  * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_SDRAM_SIZE != 0)
+#if	(CONFIG_SYS_NIOS_CPU_SDRAM_SIZE != 0)
 
-#define CFG_SDRAM_BASE		CFG_NIOS_CPU_SDRAM_BASE
-#define CFG_SDRAM_SIZE		CFG_NIOS_CPU_SDRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_NIOS_CPU_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		CONFIG_SYS_NIOS_CPU_SDRAM_SIZE
 
 #else
-#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
+#error *** CONFIG_SYS_ERROR: you have to setup any SDRAM in NIOS CPU config
 #endif
 
-#define CFG_SRAM_BASE		CFG_NIOS_CPU_SRAM_BASE
-#define CFG_SRAM_SIZE		CFG_NIOS_CPU_SRAM_SIZE
-#define CFG_VECT_BASE		CFG_NIOS_CPU_VEC_BASE
+#define CONFIG_SYS_SRAM_BASE		CONFIG_SYS_NIOS_CPU_SRAM_BASE
+#define CONFIG_SYS_SRAM_SIZE		CONFIG_SYS_NIOS_CPU_SRAM_SIZE
+#define CONFIG_SYS_VECT_BASE		CONFIG_SYS_NIOS_CPU_VEC_BASE
 
 /*------------------------------------------------------------------------
  * MEMORY ORGANIZATION - For the most part, you can put things pretty
@@ -80,39 +80,39 @@
  *	-Global data is placed below the heap.
  *	-The stack is placed below global data (&grows down).
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
-#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
 
 /*------------------------------------------------------------------------
  * FLASH (AM29LV065D)
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)
+#if	(CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0)
 
-#define CFG_FLASH_BASE		CFG_NIOS_CPU_FLASH_BASE
-#define CFG_FLASH_SIZE		CFG_NIOS_CPU_FLASH_SIZE
-#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
-#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
-#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
-#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
-#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_NIOS_CPU_FLASH_BASE
+#define CONFIG_SYS_FLASH_SIZE		CONFIG_SYS_NIOS_CPU_FLASH_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
 
 #else
-#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
+#error *** CONFIG_SYS_ERROR: you have to setup any Flash memory in NIOS CPU config
 #endif
 
 /*------------------------------------------------------------------------
  * ENVIRONMENT
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)
+#if	(CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0)
 
 #define	CONFIG_ENV_IS_IN_FLASH	1		/* Environment in flash */
-#define CONFIG_ENV_ADDR		CFG_FLASH_BASE	/* Mem addr of env	*/
+#define CONFIG_ENV_ADDR		CONFIG_SYS_FLASH_BASE	/* Mem addr of env	*/
 #define CONFIG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
 #define CONFIG_ENV_OVERWRITE			/* Serial/eth change Ok */
 
@@ -123,120 +123,120 @@
 /*------------------------------------------------------------------------
  * CONSOLE
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_UART_NUMS != 0)
+#if	(CONFIG_SYS_NIOS_CPU_UART_NUMS != 0)
 
-#define CFG_NIOS_CONSOLE	CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
+#define CONFIG_SYS_NIOS_CONSOLE	CONFIG_SYS_NIOS_CPU_UART0 /* 1st UART is Cons. */
 
-#if	(CFG_NIOS_CPU_UART0_BR != 0)
-#define CFG_NIOS_FIXEDBAUD	1		   /* Baudrate is fixed	*/
-#define CONFIG_BAUDRATE		CFG_NIOS_CPU_UART0_BR
+#if	(CONFIG_SYS_NIOS_CPU_UART0_BR != 0)
+#define CONFIG_SYS_NIOS_FIXEDBAUD	1		   /* Baudrate is fixed	*/
+#define CONFIG_BAUDRATE		CONFIG_SYS_NIOS_CPU_UART0_BR
 #else
-#undef	CFG_NIOS_FIXEDBAUD
+#undef	CONFIG_SYS_NIOS_FIXEDBAUD
 #define CONFIG_BAUDRATE		115200
 #endif
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #else
-#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
+#error *** CONFIG_SYS_ERROR: you have to setup at least one UART in NIOS CPU config
 #endif
 
 /*------------------------------------------------------------------------
  * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc  PIT,
  * so an avalon bus timer is required.
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_TIMER_NUMS != 0)
+#if	(CONFIG_SYS_NIOS_CPU_TIMER_NUMS != 0)
 
-#if	(CFG_NIOS_CPU_TICK_TIMER == 0)
+#if	(CONFIG_SYS_NIOS_CPU_TICK_TIMER == 0)
 
-#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick	*/
-#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER0_IRQ
+#define CONFIG_SYS_NIOS_TMRBASE	CONFIG_SYS_NIOS_CPU_TIMER0 /* TIMER0 as tick	*/
+#define CONFIG_SYS_NIOS_TMRIRQ		CONFIG_SYS_NIOS_CPU_TIMER0_IRQ
 
-#if	(CFG_NIOS_CPU_TIMER0_FP == 1)		    /* fixed period */
+#if	(CONFIG_SYS_NIOS_CPU_TIMER0_FP == 1)		    /* fixed period */
 
-#if	(CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
-#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
+#if	(CONFIG_SYS_NIOS_CPU_TIMER0_PER >= CONFIG_SYS_HZ)
+#define CONFIG_SYS_NIOS_TMRMS		(CONFIG_SYS_NIOS_CPU_TIMER0_PER / CONFIG_SYS_HZ)
 #else
-#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
+#error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ
 #endif
 
-#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */
+#undef	CONFIG_SYS_NIOS_TMRCNT	/* no preloadable counter value */
 
-#elif	(CFG_NIOS_CPU_TIMER0_FP == 0)		    /* variable period */
+#elif	(CONFIG_SYS_NIOS_CPU_TIMER0_FP == 0)		    /* variable period */
 
-#if	(CFG_HZ <= 1000)
-#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
+#if	(CONFIG_SYS_HZ <= 1000)
+#define CONFIG_SYS_NIOS_TMRMS		(1000 / CONFIG_SYS_HZ)
 #else
-#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
+#error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000
 #endif
 
-#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)
+#define	CONFIG_SYS_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ)
 
 #else
-#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
+#error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER0_FP correct
 #endif
 
-#elif	(CFG_NIOS_CPU_TICK_TIMER == 1)
+#elif	(CONFIG_SYS_NIOS_CPU_TICK_TIMER == 1)
 
-#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick	*/
-#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER1_IRQ
+#define CONFIG_SYS_NIOS_TMRBASE	CONFIG_SYS_NIOS_CPU_TIMER1 /* TIMER1 as tick	*/
+#define CONFIG_SYS_NIOS_TMRIRQ		CONFIG_SYS_NIOS_CPU_TIMER1_IRQ
 
-#if	(CFG_NIOS_CPU_TIMER1_FP == 1)		    /* fixed period */
+#if	(CONFIG_SYS_NIOS_CPU_TIMER1_FP == 1)		    /* fixed period */
 
-#if	(CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
-#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
+#if	(CONFIG_SYS_NIOS_CPU_TIMER1_PER >= CONFIG_SYS_HZ)
+#define CONFIG_SYS_NIOS_TMRMS		(CONFIG_SYS_NIOS_CPU_TIMER1_PER / CONFIG_SYS_HZ)
 #else
-#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
+#error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ
 #endif
 
-#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */
+#undef	CONFIG_SYS_NIOS_TMRCNT	/* no preloadable counter value */
 
-#elif	(CFG_NIOS_CPU_TIMER1_FP == 0)		    /* variable period */
+#elif	(CONFIG_SYS_NIOS_CPU_TIMER1_FP == 0)		    /* variable period */
 
-#if	(CFG_HZ <= 1000)
-#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
+#if	(CONFIG_SYS_HZ <= 1000)
+#define CONFIG_SYS_NIOS_TMRMS		(1000 / CONFIG_SYS_HZ)
 #else
-#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
+#error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000
 #endif
 
-#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)
+#define	CONFIG_SYS_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ)
 
 #else
-#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
+#error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER1_FP correct
 #endif
 
-#endif	/* CFG_NIOS_CPU_TICK_TIMER */
+#endif	/* CONFIG_SYS_NIOS_CPU_TICK_TIMER */
 
 #else
-#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
+#error *** CONFIG_SYS_ERROR: you have to setup at least one TIMER in NIOS CPU config
 #endif
 
 /*------------------------------------------------------------------------
  * Ethernet
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_LAN_NUMS == 1)
+#if	(CONFIG_SYS_NIOS_CPU_LAN_NUMS == 1)
 
-#if	(CFG_NIOS_CPU_LAN0_TYPE == 0)		/* LAN91C111		*/
+#if	(CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 0)		/* LAN91C111		*/
 
 #define	CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
 #undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
-#define	CONFIG_SMC91111_BASE	(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
+#define	CONFIG_SMC91111_BASE	(CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS)
 
-#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
+#if	(CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32)
 #define	CONFIG_SMC_USE_32_BIT	1
 #else	/* no */
 #undef	CONFIG_SMC_USE_32_BIT
 #endif
 
-#elif	(CFG_NIOS_CPU_LAN0_TYPE == 1)		/* CS8900A		*/
+#elif	(CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 1)		/* CS8900A		*/
 
 	/********************************************/
 	/* !!! CS8900 is __not__ tested on NIOS !!! */
 	/********************************************/
 #define	CONFIG_DRIVER_CS8900			/* Using CS8900		*/
-#define	CS8900_BASE		(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
+#define	CS8900_BASE		(CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS)
 
-#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
+#if	(CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32)
 #undef	CS8900_BUS16
 #define	CS8900_BUS32		1
 #else	/* no */
@@ -245,7 +245,7 @@
 #endif
 
 #else
-#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
+#error *** CONFIG_SYS_ERROR: invalid LAN0 chip type, check your NIOS CPU config
 #endif
 
 #define CONFIG_ETHADDR		08:00:3e:26:0a:5b
@@ -254,64 +254,64 @@
 #define CONFIG_SERVERIP		192.168.2.16
 
 #else
-#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
+#error *** CONFIG_SYS_ERROR: you have to setup just one LAN only or expand your config.h
 #endif
 
 /*------------------------------------------------------------------------
  * STATUS LEDs
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_PIO_NUMS != 0)
+#if	(CONFIG_SYS_NIOS_CPU_PIO_NUMS != 0)
 
-#if	(CFG_NIOS_CPU_LED_PIO == 0)
+#if	(CONFIG_SYS_NIOS_CPU_LED_PIO == 0)
 
-#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO0 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 1)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 1)
 
-#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO1 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 2)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 2)
 
-#define	STATUS_LED_BASE			CFG_NIOS_CPU_PIO2
-#define	STATUS_LED_BITS			CFG_NIOS_CPU_PIO2_BITS
+#define	STATUS_LED_BASE			CONFIG_SYS_NIOS_CPU_PIO2
+#define	STATUS_LED_BITS			CONFIG_SYS_NIOS_CPU_PIO2_BITS
 #define	STATUS_LED_ACTIVE		1 /* LED on for bit == 1 */
 
-#if	(CFG_NIOS_CPU_PIO2_TYPE == 1)
+#if	(CONFIG_SYS_NIOS_CPU_PIO2_TYPE == 1)
 #define	STATUS_LED_WRONLY		1
 #else
 #undef	STATUS_LED_WRONLY
 #endif
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 3)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 3)
 
-#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO3 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 4)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 4)
 
-#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO4 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 5)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 5)
 
-#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO5 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 6)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 6)
 
-#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO6 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 7)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 7)
 
-#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO7 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 8)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 8)
 
-#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO8 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 9)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 9)
 
-#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO9 not supported, expand your config.h
 
 #else
-#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
+#error *** CONFIG_SYS_ERROR: you have to set CONFIG_SYS_NIOS_CPU_LED_PIO in right case
 #endif
 
 #define	CONFIG_STATUS_LED		1 /* enable status led driver */
@@ -319,89 +319,89 @@
 #define	STATUS_LED_BIT			(1 << 0)	/* LED[0] */
 #define	STATUS_LED_STATE		STATUS_LED_BLINKING
 #define	STATUS_LED_BOOT_STATE		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD		(CFG_HZ / 10)	/* ca. 1 Hz */
+#define	STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 10)	/* ca. 1 Hz */
 #define	STATUS_LED_BOOT			0		/* boot LED */
 
 #if	(STATUS_LED_BITS > 1)
 #define	STATUS_LED_BIT1			(1 << 1)	/* LED[1] */
 #define	STATUS_LED_STATE1		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD1		(CFG_HZ / 50)	/* ca. 5 Hz */
+#define	STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 50)	/* ca. 5 Hz */
 #define	STATUS_LED_RED			1		/* fail LED */
 #endif
 
 #if	(STATUS_LED_BITS > 2)
 #define	STATUS_LED_BIT2			(1 << 2)	/* LED[2] */
 #define	STATUS_LED_STATE2		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD2		(CFG_HZ / 10)	/* ca. 1 Hz */
+#define	STATUS_LED_PERIOD2		(CONFIG_SYS_HZ / 10)	/* ca. 1 Hz */
 #define	STATUS_LED_YELLOW		2		/* info LED */
 #endif
 
 #if	(STATUS_LED_BITS > 3)
 #define	STATUS_LED_BIT3			(1 << 3)	/* LED[3] */
 #define	STATUS_LED_STATE3		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD3		(CFG_HZ / 10)	/* ca. 1 Hz */
+#define	STATUS_LED_PERIOD3		(CONFIG_SYS_HZ / 10)	/* ca. 1 Hz */
 #define	STATUS_LED_GREEN		3		/* info LED */
 #endif
 
 #define	STATUS_LED_PAR			1 /* makes status_led.h happy */
 
-#endif	/* CFG_NIOS_CPU_PIO_NUMS */
+#endif	/* CONFIG_SYS_NIOS_CPU_PIO_NUMS */
 
 /*------------------------------------------------------------------------
  * SEVEN SEGMENT LED DISPLAY
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_PIO_NUMS != 0)
+#if	(CONFIG_SYS_NIOS_CPU_PIO_NUMS != 0)
 
-#if	(CFG_NIOS_CPU_SEVENSEG_PIO == 0)
+#if	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 0)
 
-#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: seven segment display at PIO0 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 1)
+#elif	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 1)
 
-#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: seven segment display at PIO1 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 2)
+#elif	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 2)
 
-#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: seven segment display at PIO2 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 3)
+#elif	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 3)
 
-#define	SEVENSEG_BASE			CFG_NIOS_CPU_PIO3
-#define	SEVENSEG_BITS			CFG_NIOS_CPU_PIO3_BITS
+#define	SEVENSEG_BASE			CONFIG_SYS_NIOS_CPU_PIO3
+#define	SEVENSEG_BITS			CONFIG_SYS_NIOS_CPU_PIO3_BITS
 #define	SEVENSEG_ACTIVE			0 /* LED on for bit == 1 */
 
-#if	(CFG_NIOS_CPU_PIO3_TYPE == 1)
+#if	(CONFIG_SYS_NIOS_CPU_PIO3_TYPE == 1)
 #define	SEVENSEG_WRONLY			1
 #else
 #undef	SEVENSEG_WRONLY
 #endif
 
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 4)
+#elif	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 4)
 
-#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: seven segment display at PIO4 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 5)
+#elif	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 5)
 
-#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: seven segment display at PIO5 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 6)
+#elif	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 6)
 
-#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: seven segment display at PIO6 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 7)
+#elif	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 7)
 
-#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: seven segment display at PIO7 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 8)
+#elif	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 8)
 
-#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: seven segment display at PIO8 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 9)
+#elif	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 9)
 
-#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: seven segment display at PIO9 not supported, expand your config.h
 
 #else
-#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case
+#error *** CONFIG_SYS_ERROR: you have to set CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO in right case
 #endif
 
 #define	CONFIG_SEVENSEG			1 /* enable seven segment led driver */
@@ -435,7 +435,7 @@
 #define	SEVENSEG_DIGIT_G		(1 << 0) /* bit 0 is segment G */
 #define	SEVENSEG_DIGIT_DP		(1 << 7) /* bit 7 is decimal point */
 
-#endif	/* CFG_NIOS_CPU_PIO_NUMS */
+#endif	/* CONFIG_SYS_NIOS_CPU_PIO_NUMS */
 
 /*------------------------------------------------------------------------
  * ASMI - Active Serial Memory Interface.
@@ -444,7 +444,7 @@
  * is loaded via JTAG or ASMI. Please see doc/README.dk1c20 for details.
  *----------------------------------------------------------------------*/
 #define CONFIG_NIOS_ASMI			   /* Enable ASMI	*/
-#define CFG_NIOS_ASMIBASE	CFG_NIOS_CPU_ASMI0 /* ASMI base address	*/
+#define CONFIG_SYS_NIOS_ASMIBASE	CONFIG_SYS_NIOS_CPU_ASMI0 /* ASMI base address	*/
 
 
 /*
@@ -485,21 +485,21 @@
  *----------------------------------------------------------------------*/
 #if defined(CONFIG_CMD_IDE)
 #define CONFIG_IDE_PREINIT			/* Implement id_preinit	*/
-#define CFG_IDE_MAXBUS		1		/* 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1		/* 1 drive per IDE bus	*/
-
-#define CFG_ATA_BASE_ADDR	0x00920a00	/* IDE/ATA base addr	*/
-#define CFG_ATA_IDE0_OFFSET	0x0000		/* IDE0 offset		*/
-#define CFG_ATA_DATA_OFFSET	0x0040		/* Data IO offset	*/
-#define CFG_ATA_REG_OFFSET	0x0040		/* Register offset	*/
-#define CFG_ATA_ALT_OFFSET	0x0100		/* Alternate reg offset	*/
-#define CFG_ATA_STRIDE          4		/* Width betwix addrs	*/
+#define CONFIG_SYS_IDE_MAXBUS		1		/* 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1		/* 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0x00920a00	/* IDE/ATA base addr	*/
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000		/* IDE0 offset		*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0040		/* Data IO offset	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0040		/* Register offset	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100		/* Alternate reg offset	*/
+#define CONFIG_SYS_ATA_STRIDE          4		/* Width betwix addrs	*/
 #define CONFIG_DOS_PARTITION
 
 /* Board-specific cf regs */
-#define CFG_CF_PRESENT		0x009209b0	/* CF Present PIO base	*/
-#define CFG_CF_POWER		0x009209c0	/* CF Power FET PIO base*/
-#define CFG_CF_ATASEL		0x009209d0	/* CF ATASEL PIO base	*/
+#define CONFIG_SYS_CF_PRESENT		0x009209b0	/* CF Present PIO base	*/
+#define CONFIG_SYS_CF_POWER		0x009209c0	/* CF Power FET PIO base*/
+#define CONFIG_SYS_CF_ATASEL		0x009209d0	/* CF ATASEL PIO base	*/
 
 #endif
 
@@ -513,25 +513,25 @@
 /*------------------------------------------------------------------------
  * MISC
  *----------------------------------------------------------------------*/
-#define	CFG_LONGHELP			    /* undef to save memory	*/
-#define	CFG_PROMPT		"DK1C20 > " /* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256	    /* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	    /* max number of command args*/
-#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size */
-
-#if	(CFG_SRAM_SIZE != 0)
-#define	CFG_LOAD_ADDR		CFG_SRAM_BASE	/* Default load address	*/
+#define	CONFIG_SYS_LONGHELP			    /* undef to save memory	*/
+#define	CONFIG_SYS_PROMPT		"DK1C20 > " /* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256	    /* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	    /* max number of command args*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
+
+#if	(CONFIG_SYS_SRAM_SIZE != 0)
+#define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SRAM_BASE	/* Default load address	*/
 #else
-#undef	CFG_LOAD_ADDR
+#undef	CONFIG_SYS_LOAD_ADDR
 #endif
 
-#if	(CFG_SDRAM_SIZE != 0)
-#define	CFG_MEMTEST_START	CFG_SDRAM_BASE	/* SDRAM til stack area */
-#define	CFG_MEMTEST_END		(CFG_INIT_SP - (1024 * 1024)) /* 1MB stack */
+#if	(CONFIG_SYS_SDRAM_SIZE != 0)
+#define	CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE	/* SDRAM til stack area */
+#define	CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - (1024 * 1024)) /* 1MB stack */
 #else
-#undef	CFG_MEMTEST_START
-#undef	CFG_MEMTEST_END
+#undef	CONFIG_SYS_MEMTEST_START
+#undef	CONFIG_SYS_MEMTEST_END
 #endif
 
 /*
diff --git a/include/configs/DK1C20_safe_32.h b/include/configs/DK1C20_safe_32.h
index a483e87..86e4869 100644
--- a/include/configs/DK1C20_safe_32.h
+++ b/include/configs/DK1C20_safe_32.h
@@ -29,6 +29,6 @@
  *
  * !!! TODO !!! TODO !!!
  */
-#error *** CFG_ERROR: DK1C20_safe_32 have to be defined (use DK1C20_standard_32 as template)
+#error *** CONFIG_SYS_ERROR: DK1C20_safe_32 have to be defined (use DK1C20_standard_32 as template)
 
 #endif	/* __CONFIG_DK1C20_SAFE_32_H */
diff --git a/include/configs/DK1C20_standard_32.h b/include/configs/DK1C20_standard_32.h
index ed08121..c08aaae 100644
--- a/include/configs/DK1C20_standard_32.h
+++ b/include/configs/DK1C20_standard_32.h
@@ -30,250 +30,250 @@
  * Here we must define CPU dependencies. Any unsupported option have to
  * be defined with zero, example CPU without data cache / OCI:
  *
- *	#define	CFG_NIOS_CPU_ICACHE	4096
- *	#define	CFG_NIOS_CPU_DCACHE	0
- *	#define	CFG_NIOS_CPU_OCI_BASE	0
- *	#define	CFG_NIOS_CPU_OCI_SIZE	0
+ *	#define	CONFIG_SYS_NIOS_CPU_ICACHE	4096
+ *	#define	CONFIG_SYS_NIOS_CPU_DCACHE	0
+ *	#define	CONFIG_SYS_NIOS_CPU_OCI_BASE	0
+ *	#define	CONFIG_SYS_NIOS_CPU_OCI_SIZE	0
  */
 
 /* CPU core */
-#define	CFG_NIOS_CPU_CLK	50000000	/* NIOS CPU clock	*/
-#define	CFG_NIOS_CPU_ICACHE	(4 * 1024)	/* instruction cache	*/
-#define	CFG_NIOS_CPU_DCACHE	(4 * 1024)	/* data cache		*/
-#define	CFG_NIOS_CPU_REG_NUMS	256		/* number of register	*/
-#define	CFG_NIOS_CPU_MUL	0		/* 16x16 MUL:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_CLK	50000000	/* NIOS CPU clock	*/
+#define	CONFIG_SYS_NIOS_CPU_ICACHE	(4 * 1024)	/* instruction cache	*/
+#define	CONFIG_SYS_NIOS_CPU_DCACHE	(4 * 1024)	/* data cache		*/
+#define	CONFIG_SYS_NIOS_CPU_REG_NUMS	256		/* number of register	*/
+#define	CONFIG_SYS_NIOS_CPU_MUL	0		/* 16x16 MUL:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_MSTEP	1		/* 16x16 MSTEP:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_MSTEP	1		/* 16x16 MSTEP:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_STACK	0x008fff00	/* stack top	addr	*/
-#define	CFG_NIOS_CPU_VEC_BASE	0x008fff00	/* IRQ vectors	addr	*/
-#define	CFG_NIOS_CPU_VEC_SIZE	256		/*		size	*/
-#define	CFG_NIOS_CPU_VEC_NUMS	64		/*		numbers	*/
-#define	CFG_NIOS_CPU_RST_VECT	0x00920000	/* RESET vector	addr	*/
-#define	CFG_NIOS_CPU_DBG_CORE	0		/* CPU debug:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_STACK	0x008fff00	/* stack top	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_VEC_BASE	0x008fff00	/* IRQ vectors	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_VEC_SIZE	256		/*		size	*/
+#define	CONFIG_SYS_NIOS_CPU_VEC_NUMS	64		/*		numbers	*/
+#define	CONFIG_SYS_NIOS_CPU_RST_VECT	0x00920000	/* RESET vector	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_DBG_CORE	0		/* CPU debug:	no(0)	*/
 						/*		yes(1)	*/
 
 /* on-chip extensions */
-#define	CFG_NIOS_CPU_RAM_BASE	0		/* on chip RAM	addr	*/
-#define	CFG_NIOS_CPU_RAM_SIZE	0		/*		size	*/
+#define	CONFIG_SYS_NIOS_CPU_RAM_BASE	0		/* on chip RAM	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_RAM_SIZE	0		/*		size	*/
 
-#define	CFG_NIOS_CPU_ROM_BASE	0x00920000	/* on chip ROM	addr	*/
-#define	CFG_NIOS_CPU_ROM_SIZE	(2 * 1024)	/*  2 KB	size	*/
+#define	CONFIG_SYS_NIOS_CPU_ROM_BASE	0x00920000	/* on chip ROM	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_ROM_SIZE	(2 * 1024)	/*  2 KB	size	*/
 
-#define	CFG_NIOS_CPU_OCI_BASE	0x00920800	/* OCI core	addr	*/
-#define	CFG_NIOS_CPU_OCI_SIZE	256		/*		size	*/
+#define	CONFIG_SYS_NIOS_CPU_OCI_BASE	0x00920800	/* OCI core	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_OCI_SIZE	256		/*		size	*/
 
 /* timer */
-#define	CFG_NIOS_CPU_TIMER_NUMS	2		/* number of timer	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER_NUMS	2		/* number of timer	*/
 
-#define	CFG_NIOS_CPU_TIMER0	0x00920940	/* TIMER0	addr	*/
-#define	CFG_NIOS_CPU_TIMER0_IRQ	16		/*		IRQ	*/
-#define	CFG_NIOS_CPU_TIMER0_PER	1000		/*  periode	usec	*/
-#define	CFG_NIOS_CPU_TIMER0_AR	0		/*  always run:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0	0x00920940	/* TIMER0	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_IRQ	16		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_PER	1000		/*  periode	usec	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_AR	0		/*  always run:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER0_FP	0		/*  fixed per:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_FP	0		/*  fixed per:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER0_SS	1		/*  snaphot:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_SS	1		/*  snaphot:	no(0)	*/
 						/*		yes(1)	*/
 
-#define	CFG_NIOS_CPU_TIMER1	0x009209e0	/* TIMER1	addr	*/
-#define	CFG_NIOS_CPU_TIMER1_IRQ	50		/*		IRQ	*/
-#define	CFG_NIOS_CPU_TIMER1_PER	10000		/*  periode	usec	*/
-#define	CFG_NIOS_CPU_TIMER1_AR	1		/*  always run:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER1	0x009209e0	/* TIMER1	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER1_IRQ	50		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER1_PER	10000		/*  periode	usec	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER1_AR	1		/*  always run:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER1_FP	1		/*  fixed per:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER1_FP	1		/*  fixed per:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER1_SS	0		/*  snaphot:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER1_SS	0		/*  snaphot:	no(0)	*/
 						/*		yes(1)	*/
 
 /* serial i/o */
-#define	CFG_NIOS_CPU_UART_NUMS	1		/* number of uarts	*/
+#define	CONFIG_SYS_NIOS_CPU_UART_NUMS	1		/* number of uarts	*/
 
-#define	CFG_NIOS_CPU_UART0	0x00920900	/* UART0	addr	*/
-#define	CFG_NIOS_CPU_UART0_IRQ	25		/*		IRQ	*/
-#define	CFG_NIOS_CPU_UART0_BR	115200		/*  baudrate	var(0)	*/
-#define	CFG_NIOS_CPU_UART0_DB	8		/*  data bit		*/
-#define	CFG_NIOS_CPU_UART0_SB	1		/*  stop bit		*/
-#define	CFG_NIOS_CPU_UART0_PA	0		/*  parity	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0	0x00920900	/* UART0	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_IRQ	25		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_BR	115200		/*  baudrate	var(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_DB	8		/*  data bit		*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_SB	1		/*  stop bit		*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_PA	0		/*  parity	none(0)	*/
 						/*		odd(1)	*/
 						/*		even(2)	*/
-#define	CFG_NIOS_CPU_UART0_HS	0		/*  handshake:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_HS	0		/*  handshake:	no(0)	*/
 						/*		crts(1)	*/
-#define	CFG_NIOS_CPU_UART0_EOP	0		/*  eop reg:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_EOP	0		/*  eop reg:	no(0)	*/
 						/*		yes(1)	*/
 
 /* parallel i/o */
-#define	CFG_NIOS_CPU_PIO_NUMS	8		/* number of parports	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO_NUMS	8		/* number of parports	*/
 
-#define	CFG_NIOS_CPU_PIO0	0x00920960	/* PIO0		addr	*/
-#define	CFG_NIOS_CPU_PIO0_IRQ	40		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO0_BITS	4		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO0_TYPE	2		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0	0x00920960	/* PIO0		addr	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_IRQ	40		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_BITS	4		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_TYPE	2		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO0_CAP	1		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_CAP	1		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO0_EDGE	3		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_EDGE	3		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO0_ITYPE	2		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_ITYPE	2		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO1	0x00920970	/* PIO1		addr	*/
-#undef	CFG_NIOS_CPU_PIO1_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO1_BITS	11		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO1_TYPE	0		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1	0x00920970	/* PIO1		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO1_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_BITS	11		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_TYPE	0		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO1_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO1_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO1_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO2	0x00920980	/* PIO2		addr	*/
-#undef	CFG_NIOS_CPU_PIO2_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO2_BITS	8		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO2_TYPE	1		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO2	0x00920980	/* PIO2		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO2_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO2_BITS	8		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO2_TYPE	1		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO2_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO2_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO2_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO2_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO2_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO2_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO3	0x00920990	/* PIO3		addr	*/
-#undef	CFG_NIOS_CPU_PIO3_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO3_BITS	16		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO3_TYPE	1		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3	0x00920990	/* PIO3		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO3_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_BITS	16		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_TYPE	1		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO3_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO3_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO3_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO4	0x009209a0	/* PIO4		addr	*/
-#undef	CFG_NIOS_CPU_PIO4_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO4_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO4_TYPE	0		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO4	0x009209a0	/* PIO4		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO4_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO4_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO4_TYPE	0		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO4_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO4_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO4_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO4_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO4_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO4_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO5	0x009209b0	/* PIO5		addr	*/
-#define	CFG_NIOS_CPU_PIO5_IRQ	35		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO5_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO5_TYPE	2		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5	0x009209b0	/* PIO5		addr	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5_IRQ	35		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5_TYPE	2		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO5_CAP	1		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5_CAP	1		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO5_EDGE	3		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5_EDGE	3		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO5_ITYPE	2		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5_ITYPE	2		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO6	0x009209c0	/* PIO6		addr	*/
-#undef	CFG_NIOS_CPU_PIO6_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO6_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO6_TYPE	1		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO6	0x009209c0	/* PIO6		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO6_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO6_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO6_TYPE	1		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO6_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO6_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO6_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO6_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO6_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO6_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO7	0x009209d0	/* PIO7		addr	*/
-#undef	CFG_NIOS_CPU_PIO7_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO7_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO7_TYPE	1		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO7	0x009209d0	/* PIO7		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO7_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO7_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO7_TYPE	1		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO7_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO7_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO7_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO7_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO7_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO7_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
 /* IDE i/f */
-#define	CFG_NIOS_CPU_IDE_NUMS	1		/* number of IDE contr.	*/
-#define	CFG_NIOS_CPU_IDE0	0x00920a00	/* IDE0		addr	*/
+#define	CONFIG_SYS_NIOS_CPU_IDE_NUMS	1		/* number of IDE contr.	*/
+#define	CONFIG_SYS_NIOS_CPU_IDE0	0x00920a00	/* IDE0		addr	*/
 
 /* active serial memory i/f */
-#define	CFG_NIOS_CPU_ASMI_NUMS	1		/* number of ASMI	*/
-#define	CFG_NIOS_CPU_ASMI0	0x00920b00	/* ASMI0	addr	*/
-#define	CFG_NIOS_CPU_ASMI0_IRQ	45		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_ASMI_NUMS	1		/* number of ASMI	*/
+#define	CONFIG_SYS_NIOS_CPU_ASMI0	0x00920b00	/* ASMI0	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_ASMI0_IRQ	45		/*		IRQ	*/
 
 /* memory accessibility */
-#define	CFG_NIOS_CPU_SRAM_BASE	0x00800000	/* board SRAM	addr	*/
-#define	CFG_NIOS_CPU_SRAM_SIZE	(1024 * 1024)	/*  1 MB	size	*/
+#define	CONFIG_SYS_NIOS_CPU_SRAM_BASE	0x00800000	/* board SRAM	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_SRAM_SIZE	(1024 * 1024)	/*  1 MB	size	*/
 
-#define	CFG_NIOS_CPU_SDRAM_BASE	0x01000000	/* board SDRAM	addr	*/
-#define	CFG_NIOS_CPU_SDRAM_SIZE	(16*1024*1024)	/* 16 MB	size	*/
+#define	CONFIG_SYS_NIOS_CPU_SDRAM_BASE	0x01000000	/* board SDRAM	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_SDRAM_SIZE	(16*1024*1024)	/* 16 MB	size	*/
 
-#define	CFG_NIOS_CPU_FLASH_BASE	0x00000000	/* board Flash	addr	*/
-#define	CFG_NIOS_CPU_FLASH_SIZE	(8*1024*1024)	/*  8 MB	size	*/
+#define	CONFIG_SYS_NIOS_CPU_FLASH_BASE	0x00000000	/* board Flash	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_FLASH_SIZE	(8*1024*1024)	/*  8 MB	size	*/
 
 /* LAN */
-#define	CFG_NIOS_CPU_LAN_NUMS	1		/* number of LAN i/f	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN_NUMS	1		/* number of LAN i/f	*/
 
-#define	CFG_NIOS_CPU_LAN0_BASE	0x00910000	/* LAN0		addr	*/
-#define	CFG_NIOS_CPU_LAN0_OFFS	0x0300		/*		offset	*/
-#define	CFG_NIOS_CPU_LAN0_IRQ	30		/*		IRQ	*/
-#define	CFG_NIOS_CPU_LAN0_BUSW	32		/*	        buswidth*/
-#define	CFG_NIOS_CPU_LAN0_TYPE	0		/*	smc91111(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_BASE	0x00910000	/* LAN0		addr	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_OFFS	0x0300		/*		offset	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_IRQ	30		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_BUSW	32		/*	        buswidth*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_TYPE	0		/*	smc91111(0)	*/
 						/*	cs8900(1)	*/
 						/* ex:	alteramac(2)	*/
 
 /* symbolic redefinition (undef, if not present) */
-#define	CFG_NIOS_CPU_USER_TIMER		0	/* TIMER0: users choice	*/
-#define	CFG_NIOS_CPU_TICK_TIMER		1	/* TIMER1: tick (needed)*/
+#define	CONFIG_SYS_NIOS_CPU_USER_TIMER		0	/* TIMER0: users choice	*/
+#define	CONFIG_SYS_NIOS_CPU_TICK_TIMER		1	/* TIMER1: tick (needed)*/
 
-#define	CFG_NIOS_CPU_BUTTON_PIO		0	/* PIO0: buttons	*/
-#define	CFG_NIOS_CPU_LCD_PIO		1	/* PIO1: ASCII LCD	*/
-#define	CFG_NIOS_CPU_LED_PIO		2	/* PIO2: LED bar	*/
-#define	CFG_NIOS_CPU_SEVENSEG_PIO	3	/* PIO3: 7-seg. display	*/
-#define	CFG_NIOS_CPU_RECONF_PIO		4	/* PIO4: reconf pin	*/
-#define	CFG_NIOS_CPU_CFPRESENT_PIO	5	/* PIO5: CF present IRQ	*/
-#define	CFG_NIOS_CPU_CFPOWER_PIO	6	/* PIO6: CF power/sw.	*/
-#define	CFG_NIOS_CPU_CFATASEL_PIO	7	/* PIO7: CF ATA select	*/
+#define	CONFIG_SYS_NIOS_CPU_BUTTON_PIO		0	/* PIO0: buttons	*/
+#define	CONFIG_SYS_NIOS_CPU_LCD_PIO		1	/* PIO1: ASCII LCD	*/
+#define	CONFIG_SYS_NIOS_CPU_LED_PIO		2	/* PIO2: LED bar	*/
+#define	CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO	3	/* PIO3: 7-seg. display	*/
+#define	CONFIG_SYS_NIOS_CPU_RECONF_PIO		4	/* PIO4: reconf pin	*/
+#define	CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO	5	/* PIO5: CF present IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_CFPOWER_PIO	6	/* PIO6: CF power/sw.	*/
+#define	CONFIG_SYS_NIOS_CPU_CFATASEL_PIO	7	/* PIO7: CF ATA select	*/
 
 #endif	/* __CONFIG_DK1C20_STANDARD_32_H */
diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h
index 12d4e6b..1d031f1 100644
--- a/include/configs/DK1S10.h
+++ b/include/configs/DK1S10.h
@@ -38,7 +38,7 @@
 #elif	defined(CONFIG_NIOS_MTX_LDK_20)
 #include <configs/DK1S10_mtx_ldk_20.h>
 #else
-#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
+#error *** CONFIG_SYS_ERROR: you have to setup right NIOS CPU configuration
 #endif
 
 /*------------------------------------------------------------------------
@@ -46,36 +46,36 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_NIOS		1		/* NIOS-32 core		*/
 #define	CONFIG_DK1S10		1		/* Stratix DK-1S10 board*/
-#define CONFIG_SYS_CLK_FREQ	CFG_NIOS_CPU_CLK/* 50 MHz core clock	*/
-#define	CFG_HZ			1000		/* 1 msec time tick	*/
-#undef  CFG_CLKS_IN_HZ
+#define CONFIG_SYS_CLK_FREQ	CONFIG_SYS_NIOS_CPU_CLK/* 50 MHz core clock	*/
+#define	CONFIG_SYS_HZ			1000		/* 1 msec time tick	*/
+#undef  CONFIG_SYS_CLKS_IN_HZ
 #define	CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
 
 /*------------------------------------------------------------------------
  * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_SDRAM_SIZE != 0)
+#if	(CONFIG_SYS_NIOS_CPU_SDRAM_SIZE != 0)
 
-#define CFG_SDRAM_BASE		CFG_NIOS_CPU_SDRAM_BASE
-#define CFG_SDRAM_SIZE		CFG_NIOS_CPU_SDRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_NIOS_CPU_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		CONFIG_SYS_NIOS_CPU_SDRAM_SIZE
 
 #else
-#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
+#error *** CONFIG_SYS_ERROR: you have to setup any SDRAM in NIOS CPU config
 #endif
 
-#if	defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE)
+#if	defined(CONFIG_SYS_NIOS_CPU_SRAM_BASE) && defined(CONFIG_SYS_NIOS_CPU_SRAM_SIZE)
 
-#define	CFG_SRAM_BASE		CFG_NIOS_CPU_SRAM_BASE
-#define	CFG_SRAM_SIZE		CFG_NIOS_CPU_SRAM_SIZE
+#define	CONFIG_SYS_SRAM_BASE		CONFIG_SYS_NIOS_CPU_SRAM_BASE
+#define	CONFIG_SYS_SRAM_SIZE		CONFIG_SYS_NIOS_CPU_SRAM_SIZE
 
 #else
 
-#undef	CFG_SRAM_BASE
-#undef	CFG_SRAM_SIZE
+#undef	CONFIG_SYS_SRAM_BASE
+#undef	CONFIG_SYS_SRAM_SIZE
 
 #endif
 
-#define CFG_VECT_BASE		CFG_NIOS_CPU_VEC_BASE
+#define CONFIG_SYS_VECT_BASE		CONFIG_SYS_NIOS_CPU_VEC_BASE
 
 /*------------------------------------------------------------------------
  * MEMORY ORGANIZATION - For the most part, you can put things pretty
@@ -88,45 +88,45 @@
  *	-Global data is placed below the heap.
  *	-The stack is placed below global data (&grows down).
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
-#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
 
 /*------------------------------------------------------------------------
  * FLASH (AM29LV065D)
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)
+#if	(CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0)
 
-#define CFG_FLASH_BASE		CFG_NIOS_CPU_FLASH_BASE
-#define CFG_FLASH_SIZE		CFG_NIOS_CPU_FLASH_SIZE
-#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
-#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
-#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
-#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
-#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_NIOS_CPU_FLASH_BASE
+#define CONFIG_SYS_FLASH_SIZE		CONFIG_SYS_NIOS_CPU_FLASH_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
 
 #else
-#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
+#error *** CONFIG_SYS_ERROR: you have to setup any Flash memory in NIOS CPU config
 #endif
 
 /*------------------------------------------------------------------------
  * ENVIRONMENT
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)
+#if	(CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0)
 
 #define	CONFIG_ENV_IS_IN_FLASH	1		/* Environment in flash */
 
 #if	defined(CONFIG_NIOS_STANDARD_32)
-#define CONFIG_ENV_ADDR		CFG_FLASH_BASE	/* Mem addr of env	*/
+#define CONFIG_ENV_ADDR		CONFIG_SYS_FLASH_BASE	/* Mem addr of env	*/
 #elif	defined(CONFIG_NIOS_MTX_LDK_20)
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 #else
-#error *** CFG_ERROR: you have to setup the environment base address CONFIG_ENV_ADDR
+#error *** CONFIG_SYS_ERROR: you have to setup the environment base address CONFIG_ENV_ADDR
 #endif
 
 #define CONFIG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
@@ -139,121 +139,121 @@
 /*------------------------------------------------------------------------
  * CONSOLE
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_UART_NUMS != 0)
+#if	(CONFIG_SYS_NIOS_CPU_UART_NUMS != 0)
 
-#define CFG_NIOS_CONSOLE	CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
+#define CONFIG_SYS_NIOS_CONSOLE	CONFIG_SYS_NIOS_CPU_UART0 /* 1st UART is Cons. */
 #define CONFIG_LOADS_ECHO	1	 /* echo on for serial download */
 
-#if	(CFG_NIOS_CPU_UART0_BR != 0)
-#define CFG_NIOS_FIXEDBAUD	1		   /* Baudrate is fixed	*/
-#define CONFIG_BAUDRATE		CFG_NIOS_CPU_UART0_BR
+#if	(CONFIG_SYS_NIOS_CPU_UART0_BR != 0)
+#define CONFIG_SYS_NIOS_FIXEDBAUD	1		   /* Baudrate is fixed	*/
+#define CONFIG_BAUDRATE		CONFIG_SYS_NIOS_CPU_UART0_BR
 #else
-#undef	CFG_NIOS_FIXEDBAUD
+#undef	CONFIG_SYS_NIOS_FIXEDBAUD
 #define CONFIG_BAUDRATE		115200
 #endif
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #else
-#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
+#error *** CONFIG_SYS_ERROR: you have to setup at least one UART in NIOS CPU config
 #endif
 
 /*------------------------------------------------------------------------
  * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc  PIT,
  * so an avalon bus timer is required.
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER)
+#if	(CONFIG_SYS_NIOS_CPU_TIMER_NUMS != 0) && defined(CONFIG_SYS_NIOS_CPU_TICK_TIMER)
 
-#if	(CFG_NIOS_CPU_TICK_TIMER == 0)
+#if	(CONFIG_SYS_NIOS_CPU_TICK_TIMER == 0)
 
-#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick	*/
-#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER0_IRQ
+#define CONFIG_SYS_NIOS_TMRBASE	CONFIG_SYS_NIOS_CPU_TIMER0 /* TIMER0 as tick	*/
+#define CONFIG_SYS_NIOS_TMRIRQ		CONFIG_SYS_NIOS_CPU_TIMER0_IRQ
 
-#if	(CFG_NIOS_CPU_TIMER0_FP == 1)		    /* fixed period */
+#if	(CONFIG_SYS_NIOS_CPU_TIMER0_FP == 1)		    /* fixed period */
 
-#if	(CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
-#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
+#if	(CONFIG_SYS_NIOS_CPU_TIMER0_PER >= CONFIG_SYS_HZ)
+#define CONFIG_SYS_NIOS_TMRMS		(CONFIG_SYS_NIOS_CPU_TIMER0_PER / CONFIG_SYS_HZ)
 #else
-#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
+#error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ
 #endif
 
-#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */
+#undef	CONFIG_SYS_NIOS_TMRCNT	/* no preloadable counter value */
 
-#elif	(CFG_NIOS_CPU_TIMER0_FP == 0)		    /* variable period */
+#elif	(CONFIG_SYS_NIOS_CPU_TIMER0_FP == 0)		    /* variable period */
 
-#if	(CFG_HZ <= 1000)
-#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
+#if	(CONFIG_SYS_HZ <= 1000)
+#define CONFIG_SYS_NIOS_TMRMS		(1000 / CONFIG_SYS_HZ)
 #else
-#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
+#error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000
 #endif
 
-#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)
+#define	CONFIG_SYS_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ)
 
 #else
-#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
+#error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER0_FP correct
 #endif
 
-#elif	(CFG_NIOS_CPU_TICK_TIMER == 1)
+#elif	(CONFIG_SYS_NIOS_CPU_TICK_TIMER == 1)
 
-#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick	*/
-#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER1_IRQ
+#define CONFIG_SYS_NIOS_TMRBASE	CONFIG_SYS_NIOS_CPU_TIMER1 /* TIMER1 as tick	*/
+#define CONFIG_SYS_NIOS_TMRIRQ		CONFIG_SYS_NIOS_CPU_TIMER1_IRQ
 
-#if	(CFG_NIOS_CPU_TIMER1_FP == 1)		    /* fixed period */
+#if	(CONFIG_SYS_NIOS_CPU_TIMER1_FP == 1)		    /* fixed period */
 
-#if	(CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
-#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
+#if	(CONFIG_SYS_NIOS_CPU_TIMER1_PER >= CONFIG_SYS_HZ)
+#define CONFIG_SYS_NIOS_TMRMS		(CONFIG_SYS_NIOS_CPU_TIMER1_PER / CONFIG_SYS_HZ)
 #else
-#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
+#error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ
 #endif
 
-#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */
+#undef	CONFIG_SYS_NIOS_TMRCNT	/* no preloadable counter value */
 
-#elif	(CFG_NIOS_CPU_TIMER1_FP == 0)		    /* variable period */
+#elif	(CONFIG_SYS_NIOS_CPU_TIMER1_FP == 0)		    /* variable period */
 
-#if	(CFG_HZ <= 1000)
-#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
+#if	(CONFIG_SYS_HZ <= 1000)
+#define CONFIG_SYS_NIOS_TMRMS		(1000 / CONFIG_SYS_HZ)
 #else
-#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
+#error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000
 #endif
 
-#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)
+#define	CONFIG_SYS_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ)
 
 #else
-#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
+#error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER1_FP correct
 #endif
 
-#endif	/* CFG_NIOS_CPU_TICK_TIMER */
+#endif	/* CONFIG_SYS_NIOS_CPU_TICK_TIMER */
 
 #else
-#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
+#error *** CONFIG_SYS_ERROR: you have to setup at least one TIMER in NIOS CPU config
 #endif
 
 /*------------------------------------------------------------------------
  * Ethernet -- needs work!
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_LAN_NUMS == 1)
+#if	(CONFIG_SYS_NIOS_CPU_LAN_NUMS == 1)
 
-#if	(CFG_NIOS_CPU_LAN0_TYPE == 0)		/* LAN91C111		*/
+#if	(CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 0)		/* LAN91C111		*/
 
 #define	CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
 #undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
-#define	CONFIG_SMC91111_BASE	(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
+#define	CONFIG_SMC91111_BASE	(CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS)
 
-#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
+#if	(CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32)
 #define	CONFIG_SMC_USE_32_BIT	1
 #else	/* no */
 #undef	CONFIG_SMC_USE_32_BIT
 #endif
 
-#elif	(CFG_NIOS_CPU_LAN0_TYPE == 1)		/* CS8900A		*/
+#elif	(CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 1)		/* CS8900A		*/
 
 	/********************************************/
 	/* !!! CS8900 is __not__ tested on NIOS !!! */
 	/********************************************/
 #define	CONFIG_DRIVER_CS8900			/* Using CS8900		*/
-#define	CS8900_BASE		(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
+#define	CS8900_BASE		(CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS)
 
-#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
+#if	(CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32)
 #undef	CS8900_BUS16
 #define	CS8900_BUS32		1
 #else	/* no */
@@ -262,7 +262,7 @@
 #endif
 
 #else
-#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
+#error *** CONFIG_SYS_ERROR: invalid LAN0 chip type, check your NIOS CPU config
 #endif
 
 #define CONFIG_ETHADDR		08:00:3e:26:0a:5b
@@ -271,64 +271,64 @@
 #define CONFIG_SERVERIP		192.168.2.16
 
 #else
-#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
+#error *** CONFIG_SYS_ERROR: you have to setup just one LAN only or expand your config.h
 #endif
 
 /*------------------------------------------------------------------------
  * STATUS LEDs
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO)
+#if	(CONFIG_SYS_NIOS_CPU_PIO_NUMS != 0) && defined(CONFIG_SYS_NIOS_CPU_LED_PIO)
 
-#if	(CFG_NIOS_CPU_LED_PIO == 0)
+#if	(CONFIG_SYS_NIOS_CPU_LED_PIO == 0)
 
-#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO0 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 1)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 1)
 
-#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO1 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 2)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 2)
 
-#define	STATUS_LED_BASE			CFG_NIOS_CPU_PIO2
-#define	STATUS_LED_BITS			CFG_NIOS_CPU_PIO2_BITS
+#define	STATUS_LED_BASE			CONFIG_SYS_NIOS_CPU_PIO2
+#define	STATUS_LED_BITS			CONFIG_SYS_NIOS_CPU_PIO2_BITS
 #define	STATUS_LED_ACTIVE		1 /* LED on for bit == 1 */
 
-#if	(CFG_NIOS_CPU_PIO2_TYPE == 1)
+#if	(CONFIG_SYS_NIOS_CPU_PIO2_TYPE == 1)
 #define	STATUS_LED_WRONLY		1
 #else
 #undef	STATUS_LED_WRONLY
 #endif
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 3)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 3)
 
-#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO3 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 4)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 4)
 
-#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO4 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 5)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 5)
 
-#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO5 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 6)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 6)
 
-#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO6 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 7)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 7)
 
-#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO7 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 8)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 8)
 
-#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO8 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_LED_PIO == 9)
+#elif	(CONFIG_SYS_NIOS_CPU_LED_PIO == 9)
 
-#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: status LEDs at PIO9 not supported, expand your config.h
 
 #else
-#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
+#error *** CONFIG_SYS_ERROR: you have to set CONFIG_SYS_NIOS_CPU_LED_PIO in right case
 #endif
 
 #define	CONFIG_STATUS_LED		1 /* enable status led driver */
@@ -336,89 +336,89 @@
 #define	STATUS_LED_BIT			(1 << 0)	/* LED[0] */
 #define	STATUS_LED_STATE		STATUS_LED_BLINKING
 #define	STATUS_LED_BOOT_STATE		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD		(CFG_HZ / 10)	/* ca. 1 Hz */
+#define	STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 10)	/* ca. 1 Hz */
 #define	STATUS_LED_BOOT			0		/* boot LED */
 
 #if	(STATUS_LED_BITS > 1)
 #define	STATUS_LED_BIT1			(1 << 1)	/* LED[1] */
 #define	STATUS_LED_STATE1		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD1		(CFG_HZ / 50)	/* ca. 5 Hz */
+#define	STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 50)	/* ca. 5 Hz */
 #define	STATUS_LED_RED			1		/* fail LED */
 #endif
 
 #if	(STATUS_LED_BITS > 2)
 #define	STATUS_LED_BIT2			(1 << 2)	/* LED[2] */
 #define	STATUS_LED_STATE2		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD2		(CFG_HZ / 10)	/* ca. 1 Hz */
+#define	STATUS_LED_PERIOD2		(CONFIG_SYS_HZ / 10)	/* ca. 1 Hz */
 #define	STATUS_LED_YELLOW		2		/* info LED */
 #endif
 
 #if	(STATUS_LED_BITS > 3)
 #define	STATUS_LED_BIT3			(1 << 3)	/* LED[3] */
 #define	STATUS_LED_STATE3		STATUS_LED_OFF
-#define	STATUS_LED_PERIOD3		(CFG_HZ / 10)	/* ca. 1 Hz */
+#define	STATUS_LED_PERIOD3		(CONFIG_SYS_HZ / 10)	/* ca. 1 Hz */
 #define	STATUS_LED_GREEN		3		/* info LED */
 #endif
 
 #define	STATUS_LED_PAR			1 /* makes status_led.h happy */
 
-#endif	/* CFG_NIOS_CPU_PIO_NUMS */
+#endif	/* CONFIG_SYS_NIOS_CPU_PIO_NUMS */
 
 /*------------------------------------------------------------------------
  * SEVEN SEGMENT LED DISPLAY
  *----------------------------------------------------------------------*/
-#if	(CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_SEVENSEG_PIO)
+#if	(CONFIG_SYS_NIOS_CPU_PIO_NUMS != 0) && defined(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO)
 
-#if	(CFG_NIOS_CPU_SEVENSEG_PIO == 0)
+#if	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 0)
 
-#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: seven segment display at PIO0 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 1)
+#elif	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 1)
 
-#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: seven segment display at PIO1 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 2)
+#elif	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 2)
 
-#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: seven segment display at PIO2 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 3)
+#elif	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 3)
 
-#define	SEVENSEG_BASE			CFG_NIOS_CPU_PIO3
-#define	SEVENSEG_BITS			CFG_NIOS_CPU_PIO3_BITS
+#define	SEVENSEG_BASE			CONFIG_SYS_NIOS_CPU_PIO3
+#define	SEVENSEG_BITS			CONFIG_SYS_NIOS_CPU_PIO3_BITS
 #define	SEVENSEG_ACTIVE			0 /* LED on for bit == 1 */
 
-#if	(CFG_NIOS_CPU_PIO3_TYPE == 1)
+#if	(CONFIG_SYS_NIOS_CPU_PIO3_TYPE == 1)
 #define	SEVENSEG_WRONLY			1
 #else
 #undef	SEVENSEG_WRONLY
 #endif
 
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 4)
+#elif	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 4)
 
-#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: seven segment display at PIO4 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 5)
+#elif	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 5)
 
-#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: seven segment display at PIO5 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 6)
+#elif	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 6)
 
-#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: seven segment display at PIO6 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 7)
+#elif	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 7)
 
-#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: seven segment display at PIO7 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 8)
+#elif	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 8)
 
-#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: seven segment display at PIO8 not supported, expand your config.h
 
-#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 9)
+#elif	(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 9)
 
-#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h
+#error *** CONFIG_SYS_ERROR: seven segment display at PIO9 not supported, expand your config.h
 
 #else
-#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case
+#error *** CONFIG_SYS_ERROR: you have to set CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO in right case
 #endif
 
 #define	CONFIG_SEVENSEG			1 /* enable seven segment led driver */
@@ -452,7 +452,7 @@
 #define	SEVENSEG_DIGIT_G		(1 << 0) /* bit 0 is segment G */
 #define	SEVENSEG_DIGIT_DP		(1 << 7) /* bit 7 is decimal point */
 
-#endif	/* CFG_NIOS_CPU_PIO_NUMS */
+#endif	/* CONFIG_SYS_NIOS_CPU_PIO_NUMS */
 
 /*
  * BOOTP options
@@ -496,48 +496,48 @@
 /*------------------------------------------------------------------------
  * MISC
  *----------------------------------------------------------------------*/
-#define	CFG_LONGHELP			    /* undef to save memory	*/
-#define	CFG_PROMPT		"DK1S10 > " /* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256	    /* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	    /* max number of command args*/
-#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size */
+#define	CONFIG_SYS_LONGHELP			    /* undef to save memory	*/
+#define	CONFIG_SYS_PROMPT		"DK1S10 > " /* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256	    /* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	    /* max number of command args*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
 
 /* Default load address	*/
-#if	(CFG_SRAM_SIZE != 0)
+#if	(CONFIG_SYS_SRAM_SIZE != 0)
 
 /* default in SRAM */
-#define	CFG_LOAD_ADDR		CFG_SRAM_BASE
+#define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SRAM_BASE
 
-#elif	(CFG_SDRAM_SIZE != 0)
+#elif	(CONFIG_SYS_SDRAM_SIZE != 0)
 
 /* default in SDRAM */
-#if	(CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
-#define	CFG_LOAD_ADDR		(CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
+#if	(CONFIG_SYS_SDRAM_BASE == CONFIG_SYS_NIOS_CPU_VEC_BASE)
+#define	CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_NIOS_CPU_VEC_SIZE)
 #else
-#define	CFG_LOAD_ADDR		CFG_SDRAM_BASE
+#define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
 #endif
 
 #else
-#undef	CFG_LOAD_ADDR		/* force error break */
+#undef	CONFIG_SYS_LOAD_ADDR		/* force error break */
 #endif
 
 
 /* MEM test area */
-#if	(CFG_SDRAM_SIZE != 0)
+#if	(CONFIG_SYS_SDRAM_SIZE != 0)
 
 /* SDRAM begin to stack area (1MB stack) */
-#if	(CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
-#define	CFG_MEMTEST_START	(CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
-#define	CFG_MEMTEST_END		(CFG_INIT_SP - (1024 * 1024))
+#if	(CONFIG_SYS_SDRAM_BASE == CONFIG_SYS_NIOS_CPU_VEC_BASE)
+#define	CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_NIOS_CPU_VEC_SIZE)
+#define	CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - (1024 * 1024))
 #else
-#define	CFG_MEMTEST_START	CFG_SDRAM_BASE
-#define	CFG_MEMTEST_END		(CFG_INIT_SP - (1024 * 1024))
+#define	CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define	CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - (1024 * 1024))
 #endif
 
 #else
-#undef	CFG_MEMTEST_START	/* force error break */
-#undef	CFG_MEMTEST_END
+#undef	CONFIG_SYS_MEMTEST_START	/* force error break */
+#undef	CONFIG_SYS_MEMTEST_END
 #endif
 
 /*
diff --git a/include/configs/DK1S10_mtx_ldk_20.h b/include/configs/DK1S10_mtx_ldk_20.h
index 0115699..87a8a54 100644
--- a/include/configs/DK1S10_mtx_ldk_20.h
+++ b/include/configs/DK1S10_mtx_ldk_20.h
@@ -30,158 +30,158 @@
  * Here we must define CPU dependencies. Any unsupported option have to
  * be defined with zero, example CPU without data cache / OCI:
  *
- *	#define	CFG_NIOS_CPU_ICACHE	4096
- *	#define	CFG_NIOS_CPU_DCACHE	0
- *	#define	CFG_NIOS_CPU_OCI_BASE	0
- *	#define	CFG_NIOS_CPU_OCI_SIZE	0
+ *	#define	CONFIG_SYS_NIOS_CPU_ICACHE	4096
+ *	#define	CONFIG_SYS_NIOS_CPU_DCACHE	0
+ *	#define	CONFIG_SYS_NIOS_CPU_OCI_BASE	0
+ *	#define	CONFIG_SYS_NIOS_CPU_OCI_SIZE	0
  */
 
 /* CPU core */
-#define	CFG_NIOS_CPU_CLK	75000000	/* NIOS CPU clock	*/
-#define	CFG_NIOS_CPU_ICACHE	(0)		/* instruction cache	*/
-#define	CFG_NIOS_CPU_DCACHE	(0)		/* data cache		*/
-#define	CFG_NIOS_CPU_REG_NUMS	512		/* number of register	*/
-#define	CFG_NIOS_CPU_MUL	0		/* 16x16 MUL:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_CLK	75000000	/* NIOS CPU clock	*/
+#define	CONFIG_SYS_NIOS_CPU_ICACHE	(0)		/* instruction cache	*/
+#define	CONFIG_SYS_NIOS_CPU_DCACHE	(0)		/* data cache		*/
+#define	CONFIG_SYS_NIOS_CPU_REG_NUMS	512		/* number of register	*/
+#define	CONFIG_SYS_NIOS_CPU_MUL	0		/* 16x16 MUL:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_MSTEP	1		/* 16x16 MSTEP:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_MSTEP	1		/* 16x16 MSTEP:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_STACK	0x02000000	/* stack top	addr	*/
-#define	CFG_NIOS_CPU_VEC_BASE	0x01000000	/* IRQ vectors	addr	*/
-#define	CFG_NIOS_CPU_VEC_SIZE	256		/*		size	*/
-#define	CFG_NIOS_CPU_VEC_NUMS	64		/*		numbers	*/
-#define	CFG_NIOS_CPU_RST_VECT	0x00000000	/* RESET vector	addr	*/
-#define	CFG_NIOS_CPU_DBG_CORE	0		/* CPU debug:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_STACK	0x02000000	/* stack top	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_VEC_BASE	0x01000000	/* IRQ vectors	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_VEC_SIZE	256		/*		size	*/
+#define	CONFIG_SYS_NIOS_CPU_VEC_NUMS	64		/*		numbers	*/
+#define	CONFIG_SYS_NIOS_CPU_RST_VECT	0x00000000	/* RESET vector	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_DBG_CORE	0		/* CPU debug:	no(0)	*/
 						/*		yes(1)	*/
 
 /* The offset address in flash to check for the Nios signature "Ni".
  * (see GM_FlashExec in germs_monitor.s) */
-#define	CFG_NIOS_CPU_EXES_OFFS	0x0C
+#define	CONFIG_SYS_NIOS_CPU_EXES_OFFS	0x0C
 
 /* on-chip extensions */
-#undef	CFG_NIOS_CPU_RAM_BASE			/* on chip RAM	addr	*/
-#undef	CFG_NIOS_CPU_RAM_SIZE			/* 64 KB	size	*/
+#undef	CONFIG_SYS_NIOS_CPU_RAM_BASE			/* on chip RAM	addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_RAM_SIZE			/* 64 KB	size	*/
 
-#define	CFG_NIOS_CPU_ROM_BASE	0x00000000	/* on chip ROM	addr	*/
-#define	CFG_NIOS_CPU_ROM_SIZE	(2 * 1024)	/*  2 KB	size	*/
+#define	CONFIG_SYS_NIOS_CPU_ROM_BASE	0x00000000	/* on chip ROM	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_ROM_SIZE	(2 * 1024)	/*  2 KB	size	*/
 
-#undef	CFG_NIOS_CPU_OCI_BASE			/* OCI core	addr	*/
-#undef	CFG_NIOS_CPU_OCI_SIZE			/*		size	*/
+#undef	CONFIG_SYS_NIOS_CPU_OCI_BASE			/* OCI core	addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_OCI_SIZE			/*		size	*/
 
 /* timer */
-#define	CFG_NIOS_CPU_TIMER_NUMS	1		/* number of timer	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER_NUMS	1		/* number of timer	*/
 
-#define	CFG_NIOS_CPU_TIMER0	0x00000840	/* TIMER0	addr	*/
-#define	CFG_NIOS_CPU_TIMER0_IRQ	16		/*		IRQ	*/
-#define	CFG_NIOS_CPU_TIMER0_PER	1000		/*  periode	usec	*/
-#define	CFG_NIOS_CPU_TIMER0_AR	0		/*  always run:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0	0x00000840	/* TIMER0	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_IRQ	16		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_PER	1000		/*  periode	usec	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_AR	0		/*  always run:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER0_FP	0		/*  fixed per:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_FP	0		/*  fixed per:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER0_SS	1		/*  snaphot:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_SS	1		/*  snaphot:	no(0)	*/
 						/*		yes(1)	*/
 
 /* serial i/o */
-#define	CFG_NIOS_CPU_UART_NUMS	2		/* number of uarts	*/
-
-#define	CFG_NIOS_CPU_UART0	0x00000800	/* UART0	addr	*/
-#define	CFG_NIOS_CPU_UART0_IRQ	17		/*		IRQ	*/
-#define	CFG_NIOS_CPU_UART0_BR	115200		/*  baudrate	var(0)	*/
-#define	CFG_NIOS_CPU_UART0_DB	8		/*  data bit		*/
-#define	CFG_NIOS_CPU_UART0_SB	2		/*  stop bit		*/
-#define	CFG_NIOS_CPU_UART0_PA	0		/*  parity	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART_NUMS	2		/* number of uarts	*/
+
+#define	CONFIG_SYS_NIOS_CPU_UART0	0x00000800	/* UART0	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_IRQ	17		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_BR	115200		/*  baudrate	var(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_DB	8		/*  data bit		*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_SB	2		/*  stop bit		*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_PA	0		/*  parity	none(0)	*/
 						/*		odd(1)	*/
 						/*		even(2)	*/
-#define	CFG_NIOS_CPU_UART0_HS	0		/*  handshake:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_HS	0		/*  handshake:	no(0)	*/
 						/*		crts(1)	*/
-#define	CFG_NIOS_CPU_UART0_EOP	0		/*  eop reg:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_EOP	0		/*  eop reg:	no(0)	*/
 						/*		yes(1)	*/
 
-#define	CFG_NIOS_CPU_UART1	0x000008a0	/* UART1	addr	*/
-#define	CFG_NIOS_CPU_UART1_IRQ	18		/*		IRQ	*/
-#define	CFG_NIOS_CPU_UART1_BR	115200		/*  baudrate	var(0)	*/
-#define	CFG_NIOS_CPU_UART1_DB	8		/*  data bit		*/
-#define	CFG_NIOS_CPU_UART1_SB	1		/*  stop bit		*/
-#define	CFG_NIOS_CPU_UART1_PA	0		/*  parity	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART1	0x000008a0	/* UART1	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_UART1_IRQ	18		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_UART1_BR	115200		/*  baudrate	var(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART1_DB	8		/*  data bit		*/
+#define	CONFIG_SYS_NIOS_CPU_UART1_SB	1		/*  stop bit		*/
+#define	CONFIG_SYS_NIOS_CPU_UART1_PA	0		/*  parity	none(0)	*/
 						/*		odd(1)	*/
 						/*		even(2)	*/
-#define	CFG_NIOS_CPU_UART1_HS	0		/*  handshake:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART1_HS	0		/*  handshake:	no(0)	*/
 						/*		crts(1)	*/
-#define	CFG_NIOS_CPU_UART1_EOP	0		/*  eop reg:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART1_EOP	0		/*  eop reg:	no(0)	*/
 						/*		yes(1)	*/
 
 /* parallel i/o */
-#define	CFG_NIOS_CPU_PIO_NUMS	2		/* number of parports	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO_NUMS	2		/* number of parports	*/
 
-#define	CFG_NIOS_CPU_PIO0	0x00000860	/* PIO0		addr	*/
-#undef	CFG_NIOS_CPU_PIO0_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO0_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO0_TYPE	1		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0	0x00000860	/* PIO0		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO0_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_TYPE	1		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO0_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO0_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO0_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO1	0x00000870	/* PIO1		addr	*/
-#undef	CFG_NIOS_CPU_PIO1_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO1_BITS	4		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO1_TYPE	2		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1	0x00000870	/* PIO1		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO1_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_BITS	4		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_TYPE	2		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO1_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO1_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO1_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
 /* IDE i/f */
-#define	CFG_NIOS_CPU_IDE_NUMS	1		/* number of IDE contr.	*/
-#define	CFG_NIOS_CPU_IDE0	0x00000900	/* IDE0		addr	*/
-#define	CFG_NIOS_CPU_IDE0_IRQ	25		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_IDE_NUMS	1		/* number of IDE contr.	*/
+#define	CONFIG_SYS_NIOS_CPU_IDE0	0x00000900	/* IDE0		addr	*/
+#define	CONFIG_SYS_NIOS_CPU_IDE0_IRQ	25		/*		IRQ	*/
 
 /* memory accessibility */
-#undef	CFG_NIOS_CPU_SRAM_BASE			/* board SRAM	addr	*/
-#undef	CFG_NIOS_CPU_SRAM_SIZE			/*  1 MB	size	*/
+#undef	CONFIG_SYS_NIOS_CPU_SRAM_BASE			/* board SRAM	addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_SRAM_SIZE			/*  1 MB	size	*/
 
-#define	CFG_NIOS_CPU_SDRAM_BASE	0x01000000	/* board SDRAM	addr	*/
-#define	CFG_NIOS_CPU_SDRAM_SIZE	(16*1024*1024)	/* 16 MB	size	*/
+#define	CONFIG_SYS_NIOS_CPU_SDRAM_BASE	0x01000000	/* board SDRAM	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_SDRAM_SIZE	(16*1024*1024)	/* 16 MB	size	*/
 
-#define	CFG_NIOS_CPU_FLASH_BASE	0x00800000	/* board Flash	addr	*/
-#define	CFG_NIOS_CPU_FLASH_SIZE	(8*1024*1024)	/*  8 MB	size	*/
+#define	CONFIG_SYS_NIOS_CPU_FLASH_BASE	0x00800000	/* board Flash	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_FLASH_SIZE	(8*1024*1024)	/*  8 MB	size	*/
 
 /* LAN */
-#define	CFG_NIOS_CPU_LAN_NUMS	1		/* number of LAN i/f	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN_NUMS	1		/* number of LAN i/f	*/
 
-#define	CFG_NIOS_CPU_LAN0_BASE	0x00010000	/* LAN0		addr	*/
-#define	CFG_NIOS_CPU_LAN0_OFFS	0x0300		/*		offset	*/
-#define	CFG_NIOS_CPU_LAN0_IRQ	20		/*		IRQ	*/
-#define	CFG_NIOS_CPU_LAN0_BUSW	32		/*	        buswidth*/
-#define	CFG_NIOS_CPU_LAN0_TYPE	0		/*	smc91111(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_BASE	0x00010000	/* LAN0		addr	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_OFFS	0x0300		/*		offset	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_IRQ	20		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_BUSW	32		/*	        buswidth*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_TYPE	0		/*	smc91111(0)	*/
 						/*	cs8900(1)	*/
 						/* ex:	openmac(2)	*/
 						/* ex:	alteramac(3)	*/
 
 /* symbolic redefinition (undef, if not present) */
-#define	CFG_NIOS_CPU_TICK_TIMER		0	/* TIMER0: tick (needed)*/
-#undef	CFG_NIOS_CPU_USER_TIMER			/* TIMERx: users choice	*/
-
-#define	CFG_NIOS_CPU_CFPOWER_PIO	0	/* PIO0: CF power/sw.	*/
-#define	CFG_NIOS_CPU_BUTTON_PIO		1	/* PIO1: buttons	*/
-#undef	CFG_NIOS_CPU_LCD_PIO			/* PIOx: ASCII LCD	*/
-#undef	CFG_NIOS_CPU_LED_PIO			/* PIOx: LED bar	*/
-#undef	CFG_NIOS_CPU_SEVENSEG_PIO		/* PIOx: 7-seg. display	*/
-#undef	CFG_NIOS_CPU_RECONF_PIO			/* PIOx: reconf pin	*/
-#undef	CFG_NIOS_CPU_CFPRESENT_PIO		/* PIOx: CF present IRQ	*/
-#undef	CFG_NIOS_CPU_CFATASEL_PIO		/* PIOx: CF ATA select	*/
+#define	CONFIG_SYS_NIOS_CPU_TICK_TIMER		0	/* TIMER0: tick (needed)*/
+#undef	CONFIG_SYS_NIOS_CPU_USER_TIMER			/* TIMERx: users choice	*/
+
+#define	CONFIG_SYS_NIOS_CPU_CFPOWER_PIO	0	/* PIO0: CF power/sw.	*/
+#define	CONFIG_SYS_NIOS_CPU_BUTTON_PIO		1	/* PIO1: buttons	*/
+#undef	CONFIG_SYS_NIOS_CPU_LCD_PIO			/* PIOx: ASCII LCD	*/
+#undef	CONFIG_SYS_NIOS_CPU_LED_PIO			/* PIOx: LED bar	*/
+#undef	CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO		/* PIOx: 7-seg. display	*/
+#undef	CONFIG_SYS_NIOS_CPU_RECONF_PIO			/* PIOx: reconf pin	*/
+#undef	CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO		/* PIOx: CF present IRQ	*/
+#undef	CONFIG_SYS_NIOS_CPU_CFATASEL_PIO		/* PIOx: CF ATA select	*/
 
 #endif	/* __CONFIG_DK1S10_MTX_LDK_20_H */
diff --git a/include/configs/DK1S10_safe_32.h b/include/configs/DK1S10_safe_32.h
index 8541a11..ced4ef2 100644
--- a/include/configs/DK1S10_safe_32.h
+++ b/include/configs/DK1S10_safe_32.h
@@ -29,6 +29,6 @@
  *
  * !!! TODO !!! TODO !!!
  */
-#error *** CFG_ERROR: DK1S10_safe_32 have to be defined (use DK1S10_standard_32 as template)
+#error *** CONFIG_SYS_ERROR: DK1S10_safe_32 have to be defined (use DK1S10_standard_32 as template)
 
 #endif	/* __CONFIG_DK1S10_SAFE_32_H */
diff --git a/include/configs/DK1S10_standard_32.h b/include/configs/DK1S10_standard_32.h
index b83c315..e6ccaf5 100644
--- a/include/configs/DK1S10_standard_32.h
+++ b/include/configs/DK1S10_standard_32.h
@@ -30,245 +30,245 @@
  * Here we must define CPU dependencies. Any unsupported option have to
  * be defined with zero, example CPU without data cache / OCI:
  *
- *	#define	CFG_NIOS_CPU_ICACHE	4096
- *	#define	CFG_NIOS_CPU_DCACHE	0
- *	#define	CFG_NIOS_CPU_OCI_BASE	0
- *	#define	CFG_NIOS_CPU_OCI_SIZE	0
+ *	#define	CONFIG_SYS_NIOS_CPU_ICACHE	4096
+ *	#define	CONFIG_SYS_NIOS_CPU_DCACHE	0
+ *	#define	CONFIG_SYS_NIOS_CPU_OCI_BASE	0
+ *	#define	CONFIG_SYS_NIOS_CPU_OCI_SIZE	0
  */
 
 /* CPU core */
-#define	CFG_NIOS_CPU_CLK	50000000	/* NIOS CPU clock	*/
-#define	CFG_NIOS_CPU_ICACHE	(4 * 1024)	/* instruction cache	*/
-#define	CFG_NIOS_CPU_DCACHE	(4 * 1024)	/* data cache		*/
-#define	CFG_NIOS_CPU_REG_NUMS	256		/* number of register	*/
-#define	CFG_NIOS_CPU_MUL	0		/* 16x16 MUL:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_CLK	50000000	/* NIOS CPU clock	*/
+#define	CONFIG_SYS_NIOS_CPU_ICACHE	(4 * 1024)	/* instruction cache	*/
+#define	CONFIG_SYS_NIOS_CPU_DCACHE	(4 * 1024)	/* data cache		*/
+#define	CONFIG_SYS_NIOS_CPU_REG_NUMS	256		/* number of register	*/
+#define	CONFIG_SYS_NIOS_CPU_MUL	0		/* 16x16 MUL:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_MSTEP	1		/* 16x16 MSTEP:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_MSTEP	1		/* 16x16 MSTEP:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_STACK	0x008fff00	/* stack top	addr	*/
-#define	CFG_NIOS_CPU_VEC_BASE	0x008fff00	/* IRQ vectors	addr	*/
-#define	CFG_NIOS_CPU_VEC_SIZE	256		/*		size	*/
-#define	CFG_NIOS_CPU_VEC_NUMS	64		/*		numbers	*/
-#define	CFG_NIOS_CPU_RST_VECT	0x00920000	/* RESET vector	addr	*/
-#define	CFG_NIOS_CPU_DBG_CORE	0		/* CPU debug:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_STACK	0x008fff00	/* stack top	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_VEC_BASE	0x008fff00	/* IRQ vectors	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_VEC_SIZE	256		/*		size	*/
+#define	CONFIG_SYS_NIOS_CPU_VEC_NUMS	64		/*		numbers	*/
+#define	CONFIG_SYS_NIOS_CPU_RST_VECT	0x00920000	/* RESET vector	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_DBG_CORE	0		/* CPU debug:	no(0)	*/
 						/*		yes(1)	*/
 
 /* on-chip extensions */
-#define	CFG_NIOS_CPU_RAM_BASE	0x00900000	/* on chip RAM	addr	*/
-#define	CFG_NIOS_CPU_RAM_SIZE	(64 * 1024)	/* 64 KB	size	*/
+#define	CONFIG_SYS_NIOS_CPU_RAM_BASE	0x00900000	/* on chip RAM	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_RAM_SIZE	(64 * 1024)	/* 64 KB	size	*/
 
-#define	CFG_NIOS_CPU_ROM_BASE	0x00920000	/* on chip ROM	addr	*/
-#define	CFG_NIOS_CPU_ROM_SIZE	(2 * 1024)	/*  2 KB	size	*/
+#define	CONFIG_SYS_NIOS_CPU_ROM_BASE	0x00920000	/* on chip ROM	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_ROM_SIZE	(2 * 1024)	/*  2 KB	size	*/
 
-#define	CFG_NIOS_CPU_OCI_BASE	0x00920800	/* OCI core	addr	*/
-#define	CFG_NIOS_CPU_OCI_SIZE	256		/*		size	*/
+#define	CONFIG_SYS_NIOS_CPU_OCI_BASE	0x00920800	/* OCI core	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_OCI_SIZE	256		/*		size	*/
 
 /* timer */
-#define	CFG_NIOS_CPU_TIMER_NUMS	2		/* number of timer	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER_NUMS	2		/* number of timer	*/
 
-#define	CFG_NIOS_CPU_TIMER0	0x00920940	/* TIMER0	addr	*/
-#define	CFG_NIOS_CPU_TIMER0_IRQ	16		/*		IRQ	*/
-#define	CFG_NIOS_CPU_TIMER0_PER	1000		/*  periode	usec	*/
-#define	CFG_NIOS_CPU_TIMER0_AR	0		/*  always run:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0	0x00920940	/* TIMER0	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_IRQ	16		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_PER	1000		/*  periode	usec	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_AR	0		/*  always run:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER0_FP	0		/*  fixed per:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_FP	0		/*  fixed per:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER0_SS	1		/*  snaphot:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER0_SS	1		/*  snaphot:	no(0)	*/
 						/*		yes(1)	*/
 
-#define	CFG_NIOS_CPU_TIMER1	0x009209e0	/* TIMER1	addr	*/
-#define	CFG_NIOS_CPU_TIMER1_IRQ	50		/*		IRQ	*/
-#define	CFG_NIOS_CPU_TIMER1_PER	10000		/*  periode	usec	*/
-#define	CFG_NIOS_CPU_TIMER1_AR	1		/*  always run:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER1	0x009209e0	/* TIMER1	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER1_IRQ	50		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER1_PER	10000		/*  periode	usec	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER1_AR	1		/*  always run:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER1_FP	1		/*  fixed per:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER1_FP	1		/*  fixed per:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_TIMER1_SS	0		/*  snaphot:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_TIMER1_SS	0		/*  snaphot:	no(0)	*/
 						/*		yes(1)	*/
 
 /* serial i/o */
-#define	CFG_NIOS_CPU_UART_NUMS	1		/* number of uarts	*/
+#define	CONFIG_SYS_NIOS_CPU_UART_NUMS	1		/* number of uarts	*/
 
-#define	CFG_NIOS_CPU_UART0	0x00920900	/* UART0	addr	*/
-#define	CFG_NIOS_CPU_UART0_IRQ	25		/*		IRQ	*/
-#define	CFG_NIOS_CPU_UART0_BR	115200		/*  baudrate	var(0)	*/
-#define	CFG_NIOS_CPU_UART0_DB	8		/*  data bit		*/
-#define	CFG_NIOS_CPU_UART0_SB	1		/*  stop bit		*/
-#define	CFG_NIOS_CPU_UART0_PA	0		/*  parity	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0	0x00920900	/* UART0	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_IRQ	25		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_BR	115200		/*  baudrate	var(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_DB	8		/*  data bit		*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_SB	1		/*  stop bit		*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_PA	0		/*  parity	none(0)	*/
 						/*		odd(1)	*/
 						/*		even(2)	*/
-#define	CFG_NIOS_CPU_UART0_HS	0		/*  handshake:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_HS	0		/*  handshake:	no(0)	*/
 						/*		crts(1)	*/
-#define	CFG_NIOS_CPU_UART0_EOP	0		/*  eop reg:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_UART0_EOP	0		/*  eop reg:	no(0)	*/
 						/*		yes(1)	*/
 
 /* parallel i/o */
-#define	CFG_NIOS_CPU_PIO_NUMS	8		/* number of parports	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO_NUMS	8		/* number of parports	*/
 
-#define	CFG_NIOS_CPU_PIO0	0x00920960	/* PIO0		addr	*/
-#define	CFG_NIOS_CPU_PIO0_IRQ	40		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO0_BITS	4		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO0_TYPE	2		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0	0x00920960	/* PIO0		addr	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_IRQ	40		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_BITS	4		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_TYPE	2		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO0_CAP	1		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_CAP	1		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO0_EDGE	3		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_EDGE	3		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO0_ITYPE	2		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO0_ITYPE	2		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO1	0x00920970	/* PIO1		addr	*/
-#undef	CFG_NIOS_CPU_PIO1_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO1_BITS	11		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO1_TYPE	0		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1	0x00920970	/* PIO1		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO1_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_BITS	11		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_TYPE	0		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO1_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO1_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO1_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO1_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO2	0x00920980	/* PIO2		addr	*/
-#undef	CFG_NIOS_CPU_PIO2_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO2_BITS	8		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO2_TYPE	1		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO2	0x00920980	/* PIO2		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO2_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO2_BITS	8		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO2_TYPE	1		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO2_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO2_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO2_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO2_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO2_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO2_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO3	0x00920990	/* PIO3		addr	*/
-#undef	CFG_NIOS_CPU_PIO3_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO3_BITS	16		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO3_TYPE	1		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3	0x00920990	/* PIO3		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO3_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_BITS	16		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_TYPE	1		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO3_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO3_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO3_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO3_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO4	0x009209a0	/* PIO4		addr	*/
-#undef	CFG_NIOS_CPU_PIO4_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO4_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO4_TYPE	0		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO4	0x009209a0	/* PIO4		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO4_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO4_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO4_TYPE	0		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO4_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO4_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO4_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO4_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO4_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO4_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO5	0x009209b0	/* PIO5		addr	*/
-#define	CFG_NIOS_CPU_PIO5_IRQ	35		/*		IRQ	*/
-#define	CFG_NIOS_CPU_PIO5_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO5_TYPE	2		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5	0x009209b0	/* PIO5		addr	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5_IRQ	35		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5_TYPE	2		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO5_CAP	1		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5_CAP	1		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO5_EDGE	3		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5_EDGE	3		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO5_ITYPE	2		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO5_ITYPE	2		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO6	0x009209c0	/* PIO6		addr	*/
-#undef	CFG_NIOS_CPU_PIO6_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO6_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO6_TYPE	1		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO6	0x009209c0	/* PIO6		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO6_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO6_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO6_TYPE	1		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO6_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO6_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO6_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO6_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO6_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO6_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
-#define	CFG_NIOS_CPU_PIO7	0x009209d0	/* PIO7		addr	*/
-#undef	CFG_NIOS_CPU_PIO7_IRQ			/*		w/o IRQ	*/
-#define	CFG_NIOS_CPU_PIO7_BITS	1		/*  number  of  bits	*/
-#define	CFG_NIOS_CPU_PIO7_TYPE	1		/*  io type:	tris(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO7	0x009209d0	/* PIO7		addr	*/
+#undef	CONFIG_SYS_NIOS_CPU_PIO7_IRQ			/*		w/o IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO7_BITS	1		/*  number  of  bits	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO7_TYPE	1		/*  io type:	tris(0)	*/
 						/*		out(1)	*/
 						/*		in(2)	*/
-#define	CFG_NIOS_CPU_PIO7_CAP	0		/*  capture:	no(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO7_CAP	0		/*  capture:	no(0)	*/
 						/*		yes(1)	*/
-#define	CFG_NIOS_CPU_PIO7_EDGE	0		/*  edge type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO7_EDGE	0		/*  edge type:	none(0)	*/
 						/*		fall(1)	*/
 						/*		rise(2)	*/
 						/*		any(3)	*/
-#define	CFG_NIOS_CPU_PIO7_ITYPE	0		/*  IRQ type:	none(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_PIO7_ITYPE	0		/*  IRQ type:	none(0)	*/
 						/*		level(1)*/
 						/*		edge(2)	*/
 
 /* IDE i/f */
-#define	CFG_NIOS_CPU_IDE_NUMS	1		/* number of IDE contr.	*/
-#define	CFG_NIOS_CPU_IDE0	0x00920a00	/* IDE0		addr	*/
+#define	CONFIG_SYS_NIOS_CPU_IDE_NUMS	1		/* number of IDE contr.	*/
+#define	CONFIG_SYS_NIOS_CPU_IDE0	0x00920a00	/* IDE0		addr	*/
 
 /* memory accessibility */
-#define	CFG_NIOS_CPU_SRAM_BASE	0x00800000	/* board SRAM	addr	*/
-#define	CFG_NIOS_CPU_SRAM_SIZE	(1024 * 1024)	/*  1 MB	size	*/
+#define	CONFIG_SYS_NIOS_CPU_SRAM_BASE	0x00800000	/* board SRAM	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_SRAM_SIZE	(1024 * 1024)	/*  1 MB	size	*/
 
-#define	CFG_NIOS_CPU_SDRAM_BASE	0x01000000	/* board SDRAM	addr	*/
-#define	CFG_NIOS_CPU_SDRAM_SIZE	(16*1024*1024)	/* 16 MB	size	*/
+#define	CONFIG_SYS_NIOS_CPU_SDRAM_BASE	0x01000000	/* board SDRAM	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_SDRAM_SIZE	(16*1024*1024)	/* 16 MB	size	*/
 
-#define	CFG_NIOS_CPU_FLASH_BASE	0x00000000	/* board Flash	addr	*/
-#define	CFG_NIOS_CPU_FLASH_SIZE	(8*1024*1024)	/*  8 MB	size	*/
+#define	CONFIG_SYS_NIOS_CPU_FLASH_BASE	0x00000000	/* board Flash	addr	*/
+#define	CONFIG_SYS_NIOS_CPU_FLASH_SIZE	(8*1024*1024)	/*  8 MB	size	*/
 
 /* LAN */
-#define	CFG_NIOS_CPU_LAN_NUMS	1		/* number of LAN i/f	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN_NUMS	1		/* number of LAN i/f	*/
 
-#define	CFG_NIOS_CPU_LAN0_BASE	0x00910000	/* LAN0		addr	*/
-#define	CFG_NIOS_CPU_LAN0_OFFS	0x0300		/*		offset	*/
-#define	CFG_NIOS_CPU_LAN0_IRQ	30		/*		IRQ	*/
-#define	CFG_NIOS_CPU_LAN0_BUSW	32		/*	        buswidth*/
-#define	CFG_NIOS_CPU_LAN0_TYPE	0		/*	smc91111(0)	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_BASE	0x00910000	/* LAN0		addr	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_OFFS	0x0300		/*		offset	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_IRQ	30		/*		IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_BUSW	32		/*	        buswidth*/
+#define	CONFIG_SYS_NIOS_CPU_LAN0_TYPE	0		/*	smc91111(0)	*/
 						/*	cs8900(1)	*/
 						/* ex:	alteramac(2)	*/
 
 /* symbolic redefinition (undef, if not present) */
-#define	CFG_NIOS_CPU_USER_TIMER		0	/* TIMER0: users choice	*/
-#define	CFG_NIOS_CPU_TICK_TIMER		1	/* TIMER1: tick (needed)*/
+#define	CONFIG_SYS_NIOS_CPU_USER_TIMER		0	/* TIMER0: users choice	*/
+#define	CONFIG_SYS_NIOS_CPU_TICK_TIMER		1	/* TIMER1: tick (needed)*/
 
-#define	CFG_NIOS_CPU_BUTTON_PIO		0	/* PIO0: buttons	*/
-#define	CFG_NIOS_CPU_LCD_PIO		1	/* PIO1: ASCII LCD	*/
-#define	CFG_NIOS_CPU_LED_PIO		2	/* PIO2: LED bar	*/
-#define	CFG_NIOS_CPU_SEVENSEG_PIO	3	/* PIO3: 7-seg. display	*/
-#define	CFG_NIOS_CPU_RECONF_PIO		4	/* PIO4: reconf pin	*/
-#define	CFG_NIOS_CPU_CFPRESENT_PIO	5	/* PIO5: CF present IRQ	*/
-#define	CFG_NIOS_CPU_CFPOWER_PIO	6	/* PIO6: CF power/sw.	*/
-#define	CFG_NIOS_CPU_CFATASEL_PIO	7	/* PIO7: CF ATA select	*/
+#define	CONFIG_SYS_NIOS_CPU_BUTTON_PIO		0	/* PIO0: buttons	*/
+#define	CONFIG_SYS_NIOS_CPU_LCD_PIO		1	/* PIO1: ASCII LCD	*/
+#define	CONFIG_SYS_NIOS_CPU_LED_PIO		2	/* PIO2: LED bar	*/
+#define	CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO	3	/* PIO3: 7-seg. display	*/
+#define	CONFIG_SYS_NIOS_CPU_RECONF_PIO		4	/* PIO4: reconf pin	*/
+#define	CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO	5	/* PIO5: CF present IRQ	*/
+#define	CONFIG_SYS_NIOS_CPU_CFPOWER_PIO	6	/* PIO6: CF power/sw.	*/
+#define	CONFIG_SYS_NIOS_CPU_CFATASEL_PIO	7	/* PIO7: CF ATA select	*/
 
 #endif	/* __CONFIG_DK1S10_STANDARD_32_H */
diff --git a/include/configs/DP405.h b/include/configs/DP405.h
index acc2bd2..187547d 100644
--- a/include/configs/DP405.h
+++ b/include/configs/DP405.h
@@ -50,8 +50,9 @@
 
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
@@ -82,7 +83,7 @@
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
+#define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
@@ -91,50 +92,49 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
 #undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -151,66 +151,66 @@
 
 #undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
 #endif
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-
-#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CFG_RAMBOOT		1
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CONFIG_SYS_RAMBOOT		1
 #else
-# undef CFG_RAMBOOT
+# undef CONFIG_SYS_RAMBOOT
 #endif
 
 /*-----------------------------------------------------------------------
@@ -221,25 +221,24 @@
 #define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */
 
-#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
@@ -249,47 +248,47 @@
 #define RTC_BA		0xF0000500	    /* RTC Base Address			*/
 
 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 #if 0 /* test-only */
 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
 #endif
 
 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
-#define CFG_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
-#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
+#define CONFIG_SYS_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
+#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
-#define CFG_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
-#define CFG_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
-#define CFG_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
 
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup (PPC405EP specific)
@@ -307,13 +306,13 @@
 /* GPIO Output:		OSR=00, ISR=00, TSR=00, TCR=1 */
 /* Alt. Funtion Input:	OSR=00, ISR=01, TSR=00, TCR=0 */
 /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
-#define CFG_GPIO0_OSRH		0x40000540  /*	0 ... 15 */
-#define CFG_GPIO0_OSRL		0x00000110  /* 16 ... 31 */
-#define CFG_GPIO0_ISR1H		0x00000000  /*	0 ... 15 */
-#define CFG_GPIO0_ISR1L		0x14000045  /* 16 ... 31 */
-#define CFG_GPIO0_TSRH		0x00000000  /*	0 ... 15 */
-#define CFG_GPIO0_TSRL		0x00000000  /* 16 ... 31 */
-#define CFG_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */
+#define CONFIG_SYS_GPIO0_OSRH		0x40000540  /*	0 ... 15 */
+#define CONFIG_SYS_GPIO0_OSRL		0x00000110  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_ISR1H		0x00000000  /*	0 ... 15 */
+#define CONFIG_SYS_GPIO0_ISR1L		0x14000045  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000  /*	0 ... 15 */
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */
 
 /*
  * Internal Definitions
diff --git a/include/configs/DU405.h b/include/configs/DU405.h
index 7debc69..1d20efe 100644
--- a/include/configs/DU405.h
+++ b/include/configs/DU405.h
@@ -52,8 +52,9 @@
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
@@ -88,44 +89,44 @@
 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_RTC_MC146818		/* BQ3285 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000080 /* RTC Base Address		*/
+#define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000080 /* RTC Base Address		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_EXT_SERIAL_CLOCK	11059200  /* use external serial clock	*/
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200  /* use external serial clock	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -144,14 +145,14 @@
 
 #define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0404	/* PCI Device ID: CPCI-ISER4	*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffe00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404	/* PCI Device ID: CPCI-ISER4	*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffe00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
@@ -161,71 +162,70 @@
 #undef	CONFIG_IDE_LED			/* no led for ide supported	*/
 #undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
 
-#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR	0xF0100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFD0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFD0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC08) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
 #define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
@@ -257,36 +257,36 @@
 #define FPGA_MODE_REG	(DUART_BA+0x80)	    /* FPGA Mode Register		*/
 
 /* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP	0x92015480
-#define CFG_EBC_PB0CR	FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP	0x92015480
+#define CONFIG_SYS_EBC_PB0CR	FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (Flash Bank 1) initialization					*/
-#define CFG_EBC_PB1AP	0x92015480
-#define CFG_EBC_PB1CR	FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB1AP	0x92015480
+#define CONFIG_SYS_EBC_PB1CR	FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 2 (CAN0) initialization						*/
-#define CFG_EBC_PB2AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR	CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR	CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 3 (DUART) initialization						*/
-#define CFG_EBC_PB3AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR	DUART_BA | 0x18000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB3AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR	DUART_BA | 0x18000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 4 (CompactFlash IDE) initialization				*/
-#define CFG_EBC_PB4AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB4CR	CF_BA | 0x1A000	    /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB4AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB4CR	CF_BA | 0x1A000	    /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 5 (SRAM) initialization						*/
-#define CFG_EBC_PB5AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB5CR	SRAM_BA | 0x1A000   /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB5AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB5CR	SRAM_BA | 0x1A000   /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 6 (DURAG Bus IO Space) initialization				*/
-#define CFG_EBC_PB6AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB6CR	DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/
+#define CONFIG_SYS_EBC_PB6AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB6CR	DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/
 
 /* Memory Bank 7 (DURAG Bus Mem Space) initialization				*/
-#define CFG_EBC_PB7AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB7CR	DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB7AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB7CR	DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
 
 
 /*-----------------------------------------------------------------------
@@ -294,17 +294,17 @@
  */
 
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 
 /*
diff --git a/include/configs/DU440.h b/include/configs/DU440.h
index 9f8c423..85c0e61 100644
--- a/include/configs/DU440.h
+++ b/include/configs/DU440.h
@@ -45,53 +45,52 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor */
-#define CFG_MALLOC_LEN		(8 << 20)	/* Reserve 8 MB for malloc()  */
-
-#define CFG_BOOT_BASE_ADDR	0xf0000000
-#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
-#define CFG_FLASH_BASE		0xfc000000	/* start of FLASH	*/
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_NAND0_ADDR		0xd0000000      /* NAND Flash		*/
-#define CFG_NAND1_ADDR		0xd0100000      /* NAND Flash		*/
-#define CFG_OCM_BASE		0xe0010000      /* ocm			*/
-#define CFG_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
-#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
-#define CFG_PCI_MEMBASE1	CFG_PCI_MEMBASE  + 0x10000000
-#define CFG_PCI_MEMBASE2	CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3	CFG_PCI_MEMBASE2 + 0x10000000
-#define CFG_PCI_IOBASE          0xe8000000
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(8 << 20)	/* Reserve 8 MB for malloc()  */
+
+#define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CONFIG_SYS_FLASH_BASE		0xfc000000	/* start of FLASH	*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_NAND0_ADDR		0xd0000000      /* NAND Flash		*/
+#define CONFIG_SYS_NAND1_ADDR		0xd0100000      /* NAND Flash		*/
+#define CONFIG_SYS_OCM_BASE		0xe0010000      /* ocm			*/
+#define CONFIG_SYS_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CONFIG_SYS_PCI_MEMBASE1	CONFIG_SYS_PCI_MEMBASE  + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2	CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3	CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
+#define CONFIG_SYS_PCI_IOBASE          0xe8000000
 
 
 /* Don't change either of these */
-#define CFG_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
+#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
 
-#define CFG_USB2D0_BASE		0xe0000100
-#define CFG_USB_DEVICE		0xe0000000
-#define CFG_USB_HOST		0xe0000400
+#define CONFIG_SYS_USB2D0_BASE		0xe0000100
+#define CONFIG_SYS_USB_DEVICE		0xe0000000
+#define CONFIG_SYS_USB_HOST		0xe0000400
 
 /*
  * Initial RAM & stack pointer
  */
 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
-#define CFG_INIT_RAM_OCM	1		/* OCM as init ram	*/
-#define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM			*/
+#define CONFIG_SYS_INIT_RAM_OCM	1		/* OCM as init ram	*/
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
 
-#define CFG_INIT_RAM_END	(4 << 10)
-#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Serial Port
  */
-/* TODO: external clock oscillator will be removed */
-#define CFG_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SERIAL_MULTI     1
 #undef CONFIG_UART1_CONSOLE
 
-#define CFG_BAUDRATE_TABLE						\
+#define CONFIG_SYS_BAUDRATE_TABLE						\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
 /*
@@ -105,10 +104,10 @@
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
 #define CONFIG_VIDEO_BMP_GZIP              /* gzip compressed bmp images */
-#define CFG_VIDEO_LOGO_MAX_SIZE (4 << 20)  /* for decompressed img */
-#define CFG_DEFAULT_VIDEO_MODE 0x31a       /* 1280x1024,16bpp */
-#define CFG_CONSOLE_IS_IN_ENV
-#define CFG_ISA_IO CFG_PCI_IOBASE
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4 << 20)  /* for decompressed img */
+#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x31a       /* 1280x1024,16bpp */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_ISA_IO CONFIG_SYS_PCI_IOBASE
 
 /*
  * Environment
@@ -118,27 +117,27 @@
 /*
  * FLASH related
  */
-#define CFG_FLASH_CFI			/* The flash is CFI compatible */
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible */
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver       */
 
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	      */
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip  */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	      */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip  */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)    */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)    */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)    */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)    */
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)   */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)   */
 /* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
-#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection      */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection      */
 
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash      */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash      */
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* size of one complete sector        */
-#define CONFIG_ENV_ADDR		((-CFG_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector   */
 
 /* Address and size of Redundant Environment Sector	*/
@@ -155,9 +154,9 @@
 /*
  * DDR SDRAM
  */
-#define CFG_MBYTES_SDRAM        (1024)	/* 512 MiB      TODO: remove    */
+#define CONFIG_SYS_MBYTES_SDRAM        (1024)	/* 512 MiB      TODO: remove    */
 #define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization        */
-#define CFG_MEM_TOP_HIDE        (4 << 10) /* don't use last 4kbytes     */
+#define CONFIG_SYS_MEM_TOP_HIDE        (4 << 10) /* don't use last 4kbytes     */
 					/* 440EPx errata CHIP 11        */
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup     */
 #define CONFIG_DDR_ECC			/* Use ECC when available       */
@@ -169,27 +168,26 @@
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support    */
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged	        */
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address  */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address  */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_I2C_CMD_TREE     1
 #define CONFIG_I2C_MULTI_BUS    1
 
-#define CFG_SPD_BUS_NUM         0
+#define CONFIG_SYS_SPD_BUS_NUM         0
 #define IIC1_MCP3021_ADDR	0x4d
 #define IIC1_USB2507_ADDR	0x2c
 #ifdef CONFIG_I2C_MULTI_BUS
-#define CFG_I2C_NOPROBES        {{1, IIC1_USB2507_ADDR}}
+#define CONFIG_SYS_I2C_NOPROBES        {{1, IIC1_USB2507_ADDR}}
 #endif
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	0x54
-#define CFG_I2C_EEPROM_ADDR_LEN 2
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 5
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
 
-#define CFG_EEPROM_WREN         1
-#define CFG_I2C_BOOT_EEPROM_ADDR 0x52
+#define CONFIG_SYS_EEPROM_WREN         1
+#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
 
 /*
  * standard dtt sensor configuration - bottom bit will determine local or
@@ -209,13 +207,13 @@
  * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
  */
 #define CONFIG_DTT_ADM1021
-#define CFG_DTT_ADM1021		{ { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
+#define CONFIG_SYS_DTT_ADM1021		{ { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
 
 /*
  * RTC stuff
  */
 #define CONFIG_RTC_DS1338
-#define CFG_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
 
 #undef	CONFIG_BOOTARGS
 
@@ -249,12 +247,13 @@
 #define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #ifndef __ASSEMBLY__
 int du440_phy_addr(int devnum);
 #endif
 
+#define CONFIG_PPC4xx_EMAC
 #define	CONFIG_IBM_EMAC4_V4	1
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		du440_phy_addr(0) /* PHY address	*/
@@ -263,7 +262,7 @@ int du440_phy_addr(int devnum);
 #undef CONFIG_PHY_GIGE			/* no GbE detection		*/
 
 #define CONFIG_HAS_ETH0
-#define CFG_RX_ETH_BUFFER	128
+#define CONFIG_SYS_RX_ETH_BUFFER	128
 
 #define CONFIG_NET_MULTI	1
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
@@ -274,12 +273,12 @@ int du440_phy_addr(int devnum);
  */
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_STORAGE
-#define CFG_OHCI_BE_CONTROLLER
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
 
-#define CFG_USB_OHCI_CPU_INIT	1
-#define CFG_USB_OHCI_REGS_BASE	CFG_USB_HOST
-#define CFG_USB_OHCI_SLOT_NAME	"du440"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS	15
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	CONFIG_SYS_USB_HOST
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"du440"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
 
 /* Comment this out to enable USB 1.1 device */
 #define USB_2_0_DEVICE
@@ -319,25 +318,25 @@ int du440_phy_addr(int devnum);
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
 #endif
 /* Print Buffer Size */
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00400000 /* memtest works on		*/
-#define CFG_MEMTEST_END		0x3f000000 /* 4 ... < 1GB DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00400000 /* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x3f000000 /* 4 ... < 1GB DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
+#define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
@@ -357,65 +356,64 @@ int du440_phy_addr(int devnum);
 #define CONFIG_PCI			/* include pci support	        */
 #define CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
-#define CFG_PCI_TARGBASE       0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+#define CONFIG_SYS_PCI_TARGBASE       0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT
-#define CFG_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)     /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)     /* Initial Memory map for Linux */
 
 /*
  * External Bus Controller (EBC) Setup
  */
-#define CFG_FLASH		CFG_FLASH_BASE
+#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE
 
-#define CFG_CPLD_BASE		0xC0000000
-#define CFG_CPLD_RANGE	        0x00000010
-#define CFG_DUMEM_BASE		0xC0100000
-#define CFG_DUMEM_RANGE		0x00100000
-#define CFG_DUIO_BASE		0xC0200000
-#define CFG_DUIO_RANGE	        0x00010000
+#define CONFIG_SYS_CPLD_BASE		0xC0000000
+#define CONFIG_SYS_CPLD_RANGE	        0x00000010
+#define CONFIG_SYS_DUMEM_BASE		0xC0100000
+#define CONFIG_SYS_DUMEM_RANGE		0x00100000
+#define CONFIG_SYS_DUIO_BASE		0xC0200000
+#define CONFIG_SYS_DUIO_RANGE	        0x00010000
 
-#define CFG_NAND0_CS		2		/* NAND chip connected to CSx */
-#define CFG_NAND1_CS		3		/* NAND chip connected to CSx */
+#define CONFIG_SYS_NAND0_CS		2		/* NAND chip connected to CSx */
+#define CONFIG_SYS_NAND1_CS		3		/* NAND chip connected to CSx */
 /* Memory Bank 0 (NOR-FLASH) initialization */
-#define CFG_EBC_PB0AP		0x04017200
-#define CFG_EBC_PB0CR		(CFG_FLASH_BASE | 0xda000)
+#define CONFIG_SYS_EBC_PB0AP		0x04017200
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
 
 /* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
-#define CFG_EBC_PB1AP		0x018003c0
-#define CFG_EBC_PB1CR		(CFG_CPLD_BASE | 0x18000)
+#define CONFIG_SYS_EBC_PB1AP		0x018003c0
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_CPLD_BASE | 0x18000)
 
 /* Memory Bank 2 (NAND-FLASH) initialization */
-#define CFG_EBC_PB2AP		0x018003c0
-#define CFG_EBC_PB2CR		(CFG_NAND0_ADDR | 0x1c000)
+#define CONFIG_SYS_EBC_PB2AP		0x018003c0
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_NAND0_ADDR | 0x1c000)
 
 /* Memory Bank 3 (NAND-FLASH) initialization */
-#define CFG_EBC_PB3AP		0x018003c0
-#define CFG_EBC_PB3CR		(CFG_NAND1_ADDR | 0x1c000)
+#define CONFIG_SYS_EBC_PB3AP		0x018003c0
+#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_NAND1_ADDR | 0x1c000)
 
 /* Memory Bank 4 (DUMEM, 1MB) initialization */
-#define CFG_EBC_PB4AP		0x018053c0
-#define CFG_EBC_PB4CR		(CFG_DUMEM_BASE | 0x18000)
+#define CONFIG_SYS_EBC_PB4AP		0x018053c0
+#define CONFIG_SYS_EBC_PB4CR		(CONFIG_SYS_DUMEM_BASE | 0x18000)
 
 /* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
-#define CFG_EBC_PB5AP		0x018053c0
-#define CFG_EBC_PB5CR		(CFG_DUIO_BASE | 0x18000)
+#define CONFIG_SYS_EBC_PB5AP		0x018053c0
+#define CONFIG_SYS_EBC_PB5CR		(CONFIG_SYS_DUIO_BASE | 0x18000)
 
 /*
  * NAND FLASH
  */
-#define CFG_MAX_NAND_DEVICE	2
-#define NAND_MAX_CHIPS		CFG_MAX_NAND_DEVICE
-#define CFG_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips */
-#define CFG_NAND_BASE_LIST	{CFG_NAND0_ADDR + CFG_NAND0_CS, \
-				 CFG_NAND1_ADDR + CFG_NAND1_CS}
+#define CONFIG_SYS_MAX_NAND_DEVICE	2
+#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips */
+#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
+				 CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}
 
 /*
  * Internal Definitions
@@ -432,4 +430,7 @@ int du440_phy_addr(int devnum);
 
 #define CONFIG_AUTOSCRIPT	1
 
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
index a949454..a13db7c 100644
--- a/include/configs/EB+MCF-EV123.h
+++ b/include/configs/EB+MCF-EV123.h
@@ -27,7 +27,7 @@
 
 #define  CONFIG_EB_MCF_EV123
 
-#undef CFG_HALT_BEFOR_RAM_JUMP
+#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
 
 /*
  * High Level Configuration Options (easy to change)
@@ -39,9 +39,9 @@
 #define CONFIG_MISC_INIT_R
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE 9600
-#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef	CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */
 
@@ -91,22 +91,22 @@
 #	define CONFIG_NET_MULTI		1
 #	define CONFIG_MII		1
 #	define CONFIG_MII_INIT		1
-#	define CFG_DISCOVER_PHY
-#	define CFG_RX_ETH_BUFFER	8
-#	define CFG_FAULT_ECHO_LINK_DOWN
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 
-#	define CFG_FEC0_PINMUX		0
-#	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
 #	define MCFFEC_TOUT_LOOP		50000
-/* If CFG_DISCOVER_PHY is not defined - hardcoded */
-#	ifndef CFG_DISCOVER_PHY
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
 #		define FECDUPLEX	FULL
 #		define FECSPEED		_100BASET
 #	else
-#		ifndef CFG_FAULT_ECHO_LINK_DOWN
-#			define CFG_FAULT_ECHO_LINK_DOWN
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #		endif
-#	endif			/* CFG_DISCOVER_PHY */
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
 #endif
 
 #ifdef CONFIG_MCFFEC
@@ -119,146 +119,142 @@
 #endif				/* CONFIG_MCFFEC */
 
 #define CONFIG_BOOTDELAY	5
-#define CFG_PROMPT		"\nEV123 U-Boot> "
-#define	CFG_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"\nEV123 U-Boot> "
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_LOAD_ADDR		0x20000
+#define CONFIG_SYS_LOAD_ADDR		0x20000
 
-#define CFG_MEMTEST_START	0x100000
-#define CFG_MEMTEST_END		0x400000
-/*#define CFG_DRAM_TEST		1 */
-#undef CFG_DRAM_TEST
+#define CONFIG_SYS_MEMTEST_START	0x100000
+#define CONFIG_SYS_MEMTEST_END		0x400000
+/*#define CONFIG_SYS_DRAM_TEST		1 */
+#undef CONFIG_SYS_DRAM_TEST
 
 /* Clock and PLL Configuration */
-#define CFG_HZ			10000000
-#define	CFG_CLK			58982400       /* 9,8304MHz * 6 */
+#define CONFIG_SYS_HZ			10000000
+#define	CONFIG_SYS_CLK			58982400       /* 9,8304MHz * 6 */
 
 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
 
-#define CFG_MFD			0x01	/* PLL Multiplication Factor Devider */
-#define CFG_RFD			0x00	/* PLL Reduce Frecuency Devider */
+#define CONFIG_SYS_MFD			0x01	/* PLL Multiplication Factor Devider */
+#define CONFIG_SYS_RFD			0x00	/* PLL Reduce Frecuency Devider */
 
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
  * You should know what you are doing if you make changes here.
  */
-#define	CFG_MBAR		0x40000000
+#define	CONFIG_SYS_MBAR		0x40000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR       0x20000000
-#define CFG_INIT_RAM_END	0x10000		/* End of used area in internal SRAM	*/
-#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR       0x20000000
+#define CONFIG_SYS_INIT_RAM_END	0x10000		/* End of used area in internal SRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE1		0x00000000
-#define	CFG_SDRAM_SIZE1		16		/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_BASE1		0x00000000
+#define	CONFIG_SYS_SDRAM_SIZE1		16		/* SDRAM size in MB */
 
 /*
-#define CFG_SDRAM_BASE0		CFG_SDRAM_BASE1+CFG_SDRAM_SIZE1*1024*1024
-#define	CFG_SDRAM_SIZE0		16	*/	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_BASE0		CONFIG_SYS_SDRAM_BASE1+CONFIG_SYS_SDRAM_SIZE1*1024*1024
+#define	CONFIG_SYS_SDRAM_SIZE0		16	*/	/* SDRAM size in MB */
 
-#define CFG_SDRAM_BASE		CFG_SDRAM_BASE1
-#define	CFG_SDRAM_SIZE		CFG_SDRAM_SIZE1
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_SDRAM_BASE1
+#define	CONFIG_SYS_SDRAM_SIZE		CONFIG_SYS_SDRAM_SIZE1
 
-#define CFG_FLASH_BASE		0xFFE00000
-#define	CFG_INT_FLASH_BASE	0xF0000000
-#define CFG_INT_FLASH_ENABLE	0x21
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#define	CONFIG_SYS_INT_FLASH_BASE	0xF0000000
+#define CONFIG_SYS_INT_FLASH_ENABLE	0x21
 
 /* If M5282 port is fully implemented the monitor base will be behind
  * the vector table. */
-#if (TEXT_BASE !=  CFG_INT_FLASH_BASE)
-#define CFG_MONITOR_BASE	(TEXT_BASE + 0x400)
+#if (TEXT_BASE !=  CONFIG_SYS_INT_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_BASE	(TEXT_BASE + 0x400)
 #else
-#define CFG_MONITOR_BASE	(TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
+#define CONFIG_SYS_MONITOR_BASE	(TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
 #endif
 
-#define CFG_MONITOR_LEN		0x20000
-#define CFG_MALLOC_LEN		(256 << 10)
-#define CFG_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define	CFG_MAX_FLASH_SECT	35
-#define	CFG_MAX_FLASH_BANKS	2
-#define	CFG_FLASH_ERASE_TOUT	10000000
-#define	CFG_FLASH_PROTECTION
+#define	CONFIG_SYS_MAX_FLASH_SECT	35
+#define	CONFIG_SYS_MAX_FLASH_BANKS	2
+#define	CONFIG_SYS_FLASH_ERASE_TOUT	10000000
+#define	CONFIG_SYS_FLASH_PROTECTION
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
 
-#define CFG_CS0_BASE		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		2*1024*1024
-#define CFG_CS0_WIDTH		16
-#define CFG_CS0_RO		0
-#define CFG_CS0_WS		6
+#define CONFIG_SYS_CS0_BASE		0xFFE00000
+#define CONFIG_SYS_CS0_CTRL		0x00001980
+#define CONFIG_SYS_CS0_MASK		0x001F0001
 
-#define CFG_CS3_BASE		0xE0000000
-#define CFG_CS3_SIZE		1*1024*1024
-#define CFG_CS3_WIDTH		16
-#define CFG_CS3_RO		0
-#define CFG_CS3_WS		6
+#define CONFIG_SYS_CS3_BASE		0xE0000000
+#define CONFIG_SYS_CS0_CTRL		0x00001980
+#define CONFIG_SYS_CS3_MASK		0x000F0001
 
 /*-----------------------------------------------------------------------
  * Port configuration
  */
-#define CFG_PACNT		0x0000000	/* Port A D[31:24] */
-#define CFG_PADDR		0x0000000
-#define CFG_PADAT		0x0000000
+#define CONFIG_SYS_PACNT		0x0000000	/* Port A D[31:24] */
+#define CONFIG_SYS_PADDR		0x0000000
+#define CONFIG_SYS_PADAT		0x0000000
 
-#define CFG_PBCNT		0x0000000	/* Port B D[23:16] */
-#define CFG_PBDDR		0x0000000
-#define CFG_PBDAT		0x0000000
+#define CONFIG_SYS_PBCNT		0x0000000	/* Port B D[23:16] */
+#define CONFIG_SYS_PBDDR		0x0000000
+#define CONFIG_SYS_PBDAT		0x0000000
 
-#define CFG_PCCNT		0x0000000	/* Port C D[15:08] */
-#define CFG_PCDDR		0x0000000
-#define CFG_PCDAT		0x0000000
+#define CONFIG_SYS_PCCNT		0x0000000	/* Port C D[15:08] */
+#define CONFIG_SYS_PCDDR		0x0000000
+#define CONFIG_SYS_PCDAT		0x0000000
 
-#define CFG_PDCNT		0x0000000	/* Port D D[07:00] */
-#define CFG_PCDDR		0x0000000
-#define CFG_PCDAT		0x0000000
+#define CONFIG_SYS_PDCNT		0x0000000	/* Port D D[07:00] */
+#define CONFIG_SYS_PCDDR		0x0000000
+#define CONFIG_SYS_PCDAT		0x0000000
 
-#define CFG_PEHLPAR		0xC0
-#define CFG_PUAPAR		0x0F		/* UA0..UA3 = Uart 0 +1 */
-#define CFG_DDRUA		0x05
-#define CFG_PJPAR		0xFF;
+#define CONFIG_SYS_PEHLPAR		0xC0
+#define CONFIG_SYS_PUAPAR		0x0F		/* UA0..UA3 = Uart 0 +1 */
+#define CONFIG_SYS_DDRUA		0x05
+#define CONFIG_SYS_PJPAR		0xFF
 
 /*-----------------------------------------------------------------------
  * CCM configuration
  */
 
-#define	CFG_CCM_SIZ		0
+#define	CONFIG_SYS_CCM_SIZ		0
 
 /*---------------------------------------------------------------------*/
 #endif	/* _CONFIG_M5282EVB_H */
diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h
index 08e3d71..7939266 100644
--- a/include/configs/ELPPC.h
+++ b/include/configs/ELPPC.h
@@ -63,7 +63,7 @@
     "bootm"
 
 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
-#define CFG_LOADS_BAUD_CHANGE           /* allow baudrate changes */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE           /* allow baudrate changes */
 
 /*
  * BOOTP options
@@ -88,8 +88,8 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP                    /* undef to save memory */
-#define CFG_PROMPT              "=> "   /* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP                    /* undef to save memory */
+#define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt */
 
 /*
  * choose between COM1 and COM2 as serial console
@@ -97,72 +97,72 @@
 #define CONFIG_CONS_INDEX       1
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE              1024        /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE              1024        /* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE              256         /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE              256         /* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS             16          /* max number of command args    */
-#define CFG_BARGSIZE            CFG_CBSIZE  /* Boot Argument Buffer Size    */
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS             16          /* max number of command args    */
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START       0x00000000  /* memtest works on    */
-#define CFG_MEMTEST_END         0x04000000  /* 0 ... 64 MB in DRAM    */
+#define CONFIG_SYS_MEMTEST_START       0x00000000  /* memtest works on    */
+#define CONFIG_SYS_MEMTEST_END         0x04000000  /* 0 ... 64 MB in DRAM    */
 
-#define CFG_LOAD_ADDR           0x1000000   /* default load address    */
+#define CONFIG_SYS_LOAD_ADDR           0x1000000   /* default load address    */
 
-#define CFG_HZ                  1000        /* dec. freq: 1 ms ticks */
+#define CONFIG_SYS_HZ                  1000        /* dec. freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
  * You should know what you are doing if you make changes here.
  */
-#define CFG_BOARD_ASM_INIT
+#define CONFIG_SYS_BOARD_ASM_INIT
 #define CONFIG_MISC_INIT_R
 
 /*
  * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP)
  */
-#undef  CFG_ADDRESS_MAP_A
+#undef  CONFIG_SYS_ADDRESS_MAP_A
 
-#define CFG_PCI_MEMORY_BUS      0x00000000
-#define CFG_PCI_MEMORY_PHYS     0x00000000
-#define CFG_PCI_MEMORY_SIZE     0x40000000
+#define CONFIG_SYS_PCI_MEMORY_BUS      0x00000000
+#define CONFIG_SYS_PCI_MEMORY_PHYS     0x00000000
+#define CONFIG_SYS_PCI_MEMORY_SIZE     0x40000000
 
-#define CFG_PCI_MEM_BUS         0x80000000
-#define CFG_PCI_MEM_PHYS        0x80000000
-#define CFG_PCI_MEM_SIZE        0x7d000000
+#define CONFIG_SYS_PCI_MEM_BUS         0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS        0x80000000
+#define CONFIG_SYS_PCI_MEM_SIZE        0x7d000000
 
-#define CFG_ISA_MEM_BUS         0x00000000
-#define CFG_ISA_MEM_PHYS        0xfd000000
-#define CFG_ISA_MEM_SIZE        0x01000000
+#define CONFIG_SYS_ISA_MEM_BUS         0x00000000
+#define CONFIG_SYS_ISA_MEM_PHYS        0xfd000000
+#define CONFIG_SYS_ISA_MEM_SIZE        0x01000000
 
-#define CFG_PCI_IO_BUS          0x00800000
-#define CFG_PCI_IO_PHYS         0xfe800000
-#define CFG_PCI_IO_SIZE         0x00400000
+#define CONFIG_SYS_PCI_IO_BUS          0x00800000
+#define CONFIG_SYS_PCI_IO_PHYS         0xfe800000
+#define CONFIG_SYS_PCI_IO_SIZE         0x00400000
 
-#define CFG_ISA_IO_BUS          0x00000000
-#define CFG_ISA_IO_PHYS         0xfe000000
-#define CFG_ISA_IO_SIZE         0x00800000
+#define CONFIG_SYS_ISA_IO_BUS          0x00000000
+#define CONFIG_SYS_ISA_IO_PHYS         0xfe000000
+#define CONFIG_SYS_ISA_IO_SIZE         0x00800000
 
 /* driver defines FDC,IDE,... */
-#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
-#define CFG_ISA_IO              CFG_ISA_IO_PHYS
-#define CFG_60X_PCI_IO_OFFSET   CFG_ISA_IO_PHYS
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
+#define CONFIG_SYS_ISA_IO              CONFIG_SYS_ISA_IO_PHYS
+#define CONFIG_SYS_60X_PCI_IO_OFFSET   CONFIG_SYS_ISA_IO_PHYS
 
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE          0x00000000
+#define CONFIG_SYS_SDRAM_BASE          0x00000000
 
-#define CFG_USR_LED_BASE        0x78000000
-#define CFG_NVRAM_BASE          0xff000000
-#define CFG_UART_BASE           0xff400000
-#define CFG_FLASH_BASE          0xfff00000
+#define CONFIG_SYS_USR_LED_BASE        0x78000000
+#define CONFIG_SYS_NVRAM_BASE          0xff000000
+#define CONFIG_SYS_UART_BASE           0xff400000
+#define CONFIG_SYS_FLASH_BASE          0xfff00000
 
 #define MPC107_EUMB_ADDR        0xfce00000
 #define MPC107_EUMB_PI          0xfce41090
@@ -173,11 +173,11 @@
 /*
  * Definitions for initial stack pointer and data area
  */
-#define CFG_INIT_RAM_ADDR       0x00fd0000  /* above the memtest region */
-#define CFG_INIT_RAM_END        0x4000
-#define CFG_GBL_DATA_SIZE       64          /* size in bytes reserved for init data */
-#define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR       0x00fd0000  /* above the memtest region */
+#define CONFIG_SYS_INIT_RAM_END        0x4000
+#define CONFIG_SYS_GBL_DATA_SIZE       64          /* size in bytes reserved for init data */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Flash mapping/organization on the MPC10x.
@@ -185,11 +185,11 @@
 #define FLASH_BASE0_PRELIM      0xff800000
 #define FLASH_BASE1_PRELIM      0xffc00000
 
-#define CFG_MAX_FLASH_BANKS     2           /* max number of memory banks    */
-#define CFG_MAX_FLASH_SECT      67          /* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS     2           /* max number of memory banks    */
+#define CONFIG_SYS_MAX_FLASH_SECT      67          /* max number of sectors on one chip */
 
-#define CFG_FLASH_ERASE_TOUT    120000      /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT    500         /* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT    120000      /* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500         /* Timeout for Flash Write (in ms) */
 
 /*
  * JFFS2 partitions
@@ -209,33 +209,33 @@
 #define MTDPARTS_DEFAULT	"mtdparts=elppc-0:-(jffs2),elppc-1:-(user)"
 */
 
-#define CFG_MONITOR_BASE        CFG_FLASH_BASE
-#define CFG_MONITOR_LEN         0x40000     /* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN          0x20000     /* Reserve 128 kB for malloc() */
-#undef  CFG_MEMTEST
+#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN         0x40000     /* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN          0x20000     /* Reserve 128 kB for malloc() */
+#undef  CONFIG_SYS_MEMTEST
 
 /*
  * Environment settings
  */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_ENV_IS_IN_NVRAM     1           /* use NVRAM for environment vars */
-#define CFG_NVRAM_SIZE          0x800       /* NVRAM size (2kB) */
+#define CONFIG_SYS_NVRAM_SIZE          0x800       /* NVRAM size (2kB) */
 #define CONFIG_ENV_SIZE            0x400       /* Size of Environment vars (1kB) */
 #define CONFIG_ENV_ADDR            0x0
 #define CONFIG_ENV_MAP_ADRS        0xff000000
-#define CFG_NV_SROM_COPY_ADDR   (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
-#define CFG_NVRAM_ACCESS_ROUTINE            /* only byte accsess alowed */
-#define CFG_SROM_SIZE           0x100       /* shadow of revision info is in nvram */
+#define CONFIG_SYS_NV_SROM_COPY_ADDR   (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE            /* only byte accsess alowed */
+#define CONFIG_SYS_SROM_SIZE           0x100       /* shadow of revision info is in nvram */
 
 /*
  * Serial devices
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
-#define CFG_NS16550_CLK         24000000
-#define CFG_NS16550_COM1        (CFG_UART_BASE + 0)
-#define CFG_NS16550_COM2        (CFG_UART_BASE + 8)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK         24000000
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_UART_BASE + 0)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_UART_BASE + 8)
 
 /*
  * PCI stuff
@@ -263,74 +263,74 @@
  */
 #if 1
 
-#define CFG_IBAT0L 0
-#define CFG_IBAT0U 0
-#define CFG_DBAT0L CFG_IBAT1L
-#define CFG_DBAT0U CFG_IBAT1U
+#define CONFIG_SYS_IBAT0L 0
+#define CONFIG_SYS_IBAT0U 0
+#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
 
-#define CFG_IBAT1L 0
-#define CFG_IBAT1U 0
-#define CFG_DBAT1L CFG_IBAT1L
-#define CFG_DBAT1U CFG_IBAT1U
+#define CONFIG_SYS_IBAT1L 0
+#define CONFIG_SYS_IBAT1U 0
+#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
 
-#define CFG_IBAT2L 0
-#define CFG_IBAT2U 0
-#define CFG_DBAT2L CFG_IBAT2L
-#define CFG_DBAT2U CFG_IBAT2U
+#define CONFIG_SYS_IBAT2L 0
+#define CONFIG_SYS_IBAT2U 0
+#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
 
-#define CFG_IBAT3L 0
-#define CFG_IBAT3U 0
-#define CFG_DBAT3L CFG_IBAT3L
-#define CFG_DBAT3U CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L 0
+#define CONFIG_SYS_IBAT3U 0
+#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 
 #else
 
 /* SDRAM */
-#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW)
-#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L CFG_IBAT1L
-#define CFG_DBAT0U CFG_IBAT1U
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_RW)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
 
 /* address range for flashes */
-#define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L CFG_IBAT1L
-#define CFG_DBAT1U CFG_IBAT1U
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
 
 /* ISA IO space */
-#define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_DBAT2L CFG_IBAT2L
-#define CFG_DBAT2U CFG_IBAT2U
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
 
 /* ISA memory space */
-#define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_DBAT3L CFG_IBAT3L
-#define CFG_DBAT3U CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 
 #endif
 
 /*
  * Speed settings are board specific
  */
-#define CFG_BUS_HZ              100000000
-#define CFG_CPU_CLK             400000000
-#define CFG_BUS_CLK             CFG_BUS_HZ
+#define CONFIG_SYS_BUS_HZ              100000000
+#define CONFIG_SYS_CPU_CLK             400000000
+#define CONFIG_SYS_BUS_CLK             CONFIG_SYS_BUS_HZ
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ           (8 << 20)           /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ           (8 << 20)           /* Initial Memory map for Linux */
 
 /*
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE        32    /* For all MPC74xx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE        32    /* For all MPC74xx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT        5    /* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT        5    /* log base 2 of the above value */
 #endif
 
 /*
@@ -338,7 +338,7 @@
  * look in include/74xx_7xx.h for the defines used here
  */
 
-#define CFG_L2
+#define CONFIG_SYS_L2
 
 #if 1
 #define L2_INIT     0       /* cpu 750 CXe*/
@@ -358,7 +358,7 @@
 
 #define CONFIG_NET_MULTI        /* Multi ethernet cards support */
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
 #define CONFIG_EEPRO100_SROM_WRITE
 
 #endif    /* __CONFIG_H */
diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h
index c6a3b8b..ff58ea9 100644
--- a/include/configs/ELPT860.h
+++ b/include/configs/ELPT860.h
@@ -97,7 +97,7 @@
 #define CONFIG_RTC_DS164x	1	/* RTC is a Dallas DS1646	*/
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	  CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	  CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 
 /*
@@ -112,25 +112,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT     "LEOX_elpt860: " /* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT     "LEOX_elpt860: " /* Monitor Command Prompt	*/
 
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#  define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#  define CFG_CBSIZE	 256		/* Console I/O Buffer Size	*/
+#  define CONFIG_SYS_CBSIZE	 256		/* Console I/O Buffer Size	*/
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	  16		/* max number of command args	*/
-#define CFG_BARGSIZE	  CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	  16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	  CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x00100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 /*
  * Environment Variables and Storages
@@ -142,7 +142,7 @@
 #define CONFIG_ENV_IS_IN_FLASH	1      /* Environment is in FLASH	*/
 
 #define CONFIG_BAUDRATE		9600   /* console baudrate = 9600 bps	*/
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_ETHADDR		00:01:77:00:60:40
 #define CONFIG_IPADDR		192.168.0.30
@@ -160,58 +160,58 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFF000000
+#define CONFIG_SYS_IMMR		0xFF000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x02000000
-#define CFG_NVRAM_BASE		0x03000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x02000000
+#define CONFIG_SYS_NVRAM_BASE		0x03000000
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 #  if defined(DEBUG)
-#    define CFG_MONITOR_LEN	(320 << 10)  /* Reserve 320 kB for Monitor  */
+#    define CONFIG_SYS_MONITOR_LEN	(320 << 10)  /* Reserve 320 kB for Monitor  */
 #  else
-#    define CFG_MONITOR_LEN	(256 << 10)  /* Reserve 256 kB for Monitor  */
+#    define CONFIG_SYS_MONITOR_LEN	(256 << 10)  /* Reserve 256 kB for Monitor  */
 #  endif
 #else
 #  if defined(DEBUG)
-#    define CFG_MONITOR_LEN	(256 << 10)  /* Reserve 256 kB for Monitor  */
+#    define CONFIG_SYS_MONITOR_LEN	(256 << 10)  /* Reserve 256 kB for Monitor  */
 #  else
-#    define CFG_MONITOR_LEN	(192 << 10)  /* Reserve 192 kB for Monitor  */
+#    define CONFIG_SYS_MONITOR_LEN	(192 << 10)  /* Reserve 192 kB for Monitor  */
 #  endif
 #endif
 
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(128 << 10)  /* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)  /* Reserve 128 kB for malloc() */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)    /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)    /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	     */
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	     */
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)   */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)   */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)   */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)   */
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 #  define CONFIG_ENV_OFFSET	0x10000 /* Offset   of Environment Sector    */
@@ -221,22 +221,22 @@
 /*-----------------------------------------------------------------------
  * NVRAM organization
  */
-#define CFG_NVRAM_BASE_ADDR	CFG_NVRAM_BASE /* Base address of NVRAM area */
-#define CFG_NVRAM_SIZE		((128*1024)-8) /* clock regs resident in the */
+#define CONFIG_SYS_NVRAM_BASE_ADDR	CONFIG_SYS_NVRAM_BASE /* Base address of NVRAM area */
+#define CONFIG_SYS_NVRAM_SIZE		((128*1024)-8) /* clock regs resident in the */
 					       /*   8 top NVRAM locations    */
 
 #if defined(CONFIG_ENV_IS_IN_NVRAM)
-#  define CONFIG_ENV_ADDR		CFG_NVRAM_BASE /* Base address of NVRAM area */
+#  define CONFIG_ENV_ADDR		CONFIG_SYS_NVRAM_BASE /* Base address of NVRAM area */
 #  define CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector  */
 #endif
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs		     */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs		     */
 
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	 4	/* log base 2 of the above value     */
+#  define CONFIG_SYS_CACHELINE_SHIFT	 4	/* log base 2 of the above value     */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -246,10 +246,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT	 | SYPCR_BME | SYPCR_SWF | \
+#  define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT	 | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI | SYPCR_SWP)
 #else
-#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT	 | SYPCR_BME | SYPCR_SWF | \
+#  define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT	 | SYPCR_BME | SYPCR_SWF | \
 						   SYPCR_SWP)
 #endif
 
@@ -258,14 +258,14 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC11)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
@@ -273,14 +273,14 @@
  * Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC
  *  enabled
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -288,7 +288,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit - leave PLL multiplication factor unchanged !
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -297,7 +297,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	 SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS     | \
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -308,9 +308,9 @@
  *
  */
 #ifdef DEBUG
-#  define CFG_DER		0xFFE7400F	/* Debug Enable Register */
+#  define CONFIG_SYS_DER		0xFFE7400F	/* Debug Enable Register */
 #else
-#  define CFG_DER		0
+#  define CONFIG_SYS_DER		0
 #endif
 
 /*
@@ -320,68 +320,68 @@
  * BR0 and OR0 (FLASH)
  */
 
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	  */
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	  */
 
 /* used to re-map FLASH both when starting from SRAM or FLASH:
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_PRELIM_OR_AM	0xFF000000	/* 16 MB between each CSx */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFF000000	/* 16 MB between each CSx */
 
 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0	  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK)
 
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 
 /*
  * BR1 and OR1 (SDRAM)
  *
  */
-#define SDRAM_BASE1_PRELIM	CFG_SDRAM_BASE	/* SDRAM bank #0	*/
+#define SDRAM_BASE1_PRELIM	CONFIG_SYS_SDRAM_BASE	/* SDRAM bank #0	*/
 #define SDRAM_MAX_SIZE		0x02000000	/* 32 MB MAX for CS1	*/
 
 /* SDRAM timing:							*/
-#define CFG_OR_TIMING_SDRAM	0x00000000
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000000
 
-#define CFG_OR1_PRELIM	((2 * CFG_PRELIM_OR_AM) | CFG_OR_TIMING_SDRAM )
-#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR1_PRELIM	((2 * CONFIG_SYS_PRELIM_OR_AM) | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /*
  * BR2 and OR2 (NVRAM)
  *
  */
-#define NVRAM_BASE1_PRELIM	CFG_NVRAM_BASE	/* NVRAM bank #0	*/
+#define NVRAM_BASE1_PRELIM	CONFIG_SYS_NVRAM_BASE	/* NVRAM bank #0	*/
 #define NVRAM_MAX_SIZE		0x00020000	/* 128 KB MAX for CS2	*/
 
-#define CFG_OR2_PRELIM		0xFFF80160
-#define CFG_BR2_PRELIM	((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR2_PRELIM		0xFFF80160
+#define CONFIG_SYS_BR2_PRELIM	((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 
 /*
  * Memory Periodic Timer Prescaler
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA		97     /* start with divider for 100 MHz */
+#define CONFIG_SYS_MAMR_PTA		97     /* start with divider for 100 MHz */
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16	  /* setting for 2 banks */
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32	  /* setting for 1 bank	 */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16	  /* setting for 2 banks */
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32	  /* setting for 1 bank	 */
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit	 */
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8	  /* setting for 2 banks */
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16	  /* setting for 1 bank	 */
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8	  /* setting for 2 banks */
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16	  /* setting for 1 bank	 */
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    | \
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    | \
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    | \
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    | \
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h
index 90e3637..a0904d4 100644
--- a/include/configs/EP1C20.h
+++ b/include/configs/EP1C20.h
@@ -30,29 +30,29 @@
 #define CONFIG_EP1C20		1		/* EP1C20 board		*/
 #define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
 
-#define CFG_RESET_ADDR		0x00000000	/* Hard-reset address	*/
-#define CFG_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
-#define CFG_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
+#define CONFIG_SYS_RESET_ADDR		0x00000000	/* Hard-reset address	*/
+#define CONFIG_SYS_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
+#define CONFIG_SYS_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
 
 /*------------------------------------------------------------------------
  * CACHE -- the following will support II/s and II/f. The II/s does not
  * have dcache, so the cache instructions will behave as NOPs.
  *----------------------------------------------------------------------*/
-#define CFG_ICACHE_SIZE		4096		/* 4 KByte total	*/
-#define CFG_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
-#define CFG_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
-#define CFG_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
+#define CONFIG_SYS_ICACHE_SIZE		4096		/* 4 KByte total	*/
+#define CONFIG_SYS_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
+#define CONFIG_SYS_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
+#define CONFIG_SYS_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
 
 /*------------------------------------------------------------------------
  * MEMORY BASE ADDRESSES
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE		0x00000000	/* FLASH base addr	*/
-#define CFG_FLASH_SIZE		0x00800000	/* 8 MByte		*/
-#define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
-#define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
-#define CFG_SRAM_BASE		0x02000000	/* SRAM base addr	*/
-#define CFG_SRAM_SIZE		0x00100000	/* 1 MB (only 1M mapped)*/
+#define CONFIG_SYS_FLASH_BASE		0x00000000	/* FLASH base addr	*/
+#define CONFIG_SYS_FLASH_SIZE		0x00800000	/* 8 MByte		*/
+#define CONFIG_SYS_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
+#define CONFIG_SYS_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
+#define CONFIG_SYS_SRAM_BASE		0x02000000	/* SRAM base addr	*/
+#define CONFIG_SYS_SRAM_SIZE		0x00100000	/* 1 MB (only 1M mapped)*/
 
 /*------------------------------------------------------------------------
  * MEMORY ORGANIZATION
@@ -61,27 +61,27 @@
  *	-Global data is placed below the heap.
  *	-The stack is placed below global data (&grows down).
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 128k		*/
-#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 128k		*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
 
 /*------------------------------------------------------------------------
  * FLASH (AM29LV065D)
  *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
-#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
-#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
-#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
-#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
 
 /*------------------------------------------------------------------------
- * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
- * CFG_RESET_ADDR, since we assume the monitor is stored at the
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
  * reset address, no? This will keep the environment in user region
  * of flash. NOTE: the monitor length must be multiple of sector size
  * (which is common practice).
@@ -89,30 +89,30 @@
 #define CONFIG_ENV_IS_IN_FLASH	1		/* Environment in flash */
 #define CONFIG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
 #define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
-#define CONFIG_ENV_ADDR	(CFG_RESET_ADDR + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)
 
 /*------------------------------------------------------------------------
  * CONSOLE
  *----------------------------------------------------------------------*/
 #if defined(CONFIG_CONSOLE_JTAG)
-#define CFG_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
+#define CONFIG_SYS_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
 #else
-#define CFG_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
+#define CONFIG_SYS_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
 #endif
 
-#define CFG_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
+#define CONFIG_SYS_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
 #define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
-#define CFG_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
 
 /*------------------------------------------------------------------------
- * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for
+ * EPCS Device -- wne CONFIG_SYS_NIOS_EPCSBASE is defined code/commands for
  * epcs device access is enabled. The base address is the epcs
  * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
  * The register base is currently at offset 0x600 from the memory base.
  *----------------------------------------------------------------------*/
-#define CFG_NIOS_EPCSBASE	0x02100200	/* EPCS register base	*/
+#define CONFIG_SYS_NIOS_EPCSBASE	0x02100200	/* EPCS register base	*/
 
 /*------------------------------------------------------------------------
  * DEBUG
@@ -126,23 +126,23 @@
  * registers, we can slow it down to 10 msec using TMRCNT. If the default
  * period is acceptable, TMRCNT can be left undefined.
  *----------------------------------------------------------------------*/
-#define CFG_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
-#define CFG_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
-#define CFG_NIOS_TMRMS		10		/* 10 msec per tick	*/
-#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define CFG_HZ		(CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
+#define CONFIG_SYS_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
+#define CONFIG_SYS_NIOS_TMRMS		10		/* 10 msec per tick	*/
+#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
+#define CONFIG_SYS_HZ		(CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
 
 /*------------------------------------------------------------------------
  * STATUS LED -- Provides a simple blinking led. For Nios2 each board
  * must implement its own led routines -- leds are, after all,
  * board-specific, no?
  *----------------------------------------------------------------------*/
-#define CFG_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
+#define CONFIG_SYS_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
 #define CONFIG_STATUS_LED			/* Enable status driver */
 
 #define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
 #define STATUS_LED_STATE	1		/* Blinking		*/
-#define STATUS_LED_PERIOD	(500/CFG_NIOS_TMRMS) /* Every 500 msec	*/
+#define STATUS_LED_PERIOD	(500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec	*/
 
 /*------------------------------------------------------------------------
  * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
@@ -194,17 +194,17 @@
 /*------------------------------------------------------------------------
  * MISC
  *----------------------------------------------------------------------*/
-#define CFG_LONGHELP				/* Provide extended help*/
-#define CFG_PROMPT		"==> "		/* Command prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O buf size */
-#define CFG_MAXARGS		16		/* Max command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot arg buf size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
-#define CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* Default load address */
-#define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* Start addr for test	*/
-#define CFG_MEMTEST_END		CFG_INIT_SP - 0x00020000
-
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP				/* Provide extended help*/
+#define CONFIG_SYS_PROMPT		"==> "		/* Command prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16		/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot arg buf size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE	/* Default load address */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE	/* Start addr for test	*/
+#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_INIT_SP - 0x00020000
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h
index ae9409f..53bd0d8 100644
--- a/include/configs/EP1S10.h
+++ b/include/configs/EP1S10.h
@@ -30,28 +30,28 @@
 #define CONFIG_EP1S10		1		/* EP1S10 board		*/
 #define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
 
-#define CFG_RESET_ADDR		0x00000000	/* Hard-reset address	*/
-#define CFG_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
-#define CFG_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
+#define CONFIG_SYS_RESET_ADDR		0x00000000	/* Hard-reset address	*/
+#define CONFIG_SYS_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
+#define CONFIG_SYS_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
 
 /*------------------------------------------------------------------------
  * CACHE -- the following will support II/s and II/f. The II/s does not
  * have dcache, so the cache instructions will behave as NOPs.
  *----------------------------------------------------------------------*/
-#define CFG_ICACHE_SIZE		4096		/* 4 KByte total	*/
-#define CFG_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
-#define CFG_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
-#define CFG_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
+#define CONFIG_SYS_ICACHE_SIZE		4096		/* 4 KByte total	*/
+#define CONFIG_SYS_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
+#define CONFIG_SYS_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
+#define CONFIG_SYS_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
 
 /*------------------------------------------------------------------------
  * MEMORY BASE ADDRESSES
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE		0x00000000	/* FLASH base addr	*/
-#define CFG_FLASH_SIZE		0x00800000	/* 8 MByte		*/
-#define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
-#define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
-#define CFG_SRAM_BASE		0x02000000	/* SRAM base addr	*/
-#define CFG_SRAM_SIZE		0x00100000	/* 1 MB			*/
+#define CONFIG_SYS_FLASH_BASE		0x00000000	/* FLASH base addr	*/
+#define CONFIG_SYS_FLASH_SIZE		0x00800000	/* 8 MByte		*/
+#define CONFIG_SYS_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
+#define CONFIG_SYS_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
+#define CONFIG_SYS_SRAM_BASE		0x02000000	/* SRAM base addr	*/
+#define CONFIG_SYS_SRAM_SIZE		0x00100000	/* 1 MB			*/
 
 /*------------------------------------------------------------------------
  * MEMORY ORGANIZATION
@@ -60,26 +60,26 @@
  *	-Global data is placed below the heap.
  *	-The stack is placed below global data (&grows down).
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
-#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 256*1024) /* 256k heap */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 256*1024) /* 256k heap */
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
 
 /*------------------------------------------------------------------------
  * FLASH (AM29LV065D)
  *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
-#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
-#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
-#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
 
 /*------------------------------------------------------------------------
- * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
- * CFG_FLASH_BASE, since we assume that u-boot is stored at the bottom
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_FLASH_BASE, since we assume that u-boot is stored at the bottom
  * of flash memory. This will keep the environment in user region
  * of flash. NOTE: the monitor length must be multiple of sector size
  * (which is common practice).
@@ -87,27 +87,27 @@
 #define CONFIG_ENV_IS_IN_FLASH	1		/* Environment in flash */
 #define CONFIG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
 #define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
-#define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 
 /*------------------------------------------------------------------------
  * CONSOLE
  *----------------------------------------------------------------------*/
 #if defined(CONFIG_CONSOLE_JTAG)
-#define CFG_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
+#define CONFIG_SYS_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
 #else
-#define CFG_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
+#define CONFIG_SYS_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
 #endif
 
-#define CFG_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
+#define CONFIG_SYS_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
 #define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
-#define CFG_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
 
 /*------------------------------------------------------------------------
  * EPCS Device -- None for stratix.
  *----------------------------------------------------------------------*/
-#undef CFG_NIOS_EPCSBASE
+#undef CONFIG_SYS_NIOS_EPCSBASE
 
 /*------------------------------------------------------------------------
  * DEBUG
@@ -121,22 +121,22 @@
  * registers, we can slow it down to 10 msec using TMRCNT. If the default
  * period is acceptable, TMRCNT can be left undefined.
  *----------------------------------------------------------------------*/
-#define CFG_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
-#define CFG_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
-#define CFG_NIOS_TMRMS		10		/* 10 msec per tick	*/
-#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define CFG_HZ		(CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
+#define CONFIG_SYS_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
+#define CONFIG_SYS_NIOS_TMRMS		10		/* 10 msec per tick	*/
+#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
+#define CONFIG_SYS_HZ		(CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
 
 /*------------------------------------------------------------------------
  * STATUS LED -- Provides a simple blinking led. For Nios2 each board
  * must implement its own led routines -- since leds are board-specific.
  *----------------------------------------------------------------------*/
-#define CFG_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
+#define CONFIG_SYS_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
 #define CONFIG_STATUS_LED			/* Enable status driver */
 
 #define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
 #define STATUS_LED_STATE	1		/* Blinking		*/
-#define STATUS_LED_PERIOD	(500/CFG_NIOS_TMRMS) /* Every 500 msec	*/
+#define STATUS_LED_PERIOD	(500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec	*/
 
 /*------------------------------------------------------------------------
  * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
@@ -170,7 +170,7 @@
 #define CONFIG_CMD_BDI
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ECHO
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_IMI
 #define CONFIG_CMD_IRQ
@@ -187,17 +187,17 @@
 /*------------------------------------------------------------------------
  * MISC
  *----------------------------------------------------------------------*/
-#define CFG_LONGHELP				/* Provide extended help*/
-#define CFG_PROMPT		"==> "		/* Command prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O buf size */
-#define CFG_MAXARGS		16		/* Max command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot arg buf size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
-#define CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* Default load address */
-#define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* Start addr for test	*/
-#define CFG_MEMTEST_END		CFG_INIT_SP - 0x00020000
-
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP				/* Provide extended help*/
+#define CONFIG_SYS_PROMPT		"==> "		/* Command prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16		/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot arg buf size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE	/* Default load address */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE	/* Start addr for test	*/
+#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_INIT_SP - 0x00020000
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h
index 95ae147..9e9a8a4 100644
--- a/include/configs/EP1S40.h
+++ b/include/configs/EP1S40.h
@@ -30,28 +30,28 @@
 #define CONFIG_EP1S40		1		/* EP1S40 board		*/
 #define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
 
-#define CFG_RESET_ADDR		0x00000000	/* Hard-reset address	*/
-#define CFG_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
-#define CFG_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
+#define CONFIG_SYS_RESET_ADDR		0x00000000	/* Hard-reset address	*/
+#define CONFIG_SYS_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
+#define CONFIG_SYS_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
 
 /*------------------------------------------------------------------------
  * CACHE -- the following will support II/s and II/f. The II/s does not
  * have dcache, so the cache instructions will behave as NOPs.
  *----------------------------------------------------------------------*/
-#define CFG_ICACHE_SIZE		4096		/* 4 KByte total	*/
-#define CFG_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
-#define CFG_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
-#define CFG_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
+#define CONFIG_SYS_ICACHE_SIZE		4096		/* 4 KByte total	*/
+#define CONFIG_SYS_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
+#define CONFIG_SYS_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
+#define CONFIG_SYS_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
 
 /*------------------------------------------------------------------------
  * MEMORY BASE ADDRESSES
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE		0x00000000	/* FLASH base addr	*/
-#define CFG_FLASH_SIZE		0x00800000	/* 8 MByte		*/
-#define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
-#define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
-#define CFG_SRAM_BASE		0x02000000	/* SRAM base addr	*/
-#define CFG_SRAM_SIZE		0x00100000	/* 1 MB			*/
+#define CONFIG_SYS_FLASH_BASE		0x00000000	/* FLASH base addr	*/
+#define CONFIG_SYS_FLASH_SIZE		0x00800000	/* 8 MByte		*/
+#define CONFIG_SYS_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
+#define CONFIG_SYS_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
+#define CONFIG_SYS_SRAM_BASE		0x02000000	/* SRAM base addr	*/
+#define CONFIG_SYS_SRAM_SIZE		0x00100000	/* 1 MB			*/
 
 /*------------------------------------------------------------------------
  * MEMORY ORGANIZATION
@@ -60,26 +60,26 @@
  *	-Global data is placed below the heap.
  *	-The stack is placed below global data (&grows down).
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
-#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 256*1024) /* 256k heap */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 256*1024) /* 256k heap */
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
 
 /*------------------------------------------------------------------------
  * FLASH (AM29LV065D)
  *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
-#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
-#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
-#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
 
 /*------------------------------------------------------------------------
- * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
- * CFG_FLASH_BASE, since we assume that u-boot is stored at the bottom
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_FLASH_BASE, since we assume that u-boot is stored at the bottom
  * of flash memory. This will keep the environment in user region
  * of flash. NOTE: the monitor length must be multiple of sector size
  * (which is common practice).
@@ -87,27 +87,27 @@
 #define CONFIG_ENV_IS_IN_FLASH	1		/* Environment in flash */
 #define CONFIG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
 #define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
-#define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 
 /*------------------------------------------------------------------------
  * CONSOLE
  *----------------------------------------------------------------------*/
 #if defined(CONFIG_CONSOLE_JTAG)
-#define CFG_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
+#define CONFIG_SYS_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
 #else
-#define CFG_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
+#define CONFIG_SYS_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
 #endif
 
-#define CFG_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
+#define CONFIG_SYS_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
 #define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
-#define CFG_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
 
 /*------------------------------------------------------------------------
  * EPCS Device -- None for stratix.
  *----------------------------------------------------------------------*/
-#undef CFG_NIOS_EPCSBASE
+#undef CONFIG_SYS_NIOS_EPCSBASE
 
 /*------------------------------------------------------------------------
  * DEBUG
@@ -121,22 +121,22 @@
  * registers, we can slow it down to 10 msec using TMRCNT. If the default
  * period is acceptable, TMRCNT can be left undefined.
  *----------------------------------------------------------------------*/
-#define CFG_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
-#define CFG_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
-#define CFG_NIOS_TMRMS		10		/* 10 msec per tick	*/
-#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define CFG_HZ		(CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
+#define CONFIG_SYS_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
+#define CONFIG_SYS_NIOS_TMRMS		10		/* 10 msec per tick	*/
+#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
+#define CONFIG_SYS_HZ		(CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
 
 /*------------------------------------------------------------------------
  * STATUS LED -- Provides a simple blinking led. For Nios2 each board
  * must implement its own led routines -- since leds are board-specific.
  *----------------------------------------------------------------------*/
-#define CFG_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
+#define CONFIG_SYS_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
 #define CONFIG_STATUS_LED			/* Enable status driver */
 
 #define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
 #define STATUS_LED_STATE	1		/* Blinking		*/
-#define STATUS_LED_PERIOD	(500/CFG_NIOS_TMRMS) /* Every 500 msec	*/
+#define STATUS_LED_PERIOD	(500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec	*/
 
 /*------------------------------------------------------------------------
  * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
@@ -170,7 +170,7 @@
 #define CONFIG_CMD_BDI
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ECHO
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_IMI
 #define CONFIG_CMD_IRQ
@@ -187,17 +187,17 @@
 /*------------------------------------------------------------------------
  * MISC
  *----------------------------------------------------------------------*/
-#define CFG_LONGHELP				/* Provide extended help*/
-#define CFG_PROMPT		"==> "		/* Command prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O buf size */
-#define CFG_MAXARGS		16		/* Max command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot arg buf size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
-#define CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* Default load address */
-#define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* Start addr for test	*/
-#define CFG_MEMTEST_END		CFG_INIT_SP - 0x00020000
-
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP				/* Provide extended help*/
+#define CONFIG_SYS_PROMPT		"==> "		/* Command prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16		/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot arg buf size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE	/* Default load address */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE	/* Start addr for test	*/
+#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_INIT_SP - 0x00020000
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h
index 106cc6f..e1c6096 100644
--- a/include/configs/EP88x.h
+++ b/include/configs/EP88x.h
@@ -41,15 +41,15 @@
 #define	CONFIG_ETHER_ON_FEC1			/* Enable Ethernet on FEC1	*/
 #define	CONFIG_ETHER_ON_FEC2			/* Enable Ethernet on FEC2	*/
 #if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
-#define CFG_DISCOVER_PHY
+#define CONFIG_SYS_DISCOVER_PHY
 #define CONFIG_MII_INIT		1
 #define FEC_ENET
 #endif /* CONFIG_FEC_ENET */
 
 #define CONFIG_8xx_OSCLK		10000000 /* 10 MHz oscillator on EXTCLK */
 #define CONFIG_8xx_CPUCLK_DEFAULT	100000000
-#define CFG_8xx_CPUCLK_MIN		40000000
-#define CFG_8xx_CPUCLK_MAX		133000000
+#define CONFIG_SYS_8xx_CPUCLK_MIN		40000000
+#define CONFIG_SYS_8xx_CPUCLK_MAX		133000000
 
 /*
  * BOOTP options
@@ -81,28 +81,28 @@
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  */
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#define CFG_LONGHELP				/* #undef to save memory	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)  /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* Max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP				/* #undef to save memory	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)  /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* Max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_LOAD_ADDR		0x400000	/* Default load address		*/
+#define CONFIG_SYS_LOAD_ADDR		0x400000	/* Default load address		*/
 
-#define CFG_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
+#define CONFIG_SYS_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
- * RAM configuration (note that CFG_SDRAM_BASE must be zero)
+ * RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero)
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_MAX_SIZE	0x08000000	/* Up to 128 Mbyte		*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_MAX_SIZE	0x08000000	/* Up to 128 Mbyte		*/
 
-#define CFG_MAMR		0x00805000
+#define CONFIG_SYS_MAMR		0x00805000
 
 /*
  * 4096	Up to 4096 SDRAM rows
@@ -111,99 +111,99 @@
  * 4	Number of refresh cycles per period
  * 64	Refresh cycle in ms per number of rows
  */
-#define CFG_PTA_PER_CLK		((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_PTA_PER_CLK		((4096 * 32 * 1000) / (4 * 64))
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x00500000	/* 1 ... 5 MB in SDRAM		*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x00500000	/* 1 ... 5 MB in SDRAM		*/
 
-#define CFG_RESET_ADDRESS	0x09900000
+#define CONFIG_SYS_RESET_ADDRESS	0x09900000
 
 /*-----------------------------------------------------------------------
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for Monitor   */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for Monitor   */
 #ifdef CONFIG_BZIP2
-#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve ~4 MB for malloc()   */
+#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve ~4 MB for malloc()   */
 #else
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()  */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()  */
 #endif /* CONFIG_BZIP2 */
 
 /*-----------------------------------------------------------------------
  * Flash organisation
  */
-#define CFG_FLASH_BASE		0xFC000000
-#define CFG_FLASH_CFI				/* The flash is CFI compatible  */
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible  */
 #define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
-#define CFG_MAX_FLASH_BANKS	1		/* Max number of flash banks	*/
-#define CFG_MAX_FLASH_SECT	512		/* Max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max number of flash banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512		/* Max num of sects on one chip */
 
 /* Environment is in flash */
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000		/* We use one complete sector	*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 
-#define CFG_OR0_PRELIM		0xFC000160
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_PS_32 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM		0xFC000160
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BR_PS_32 | BR_MS_GPCM | BR_V)
 
-#define	CFG_DIRECT_FLASH_TFTP
+#define	CONFIG_SYS_DIRECT_FLASH_TFTP
 
 /*-----------------------------------------------------------------------
  * BCSR
  */
-#define CFG_OR3_PRELIM		0xFF0005B0
-#define CFG_BR3_PRELIM		(0xFA000000 |BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR3_PRELIM		0xFF0005B0
+#define CONFIG_SYS_BR3_PRELIM		(0xFA000000 |BR_PS_16 | BR_MS_GPCM | BR_V)
 
-#define CFG_BCSR		0xFA400000
+#define CONFIG_SYS_BCSR		0xFA400000
 
 /*-----------------------------------------------------------------------
  * Internal Memory Map Register
  */
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR		0xF0000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00		/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128  /* Size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00		/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* Size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Configuration registers
  */
 #ifdef CONFIG_WATCHDOG
-#define CFG_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
+#define CONFIG_SYS_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
 				 SYPCR_SWF  | SYPCR_SWE | SYPCR_SWRI | \
 				 SYPCR_SWP)
 #else
-#define CFG_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
+#define CONFIG_SYS_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
 				 SYPCR_SWF  | SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
-#define CFG_SIUMCR		(SIUMCR_MLRC01 | SIUMCR_DBGC11)
+#define CONFIG_SYS_SIUMCR		(SIUMCR_MLRC01 | SIUMCR_DBGC11)
 
 /* TBSCR - Time Base Status and Control Register */
-#define CFG_TBSCR		(TBSCR_TBF | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR		(TBSCR_TBF | TBSCR_TBE)
 
 /* PISCR - Periodic Interrupt Status and Control */
-#define CFG_PISCR		PISCR_PS
+#define CONFIG_SYS_PISCR		PISCR_PS
 
 /* SCCR - System Clock and reset Control Register */
 #define SCCR_MASK		SCCR_EBDF11
-#define CFG_SCCR		SCCR_RTSEL
+#define CONFIG_SYS_SCCR		SCCR_RTSEL
 
-#define CFG_DER			0
+#define CONFIG_SYS_DER			0
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx chips			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx chips			*/
 
 /*-----------------------------------------------------------------------
  * Internal Definitions
diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h
index c3c7aa4..201e62a 100644
--- a/include/configs/ERIC.h
+++ b/include/configs/ERIC.h
@@ -54,13 +54,13 @@
 #endif					/* total size of a X1240 is 2048 bytes */
 
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x57	/* X1240 has two I2C slave addresses, one for EEPROM */
-#define CFG_I2C_EEPROM_ADDR_LEN	2	/* address length for the eeprom */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57	/* X1240 has two I2C slave addresses, one for EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* address length for the eeprom */
 #define CONFIG_I2C_RTC		1	/* we have a Xicor X1240 RTC */
-#define CFG_I2C_RTC_ADDR	0x6F	/*                                and one for RTC */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x6F	/*                                and one for RTC */
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #undef CONFIG_ENV_IS_IN_NVRAM
@@ -91,8 +91,9 @@
 				"ip=192.168.1.22:192.168.1.2"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		1	/* PHY address			*/
 
@@ -113,7 +114,7 @@
 
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 
 
@@ -122,31 +123,31 @@
 /*
  * Miscellaneous configurable options
  */
-#undef	CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#undef	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	 CFG_EXT_SERIAL_CLOCK	 14318180
+#define	 CONFIG_SYS_EXT_SERIAL_CLOCK	 14318180
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -161,14 +162,14 @@
 #undef  CONFIG_PCI_PNP			/* no pci plug-and-play         */
 					/* resource configuration       */
 
-#define CFG_PCI_SUBSYS_VENDORID 0x1743	/* PCI Vendor ID: Peppercon AG	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: 405GP		*/
-#define CFG_PCI_PTM1LA	0xFFFC0000	/* point to flash		*/
-#define CFG_PCI_PTM1MS	0xFFFFF001	/* 4kB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1743	/* PCI Vendor ID: Peppercon AG	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: 405GP		*/
+#define CONFIG_SYS_PCI_PTM1LA	0xFFFC0000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xFFFFF001	/* 4kB, enable hard-wired to 1	*/
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * External peripheral base address
@@ -224,21 +225,21 @@
 #define CS7_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
 #define CS7_CR	0xF0618000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
 
-#define CFG_NVRAM_REG_BASE_ADDR	 0xF0000000
-#define CFG_RTC_REG_BASE_ADDR	 (0xF0000000 + 0x7F8)
-#define CFG_ADC_REG_BASE_ADDR	 0xF0100000
-#define CFG_PHYRES_REG_BASE_ADDR 0xF0200000
-#define CFG_PRSNT1_REG_BASE_ADDR 0xF0300000
-#define CFG_PRSNT2_REG_BASE_ADDR 0xF0400000
-#define CFG_LED0_REG_BASE_ADDR	 0xF0500000
-#define CFG_LED1_REG_BASE_ADDR	 0xF0600000
+#define CONFIG_SYS_NVRAM_REG_BASE_ADDR	 0xF0000000
+#define CONFIG_SYS_RTC_REG_BASE_ADDR	 (0xF0000000 + 0x7F8)
+#define CONFIG_SYS_ADC_REG_BASE_ADDR	 0xF0100000
+#define CONFIG_SYS_PHYRES_REG_BASE_ADDR 0xF0200000
+#define CONFIG_SYS_PRSNT1_REG_BASE_ADDR 0xF0300000
+#define CONFIG_SYS_PRSNT2_REG_BASE_ADDR 0xF0400000
+#define CONFIG_SYS_LED0_REG_BASE_ADDR	 0xF0500000
+#define CONFIG_SYS_LED1_REG_BASE_ADDR	 0xF0600000
 
 
 /*  SDRAM CONFIG */
-#define CFG_SDRAM_MANUALLY    1
-#define CFG_SDRAM_SINGLE_BANK 1
+#define CONFIG_SYS_SDRAM_MANUALLY    1
+#define CONFIG_SYS_SDRAM_SINGLE_BANK 1
 
-#ifdef CFG_SDRAM_MANUALLY
+#ifdef CONFIG_SYS_SDRAM_MANUALLY
 /*-----------------------------------------------------------------------
  * Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2)
  *----------------------------------------------------------------------*/
@@ -246,7 +247,7 @@
 /*-----------------------------------------------------------------------
  * Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2)
  *----------------------------------------------------------------------*/
-#ifdef CFG_SDRAM_SINGLE_BANK
+#ifdef CONFIG_SYS_SDRAM_SINGLE_BANK
 #define MB1CF	0x0 /*  0MB @ 32MB */
 #else
 #define MB1CF	0x02062001 /*  32MB @ 32MB */
@@ -265,37 +266,37 @@
 #define SDTR_66     0x00854006	/* orig U-Boot-wallnut says 0x00854006 */
 #define RTR_66      0x03f8
 
-#endif   /* CFG_SDRAM_MANUALLY */
+#endif   /* CONFIG_SYS_SDRAM_MANUALLY */
 
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_SIZE		32
-#define CFG_FLASH_BASE		0xFF800000      /* 8 MByte Flash */
-#define CFG_MONITOR_BASE	0xFFFE0000      /* last 128kByte within Flash */
-/*#define CFG_MONITOR_LEN		(192 * 1024)*/	/* Reserve 196 kB for Monitor	*/
-#define CFG_MONITOR_LEN		(128 * 1024)	/* Reserve 128 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		32
+#define CONFIG_SYS_FLASH_BASE		0xFF800000      /* 8 MByte Flash */
+#define CONFIG_SYS_MONITOR_BASE	0xFFFE0000      /* last 128kByte within Flash */
+/*#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)*/	/* Reserve 196 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)	/* Reserve 128 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-#define CFG_FLASH_16BIT		1	/* Rom 16 bit data bus			*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_16BIT		1	/* Rom 16 bit data bus			*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 /* BEG ENVIRONNEMENT FLASH */
 #ifdef CONFIG_ENV_IS_IN_FLASH
@@ -305,9 +306,9 @@
 #define CONFIG_ENV_ADDR            0xfffa0000
 #else  /* force ENV to be embedded */
 #define	CONFIG_ENV_SIZE		(2 * 1024) /* Total Size of Environment Sector 2k */
-#define CONFIG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN - CONFIG_ENV_SIZE - 0x10) /* let space for reset vector */
-/* #define CONFIG_ENV_ADDR            (CFG_MONITOR_BASE)*/
-#define CONFIG_ENV_OFFSET          (CONFIG_ENV_ADDR - CFG_FLASH_BASE)
+#define CONFIG_ENV_ADDR            (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SIZE - 0x10) /* let space for reset vector */
+/* #define CONFIG_ENV_ADDR            (CONFIG_SYS_MONITOR_BASE)*/
+#define CONFIG_ENV_OFFSET          (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
 #endif
 
 #endif
@@ -315,13 +316,13 @@
 /*-----------------------------------------------------------------------
  * NVRAM organization
  */
-#define CFG_NVRAM_BASE_ADDR	CFG_NVRAM_REG_BASE_ADDR	/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		0x7F8		/* NVRAM size 2kByte - 8 Byte for RTC */
+#define CONFIG_SYS_NVRAM_BASE_ADDR	CONFIG_SYS_NVRAM_REG_BASE_ADDR	/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		0x7F8		/* NVRAM size 2kByte - 8 Byte for RTC */
 
 #ifdef CONFIG_ENV_IS_IN_NVRAM
 #define CONFIG_ENV_SIZE		0x7F8		/* Size of Environment vars	*/
 #define CONFIG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
 #endif
 
 /*
@@ -340,11 +341,11 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x00df0000  /* inside of SDRAM		       */
-#define CFG_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x00df0000  /* inside of SDRAM		       */
+#define CONFIG_SYS_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for Serial Presence Detect EEPROM address
diff --git a/include/configs/ESTEEM192E.h b/include/configs/ESTEEM192E.h
index 02539e2..11a862e 100644
--- a/include/configs/ESTEEM192E.h
+++ b/include/configs/ESTEEM192E.h
@@ -44,7 +44,7 @@
 
 #define MPC8XX_FACT	10		/* Multiply by 10		*/
 #define MPC8XX_XIN	4915200	/* 4.915200 MHz in	- ??? - XXX	*/
-#define CFG_PLPRCR_MF	((MPC8XX_FACT-1) << 20)
+#define CONFIG_SYS_PLPRCR_MF	((MPC8XX_FACT-1) << 20)
 #define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz	*/
 
 #define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ	/* Force it - dont measure it */
@@ -66,7 +66,7 @@
  */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -86,22 +86,22 @@
 #include <config_cmd_default.h>
 
 
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"BOOT: "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE	256			/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	8			/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"BOOT: "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE	256			/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	8			/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ			1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks	*/
 
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 
 /*
@@ -112,47 +112,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFF000000
+#define CONFIG_SYS_IMMR		0xFF000000
 
   /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
 #ifdef	DEBUG
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
@@ -160,7 +160,7 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control				11-9
@@ -168,21 +168,21 @@
  *-----------------------------------------------------------------------
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 
 /*-----------------------------------------------------------------------
  * SUMCR - SIU Module Configuration				11-6
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /* DBGC00 */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /* DBGC00 */
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
 
 /* (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) */
 
@@ -192,7 +192,7 @@
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -200,7 +200,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit - leave PLL multiplication factor unchanged !
  */
-#define CFG_PLPRCR	(CFG_PLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(CONFIG_SYS_PLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -209,7 +209,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS     | \
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -219,25 +219,25 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
-#define CFG_PCMCIA_INTERRUPT	SIU_LEVEL6
+#define CONFIG_SYS_PCMCIA_INTERRUPT	SIU_LEVEL6
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
-/*#define CFG_DER	0x02002000 */
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
+/*#define CONFIG_SYS_DER	0x02002000 */
 
 
 /*
@@ -253,21 +253,21 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	0x00000160
+#define CONFIG_SYS_OR_TIMING_FLASH	0x00000160
 				/*(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
 				 OR_SCY_5_CLK | OR_EHTR) */
 
-#define CFG_OR0_REMAP	0x80000160     /*(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)*/
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	( FLASH_BASE0_PRELIM | 0x00000801 )
+#define CONFIG_SYS_OR0_REMAP	0x80000160     /*(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)*/
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	( FLASH_BASE0_PRELIM | 0x00000801 )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	( FLASH_BASE1_PRELIM | 0x00000801 )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	( FLASH_BASE1_PRELIM | 0x00000801 )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -278,13 +278,13 @@
 #define	SDRAM_MAX_SIZE		0x02000000	/* max 32 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	0xFC000E00
-#define CFG_BR2_PRELIM	(SDRAM_BASE2_PRELIM | 0x00000081)
+#define CONFIG_SYS_OR2_PRELIM	0xFC000E00
+#define CONFIG_SYS_BR2_PRELIM	(SDRAM_BASE2_PRELIM | 0x00000081)
 
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	(SDRAM_BASE3_PRELIM | 0x00000081)
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	(SDRAM_BASE3_PRELIM | 0x00000081)
 
 
 /*
@@ -292,23 +292,23 @@
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	0x18803112
-#define CFG_MAMR_9COL	0x18803112	/* same as 8 column because its just easier to port with*/
+#define CONFIG_SYS_MAMR_8COL	0x18803112
+#define CONFIG_SYS_MAMR_9COL	0x18803112	/* same as 8 column because its just easier to port with*/
 
 
 /*
diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h
index adf79c7..c36f2bb1 100644
--- a/include/configs/ETX094.h
+++ b/include/configs/ETX094.h
@@ -76,7 +76,7 @@
 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/
 
@@ -102,25 +102,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0300000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -130,46 +130,46 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
 #ifdef	DEBUG
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	35	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	35	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #ifdef CONFIG_FLASH_16BIT
@@ -183,16 +183,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -202,10 +202,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif	/* CONFIG_WATCHDOG */
 
 /*-----------------------------------------------------------------------
@@ -213,27 +213,27 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -241,7 +241,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit - leave PLL multiplication factor unchanged !
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -250,7 +250,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS     | \
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -260,21 +260,21 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -289,26 +289,26 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /* FLASH timing: ACS = 11, TRLX = 1, CSNT = 0, SCY = 2, EHTR = 0	*/
-#define CFG_OR_TIMING_FLASH    (OR_ACS_DIV2 | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH    (OR_ACS_DIV2 | OR_BI | \
 			       OR_SCY_2_CLK | OR_TRLX )
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 
 #ifdef CONFIG_FLASH_16BIT	/* 16 bit data port */
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
 #else				/* 32 bit data port */
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
 #endif	/* CONFIG_FLASH_16BIT */
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -319,39 +319,39 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /*
  * Memory Periodic Timer Prescaler
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	23		/* start with divider for 100 MHz	*/
+#define CONFIG_SYS_MAMR_PTA	23		/* start with divider for 100 MHz	*/
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_1X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_1X)
 
diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h
index f98831e..bf41c13 100644
--- a/include/configs/EVB64260.h
+++ b/include/configs/EVB64260.h
@@ -40,7 +40,7 @@
  */
 
 #define CONFIG_EVB64260		1	/* this is an EVB64260 board	*/
-#define CFG_GT_6426x        GT_64260 /* with a 64260 system controller */
+#define CONFIG_SYS_GT_6426x        GT_64260 /* with a 64260 system controller */
 
 #define CONFIG_BAUDRATE		38400	/* console baudrate = 38400	*/
 
@@ -52,13 +52,13 @@
 #define CONFIG_BOARD_EARLY_INIT_F 1
 
 #ifndef CONFIG_EVB64260_750CX
-#define CFG_BOARD_NAME		"EVB64260"
+#define CONFIG_SYS_BOARD_NAME		"EVB64260"
 #else
-#define CFG_BOARD_NAME         "EVB64260-750CX"
+#define CONFIG_SYS_BOARD_NAME         "EVB64260-750CX"
 #endif
 
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 /*
  * The following defines let you select what serial you want to use
@@ -66,7 +66,7 @@
  *
  * what to do:
  * to use the DUART, undef CONFIG_MPSC.  If you have hacked a serial
- * cable onto the second DUART channel, change the CFG_DUART port from 1
+ * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
  * to 0 below.
  *
  * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
@@ -98,7 +98,7 @@
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
-#define	CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+#define	CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 #undef	CONFIG_ALTIVEC                  /* undef to disable             */
@@ -124,31 +124,31 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x00300000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x00300000	/* default load address	*/
 
-#define	CFG_HZ			1000		/* decr freq: 1ms ticks	*/
-#define CFG_BUS_HZ		100000000	/* 100 MHz		*/
-#define CFG_BUS_CLK		CFG_BUS_HZ
+#define	CONFIG_SYS_HZ			1000		/* decr freq: 1ms ticks	*/
+#define CONFIG_SYS_BUS_HZ		100000000	/* 100 MHz		*/
+#define CONFIG_SYS_BUS_CLK		CONFIG_SYS_BUS_HZ
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #ifdef CONFIG_EVB64260_750CX
 #define CONFIG_750CX
-#define CFG_BROKEN_CL2
+#define CONFIG_SYS_BROKEN_CL2
 #endif
 
 /*
@@ -160,51 +160,51 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area
  */
-#define CFG_INIT_RAM_ADDR	0x40000000
-#define	CFG_INIT_RAM_END	0x1000
-#define	CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define	CONFIG_SYS_INIT_RAM_END	0x1000
+#define	CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_LOCK
 
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xfff00000
-#define CFG_RESET_ADDRESS	0xfff00100
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xfff00000
+#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
 
 /* areas to map different things with the GT in physical space */
-#define CFG_DRAM_BANKS		4
-#define CFG_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */
+#define CONFIG_SYS_DRAM_BANKS		4
+#define CONFIG_SYS_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */
 
 /* What to put in the bats. */
-#define CFG_MISC_REGION_BASE	0xf0000000
+#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
 
 /* Peripheral Device section */
-#define CFG_GT_REGS		0xf8000000
-#define CFG_DEV_BASE		0xfc000000
-
-#define CFG_DEV0_SPACE		CFG_DEV_BASE
-#define CFG_DEV1_SPACE		(CFG_DEV0_SPACE + CFG_DEV0_SIZE)
-#define CFG_DEV2_SPACE		(CFG_DEV1_SPACE + CFG_DEV1_SIZE)
-#define CFG_DEV3_SPACE		(CFG_DEV2_SPACE + CFG_DEV2_SIZE)
-
-#define CFG_DEV0_SIZE		 _8M /* evb64260 sram  @ 0xfc00.0000 */
-#define CFG_DEV1_SIZE		 _8M /* evb64260 rtc   @ 0xfc80.0000 */
-#define CFG_DEV2_SIZE		_16M /* evb64260 duart @ 0xfd00.0000 */
-#define CFG_DEV3_SIZE		_16M /* evb64260 flash @ 0xfe00.0000 */
-
-#define CFG_DEV0_PAR		0x20205093
-#define CFG_DEV1_PAR		0xcfcfffff
-#define CFG_DEV2_PAR		0xc0059bd4
-#define CFG_8BIT_BOOT_PAR	0xc00b5e7c
-#define CFG_32BIT_BOOT_PAR	0xc4a8241c
+#define CONFIG_SYS_GT_REGS		0xf8000000
+#define CONFIG_SYS_DEV_BASE		0xfc000000
+
+#define CONFIG_SYS_DEV0_SPACE		CONFIG_SYS_DEV_BASE
+#define CONFIG_SYS_DEV1_SPACE		(CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
+#define CONFIG_SYS_DEV2_SPACE		(CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
+#define CONFIG_SYS_DEV3_SPACE		(CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
+
+#define CONFIG_SYS_DEV0_SIZE		 _8M /* evb64260 sram  @ 0xfc00.0000 */
+#define CONFIG_SYS_DEV1_SIZE		 _8M /* evb64260 rtc   @ 0xfc80.0000 */
+#define CONFIG_SYS_DEV2_SIZE		_16M /* evb64260 duart @ 0xfd00.0000 */
+#define CONFIG_SYS_DEV3_SIZE		_16M /* evb64260 flash @ 0xfe00.0000 */
+
+#define CONFIG_SYS_DEV0_PAR		0x20205093
+#define CONFIG_SYS_DEV1_PAR		0xcfcfffff
+#define CONFIG_SYS_DEV2_PAR		0xc0059bd4
+#define CONFIG_SYS_8BIT_BOOT_PAR	0xc00b5e7c
+#define CONFIG_SYS_32BIT_BOOT_PAR	0xc4a8241c
 	/*   c    4    a      8     2     4    1      c		*/
 	/* 33 22|2222|22 22|111 1|11 11|1 1  |    |		*/
 	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
@@ -212,19 +212,19 @@
 	/*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/
 
 #if 0 /* Wrong?? NTL */
-#define CFG_MPP_CONTROL_0	0x53541717	/* InitAct EOT[4] DBurst TCEn[1] */
+#define CONFIG_SYS_MPP_CONTROL_0	0x53541717	/* InitAct EOT[4] DBurst TCEn[1] */
 						/* DMAAck[1:0] GNT0[1:0] */
 #else
-#define CFG_MPP_CONTROL_0	0x53547777	/* InitAct EOT[4] DBurst TCEn[1] */
+#define CONFIG_SYS_MPP_CONTROL_0	0x53547777	/* InitAct EOT[4] DBurst TCEn[1] */
 						/* REQ0[1:0] GNT0[1:0] */
 #endif
-#define CFG_MPP_CONTROL_1	0x44009911	/* TCEn[4] TCTcnt[4] GPP[13:12] */
+#define CONFIG_SYS_MPP_CONTROL_1	0x44009911	/* TCEn[4] TCTcnt[4] GPP[13:12] */
 						/* DMAReq[4] DMAAck[4] WDNMI WDE */
 #if 0 /* Wrong?? NTL */
-#define CFG_MPP_CONTROL_2	0x40091818	/* TCTcnt[0] GPP[22:21] BClkIn */
+#define CONFIG_SYS_MPP_CONTROL_2	0x40091818	/* TCTcnt[0] GPP[22:21] BClkIn */
 						/* DMAAck[1:0] GNT1[1:0] */
 #else
-#define CFG_MPP_CONTROL_2	0x40098888	/* TCTcnt[0] */
+#define CONFIG_SYS_MPP_CONTROL_2	0x40098888	/* TCTcnt[0] */
 						/* GPP[22] (RS232IntB or PCI1Int) */
 						/* GPP[21] (RS323IntA) */
 						/* BClkIn */
@@ -232,10 +232,10 @@
 #endif
 
 #if 0 /* Wrong?? NTL */
-# define CFG_MPP_CONTROL_3	0x00090066	/* GPP[31:29] BClkOut0 */
+# define CONFIG_SYS_MPP_CONTROL_3	0x00090066	/* GPP[31:29] BClkOut0 */
 						/* GPP[27:26] Int[1:0] */
 #else
-# define CFG_MPP_CONTROL_3	0x22090066      /* MREQ MGNT */
+# define CONFIG_SYS_MPP_CONTROL_3	0x22090066      /* MREQ MGNT */
 						/* GPP[29]    (PCI1Int) */
 						/* BClkOut0 */
 						/* GPP[27]    (PCI0Int) */
@@ -243,17 +243,17 @@
 						/* CPUInt[25:24] */
 #endif
 
-# define CFG_SERIAL_PORT_MUX	0x00000102	/* 0=hiZ  1=MPSC0 2=ETH 0 and 2 RMII */
+# define CONFIG_SYS_SERIAL_PORT_MUX	0x00000102	/* 0=hiZ  1=MPSC0 2=ETH 0 and 2 RMII */
 
 #if 0 /* Wrong?? - NTL */
-# define CFG_GPP_LEVEL_CONTROL	0x000002c6
+# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x000002c6
 #else
-# define CFG_GPP_LEVEL_CONTROL	0x2c600000	/* 0010 1100 0110 0000 */
+# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x2c600000	/* 0010 1100 0110 0000 */
 						/* gpp[29] */
 						/* gpp[27:26] */
 						/* gpp[22:21] */
 
-# define CFG_SDRAM_CONFIG	0xd8e18200	/* 0x448 */
+# define CONFIG_SYS_SDRAM_CONFIG	0xd8e18200	/* 0x448 */
 				/* idmas use buffer 1,1
 				   comm use buffer 0
 				   pci use buffer 1,1
@@ -270,12 +270,12 @@
 				/* 1  0  0x200 */
 #endif
 
-#define CFG_DUART_IO		CFG_DEV2_SPACE
-#define CFG_DUART_CHAN		1		/* channel to use for console */
-#define CFG_INIT_CHAN1
-#define CFG_INIT_CHAN2
+#define CONFIG_SYS_DUART_IO		CONFIG_SYS_DEV2_SPACE
+#define CONFIG_SYS_DUART_CHAN		1		/* channel to use for console */
+#define CONFIG_SYS_INIT_CHAN1
+#define CONFIG_SYS_INIT_CHAN2
 
-#define SRAM_BASE		CFG_DEV0_SPACE
+#define SRAM_BASE		CONFIG_SYS_DEV0_SPACE
 #define SRAM_SIZE		0x00100000		/* 1 MB of sram */
 
 
@@ -293,37 +293,37 @@
 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 
 /* PCI MEMORY MAP section */
-#define CFG_PCI0_MEM_BASE	0x80000000
-#define CFG_PCI0_MEM_SIZE	_128M
-#define CFG_PCI1_MEM_BASE	0x88000000
-#define CFG_PCI1_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
 
-#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
-#define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
+#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
+#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
 
 
 /* PCI I/O MAP section */
-#define CFG_PCI0_IO_BASE	0xfa000000
-#define CFG_PCI0_IO_SIZE	_16M
-#define CFG_PCI1_IO_BASE	0xfb000000
-#define CFG_PCI1_IO_SIZE	_16M
+#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
+#define CONFIG_SYS_PCI0_IO_SIZE	_16M
+#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
+#define CONFIG_SYS_PCI1_IO_SIZE	_16M
 
-#define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
-#define CFG_PCI0_IO_SPACE_PCI	0x00000000
-#define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
-#define CFG_PCI1_IO_SPACE_PCI	0x00000000
+#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
+#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000
+#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
+#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000
 
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
+#define CONFIG_SYS_NS16550
 
-#define CFG_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
 
-#define CFG_NS16550_CLK		3686400
+#define CONFIG_SYS_NS16550_CLK		3686400
 
-#define CFG_NS16550_COM1	(CFG_DUART_IO + 0)
-#define CFG_NS16550_COM2	(CFG_DUART_IO + 0x20)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_DUART_IO + 0)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_DUART_IO + 0x20)
 
 /*----------------------------------------------------------------------
  * Initial BAT mappings
@@ -335,32 +335,32 @@
  */
 
 /* SDRAM */
-#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT0U CFG_IBAT0U
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
 
 /* init ram */
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 
 /* PCI0, PCI1 in one BAT */
-#define CFG_IBAT2L BATL_NO_ACCESS
-#define CFG_IBAT2U CFG_DBAT2U
-#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
+#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* GT regs, bootrom, all the devices, PCI I/O */
-#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 
 /* I2C speed and slave address (for compatability) defaults */
-#define CFG_I2C_SPEED	400000
-#define CFG_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_SPEED	400000
+#define CONFIG_SYS_I2C_SLAVE	0x7F
 
 /* I2C addresses for the two DIMM SPD chips */
 #ifndef CONFIG_EVB64260_750CX
@@ -376,32 +376,32 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8<<20)	/* Initial Memory map for Linux */
+#define	CONFIG_SYS_BOOTMAPSZ		(8<<20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
 
-#define CFG_EXTRA_FLASH_DEVICE	DEVICE3	/* extra flash at device 3 */
-#define CFG_EXTRA_FLASH_WIDTH	4	/* 32 bit */
+#define CONFIG_SYS_EXTRA_FLASH_DEVICE	DEVICE3	/* extra flash at device 3 */
+#define CONFIG_SYS_EXTRA_FLASH_WIDTH	4	/* 32 bit */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_CFI		1
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_CFI		1
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
 #define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_ADDR    (CFG_FLASH_BASE+CFG_MONITOR_LEN-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR    (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE)
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -409,7 +409,7 @@
  * look in include/74xx_7xx.h for the defines used here
  */
 
-#define CFG_L2
+#define CONFIG_SYS_L2
 
 #ifdef CONFIG_750CX
 #define L2_INIT		0
@@ -428,7 +428,7 @@
 #define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02		/* Software reboot		    */
 
-#define CFG_BOARD_ASM_INIT      1
+#define CONFIG_SYS_BOARD_ASM_INIT      1
 
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h
index 5ba1706..1dd6e57 100644
--- a/include/configs/EXBITGEN.h
+++ b/include/configs/EXBITGEN.h
@@ -43,8 +43,8 @@
 
 /* I2C configuration */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#define CFG_I2C_SPEED		40000	/* I2C speed			*/
-#define CFG_I2C_SLAVE		0x7F	/* I2C slave address		*/
+#define CONFIG_SYS_I2C_SPEED		40000	/* I2C speed			*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave address		*/
 
 /* environment is in EEPROM */
 #define CONFIG_ENV_IS_IN_EEPROM    1
@@ -52,11 +52,11 @@
 #undef CONFIG_ENV_IS_IN_NVRAM
 
 #ifdef CONFIG_ENV_IS_IN_EEPROM
-#define CFG_I2C_EEPROM_ADDR		0x56    /* 1010110 */
-#define CFG_I2C_EEPROM_ADDR_LEN		1	/* 8-bit internal addressing */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	1	/* ... and 1 bit in I2C address */
-#define CFG_EEPROM_PAGE_WRITE_BITS	3	/* 4 bytes per page */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	40	/* write takes up to 40 msec */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x56    /* 1010110 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1	/* 8-bit internal addressing */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	1	/* ... and 1 bit in I2C address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3	/* 4 bytes per page */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	40	/* write takes up to 40 msec */
 #define CONFIG_ENV_OFFSET		4	/* Offset of Environment Sector	*/
 #define	CONFIG_ENV_SIZE		350	/* that is 350 bytes only!	*/
 #endif
@@ -77,7 +77,7 @@
 				"ram=128M debug"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
@@ -88,6 +88,7 @@
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
@@ -103,37 +104,37 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
 /* UART configuration */
-#define CFG_BASE_BAUD		691200
+#define CONFIG_SYS_BASE_BAUD		691200
 
 /* Default baud rate */
 #define CONFIG_BAUDRATE		115200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CONFIG_SYS_BAUDRATE_TABLE      \
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_CLKS_IN_HZ		1	/* everything, incl board info, in Hz */
+#define CONFIG_SYS_CLKS_IN_HZ		1	/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -149,28 +150,28 @@
 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 #undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
 
-#define	CFG_KEY_REG_BASE_ADDR	0xF0100000
-#define	CFG_IR_REG_BASE_ADDR	0xF0200000
-#define	CFG_FPGA_REG_BASE_ADDR	0xF0300000
+#define	CONFIG_SYS_KEY_REG_BASE_ADDR	0xF0100000
+#define	CONFIG_SYS_IR_REG_BASE_ADDR	0xF0200000
+#define	CONFIG_SYS_FPGA_REG_BASE_ADDR	0xF0300000
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH0_BASE		0xFFF80000
-#define CFG_FLASH0_SIZE		0x00080000
-#define CFG_FLASH1_BASE		0x20000000
-#define CFG_FLASH1_SIZE		0x02000000
-#define CFG_FLASH_BASE		CFG_FLASH0_BASE
-#define CFG_FLASH_SIZE		CFG_FLASH0_SIZE
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-#if CFG_MONITOR_BASE < CFG_FLASH0_BASE
-#define CFG_RAMSTART
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH0_BASE		0xFFF80000
+#define CONFIG_SYS_FLASH0_SIZE		0x00080000
+#define CONFIG_SYS_FLASH1_BASE		0x20000000
+#define CONFIG_SYS_FLASH1_SIZE		0x02000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_FLASH_SIZE		CONFIG_SYS_FLASH0_SIZE
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_RAMSTART
 #endif
 
 /*
@@ -178,15 +179,15 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	5	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	5	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_OFFSET		0x00060000 /* Offset of Environment Sector      */
@@ -195,15 +196,15 @@
 #endif
 
 /* On Chip Memory location/size */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 
 /* Global info and initial stack */
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of on-chip SRAM	*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM	*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Internal Definitions
diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h
index abf51ef..cb75960 100644
--- a/include/configs/FADS823.h
+++ b/include/configs/FADS823.h
@@ -18,14 +18,14 @@
  * 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot
 */
 
-#define CFG_PCMCIA_IO_ADDR	0xff020000
-#define CFG_PCMCIA_IO_SIZE	0x10000
-#define CFG_PCMCIA_MEM_ADDR	0xe0000000
-#define CFG_PCMCIA_MEM_SIZE	0x10000
-#define CFG_IMMR		0xFF000000
-#define	CFG_SDRAM_SIZE		(4<<20) /* standard FADS has 4M */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x02800000
+#define CONFIG_SYS_PCMCIA_IO_ADDR	0xff020000
+#define CONFIG_SYS_PCMCIA_IO_SIZE	0x10000
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	0xe0000000
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	0x10000
+#define CONFIG_SYS_IMMR		0xFF000000
+#define	CONFIG_SYS_SDRAM_SIZE		(4<<20) /* standard FADS has 4M */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x02800000
 #define BCSR_ADDR		((uint) 0xff010000)
 #define FLASH_BASE0_PRELIM	0x02800000	/* FLASH bank #0	*/
 
@@ -43,8 +43,8 @@
 
 #define CONFIG_VIDEO		1	/* To enable video controller support */
 #define CONFIG_HARD_I2C		1	/* To I2C with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*#define CONFIG_PCMCIA		1	/ * To enable PCMCIA support */
 
@@ -82,7 +82,7 @@
 #else
 #define MPC8XX_FACT	10			/* Multiply by 10 */
 #define MPC8XX_XIN	5000000			/* 5 MHz in */
-#define CFG_PLPRCR_MF	(MPC8XX_FACT-1) << 20	/* From 0 to 4095 */
+#define CONFIG_SYS_PLPRCR_MF	(MPC8XX_FACT-1) << 20	/* From 0 to 4095 */
 #endif
 #define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
 
@@ -134,25 +134,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		":>"		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		":>"		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00004000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x01000000	/* 0 ... 16 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00004000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x01000000	/* 0 ... 16 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x00100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -162,58 +162,58 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+#define CONFIG_SYS_IMMR_SIZE		((uint)(64 * 1024))
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
  */
-#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+#define CONFIG_SYS_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
 #if 0
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
 #define	CONFIG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -223,10 +223,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -234,21 +234,21 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control					11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
@@ -256,7 +256,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer  *
  * interrupt status bit - leave PLL multiplication factor unchanged !
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CONFIG_SYS_PLPRCR_MF)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -265,7 +265,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR       (SCCR_TBS     | \
+#define CONFIG_SYS_SCCR       (SCCR_TBS     | \
 				SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 				SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 				SCCR_DFALCD00)
@@ -275,7 +275,7 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER		0
+#define CONFIG_SYS_DER		0
 
 /* Because of the way the 860 starts up and assigns CS0 the
 * entire address space, we have to set the memory controller
@@ -296,20 +296,20 @@
 
 #define FLASH_BASE1_PRELIM	0x00000000	/* FLASH bank #1	*/
 
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFFE00000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFFE00000	/* OR addr mask */
 
 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
 /* BCSRx - Board Control and Status Registers */
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	0xffff8110									/* 64Kbyte address space */
-#define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	0xffff8110									/* 64Kbyte address space */
+#define CONFIG_SYS_BR1_PRELIM	((BCSR_ADDR) | BR_V )
 
 
 /*
@@ -317,30 +317,30 @@
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA		97		/* start with divider for 100 MHz	*/
+#define CONFIG_SYS_MAMR_PTA		97		/* start with divider for 100 MHz	*/
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
-#define CFG_MAMR		0x13a01114
+#define CONFIG_SYS_MAMR		0x13a01114
 /*
  * Internal Definitions
  *
@@ -477,6 +477,6 @@
 #define PCMCIA_SLOT_A 1
 #endif
 
-#define CFG_DAUGHTERBOARD
+#define CONFIG_SYS_DAUGHTERBOARD
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h
index d617868..84187fb 100644
--- a/include/configs/FADS850SAR.h
+++ b/include/configs/FADS850SAR.h
@@ -80,25 +80,25 @@
 /*
  * Miscellaneous configurable options
  */
-#undef	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		":>"		/* Monitor Command Prompt	*/
+#undef	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		":>"		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00004000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00800000	/* 0 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00004000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00800000	/* 0 ... 8 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x00100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -108,62 +108,62 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR			0xFF000000
-#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+#define CONFIG_SYS_IMMR			0xFF000000
+#define CONFIG_SYS_IMMR_SIZE		((uint)(64 * 1024))
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define	CFG_SDRAM_SIZE		(4<<20) /* standard FADS has 4M */
-#define CFG_FLASH_BASE		0x02800000
-#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define	CONFIG_SYS_SDRAM_SIZE		(4<<20) /* standard FADS has 4M */
+#define CONFIG_SYS_FLASH_BASE		0x02800000
+#define CONFIG_SYS_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
 #if 0
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 128 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 128 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
 #define	CONFIG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -173,10 +173,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -184,21 +184,21 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control					11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
@@ -206,7 +206,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer  *
  * interrupt status bit - leave PLL multiplication factor unchanged !
  */
-#define CFG_PLPRCR	(((MPC8XX_FACT-1) << 20) | \
+#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << 20) | \
 				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
@@ -216,7 +216,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR       (SCCR_TBS     | \
+#define CONFIG_SYS_SCCR       (SCCR_TBS     | \
 				SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 				SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 				SCCR_DFALCD00)
@@ -226,7 +226,7 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER		0
+#define CONFIG_SYS_DER		0
 
 /* Because of the way the 860 starts up and assigns CS0 the
 * entire address space, we have to set the memory controller
@@ -250,20 +250,20 @@
 #define FLASH_BASE0_PRELIM	0x02800000	/* FLASH bank #0	*/
 #define FLASH_BASE1_PRELIM	0x00000000	/* FLASH bank #1	*/
 
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFFE00000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFFE00000	/* OR addr mask */
 
 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
 /* BCSRx - Board Control and Status Registers */
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	0xffff8110									/* 64Kbyte address space */
-#define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	0xffff8110									/* 64Kbyte address space */
+#define CONFIG_SYS_BR1_PRELIM	((BCSR_ADDR) | BR_V )
 
 
 /*
@@ -271,30 +271,30 @@
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA		97		/* start with divider for 100 MHz	*/
+#define CONFIG_SYS_MAMR_PTA		97		/* start with divider for 100 MHz	*/
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
-#define CFG_MAMR		0x13a01114
+#define CONFIG_SYS_MAMR		0x13a01114
 /*
  * Internal Definitions
  *
@@ -421,6 +421,6 @@
 #define PCMCIA_SLOT_A 1
 #endif
 
-#define CFG_DAUGHTERBOARD
+#define CONFIG_SYS_DAUGHTERBOARD
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/FADS860T.h b/include/configs/FADS860T.h
index 38295c4..dcb0c39 100644
--- a/include/configs/FADS860T.h
+++ b/include/configs/FADS860T.h
@@ -27,12 +27,12 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 
 #if 0 /* old FADS */
-# define CFG_8XX_FACT		12	/* 4 MHz oscillator on EXTCLK */
+# define CONFIG_SYS_8XX_FACT		12	/* 4 MHz oscillator on EXTCLK */
 #else /* new FADS */
-# define CFG_8XX_FACT		10	/* 5 MHz oscillator on EXTCLK */
+# define CONFIG_SYS_8XX_FACT		10	/* 5 MHz oscillator on EXTCLK */
 #endif
 
-#define CFG_PLPRCR  (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+#define CONFIG_SYS_PLPRCR  (((CONFIG_SYS_8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
 		PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 #define CONFIG_DRAM_50MHZ		1
@@ -45,12 +45,12 @@
  * These values fit our FADS860T ...
  * The "default" behaviour with 1Mbyte initial doesn't work for us!
  */
-#undef CFG_OR0_PRELIM
-#undef CFG_BR0_PRELIM
-#define CFG_OR0_PRELIM	0x0FFC00D34 /* Real values for the board */
-#define CFG_BR0_PRELIM	0x02800001  /* Real values for the board */
+#undef CONFIG_SYS_OR0_PRELIM
+#undef CONFIG_SYS_BR0_PRELIM
+#define CONFIG_SYS_OR0_PRELIM	0x0FFC00D34 /* Real values for the board */
+#define CONFIG_SYS_BR0_PRELIM	0x02800001  /* Real values for the board */
 #endif
 
-#define CFG_DAUGHTERBOARD /* FADS has processor-specific daughterboard */
+#define CONFIG_SYS_DAUGHTERBOARD /* FADS has processor-specific daughterboard */
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/FLAGADM.h b/include/configs/FLAGADM.h
index 52b5ab4..d831238 100644
--- a/include/configs/FLAGADM.h
+++ b/include/configs/FLAGADM.h
@@ -57,7 +57,7 @@
 #endif /* 0|1*/
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 /*#define	CONFIG_WATCHDOG*/	/* watchdog enabled		*/
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
@@ -83,7 +83,7 @@
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_LOADB
 #define CONFIG_CMD_LOADS
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_IMMAP
 #define CONFIG_CMD_NET
@@ -92,25 +92,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"EEG> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"EEG> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x40040000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x40040000	/* default load address */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -120,43 +120,43 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFF000000
+#define CONFIG_SYS_IMMR		0xFF000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 /* This is a litlebit wasteful, but one sector is 128kb and we have to
@@ -169,9 +169,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -181,9 +181,9 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #ifdef CONFIG_WATCHDOG
-#define CFG_SYPCR (SYPCR_SWTC | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -191,29 +191,29 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_PRE_SIUMCR (SIUMCR_DBGC11 | SIUMCR_MPRE | \
+#define CONFIG_SYS_PRE_SIUMCR (SIUMCR_DBGC11 | SIUMCR_MPRE | \
 							SIUMCR_MLRC01 | SIUMCR_GB5E)
-#define CFG_SIUMCR (CFG_PRE_SIUMCR | SIUMCR_DLK)
+#define CONFIG_SYS_SIUMCR (CONFIG_SYS_PRE_SIUMCR | SIUMCR_DLK)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -222,7 +222,7 @@
  * interrupt status bit miltiplier of 0x00b i.e. operation clock is
  * 4MHz * (0x00b+1) = 4MHz * 12 =  48MHz
  */
-#define CFG_PLPRCR	(0x00b00000 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(0x00b00000 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -231,11 +231,11 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	( SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CONFIG_SYS_SCCR	( SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 
-#define CFG_DER 0
+#define CONFIG_SYS_DER 0
 
 /*
  * In the Flaga DM we have:
@@ -250,7 +250,7 @@
  * untouched.
 */
 
-#define CFG_FLASH_PROTECTION 0
+#define CONFIG_SYS_FLASH_PROTECTION 0
 
 #define FLASH_BASE0		0x40000000	/* FLASH bank #0	*/
 
@@ -258,15 +258,15 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_OR_AM		0xff000000	/* OR addr mask */
-#define CFG_OR_ATM		0x00006000
+#define CONFIG_SYS_OR_AM		0xff000000	/* OR addr mask */
+#define CONFIG_SYS_OR_ATM		0x00006000
 
 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | \
 				 OR_SCY_3_CLK | OR_TRLX | OR_EHTR )
 
-#define CFG_OR0_PRELIM	(CFG_OR_AM | CFG_OR_ATM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0 & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_OR_AM | CONFIG_SYS_OR_ATM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0 & BR_BA_MSK) | BR_PS_16 | BR_V )
 
 /*
  * BR2 and OR2 (SDRAM)
@@ -276,18 +276,18 @@
 #define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	( 0x00000800 )
+#define CONFIG_SYS_OR_TIMING_SDRAM	( 0x00000800 )
 
-#define CFG_OR2_PRELIM	(CFG_OR_AM | CFG_OR_TIMING_SDRAM)
-#define CFG_BR2_PRELIM	((SDRAM_BASE2 & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM)
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2 & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
-#define CFG_BR2			CFG_BR2_PRELIM
-#define CFG_OR2			CFG_OR2_PRELIM
+#define CONFIG_SYS_BR2			CONFIG_SYS_BR2_PRELIM
+#define CONFIG_SYS_OR2			CONFIG_SYS_OR2_PRELIM
 
 /*
  * MAMR settings for SDRAM
  */
-#define CFG_MAMR_48_SDR (CFG_MAMR_PTA |	 MAMR_WLFA_1X | MAMR_RLFA_1X  \
+#define CONFIG_SYS_MAMR_48_SDR (CONFIG_SYS_MAMR_PTA |	 MAMR_WLFA_1X | MAMR_RLFA_1X  \
 					| MAMR_G0CLA_A11)
 
 /*
@@ -295,7 +295,7 @@
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	0x0F000000
+#define CONFIG_SYS_MAMR_PTA	0x0F000000
 
 /*
    * BR4 and OR4 (DSP1)
@@ -306,8 +306,8 @@
 */
 #define DSP_BASE 0x80000000
 
-#define CFG_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI | OR_G5LS)
-#define CFG_BR4 ( (DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_UPMB | BR_V )
+#define CONFIG_SYS_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI | OR_G5LS)
+#define CONFIG_SYS_BR4 ( (DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_UPMB | BR_V )
 
 /*
  * Internal Definitions
diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h
index c9d6c91..08408e2 100644
--- a/include/configs/FPS850L.h
+++ b/include/configs/FPS850L.h
@@ -80,7 +80,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -124,32 +124,32 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -159,47 +159,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
@@ -209,7 +209,7 @@
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 #define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
 
@@ -228,16 +228,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -247,10 +247,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -258,27 +258,27 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -286,7 +286,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit - leave PLL multiplication factor unchanged !
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -295,7 +295,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS     | \
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -305,21 +305,21 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -334,22 +334,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -360,13 +360,13 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /*
  * Memory Periodic Timer Prescaler
@@ -395,34 +395,34 @@
  * 80 Mhz => 80.000.000 / Divider = 156
  */
 
-#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
-#define CFG_MAMR_PTA	98
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h
index bf20a0d..e5f3b60 100644
--- a/include/configs/FPS860L.h
+++ b/include/configs/FPS860L.h
@@ -80,7 +80,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -124,32 +124,32 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -159,47 +159,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
@@ -209,7 +209,7 @@
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 #define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
 
@@ -228,16 +228,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -247,10 +247,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -258,27 +258,27 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -286,7 +286,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit - leave PLL multiplication factor unchanged !
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -295,7 +295,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS     | \
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -305,21 +305,21 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -334,22 +334,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -360,13 +360,13 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /*
  * Memory Periodic Timer Prescaler
@@ -395,34 +395,34 @@
  * 80 Mhz => 80.000.000 / Divider = 156
  */
 
-#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
-#define CFG_MAMR_PTA	98
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/G2000.h b/include/configs/G2000.h
index 81a12f1..bf9fd82 100644
--- a/include/configs/G2000.h
+++ b/include/configs/G2000.h
@@ -76,10 +76,11 @@
 	""
 #define CONFIG_BOOTCOMMAND	"run net_nfs"
 
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_NET_MULTI	1
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_PHY1_ADDR	1	/* PHY address			*/
@@ -124,53 +125,52 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
 #undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*----------------------------------------------------------------------------*/
 /* adding Ethernet setting:  FTS OUI 00:11:0B */
@@ -188,14 +188,14 @@
  *-----------------------------------------------------------------------
  */
 #define CONFIG_RTC_DS1337
-#define CFG_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
 
 #if 0 /* test-only */
 /*-----------------------------------------------------------------------
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
 #define SECTORSIZE 512
 
 #define ADDR_COLUMN 1
@@ -204,20 +204,19 @@
 
 #define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
 
-#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
+#define CONFIG_SYS_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
+#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
+#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
 
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CE);} while(0)
+#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_CE);} while(0)
+#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_ALE);} while(0)
+#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_ALE);} while(0)
+#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_CLE);} while(0)
+#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CLE);} while(0)
+#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CONFIG_SYS_NAND_RDY))
 
 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
@@ -242,58 +241,58 @@
 
 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #if 0 /* APC405 */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#undef CFG_FLASH_PROTECTION		/* don't use hardware protection	*/
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_BASE		0xFE000000 /* test-only...*/
-#define CFG_FLASH_INCREMENT	0x01000000 /* test-only */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#undef CONFIG_SYS_FLASH_PROTECTION		/* don't use hardware protection	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* test-only...*/
+#define CONFIG_SYS_FLASH_INCREMENT	0x01000000 /* test-only */
 #else /* G2000 */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#undef CFG_FLASH_PROTECTION		/* don't use hardware protection	*/
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_BASE		0xFF800000 /* test-only...*/
-#define CFG_FLASH_INCREMENT	0x01000000 /* test-only */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#undef CONFIG_SYS_FLASH_PROTECTION		/* don't use hardware protection	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_BASE		0xFF800000 /* test-only...*/
+#define CONFIG_SYS_FLASH_INCREMENT	0x01000000 /* test-only */
 #endif
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 
-#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains u-boot    */
+#define CONFIG_SYS_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
+#define CONFIG_SYS_JFFS2_NUM_BANKS     1           /* ! second bank contains u-boot    */
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MONITOR_BASE	0xFFFC0000
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_BASE	0xFFFC0000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
 
 /*-----------------------------------------------------------------------
  * Environment Variable setup
@@ -316,63 +315,62 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
 /* CAT24WC08/16... */
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  */
 
 /* Memory Bank 0 (Intel Strata Flash) initialization                            */
-#define CFG_EBC_PB0AP   0x92015480
-#define CFG_EBC_PB0CR   0xFF87A000          /* BAS=0xFF8,BS=08MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB0AP   0x92015480
+#define CONFIG_SYS_EBC_PB0CR   0xFF87A000          /* BAS=0xFF8,BS=08MB,BU=R/W,BW=16bit*/
 
 /* Memory Bank 1 ( Power TAU) initialization               */
-/* #define CFG_EBC_PB1AP           0x04041000 */
-/* #define CFG_EBC_PB1CR           0xF0018000   */  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
-#define CFG_EBC_PB1AP           0x00000000
-#define CFG_EBC_PB1CR           0x00000000
+/* #define CONFIG_SYS_EBC_PB1AP           0x04041000 */
+/* #define CONFIG_SYS_EBC_PB1CR           0xF0018000   */  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+#define CONFIG_SYS_EBC_PB1AP           0x00000000
+#define CONFIG_SYS_EBC_PB1CR           0x00000000
 
 /* Memory Bank 2 (Intel Flash) initialization                 */
-#define CFG_EBC_PB2AP           0x00000000
-#define CFG_EBC_PB2CR           0x00000000
+#define CONFIG_SYS_EBC_PB2AP           0x00000000
+#define CONFIG_SYS_EBC_PB2CR           0x00000000
 
 /* Memory Bank 3 (NAND) initialization                        */
-#define CFG_EBC_PB3AP           0x92015480
-#define CFG_EBC_PB3CR           0xF40B8000  /*addr 0xF40, BS=32M,BU=R/W, BW=8bit */
+#define CONFIG_SYS_EBC_PB3AP           0x92015480
+#define CONFIG_SYS_EBC_PB3CR           0xF40B8000  /*addr 0xF40, BS=32M,BU=R/W, BW=8bit */
 
 /* Memory Bank 4 (FPGA regs) initialization                                     */
-#define CFG_EBC_PB4AP           0x00000000
-#define CFG_EBC_PB4CR           0x00000000  /* leave it blank  */
+#define CONFIG_SYS_EBC_PB4AP           0x00000000
+#define CONFIG_SYS_EBC_PB4CR           0x00000000  /* leave it blank  */
 
-#define CFG_NAND_BASE   0xF4000000
+#define CONFIG_SYS_NAND_BASE   0xF4000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
 
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup (PPC405EP specific)
@@ -388,13 +386,13 @@
  *
  * following GPIO setting changed for G20000, 080304
  */
-#define CFG_GPIO0_OSRH          0x40005555
-#define CFG_GPIO0_OSRL          0x40000110
-#define CFG_GPIO0_ISR1H         0x00000000
-#define CFG_GPIO0_ISR1L         0x15555445
-#define CFG_GPIO0_TSRH          0x00000000
-#define CFG_GPIO0_TSRL          0x00000000
-#define CFG_GPIO0_TCR           0xF7FF8014
+#define CONFIG_SYS_GPIO0_OSRH          0x40005555
+#define CONFIG_SYS_GPIO0_OSRL          0x40000110
+#define CONFIG_SYS_GPIO0_ISR1H         0x00000000
+#define CONFIG_SYS_GPIO0_ISR1L         0x15555445
+#define CONFIG_SYS_GPIO0_TSRH          0x00000000
+#define CONFIG_SYS_GPIO0_TSRL          0x00000000
+#define CONFIG_SYS_GPIO0_TCR           0xF7FF8014
 
 /*
  * Internal Definitions
diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h
index 1627344..a399d22 100644
--- a/include/configs/GEN860T.h
+++ b/include/configs/GEN860T.h
@@ -64,7 +64,7 @@
 /*
  * Set allowable console baud rates
  */
-#define CFG_BAUDRATE_TABLE		{ 9600,		\
+#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600,		\
 					  19200,	\
 					  38400,	\
 					  57600,	\
@@ -74,7 +74,7 @@
 /*
  * Print console information
  */
-#undef	 CFG_CONSOLE_INFO_QUIET
+#undef	 CONFIG_SYS_CONSOLE_INFO_QUIET
 
 /*
  * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
@@ -101,12 +101,12 @@
  * for downloads
  */
 #undef	CONFIG_LOADS_ECHO
-#define	CFG_LOADS_BAUD_CHANGE
+#define	CONFIG_SYS_LOADS_BAUD_CHANGE
 
 /*
  * Set default load address for tftp network downloads
  */
-#define	CFG_TFTP_LOADADDR				0x01000000
+#define	CONFIG_SYS_TFTP_LOADADDR				0x01000000
 
 /*
  * Turn off the watchdog timer
@@ -127,7 +127,7 @@
  * Reset address. We pick an address such that when an instruction
  * is executed at that address, a machine check exception occurs
  */
-#define CFG_RESET_ADDRESS				((ulong) -1)
+#define CONFIG_SYS_RESET_ADDRESS				((ulong) -1)
 
 /*
  * BOOTP options
@@ -145,7 +145,7 @@
  * MII address is hardwired on the board to zero.
  */
 #define CONFIG_FEC_ENET
-#define CFG_DISCOVER_PHY
+#define CONFIG_SYS_DISCOVER_PHY
 #define CONFIG_MII
 #define CONFIG_MII_INIT			1
 #define CONFIG_PHY_ADDR			0
@@ -162,10 +162,10 @@
  * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
  * the MPC860T I2C interface.
  */
-#define CFG_I2C_EEPROM_ADDR				0x50
-#define CFG_EEPROM_PAGE_WRITE_BITS		6		/* 64 byte pages		*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	12		/* 10 mS w/ 20% margin	*/
-#define	CFG_I2C_EEPROM_ADDR_LEN			2		/* need 16 bit address	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR				0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS		6		/* 64 byte pages		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	12		/* 10 mS w/ 20% margin	*/
+#define	CONFIG_SYS_I2C_EEPROM_ADDR_LEN			2		/* need 16 bit address	*/
 #define CONFIG_ENV_EEPROM_SIZE				(32 * 1024)
 
 /*
@@ -175,8 +175,8 @@
 #undef	CONFIG_SOFT_I2C						/* Bit-banged I2C			*/
 
 #ifdef CONFIG_HARD_I2C
-#define	CFG_I2C_SPEED		100000			/* clock speed in Hz		*/
-#define CFG_I2C_SLAVE		0xFE			/* I2C slave address		*/
+#define	CONFIG_SYS_I2C_SPEED		100000			/* clock speed in Hz		*/
+#define CONFIG_SYS_I2C_SLAVE		0xFE			/* I2C slave address		*/
 #endif
 
 #ifdef CONFIG_SOFT_I2C
@@ -208,7 +208,7 @@
  * length of time, so we use an external RTC on the I2C bus instead.
  */
 #define CONFIG_RTC_DS1337
-#define CFG_I2C_RTC_ADDR				0x68
+#define CONFIG_SYS_I2C_RTC_ADDR				0x68
 
 #else
 /*
@@ -220,11 +220,11 @@
 /*
  * Power On Self Test support
  */
-#define CONFIG_POST			  ( CFG_POST_CACHE		| \
-								CFG_POST_MEMORY		| \
-								CFG_POST_CPU		| \
-								CFG_POST_UART		| \
-								CFG_POST_SPR )
+#define CONFIG_POST			  ( CONFIG_SYS_POST_CACHE		| \
+								CONFIG_SYS_POST_MEMORY		| \
+								CONFIG_SYS_POST_CPU		| \
+								CONFIG_SYS_POST_UART		| \
+								CONFIG_SYS_POST_SPR )
 
 
 /*
@@ -277,7 +277,7 @@
 #define CONFIG_FPGA
 #define CONFIG_FPGA_XILINX
 #define CONFIG_FPGA_VIRTEX2
-#define CFG_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
 
 
 #define CONFIG_NAND_LEGACY
@@ -285,64 +285,64 @@
 /*
  * Verbose help from command monitor.
  */
-#define	CFG_LONGHELP
+#define	CONFIG_SYS_LONGHELP
 #if !defined(CONFIG_SC)
-#define	CFG_PROMPT			"B2> "
+#define	CONFIG_SYS_PROMPT			"B2> "
 #else
-#define	CFG_PROMPT			"SC> "
+#define	CONFIG_SYS_PROMPT			"SC> "
 #endif
 
 
 /*
  * Use the "hush" command parser
  */
-#define	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 /*
  * Set buffer size for console I/O
  */
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE			1024
+#define	CONFIG_SYS_CBSIZE			1024
 #else
-#define	CFG_CBSIZE			256
+#define	CONFIG_SYS_CBSIZE			256
 #endif
 
 /*
  * Print buffer size
  */
-#define	CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 
 /*
  * Maximum number of arguments that a command can accept
  */
-#define	CFG_MAXARGS			16
+#define	CONFIG_SYS_MAXARGS			16
 
 /*
  * Boot argument buffer size
  */
-#define CFG_BARGSIZE		CFG_CBSIZE
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
 /*
  * Default memory test range
  */
-#define CFG_MEMTEST_START	0x0100000
-#define CFG_MEMTEST_END		(CFG_MEMTEST_START  + (128 * 1024))
+#define CONFIG_SYS_MEMTEST_START	0x0100000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START  + (128 * 1024))
 
 /*
  * Select the more full-featured memory test
  */
-#define	CFG_ALT_MEMTEST
+#define	CONFIG_SYS_ALT_MEMTEST
 
 /*
  * Default load address
  */
-#define	CFG_LOAD_ADDR		0x01000000
+#define	CONFIG_SYS_LOAD_ADDR		0x01000000
 
 /*
  * Set decrementer frequency (1 ms ticks)
  */
-#define	CFG_HZ				1000
+#define	CONFIG_SYS_HZ				1000
 
 /*
  * Device memory map (after SDRAM remap to 0x0):
@@ -363,7 +363,7 @@
 /*
  * Base addresses and block sizes
  */
-#define CFG_IMMR			0xFF000000
+#define CONFIG_SYS_IMMR			0xFF000000
 
 #define SDRAM_BASE			0x00000000
 #define SDRAM_SIZE			(64 * 1024 * 1024)
@@ -386,27 +386,27 @@
 /*
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR		CFG_IMMR
-#define	CFG_INIT_RAM_END		0x2F00	/* End of used area in DPRAM		*/
-#define	CFG_INIT_DATA_SIZE		64	/* # bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET		(CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET		CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR		CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END		0x2F00	/* End of used area in DPRAM		*/
+#define	CONFIG_SYS_INIT_DATA_SIZE		64	/* # bytes reserved for initial data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET		(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET		CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE			SDRAM_BASE
+#define	CONFIG_SYS_SDRAM_BASE			SDRAM_BASE
 
 /*
  * FLASH organization
  */
-#define CFG_FLASH_BASE			FLASH_BASE
-#define CFG_FLASH_SIZE			FLASH_SIZE
-#define CFG_FLASH_SECT_SIZE		(128 * 1024)
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		128
+#define CONFIG_SYS_FLASH_BASE			FLASH_BASE
+#define CONFIG_SYS_FLASH_SIZE			FLASH_SIZE
+#define CONFIG_SYS_FLASH_SECT_SIZE		(128 * 1024)
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		128
 
 /*
  * The timeout values are for an entire chip and are in milliseconds.
@@ -415,20 +415,20 @@
  * case VCC and temp after 100K programming cycles.  It works out
  * to 280 minutes (might as well be forever).
  */
-#define CFG_FLASH_ERASE_TOUT	(CFG_MAX_FLASH_SECT * 5000)
-#define CFG_FLASH_WRITE_TOUT	(CFG_MAX_FLASH_SECT * 128 * 1024 * 1)
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(CONFIG_SYS_MAX_FLASH_SECT * 5000)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(CONFIG_SYS_MAX_FLASH_SECT * 128 * 1024 * 1)
 
 /*
  * Allow direct writes to FLASH from tftp transfers (** dangerous **)
  */
-#define	CFG_DIRECT_FLASH_TFTP
+#define	CONFIG_SYS_DIRECT_FLASH_TFTP
 
 /*
  * Reserve memory for U-Boot.
  */
-#define CFG_MAX_UBOOT_SECTS		4
-#define	CFG_MONITOR_LEN			(CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE)
-#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+#define CONFIG_SYS_MAX_UBOOT_SECTS		4
+#define	CONFIG_SYS_MONITOR_LEN			(CONFIG_SYS_MAX_UBOOT_SECTS * CONFIG_SYS_FLASH_SECT_SIZE)
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 
 /*
  * Select environment placement.  NOTE that u-boot.lds must
@@ -442,7 +442,7 @@
 #define CONFIG_ENV_OFFSET			(CONFIG_ENV_EEPROM_SIZE - (8 * 1024))
 #else
 #define CONFIG_ENV_SIZE			0x1000
-#define CONFIG_ENV_SECT_SIZE		CFG_FLASH_SECT_SIZE
+#define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_FLASH_SECT_SIZE
 
 /*
  * This ultimately gets passed right into the linker script, so we have to
@@ -454,21 +454,21 @@
 /*
  * Reserve memory for malloc()
  */
-#define	CFG_MALLOC_LEN		(128 * 1024)
+#define	CONFIG_SYS_MALLOC_LEN		(128 * 1024)
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 * 1024 * 1024)
+#define	CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 
 /*
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE		16	/* For all MPC8xx CPUs				*/
+#define CONFIG_SYS_CACHELINE_SIZE		16	/* For all MPC8xx CPUs				*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT		4	/* log base 2 of above value		*/
+#define CONFIG_SYS_CACHELINE_SHIFT		4	/* log base 2 of above value		*/
 #endif
 
 /*------------------------------------------------------------------------
@@ -479,7 +479,7 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	( SYPCR_SWTC	| \
+#define CONFIG_SYS_SYPCR	( SYPCR_SWTC	| \
 					  SYPCR_BMT	| \
 					  SYPCR_BME	| \
 					  SYPCR_SWF	| \
@@ -488,7 +488,7 @@
 					  SYPCR_SWP		  \
 					)
 #else
-#define CFG_SYPCR	( SYPCR_SWTC	| \
+#define CONFIG_SYS_SYPCR	( SYPCR_SWTC	| \
 					  SYPCR_BMT	| \
 					  SYPCR_BME	| \
 					  SYPCR_SWF	| \
@@ -501,7 +501,7 @@
  *-----------------------------------------------------------------------
  * Set debug pin mux, enable SPKROUT and GPLB5*.
  */
-#define CFG_SIUMCR	( SIUMCR_DBGC11 | \
+#define CONFIG_SYS_SIUMCR	( SIUMCR_DBGC11 | \
 					  SIUMCR_DBPC11 | \
 					  SIUMCR_MLRC11	| \
 					  SIUMCR_GB5E	  \
@@ -512,7 +512,7 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freeze enabled
  */
-#define CFG_TBSCR	( TBSCR_REFA | \
+#define CONFIG_SYS_TBSCR	( TBSCR_REFA | \
 					  TBSCR_REFB | \
 					  TBSCR_TBF	   \
 					)
@@ -521,7 +521,7 @@
  * RTCSC - Real-Time Clock Status and Control Register			UM 11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	( RTCSC_SEC	| \
+#define CONFIG_SYS_RTCSC	( RTCSC_SEC	| \
 					  RTCSC_ALR | \
 					  RTCSC_RTF | \
 					  RTCSC_RTE	  \
@@ -532,7 +532,7 @@
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	( PISCR_PS		| \
+#define CONFIG_SYS_PISCR	( PISCR_PS		| \
 					  PISCR_PITF	  \
 					)
 
@@ -542,7 +542,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit. Set MF for 1:2:1 mode.
  */
-#define CFG_PLPRCR	( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK)	| \
+#define CONFIG_SYS_PLPRCR	( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK)	| \
 					  PLPRCR_SPLSS	| \
 					  PLPRCR_TEXPS	| \
 					  PLPRCR_TMIST	  \
@@ -557,7 +557,7 @@
 #define SCCR_MASK   SCCR_EBDF11
 
 #if !defined(CONFIG_SC)
-#define CFG_SCCR	( SCCR_TBS			|	/* timebase = GCLK/2	*/ \
+#define CONFIG_SYS_SCCR	( SCCR_TBS			|	/* timebase = GCLK/2	*/ \
 					  SCCR_COM00		|	/* full strength CLKOUT	*/ \
 					  SCCR_DFSYNC00	|	/* SYNCLK / 1 (normal)	*/ \
 					  SCCR_DFBRG00		|	/* BRGCLK / 1 (normal)	*/ \
@@ -565,7 +565,7 @@
 					  SCCR_DFNH000		  \
 					)
 #else
-#define CFG_SCCR	( SCCR_TBS			|	/* timebase = GCLK/2	*/ \
+#define CONFIG_SYS_SCCR	( SCCR_TBS			|	/* timebase = GCLK/2	*/ \
 					  SCCR_COM00		|	/* full strength CLKOUT	*/ \
 					  SCCR_DFSYNC00	|	/* SYNCLK / 1 (normal)	*/ \
 					  SCCR_DFBRG00		|	/* BRGCLK / 1 (normal)	*/ \
@@ -581,7 +581,7 @@
  *-----------------------------------------------------------------------
  * Mask all events that can cause entry into debug mode
  */
-#define CFG_DER				0
+#define CONFIG_SYS_DER				0
 
 /*
  * Initialize Memory Controller:
@@ -593,13 +593,13 @@
 /*
  * Flash address mask
  */
-#define CFG_PRELIM_OR_AM	0xfe000000
+#define CONFIG_SYS_PRELIM_OR_AM	0xfe000000
 
 /*
  * FLASH timing:
  * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
  */
-#define CFG_OR_TIMING_FLASH	( OR_CSNT_SAM	| \
+#define CONFIG_SYS_OR_TIMING_FLASH	( OR_CSNT_SAM	| \
 							  OR_ACS_DIV2	| \
 							  OR_BI			| \
 							  OR_SCY_2_CLK	| \
@@ -607,11 +607,11 @@
 							  OR_EHTR		  \
 							)
 
-#define CFG_OR0_PRELIM	( CFG_PRELIM_OR_AM		| \
-						  CFG_OR_TIMING_FLASH	  \
+#define CONFIG_SYS_OR0_PRELIM	( CONFIG_SYS_PRELIM_OR_AM		| \
+						  CONFIG_SYS_OR_TIMING_FLASH	  \
 						)
 
-#define CFG_BR0_PRELIM	( (FLASH_BASE0_PRELIM & BR_BA_MSK)	| \
+#define CONFIG_SYS_BR0_PRELIM	( (FLASH_BASE0_PRELIM & BR_BA_MSK)	| \
 						  BR_MS_GPCM						| \
 						  BR_PS_8							| \
 						  BR_V								  \
@@ -620,12 +620,12 @@
 /*
  * SDRAM configuration
  */
-#define CFG_OR1_AM	0xfc000000
-#define CFG_OR1		( (CFG_OR1_AM & OR_AM_MSK)	| \
+#define CONFIG_SYS_OR1_AM	0xfc000000
+#define CONFIG_SYS_OR1		( (CONFIG_SYS_OR1_AM & OR_AM_MSK)	| \
 					  OR_CSNT_SAM				  \
 					)
 
-#define CFG_BR1		( (SDRAM_BASE & BR_BA_MSK)	| \
+#define CONFIG_SYS_BR1		( (SDRAM_BASE & BR_BA_MSK)	| \
 					  BR_MS_UPMA				| \
 					  BR_PS_32					| \
 					  BR_V						  \
@@ -635,17 +635,17 @@
  * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
  * of 256 MBit SDRAM
  */
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16
 
 /*
  * Periodic timer for refresh @ 33 MHz system clock
  */
-#define CFG_MAMR_PTA	64
+#define CONFIG_SYS_MAMR_PTA	64
 
 /*
  * MAMR settings for SDRAM
  */
-#define CFG_MAMR_8COL	( (CFG_MAMR_PTA << MAMR_PTA_SHIFT)	| \
+#define CONFIG_SYS_MAMR_8COL	( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)	| \
 						  MAMR_PTAE				| \
 						  MAMR_AMA_TYPE_1			| \
 						  MAMR_DSA_1_CYCL			| \
@@ -660,7 +660,7 @@
  * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
  * no burst.
  */
-#define CFG_OR2_PRELIM	( (0xffff0000 & OR_AM_MSK)	| \
+#define CONFIG_SYS_OR2_PRELIM	( (0xffff0000 & OR_AM_MSK)	| \
 						  OR_CSNT_SAM				| \
 						  OR_ACS_DIV2				| \
 						  OR_BI						| \
@@ -669,7 +669,7 @@
 						  OR_EHTR					  \
 						)
 
-#define CFG_BR2_PRELIM	( (DOC_BASE & BR_BA_MSK)	| \
+#define CONFIG_SYS_BR2_PRELIM	( (DOC_BASE & BR_BA_MSK)	| \
 						  BR_PS_8					| \
 						  BR_MS_GPCM				| \
 						  BR_V						  \
@@ -683,12 +683,12 @@
  * the cycle will still complete even if there is a configuration
  * error that prevents TA from asserting on FPGA accesss.
  */
-#define CFG_OR3_PRELIM	( (0xfc000000 & OR_AM_MSK)  | \
+#define CONFIG_SYS_OR3_PRELIM	( (0xfc000000 & OR_AM_MSK)  | \
 						  OR_SCY_15_CLK				| \
 						  OR_BI					  \
 						)
 
-#define CFG_BR3_PRELIM	( (FPGA_BASE & BR_BA_MSK)	| \
+#define CONFIG_SYS_BR3_PRELIM	( (FPGA_BASE & BR_BA_MSK)	| \
 						  BR_PS_32					| \
 						  BR_MS_GPCM				| \
 						  BR_V						  \
@@ -698,12 +698,12 @@
  * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
  * of GCLK1_50
  */
-#define CFG_OR4_PRELIM	( (0xffff0000 & OR_AM_MSK)	| \
+#define CONFIG_SYS_OR4_PRELIM	( (0xffff0000 & OR_AM_MSK)	| \
 						  OR_G5LS						| \
 						  OR_BI							  \
 						)
 
-#define CFG_BR4_PRELIM	( (SELECTMAP_BASE & BR_BA_MSK)	| \
+#define CONFIG_SYS_BR4_PRELIM	( (SELECTMAP_BASE & BR_BA_MSK)	| \
 						  BR_PS_8						| \
 						  BR_MS_UPMB					| \
 						  BR_V							  \
@@ -717,7 +717,7 @@
  * the cycle will still complete even if there is a configuration
  * error that prevents TA from asserting on FPGA accesss.
  */
-#define CFG_OR5_PRELIM	( (0xffff0000 & OR_AM_MSK)  | \
+#define CONFIG_SYS_OR5_PRELIM	( (0xffff0000 & OR_AM_MSK)  | \
 						  OR_SCY_15_CLK				| \
 						  OR_EHTR					| \
 						  OR_TRLX					| \
@@ -725,7 +725,7 @@
 						  OR_BI						  \
 						)
 
-#define CFG_BR5_PRELIM	( (M1553_BASE & BR_BA_MSK)	| \
+#define CONFIG_SYS_BR5_PRELIM	( (M1553_BASE & BR_BA_MSK)	| \
 						  BR_PS_16					| \
 						  BR_MS_GPCM				| \
 						  BR_V						  \
@@ -741,10 +741,10 @@
  * Disk On Chip (millenium) configuration
  */
 #if !defined(CONFIG_SC)
-#define CFG_MAX_DOC_DEVICE	1
-#undef	CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
-#undef	CFG_DOC_PASSIVE_PROBE
+#define CONFIG_SYS_MAX_DOC_DEVICE	1
+#undef	CONFIG_SYS_DOC_SUPPORT_2000
+#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
+#undef	CONFIG_SYS_DOC_PASSIVE_PROBE
 #endif
 
 /*
diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h
index b6cc17b..fadd830 100644
--- a/include/configs/GENIETV.h
+++ b/include/configs/GENIETV.h
@@ -41,19 +41,19 @@
 #define	CONFIG_ETHADDR		08:00:22:50:70:63	/* Ethernet address */
 #define CONFIG_ENV_OVERWRITE	1	/* Overwrite the environment */
 
-#define CFG_ALLOC_DPRAM			/* Use dynamic DPRAM allocation */
+#define CONFIG_SYS_ALLOC_DPRAM			/* Use dynamic DPRAM allocation */
 
-#define CFG_AUTOLOAD		"n"	/* No autoload */
+#define CONFIG_SYS_AUTOLOAD		"n"	/* No autoload */
 
 /*#define CONFIG_VIDEO		1	/  To enable the video initialization */
 /*#define CONFIG_VIDEO_ADDR	0x00200000 */
 /*#define CONFIG_HARD_I2C	1	/  I2C with hardware support */
 /*#define CONFIG_PCMCIA		1	/  To enable the PCMCIA initialization */
 
-/*#define CFG_PCMCIA_IO_ADDR	0xff020000 */
-/*#define CFG_PCMCIA_IO_SIZE	0x10000 */
-/*#define CFG_PCMCIA_MEM_ADDR	0xe0000000 */
-/*#define CFG_PCMCIA_MEM_SIZE	0x10000 */
+/*#define CONFIG_SYS_PCMCIA_IO_ADDR	0xff020000 */
+/*#define CONFIG_SYS_PCMCIA_IO_SIZE	0x10000 */
+/*#define CONFIG_SYS_PCMCIA_MEM_ADDR	0xe0000000 */
+/*#define CONFIG_SYS_PCMCIA_MEM_SIZE	0x10000 */
 
 /* Video related */
 
@@ -84,7 +84,7 @@
 #define MPC8XX_XIN	5000000			/* 4 MHz clock		*/
 
 #define MPC8XX_HZ	((MPC8XX_XIN) * (MPC8XX_FACT))
-#define CFG_PLPRCR_MF	((MPC8XX_FACT-1) << 20)
+#define CONFIG_SYS_PLPRCR_MF	((MPC8XX_FACT-1) << 20)
 #define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ	/* Force it - dont measure it */
 
 #define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
@@ -124,25 +124,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		":>"		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		":>"		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		8		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		8		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00004000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00800000	/* 0 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00004000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00800000	/* 0 ... 8 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x00100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 4800, 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 4800, 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -152,49 +152,49 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFF000000
-#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+#define CONFIG_SYS_IMMR		0xFF000000
+#define CONFIG_SYS_IMMR_SIZE		((uint)(64 * 1024))
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x02800000
-#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x02800000
+#define CONFIG_SYS_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
 #if 0
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 128 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 128 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x10000	/* Offset of Environment Sector		*/
@@ -205,9 +205,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -217,10 +217,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -228,23 +228,23 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  *
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC10)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC10)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control					11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
@@ -252,9 +252,9 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer  *
  * interrupt status bit - leave PLL multiplication factor unchanged !
  *
- * #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+ * #define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CONFIG_SYS_PLPRCR_MF)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -263,7 +263,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR       (SCCR_TBS     | \
+#define CONFIG_SYS_SCCR       (SCCR_TBS     | \
 				SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 				SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 				SCCR_DFALCD00)
@@ -273,7 +273,7 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER		0
+#define CONFIG_SYS_DER		0
 
 /* Because of the way the 860 starts up and assigns CS0 the
 * entire address space, we have to set the memory controller
@@ -291,22 +291,22 @@
 
 #define FLASH_BASE0_PRELIM	0x02800000	/* FLASH bank #0		*/
 
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask		*/
-#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask (512Kb) */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask		*/
+#define CONFIG_SYS_PRELIM_OR_AM	0xFF800000	/* OR addr mask (512Kb) */
 
 /* FLASH timing */
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
 				OR_SCY_15_CLK | OR_TRLX )
 
-/*#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH) */
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)		/* 0xfff80ff4 */
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)	/* 0x02800401 */
+/*#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH) */
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)		/* 0xfff80ff4 */
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)	/* 0x02800401 */
 
 /*
  * BR1/2 and OR1/2 (SDRAM)
 */
 
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
 #define SDRAM_MAX_SIZE		0x04000000	/* 64Mb bank */
 #define SDRAM_BASE1_PRELIM	0x00000000	/* First bank */
@@ -317,17 +317,17 @@
  */
 
 /* periodic timer for refresh */
-#define CFG_MBMR_PTB		0x5d		/* start with divider for 100 MHz	*/
+#define CONFIG_SYS_MBMR_PTB		0x5d		/* start with divider for 100 MHz	*/
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K        MPTPR_PTP_DIV32
 /*
  * MBMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
+#define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
 			MAMR_G0CLA_A11 | MAMR_RLFA_1X | MAMR_WLFA_1X \
 			| MAMR_TLFA_4X)	/* 0x5d802114 */
 
diff --git a/include/configs/GTH.h b/include/configs/GTH.h
index 18bbbc3..c2cf852 100644
--- a/include/configs/GTH.h
+++ b/include/configs/GTH.h
@@ -88,11 +88,11 @@
 #if 1
 #define	CONFIG_SCC1_ENET	1	/* use SCC1 ethernet */
 #undef	CONFIG_FEC_ENET			/* disable FEC ethernet  */
-#define CFG_DISCOVER_PHY
+#define CONFIG_SYS_DISCOVER_PHY
 #else
 #undef	CONFIG_SCC1_ENET		/* disable SCC1 ethernet */
 #define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
-#define CFG_DISCOVER_PHY
+#define CONFIG_SYS_DISCOVER_PHY
 #endif
 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
@@ -122,25 +122,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_PROMPT		"=>"	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_PROMPT		"=>"	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
 
 /* Default location to load data from net */
-#define CFG_LOAD_ADDR		0x100000
+#define CONFIG_SYS_LOAD_ADDR		0x100000
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400 }
 
 /*
  * Low Level Configuration Settings
@@ -150,49 +150,49 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR			0xFF000000
-#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+#define CONFIG_SYS_IMMR			0xFF000000
+#define CONFIG_SYS_IMMR_SIZE		((uint)(64 * 1024))
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
 
-#define CFG_FLASH_BASE		0x80000000
+#define CONFIG_SYS_FLASH_BASE		0x80000000
 
-#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+#define CONFIG_SYS_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
 
-#define	CFG_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
 
-#define CFG_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
 
-#define	CFG_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
+#define	CONFIG_SYS_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH 1
 #undef CONFIG_ENV_IS_IN_EEPROM
@@ -204,9 +204,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -216,10 +216,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -227,14 +227,14 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control					11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
@@ -242,22 +242,22 @@
  */
 
 /*FIXME dont use for now */
-/*#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
-/*#define CFG_RTCSC	(RTCSC_RTF) */
+/*#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
+/*#define CONFIG_SYS_RTCSC	(RTCSC_RTF) */
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 /* PITE */
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
  *-----------------------------------------------------------------------
  * set the PLL, the low-power modes and the reset control (15-29)
  */
-#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
 				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
@@ -269,14 +269,14 @@
 
 /* FIXME check values */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS|SCCR_RTSEL|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
+#define CONFIG_SYS_SCCR	(SCCR_TBS|SCCR_RTSEL|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
 
  /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER		0
+#define CONFIG_SYS_DER		0
 
 /* Because of the way the 860 starts up and assigns CS0 the
 * entire address space, we have to set the memory controller
@@ -293,22 +293,22 @@
  */
 /* the other CS:s are determined by looking at parameters in BCSRx */
 
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	*/
 
-#define CFG_REMAP_OR_AM		0xFF800000	/* 4 MB OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0xFF800000	/* 4 MB OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
 
 #define FPGA_2_BASE 0x90000000
 #define FPGA_3_BASE 0x98000000
 
 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 
 
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16 )
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16 )
 
 /*
  * Internal Definitions
@@ -341,31 +341,31 @@
 #define CONFIG_PCMCIA_SLOT_A 1
 #endif
 
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 #define CONFIG_IDE_8xx_PCCARD       1       /* Use IDE with PC Card Adapter */
 #undef  CONFIG_IDE_8xx_DIRECT               /* Direct IDE    not supported  */
 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 
-#define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
-#define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
+#define CONFIG_SYS_IDE_MAXBUS          1       /* max. 1 IDE bus               */
+#define CONFIG_SYS_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 
-#define CFG_ATA_IDE0_OFFSET     0x0000
-#define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_IDE0_OFFSET     0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR       CONFIG_SYS_PCMCIA_MEM_ADDR
 /* Offset for data I/O                  */
-#define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET     (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 /* Offset for normal register accesses  */
-#define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET      (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 /* Offset for alternate registers       */
-#define CFG_ATA_ALT_OFFSET      0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET      0x0100
 
 #define CONFIG_8xx_GCLK_FREQ   MPC8XX_HZ       /* Force it - dont measure it */
 
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index 7ff03b1..ed9a235 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -62,8 +62,9 @@
 	"pciconfighost=1\0"						\
 	""
 
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_NET_MULTI	1
 #undef  CONFIG_HAS_ETH1
 
@@ -93,10 +94,10 @@
 #define CONFIG_CONSOLE_EXTRA_INFO
 #define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_SPLASH_SCREEN
-#define CFG_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_VIDEO_BMP_GZIP		/* gzip compressed bmp images	*/
-#define CFG_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* for decompressed img */
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* for decompressed img */
 
 #endif /* CONFIG_VIDEO */
 
@@ -149,76 +150,74 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+#define CONFIG_SYS_DEVICE_NULLDEV      1       /* include nulldev device       */
 
-#undef  CFG_CONSOLE_INFO_QUIET          /* print console @ startup	*/
+#undef  CONFIG_SYS_CONSOLE_INFO_QUIET          /* print console @ startup	*/
 
 #define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
-#define CFG_BASE_BAUD       691200
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD       691200
 #define CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CONFIG_SYS_BAUDRATE_TABLE      \
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */
+#define CONFIG_SYS_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */
 
 /*-----------------------------------------------------------------------
  * RTC stuff
  *-----------------------------------------------------------------------
  */
 #define CONFIG_RTC_DS1338
-#define CFG_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
 
 /*-----------------------------------------------------------------------
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
-#define NAND_MAX_CHIPS          1
-#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
 #define NAND_BIG_DELAY_US	25
 
-#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
-#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
-#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
-#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
+#define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
-#define CFG_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
-#define CFG_NAND_QUIET          1
+#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
+#define CONFIG_SYS_NAND_QUIET          1
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -237,15 +236,15 @@
 
 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
@@ -255,66 +254,66 @@
 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 #define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
 
-#define	CFG_IDE_MAXBUS	        1		/* max. 1 IDE busses	*/
-#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define	CONFIG_SYS_IDE_MAXBUS	        1		/* max. 1 IDE busses	*/
+#define	CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 
-#define	CFG_ATA_BASE_ADDR	0xF0100000
-#define	CFG_ATA_IDE0_OFFSET	0x0000
+#define	CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
+#define	CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define	CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
+#define CONFIG_SYS_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
+#define CONFIG_SYS_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+#define CONFIG_SYS_FLASH_READ0         0x0000  /* 0 is standard                        */
+#define CONFIG_SYS_FLASH_READ1         0x0001  /* 1 is standard                        */
+#define CONFIG_SYS_FLASH_READ2         0x0002  /* 2 is standard                        */
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 
 #if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
+#define CONFIG_SYS_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
+#define CONFIG_SYS_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
 #endif
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFF80000
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(4 << 20)	/* Reserve 4 MB for malloc()	*/
-
-#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CFG_RAMBOOT		1
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFF80000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* Reserve 4 MB for malloc()	*/
+
+#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CONFIG_SYS_RAMBOOT		1
 #else
-# undef CFG_RAMBOOT
+# undef CONFIG_SYS_RAMBOOT
 #endif
 
 /*-----------------------------------------------------------------------
@@ -325,42 +324,41 @@
 #define CONFIG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */
 
-#define CFG_NVRAM_BASE_ADDR	0xF4080000		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		0x8000		        /* NVRAM size		*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF4080000		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		0x8000		        /* NVRAM size		*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
 #if 0 /* test-only */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #else
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
 #endif
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
-#define CFG_EEPROM_WREN         1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
+#define CONFIG_SYS_EEPROM_WREN         1
 
 #if 1 /* test-only */
 /* CAT24WC08/16... */
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last	4 bits of the address	*/
 #else
 /* CAT24WC32/64... */
-#define CFG_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
-#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x01
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
 					/* 32 byte page write mode using*/
 					/* last	5 bits of the address	*/
 #endif
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
@@ -368,37 +366,37 @@
 
 #define CAN_BA          0xF0000000          /* CAN Base Address                 */
 #define LCD_BA          0xF1000000          /* Epson LCD Base Address           */
-#define CFG_NAND_BASE   0xF4000000          /* NAND FLASH Base Address          */
-#define CFG_NVRAM_BASE  0xF4080000          /* NVRAM Base Address               */
+#define CONFIG_SYS_NAND_BASE   0xF4000000          /* NAND FLASH Base Address          */
+#define CONFIG_SYS_NVRAM_BASE  0xF4080000          /* NVRAM Base Address               */
 
 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
-#define CFG_EBC_PB0AP           0x92015480
-#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP           0x92015480
+#define CONFIG_SYS_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization              */
-#define CFG_EBC_PB1AP           0x92015480
-#define CFG_EBC_PB1CR           0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
+#define CONFIG_SYS_EBC_PB1AP           0x92015480
+#define CONFIG_SYS_EBC_PB1CR           0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
 
 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
-#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+#define CONFIG_SYS_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 
 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization     */
-#define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 4 (Epson LCD) initialization                                     */
-#define CFG_EBC_PB4AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
-#define CFG_EBC_PB4CR   LCD_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB4AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
+#define CONFIG_SYS_EBC_PB4CR   LCD_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
 
 /*-----------------------------------------------------------------------
  * LCD Setup
  */
 
-#define CFG_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
-#define CFG_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
-#define CFG_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
-#define CFG_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */
+#define CONFIG_SYS_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
+#define CONFIG_SYS_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
+#define CONFIG_SYS_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
+#define CONFIG_SYS_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */
 
 /*-----------------------------------------------------------------------
  * Universal Interrupt Controller (UIC) Setup
@@ -407,30 +405,30 @@
 /*
  * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high
  */
-#define CFG_UIC0_POLARITY       (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6))
+#define CONFIG_SYS_UIC0_POLARITY       (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6))
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
 
-#define CFG_FPGA_BASE_ADDR 0xF0100100       /* FPGA internal Base Address       */
+#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100       /* FPGA internal Base Address       */
 
 /* FPGA internal regs */
-#define CFG_FPGA_CTRL           0x000
+#define CONFIG_SYS_FPGA_CTRL           0x000
 
 /* FPGA Control Reg */
-#define CFG_FPGA_CTRL_REV0      0x0001
-#define CFG_FPGA_CTRL_REV1      0x0002
-#define CFG_FPGA_CTRL_VGA0_BL   0x0004
-#define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008
-#define CFG_FPGA_CTRL_CF_RESET  0x0040
-#define CFG_FPGA_CTRL_PS2_PWR   0x0080
-#define CFG_FPGA_CTRL_CF_PWRN   0x0100      /* low active                    */
-#define CFG_FPGA_CTRL_CF_BUS_EN 0x0200
-#define CFG_FPGA_CTRL_LCD_CLK   0x7000      /* Mask for lcd clock            */
-#define CFG_FPGA_CTRL_OW_ENABLE 0x8000
-
-#define CFG_FPGA_STATUS_CF_DETECT 0x8000
+#define CONFIG_SYS_FPGA_CTRL_REV0      0x0001
+#define CONFIG_SYS_FPGA_CTRL_REV1      0x0002
+#define CONFIG_SYS_FPGA_CTRL_VGA0_BL   0x0004
+#define CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE 0x0008
+#define CONFIG_SYS_FPGA_CTRL_CF_RESET  0x0040
+#define CONFIG_SYS_FPGA_CTRL_PS2_PWR   0x0080
+#define CONFIG_SYS_FPGA_CTRL_CF_PWRN   0x0100      /* low active                    */
+#define CONFIG_SYS_FPGA_CTRL_CF_BUS_EN 0x0200
+#define CONFIG_SYS_FPGA_CTRL_LCD_CLK   0x7000      /* Mask for lcd clock            */
+#define CONFIG_SYS_FPGA_CTRL_OW_ENABLE 0x8000
+
+#define CONFIG_SYS_FPGA_STATUS_CF_DETECT 0x8000
 
 #define LCD_CLK_OFF             0x0000      /* Off                           */
 #define LCD_CLK_02083           0x1000      /* 2.083 MHz                     */
@@ -441,31 +439,31 @@
 #define LCD_CLK_12500           0x6000      /* 12.50 MHz                     */
 #define LCD_CLK_25000           0x7000      /* 25.00 MHz                     */
 
-#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S50E*/
+#define CONFIG_SYS_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S50E*/
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
+#define CONFIG_SYS_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
+#define CONFIG_SYS_TEMP_STACK_OCM        1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
 
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup (PPC405EP specific)
@@ -479,19 +477,19 @@
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  */
-#define CFG_GPIO0_OSRH		0x40000550
-#define CFG_GPIO0_OSRL		0x00000110
-#define CFG_GPIO0_ISR1H		0x00000000
-#define CFG_GPIO0_ISR1L		0x15555440
-#define CFG_GPIO0_TSRH		0x00000000
-#define CFG_GPIO0_TSRL		0x00000000
-#define CFG_GPIO0_TCR		0xF7FE0017
-
-#define CFG_LCD_ENDIAN		(0x80000000 >> 7)
-#define CFG_EEPROM_WP		(0x80000000 >> 8)   /* GPIO8 */
-#define CFG_TOUCH_RST		(0x80000000 >> 9)   /* GPIO9 */
-#define CFG_LCD0_RST		(0x80000000 >> 30)
-#define CFG_LCD1_RST		(0x80000000 >> 31)
+#define CONFIG_SYS_GPIO0_OSRH		0x40000550
+#define CONFIG_SYS_GPIO0_OSRL		0x00000110
+#define CONFIG_SYS_GPIO0_ISR1H		0x00000000
+#define CONFIG_SYS_GPIO0_ISR1L		0x15555440
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0xF7FE0017
+
+#define CONFIG_SYS_LCD_ENDIAN		(0x80000000 >> 7)
+#define CONFIG_SYS_EEPROM_WP		(0x80000000 >> 8)   /* GPIO8 */
+#define CONFIG_SYS_TOUCH_RST		(0x80000000 >> 9)   /* GPIO9 */
+#define CONFIG_SYS_LCD0_RST		(0x80000000 >> 30)
+#define CONFIG_SYS_LCD1_RST		(0x80000000 >> 31)
 
 /*
  * Internal Definitions
diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h
index c8c0409..f6777b9 100644
--- a/include/configs/HIDDEN_DRAGON.h
+++ b/include/configs/HIDDEN_DRAGON.h
@@ -77,14 +77,14 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		1		/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -95,7 +95,7 @@
 
 #define CONFIG_NET_MULTI			/* Multi ethernet cards support */
 
-#define CFG_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
+#define CONFIG_SYS_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
 
 #define PCI_ENET0_IOADDR	0x80000000
 #define PCI_ENET0_MEMADDR	0x80000000
@@ -114,53 +114,53 @@
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	0x02000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE	0x02000000
 
-#define CFG_RESET_ADDRESS	0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
 
 #if defined (USE_DINK32)
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	0x00090000
-#define CFG_RAMBOOT		1
-#define CFG_INIT_RAM_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_INIT_RAM_END	0x10000
-#define CFG_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_LEN		0x00030000
+#define CONFIG_SYS_MONITOR_BASE	0x00090000
+#define CONFIG_SYS_RAMBOOT		1
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_INIT_RAM_END	0x10000
+#define CONFIG_SYS_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #else
-#undef	CFG_RAMBOOT
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	TEXT_BASE
+#undef	CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_MONITOR_LEN		0x00030000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 
-#define CFG_GBL_DATA_SIZE	128
+#define CONFIG_SYS_GBL_DATA_SIZE	128
 
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_END      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 #endif
 
-#define CFG_FLASH_BASE		0xFFE00000
-#define CFG_FLASH_SIZE		(2 * 1024 * 1024)	/* Unity has onboard 1MByte flash */
+#define CONFIG_SYS_FLASH_BASE		0xFFE00000
+#define CONFIG_SYS_FLASH_SIZE		(2 * 1024 * 1024)	/* Unity has onboard 1MByte flash */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
 #define CONFIG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
 
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
 
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM		*/
 
-#define CFG_EUMB_ADDR		0xFC000000
+#define CONFIG_SYS_EUMB_ADDR		0xFC000000
 
-#define CFG_ISA_MEM		0xFD000000
-#define CFG_ISA_IO		0xFE000000
+#define CONFIG_SYS_ISA_MEM		0xFD000000
+#define CONFIG_SYS_ISA_IO		0xFE000000
 
-#define CFG_FLASH_RANGE_BASE	0xFFE00000	/* flash memory address range	*/
-#define CFG_FLASH_RANGE_SIZE	0x00200000
+#define CONFIG_SYS_FLASH_RANGE_BASE	0xFFE00000	/* flash memory address range	*/
+#define CONFIG_SYS_FLASH_RANGE_SIZE	0x00200000
 #define FLASH_BASE0_PRELIM	0xFFE00000	/* processor board flash	*/
 
 /*
@@ -172,8 +172,8 @@
  */
 #define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
 #undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 #ifdef CONFIG_SOFT_I2C
 #error "Soft I2C is not configured properly.  Please review!"
@@ -188,13 +188,13 @@
 #define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
 #endif /* CONFIG_SOFT_I2C */
 
-#define CFG_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1		/* Bytes of address		*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1		/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_FLASH_BANKS		{ FLASH_BASE0_PRELIM }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_FLASH_BANKS		{ FLASH_BASE0_PRELIM }
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
@@ -202,12 +202,12 @@
 
 
 #define CONFIG_WINBOND_83C553	1	/*has a winbond bridge			*/
-#define CFG_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
-#define CFG_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
-#define CFG_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/
+#define CONFIG_SYS_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
+#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
+#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/
 
-#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 
 /* TODO: Change this to VIA686A */
 
@@ -216,40 +216,40 @@
  */
 #define CONFIG_NS87308			/* Nat Semi super-io controller on ISA bus */
 
-#define CFG_NS87308_BADDR_10	1
+#define CONFIG_SYS_NS87308_BADDR_10	1
 
-#define CFG_NS87308_DEVS	( CFG_NS87308_UART1   | \
-				  CFG_NS87308_UART2   | \
-				  CFG_NS87308_POWRMAN | \
-				  CFG_NS87308_RTC_APC )
+#define CONFIG_SYS_NS87308_DEVS	( CONFIG_SYS_NS87308_UART1   | \
+				  CONFIG_SYS_NS87308_UART2   | \
+				  CONFIG_SYS_NS87308_POWRMAN | \
+				  CONFIG_SYS_NS87308_RTC_APC )
 
-#undef	CFG_NS87308_PS2MOD
+#undef	CONFIG_SYS_NS87308_PS2MOD
 
-#define CFG_NS87308_CS0_BASE	0x0076
-#define CFG_NS87308_CS0_CONF	0x30
-#define CFG_NS87308_CS1_BASE	0x0075
-#define CFG_NS87308_CS1_CONF	0x30
-#define CFG_NS87308_CS2_BASE	0x0074
-#define CFG_NS87308_CS2_CONF	0x30
+#define CONFIG_SYS_NS87308_CS0_BASE	0x0076
+#define CONFIG_SYS_NS87308_CS0_CONF	0x30
+#define CONFIG_SYS_NS87308_CS1_BASE	0x0075
+#define CONFIG_SYS_NS87308_CS1_CONF	0x30
+#define CONFIG_SYS_NS87308_CS2_BASE	0x0074
+#define CONFIG_SYS_NS87308_CS2_CONF	0x30
 
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
 
-#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_REG_SIZE	1
 
 #if (CONFIG_CONS_INDEX > 2)
-#define CFG_NS16550_CLK		CONFIG_DRAM_SPEED*1000000
+#define CONFIG_SYS_NS16550_CLK		CONFIG_DRAM_SPEED*1000000
 #else
-#define CFG_NS16550_CLK		1843200
+#define CONFIG_SYS_NS16550_CLK		1843200
 #endif
 
-#define CFG_NS16550_COM1	(CFG_ISA_IO + CFG_NS87308_UART1_BASE)
-#define CFG_NS16550_COM2	(CFG_ISA_IO + CFG_NS87308_UART2_BASE)
-#define CFG_NS16550_COM3	(CFG_EUMB_ADDR + 0x4500)
-#define CFG_NS16550_COM4	(CFG_EUMB_ADDR + 0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_EUMB_ADDR + 0x4500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_EUMB_ADDR + 0x4600)
 
 /*
  * Low Level Configuration Settings
@@ -259,27 +259,27 @@
 
 #define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
 
-#define CFG_ROMNAL		7	/*rom/flash next access time		*/
-#define CFG_ROMFAL		11	/*rom/flash access time			*/
+#define CONFIG_SYS_ROMNAL		7	/*rom/flash next access time		*/
+#define CONFIG_SYS_ROMFAL		11	/*rom/flash access time			*/
 
-#define CFG_REFINT	430	/* no of clock cycles between CBR refresh cycles */
+#define CONFIG_SYS_REFINT	430	/* no of clock cycles between CBR refresh cycles */
 
 /* the following are for SDRAM only*/
-#define CFG_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
-#define CFG_REFREC		8	/* Refresh to activate interval		*/
-#define CFG_RDLAT		4	/* data latency from read command	*/
-#define CFG_PRETOACT		3	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
-#define CFG_ACTORW		3	/* Activate to R/W			*/
-#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
-#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#define CONFIG_SYS_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
+#define CONFIG_SYS_REFREC		8	/* Refresh to activate interval		*/
+#define CONFIG_SYS_RDLAT		4	/* data latency from read command	*/
+#define CONFIG_SYS_PRETOACT		3	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
 #if 0
-#define CFG_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
+#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
 #endif
 
-#define CFG_REGISTERD_TYPE_BUFFER   1
-#define CFG_EXTROM 1
-#define CFG_REGDIMM 0
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
+#define CONFIG_SYS_EXTROM 1
+#define CONFIG_SYS_REGDIMM 0
 
 
 /* memory bank settings*/
@@ -289,93 +289,93 @@
  * bits will be set to 0x00000 for a start address, or 0xfffff for an
  * end address
  */
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x3ff00000
-#define CFG_BANK1_END		0x3fffffff
-#define CFG_BANK1_ENABLE	0
-#define CFG_BANK2_START		0x3ff00000
-#define CFG_BANK2_END		0x3fffffff
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x3ff00000
-#define CFG_BANK3_END		0x3fffffff
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x00000000
-#define CFG_BANK4_END		0x00000000
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x00000000
-#define CFG_BANK5_END		0x00000000
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x00000000
-#define CFG_BANK6_END		0x00000000
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x00000000
-#define CFG_BANK7_END		0x00000000
-#define CFG_BANK7_ENABLE	0
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x3ff00000
+#define CONFIG_SYS_BANK1_END		0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE	0
+#define CONFIG_SYS_BANK2_START		0x3ff00000
+#define CONFIG_SYS_BANK2_END		0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x3ff00000
+#define CONFIG_SYS_BANK3_END		0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x00000000
+#define CONFIG_SYS_BANK4_END		0x00000000
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x00000000
+#define CONFIG_SYS_BANK5_END		0x00000000
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x00000000
+#define CONFIG_SYS_BANK6_END		0x00000000
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x00000000
+#define CONFIG_SYS_BANK7_END		0x00000000
+#define CONFIG_SYS_BANK7_ENABLE	0
 /*
  * Memory bank enable bitmask, specifying which of the banks defined above
  are actually present. MSB is for bank #7, LSB is for bank #0.
  */
-#define CFG_BANK_ENABLE		0x01
+#define CONFIG_SYS_BANK_ENABLE		0x01
 
-#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
+#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
 					/* see 8240 book for bit definitions	*/
-#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
 					/* currently accessed page in memory	*/
 					/* see 8240 book for details		*/
 
 /* SDRAM 0 - 256MB */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* stack in DCACHE @ 1GB (no backing mem) */
 #if defined(USE_DINK32)
-#define CFG_IBAT1L	(0x40000000 | BATL_PP_00 )
-#define CFG_IBAT1U	(0x40000000 | BATU_BL_128K )
+#define CONFIG_SYS_IBAT1L	(0x40000000 | BATL_PP_00 )
+#define CONFIG_SYS_IBAT1U	(0x40000000 | BATU_BL_128K )
 #else
-#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 #endif
 
 /* PCI memory */
-#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* Flash, config addrs, etc */
-#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	36	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	36	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*
diff --git a/include/configs/HMI10.h b/include/configs/HMI10.h
index c58cb8c..6c8e81f 100644
--- a/include/configs/HMI10.h
+++ b/include/configs/HMI10.h
@@ -52,7 +52,7 @@
 #define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
 #define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
 #define CONFIG_PS2SERIAL	2	/* .. on COM3			*/
-#define CONFIG_PS2MULT_DELAY	(CFG_HZ/2)	/* Initial delay	*/
+#define CONFIG_PS2MULT_DELAY	(CONFIG_SYS_HZ/2)	/* Initial delay	*/
 
 #define CONFIG_BOOTCOUNT_LIMIT
 
@@ -88,14 +88,14 @@
 #define CONFIG_MISC_INIT_R	  1
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 /* enable I2C and select the hardware/software driver */
 #undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
 
-#define CFG_I2C_SPEED		40000	/* 40 kHz is supposed to work	*/
-#define CFG_I2C_SLAVE		0xFE
+#define CONFIG_SYS_I2C_SPEED		40000	/* 40 kHz is supposed to work	*/
+#define CONFIG_SYS_I2C_SLAVE		0xFE
 
 /* Software (bit-bang) I2C driver configuration */
 #define PB_SCL		0x00000020	/* PB 26 */
@@ -131,7 +131,7 @@
 #define CONFIG_DOS_PARTITION
 
 #define CONFIG_RTC_DS1337		/* Use ds1337 rtc via i2c	*/
-#define CFG_I2C_RTC_ADDR 0x68		/* at address 0x68		*/
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68		/* at address 0x68		*/
 
 
 /*
@@ -156,33 +156,33 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #if 0
-#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
 #endif
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -192,47 +192,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
@@ -245,16 +245,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -264,10 +264,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -276,9 +276,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -286,20 +286,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -309,7 +309,7 @@
  *
  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -318,7 +318,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 
@@ -327,14 +327,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0100000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4100000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8100000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC100000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0100000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4100000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8100000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC100000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 #define PCMCIA_MEM_WIN_NO	5
 #define NSCU_OE_INV		1		/* PCMCIA_GCRX_CXOE is inverted */
 
@@ -351,28 +351,28 @@
 #define CONFIG_IDE_LED		1	/* LED   for ide supported	*/
 #endif
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER 0
+#define CONFIG_SYS_DER 0
 
 /*
  * Init Memory Controller:
@@ -387,22 +387,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -413,19 +413,19 @@
 #define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 #ifndef CONFIG_CAN_DRIVER
-#define CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 #endif	/* CONFIG_CAN_DRIVER */
 
@@ -456,34 +456,34 @@
  * 80 Mhz => 80.000.000 / Divider = 156
  */
 
-#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
-#define CFG_MAMR_PTA	98
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
index 0727606..0e7d2c0 100644
--- a/include/configs/HUB405.h
+++ b/include/configs/HUB405.h
@@ -52,8 +52,9 @@
 
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
@@ -92,50 +93,49 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
 #undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /* Ethernet stuff */
 #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
@@ -147,18 +147,17 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
-#define NAND_MAX_CHIPS          1
-#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
 #define NAND_BIG_DELAY_US	25
 
-#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
-#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
-#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
-#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
+#define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
-#define CFG_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
-#define CFG_NAND_QUIET          1
+#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
+#define CONFIG_SYS_NAND_QUIET          1
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -175,58 +174,58 @@
 
 #undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -237,25 +236,24 @@
 #define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */
 
-#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 /*
  * Init Memory Controller:
@@ -270,57 +268,57 @@
  */
 
 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x92015480
-/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+/*#define CONFIG_SYS_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 2 (8 Bit Peripheral: UART) initialization			*/
 #if 0
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 #else
-#define CFG_EBC_PB2AP		0x92015480
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2AP		0x92015480
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 #endif
 
 #define DUART0_BA	0xF0000000	    /* DUART Base Address		*/
 #define DUART1_BA	0xF0000008	    /* DUART Base Address		*/
 #define DUART2_BA	0xF0000010	    /* DUART Base Address		*/
 #define DUART3_BA	0xF0000018	    /* DUART Base Address		*/
-#define CFG_NAND_BASE	0xF4000000
+#define CONFIG_SYS_NAND_BASE	0xF4000000
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
 
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup (PPC405EP specific)
@@ -334,19 +332,19 @@
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  */
-#define CFG_GPIO0_OSRH		0x40000550
-#define CFG_GPIO0_OSRL		0x00000110
-#define CFG_GPIO0_ISR1H		0x00000000
-#define CFG_GPIO0_ISR1L		0x15555445
-#define CFG_GPIO0_TSRH		0x00000000
-#define CFG_GPIO0_TSRL		0x00000000
-#define CFG_GPIO0_TCR		0xF7FE0014
-
-#define CFG_DUART_RST           (0x80000000 >> 14)
-#define CFG_UART2_RS232         (0x80000000 >> 5)
-#define CFG_UART3_RS232         (0x80000000 >> 6)
-#define CFG_UART4_RS232         (0x80000000 >> 7)
-#define CFG_UART5_RS232         (0x80000000 >> 8)
+#define CONFIG_SYS_GPIO0_OSRH		0x40000550
+#define CONFIG_SYS_GPIO0_OSRL		0x00000110
+#define CONFIG_SYS_GPIO0_ISR1H		0x00000000
+#define CONFIG_SYS_GPIO0_ISR1L		0x15555445
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0xF7FE0014
+
+#define CONFIG_SYS_DUART_RST           (0x80000000 >> 14)
+#define CONFIG_SYS_UART2_RS232         (0x80000000 >> 5)
+#define CONFIG_SYS_UART3_RS232         (0x80000000 >> 6)
+#define CONFIG_SYS_UART4_RS232         (0x80000000 >> 7)
+#define CONFIG_SYS_UART5_RS232         (0x80000000 >> 8)
 
 /*
  * Internal Definitions
diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h
index a4944f1..ca488c6 100644
--- a/include/configs/IAD210.h
+++ b/include/configs/IAD210.h
@@ -97,12 +97,12 @@
 # undef  CONFIG_SCC1_ENET		/* disable SCC1 ethernet */
 # define CONFIG_FEC_ENET    1	/* use FEC ethernet  */
 # define CONFIG_MII         1
-# define CFG_DISCOVER_PHY   1
+# define CONFIG_SYS_DISCOVER_PHY   1
 # define CONFIG_FEC_UTOPIA  1
 # define CONFIG_ETHADDR     08:00:06:26:A2:6D
 # define CONFIG_IPADDR      192.168.28.128
 # define CONFIG_SERVERIP    139.10.137.138
-# define CFG_DISCOVER_PHY   1
+# define CONFIG_SYS_DISCOVER_PHY   1
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -110,9 +110,9 @@
 /* enable I2C and select the hardware/software driver */
 #undef  CONFIG_HARD_I2C			/* I2C with hardware support    */
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged               */
-# define CFG_I2C_SPEED		50000
-# define CFG_I2C_SLAVE		0xDD
-# define CFG_I2C_EEPROM_ADDR	0x50
+# define CONFIG_SYS_I2C_SPEED		50000
+# define CONFIG_SYS_I2C_SLAVE		0xDD
+# define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
 /*
  * Software (bit-bang) I2C driver configuration
  */
@@ -145,25 +145,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x00100000
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -173,52 +173,52 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
-#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+#define CONFIG_SYS_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR_SIZE		((uint)(64 * 1024))
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x08000000
-#define CFG_FLASH_SIZE		((uint)(4 * 1024 * 1024))	/* max 16Mbyte */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x08000000
+#define CONFIG_SYS_FLASH_SIZE		((uint)(4 * 1024 * 1024))	/* max 16Mbyte */
 
-#define CFG_RESET_ADDRESS	0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
 
 #if defined(DEBUG)
-# define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+# define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-# define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+# define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
 
-# define CFG_MONITOR_BASE	CFG_FLASH_BASE
-# define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+# define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+# define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x8000
@@ -227,9 +227,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -239,10 +239,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -250,28 +250,28 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control					11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
  *-----------------------------------------------------------------------
  * set the PLL, the low-power modes and the reset control (15-29)
  */
-#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
 				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
@@ -282,7 +282,7 @@
  */
 #define SCCR_MASK	SCCR_EBDF11
 
-#define CFG_SCCR	(SCCR_TBS	| SCCR_COM00	| SCCR_DFSYNC00	| \
+#define CONFIG_SYS_SCCR	(SCCR_TBS	| SCCR_COM00	| SCCR_DFSYNC00	| \
 			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
 			 SCCR_DFLCD000	|SCCR_DFALCD00	)
 
@@ -291,7 +291,7 @@
  *-----------------------------------------------------------------------
  */
 /* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
-#define CFG_RCCR 0x0020
+#define CONFIG_SYS_RCCR 0x0020
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
@@ -305,7 +305,7 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER		0
+#define CONFIG_SYS_DER		0
 
 /* Because of the way the 860 starts up and assigns CS0 the
 * entire address space, we have to set the memory controller
@@ -321,22 +321,22 @@
  * BR0 and OR0 (FLASH)
  */
 
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	*/
 
 /* used to re-map FLASH both when starting from SRAM or FLASH:
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0xF8000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xF8000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0xF8000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xF8000000	/* OR addr mask */
 
 /* FLASH timing:
  TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | \
 				 OR_SCY_3_CLK | OR_EHTR)
 
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -347,25 +347,25 @@
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | OR_CSNT_SAM  | OR_BI | OR_ACS_DIV4)
-#define CFG_BR2_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | OR_CSNT_SAM  | OR_BI | OR_ACS_DIV4)
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 
 /*
  * Memory Periodic Timer Prescaler
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	124		/* start with divider for 64 MHz	*/
+#define CONFIG_SYS_MAMR_PTA	124		/* start with divider for 64 MHz	*/
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR	        MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR	        MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
-#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_8X)
 
diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h
index 0ff7fa9..917135e 100644
--- a/include/configs/ICU862.h
+++ b/include/configs/ICU862.h
@@ -95,9 +95,9 @@
 #define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
 #define	CONFIG_MII		1
 #if 1
-#define CFG_DISCOVER_PHY	1
+#define CONFIG_SYS_DISCOVER_PHY	1
 #else
-#undef	CFG_DISCOVER_PHY
+#undef	CONFIG_SYS_DISCOVER_PHY
 #endif
 
 #define CONFIG_MAC_PARTITION
@@ -106,10 +106,10 @@
 /* enable I2C and select the hardware/software driver */
 #undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-# define CFG_I2C_SPEED		50000
-# define CFG_I2C_SLAVE		0xFE
-# define CFG_I2C_EEPROM_ADDR	0x50
-# define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+# define CONFIG_SYS_I2C_SPEED		50000
+# define CONFIG_SYS_I2C_SLAVE		0xFE
+# define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /*
  * Software (bit-bang) I2C driver configuration
  */
@@ -126,8 +126,8 @@
 			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
 
-#define CFG_EEPROM_X40430		/* Use a Xicor X40430 EEPROM	*/
-#define CFG_EEPROM_PAGE_WRITE_BITS  4	/* 16 bytes page write mode	*/
+#define CONFIG_SYS_EEPROM_X40430		/* Use a Xicor X40430 EEPROM	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS  4	/* 16 bytes page write mode	*/
 
 #define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
@@ -150,25 +150,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x00100000
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -178,55 +178,55 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xF0000000
-#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+#define CONFIG_SYS_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR_SIZE		((uint)(64 * 1024))
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define CFG_FLASH_SIZE		((uint)(16 * 1024 * 1024))	/* max 16Mbyte */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define CONFIG_SYS_FLASH_SIZE		((uint)(16 * 1024 * 1024))	/* max 16Mbyte */
 
-#define CFG_RESET_ADDRESS	0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
 
 #if 0
 #if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
 #else
-#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
 #endif
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
 
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
@@ -234,14 +234,14 @@
 
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* Total Size of Environment sector	*/
 #define	CONFIG_ENV_SIZE		0x4000	/* Used Size of Environment Sector	*/
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -251,10 +251,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -262,28 +262,28 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control					11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
  *-----------------------------------------------------------------------
  * set the PLL, the low-power modes and the reset control (15-29)
  */
-#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
 				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
@@ -294,12 +294,12 @@
  */
 #ifdef CONFIG_100MHz	/* for 100 MHz, external bus is half CPU clock */
 #define SCCR_MASK	0
-#define CFG_SCCR	(SCCR_TBS	| SCCR_COM00	| SCCR_DFSYNC00	| \
+#define CONFIG_SYS_SCCR	(SCCR_TBS	| SCCR_COM00	| SCCR_DFSYNC00	| \
 			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
 			 SCCR_DFLCD000	|SCCR_DFALCD00	| SCCR_EBDF01)
 #else			/* up to 50 MHz we use a 1:1 clock */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS	| SCCR_COM00	| SCCR_DFSYNC00	| \
+#define CONFIG_SYS_SCCR	(SCCR_TBS	| SCCR_COM00	| SCCR_DFSYNC00	| \
 			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
 			 SCCR_DFLCD000	|SCCR_DFALCD00	)
 #endif	/* CONFIG_100MHz */
@@ -309,20 +309,20 @@
  *-----------------------------------------------------------------------
  */
 /* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
-#define CFG_RCCR 0x0020
+#define CONFIG_SYS_RCCR 0x0020
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * PCMCIA Power Switch
@@ -356,21 +356,21 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 
  /*-----------------------------------------------------------------------
@@ -378,7 +378,7 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER		0
+#define CONFIG_SYS_DER		0
 
 /* Because of the way the 860 starts up and assigns CS0 the
 * entire address space, we have to set the memory controller
@@ -397,16 +397,16 @@
 #define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
 #define FLASH_BASE1_PRELIM	0x0		/* FLASH bank #1	*/
 
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 
-#define CFG_OR0_PRELIM	0xFF000954		/* Real values for the board */
-#define CFG_BR0_PRELIM	0x40000001		/* Real values for the board */
+#define CONFIG_SYS_OR0_PRELIM	0xFF000954		/* Real values for the board */
+#define CONFIG_SYS_BR0_PRELIM	0x40000001		/* Real values for the board */
 
 /*
  * BR1 and OR1 (SDRAM)
@@ -414,40 +414,40 @@
 #define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank		*/
 #define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
-#define CFG_OR_TIMING_SDRAM	0x00000800	/* BIH is not set	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000800	/* BIH is not set	*/
 
-#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
-#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+#define CONFIG_SYS_OR1_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM)
+#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 
 /*
  * Memory Periodic Timer Prescaler
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA		97	/* start with divider for 100 MHz	*/
+#define CONFIG_SYS_MAMR_PTA		97	/* start with divider for 100 MHz	*/
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
-#define CFG_MAMR		0x13a01114
+#define CONFIG_SYS_MAMR		0x13a01114
 /*
  * Internal Definitions
  *
diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
index 4d0397c..fbcbddb 100644
--- a/include/configs/IDS8247.h
+++ b/include/configs/IDS8247.h
@@ -73,8 +73,8 @@
 /* enable I2C and select the hardware/software driver */
 #undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * Software (bit-bang) I2C driver configuration
@@ -91,10 +91,10 @@
 #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
 
 #if 0
-#define CFG_I2C_EEPROM_ADDR	0x50
-#define CFG_I2C_EEPROM_ADDR_LEN 2
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
 #define CONFIG_I2C_X
 #endif
@@ -108,17 +108,17 @@
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
 
-#define CFG_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_REG_SIZE    1
 
-#define CFG_NS16550_CLK         14745600
+#define CONFIG_SYS_NS16550_CLK         14745600
 
-#define	CFG_UART_BASE	0xE0000000
-#define CFG_UART_SIZE	0x10000
+#define	CONFIG_SYS_UART_BASE	0xE0000000
+#define CONFIG_SYS_UART_SIZE	0x10000
 
-#define CFG_NS16550_COM1        (CFG_UART_BASE + 0x8000)
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_UART_BASE + 0x8000)
 
 
 /* pass open firmware flat tree */
@@ -154,17 +154,17 @@
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 
 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 #define CONFIG_8260_CLKIN	66666666	/* in Hz */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -180,7 +180,7 @@
 #define CONFIG_BOOTP_BOOTFILESIZE
 
 #define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR		0x51
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
 
 /*
  * Command line configuration.
@@ -197,62 +197,62 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define	CFG_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
+#define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 
-#define CFG_FLASH_CFI				/* The flash is CFI compatible  */
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible  */
 #define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
-#define CFG_FLASH_BANKS_LIST	{ 0xFF800000 }
-#define CFG_MAX_FLASH_BANKS_DETECT	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ 0xFF800000 }
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
 /* What should the base address of the main FLASH be and how big is
  * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk
  * The main FLASH is whichever is connected to *CS0.
  */
-#define CFG_FLASH0_BASE 0xFFF00000
-#define CFG_FLASH0_SIZE 8
+#define CONFIG_SYS_FLASH0_BASE 0xFFF00000
+#define CONFIG_SYS_FLASH0_SIZE 8
 
 /* Flash bank size (for preliminary settings)
  */
-#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
+#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
 
 /* Environment in flash */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE+0x60000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x60000)
 #define CONFIG_ENV_SIZE		0x20000
 #define CONFIG_ENV_SECT_SIZE	0x20000
 
@@ -263,9 +263,9 @@
 #if defined(CONFIG_CMD_NAND)
 
 #define CONFIG_NAND_LEGACY
-#define CFG_NAND0_BASE 0xE1000000
+#define CONFIG_SYS_NAND0_BASE 0xE1000000
 
-#define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
 #define SECTORSIZE 512
 #define NAND_NO_RB
 
@@ -275,7 +275,6 @@
 
 #define NAND_ChipID_UNKNOWN     0x00
 #define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
 
 #define NAND_DISABLE_CE(nand) do \
 { \
@@ -326,47 +325,47 @@
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  *
- * if you change bits in the HRCW, you must also change the CFG_*
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
  * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
  */
-#define CFG_HRCW_MASTER	(HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
+#define CONFIG_SYS_HRCW_MASTER	(HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
 
 /* no slaves so just fill with zeros */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR		0xF0000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2000  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2000  /* End of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  *
- * 60x SDRAM is mapped at CFG_SDRAM_BASE
+ * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		CFG_FLASH0_BASE
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
 
 /*
  * Internal Definitions
@@ -380,9 +379,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 #if defined(CONFIG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -396,28 +395,28 @@
  * HID1 has only read-only information - nothing to set.
  */
 
-#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
-#define CFG_HID0_FINAL  0
-#define CFG_HID2        0
+#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
+#define CONFIG_SYS_HID0_FINAL  0
+#define CONFIG_SYS_HID2        0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register                                     5-5
  *-----------------------------------------------------------------------
  * turn on Checkstop Reset Enable
  */
-#define CFG_RMR         0
+#define CONFIG_SYS_RMR         0
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration                                       4-25
  *-----------------------------------------------------------------------
  */
-#define CFG_BCR		0
+#define CONFIG_SYS_BCR		0
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration                             4-31
  *-----------------------------------------------------------------------
  */
-#define CFG_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
+#define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
 
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control                             4-35
@@ -426,10 +425,10 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
@@ -439,7 +438,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control                 4-42
@@ -447,20 +446,20 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control                                   9-8
  *-----------------------------------------------------------------------
  * Ensure DFBRG is Divide by 16
  */
-#define CFG_SCCR        (0x00000028 | SCCR_DFBRG01)
+#define CONFIG_SYS_SCCR        (0x00000028 | SCCR_DFBRG01)
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration                         13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR        0
+#define CONFIG_SYS_RCCR        0
 
 /*
  * Init Memory Controller:
@@ -479,60 +478,60 @@
 /* Minimum mask to separate preliminary
  * address ranges for CS[0:2]
  */
-#define CFG_GLOBAL_SDRAM_LIMIT	(32<<20)	/* less than 32 MB */
+#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(32<<20)	/* less than 32 MB */
 
-#define CFG_MPTPR       0x6600
+#define CONFIG_SYS_MPTPR       0x6600
 
 /*-----------------------------------------------------------------------------
  * Address for Mode Register Set (MRS) command
  *-----------------------------------------------------------------------------
  */
-#define CFG_MRS_OFFS	0x00000110
+#define CONFIG_SYS_MRS_OFFS	0x00000110
 
 
 /* Bank 0 - FLASH
  */
-#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_8                       |\
 			 BRx_MS_GPCM_P                  |\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 			 ORxG_SCY_6_CLK                 )
 
 #if defined(CONFIG_CMD_NAND)
 /* Bank 1 - NAND Flash
 */
-#define	CFG_NAND_BASE		CFG_NAND0_BASE
-#define	CFG_NAND_SIZE		0x8000
+#define	CONFIG_SYS_NAND_BASE		CONFIG_SYS_NAND0_BASE
+#define	CONFIG_SYS_NAND_SIZE		0x8000
 
-#define CFG_OR_TIMING_NAND	0x000036
+#define CONFIG_SYS_OR_TIMING_NAND	0x000036
 
-#define CFG_BR1_PRELIM  ((CFG_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
-#define CFG_OR1_PRELIM  (P2SZ_TO_AM(CFG_NAND_SIZE) | CFG_OR_TIMING_NAND )
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
+#define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND )
 #endif
 
 /* Bank 2 - 60x bus SDRAM
  */
-#define CFG_PSRT        0x20
-#define CFG_LSRT        0x20
+#define CONFIG_SYS_PSRT        0x20
+#define CONFIG_SYS_LSRT        0x20
 
-#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_32                      |\
 			 BRx_MS_SDRAM_P                 |\
 			 BRx_V)
 
-#define CFG_OR2_PRELIM	CFG_OR2
+#define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_OR2
 
 
 /* SDRAM initialization values
 */
-#define CFG_OR2    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+#define CONFIG_SYS_OR2    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI0_A9		|\
 			 ORxS_NUMR_12)
 
-#define CFG_PSDMR  (PSDMR_SDAM_A14_IS_A5 |\
+#define CONFIG_SYS_PSDMR  (PSDMR_SDAM_A14_IS_A5 |\
 			 PSDMR_BSMA_A15_A17           |\
 			 PSDMR_SDA10_PBI0_A10		|\
 			 PSDMR_RFRC_5_CLK               |\
@@ -546,7 +545,7 @@
 /* Bank 3 - UART
 */
 
-#define CFG_BR3_PRELIM  ((CFG_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
-#define CFG_OR3_PRELIM  (((-CFG_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
+#define CONFIG_SYS_BR3_PRELIM  ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
+#define CONFIG_SYS_OR3_PRELIM  (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/IP860.h b/include/configs/IP860.h
index c0bf367..b9c5713 100644
--- a/include/configs/IP860.h
+++ b/include/configs/IP860.h
@@ -52,7 +52,7 @@
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -77,14 +77,14 @@
 #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
 
 
-# define CFG_I2C_SPEED		50000
-# define CFG_I2C_SLAVE		0xFE
-# define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM X24C16		*/
-# define CFG_I2C_EEPROM_ADDR_LEN 1	/* bytes of address		*/
+# define CONFIG_SYS_I2C_SPEED		50000
+# define CONFIG_SYS_I2C_SLAVE		0xFE
+# define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM X24C16		*/
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec */
 
 #define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
 
@@ -111,27 +111,27 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address	*/
 
-#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+#define	CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -141,50 +141,50 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xF1000000	/* Non-standard value!!	*/
+#define CONFIG_SYS_IMMR		0xF1000000	/* Non-standard value!!	*/
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x10000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x10000000
 #ifdef	DEBUG
-#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
 #else
 #if 0 /* need more space for I2C tests */
-#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(256 << 10)
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)
 #endif
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	124	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	124	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #undef	CONFIG_ENV_IS_IN_FLASH
 #undef	CONFIG_ENV_IS_IN_NVRAM
@@ -205,9 +205,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -218,10 +218,10 @@
  * +0x0004
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -229,7 +229,7 @@
  *-----------------------------------------------------------------------
  * +0x0000 => 0x80600800
  */
-#define CFG_SIUMCR	(SIUMCR_EARB   | SIUMCR_EARP0 | \
+#define CONFIG_SYS_SIUMCR	(SIUMCR_EARB   | SIUMCR_EARP0 | \
 			 SIUMCR_DBGC11 | SIUMCR_MLRC10)
 
 /*-----------------------------------------------------------------------
@@ -247,7 +247,7 @@ extern  unsigned long           ip860_get_clk_freq (void);
  * Clear Reference Interrupt Status, Timebase freezing enabled
  * +0x0200 => 0x00C2
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
@@ -255,7 +255,7 @@ extern  unsigned long           ip860_get_clk_freq (void);
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  * +0x0240 => 0x0082
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -264,7 +264,7 @@ extern  unsigned long           ip860_get_clk_freq (void);
  * interrupt status bit, set PLL multiplication factor !
  */
 /* +0x0286 => was: 0x0000D000 */
-#define CFG_PLPRCR							\
+#define CONFIG_SYS_PLPRCR							\
 		(	PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
 			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
 			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
@@ -277,7 +277,7 @@ extern  unsigned long           ip860_get_clk_freq (void);
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00	|   SCCR_TBS	  |	\
+#define CONFIG_SYS_SCCR	(SCCR_COM00	|   SCCR_TBS	  |	\
 			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
 			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
 			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
@@ -289,7 +289,7 @@ extern  unsigned long           ip860_get_clk_freq (void);
  *-----------------------------------------------------------------------
  */
 /* +0x0220 => 0x00C3 */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 
 /*-----------------------------------------------------------------------
@@ -297,20 +297,20 @@ extern  unsigned long           ip860_get_clk_freq (void);
  *-----------------------------------------------------------------------
  */
 /* +0x09C4 => TIMEP=1 */
-#define CFG_RCCR 0x0100
+#define CONFIG_SYS_RCCR 0x0100
 
 /*-----------------------------------------------------------------------
  * RMDS - RISC Microcode Development Support Control Register
  *-----------------------------------------------------------------------
  */
-#define CFG_RMDS 0
+#define CONFIG_SYS_RMDS 0
 
 /*-----------------------------------------------------------------------
  * DER - Debug Event Register
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -322,9 +322,9 @@ extern  unsigned long           ip860_get_clk_freq (void);
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	0xC3
+#define CONFIG_SYS_MAMR_PTA	0xC3
 
-#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /*
@@ -337,18 +337,18 @@ extern  unsigned long           ip860_get_clk_freq (void);
  * but not too much to meddle with FLASH accesses
  */
 /* allow for max 8 MB of Flash */
-#define CFG_REMAP_OR_AM		0xFF800000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0xFF800000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
 
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 /* 16 bit, bank valid */
-#define CFG_BR0_PRELIM	((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
 
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	CFG_BR0_PRELIM
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_BR0_PRELIM
 
 /*
  * BR2/OR2 - SDRAM
@@ -359,46 +359,46 @@ extern  unsigned long           ip860_get_clk_freq (void);
 
 #define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
 
-#define CFG_OR2		(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CFG_BR2		((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2		(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
+#define CONFIG_SYS_BR2		((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /*
  * BR3/OR3 - SRAM (16 bit)
  */
 #define	SRAM_BASE	0x20000000
-#define CFG_OR3		0xFFF00130		/* BI/SCY = 5/TRLX (internal) */
-#define CFG_BR3		((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define SRAM_SIZE	(1 + (~(CFG_OR3 & BR_BA_MSK)))
-#define CFG_OR3_PRELIM	CFG_OR3			/* Make sure to map early */
-#define CFG_BR3_PRELIM	CFG_BR3			/* in case it's used for ENV */
+#define CONFIG_SYS_OR3		0xFFF00130		/* BI/SCY = 5/TRLX (internal) */
+#define CONFIG_SYS_BR3		((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define SRAM_SIZE	(1 + (~(CONFIG_SYS_OR3 & BR_BA_MSK)))
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR3			/* Make sure to map early */
+#define CONFIG_SYS_BR3_PRELIM	CONFIG_SYS_BR3			/* in case it's used for ENV */
 
 /*
  * BR4/OR4 - Board Control & Status (8 bit)
  */
 #define	BCSR_BASE	0xFC000000
-#define CFG_OR4		0xFFFF0120		/* BI (internal) */
-#define CFG_BR4		((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR4		0xFFFF0120		/* BI (internal) */
+#define CONFIG_SYS_BR4		((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 
 /*
  * BR5/OR5 - IP Slot A/B (16 bit)
  */
 #define	IP_SLOT_BASE	0x40000000
-#define CFG_OR5		0xFE00010C		/* SETA/TRLX/BI/ SCY=0 (external) */
-#define CFG_BR5		((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR5		0xFE00010C		/* SETA/TRLX/BI/ SCY=0 (external) */
+#define CONFIG_SYS_BR5		((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 
 /*
  * BR6/OR6 - VME STD  (16 bit)
  */
 #define	VME_STD_BASE	0xFE000000
-#define CFG_OR6		0xFF00010C		/* SETA/TRLX/BI/SCY=0  (external) */
-#define CFG_BR6		((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR6		0xFF00010C		/* SETA/TRLX/BI/SCY=0  (external) */
+#define CONFIG_SYS_BR6		((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 
 /*
  * BR7/OR7 - SHORT I/O + RTC + IACK  (16 bit)
  */
 #define VME_SHORT_BASE	0xFF000000
-#define CFG_OR7		0xFF00010C		/* SETA/TRLX/BI/ SCY=0 (external) */
-#define CFG_BR7		((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR7		0xFF00010C		/* SETA/TRLX/BI/ SCY=0 (external) */
+#define CONFIG_SYS_BR7		((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 
 /*-----------------------------------------------------------------------
  * Board Control and Status Region:
diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h
index 31fbf32..3cb6cf7 100644
--- a/include/configs/IPHASE4539.h
+++ b/include/configs/IPHASE4539.h
@@ -80,10 +80,10 @@
  * - Select bus for bd/buffers (see 28-13)
  * - Half duplex
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 #endif	/* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 
@@ -110,8 +110,8 @@
  */
 #undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * Software (bit-bang) I2C driver configuration
@@ -152,30 +152,30 @@
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15 MB in DRAM	*/
 
 #define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passed to Linux in MHz */
 					/* for versions < 2.4.5-pre5	 */
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define CFG_RESET_ADDRESS	0x04400000
+#define CONFIG_SYS_RESET_ADDRESS	0x04400000
 
 #define CONFIG_MISC_INIT_R	1	/* We need misc_init_r()	*/
 
@@ -184,70 +184,70 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration (Setup by the
- * startup code). Please note that CFG_SDRAM_BASE _must_ start at 0.
+ * startup code). Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0.
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFF800000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF800000
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 << 10)     /* Reserve 256 kB for Monitor  */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)     /* Reserve 256 kB for Monitor  */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	64	/* max num of sects on one chip */
-#define CFG_MAX_FLASH_SIZE	(CFG_MAX_FLASH_SECT * 0x10000)	/* 4 MB */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_SIZE	(CONFIG_SYS_MAX_FLASH_SECT * 0x10000)	/* 4 MB */
 
-#define CFG_FLASH_ERASE_TOUT	2400000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	2400000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
 
 /* Environment in FLASH, there is little space left in Serial EEPROM */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SECT_SIZE	0x10000 /* We use one complete sector	*/
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x10000) /* 2. sector */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x10000) /* 2. sector */
 
 
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  *
- * if you change bits in the HRCW, you must also change the CFG_*
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
  * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
  */
-#define CFG_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM )		|\
+#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM )		|\
 			  ( HRCW_L2CPC10 | HRCW_ISB110 )	|\
 			  ( HRCW_MMR11 | HRCW_APPC10 )		|\
 			  ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )	 \
 			) /* 0x14863245 */
 
 /* no slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
+#define CONFIG_SYS_HRCW_SLAVE1 0
+#define CONFIG_SYS_HRCW_SLAVE2 0
+#define CONFIG_SYS_HRCW_SLAVE3 0
+#define CONFIG_SYS_HRCW_SLAVE4 0
+#define CONFIG_SYS_HRCW_SLAVE5 0
+#define CONFIG_SYS_HRCW_SLAVE6 0
+#define CONFIG_SYS_HRCW_SLAVE7 0
 
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFF000000 /* We keep original value */
+#define CONFIG_SYS_IMMR		0xFF000000 /* We keep original value */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Internal Definitions
@@ -261,9 +261,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32     /* For MPC8260 CPU		*/
+#define CONFIG_SYS_CACHELINE_SIZE	32     /* For MPC8260 CPU		*/
 #if defined(CONFIG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5      /* log base 2 of the above value */
+# define CONFIG_SYS_CACHELINE_SHIFT	5      /* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -273,29 +273,29 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 			 HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL	(HID0_IFEM|HID0_ABE)
-#define CFG_HID2	0
+#define CONFIG_SYS_HID0_FINAL	(HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2	0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register					 5-5
  *-----------------------------------------------------------------------
  * turn on Checkstop Reset Enable
  */
-#define CFG_RMR		RMR_CSRE
+#define CONFIG_SYS_RMR		RMR_CSRE
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration					 4-25
  *-----------------------------------------------------------------------
  */
-#define CFG_BCR		0xA01C0000
+#define CONFIG_SYS_BCR		0xA01C0000
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration				 4-31
  *-----------------------------------------------------------------------
  */
-#define CFG_SIUMCR	0X4205C000
+#define CONFIG_SYS_SIUMCR	0X4205C000
 
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control				 4-35
@@ -304,10 +304,10 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #if defined (CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
@@ -317,7 +317,7 @@
  * and enable Time Counter
  *-----------------------------------------------------------------------
  */
-#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		 4-42
@@ -325,20 +325,20 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control					 9-8
  *-----------------------------------------------------------------------
  * Ensure DFBRG is Divide by 16
  */
-#define CFG_SCCR	0
+#define CONFIG_SYS_SCCR	0
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration				13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR	0
+#define CONFIG_SYS_RCCR	0
 
 /*-----------------------------------------------------------------------
  * Init Memory Controller:
@@ -349,13 +349,13 @@
  *  1	60x	SDRAM	64 bit	SDRAM
  */
 
-#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK) | 0x0801)
-#define CFG_OR0_PRELIM	0xFF800882
-#define CFG_BR1_PRELIM	((CFG_SDRAM_BASE & BRx_BA_MSK) | 0x0041)
-#define CFG_OR1_PRELIM	0xF8002CD0
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) | 0x0801)
+#define CONFIG_SYS_OR0_PRELIM	0xFF800882
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) | 0x0041)
+#define CONFIG_SYS_OR1_PRELIM	0xF8002CD0
 
-#define CFG_PSDMR	0x404A241A
-#define CFG_MPTPR	0x00007400
-#define CFG_PSRT	0x00000007
+#define CONFIG_SYS_PSDMR	0x404A241A
+#define CONFIG_SYS_MPTPR	0x00007400
+#define CONFIG_SYS_PSRT	0x00000007
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h
index 8b6f3ce..6eb466a 100644
--- a/include/configs/ISPAN.h
+++ b/include/configs/ISPAN.h
@@ -69,14 +69,14 @@
 
 #if CONFIG_ETHER_INDEX == 3
 
-#define CFG_PHY_ADDR		0
-#define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
-#define CFG_CMXFCR_MASK		(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+#define CONFIG_SYS_PHY_ADDR		0
+#define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
+#define CONFIG_SYS_CMXFCR_MASK		(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
 
 #endif /* CONFIG_ETHER_INDEX == 3 */
 
-#define CFG_CPMFCR_RAMTYPE	0
-#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 
 #define CONFIG_MII				/* MII PHY management		*/
 #define CONFIG_BITBANGMII			/* Bit-bang MII PHY management	*/
@@ -85,18 +85,18 @@
  */
 #define MDIO_PORT		3		/* Port D */
 
-#define CFG_MDIO_PIN		0x00040000	/* PD13 */
-#define CFG_MDC_PIN		0x00080000	/* PD12 */
+#define CONFIG_SYS_MDIO_PIN		0x00040000	/* PD13 */
+#define CONFIG_SYS_MDC_PIN		0x00080000	/* PD12 */
 
-#define MDIO_ACTIVE		(iop->pdir |=  CFG_MDIO_PIN)
-#define MDIO_TRISTATE		(iop->pdir &= ~CFG_MDIO_PIN)
-#define MDIO_READ		((iop->pdat &  CFG_MDIO_PIN) != 0)
+#define MDIO_ACTIVE		(iop->pdir |=  CONFIG_SYS_MDIO_PIN)
+#define MDIO_TRISTATE		(iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
+#define MDIO_READ		((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 
-#define MDIO(bit)		if(bit) iop->pdat |=  CFG_MDIO_PIN; \
-				else	iop->pdat &= ~CFG_MDIO_PIN
+#define MDIO(bit)		if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
+				else	iop->pdat &= ~CONFIG_SYS_MDIO_PIN
 
-#define MDC(bit)		if(bit) iop->pdat |=  CFG_MDC_PIN; \
-				else	iop->pdat &= ~CFG_MDC_PIN
+#define MDC(bit)		if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
+				else	iop->pdat &= ~CONFIG_SYS_MDC_PIN
 
 #define MIIDELAY		udelay(1)
 
@@ -138,25 +138,25 @@
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  */
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#define CFG_LONGHELP				/* #undef to save memory	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)  /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* Max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP				/* #undef to save memory	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)  /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* Max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x03B00000	/* 1 ... 59 MB in SDRAM		*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x03B00000	/* 1 ... 59 MB in SDRAM		*/
 
-#define CFG_LOAD_ADDR		0x100000	/* Default load address		*/
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* Default load address		*/
 
-#define CFG_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
+#define CONFIG_SYS_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define CFG_RESET_ADDRESS	0x09900000
+#define CONFIG_SYS_RESET_ADDRESS	0x09900000
 
 #define CONFIG_MISC_INIT_R			/* We need misc_init_r()	*/
 
@@ -165,70 +165,70 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor   */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor   */
 #ifdef CONFIG_BZIP2
-#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()    */
+#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()    */
 #else
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()  */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()  */
 #endif /* CONFIG_BZIP2 */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_FLASH_BASE		0xFE000000
-#define CFG_FLASH_CFI				/* The flash is CFI compatible  */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible  */
 #define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
-#define CFG_MAX_FLASH_BANKS	1		/* Max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	142		/* Max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	142		/* Max num of sects on one chip */
 
 /* Environment is in flash, there is little space left in Serial EEPROM */
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x10000		/* We use one complete sector	*/
 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  *
- * If you change bits in the HRCW, you must also change the CFG_*
+ * If you change bits in the HRCW, you must also change the CONFIG_SYS_*
  * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
  */
 /* 0x1686B245 */
-#define CFG_HRCW_MASTER (HRCW_EBM      | HRCW_BPS01       | HRCW_CIP    |\
+#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM      | HRCW_BPS01       | HRCW_CIP    |\
 			 HRCW_L2CPC10  | HRCW_ISB110                    |\
 			 HRCW_BMS      | HRCW_MMR11       | HRCW_APPC10 |\
 			 HRCW_CS10PC01 | HRCW_MODCK_H0101                \
 			)
 /* No slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
+#define CONFIG_SYS_HRCW_SLAVE1 0
+#define CONFIG_SYS_HRCW_SLAVE2 0
+#define CONFIG_SYS_HRCW_SLAVE3 0
+#define CONFIG_SYS_HRCW_SLAVE4 0
+#define CONFIG_SYS_HRCW_SLAVE5 0
+#define CONFIG_SYS_HRCW_SLAVE6 0
+#define CONFIG_SYS_HRCW_SLAVE7 0
 
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xF0F00000
-#ifdef CFG_REV_B
-#define CFG_DEFAULT_IMMR	0xFF000000
-#endif /* CFG_REV_B */
+#define CONFIG_SYS_IMMR		0xF0F00000
+#ifdef CONFIG_SYS_REV_B
+#define CONFIG_SYS_DEFAULT_IMMR	0xFF000000
+#endif /* CONFIG_SYS_REV_B */
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000		/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128  /* Size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* Size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Internal Definitions
@@ -241,7 +241,7 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU			*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU			*/
 
 /*-----------------------------------------------------------------------
  * HIDx - Hardware Implementation-dependent Registers		2-11
@@ -250,29 +250,29 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT		(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+#define CONFIG_SYS_HID0_INIT		(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 				HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL		(HID0_ICE|HID0_IFEM|HID0_ABE)
-#define CFG_HID2		0
+#define CONFIG_SYS_HID0_FINAL		(HID0_ICE|HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2		0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register					 5-5
  *-----------------------------------------------------------------------
  * turn on Checkstop Reset Enable
  */
-#define CFG_RMR			RMR_CSRE
+#define CONFIG_SYS_RMR			RMR_CSRE
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration					 4-25
  *-----------------------------------------------------------------------
  */
-#define CFG_BCR			0xA01C0000
+#define CONFIG_SYS_BCR			0xA01C0000
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration				 4-31
  *-----------------------------------------------------------------------
  */
-#define CFG_SIUMCR		0x42250000/* 0x4205C000 */
+#define CONFIG_SYS_SIUMCR		0x42250000/* 0x4205C000 */
 
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control				 4-35
@@ -281,10 +281,10 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #if defined (CONFIG_WATCHDOG)
-#define CFG_SYPCR		(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR		(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 				SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
-#define CFG_SYPCR		(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR		(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 				SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
@@ -294,7 +294,7 @@
  * and enable Time Counter
  *-----------------------------------------------------------------------
  */
-#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		 4-42
@@ -302,20 +302,20 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control					 9-8
  *-----------------------------------------------------------------------
  * Ensure DFBRG is Divide by 16
  */
-#define CFG_SCCR		SCCR_DFBRG01
+#define CONFIG_SYS_SCCR		SCCR_DFBRG01
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration				13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR		0
+#define CONFIG_SYS_RCCR		0
 
 /*-----------------------------------------------------------------------
  * Init Memory Controller:
@@ -326,31 +326,31 @@
  *  1	60x	SDRAM	64 bit                          SDRAM
  *  2	Local	SDRAM	32 bit	                        SDRAM
  */
-#define CFG_USE_FIRMWARE	/* If defined - do not initialise memory
+#define CONFIG_SYS_USE_FIRMWARE	/* If defined - do not initialise memory
 				   controller, rely on initialisation
 				   performed by the Interphase boot firmware.
 				 */
 
-#define CFG_OR0_PRELIM		0xFE000882
-#ifdef CFG_REV_B
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BRx_PS_8  | BRx_V)
+#define CONFIG_SYS_OR0_PRELIM		0xFE000882
+#ifdef CONFIG_SYS_REV_B
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BRx_PS_8  | BRx_V)
 #else  /* Rev. D */
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BRx_PS_16 | BRx_V)
-#endif /* CFG_REV_B */
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BRx_PS_16 | BRx_V)
+#endif /* CONFIG_SYS_REV_B */
 
-#define CFG_MPTPR		0x7F00
+#define CONFIG_SYS_MPTPR		0x7F00
 
 /* Please note that 60x SDRAM MUST start at 0 */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_60x_BR		0x00000041
-#define CFG_60x_OR		0xF0002CD0
-#define CFG_PSDMR		0x0049929A
-#define CFG_PSRT		0x07
-
-#define CFG_LSDRAM_BASE		0xF7000000
-#define CFG_LOC_BR		0x00001861
-#define CFG_LOC_OR		0xFF803280
-#define CFG_LSDMR		0x8285A552
-#define CFG_LSRT		0x07
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_60x_BR		0x00000041
+#define CONFIG_SYS_60x_OR		0xF0002CD0
+#define CONFIG_SYS_PSDMR		0x0049929A
+#define CONFIG_SYS_PSRT		0x07
+
+#define CONFIG_SYS_LSDRAM_BASE		0xF7000000
+#define CONFIG_SYS_LOC_BR		0x00001861
+#define CONFIG_SYS_LOC_OR		0xFF803280
+#define CONFIG_SYS_LSDMR		0x8285A552
+#define CONFIG_SYS_LSRT		0x07
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h
index 6a422c8..cd100df 100644
--- a/include/configs/IVML24.h
+++ b/include/configs/IVML24.h
@@ -66,7 +66,7 @@
 				"nfsaddrs=10.0.0.99:10.0.0.2"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -96,36 +96,36 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address	*/
 
-#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+#define	CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
 
-#define CFG_PB_12V_ENABLE	0x00002000		/* PB 18	*/
-#define CFG_PB_ILOCK_SWITCH	0x00004000		/* PB 17	*/
-#define CFG_PB_SDRAM_CLKE	0x00008000		/* PB 16	*/
-#define CFG_PB_ETH_POWERDOWN	0x00010000		/* PB 15	*/
-#define CFG_PB_IDE_MOTOR	0x00020000		/* PB 14	*/
+#define CONFIG_SYS_PB_12V_ENABLE	0x00002000		/* PB 18	*/
+#define CONFIG_SYS_PB_ILOCK_SWITCH	0x00004000		/* PB 17	*/
+#define CONFIG_SYS_PB_SDRAM_CLKE	0x00008000		/* PB 16	*/
+#define CONFIG_SYS_PB_ETH_POWERDOWN	0x00010000		/* PB 15	*/
+#define CONFIG_SYS_PB_IDE_MOTOR	0x00020000		/* PB 14	*/
 
-#define CFG_PC_ETH_RESET	((ushort)0x0010)	/* PC 11	*/
-#define CFG_PC_IDE_RESET	((ushort)0x0020)	/* PC 10	*/
+#define CONFIG_SYS_PC_ETH_RESET	((ushort)0x0010)	/* PC 11	*/
+#define CONFIG_SYS_PC_IDE_RESET	((ushort)0x0020)	/* PC 10	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -135,54 +135,54 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000 /* was: 0xFF000000 */
+#define CONFIG_SYS_IMMR		0xFFF00000 /* was: 0xFF000000 */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
 
 #if defined (CONFIG_IVML24_16M)
-# define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+# define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
 #elif defined (CONFIG_IVML24_32M)
-# define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+# define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
 #elif defined (CONFIG_IVML24_64M)
-# define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+# define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
 #endif
 
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFF000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
 #ifdef	DEBUG
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x7A000	/*   Offset   of Environment Sector	*/
@@ -190,9 +190,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -204,18 +204,18 @@
 #if defined(CONFIG_WATCHDOG)
 
 # if defined (CONFIG_IVML24_16M)
-#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#  define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 # elif defined (CONFIG_IVML24_32M)
-#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#  define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWP)
 # elif defined (CONFIG_IVML24_64M)
-#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#  define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWP)
 # endif
 
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -225,21 +225,21 @@
  */
 /* EARB, DBGC and DBPC are initialised by the HCW */
 /* => 0x000000C0 */
-#define CFG_SIUMCR	(SIUMCR_BSC | SIUMCR_GB5E)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_BSC | SIUMCR_GB5E)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -248,7 +248,7 @@
  * interrupt status bit, set PLL multiplication factor !
  */
 /* 0x00B0C0C0 */
-#define CFG_PLPRCR							\
+#define CONFIG_SYS_PLPRCR							\
 		(	(11 << PLPRCR_MF_SHIFT) |			\
 			PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/	\
 			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
@@ -263,7 +263,7 @@
  */
 #define SCCR_MASK	SCCR_EBDF11
 /* 0x01800014 */
-#define CFG_SCCR	(SCCR_COM01	| /*SCCR_TBS|*/		\
+#define CONFIG_SYS_SCCR	(SCCR_COM01	| /*SCCR_TBS|*/		\
 			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
 			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
 			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
@@ -276,7 +276,7 @@
  *-----------------------------------------------------------------------
  */
 /* 0x00C3 */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 
 /*-----------------------------------------------------------------------
@@ -284,34 +284,34 @@
  *-----------------------------------------------------------------------
  */
 /* TIMEP=2 */
-#define CFG_RCCR 0x0200
+#define CONFIG_SYS_RCCR 0x0200
 
 /*-----------------------------------------------------------------------
  * RMDS - RISC Microcode Development Support Control Register
  *-----------------------------------------------------------------------
  */
-#define CFG_RMDS 0
+#define CONFIG_SYS_RMDS 0
 
 /*-----------------------------------------------------------------------
  *
  * Interrupt Levels
  *-----------------------------------------------------------------------
  */
-#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
+#define CONFIG_SYS_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
@@ -320,23 +320,23 @@
 #define CONFIG_IDE_8xx_DIRECT	1	/* PCMCIA interface required	*/
 #define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* The IVML24 has only 1 IDE bus*/
-#define CFG_IDE_MAXDEVICE	1	/*    ... and only 1 IDE device	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* The IVML24 has only 1 IDE bus*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/*    ... and only 1 IDE device	*/
 
-#define CFG_ATA_BASE_ADDR	0xFE100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#undef	CFG_ATA_IDE1_OFFSET		/* only one IDE bus available	*/
+#define CONFIG_SYS_ATA_BASE_ADDR	0xFE100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#undef	CONFIG_SYS_ATA_IDE1_OFFSET		/* only one IDE bus available	*/
 
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*/
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -351,18 +351,18 @@
  * but not too much to meddle with FLASH accesses
  */
 /* EPROMs are 512kb */
-#define CFG_REMAP_OR_AM		0xFFF80000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0xFFF80000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
 
 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_SCY_5_CLK | OR_EHTR)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_SCY_5_CLK | OR_EHTR)
 
-#define CFG_OR0_REMAP	( CFG_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \
-				CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \
-				CFG_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_REMAP	( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \
+				CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \
+				CONFIG_SYS_OR_TIMING_FLASH)
 /* 16 bit, bank valid */
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 
 /*
  * BR1/OR1 - ELIC SACCO bank  @ 0xFE000000
@@ -373,9 +373,9 @@
 #define ELIC_SACCO_OR_AM	0xFFFF8000
 #define ELIC_SACCO_TIMING	(OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
 
-#define CFG_OR1	(ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
+#define CONFIG_SYS_OR1	(ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
 			ELIC_SACCO_TIMING)
-#define CFG_BR1	((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_BR1	((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 
 /*
  * BR2/OR2 - ELIC EPIC bank   @ 0xFE008000
@@ -386,9 +386,9 @@
 #define ELIC_EPIC_OR_AM		0xFFFF8000
 #define ELIC_EPIC_TIMING	(OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
 
-#define CFG_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
+#define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
 			ELIC_EPIC_TIMING)
-#define CFG_BR2	((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_BR2	((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 
 /*
  * BR3/OR3: SDRAM
@@ -401,8 +401,8 @@
 
 #define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
 
-#define CFG_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
+#define CONFIG_SYS_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
 
 /*
  * BR4/OR4 - HDLC Address
@@ -413,8 +413,8 @@
 #define HDLC_ADDR_OR_AM		0xFFFF8000
 #define HDLC_ADDR_TIMING	OR_SCY_1_CLK
 
-#define CFG_OR4	(HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING)
-#define CFG_BR4	((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V )
+#define CONFIG_SYS_OR4	(HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING)
+#define CONFIG_SYS_BR4	((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V )
 
 /*
  * BR5/OR5: SHARC ADSP-2165L
@@ -425,29 +425,29 @@
 #define SHARC_OR_AM		0xFFC00000
 #define SHARC_TIMING		OR_SCY_0_CLK
 
-#define CFG_OR5	(SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING )
-#define CFG_BR5	((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR5	(SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING )
+#define CONFIG_SYS_BR5	((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
 
 /*
  * Memory Periodic Timer Prescaler
  */
 
 /* periodic timer for refresh */
-#define CFG_MBMR_PTB	204
+#define CONFIG_SYS_MBMR_PTB	204
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
 
 #if defined (CONFIG_IVML24_16M)
-# define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+# define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 #elif defined (CONFIG_IVML24_32M)
-# define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+# define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 #elif defined (CONFIG_IVML24_64M)
-# define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV8		/* setting for 1 bank	*/
+# define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV8		/* setting for 1 bank	*/
 #endif
 
 
@@ -457,17 +457,17 @@
 
 #if defined (CONFIG_IVML24_16M)
  /* 8 column SDRAM */
-# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+# define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #elif defined (CONFIG_IVML24_32M)
 /* 128 MBit SDRAM */
-# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+# define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #elif defined (CONFIG_IVML24_64M)
 /* 128 MBit SDRAM */
-# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+# define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #endif
diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h
index 54477ee..125cb4b 100644
--- a/include/configs/IVMS8.h
+++ b/include/configs/IVMS8.h
@@ -66,7 +66,7 @@
 				"nfsaddrs=10.0.0.99:10.0.0.2"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -95,34 +95,34 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address	*/
 
-#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+#define	CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
 
-#define CFG_PB_SDRAM_CLKE	0x00008000		/* PB 16	*/
-#define CFG_PB_ETH_POWERDOWN	0x00010000		/* PB 15	*/
-#define CFG_PB_IDE_MOTOR	0x00020000		/* PB 14	*/
+#define CONFIG_SYS_PB_SDRAM_CLKE	0x00008000		/* PB 16	*/
+#define CONFIG_SYS_PB_ETH_POWERDOWN	0x00010000		/* PB 15	*/
+#define CONFIG_SYS_PB_IDE_MOTOR	0x00020000		/* PB 14	*/
 
-#define CFG_PC_ETH_RESET	((ushort)0x0010)	/* PC 11	*/
-#define CFG_PC_IDE_RESET	((ushort)0x0020)	/* PC 10	*/
+#define CONFIG_SYS_PC_ETH_RESET	((ushort)0x0010)	/* PC 11	*/
+#define CONFIG_SYS_PC_IDE_RESET	((ushort)0x0020)	/* PC 10	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -132,53 +132,53 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000 /* was: 0xFF000000 */
+#define CONFIG_SYS_IMMR		0xFFF00000 /* was: 0xFF000000 */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
 #if defined (CONFIG_IVMS8_16M)
-# define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+# define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
 #elif defined (CONFIG_IVMS8_32M)
-# define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+# define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
 #elif defined (CONFIG_IVMS8_64M)
-# define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+# define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
 #endif
 
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFF000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
 #ifdef	DEBUG
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x7A000	/*   Offset   of Environment Sector	*/
@@ -186,9 +186,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -199,17 +199,17 @@
  */
 #if defined(CONFIG_WATCHDOG)
 # if defined (CONFIG_IVMS8_16M)
-#   define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#   define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #  elif defined (CONFIG_IVMS8_32M)
-#   define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#   define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWP)
 #  elif defined (CONFIG_IVMS8_64M)
-#   define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#   define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWP)
 #  endif
 #else
-# define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+# define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -219,21 +219,21 @@
  */
 /* EARB, DBGC and DBPC are initialised by the HCW */
 /* => 0x000000C0 */
-#define CFG_SIUMCR	(SIUMCR_BSC | SIUMCR_GB5E)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_BSC | SIUMCR_GB5E)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -242,7 +242,7 @@
  * interrupt status bit, set PLL multiplication factor !
  */
 /* 0x00B0C0C0 */
-#define CFG_PLPRCR							\
+#define CONFIG_SYS_PLPRCR							\
 		(	(11 << PLPRCR_MF_SHIFT) |			\
 			PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/	\
 			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
@@ -257,7 +257,7 @@
  */
 #define SCCR_MASK	SCCR_EBDF11
 /* 0x01800014 */
-#define CFG_SCCR	(SCCR_COM01	| /*SCCR_TBS|*/		\
+#define CONFIG_SYS_SCCR	(SCCR_COM01	| /*SCCR_TBS|*/		\
 			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
 			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
 			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
@@ -270,7 +270,7 @@
  *-----------------------------------------------------------------------
  */
 /* 0x00C3 */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 
 /*-----------------------------------------------------------------------
@@ -278,34 +278,34 @@
  *-----------------------------------------------------------------------
  */
 /* TIMEP=2 */
-#define CFG_RCCR 0x0200
+#define CONFIG_SYS_RCCR 0x0200
 
 /*-----------------------------------------------------------------------
  * RMDS - RISC Microcode Development Support Control Register
  *-----------------------------------------------------------------------
  */
-#define CFG_RMDS 0
+#define CONFIG_SYS_RMDS 0
 
 /*-----------------------------------------------------------------------
  *
  * Interrupt Levels
  *-----------------------------------------------------------------------
  */
-#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
+#define CONFIG_SYS_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
@@ -314,23 +314,23 @@
 #define CONFIG_IDE_8xx_DIRECT	1	/* PCMCIA interface required	*/
 #define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* The IVMS8 has only 1 IDE bus	*/
-#define CFG_IDE_MAXDEVICE	1	/*    ... and only 1 IDE device	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* The IVMS8 has only 1 IDE bus	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/*    ... and only 1 IDE device	*/
 
-#define CFG_ATA_BASE_ADDR	0xFE100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#undef	CFG_ATA_IDE1_OFFSET		/* only one IDE bus available	*/
+#define CONFIG_SYS_ATA_BASE_ADDR	0xFE100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#undef	CONFIG_SYS_ATA_IDE1_OFFSET		/* only one IDE bus available	*/
 
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*/
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -345,17 +345,17 @@
  * but not too much to meddle with FLASH accesses
  */
 /* EPROMs are 512kb */
-#define CFG_REMAP_OR_AM		0xFFF80000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0xFFF80000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
 
 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
 				 OR_SCY_5_CLK | OR_EHTR)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 /* 16 bit, bank valid */
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 
 /*
  * BR1/OR1 - ELIC SACCO bank  @ 0xFE000000
@@ -366,8 +366,8 @@
 #define ELIC_SACCO_OR_AM	0xFFFF8000
 #define ELIC_SACCO_TIMING	0x00000F26
 
-#define CFG_OR1	(ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING)
-#define CFG_BR1	((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR1	(ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING)
+#define CONFIG_SYS_BR1	((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 
 /*
  * BR2/OR2 - ELIC EPIC bank   @ 0xFE008000
@@ -378,8 +378,8 @@
 #define ELIC_EPIC_OR_AM		0xFFFF8000
 #define ELIC_EPIC_TIMING	0x00000F26
 
-#define CFG_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING)
-#define CFG_BR2	((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING)
+#define CONFIG_SYS_BR2	((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 
 /*
  * BR3/OR3: SDRAM
@@ -392,8 +392,8 @@
 
 #define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
 
-#define CFG_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
+#define CONFIG_SYS_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
 
 /*
  * BR4/OR4: not used
@@ -408,28 +408,28 @@
 #define SHARC_OR_AM		0xFFC00000
 #define SHARC_TIMING		0x00000700
 
-#define CFG_OR5	(SHARC_OR_AM | SHARC_TIMING )
-#define CFG_BR5	((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR5	(SHARC_OR_AM | SHARC_TIMING )
+#define CONFIG_SYS_BR5	((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
 
 /*
  * Memory Periodic Timer Prescaler
  */
 
 /* periodic timer for refresh */
-#define CFG_MBMR_PTB	204
+#define CONFIG_SYS_MBMR_PTB	204
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
 #if defined (CONFIG_IVMS8_16M)
- #define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+ #define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 #elif defined (CONFIG_IVMS8_32M)
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 #elif defined (CONFIG_IVMS8_64M)
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV8		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV8		/* setting for 1 bank	*/
 #endif
 
 
@@ -439,17 +439,17 @@
 
 #if defined (CONFIG_IVMS8_16M)
  /* 8 column SDRAM */
-# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+# define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #elif defined (CONFIG_IVMS8_32M)
 /* 128 MBit SDRAM */
-#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+#define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #elif defined (CONFIG_IVMS8_64M)
 /* 128 MBit SDRAM */
-#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+#define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index a705ac1..5ef0b77 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -32,7 +32,7 @@
 #define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
 #define CONFIG_ICECUBE		1	/* ... on IceCube board */
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
@@ -44,7 +44,7 @@
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 
 #ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
@@ -69,12 +69,12 @@
 #define CONFIG_PCI_IO_SIZE	0x01000000
 #endif
 
-#define CFG_XLB_PIPELINING	1
+#define CONFIG_SYS_XLB_PIPELINING	1
 
 #define CONFIG_NET_MULTI	1
 #define CONFIG_MII		1
 #define CONFIG_EEPRO100		1
-#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
 #define CONFIG_NS8382X		1
 
 #else
@@ -89,12 +89,12 @@
 /* USB */
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_STORAGE
-#define CFG_OHCI_BE_CONTROLLER
-#undef CFG_USB_OHCI_BOARD_INIT
-#define CFG_USB_OHCI_CPU_INIT	1
-#define CFG_USB_OHCI_REGS_BASE	MPC5XXX_USB
-#define CFG_USB_OHCI_SLOT_NAME	"mpc5200"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS	15
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
+#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	MPC5XXX_USB
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"mpc5200"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
 
 #define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
 
@@ -127,15 +127,15 @@
 
 
 #if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
-#   define CFG_LOWBOOT	        1
-#   define CFG_LOWBOOT16	1
+#   define CONFIG_SYS_LOWBOOT	        1
+#   define CONFIG_SYS_LOWBOOT16	1
 #endif
 #if (TEXT_BASE == 0xFF800000)		/* Boot low with  8 MB Flash */
 #if defined(CONFIG_LITE5200B)
-#   error CFG_LOWBOOT08 is incompatible with the Lite5200B
+#   error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
 #else
-#   define CFG_LOWBOOT	        1
-#   define CFG_LOWBOOT08	1
+#   define CONFIG_SYS_LOWBOOT	        1
+#   define CONFIG_SYS_LOWBOOT08	1
 #endif
 #endif
 
@@ -174,9 +174,9 @@
  * IPB Bus clocking configuration.
  */
 #if defined(CONFIG_LITE5200B)
-#define CFG_IPBCLK_EQUALS_XLBCLK	/* define for 133MHz speed */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK	/* define for 133MHz speed */
 #else
-#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 #endif
 #endif /* CONFIG_MPC5200 */
 
@@ -193,62 +193,62 @@
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
 
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration
  */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
 
 /*
  * Flash configuration
  */
 #if defined(CONFIG_LITE5200B)
-#define CFG_FLASH_BASE		0xFE000000
-#define CFG_FLASH_SIZE		0x01000000
-#if !defined(CFG_LOWBOOT)
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x01760000 + 0x00800000)
-#else	/* CFG_LOWBOOT */
-#if defined(CFG_LOWBOOT08)
-# error CFG_LOWBOOT08 is incompatible with the Lite5200B
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
+#if !defined(CONFIG_SYS_LOWBOOT)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000)
+#else	/* CONFIG_SYS_LOWBOOT */
+#if defined(CONFIG_SYS_LOWBOOT08)
+# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
 #endif
-#if defined(CFG_LOWBOOT16)
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x01060000)
+#if defined(CONFIG_SYS_LOWBOOT16)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x01060000)
 #endif
-#endif /* CFG_LOWBOOT */
+#endif /* CONFIG_SYS_LOWBOOT */
 #else /* !CONFIG_LITE5200B (IceCube)*/
-#define CFG_FLASH_BASE		0xFF000000
-#define CFG_FLASH_SIZE		0x01000000
-#if !defined(CFG_LOWBOOT)
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00740000 + 0x00800000)
-#else	/* CFG_LOWBOOT */
-#if defined(CFG_LOWBOOT08)
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000 + 0x00800000)
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
+#if !defined(CONFIG_SYS_LOWBOOT)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000)
+#else	/* CONFIG_SYS_LOWBOOT */
+#if defined(CONFIG_SYS_LOWBOOT08)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000)
 #endif
-#if defined(CFG_LOWBOOT16)
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000)
+#if defined(CONFIG_SYS_LOWBOOT16)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
 #endif
-#endif	/* CFG_LOWBOOT */
+#endif	/* CONFIG_SYS_LOWBOOT */
 #endif /* CONFIG_LITE5200B */
-#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks      */
 
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
 
 #undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */
 
 #if defined(CONFIG_LITE5200B)
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_BANKS_LIST	{CFG_CS1_START,CFG_CS0_START}
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START}
 #endif
 
 
@@ -267,121 +267,119 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
 /*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
  */
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
 #define CONFIG_PHY_ADDR		0x00
-#if defined(CONFIG_LITE5200B)
-#define CONFIG_FEC_MII100	1
-#endif
 
 /*
  * GPIO configuration
  */
 #ifdef CONFIG_MPC5200_DDR
-#define CFG_GPS_PORT_CONFIG	0x90000004
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x90000004
 #else
-#define CFG_GPS_PORT_CONFIG	0x10000004
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x10000004
 #endif
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*
  * Various low-level settings
  */
 #if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 #else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
 #endif
 
 #if defined(CONFIG_LITE5200B)
-#define CFG_CS1_START		CFG_FLASH_BASE
-#define CFG_CS1_SIZE		CFG_FLASH_SIZE
-#define CFG_CS1_CFG		0x00047800
-#define CFG_CS0_START		(CFG_FLASH_BASE + CFG_FLASH_SIZE)
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_START	CFG_CS0_START
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x00047800
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS1_CFG		0x00047800
+#define CONFIG_SYS_CS0_START		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_CS0_START
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047800
 #else /* IceCube aka Lite5200 */
 #ifdef CONFIG_MPC5200_DDR
 
-#define CFG_BOOTCS_START	(CFG_CS1_START + CFG_CS1_SIZE)
-#define CFG_BOOTCS_SIZE		0x00800000
-#define CFG_BOOTCS_CFG		0x00047801
-#define CFG_CS1_START		CFG_FLASH_BASE
-#define CFG_CS1_SIZE		0x00800000
-#define CFG_CS1_CFG		0x00047800
+#define CONFIG_SYS_BOOTCS_START	(CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE)
+#define CONFIG_SYS_BOOTCS_SIZE		0x00800000
+#define CONFIG_SYS_BOOTCS_CFG		0x00047801
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS1_SIZE		0x00800000
+#define CONFIG_SYS_CS1_CFG		0x00047800
 
 #else /* !CONFIG_MPC5200_DDR */
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x00047801
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047801
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
 #endif /* CONFIG_MPC5200_DDR */
 #endif /*CONFIG_LITE5200B */
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
 
-#define CFG_RESET_ADDRESS	0xff000000
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
 
 /*-----------------------------------------------------------------------
  * USB stuff
@@ -403,24 +401,24 @@
 #define	CONFIG_IDE_RESET		/* reset for ide supported	*/
 #define CONFIG_IDE_PREINIT
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(0x0060)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005C)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
 
 /* Interval between registers                                                */
-#define CFG_ATA_STRIDE          4
+#define CONFIG_SYS_ATA_STRIDE          4
 
 #define CONFIG_ATAPI            1
 
diff --git a/include/configs/JSE.h b/include/configs/JSE.h
index b457272..8aca1f9 100644
--- a/include/configs/JSE.h
+++ b/include/configs/JSE.h
@@ -41,28 +41,28 @@
   /* ... with a 33MHz OSC. connected to the SysCLK input */
 #define CONFIG_SYS_CLK_FREQ	33333333
   /* ... with on-chip memory here (4KBytes) */
-#define CFG_OCM_DATA_ADDR 0xF4000000
-#define CFG_OCM_DATA_SIZE 0x00001000
+#define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000
+#define CONFIG_SYS_OCM_DATA_SIZE 0x00001000
   /* Do not set up locked dcache as init ram. */
-#undef CFG_INIT_DCACHE_CS
+#undef CONFIG_SYS_INIT_DCACHE_CS
 
   /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
 #define CONFIG_SYSTEMACE 1
-#define CFG_SYSTEMACE_BASE 0xf0000000
-#define CFG_SYSTEMACE_WIDTH 8
+#define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
+#define CONFIG_SYS_SYSTEMACE_WIDTH 8
 #define CONFIG_DOS_PARTITION 1
 
   /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
-#define CFG_TEMP_STACK_OCM 1
+#define CONFIG_SYS_TEMP_STACK_OCM 1
   /* ... place INIT RAM in the OCM address */
-# define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR
+# define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR
   /* ... give it the whole init ram */
-# define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE
+# define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE
   /* ... Shave a bit off the end for global data */
-# define CFG_GBL_DATA_SIZE	128
-# define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+# define CONFIG_SYS_GBL_DATA_SIZE	128
+# define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
   /* ... and place the stack pointer at the top of what's left. */
-# define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+# define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
   /* Enable board_pre_init function */
 #define CONFIG_BOARD_PRE_INIT	1
@@ -72,7 +72,7 @@
   /* Disable call to post_init_f: late init function. */
 #undef CONFIG_POST
   /* Enable DRAM test. */
-#define CFG_DRAM_TEST 1
+#define CONFIG_SYS_DRAM_TEST 1
   /* Enable misc_init_r function. */
 #define CONFIG_MISC_INIT_R 1
 
@@ -83,14 +83,14 @@
 #undef	CONFIG_ENV_IS_NOWHERE
 
   /* This is the 7bit address of the device, not including P. */
-#define CFG_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
   /* After the device address, need one more address byte. */
-#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
   /* The EEPROM is 512 bytes. */
-#define CFG_EEPROM_SIZE 512
+#define CONFIG_SYS_EEPROM_SIZE 512
   /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
-#define CFG_EEPROM_PAGE_WRITE_BITS 4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
   /* Put the environment in the second half. */
 #define CONFIG_ENV_OFFSET	0x00
 #define CONFIG_ENV_SIZE	512
@@ -130,8 +130,9 @@
 
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		1	/* PHY address			*/
 
@@ -171,52 +172,52 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#define CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
 /*
- * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
  * The Linux BASE_BAUD define should match this configuration.
  *    baseBaud = cpuClock/(uartDivisor*16)
- * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  * set Linux BASE_BAUD to 403200.
  */
-#undef	CFG_EXT_SERIAL_CLOCK	       /* external serial clock */
-#undef	CFG_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* external serial clock */
+#undef	CONFIG_SYS_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD	    691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 
 /*-----------------------------------------------------------------------
@@ -232,14 +233,14 @@
 #undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
 					/* resource configuration	*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * External peripheral base address
@@ -248,36 +249,36 @@
 #undef	CONFIG_IDE_LED			/* no led for ide supported	*/
 #undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
 
-#define CFG_KEY_REG_BASE_ADDR	0xF0100000
-#define CFG_IR_REG_BASE_ADDR	0xF0200000
-#define CFG_FPGA_REG_BASE_ADDR	0xF0300000
+#define CONFIG_SYS_KEY_REG_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_IR_REG_BASE_ADDR	0xF0200000
+#define CONFIG_SYS_FPGA_REG_BASE_ADDR	0xF0300000
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFF80000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFF80000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 /*
  * Init Memory Controller:
@@ -285,7 +286,7 @@
  * BR0/1 and OR0/1 (FLASH)
  */
 
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	*/
 #define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
 
 
diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h
index eeb3924..4b67c94 100644
--- a/include/configs/KAREF.h
+++ b/include/configs/KAREF.h
@@ -43,7 +43,7 @@
 #define CONFIG_BOARD_EARLY_INIT_F 1	     /* Call board_pre_init	*/
 #define CONFIG_MISC_INIT_F	  1	     /* Call board misc_init_f	*/
 #define CONFIG_MISC_INIT_R	  1	     /* Call board misc_init_r	*/
-#undef	CFG_DRAM_TEST			     /* Disable-takes long time!*/
+#undef	CONFIG_SYS_DRAM_TEST			     /* Disable-takes long time!*/
 #define CONFIG_SYS_CLK_FREQ	  66666666   /* external freq to pll	*/
 
 #define CONFIG_VERY_BIG_RAM 1
@@ -55,38 +55,38 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE	       0x00000000    /* _must_ be 0		*/
-#define CFG_FLASH_BASE	       0xfff80000    /* start of FLASH		*/
-#define CFG_MONITOR_BASE       0xfff80000    /* start of monitor	*/
-#define CFG_PCI_MEMBASE	       0x80000000    /* mapped pci memory	*/
-#define CFG_PERIPHERAL_BASE    0xe0000000    /* internal peripherals	*/
-#define CFG_ISRAM_BASE	       0xc0000000    /* internal SRAM		*/
-#define CFG_PCI_BASE	       0xd0000000    /* internal PCI regs	*/
-
-#define CFG_NVRAM_BASE_ADDR   (CFG_PERIPHERAL_BASE + 0x08000000)
-#define CFG_KAREF_FPGA_BASE   (CFG_PERIPHERAL_BASE + 0x08200000)
-#define CFG_OFEM_FPGA_BASE    (CFG_PERIPHERAL_BASE + 0x08400000)
-#define CFG_BME32_BASE	      (CFG_PERIPHERAL_BASE + 0x08500000)
-#define CFG_GPIO_BASE	      (CFG_PERIPHERAL_BASE + 0x00000700)
+#define CONFIG_SYS_SDRAM_BASE	       0x00000000    /* _must_ be 0		*/
+#define CONFIG_SYS_FLASH_BASE	       0xfff80000    /* start of FLASH		*/
+#define CONFIG_SYS_MONITOR_BASE       0xfff80000    /* start of monitor	*/
+#define CONFIG_SYS_PCI_MEMBASE	       0x80000000    /* mapped pci memory	*/
+#define CONFIG_SYS_PERIPHERAL_BASE    0xe0000000    /* internal peripherals	*/
+#define CONFIG_SYS_ISRAM_BASE	       0xc0000000    /* internal SRAM		*/
+#define CONFIG_SYS_PCI_BASE	       0xd0000000    /* internal PCI regs	*/
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR   (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
+#define CONFIG_SYS_KAREF_FPGA_BASE   (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
+#define CONFIG_SYS_OFEM_FPGA_BASE    (CONFIG_SYS_PERIPHERAL_BASE + 0x08400000)
+#define CONFIG_SYS_BME32_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
+#define CONFIG_SYS_GPIO_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
 
 /* Here for completeness */
-#define CFG_OFEMAC_BASE	      (CFG_PERIPHERAL_BASE + 0x08600000)
+#define CONFIG_SYS_OFEMAC_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08600000)
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
-#define CFG_TEMP_STACK_OCM    1
-#define CFG_OCM_DATA_ADDR     CFG_ISRAM_BASE
-#define CFG_INIT_RAM_ADDR     CFG_ISRAM_BASE /* Initial RAM address	*/
-#define CFG_INIT_RAM_END      0x2000	     /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE     128	     /* num bytes initial data	*/
+#define CONFIG_SYS_TEMP_STACK_OCM    1
+#define CONFIG_SYS_OCM_DATA_ADDR     CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR     CONFIG_SYS_ISRAM_BASE /* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_END      0x2000	     /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE     128	     /* num bytes initial data	*/
 
-#define CFG_GBL_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR    (CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET    CFG_POST_WORD_ADDR
+#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_POST_WORD_ADDR    (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_POST_WORD_ADDR
 
-#define CFG_MONITOR_LEN	      (256 * 1024)   /* Rsrv 256kB for Mon	*/
-#define CFG_MALLOC_LEN	      (128 * 1024)   /* Rsrv 128kB for malloc	*/
+#define CONFIG_SYS_MONITOR_LEN	      (256 * 1024)   /* Rsrv 256kB for Mon	*/
+#define CONFIG_SYS_MALLOC_LEN	      (128 * 1024)   /* Rsrv 128kB for malloc	*/
 
 /*-----------------------------------------------------------------------
  * Serial Port
@@ -95,7 +95,7 @@
 #define CONFIG_SERIAL_MULTI   1
 #define CONFIG_BAUDRATE	      9600
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
 /*-----------------------------------------------------------------------
@@ -105,21 +105,21 @@
  * The DS1743 code assumes this condition (i.e. -- it assumes the base
  * address for the RTC registers is:
  *
- *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *	CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
  *
  *----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE	      (0x2000 - 8)   /* NVRAM size(8k)- RTC regs*/
+#define CONFIG_SYS_NVRAM_SIZE	      (0x2000 - 8)   /* NVRAM size(8k)- RTC regs*/
 #define CONFIG_RTC_DS174x     1		     /* DS1743 RTC		*/
 
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS   1		     /* number of banks		*/
-#define CFG_MAX_FLASH_SECT    8		     /* sectors per device	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS   1		     /* number of banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT    8		     /* sectors per device	*/
 
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT  120000	     /* Flash Erase TO (in ms)	 */
-#define CFG_FLASH_WRITE_TOUT  500	     /* Flash Write TO(in ms)	 */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT  120000	     /* Flash Erase TO (in ms)	 */
+#define CONFIG_SYS_FLASH_WRITE_TOUT  500	     /* Flash Write TO(in ms)	 */
 
 /*-----------------------------------------------------------------------
  * DDR SDRAM
@@ -132,9 +132,9 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C	      1		     /* I2C hardware support	*/
 #undef	CONFIG_SOFT_I2C			     /* I2C !bit-banged		*/
-#define CFG_I2C_SPEED	      400000	     /* I2C speed 400kHz	*/
-#define CFG_I2C_SLAVE	      0x7F	     /* I2C slave address	*/
-#define CFG_I2C_NOPROBES      {0x69}	     /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_SPEED	      400000	     /* I2C speed 400kHz	*/
+#define CONFIG_SYS_I2C_SLAVE	      0x7F	     /* I2C slave address	*/
+#define CONFIG_SYS_I2C_NOPROBES      {0x69}	     /* Don't probe these addrs */
 #define CONFIG_I2C_BUS1	      1		     /* Include i2c bus 1 supp	*/
 
 
@@ -147,16 +147,17 @@
 #define CONFIG_ENV_OVERWRITE  1		     /* allow env overwrite	*/
 
 #define CONFIG_ENV_SIZE	      0x1000	     /* Size of Env vars	*/
-#define CONFIG_ENV_ADDR	      (CFG_NVRAM_BASE_ADDR)
+#define CONFIG_ENV_ADDR	      (CONFIG_SYS_NVRAM_BASE_ADDR)
 
 #define CONFIG_BOOTDELAY      5		    /* 5 second autoboot */
 
 #define CONFIG_LOADS_ECHO     1		     /* echo on for serial dnld */
-#define CFG_LOADS_BAUD_CHANGE 1		     /* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1		     /* allow baudrate change	*/
 
 /*-----------------------------------------------------------------------
  * Networking
  *----------------------------------------------------------------------*/
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII	      1		     /* MII PHY management	*/
 #define CONFIG_NET_MULTI      1
 #define CONFIG_PHY_ADDR	      0xff	     /* no phy on EMAC0		*/
@@ -175,7 +176,7 @@
 #define CONFIG_NETMASK	      255.255.0.0
 #define CONFIG_ETHADDR	      00:00:00:00:00:00 /* No EMAC 0 support	*/
 #define CONFIG_ETH1ADDR	      00:00:00:00:00:00 /* No EMAC 1 support	*/
-#define CFG_RX_ETH_BUFFER     32	     /* #eth rx buff & descrs	*/
+#define CONFIG_SYS_RX_ETH_BUFFER     32	     /* #eth rx buff & descrs	*/
 
 
 /*
@@ -212,33 +213,33 @@
 
 /* Include auto complete with tabs */
 #define CONFIG_AUTO_COMPLETE 1
-#define CFG_ALT_MEMTEST	     1	     /* use real memory test	 */
+#define CONFIG_SYS_ALT_MEMTEST	     1	     /* use real memory test	 */
 
-#define CFG_LONGHELP			     /* undef to save memory	*/
-#define CFG_PROMPT	      "KaRefDes=> "  /* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			     /* undef to save memory	*/
+#define CONFIG_SYS_PROMPT	      "KaRefDes=> "  /* Monitor Command Prompt	*/
 
-#define CFG_HUSH_PARSER	       1	     /* HUSH for ext'd cli	*/
-#define CFG_PROMPT_HUSH_PS2    "> "
+#define CONFIG_SYS_HUSH_PARSER	       1	     /* HUSH for ext'd cli	*/
+#define CONFIG_SYS_PROMPT_HUSH_PS2    "> "
 
 
 /*-----------------------------------------------------------------------
  * Console Buffer
  *----------------------------------------------------------------------*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	      1024	     /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	      1024	     /* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE	      256	     /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	      256	     /* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 					     /* Print Buffer Size	*/
-#define CFG_MAXARGS	      16	     /* max number of cmd args	*/
-#define CFG_BARGSIZE	      CFG_CBSIZE     /* Boot Arg Buffer Size	*/
+#define CONFIG_SYS_MAXARGS	      16	     /* max number of cmd args	*/
+#define CONFIG_SYS_BARGSIZE	      CONFIG_SYS_CBSIZE     /* Boot Arg Buffer Size	*/
 
 /*-----------------------------------------------------------------------
  * Memory Test
  *----------------------------------------------------------------------*/
-#define CFG_MEMTEST_START     0x0400000	     /* memtest works on	*/
-#define CFG_MEMTEST_END	      0x0C00000	     /* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START     0x0400000	     /* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END	      0x0C00000	     /* 4 ... 12 MB in DRAM	*/
 
 /*-----------------------------------------------------------------------
  * Compact Flash (in true IDE mode)
@@ -247,16 +248,16 @@
 #undef	CONFIG_IDE_LED			/* no led for ide supported	*/
 
 #define CONFIG_IDE_RESET		/* reset for ide supported	*/
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR	0xF0000000
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#define CFG_ATA_DATA_OFFSET	0x0000	 /* Offset for data I/O */
-#define CFG_ATA_REG_OFFSET	0x0000	 /* Offset for normal register accesses*/
-#define CFG_ATA_ALT_OFFSET	0x100000 /* Offset for alternate registers */
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0000000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	 /* Offset for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	 /* Offset for normal register accesses*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x100000 /* Offset for alternate registers */
 
-#define CFG_ATA_STRIDE		2	 /* Directly connected CF, needs a stride
+#define CONFIG_SYS_ATA_STRIDE		2	 /* Directly connected CF, needs a stride
 					    to get to the correct offset */
 #define CONFIG_DOS_PARTITION  1		     /* Include dos partition	*/
 
@@ -267,20 +268,20 @@
 #define CONFIG_PCI			     /* include pci support	*/
 #define CONFIG_PCI_PNP			     /* do pci plug-and-play	*/
 #define CONFIG_PCI_SCAN_SHOW		     /* show pci devices	*/
-#define CFG_PCI_TARGBASE      (CFG_PCI_MEMBASE)
+#define CONFIG_SYS_PCI_TARGBASE      (CONFIG_SYS_PCI_MEMBASE)
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT		     /* let board init pci target*/
+#define CONFIG_SYS_PCI_TARGET_INIT		     /* let board init pci target*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x17BA	     /* Sandburst */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	     /* Whatever */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA	     /* Sandburst */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	     /* Whatever */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*
  * Internal Definitions
@@ -299,10 +300,10 @@
  * Miscellaneous configurable options
  *----------------------------------------------------------------------*/
 #undef CONFIG_WATCHDOG			     /* watchdog disabled	*/
-#define CFG_LOAD_ADDR	      0x8000000	     /* default load address	*/
-#define CFG_EXTBDINFO	      1		     /* use extended board_info */
+#define CONFIG_SYS_LOAD_ADDR	      0x8000000	     /* default load address	*/
+#define CONFIG_SYS_EXTBDINFO	      1		     /* use extended board_info */
 
-#define CFG_HZ		      100	     /* decr freq: 1 ms ticks	*/
+#define CONFIG_SYS_HZ		      100	     /* decr freq: 1 ms ticks	*/
 
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h
index 6f99c1b..a829984 100644
--- a/include/configs/KUP4K.h
+++ b/include/configs/KUP4K.h
@@ -81,7 +81,7 @@
 #define CONFIG_MISC_INIT_F	1
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #define	CONFIG_WATCHDOG	1		/* watchdog enabled		*/
 
@@ -109,8 +109,8 @@
 #undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/
 
-#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
-#define CFG_I2C_SLAVE		0xFE
+#define CONFIG_SYS_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CONFIG_SYS_I2C_SLAVE		0xFE
 
 #ifdef CONFIG_SOFT_I2C
 /*
@@ -135,20 +135,20 @@
  * I2C Configuration
  */
 
-#define CFG_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander			*/
-#define CFG_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/
+#define CONFIG_SYS_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander			*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/
 
 
 /* List of I2C addresses to be verified by POST */
 
-#define I2C_ADDR_LIST	{CFG_I2C_PICIO_ADDR,	\
-			CFG_I2C_RTC_ADDR,	\
+#define I2C_ADDR_LIST	{CONFIG_SYS_I2C_PICIO_ADDR,	\
+			CONFIG_SYS_I2C_RTC_ADDR,	\
 			}
 
 
 #define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
 
-#define CFG_DISCOVER_PHY
+#define CONFIG_SYS_DISCOVER_PHY
 #define CONFIG_MII
 
 #if 0
@@ -161,9 +161,9 @@
 #if 1
 /* POST support */
 
-#define CONFIG_POST		(CFG_POST_CPU	   | \
-				 CFG_POST_RTC	   | \
-				 CFG_POST_I2C)
+#define CONFIG_POST		(CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_RTC	   | \
+				 CONFIG_SYS_POST_I2C)
 #endif
 
 
@@ -186,27 +186,27 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x000400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x002C00000	/* 4 ... 44 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x000400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x002C00000	/* 4 ... 44 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x200000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 115200 }
 
-#define CFG_CONSOLE_INFO_QUIET 1
+#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
 
 /*
  * Low Level Configuration Settings
@@ -216,43 +216,43 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	19	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	19	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
@@ -268,16 +268,16 @@
  * Hardware Information Block
  */
 #if 1
-#define CFG_HWINFO_OFFSET	0x000F0000	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000100	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x4B26500D	/* 'K&P<CR>' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x000F0000	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000100	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x4B26500D	/* 'K&P<CR>' */
 #endif
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -287,10 +287,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if 0 && defined(CONFIG_WATCHDOG)       /* KUP uses external TPS3705 WD */
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -298,27 +298,27 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -328,7 +328,7 @@
  *
  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  */
-#define CFG_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+#define CONFIG_SYS_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -337,7 +337,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF00
-#define CFG_SCCR	(SCCR_TBS | SCCR_EBDF01 |  \
+#define CONFIG_SYS_SCCR	(SCCR_TBS | SCCR_EBDF01 |  \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -351,14 +351,14 @@
 /* KUP4K use both slots, SLOT_A as "primary". */
 #define CONFIG_PCMCIA_SLOT_A 1
 
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 #define PCMCIA_SOCKETS_NO 2
 #define PCMCIA_MEM_WIN_NO 8
@@ -373,23 +373,23 @@
 #define CONFIG_IDE_LED		1	/* LED	 for ide supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		2
-#define CFG_IDE_MAXDEVICE	4
+#define CONFIG_SYS_IDE_MAXBUS		2
+#define CONFIG_SYS_IDE_MAXDEVICE	4
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_IDE1_OFFSET	(4 * CFG_PCMCIA_MEM_SIZE)
+#define CONFIG_SYS_ATA_IDE1_OFFSET	(4 * CONFIG_SYS_PCMCIA_MEM_SIZE)
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 
 /*-----------------------------------------------------------------------
@@ -397,7 +397,7 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER 0
+#define CONFIG_SYS_DER 0
 
 /*
  * Init Memory Controller:
@@ -410,22 +410,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
 
 /*
@@ -455,11 +455,11 @@
  * 80 Mhz => 80.000.000 / Divider = 156
  */
 #if   defined(CONFIG_80MHz)
-#define CFG_MAMR_PTA		156
+#define CONFIG_SYS_MAMR_PTA		156
 #elif defined(CONFIG_66MHz)
-#define CFG_MAMR_PTA		129
+#define CONFIG_SYS_MAMR_PTA		129
 #else		/*   50 MHz */
-#define CFG_MAMR_PTA		 98
+#define CONFIG_SYS_MAMR_PTA		 98
 #endif	/*CONFIG_??MHz */
 
 /*
@@ -467,15 +467,15 @@
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR 0x400
+#define CONFIG_SYS_MPTPR 0x400
 
 /*
  * MAMR settings for SDRAM
  */
-#define CFG_MAMR 0x80802114
+#define CONFIG_SYS_MAMR 0x80802114
 
 /*
  * Internal Definitions
diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h
index a71be0f..be6dfda 100644
--- a/include/configs/KUP4X.h
+++ b/include/configs/KUP4X.h
@@ -50,11 +50,11 @@
 
 #define CONFIG_BOARD_TYPES	1	/* support board types			*/
 
-#define CFG_8XX_FACT		8	/* Multiply by 8			*/
-#define CFG_8XX_XIN		16000000	/* 16 MHz in			*/
+#define CONFIG_SYS_8XX_FACT		8	/* Multiply by 8			*/
+#define CONFIG_SYS_8XX_XIN		16000000	/* 16 MHz in			*/
 
 
-#define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT))
+#define MPC8XX_HZ ((CONFIG_SYS_8XX_XIN) * (CONFIG_SYS_8XX_FACT))
 
 /* should ALWAYS define this, measure_gclk in speed.c is unreliable */
 /* in general, we always know this for FADS+new ADS anyway */
@@ -91,7 +91,7 @@
 #define CONFIG_MISC_INIT_F	1
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/
 
@@ -118,8 +118,8 @@
 #undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/
 
-#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
-#define CFG_I2C_SLAVE		0xFE
+#define CONFIG_SYS_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CONFIG_SYS_I2C_SLAVE		0xFE
 
 #ifdef CONFIG_SOFT_I2C
 /*
@@ -144,20 +144,20 @@
  * I2C Configuration
  */
 
-#define CFG_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander			*/
-#define CFG_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/
+#define CONFIG_SYS_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander			*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/
 
 
 /* List of I2C addresses to be verified by POST */
 
-#define I2C_ADDR_LIST	{CFG_I2C_PICIO_ADDR,	\
-			CFG_I2C_RTC_ADDR,	\
+#define I2C_ADDR_LIST	{CONFIG_SYS_I2C_PICIO_ADDR,	\
+			CONFIG_SYS_I2C_RTC_ADDR,	\
 			}
 
 
 #define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
 
-#define CFG_DISCOVER_PHY
+#define CONFIG_SYS_DISCOVER_PHY
 #define CONFIG_MII
 
 #if 0
@@ -172,9 +172,9 @@
 #if 1
 /* POST support */
 
-#define CONFIG_POST		(CFG_POST_CPU	   | \
-				 CFG_POST_RTC	   | \
-				 CFG_POST_I2C)
+#define CONFIG_POST		(CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_RTC	   | \
+				 CONFIG_SYS_POST_I2C)
 #endif
 
 
@@ -199,26 +199,26 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x000400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x003C00000	/* 4 ... 60 MB in DRAM	*/
-#define CFG_LOAD_ADDR		0x200000	/* default load address */
+#define CONFIG_SYS_MEMTEST_START	0x000400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x003C00000	/* 4 ... 60 MB in DRAM	*/
+#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 115200 }
 
-#define CFG_CONSOLE_INFO_QUIET 1
+#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
 
 /*
  * Low Level Configuration Settings
@@ -228,43 +228,43 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	19	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	19	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
@@ -280,16 +280,16 @@
  * Hardware Information Block
  */
 #if 1
-#define CFG_HWINFO_OFFSET	0x000F0000	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000100	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x4B26500D	/* 'K&P<CR>' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x000F0000	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000100	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x4B26500D	/* 'K&P<CR>' */
 #endif
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -299,10 +299,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if 0 && defined(CONFIG_WATCHDOG)       /* KUP uses external TPS3705 WD */
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -310,14 +310,14 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 
 /*-----------------------------------------------------------------------
@@ -325,7 +325,7 @@
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 
 /*-----------------------------------------------------------------------
@@ -333,7 +333,7 @@
  *-----------------------------------------------------------------------
  * set the PLL, the low-power modes and the reset control (15-29)
  */
-#define CFG_PLPRCR	((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) |	\
+#define CONFIG_SYS_PLPRCR	((CONFIG_SYS_8XX_FACT << PLPRCR_MFI_SHIFT) |	\
 				PLPRCR_SPLSS | PLPRCR_TEXPS)
 
 
@@ -344,7 +344,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF00
-#define CFG_SCCR	(SCCR_TBS | SCCR_EBDF01 |  \
+#define CONFIG_SYS_SCCR	(SCCR_TBS | SCCR_EBDF01 |  \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -358,14 +358,14 @@
 /* KUP4K use both slots, SLOT_A as "primary". */
 #define CONFIG_PCMCIA_SLOT_A 1
 
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 #define PCMCIA_SOCKETS_NO 1
 #define PCMCIA_MEM_WIN_NO 8
@@ -380,23 +380,23 @@
 #define CONFIG_IDE_LED			1   /* LED   for ide supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1
-#define CFG_IDE_MAXDEVICE	2
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	2
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_IDE1_OFFSET	(4 * CFG_PCMCIA_MEM_SIZE)
+#define CONFIG_SYS_ATA_IDE1_OFFSET	(4 * CONFIG_SYS_PCMCIA_MEM_SIZE)
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 
 /*-----------------------------------------------------------------------
@@ -404,7 +404,7 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER 0
+#define CONFIG_SYS_DER 0
 
 /*
  * Init Memory Controller:
@@ -417,30 +417,30 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
 
-#define CFG_MPTPR 0x400
+#define CONFIG_SYS_MPTPR 0x400
 
 /*
  * MAMR settings for SDRAM
  */
-#define CFG_MAMR 0x80802114
+#define CONFIG_SYS_MAMR 0x80802114
 
 
 /*
diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h
index 8b7b1e1..f14d945 100644
--- a/include/configs/LANTEC.h
+++ b/include/configs/LANTEC.h
@@ -68,7 +68,7 @@
 	"setenv bootargs root=/dev/ram panic=5;bootm 40040000 400A0000"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -119,25 +119,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -147,43 +147,43 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
@@ -192,9 +192,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -204,10 +204,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -215,7 +215,7 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_DLK)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_DLK)
 
 /*-----------------------------------------------------------------------
  * Clock Setting - Has the Lantec board a 32kHz clock ??? [XXX]
@@ -228,20 +228,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -252,7 +252,7 @@
  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  */
 			/* up to 50 MHz we use a 1:1 clock */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -262,7 +262,7 @@
  */
 #define SCCR_MASK	SCCR_EBDF11
 			/* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -272,7 +272,7 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -287,20 +287,20 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /* FLASH timing */
-#define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_BI | \
 				 OR_SCY_5_CLK | OR_TRLX)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR5_REMAP   CFG_OR0_REMAP
-#define CFG_OR5_PRELIM  CFG_OR0_PRELIM
-#define CFG_BR5_PRELIM  ((FLASH_BASE5_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR5_REMAP   CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR5_PRELIM  CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR5_PRELIM  ((FLASH_BASE5_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -310,32 +310,32 @@
 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 
 /* SDRAM timing: Multiplexed addresses					*/
-#define CFG_OR_TIMING_SDRAM     (OR_CSNT_SAM)
+#define CONFIG_SYS_OR_TIMING_SDRAM     (OR_CSNT_SAM)
 
-#define CFG_OR3_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR3_PRELIM  (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /*
  * Memory Periodic Timer Prescaler
  */
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL \
-			((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |	\
+#define CONFIG_SYS_MAMR_8COL \
+			((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index 7f24c4e..5d5966f 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -39,9 +39,9 @@
 #define CONFIG_M52277EVB	/* M52277EVB board */
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
-#define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef CONFIG_WATCHDOG
 
@@ -72,21 +72,50 @@
 #define CONFIG_CMD_REGINFO
 #undef CONFIG_CMD_USB
 #undef CONFIG_CMD_BMP
-
-#define CONFIG_HOSTNAME		M52277EVB
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+
+#define CONFIG_HOSTNAME			M52277EVB
+#define CONFIG_SYS_UBOOT_END		0x3FFFF
+#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
+#ifdef CONFIG_SYS_STMICRO_BOOT
+/* ST Micro serial flash */
 #define CONFIG_EXTRA_ENV_SETTINGS		\
-	"inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0"	\
-	"loadaddr=" MK_STR(CFG_LOAD_ADDR) "\0"	\
-	"u-boot=u-boot.bin\0"			\
-	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=loadb ${loadaddr} ${baudrate};"	\
+	"loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
 	"upd=run load; run prog\0"		\
-	"prog=prot off 0 0x3ffff;"		\
-	"era 0 3ffff;"				\
-	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"prog=sf probe 0:2 10000 1;"		\
+	"sf erase 0 30000;"			\
+	"sf write ${loadaddr} 0 30000;"		\
 	"save\0"				\
 	""
+#endif
+#ifdef CONFIG_SYS_SPANSION_BOOT
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=loadb ${loadaddr} ${baudrate}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off " MK_STR(CONFIG_SYS_FLASH_BASE)	\
+	" " MK_STR(CONFIG_SYS_UBOOT_END) ";"		\
+	"era " MK_STR(CONFIG_SYS_FLASH_BASE) " "	\
+	MK_STR(CONFIG_SYS_UBOOT_END) ";"		\
+	"cp.b ${loadaddr} " MK_STR(CONFIG_SYS_FLASH_BASE)	\
+	" ${filesize}; save\0"			\
+	"updsbf=run loadsbf; run progsbf\0"	\
+	"loadsbf=loadb ${loadaddr} ${baudrate};"	\
+	"loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
+	"progsbf=sf probe 0:2 10000 1;"		\
+	"sf erase 0 30000;"			\
+	"sf write ${loadaddr} 0 30000;"		\
+	""
+#endif
 
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */
+#define CONFIG_BOOTDELAY		3	/* autoboot after 3 seconds */
 /* LCD */
 #ifdef CONFIG_CMD_BMP
 #define CONFIG_LCD
@@ -102,14 +131,14 @@
 #define CONFIG_DOS_PARTITION
 #define CONFIG_MAC_PARTITION
 #define CONFIG_ISO_PARTITION
-#define CFG_USB_EHCI_REGS_BASE		0xFC0B0000
-#define CFG_USB_EHCI_CPU_INIT
+#define CONFIG_SYS_USB_EHCI_REGS_BASE	0xFC0B0000
+#define CONFIG_SYS_USB_EHCI_CPU_INIT
 #endif
 
 /* Realtime clock */
 #define CONFIG_MCFRTC
 #undef RTC_DEBUG
-#define CFG_RTC_OSCILLATOR	(32 * CFG_HZ)
+#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)
 
 /* Timer */
 #define CONFIG_MCFTMR
@@ -119,35 +148,58 @@
 #define CONFIG_FSL_I2C
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged               */
-#define CFG_I2C_SPEED		80000	/* I2C speed and slave address  */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_OFFSET		0x58000
-#define CFG_IMMR		CFG_MBAR
+#define CONFIG_SYS_I2C_SPEED		80000	/* I2C speed and slave address  */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x58000
+#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
+
+/* DSPI and Serial Flash */
+#define CONFIG_CF_DSPI
+#define CONFIG_HARD_SPI
+#define CONFIG_SYS_SER_FLASH_BASE	0x01000000
+#define CONFIG_SYS_SBFHDR_SIZE		0x7
+#ifdef CONFIG_CMD_SPI
+#	define CONFIG_SYS_DSPI_CS2
+#	define CONFIG_SPI_FLASH
+#	define CONFIG_SPI_FLASH_STMICRO
+
+#	define CONFIG_SYS_DSPI_DCTAR0	(DSPI_DCTAR_TRSZ(7) | \
+					 DSPI_DCTAR_CPOL | \
+					 DSPI_DCTAR_CPHA | \
+					 DSPI_DCTAR_PCSSCK_1CLK | \
+					 DSPI_DCTAR_PASC(0) | \
+					 DSPI_DCTAR_PDT(0) | \
+					 DSPI_DCTAR_CSSCK(0) | \
+					 DSPI_DCTAR_ASC(0) | \
+					 DSPI_DCTAR_PBR(0) | \
+					 DSPI_DCTAR_DT(1) | \
+					 DSPI_DCTAR_BR(1))
+#endif
 
 /* Input, PCI, Flexbus, and VCO */
 #define CONFIG_EXTRA_CLOCK
 
-#define CFG_INPUT_CLKSRC	16000000
+#define CONFIG_SYS_INPUT_CLKSRC	16000000
 
-#define CONFIG_PRAM		512	/* 512 KB */
+#define CONFIG_PRAM		2048	/* 2048 KB */
 
-#define CFG_PROMPT		"-> "
-#define CFG_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 
-#define CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 0x10000)
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x10000)
 
-#define CFG_HZ			1000
+#define CONFIG_SYS_HZ		1000
 
-#define CFG_MBAR		0xFC000000
+#define CONFIG_SYS_MBAR		0xFC000000
 
 /*
  * Low Level Configuration Settings
@@ -155,65 +207,88 @@
  * You should know what you are doing if you make changes here.
  */
 
-/*-----------------------------------------------------------------------
+/*
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x80000000
-#define CFG_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
-#define CFG_INIT_RAM_CTRL	0x21
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_END		0x8000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 32)
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - 32)
 
-/*-----------------------------------------------------------------------
+/*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x40000000
-#define CFG_SDRAM_SIZE		64	/* SDRAM size in MB */
-#define CFG_SDRAM_CFG1		0x43711630
-#define CFG_SDRAM_CFG2		0x56670000
-#define CFG_SDRAM_CTRL		0xE1092000
-#define CFG_SDRAM_EMOD		0x81810000
-#define CFG_SDRAM_MODE		0x00CD0000
-
-#define CFG_MEMTEST_START	CFG_SDRAM_BASE + 0x400
-#define CFG_MEMTEST_END		((CFG_SDRAM_SIZE - 3) << 20)
-
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
-#define CFG_BOOTPARAMS_LEN	64*1024
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x43711630
+#define CONFIG_SYS_SDRAM_CFG2		0x56670000
+#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
+#define CONFIG_SYS_SDRAM_EMOD		0x81810000
+#define CONFIG_SYS_SDRAM_MODE		0x00CD0000
+#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x00
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#ifdef CONFIG_CF_SBF
+#	define CONFIG_SYS_MONITOR_BASE	(TEXT_BASE + 0x400)
+#else
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
 
 /* Initial Memory map for Linux */
-#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 
-/* Configuration for environment
+/*
+ * Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
  */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OVERWRITE	1
+#ifdef CONFIG_CF_SBF
+#	define CONFIG_ENV_IS_IN_SPI_FLASH
+#	define CONFIG_ENV_SPI_CS	2
+#else
+#	define CONFIG_ENV_IS_IN_FLASH	1
+#endif
+#define CONFIG_ENV_OVERWRITE		1
 #undef CONFIG_ENV_IS_EMBEDDED
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_FLASH_BASE		CFG_CS0_BASE
-#define CFG_FLASH0_BASE		CFG_CS0_BASE
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x8000)
-#define CONFIG_ENV_SECT_SIZE	0x8000
-
-#define CFG_FLASH_CFI
-#ifdef CFG_FLASH_CFI
+#ifdef CONFIG_SYS_STMICRO_BOOT
+#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_SER_FLASH_BASE
+#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_SER_FLASH_BASE
+#	define CONFIG_SYS_FLASH1_BASE	CONFIG_SYS_CS0_BASE
+#	define CONFIG_ENV_OFFSET	0x30000
+#	define CONFIG_ENV_SIZE		0x1000
+#	define CONFIG_ENV_SECT_SIZE	0x10000
+#endif
+#ifdef CONFIG_SYS_SPANSION_BOOT
+#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_CS0_BASE
+#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x8000)
+#	define CONFIG_ENV_SIZE		0x1000
+#	define CONFIG_ENV_SECT_SIZE	0x8000
+#endif
 
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
 #	define CONFIG_FLASH_CFI_DRIVER	1
-#	define CFG_FLASH_SIZE		0x1000000	/* Max size that the board might have */
-#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#	define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#	define CFG_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
-#	define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
-#	define CFG_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
 #endif
 
 /*
@@ -223,13 +298,13 @@
 #ifdef CONFIG_CMD_JFFS2
 #	define CONFIG_JFFS2_DEV		"nor0"
 #	define CONFIG_JFFS2_PART_SIZE	(0x01000000 - 0x40000)
-#	define CONFIG_JFFS2_PART_OFFSET	(CFG_FLASH0_BASE + 0x40000)
+#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x40000)
 #endif
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE		16
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /*-----------------------------------------------------------------------
  * Memory bank definitions
@@ -243,8 +318,14 @@
  * CS5 - Available
  */
 
-#define CFG_CS0_BASE		0x00000000
-#define CFG_CS0_MASK		0x00FF0001
-#define CFG_CS0_CTRL		0x00001FA0
+#ifdef CONFIG_CF_SBF
+#define CONFIG_SYS_CS0_BASE		0x04000000
+#define CONFIG_SYS_CS0_MASK		0x00FF0001
+#define CONFIG_SYS_CS0_CTRL		0x00001FA0
+#else
+#define CONFIG_SYS_CS0_BASE		0x00000000
+#define CONFIG_SYS_CS0_MASK		0x00FF0001
+#define CONFIG_SYS_CS0_CTRL		0x00001FA0
+#endif
 
 #endif				/* _M52277EVB_H */
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index f352db1..8c66f87 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -38,9 +38,9 @@
 #define CONFIG_M5235		/* define processor type */
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef CONFIG_WATCHDOG
 #define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
@@ -78,22 +78,22 @@
 #	define CONFIG_NET_MULTI		1
 #	define CONFIG_MII		1
 #	define CONFIG_MII_INIT		1
-#	define CFG_DISCOVER_PHY
-#	define CFG_RX_ETH_BUFFER	8
-#	define CFG_FAULT_ECHO_LINK_DOWN
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 
-#	define CFG_FEC0_PINMUX		0
-#	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
 #	define MCFFEC_TOUT_LOOP		50000
-/* If CFG_DISCOVER_PHY is not defined - hardcoded */
-#	ifndef CFG_DISCOVER_PHY
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
 #		define FECDUPLEX	FULL
 #		define FECSPEED		_100BASET
 #	else
-#		ifndef CFG_FAULT_ECHO_LINK_DOWN
-#			define CFG_FAULT_ECHO_LINK_DOWN
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #		endif
-#	endif			/* CFG_DISCOVER_PHY */
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
 #endif
 
 /* Timer */
@@ -104,13 +104,13 @@
 #define CONFIG_FSL_I2C
 #define CONFIG_HARD_I2C		/* I2C with hw support */
 #undef CONFIG_SOFT_I2C		/* I2C bit-banged */
-#define CFG_I2C_SPEED		80000
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_OFFSET		0x00000300
-#define CFG_IMMR		CFG_MBAR
-#define CFG_I2C_PINMUX_REG	(gpio->par_qspi)
-#define CFG_I2C_PINMUX_CLR	~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
-#define CFG_I2C_PINMUX_SET	(GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
+#define CONFIG_SYS_I2C_SPEED		80000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x00000300
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+#define CONFIG_SYS_I2C_PINMUX_REG	(gpio->par_qspi)
+#define CONFIG_SYS_I2C_PINMUX_CLR	~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
+#define CONFIG_SYS_I2C_PINMUX_SET	(GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
@@ -138,25 +138,25 @@
 	""
 
 #define CONFIG_PRAM		512	/* 512 KB */
-#define CFG_PROMPT		"-> "
-#define CFG_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
 
 #if defined(CONFIG_KGDB)
-#	define CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#	define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 #else
-#	define CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#	define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
-#define CFG_LOAD_ADDR		(CFG_SDRAM_BASE+0x20000)
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE+0x20000)
 
-#define CFG_HZ			1000
-#define CFG_CLK			75000000
-#define CFG_CPU_CLK		CFG_CLK * 2
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CLK			75000000
+#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2
 
-#define CFG_MBAR		0x40000000
+#define CONFIG_SYS_MBAR		0x40000000
 
 /*
  * Low Level Configuration Settings
@@ -166,29 +166,29 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x20000000
-#define CFG_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
-#define CFG_INIT_RAM_CTRL	0x21
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE - 0x10)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x21
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_SIZE		16	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
 
-#define CFG_MEMTEST_START	CFG_SDRAM_BASE + 0x400
-#define CFG_MEMTEST_END		((CFG_SDRAM_SIZE - 3) << 20)
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
 
-#define CFG_BOOTPARAMS_LEN	64*1024
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
 
 /*
  * For booting Linux, the board info and command line data
@@ -196,26 +196,26 @@
  * the maximum mapped by the Linux kernel during initialization ??
  */
 /* Initial Memory map for Linux */
-#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_FLASH_CFI
-#ifdef CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
 #	define CONFIG_FLASH_CFI_DRIVER	1
-#	define CFG_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
 #ifdef NORFLASH_PS32BIT
-#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
 #else
-#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 #endif
-#	define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#	define CFG_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
-#	define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
 #endif
 
-#define CFG_FLASH_BASE		(CFG_CS0_BASE << 16)
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
@@ -235,7 +235,7 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
@@ -251,13 +251,13 @@
  * CS7 - Available
  */
 #ifdef NORFLASH_PS32BIT
-#	define CFG_CS0_BASE	0xFFC0
-#	define CFG_CS0_MASK	0x003f0001
-#	define CFG_CS0_CTRL	0x1D00
+#	define CONFIG_SYS_CS0_BASE	0xFFC00000
+#	define CONFIG_SYS_CS0_MASK	0x003f0001
+#	define CONFIG_SYS_CS0_CTRL	0x00001D00
 #else
-#	define CFG_CS0_BASE	0xFFE0
-#	define CFG_CS0_MASK	0x001f0001
-#	define CFG_CS0_CTRL	0x1D80
+#	define CONFIG_SYS_CS0_BASE	0xFFE00000
+#	define CONFIG_SYS_CS0_MASK	0x001f0001
+#	define CONFIG_SYS_CS0_CTRL	0x00001D80
 #endif
 
 #endif				/* _M5329EVB_H */
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index 4525e2d..e3830e5 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -40,9 +40,9 @@
 #define CONFIG_MCFTMR
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef  CONFIG_WATCHDOG
 
@@ -62,38 +62,38 @@
 #include <config_cmd_default.h>
 #undef CONFIG_CMD_NET
 
-#define CFG_PROMPT		"=> "
-#define CFG_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup	*/
 #define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support	*/
 #define CONFIG_LOOPW		1	/* enable loopw command	*/
 #define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands	*/
 
-#define CFG_LOAD_ADDR		0x200000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
 
-#define CFG_MEMTEST_START	0x400
-#define CFG_MEMTEST_END		0x380000
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
 
-#define CFG_HZ			1000
+#define CONFIG_SYS_HZ			1000
 
 /*
  * Clock configuration: enable only one of the following options
  */
 
-#undef  CFG_PLL_BYPASS				/* bypass PLL for test purpose */
-#define CFG_FAST_CLK		1		/* MCF5249 can run at 140MHz   */
-#define	CFG_CLK			132025600	/* MCF5249 can run at 140MHz   */
+#undef  CONFIG_SYS_PLL_BYPASS				/* bypass PLL for test purpose */
+#define CONFIG_SYS_FAST_CLK		1		/* MCF5249 can run at 140MHz   */
+#define	CONFIG_SYS_CLK			132025600	/* MCF5249 can run at 140MHz   */
 
 /*
  * Low Level Configuration Settings
@@ -101,17 +101,17 @@
  * You should know what you are doing if you make changes here.
  */
 
-#define CFG_MBAR		0x10000000	/* Register Base Addrs */
-#define	CFG_MBAR2		0x80000000
+#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+#define	CONFIG_SYS_MBAR2		0x80000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x20000000
-#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
-#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x4000	/* Address of Environment Sector*/
@@ -121,74 +121,74 @@
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_SIZE		16		/* SDRAM size in MB */
-#define CFG_FLASH_BASE		(CFG_CSAR0 << 16)
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
 
 #if 0 /* test-only */
 #define CONFIG_PRAM		512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
 #endif
 
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
 
-#define CFG_MONITOR_LEN		0x20000
-#define CFG_MALLOC_LEN		(1 * 1024*1024)	/* Reserve 1 MB for malloc()	*/
-#define CFG_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024*1024)	/* Reserve 1 MB for malloc()	*/
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_FLASH_CFI
-#ifdef CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
 
 #	define CONFIG_FLASH_CFI_DRIVER	1
-#	define CFG_FLASH_SIZE		0x1000000	/* Max size that the board might have */
-#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#	define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#	define CFG_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
-#	define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
-#	define CFG_FLASH_CHECKSUM
-#	define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 #endif
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
 
 /* CS0 - AMD Flash, address 0xffc00000 */
-#define	CFG_CSAR0		0xffe0
-#define	CFG_CSCR0		0x1980		/* WS=0110, AA=1, PS=10         */
+#define	CONFIG_SYS_CS0_BASE		0xffe00000
+#define	CONFIG_SYS_CS0_CTRL		0x00001980	/* WS=0110, AA=1, PS=10         */
 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
-#define	CFG_CSMR0		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
+#define	CONFIG_SYS_CS0_MASK		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
 
 /* CS1 - FPGA, address 0xe0000000 */
-#define	CFG_CSAR1		0xe000
-#define	CFG_CSCR1		0x0d80		/* WS=0011, AA=1, PS=10         */
-#define	CFG_CSMR1		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
+#define	CONFIG_SYS_CS1_BASE		0xe0000000
+#define	CONFIG_SYS_CS1_CTRL		0x00000d80	/* WS=0011, AA=1, PS=10         */
+#define	CONFIG_SYS_CS1_MASK		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
 
 /*-----------------------------------------------------------------------
  * Port configuration
  */
-#define	CFG_GPIO_FUNC		0x00000008	/* Set gpio pins: none          */
-#define	CFG_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54*/
-#define	CFG_GPIO_EN		0x00000008	/* Set gpio output enable       */
-#define	CFG_GPIO1_EN		0x00c70000	/* Set gpio output enable       */
-#define	CFG_GPIO_OUT		0x00000008	/* Set outputs to default state */
-#define	CFG_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
-#define CFG_GPIO1_LED		0x00400000	/* user led                     */
+#define	CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none          */
+#define	CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54*/
+#define	CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable       */
+#define	CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable       */
+#define	CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
+#define	CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
+#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led                     */
 
 #endif	/* M5249 */
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index 8d9bfa3..378e45a 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -31,9 +31,9 @@
 #define CONFIG_MCFTMR
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef CONFIG_WATCHDOG		/* disable watchdog */
 
@@ -47,7 +47,7 @@
 #	define CONFIG_ENV_SECT_SIZE	0x1000
 #	define CONFIG_ENV_IS_IN_FLASH	1
 #else
-#	define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x4000)
+#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
 #	define CONFIG_ENV_SECT_SIZE	0x1000
 #	define CONFIG_ENV_IS_IN_FLASH	1
 #endif
@@ -75,22 +75,22 @@
 #	define CONFIG_ATAPI
 #	undef CONFIG_LBA48
 
-#	define CFG_IDE_MAXBUS		1
-#	define CFG_IDE_MAXDEVICE	2
+#	define CONFIG_SYS_IDE_MAXBUS		1
+#	define CONFIG_SYS_IDE_MAXDEVICE	2
 
-#	define CFG_ATA_BASE_ADDR	(CFG_MBAR2 + 0x800)
-#	define CFG_ATA_IDE0_OFFSET	0
+#	define CONFIG_SYS_ATA_BASE_ADDR	(CONFIG_SYS_MBAR2 + 0x800)
+#	define CONFIG_SYS_ATA_IDE0_OFFSET	0
 
-#	define CFG_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
-#	define CFG_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
-#	define CFG_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
-#	define CFG_ATA_STRIDE		4	/* Interval between registers */
+#	define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
+#	define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
+#	define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
+#	define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers */
 #	define _IO_BASE			0
 #endif
 
 #define CONFIG_DRIVER_DM9000
 #ifdef CONFIG_DRIVER_DM9000
-#	define CONFIG_DM9000_BASE	((CFG_CSAR1 << 16) | 0x300)
+#	define CONFIG_DM9000_BASE	(CONFIG_SYS_CS1_BASE | 0x300)
 #	define DM9000_IO		CONFIG_DM9000_BASE
 #	define DM9000_DATA		(CONFIG_DM9000_BASE + 4)
 #	undef CONFIG_DM9000_DEBUG
@@ -104,7 +104,7 @@
 
 #	define CONFIG_EXTRA_ENV_SETTINGS		\
 		"netdev=eth0\0"				\
-		"inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0"	\
+		"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
 		"loadaddr=10000\0"			\
 		"u-boot=u-boot.bin\0"			\
 		"load=tftp ${loadaddr) ${u-boot}\0"	\
@@ -121,41 +121,41 @@
 /* I2C */
 #define CONFIG_FSL_I2C
 #define CONFIG_HARD_I2C		/* I2C with hw support */
-#define CFG_I2C_SPEED		80000
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_OFFSET		0x00000280
-#define CFG_IMMR		CFG_MBAR
-#define CFG_I2C_PINMUX_REG	(*(u32 *) (CFG_MBAR+0x19C))
-#define CFG_I2C_PINMUX_CLR	(0xFFFFE7FF)
-#define CFG_I2C_PINMUX_SET	(0)
+#define CONFIG_SYS_I2C_SPEED		80000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x00000280
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+#define CONFIG_SYS_I2C_PINMUX_REG	(*(u32 *) (CONFIG_SYS_MBAR+0x19C))
+#define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFFFE7FF)
+#define CONFIG_SYS_I2C_PINMUX_SET	(0)
 
-#define CFG_PROMPT		"=> "
-#define CFG_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
 
 #if defined(CONFIG_CMD_KGDB)
-#	define CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#	define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 #else
-#	define CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#	define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
-#define CFG_LOAD_ADDR		0x00100000
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
 
-#define CFG_MEMTEST_START	0x400
-#define CFG_MEMTEST_END		0x380000
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
 
-#define CFG_HZ			1000
+#define CONFIG_SYS_HZ			1000
 
-#undef CFG_PLL_BYPASS		/* bypass PLL for test purpose */
-#define CFG_FAST_CLK
-#ifdef CFG_FAST_CLK
-#	define CFG_PLLCR	0x1243E054
-#	define CFG_CLK		140000000
+#undef CONFIG_SYS_PLL_BYPASS		/* bypass PLL for test purpose */
+#define CONFIG_SYS_FAST_CLK
+#ifdef CONFIG_SYS_FAST_CLK
+#	define CONFIG_SYS_PLLCR	0x1243E054
+#	define CONFIG_SYS_CLK		140000000
 #else
-#	define CFG_PLLCR	0x135a4140
-#	define CFG_CLK		70000000
+#	define CONFIG_SYS_PLLCR	0x135a4140
+#	define CONFIG_SYS_CLK		70000000
 #endif
 
 /*
@@ -164,100 +164,92 @@
  * You should know what you are doing if you make changes here.
  */
 
-#define CFG_MBAR		0x10000000	/* Register Base Addrs */
-#define CFG_MBAR2		0x80000000	/* Module Base Addrs 2 */
+#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+#define CONFIG_SYS_MBAR2		0x80000000	/* Module Base Addrs 2 */
 
 /*
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x20000000
-#define CFG_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_SIZE		16	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
 
 #ifdef CONFIG_MONITOR_IS_IN_RAM
-#	define CFG_MONITOR_BASE	0x20000
+#	define CONFIG_SYS_MONITOR_BASE	0x20000
 #else
-#	define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
 #endif
 
-#define CFG_MONITOR_LEN		0x40000
-#define CFG_MALLOC_LEN		(256 << 10)
-#define CFG_BOOTPARAMS_LEN	(64*1024)
+#define CONFIG_SYS_MONITOR_LEN		0x40000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 
 /* FLASH organization */
-#define CFG_FLASH_BASE		(CFG_CSAR0 << 16)
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	2048	/* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT	1000
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	2048	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
 
 #define FLASH_SST6401B		0x200
 #define SST_ID_xF6401B		0x236D236D
 
-#undef CFG_FLASH_CFI
-#ifdef CFG_FLASH_CFI
+#undef CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
 /*
  * Unable to use CFI driver, due to incompatible sector erase command by SST.
  * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
  * 0x30 is block erase in SST
  */
 #	define CONFIG_FLASH_CFI_DRIVER	1
-#	define CFG_FLASH_SIZE		0x800000
-#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_FLASH_SIZE		0x800000
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 #	define CONFIG_FLASH_CFI_LEGACY
 #else
-#	define CFG_SST_SECT		2048
-#	define CFG_SST_SECTSZ		0x1000
-#	define CFG_FLASH_WRITE_TOUT	500
+#	define CONFIG_SYS_SST_SECT		2048
+#	define CONFIG_SYS_SST_SECTSZ		0x1000
+#	define CONFIG_SYS_FLASH_WRITE_TOUT	500
 #endif
 
 /* Cache Configuration */
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /* Port configuration */
-#define CFG_FECI2C		0xF0
+#define CONFIG_SYS_FECI2C		0xF0
 
-#define CFG_CSAR0		0xFF80
-#define CFG_CSMR0		0x007F0021
-#define CFG_CSCR0		0x1D80
+#define CONFIG_SYS_CS0_BASE		0xFF800000
+#define CONFIG_SYS_CS0_MASK		0x007F0021
+#define CONFIG_SYS_CS0_CTRL		0x00001D80
 
-#define CFG_CSAR1               0xE000
-#define CFG_CSMR1               0x00000001
-#define CFG_CSCR1               0x3DD8
-
-#define CFG_CSAR2		0
-#define CFG_CSMR2		0
-#define CFG_CSCR2		0
-
-#define CFG_CSAR3		0
-#define CFG_CSMR3		0
-#define CFG_CSCR3		0
+#define CONFIG_SYS_CS1_BASE		0xE0000000
+#define CONFIG_SYS_CS1_MASK		0x00000001
+#define CONFIG_SYS_CS1_CTRL		0x00003DD8
 
 /*-----------------------------------------------------------------------
  * Port configuration
  */
-#define CFG_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
-#define CFG_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
-#define CFG_GPIO_EN		0x00000008	/* Set gpio output enable */
-#define CFG_GPIO1_EN		0x00c70000	/* Set gpio output enable */
-#define CFG_GPIO_OUT		0x00000008	/* Set outputs to default state */
-#define CFG_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
-#define CFG_GPIO1_LED		0x00400000	/* user led */
+#define CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
+#define CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
+#define CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable */
+#define CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable */
+#define CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
+#define CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
+#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led */
 
 #endif				/* _M5253DEMO_H */
diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
index f58f89c..86de97d 100644
--- a/include/configs/M5253EVBE.h
+++ b/include/configs/M5253EVBE.h
@@ -31,9 +31,9 @@
 #define CONFIG_MCFTMR
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef CONFIG_WATCHDOG		/* disable watchdog */
 
@@ -81,45 +81,45 @@
 #define CONFIG_ATAPI
 #undef CONFIG_LBA48
 
-#define CFG_IDE_MAXBUS		1
-#define CFG_IDE_MAXDEVICE	2
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	2
 
-#define CFG_ATA_BASE_ADDR	(CFG_MBAR2 + 0x800)
-#define CFG_ATA_IDE0_OFFSET	0
+#define CONFIG_SYS_ATA_BASE_ADDR	(CONFIG_SYS_MBAR2 + 0x800)
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0
 
-#define CFG_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
-#define CFG_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
-#define CFG_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
-#define CFG_ATA_STRIDE		4	/* Interval between registers */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
+#define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers */
 #define _IO_BASE		0
 
-#define CFG_PROMPT		"=> "
-#define CFG_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
-#define CFG_LOAD_ADDR		0x00100000
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
 
-#define CFG_MEMTEST_START	0x400
-#define CFG_MEMTEST_END		0x380000
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
 
-#define CFG_HZ			1000
+#define CONFIG_SYS_HZ			1000
 
-#undef CFG_PLL_BYPASS		/* bypass PLL for test purpose */
-#define CFG_FAST_CLK
-#ifdef CFG_FAST_CLK
-#	define CFG_PLLCR	0x1243E054
-#	define CFG_CLK		140000000
+#undef CONFIG_SYS_PLL_BYPASS		/* bypass PLL for test purpose */
+#define CONFIG_SYS_FAST_CLK
+#ifdef CONFIG_SYS_FAST_CLK
+#	define CONFIG_SYS_PLLCR	0x1243E054
+#	define CONFIG_SYS_CLK		140000000
 #else
-#	define CFG_PLLCR	0x135a4140
-#	define CFG_CLK		70000000
+#	define CONFIG_SYS_PLLCR	0x135a4140
+#	define CONFIG_SYS_CLK		70000000
 #endif
 
 /*
@@ -128,85 +128,73 @@
  * You should know what you are doing if you make changes here.
  */
 
-#define CFG_MBAR		0x10000000	/* Register Base Addrs */
-#define CFG_MBAR2		0x80000000	/* Module Base Addrs 2 */
+#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+#define CONFIG_SYS_MBAR2		0x80000000	/* Module Base Addrs 2 */
 
 /*
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x20000000
-#define CFG_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_SIZE		8	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		8	/* SDRAM size in MB */
 
 #ifdef CONFIG_MONITOR_IS_IN_RAM
-#define CFG_MONITOR_BASE	0x20000
+#define CONFIG_SYS_MONITOR_BASE	0x20000
 #else
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
 #endif
 
-#define CFG_MONITOR_LEN		0x40000
-#define CFG_MALLOC_LEN		(256 << 10)
-#define CFG_BOOTPARAMS_LEN	(64*1024)
+#define CONFIG_SYS_MONITOR_LEN		0x40000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 
 /* FLASH organization */
-#define CFG_FLASH_BASE		0xffe00000
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	35	/* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT	1000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	35	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
 
-#define CFG_FLASH_CFI		1
+#define CONFIG_SYS_FLASH_CFI		1
 #define CONFIG_FLASH_CFI_DRIVER	1
-#define CFG_FLASH_SIZE		0x200000
-#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_SIZE		0x200000
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 
 /* Cache Configuration */
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /* Port configuration */
-#define CFG_FECI2C		0xF0
+#define CONFIG_SYS_FECI2C		0xF0
 
-#define CFG_CSAR0		0xFFE0
-#define CFG_CSMR0		0x001F0021
-#define CFG_CSCR0		0x1D80
-
-#define CFG_CSAR1		0
-#define CFG_CSMR1		0
-#define CFG_CSCR1		0
-
-#define CFG_CSAR2		0
-#define CFG_CSMR2		0
-#define CFG_CSCR2		0
-
-#define CFG_CSAR3		0
-#define CFG_CSMR3		0
-#define CFG_CSCR3		0
+#define CONFIG_SYS_CS0_BASE		0xFFE00000
+#define CONFIG_SYS_CS0_MASK		0x001F0021
+#define CONFIG_SYS_CS0_CTRL		0x00001D80
 
 /*-----------------------------------------------------------------------
  * Port configuration
  */
-#define CFG_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
-#define CFG_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
-#define CFG_GPIO_EN		0x00000008	/* Set gpio output enable */
-#define CFG_GPIO1_EN		0x00c70000	/* Set gpio output enable */
-#define CFG_GPIO_OUT		0x00000008	/* Set outputs to default state */
-#define CFG_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
-#define CFG_GPIO1_LED		0x00400000	/* user led */
+#define CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
+#define CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
+#define CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable */
+#define CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable */
+#define CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
+#define CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
+#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led */
 
 #endif				/* _M5253EVB_H */
diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h
index 844b74f..50b3ab2 100644
--- a/include/configs/M5271EVB.h
+++ b/include/configs/M5271EVB.h
@@ -41,9 +41,9 @@
 #define CONFIG_MCFTMR
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef CONFIG_WATCHDOG		/* disable watchdog */
 
@@ -57,7 +57,7 @@
 #endif
 #define CONFIG_ENV_SECT_SIZE	0x2000
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 /*
  * BOOTP options
@@ -82,41 +82,44 @@
 #define CONFIG_CMD_MISC
 
 #undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMDLINE_EDITING	1 /* enables command line history */
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
 #define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC
 #	define CONFIG_NET_MULTI		1
 #	define CONFIG_MII		1
 #	define CONFIG_MII_INIT		1
-#	define CFG_DISCOVER_PHY
-#	define CFG_RX_ETH_BUFFER	8
-#	define CFG_FAULT_ECHO_LINK_DOWN
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 
-#	define CFG_FEC0_PINMUX		0
-#	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
 #	define MCFFEC_TOUT_LOOP		50000
-/* If CFG_DISCOVER_PHY is not defined - hardcoded */
-#	ifndef CFG_DISCOVER_PHY
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
 #		define FECDUPLEX	FULL
 #		define FECSPEED		_100BASET
 #	else
-#		ifndef CFG_FAULT_ECHO_LINK_DOWN
-#			define CFG_FAULT_ECHO_LINK_DOWN
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #		endif
-#	endif			/* CFG_DISCOVER_PHY */
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
 #endif
 
 /* I2C */
 #define CONFIG_FSL_I2C
 #define CONFIG_HARD_I2C		/* I2C with hw support */
 #undef CONFIG_SOFT_I2C		/* I2C bit-banged */
-#define CFG_I2C_SPEED		80000
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_OFFSET		0x00000300
-#define CFG_IMMR		CFG_MBAR
+#define CONFIG_SYS_I2C_SPEED		80000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x00000300
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
 
-#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
+#define CONFIG_BOOTDELAY	1	/* autoboot after 1 seconds */
 #define CONFIG_BOOTFILE		"u-boot.bin"
 #ifdef CONFIG_MCFFEC
 #	define CONFIG_NET_RETRY_COUNT	5
@@ -128,38 +131,48 @@
 #	define CONFIG_OVERWRITE_ETHADDR_ONCE
 #endif				/* FEC_ENET */
 
-#define CONFIG_HOSTNAME		M5235EVB
+#define CONFIG_HOSTNAME		M5271EVB
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"netdev=eth0\0"				\
 	"loadaddr=10000\0"			\
-	"u-boot=u-boot.bin\0"			\
-	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"uboot=u-boot.bin\0"		\
+	"load=tftp $loadaddr $uboot\0"	\
 	"upd=run load; run prog\0"		\
-	"prog=prot off ffe00000 ffe2ffff;"		\
-	"era ffe00000 ffe2ffff;"				\
-	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"prog=prot off ffe00000 ffe3ffff;"	\
+	"era ffe00000 ffe3ffff;"		\
+	"cp.b $loadaddr ffe00000 $filesize;"	\
 	"save\0"				\
 	""
 
-#define CFG_PROMPT		"=> "
-#define CFG_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size      */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size      */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 
-#define CFG_LOAD_ADDR		0x00100000
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
 
-#define CFG_MEMTEST_START	0x400
-#define CFG_MEMTEST_END		0x380000
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
 
-#define CFG_HZ			1000000
-#define CFG_CLK			100000000
+#define CONFIG_SYS_HZ			1000000
+
+/* Clock configuration
+ * The external oscillator is a 25.000 MHz
+ * CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk)
+ * bus_clk = (cpu_clk/2) (fixed ratio)
+ *
+ * If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to
+ * match the new clock speed. Max cpu_clk is 150 MHz.
+ */
+#define CONFIG_SYS_CLK			100000000
+#define CONFIG_SYS_MCF_SYNCR 	(MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1)
 
 /*
  * Low Level Configuration Settings
@@ -167,56 +180,63 @@
  * You should know what you are doing if you make changes here.
  */
 
-#define CFG_MBAR		0x40000000	/* Register Base Addrs */
+#define CONFIG_SYS_MBAR		0x40000000	/* Register Base Addrs */
 
 /*
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x20000000
-#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM    */
-#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM    */
+#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_SIZE		16	/* SDRAM size in MB */
-#define CFG_FLASH_BASE		0xffe00000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
+#define CONFIG_SYS_FLASH_BASE		0xffe00000
 
 #ifdef	CONFIG_MONITOR_IS_IN_RAM
-#define CFG_MONITOR_BASE	0x20000
+#define CONFIG_SYS_MONITOR_BASE	0x20000
 #else
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
 #endif
 
-#define CFG_MONITOR_LEN		0x40000
-#define CFG_MALLOC_LEN		(256 << 10)
-#define CFG_BOOTPARAMS_LEN	(64*1024)
+#define CONFIG_SYS_MONITOR_LEN		0x40000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 
 /* FLASH organization */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks           */
-#define CFG_MAX_FLASH_SECT	11	/* max number of sectors on one chip    */
-#define CFG_FLASH_ERASE_TOUT	1000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks           */
+#define CONFIG_SYS_MAX_FLASH_SECT	11	/* max number of sectors on one chip    */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
 
-#define CFG_FLASH_CFI		1
+#define CONFIG_SYS_FLASH_CFI		1
 #define CONFIG_FLASH_CFI_DRIVER	1
-#define CFG_FLASH_SIZE		0x200000
+#define CONFIG_SYS_FLASH_SIZE		0x200000
 
 /* Cache Configuration */
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+/* Chip Select 0  : Boot Flash */
+#define CONFIG_SYS_CS0_BASE	0xFFE00000
+#define CONFIG_SYS_CS0_MASK	0x001F0001
+#define CONFIG_SYS_CS0_CTRL	0x00001980
 
-/* Port configuration */
-#define CFG_FECI2C		0xF0
+/* Chip Select 1 : External SRAM */
+#define CONFIG_SYS_CS1_BASE	0x30000000
+#define CONFIG_SYS_CS1_MASK	0x00070001
+#define CONFIG_SYS_CS1_CTRL	0x00001900
 
 #endif				/* _M5271EVB_H */
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index d2dcdd2..fc73d64 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -39,9 +39,9 @@
 #define CONFIG_MCFTMR
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef CONFIG_WATCHDOG
 #define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */
@@ -92,22 +92,22 @@
 #	define CONFIG_NET_MULTI		1
 #	define CONFIG_MII		1
 #	define CONFIG_MII_INIT		1
-#	define CFG_DISCOVER_PHY
-#	define CFG_RX_ETH_BUFFER	8
-#	define CFG_FAULT_ECHO_LINK_DOWN
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 
-#	define CFG_FEC0_PINMUX		0
-#	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
 #	define MCFFEC_TOUT_LOOP		50000
-/* If CFG_DISCOVER_PHY is not defined - hardcoded */
-#	ifndef CFG_DISCOVER_PHY
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
 #		define FECDUPLEX	FULL
 #		define FECSPEED		_100BASET
 #	else
-#		ifndef CFG_FAULT_ECHO_LINK_DOWN
-#			define CFG_FAULT_ECHO_LINK_DOWN
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #		endif
-#	endif			/* CFG_DISCOVER_PHY */
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
 #endif
 
 #ifdef CONFIG_MCFFEC
@@ -132,108 +132,114 @@
 	"save\0"				\
 	""
 
-#define CFG_PROMPT		"-> "
-#define CFG_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size      */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size      */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
 #endif
 
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
-#define CFG_LOAD_ADDR		0x20000
-#define CFG_MEMTEST_START	0x400
-#define CFG_MEMTEST_END		0x380000
-#define CFG_HZ			1000
-#define CFG_CLK			66000000
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LOAD_ADDR		0x20000
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CLK			66000000
 
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
  * You should know what you are doing if you make changes here.
  */
-#define CFG_MBAR		0x10000000	/* Register Base Addrs */
-#define CFG_SCR			0x0003;
-#define CFG_SPR			0xffff;
+#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+#define CONFIG_SYS_SCR			0x0003
+#define CONFIG_SYS_SPR			0xffff
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x20000000
-#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM    */
-#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM    */
+#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_SIZE		4	/* SDRAM size in MB */
-#define CFG_FLASH_BASE		0xffe00000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		4	/* SDRAM size in MB */
+#define CONFIG_SYS_FLASH_BASE		0xffe00000
 
 #ifdef	CONFIG_MONITOR_IS_IN_RAM
-#define CFG_MONITOR_BASE	0x20000
+#define CONFIG_SYS_MONITOR_BASE	0x20000
 #else
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
 #endif
 
-#define CFG_MONITOR_LEN		0x20000
-#define CFG_MALLOC_LEN		(256 << 10)
-#define CFG_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 
-/*-----------------------------------------------------------------------
+/*
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks           */
-#define CFG_MAX_FLASH_SECT	11	/* max number of sectors on one chip    */
-#define CFG_FLASH_ERASE_TOUT	1000
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_FLASH_CFI_DRIVER	1
+#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#endif
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
-#define CFG_BR0_PRELIM		0xFFE00201
-#define CFG_OR0_PRELIM		0xFFE00014
-#define CFG_BR1_PRELIM		0
-#define CFG_OR1_PRELIM		0
-#define CFG_BR2_PRELIM		0x30000001
-#define CFG_OR2_PRELIM		0xFFF80000
-#define CFG_BR3_PRELIM		0
-#define CFG_OR3_PRELIM		0
-#define CFG_BR4_PRELIM		0
-#define CFG_OR4_PRELIM		0
-#define CFG_BR5_PRELIM		0
-#define CFG_OR5_PRELIM		0
-#define CFG_BR6_PRELIM		0
-#define CFG_OR6_PRELIM		0
-#define CFG_BR7_PRELIM		0x00000701
-#define CFG_OR7_PRELIM		0xFFC0007C
+#define CONFIG_SYS_BR0_PRELIM		0xFFE00201
+#define CONFIG_SYS_OR0_PRELIM		0xFFE00014
+#define CONFIG_SYS_BR1_PRELIM		0
+#define CONFIG_SYS_OR1_PRELIM		0
+#define CONFIG_SYS_BR2_PRELIM		0x30000001
+#define CONFIG_SYS_OR2_PRELIM		0xFFF80000
+#define CONFIG_SYS_BR3_PRELIM		0
+#define CONFIG_SYS_OR3_PRELIM		0
+#define CONFIG_SYS_BR4_PRELIM		0
+#define CONFIG_SYS_OR4_PRELIM		0
+#define CONFIG_SYS_BR5_PRELIM		0
+#define CONFIG_SYS_OR5_PRELIM		0
+#define CONFIG_SYS_BR6_PRELIM		0
+#define CONFIG_SYS_OR6_PRELIM		0
+#define CONFIG_SYS_BR7_PRELIM		0x00000701
+#define CONFIG_SYS_OR7_PRELIM		0xFFC0007C
 
 /*-----------------------------------------------------------------------
  * Port configuration
  */
-#define CFG_PACNT		0x00000000
-#define CFG_PADDR		0x0000
-#define CFG_PADAT		0x0000
-#define CFG_PBCNT		0x55554155	/* Ethernet/UART configuration */
-#define CFG_PBDDR		0x0000
-#define CFG_PBDAT		0x0000
-#define CFG_PDCNT		0x00000000
+#define CONFIG_SYS_PACNT		0x00000000
+#define CONFIG_SYS_PADDR		0x0000
+#define CONFIG_SYS_PADAT		0x0000
+#define CONFIG_SYS_PBCNT		0x55554155	/* Ethernet/UART configuration */
+#define CONFIG_SYS_PBDDR		0x0000
+#define CONFIG_SYS_PBDAT		0x0000
+#define CONFIG_SYS_PDCNT		0x00000000
 #endif				/* _M5272C3_H */
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index b0ef41e..db48d76 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -44,9 +44,9 @@
 #define CONFIG_MCFTMR
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
@@ -90,22 +90,22 @@
 #define CONFIG_NET_MULTI	1
 #define CONFIG_MII		1
 #define CONFIG_MII_INIT		1
-#define CFG_DISCOVER_PHY
-#define CFG_RX_ETH_BUFFER	8
-#define CFG_FAULT_ECHO_LINK_DOWN
-#define CFG_FEC0_PINMUX		0
-#define CFG_FEC0_MIIBASE	CFG_FEC0_IOBASE
-#define CFG_FEC1_PINMUX		0
-#define CFG_FEC1_MIIBASE	CFG_FEC1_IOBASE
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_SYS_FEC0_PINMUX		0
+#define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#define CONFIG_SYS_FEC1_PINMUX		0
+#define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC1_IOBASE
 #define MCFFEC_TOUT_LOOP	50000
 #define CONFIG_HAS_ETH1
-/* If CFG_DISCOVER_PHY is not defined - hardcoded */
-#ifndef CFG_DISCOVER_PHY
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#ifndef CONFIG_SYS_DISCOVER_PHY
 #define FECDUPLEX		FULL
 #define FECSPEED		_100BASET
 #else
-#ifndef CFG_FAULT_ECHO_LINK_DOWN
-#define CFG_FAULT_ECHO_LINK_DOWN
+#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #endif
 #endif
 #endif
@@ -114,40 +114,40 @@
 #define CONFIG_FSL_I2C
 #define CONFIG_HARD_I2C		/* I2C with hw support */
 #undef CONFIG_SOFT_I2C
-#define CFG_I2C_SPEED		80000
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_OFFSET		0x00000300
-#define CFG_IMMR		CFG_MBAR
-#define CFG_I2C_PINMUX_REG	(gpio_reg->par_feci2c)
-#define CFG_I2C_PINMUX_CLR	(0xFFF0)
-#define CFG_I2C_PINMUX_SET	(0x000F)
+#define CONFIG_SYS_I2C_SPEED		80000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x00000300
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+#define CONFIG_SYS_I2C_PINMUX_REG	(gpio_reg->par_feci2c)
+#define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFF0)
+#define CONFIG_SYS_I2C_PINMUX_SET	(0x000F)
 
 #ifdef CONFIG_MCFFEC
 #define CONFIG_ETHADDR		00:06:3b:01:41:55
 #define CONFIG_ETH1ADDR		00:0e:0c:bc:e5:60
 #endif
 
-#define CFG_PROMPT		"-> "
-#define CFG_LONGHELP		/* undef to save memory	*/
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
 
 #if (CONFIG_CMD_KGDB)
-#	define CFG_CBSIZE	1024
+#	define CONFIG_SYS_CBSIZE	1024
 #else
-#	define CFG_CBSIZE	256
+#	define CONFIG_SYS_CBSIZE	256
 #endif
-#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS		16
-#define CFG_BARGSIZE		CFG_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
-#define CFG_LOAD_ADDR		0x800000
+#define CONFIG_SYS_LOAD_ADDR		0x800000
 
 #define CONFIG_BOOTDELAY	5
 #define CONFIG_BOOTCOMMAND	"bootm ffe40000"
-#define CFG_MEMTEST_START	0x400
-#define CFG_MEMTEST_END		0x380000
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
 
-#define CFG_HZ			1000
-#define CFG_CLK			150000000
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CLK			150000000
 
 /*
  * Low Level Configuration Settings
@@ -155,73 +155,73 @@
  * You should know what you are doing if you make changes here.
  */
 
-#define CFG_MBAR		0x40000000
+#define CONFIG_SYS_MBAR		0x40000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x20000000
-#define CFG_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
-#define CFG_GBL_DATA_SIZE	1000	/* bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	1000	/* bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_SIZE		16	/* SDRAM size in MB */
-#define CFG_FLASH_BASE		0xffe00000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
 
 #ifdef CONFIG_MONITOR_IS_IN_RAM
-#define CFG_MONITOR_BASE	0x20000
+#define CONFIG_SYS_MONITOR_BASE	0x20000
 #else
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
 #endif
 
-#define CFG_MONITOR_LEN		0x20000
-#define CFG_MALLOC_LEN		(256 << 10)
-#define CFG_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial mmap for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial mmap for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	11	/* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT	1000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	11	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
 
-#define CFG_FLASH_CFI		1
+#define CONFIG_SYS_FLASH_CFI		1
 #define CONFIG_FLASH_CFI_DRIVER	1
-#define CFG_FLASH_SIZE		0x200000
+#define CONFIG_SYS_FLASH_SIZE		0x200000
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
-#define CFG_AR0_PRELIM		(CFG_FLASH_BASE >> 16)
-#define CFG_CR0_PRELIM		0x1980
-#define CFG_MR0_PRELIM		0x001F0001
+#define CONFIG_SYS_CS0_BASE		0xffe00000
+#define CONFIG_SYS_CS0_CTRL		0x00001980
+#define CONFIG_SYS_CS0_MASK		0x001F0001
 
-#define CFG_AR1_PRELIM		0x3000
-#define CFG_CR1_PRELIM		0x1900
-#define CFG_MR1_PRELIM		0x00070001
+#define CONFIG_SYS_CS1_BASE		0x30000000
+#define CONFIG_SYS_CS1_CTRL		0x00001900
+#define CONFIG_SYS_CS1_MASK		0x00070001
 
 /*-----------------------------------------------------------------------
  * Port configuration
  */
-#define CFG_FECI2C		0x0FA0
+#define CONFIG_SYS_FECI2C		0x0FA0
 
 #endif	/* _M5275EVB_H */
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index 5cc64c1..15590cf 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -39,9 +39,9 @@
 #define CONFIG_MCFTMR
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef	CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */
 
@@ -76,22 +76,22 @@
 #	define CONFIG_NET_MULTI		1
 #	define CONFIG_MII		1
 #	define CONFIG_MII_INIT		1
-#	define CFG_DISCOVER_PHY
-#	define CFG_RX_ETH_BUFFER	8
-#	define CFG_FAULT_ECHO_LINK_DOWN
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 
-#	define CFG_FEC0_PINMUX		0
-#	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
 #	define MCFFEC_TOUT_LOOP		50000
-/* If CFG_DISCOVER_PHY is not defined - hardcoded */
-#	ifndef CFG_DISCOVER_PHY
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
 #		define FECDUPLEX	FULL
 #		define FECSPEED		_100BASET
 #	else
-#		ifndef CFG_FAULT_ECHO_LINK_DOWN
-#			define CFG_FAULT_ECHO_LINK_DOWN
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #		endif
-#	endif			/* CFG_DISCOVER_PHY */
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
 #endif
 
 #define CONFIG_BOOTDELAY	5
@@ -117,135 +117,127 @@
 	"save\0"				\
 	""
 
-#define CFG_PROMPT		"-> "
-#define	CFG_LONGHELP		/* undef to save memory         */
+#define CONFIG_SYS_PROMPT		"-> "
+#define	CONFIG_SYS_LONGHELP		/* undef to save memory         */
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size      */
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size      */
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 
-#define CFG_LOAD_ADDR		0x20000
+#define CONFIG_SYS_LOAD_ADDR		0x20000
 
-#define CFG_MEMTEST_START	0x400
-#define CFG_MEMTEST_END		0x380000
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
 
-#define CFG_HZ			1000
-#define	CFG_CLK			64000000
+#define CONFIG_SYS_HZ			1000
+#define	CONFIG_SYS_CLK			64000000
 
 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
 
-#define CFG_MFD			0x02	/* PLL Multiplication Factor Devider */
-#define CFG_RFD			0x00	/* PLL Reduce Frecuency Devider */
+#define CONFIG_SYS_MFD			0x02	/* PLL Multiplication Factor Devider */
+#define CONFIG_SYS_RFD			0x00	/* PLL Reduce Frecuency Devider */
 
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
  * You should know what you are doing if you make changes here.
  */
-#define	CFG_MBAR		0x40000000
+#define	CONFIG_SYS_MBAR		0x40000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x20000000
-#define CFG_INIT_RAM_END	0x10000	/* End of used area in internal SRAM    */
-#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_END	0x10000	/* End of used area in internal SRAM    */
+#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define	CFG_SDRAM_SIZE		16	/* SDRAM size in MB */
-#define CFG_FLASH_BASE		0xffe00000
-#define	CFG_INT_FLASH_BASE	0xf0000000
-#define CFG_INT_FLASH_ENABLE	0x21
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define	CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#define	CONFIG_SYS_INT_FLASH_BASE	0xf0000000
+#define CONFIG_SYS_INT_FLASH_ENABLE	0x21
 
 /* If M5282 port is fully implemented the monitor base will be behind
  * the vector table. */
-#if (TEXT_BASE != CFG_INT_FLASH_BASE)
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#if (TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
 #else
-#define CFG_MONITOR_BASE	(TEXT_BASE + 0x418)	/* 24 Byte for CFM-Config */
+#define CONFIG_SYS_MONITOR_BASE	(TEXT_BASE + 0x418)	/* 24 Byte for CFM-Config */
 #endif
 
-#define CFG_MONITOR_LEN		0x20000
-#define CFG_MALLOC_LEN		(256 << 10)
-#define CFG_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_FLASH_CFI
-#ifdef CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
 
 #	define CONFIG_FLASH_CFI_DRIVER	1
-#	define CFG_FLASH_SIZE		0x1000000	/* Max size that the board might have */
-#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#	define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#	define CFG_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
-#	define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
-#	define CFG_FLASH_CHECKSUM
-#	define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 #endif
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
-#define CFG_CS0_BASE		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		2*1024*1024
-#define CFG_CS0_WIDTH		16
-#define CFG_CS0_RO		0
-#define CFG_CS0_WS		6
-/*
-#define CFG_CS3_BASE		0xE0000000
-#define CFG_CS3_SIZE		1*1024*1024
-#define CFG_CS3_WIDTH		16
-#define CFG_CS3_RO		0
-#define CFG_CS3_WS		6
-*/
+#define CONFIG_SYS_CS0_BASE		0xFFE00000
+#define CONFIG_SYS_CS0_CTRL		0x00001980
+#define CONFIG_SYS_CS0_MASK		0x001F0001
+
 /*-----------------------------------------------------------------------
  * Port configuration
  */
-#define CFG_PACNT		0x0000000	/* Port A D[31:24] */
-#define CFG_PADDR		0x0000000
-#define CFG_PADAT		0x0000000
-
-#define CFG_PBCNT		0x0000000	/* Port B D[23:16] */
-#define CFG_PBDDR		0x0000000
-#define CFG_PBDAT		0x0000000
-
-#define CFG_PCCNT		0x0000000	/* Port C D[15:08] */
-#define CFG_PCDDR		0x0000000
-#define CFG_PCDAT		0x0000000
-
-#define CFG_PDCNT		0x0000000	/* Port D D[07:00] */
-#define CFG_PCDDR		0x0000000
-#define CFG_PCDAT		0x0000000
-
-#define CFG_PEHLPAR		0xC0
-#define CFG_PUAPAR		0x0F	/* UA0..UA3 = Uart 0 +1 */
-#define CFG_DDRUA		0x05
-#define CFG_PJPAR		0xFF;
+#define CONFIG_SYS_PACNT		0x0000000	/* Port A D[31:24] */
+#define CONFIG_SYS_PADDR		0x0000000
+#define CONFIG_SYS_PADAT		0x0000000
+
+#define CONFIG_SYS_PBCNT		0x0000000	/* Port B D[23:16] */
+#define CONFIG_SYS_PBDDR		0x0000000
+#define CONFIG_SYS_PBDAT		0x0000000
+
+#define CONFIG_SYS_PCCNT		0x0000000	/* Port C D[15:08] */
+#define CONFIG_SYS_PCDDR		0x0000000
+#define CONFIG_SYS_PCDAT		0x0000000
+
+#define CONFIG_SYS_PDCNT		0x0000000	/* Port D D[07:00] */
+#define CONFIG_SYS_PCDDR		0x0000000
+#define CONFIG_SYS_PCDAT		0x0000000
+
+#define CONFIG_SYS_PEHLPAR		0xC0
+#define CONFIG_SYS_PUAPAR		0x0F	/* UA0..UA3 = Uart 0 +1 */
+#define CONFIG_SYS_DDRUA		0x05
+#define CONFIG_SYS_PJPAR		0xFF
 
 #endif				/* _CONFIG_M5282EVB_H */
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
new file mode 100644
index 0000000..df54c60
--- /dev/null
+++ b/include/configs/M53017EVB.h
@@ -0,0 +1,247 @@
+/*
+ * Configuation settings for the Freescale MCF53017EVB.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M53017EVB_H
+#define _M53017EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF5301x		/* define processor family */
+#define CONFIG_M53015		/* define processor type */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT		5000
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#undef CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#define CONFIG_SYS_UNIFY_CACHE
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_NET_MULTI		1
+#	define CONFIG_MII		1
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#	define CONFIG_HAS_ETH1
+
+#	define CONFIG_SYS_FEC0_PINMUX	0
+#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#	define CONFIG_SYS_FEC1_PINMUX	0
+#	define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC1_IOBASE
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+#define CONFIG_SYS_RTC_CNT		(0x8000)
+#define CONFIG_SYS_RTC_SETUP		(RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C			/* I2C with hw support */
+#undef CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SPEED		80000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x58000
+#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
+
+#define CONFIG_BOOTDELAY		1	/* autoboot after 5 seconds */
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
+#	define CONFIG_ETH1ADDR	00:e0:0c:bc:e5:61
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif				/* FEC_ENET */
+
+#define CONFIG_HOSTNAME		M53017
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=40010000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off 0 3ffff;"		\
+	"era 0 3ffff;"				\
+	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"save\0"				\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+#define CONFIG_SYS_PROMPT	"-> "
+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of cmd args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Arg Buf Sz */
+#define CONFIG_SYS_LOAD_ADDR	0x40010000
+
+#define CONFIG_SYS_HZ		1000
+#define CONFIG_SYS_CLK		80000000
+#define CONFIG_SYS_CPU_CLK	CONFIG_SYS_CLK * 3
+
+#define CONFIG_SYS_MBAR		0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_END		0x20000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x21
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x43711630
+#define CONFIG_SYS_SDRAM_CFG2		0x56670000
+#define CONFIG_SYS_SDRAM_CTRL		0xE1002000
+#define CONFIG_SYS_SDRAM_EMOD		0x80010000
+#define CONFIG_SYS_SDRAM_MODE		0x00CD0000
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_FLASH_CFI_DRIVER		1
+#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CONFIG_ENV_OFFSET		0x8000
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_ENV_SECT_SIZE		0x8000
+#define CONFIG_ENV_IS_IN_FLASH		1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash
+ * CS1 - Ext SRAM
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CONFIG_SYS_CS0_BASE		0
+#define CONFIG_SYS_CS0_MASK		0x00FF0001
+#define CONFIG_SYS_CS0_CTRL		0x00001FA0
+
+#define CONFIG_SYS_CS1_BASE		0xC0000000
+#define CONFIG_SYS_CS1_MASK		0x00070001
+#define CONFIG_SYS_CS1_CTRL		0x00001FA0
+
+#endif				/* _M53017EVB_H */
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 3a8e49a..1f1586a 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -38,9 +38,9 @@
 #define CONFIG_M5329		/* define processor type */
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef CONFIG_WATCHDOG
 #define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
@@ -64,29 +64,29 @@
 #      define CONFIG_CMD_NAND
 #endif
 
-#define CFG_UNIFY_CACHE
+#define CONFIG_SYS_UNIFY_CACHE
 
 #define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC
 #	define CONFIG_NET_MULTI		1
 #	define CONFIG_MII		1
 #	define CONFIG_MII_INIT		1
-#	define CFG_DISCOVER_PHY
-#	define CFG_RX_ETH_BUFFER	8
-#	define CFG_FAULT_ECHO_LINK_DOWN
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 
-#	define CFG_FEC0_PINMUX		0
-#	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
 #	define MCFFEC_TOUT_LOOP		50000
-/* If CFG_DISCOVER_PHY is not defined - hardcoded */
-#	ifndef CFG_DISCOVER_PHY
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
 #		define FECDUPLEX	FULL
 #		define FECSPEED		_100BASET
 #	else
-#		ifndef CFG_FAULT_ECHO_LINK_DOWN
-#			define CFG_FAULT_ECHO_LINK_DOWN
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #		endif
-#	endif			/* CFG_DISCOVER_PHY */
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
 #endif
 
 #define CONFIG_MCFRTC
@@ -100,10 +100,10 @@
 #define CONFIG_FSL_I2C
 #define CONFIG_HARD_I2C			/* I2C with hw support */
 #undef CONFIG_SOFT_I2C			/* I2C bit-banged */
-#define CFG_I2C_SPEED		80000
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_OFFSET		0x58000
-#define CFG_IMMR		CFG_MBAR
+#define CONFIG_SYS_I2C_SPEED		80000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x58000
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
 
 #define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
 #define CONFIG_UDP_CHECKSUM
@@ -131,27 +131,27 @@
 	""
 
 #define CONFIG_PRAM		512	/* 512 KB */
-#define CFG_PROMPT		"-> "
-#define CFG_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
 
 #ifdef CONFIG_CMD_KGDB
-#	define CFG_CBSIZE	1024	/* Console I/O Buffer Size */
+#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
 #else
-#	define CFG_CBSIZE	256	/* Console I/O Buffer Size */
+#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
-#define CFG_LOAD_ADDR		0x40010000
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LOAD_ADDR		0x40010000
 
-#define CFG_HZ			1000
-#define CFG_CLK			80000000
-#define CFG_CPU_CLK		CFG_CLK * 3
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CLK			80000000
+#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 3
 
-#define CFG_MBAR		0xFC000000
+#define CONFIG_SYS_MBAR		0xFC000000
 
-#define CFG_LATCH_ADDR		(CFG_CS1_BASE + 0x80000)
+#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)
 
 /*
  * Low Level Configuration Settings
@@ -161,69 +161,68 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x80000000
-#define CFG_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
-#define CFG_INIT_RAM_CTRL	0x221
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x40000000
-#define CFG_SDRAM_SIZE		32	/* SDRAM size in MB */
-#define CFG_SDRAM_CFG1		0x53722730
-#define CFG_SDRAM_CFG2		0x56670000
-#define CFG_SDRAM_CTRL		0xE1092000
-#define CFG_SDRAM_EMOD		0x40010000
-#define CFG_SDRAM_MODE		0x018D0000
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x53722730
+#define CONFIG_SYS_SDRAM_CFG2		0x56670000
+#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
+#define CONFIG_SYS_SDRAM_EMOD		0x40010000
+#define CONFIG_SYS_SDRAM_MODE		0x018D0000
 
-#define CFG_MEMTEST_START	CFG_SDRAM_BASE + 0x400
-#define CFG_MEMTEST_END		((CFG_SDRAM_SIZE - 3) << 20)
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
 
-#define CFG_BOOTPARAMS_LEN	64*1024
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_FLASH_CFI
-#ifdef CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
 #	define CONFIG_FLASH_CFI_DRIVER	1
-#	define CFG_FLASH_SIZE		0x800000	/* Max size that the board might have */
-#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#	define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#	define CFG_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
-#	define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
 #endif
 
 #ifdef NANDFLASH_SIZE
-#	define CFG_MAX_NAND_DEVICE	1
-#	define CFG_NAND_BASE		CFG_CS2_BASE
-#	define CFG_NAND_SIZE		1
-#	define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
-#	define NAND_MAX_CHIPS		1
+#	define CONFIG_SYS_MAX_NAND_DEVICE	1
+#	define CONFIG_SYS_NAND_BASE		CONFIG_SYS_CS2_BASE
+#	define CONFIG_SYS_NAND_SIZE		1
+#	define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #	define NAND_ALLOW_ERASE_ALL	1
 #	define CONFIG_JFFS2_NAND	1
 #	define CONFIG_JFFS2_DEV		"nand0"
-#	define CONFIG_JFFS2_PART_SIZE	(CFG_CS2_MASK & ~1)
+#	define CONFIG_JFFS2_PART_SIZE	(CONFIG_SYS_CS2_MASK & ~1)
 #	define CONFIG_JFFS2_PART_OFFSET	0x00000000
 #endif
 
-#define CFG_FLASH_BASE		CFG_CS0_BASE
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
@@ -236,7 +235,7 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
@@ -249,18 +248,18 @@
  * CS4 - Available
  * CS5 - Available
  */
-#define CFG_CS0_BASE		0
-#define CFG_CS0_MASK		0x007f0001
-#define CFG_CS0_CTRL		0x00001fa0
+#define CONFIG_SYS_CS0_BASE		0
+#define CONFIG_SYS_CS0_MASK		0x007f0001
+#define CONFIG_SYS_CS0_CTRL		0x00001fa0
 
-#define CFG_CS1_BASE		0x10000000
-#define CFG_CS1_MASK		0x001f0001
-#define CFG_CS1_CTRL		0x002A3780
+#define CONFIG_SYS_CS1_BASE		0x10000000
+#define CONFIG_SYS_CS1_MASK		0x001f0001
+#define CONFIG_SYS_CS1_CTRL		0x002A3780
 
 #ifdef NANDFLASH_SIZE
-#define CFG_CS2_BASE		0x20000000
-#define CFG_CS2_MASK		((NANDFLASH_SIZE << 20) | 1)
-#define CFG_CS2_CTRL		0x00001f60
+#define CONFIG_SYS_CS2_BASE		0x20000000
+#define CONFIG_SYS_CS2_MASK		((NANDFLASH_SIZE << 20) | 1)
+#define CONFIG_SYS_CS2_CTRL		0x00001f60
 #endif
 
 #endif				/* _M5329EVB_H */
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index 34698ee..1991687 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -38,9 +38,9 @@
 #define CONFIG_M5373		/* define processor type */
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef CONFIG_WATCHDOG
 #define CONFIG_WATCHDOG_TIMEOUT	3360	/* timeout in ms, max is 3.36 sec */
@@ -64,29 +64,29 @@
 #      define CONFIG_CMD_NAND
 #endif
 
-#define CFG_UNIFY_CACHE
+#define CONFIG_SYS_UNIFY_CACHE
 
 #define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC
 #	define CONFIG_NET_MULTI		1
 #	define CONFIG_MII		1
 #	define CONFIG_MII_INIT		1
-#	define CFG_DISCOVER_PHY
-#	define CFG_RX_ETH_BUFFER	8
-#	define CFG_FAULT_ECHO_LINK_DOWN
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 
-#	define CFG_FEC0_PINMUX		0
-#	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
 #	define MCFFEC_TOUT_LOOP		50000
-/* If CFG_DISCOVER_PHY is not defined - hardcoded */
-#	ifndef CFG_DISCOVER_PHY
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
 #		define FECDUPLEX	FULL
 #		define FECSPEED		_100BASET
 #	else
-#		ifndef CFG_FAULT_ECHO_LINK_DOWN
-#			define CFG_FAULT_ECHO_LINK_DOWN
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #		endif
-#	endif			/* CFG_DISCOVER_PHY */
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
 #endif
 
 #define CONFIG_MCFRTC
@@ -100,10 +100,10 @@
 #define CONFIG_FSL_I2C
 #define CONFIG_HARD_I2C		/* I2C with hw support */
 #undef CONFIG_SOFT_I2C		/* I2C bit-banged */
-#define CFG_I2C_SPEED		80000
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_OFFSET		0x58000
-#define CFG_IMMR		CFG_MBAR
+#define CONFIG_SYS_I2C_SPEED		80000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x58000
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
 
 #define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
 #define CONFIG_UDP_CHECKSUM
@@ -120,7 +120,7 @@
 #define CONFIG_HOSTNAME		M5373EVB
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"			\
-	"loadaddr=" MK_STR(CFG_LOAD_ADDR) "\0"	\
+	"loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0"	\
 	"u-boot=u-boot.bin\0"	\
 	"load=tftp ${loadaddr) ${u-boot}\0"	\
 	"upd=run load; run prog\0"	\
@@ -131,27 +131,27 @@
 	""
 
 #define CONFIG_PRAM		512	/* 512 KB */
-#define CFG_PROMPT		"-> "
-#define CFG_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
 
 #ifdef CONFIG_CMD_KGDB
-#	define CFG_CBSIZE	1024	/* Console I/O Buffer Size */
+#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
 #else
-#	define CFG_CBSIZE	256	/* Console I/O Buffer Size */
+#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
-#define CFG_LOAD_ADDR		0x40010000
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LOAD_ADDR		0x40010000
 
-#define CFG_HZ			1000
-#define CFG_CLK			80000000
-#define CFG_CPU_CLK		CFG_CLK * 3
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CLK			80000000
+#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 3
 
-#define CFG_MBAR		0xFC000000
+#define CONFIG_SYS_MBAR		0xFC000000
 
-#define CFG_LATCH_ADDR		(CFG_CS1_BASE + 0x80000)
+#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)
 
 /*
  * Low Level Configuration Settings
@@ -161,69 +161,68 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x80000000
-#define CFG_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
-#define CFG_INIT_RAM_CTRL	0x221
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x40000000
-#define CFG_SDRAM_SIZE		32	/* SDRAM size in MB */
-#define CFG_SDRAM_CFG1		0x53722730
-#define CFG_SDRAM_CFG2		0x56670000
-#define CFG_SDRAM_CTRL		0xE1092000
-#define CFG_SDRAM_EMOD		0x40010000
-#define CFG_SDRAM_MODE		0x018D0000
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x53722730
+#define CONFIG_SYS_SDRAM_CFG2		0x56670000
+#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
+#define CONFIG_SYS_SDRAM_EMOD		0x40010000
+#define CONFIG_SYS_SDRAM_MODE		0x018D0000
 
-#define CFG_MEMTEST_START	CFG_SDRAM_BASE + 0x400
-#define CFG_MEMTEST_END		((CFG_SDRAM_SIZE - 3) << 20)
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
 
-#define CFG_BOOTPARAMS_LEN	64*1024
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_FLASH_CFI
-#ifdef CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
 #	define CONFIG_FLASH_CFI_DRIVER	1
-#	define CFG_FLASH_SIZE		0x800000	/* Max size that the board might have */
-#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#	define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#	define CFG_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
-#	define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
 #endif
 
 #ifdef NANDFLASH_SIZE
-#	define CFG_MAX_NAND_DEVICE	1
-#	define CFG_NAND_BASE		CFG_CS2_BASE
-#	define CFG_NAND_SIZE		1
-#	define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
-#	define NAND_MAX_CHIPS		1
+#	define CONFIG_SYS_MAX_NAND_DEVICE	1
+#	define CONFIG_SYS_NAND_BASE		CONFIG_SYS_CS2_BASE
+#	define CONFIG_SYS_NAND_SIZE		1
+#	define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #	define NAND_ALLOW_ERASE_ALL	1
 #	define CONFIG_JFFS2_NAND	1
 #	define CONFIG_JFFS2_DEV		"nand0"
-#	define CONFIG_JFFS2_PART_SIZE	(CFG_CS2_MASK & ~1)
+#	define CONFIG_JFFS2_PART_SIZE	(CONFIG_SYS_CS2_MASK & ~1)
 #	define CONFIG_JFFS2_PART_OFFSET	0x00000000
 #endif
 
-#define CFG_FLASH_BASE		CFG_CS0_BASE
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
@@ -236,7 +235,7 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
@@ -249,18 +248,18 @@
  * CS4 - Available
  * CS5 - Available
  */
-#define CFG_CS0_BASE		0
-#define CFG_CS0_MASK		0x007f0001
-#define CFG_CS0_CTRL		0x00001fa0
+#define CONFIG_SYS_CS0_BASE		0
+#define CONFIG_SYS_CS0_MASK		0x007f0001
+#define CONFIG_SYS_CS0_CTRL		0x00001fa0
 
-#define CFG_CS1_BASE		0x10000000
-#define CFG_CS1_MASK		0x001f0001
-#define CFG_CS1_CTRL		0x002A3780
+#define CONFIG_SYS_CS1_BASE		0x10000000
+#define CONFIG_SYS_CS1_MASK		0x001f0001
+#define CONFIG_SYS_CS1_CTRL		0x002A3780
 
 #ifdef NANDFLASH_SIZE
-#define CFG_CS2_BASE		0x20000000
-#define CFG_CS2_MASK		((NANDFLASH_SIZE << 20) | 1)
-#define CFG_CS2_CTRL		0x00001f60
+#define CONFIG_SYS_CS2_BASE		0x20000000
+#define CONFIG_SYS_CS2_MASK		((NANDFLASH_SIZE << 20) | 1)
+#define CONFIG_SYS_CS2_CTRL		0x00001f60
 #endif
 
 #endif				/* _M5373EVB_H */
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index 03d21be..45f7016 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -39,9 +39,9 @@
 #define CONFIG_M54451EVB	/* M54451EVB board */
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef CONFIG_WATCHDOG
 
@@ -84,12 +84,12 @@
 #	define CONFIG_NET_MULTI		1
 #	define CONFIG_MII		1
 #	define CONFIG_MII_INIT		1
-#	define CFG_DISCOVER_PHY
-#	define CFG_RX_ETH_BUFFER	8
-#	define CFG_FAULT_ECHO_LINK_DOWN
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 
-#	define CFG_FEC0_PINMUX	0
-#	define CFG_FEC0_MIIBASE	CFG_FEC0_IOBASE
+#	define CONFIG_SYS_FEC0_PINMUX	0
+#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
 #	define MCFFEC_TOUT_LOOP 50000
 
 #	define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
@@ -102,29 +102,29 @@
 #	define CONFIG_GATEWAYIP		192.162.1.1
 #	define CONFIG_OVERWRITE_ETHADDR_ONCE
 
-/* If CFG_DISCOVER_PHY is not defined - hardcoded */
-#	ifndef CFG_DISCOVER_PHY
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
 #		define FECDUPLEX	FULL
 #		define FECSPEED		_100BASET
 #	else
-#		ifndef CFG_FAULT_ECHO_LINK_DOWN
-#			define CFG_FAULT_ECHO_LINK_DOWN
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #		endif
-#	endif			/* CFG_DISCOVER_PHY */
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
 #endif
 
 #define CONFIG_HOSTNAME		M54451EVB
-#ifdef CFG_STMICRO_BOOT
+#ifdef CONFIG_SYS_STMICRO_BOOT
 /* ST Micro serial flash */
-#define	CFG_LOAD_ADDR2		0x40010007
+#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"netdev=eth0\0"				\
-	"inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0"	\
+	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
 	"loadaddr=0x40010000\0"			\
 	"sbfhdr=sbfhdr.bin\0"			\
 	"uboot=u-boot.bin\0"			\
 	"load=tftp ${loadaddr} ${sbfhdr};"	\
-	"tftp " MK_STR(CFG_LOAD_ADDR2) " ${uboot} \0"	\
+	"tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
 	"upd=run load; run prog\0"		\
 	"prog=sf probe 0:1 10000 1;"		\
 	"sf erase 0 30000;"			\
@@ -132,16 +132,16 @@
 	"save\0"				\
 	""
 #else
-#define CFG_UBOOT_END	0x3FFFF
+#define CONFIG_SYS_UBOOT_END	0x3FFFF
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"netdev=eth0\0"				\
-	"inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0"	\
+	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
 	"loadaddr=40010000\0"			\
 	"u-boot=u-boot.bin\0"			\
 	"load=tftp ${loadaddr) ${u-boot}\0"	\
 	"upd=run load; run prog\0"		\
-	"prog=prot off 0 " MK_STR(CFG_UBOOT_END)	\
-	"; era 0 " MK_STR(CFG_UBOOT_END) " ;"	\
+	"prog=prot off 0 " MK_STR(CONFIG_SYS_UBOOT_END)	\
+	"; era 0 " MK_STR(CONFIG_SYS_UBOOT_END) " ;"	\
 	"cp.b ${loadaddr} 0 ${filesize};"	\
 	"save\0"				\
 	""
@@ -150,7 +150,7 @@
 /* Realtime clock */
 #define CONFIG_MCFRTC
 #undef RTC_DEBUG
-#define CFG_RTC_OSCILLATOR	(32 * CFG_HZ)
+#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)
 
 /* Timer */
 #define CONFIG_MCFTMR
@@ -160,22 +160,22 @@
 #define CONFIG_FSL_I2C
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged               */
-#define CFG_I2C_SPEED		80000	/* I2C speed and slave address  */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_OFFSET		0x58000
-#define CFG_IMMR		CFG_MBAR
+#define CONFIG_SYS_I2C_SPEED		80000	/* I2C speed and slave address  */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x58000
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
 
 /* DSPI and Serial Flash */
 #define CONFIG_CF_DSPI
 #define CONFIG_SERIAL_FLASH
 #define CONFIG_HARD_SPI
-#define CFG_SER_FLASH_BASE	0x01000000
-#define CFG_SBFHDR_SIZE		0x7
+#define CONFIG_SYS_SER_FLASH_BASE	0x01000000
+#define CONFIG_SYS_SBFHDR_SIZE		0x7
 #ifdef CONFIG_CMD_SPI
 #	define CONFIG_SPI_FLASH
 #	define CONFIG_SPI_FLASH_STMICRO
 
-#	define CFG_DSPI_DCTAR0		(DSPI_DCTAR_TRSZ(7) | \
+#	define CONFIG_SYS_DSPI_DCTAR0		(DSPI_DCTAR_TRSZ(7) | \
 					 DSPI_DCTAR_CPOL | \
 					 DSPI_DCTAR_CPHA | \
 					 DSPI_DCTAR_PCSSCK_1CLK | \
@@ -193,23 +193,23 @@
 
 #define CONFIG_PRAM		2048	/* 2048 KB */
 
-#define CFG_PROMPT		"-> "
-#define CFG_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE			1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE			1024	/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE			256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE			256	/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 
-#define CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 0x10000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)
 
-#define CFG_HZ			1000
+#define CONFIG_SYS_HZ			1000
 
-#define CFG_MBAR		0xFC000000
+#define CONFIG_SYS_MBAR		0xFC000000
 
 /*
  * Low Level Configuration Settings
@@ -220,39 +220,39 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x80000000
-#define CFG_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
-#define CFG_INIT_RAM_CTRL	0x221
-#define CFG_GBL_DATA_SIZE	256	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 32)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-#define CFG_SBFHDR_DATA_OFFSET	(CFG_INIT_RAM_END - 32)
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_SIZE	256	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - 32)
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x40000000
-#define CFG_SDRAM_SIZE		128	/* SDRAM size in MB */
-#define CFG_SDRAM_CFG1		0x33633F30
-#define CFG_SDRAM_CFG2		0x57670000
-#define CFG_SDRAM_CTRL		0xE20D2C00
-#define CFG_SDRAM_EMOD		0x80810000
-#define CFG_SDRAM_MODE		0x008D0000
-#define CFG_SDRAM_DRV_STRENGTH	0x44
-
-#define CFG_MEMTEST_START	CFG_SDRAM_BASE + 0x400
-#define CFG_MEMTEST_END		((CFG_SDRAM_SIZE - 3) << 20)
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x33633F30
+#define CONFIG_SYS_SDRAM_CFG2		0x57670000
+#define CONFIG_SYS_SDRAM_CTRL		0xE20D2C00
+#define CONFIG_SYS_SDRAM_EMOD		0x80810000
+#define CONFIG_SYS_SDRAM_MODE		0x008D0000
+#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x44
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 
 #ifdef CONFIG_CF_SBF
-#	define CFG_MONITOR_BASE	(TEXT_BASE + 0x400)
+#	define CONFIG_SYS_MONITOR_BASE	(TEXT_BASE + 0x400)
 #else
-#	define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
 #endif
-#define CFG_BOOTPARAMS_LEN	64*1024
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
 
 /*
  * For booting Linux, the board info and command line data
@@ -260,7 +260,7 @@
  * the maximum mapped by the Linux kernel during initialization ??
  */
 /* Initial Memory map for Linux */
-#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
@@ -273,7 +273,7 @@
 #	define CONFIG_ENV_SECT_SIZE	0x10000
 #else
 #	define CONFIG_ENV_IS_IN_FLASH	1
-#	define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x4000)
+#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
 #	define CONFIG_ENV_SECT_SIZE	0x2000
 #endif
 #undef CONFIG_ENV_OVERWRITE
@@ -282,28 +282,28 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#ifdef CFG_STMICRO_BOOT
-#	define CFG_FLASH_BASE		CFG_SER_FLASH_BASE
-#	define CFG_FLASH0_BASE		CFG_SER_FLASH_BASE
-#	define CFG_FLASH1_BASE		CFG_CS0_BASE
+#ifdef CONFIG_SYS_STMICRO_BOOT
+#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_SER_FLASH_BASE
+#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_SER_FLASH_BASE
+#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS0_BASE
 #endif
-#ifdef CFG_SPANSION_BOOT
-#	define CFG_FLASH_BASE		CFG_CS0_BASE
-#	define CFG_FLASH0_BASE		CFG_CS0_BASE
-#	define CFG_FLASH1_BASE		CFG_SER_FLASH_BASE
+#ifdef CONFIG_SYS_SPANSION_BOOT
+#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_SER_FLASH_BASE
 #endif
 
-#define CFG_FLASH_CFI
-#ifdef CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
 
 #	define CONFIG_FLASH_CFI_DRIVER	1
-#	define CFG_FLASH_SIZE		0x1000000	/* Max size that the board might have */
-#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#	define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#	define CFG_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
-#	define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
-#	define CFG_FLASH_CHECKSUM
-#	define CFG_FLASH_BANKS_LIST	{ CFG_CS0_BASE }
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
 
 #endif
 
@@ -311,21 +311,21 @@
  * This is setting for JFFS2 support in u-boot.
  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
  */
-#ifdef CFG_SPANSION_BOOT
+#ifdef CONFIG_SYS_SPANSION_BOOT
 #	define CONFIG_JFFS2_DEV		"nor0"
 #	define CONFIG_JFFS2_PART_SIZE	0x01000000
-#	define CONFIG_JFFS2_PART_OFFSET	(CFG_FLASH0_BASE + 0x500000)
+#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
 #endif
-#ifdef CFG_STMICRO_BOOT
+#ifdef CONFIG_SYS_STMICRO_BOOT
 #	define CONFIG_JFFS2_DEV		"nor0"
 #	define CONFIG_JFFS2_PART_SIZE	0x01000000
-#	define CONFIG_JFFS2_PART_OFFSET	(CFG_FLASH0_BASE + 0x500000)
+#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
 #endif
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE		16
+#define CONFIG_SYS_CACHELINE_SIZE		16
 
 /*-----------------------------------------------------------------------
  * Memory bank definitions
@@ -340,10 +340,10 @@
  */
 
  /* SPANSION Flash */
-#define CFG_CS0_BASE		0x00000000
-#define CFG_CS0_MASK		0x007F0001
-#define CFG_CS0_CTRL		0x00001180
+#define CONFIG_SYS_CS0_BASE		0x00000000
+#define CONFIG_SYS_CS0_MASK		0x007F0001
+#define CONFIG_SYS_CS0_CTRL		0x00001180
 
-#define CFG_SPANSION_BASE	CFG_CS0_BASE
+#define CONFIG_SYS_SPANSION_BASE	CONFIG_SYS_CS0_BASE
 
 #endif				/* _M54451EVB_H */
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 9513279..101dced 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -39,9 +39,9 @@
 #define CONFIG_M54455EVB	/* M54455EVB board */
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef CONFIG_WATCHDOG
 
@@ -88,14 +88,14 @@
 #	define CONFIG_NET_MULTI		1
 #	define CONFIG_MII		1
 #	define CONFIG_MII_INIT		1
-#	define CFG_DISCOVER_PHY
-#	define CFG_RX_ETH_BUFFER	8
-#	define CFG_FAULT_ECHO_LINK_DOWN
-
-#	define CFG_FEC0_PINMUX	0
-#	define CFG_FEC1_PINMUX	0
-#	define CFG_FEC0_MIIBASE	CFG_FEC0_IOBASE
-#	define CFG_FEC1_MIIBASE	CFG_FEC0_IOBASE
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX	0
+#	define CONFIG_SYS_FEC1_PINMUX	0
+#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#	define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC0_IOBASE
 #	define MCFFEC_TOUT_LOOP 50000
 #	define CONFIG_HAS_ETH1
 
@@ -110,29 +110,29 @@
 #	define CONFIG_GATEWAYIP		192.162.1.1
 #	define CONFIG_OVERWRITE_ETHADDR_ONCE
 
-/* If CFG_DISCOVER_PHY is not defined - hardcoded */
-#	ifndef CFG_DISCOVER_PHY
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
 #		define FECDUPLEX	FULL
 #		define FECSPEED		_100BASET
 #	else
-#		ifndef CFG_FAULT_ECHO_LINK_DOWN
-#			define CFG_FAULT_ECHO_LINK_DOWN
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #		endif
-#	endif			/* CFG_DISCOVER_PHY */
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
 #endif
 
 #define CONFIG_HOSTNAME		M54455EVB
-#ifdef CFG_STMICRO_BOOT
+#ifdef CONFIG_SYS_STMICRO_BOOT
 /* ST Micro serial flash */
-#define	CFG_LOAD_ADDR2		0x40010013
+#define	CONFIG_SYS_LOAD_ADDR2		0x40010013
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"netdev=eth0\0"				\
-	"inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0"	\
+	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
 	"loadaddr=0x40010000\0"			\
 	"sbfhdr=sbfhdr.bin\0"			\
 	"uboot=u-boot.bin\0"			\
 	"load=tftp ${loadaddr} ${sbfhdr};"	\
-	"tftp " MK_STR(CFG_LOAD_ADDR2) " ${uboot} \0"	\
+	"tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
 	"upd=run load; run prog\0"		\
 	"prog=sf probe 0:1 10000 1;"		\
 	"sf erase 0 30000;"			\
@@ -141,23 +141,23 @@
 	""
 #else
 /* Atmel and Intel */
-#ifdef CFG_ATMEL_BOOT
-#	define CFG_UBOOT_END	0x0403FFFF
-#elif defined(CFG_INTEL_BOOT)
-#	define CFG_UBOOT_END	0x3FFFF
+#ifdef CONFIG_SYS_ATMEL_BOOT
+#	define CONFIG_SYS_UBOOT_END	0x0403FFFF
+#elif defined(CONFIG_SYS_INTEL_BOOT)
+#	define CONFIG_SYS_UBOOT_END	0x3FFFF
 #endif
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"netdev=eth0\0"				\
-	"inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0"	\
+	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
 	"loadaddr=0x40010000\0"			\
 	"uboot=u-boot.bin\0"			\
 	"load=tftp ${loadaddr} ${uboot}\0"	\
 	"upd=run load; run prog\0"		\
-	"prog=prot off " MK_STR(CFG_FLASH_BASE)	\
-	" " MK_STR(CFG_UBOOT_END) ";"		\
-	"era " MK_STR(CFG_FLASH_BASE) " "	\
-	MK_STR(CFG_UBOOT_END) ";"		\
-	"cp.b ${loadaddr} " MK_STR(CFG_FLASH_BASE)	\
+	"prog=prot off " MK_STR(CONFIG_SYS_FLASH_BASE)	\
+	" " MK_STR(CONFIG_SYS_UBOOT_END) ";"		\
+	"era " MK_STR(CONFIG_SYS_FLASH_BASE) " "	\
+	MK_STR(CONFIG_SYS_UBOOT_END) ";"		\
+	"cp.b ${loadaddr} " MK_STR(CONFIG_SYS_FLASH_BASE)	\
 	" ${filesize}; save\0"			\
 	""
 #endif
@@ -170,22 +170,22 @@
 #define CONFIG_ATAPI
 #undef CONFIG_LBA48
 
-#define CFG_IDE_MAXBUS		1
-#define CFG_IDE_MAXDEVICE	2
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	2
 
-#define CFG_ATA_BASE_ADDR	0x90000000
-#define CFG_ATA_IDE0_OFFSET	0
+#define CONFIG_SYS_ATA_BASE_ADDR	0x90000000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0
 
-#define CFG_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O                            */
-#define CFG_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
-#define CFG_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers           */
-#define CFG_ATA_STRIDE		4	/* Interval between registers                 */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O                            */
+#define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers           */
+#define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers                 */
 #define _IO_BASE		0
 
 /* Realtime clock */
 #define CONFIG_MCFRTC
 #undef RTC_DEBUG
-#define CFG_RTC_OSCILLATOR	(32 * CFG_HZ)
+#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)
 
 /* Timer */
 #define CONFIG_MCFTMR
@@ -195,21 +195,21 @@
 #define CONFIG_FSL_I2C
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged               */
-#define CFG_I2C_SPEED		80000	/* I2C speed and slave address  */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_OFFSET		0x58000
-#define CFG_IMMR		CFG_MBAR
+#define CONFIG_SYS_I2C_SPEED		80000	/* I2C speed and slave address  */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x58000
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
 
 /* DSPI and Serial Flash */
 #define CONFIG_CF_DSPI
 #define CONFIG_HARD_SPI
-#define CFG_SER_FLASH_BASE	0x01000000
-#define CFG_SBFHDR_SIZE		0x13
+#define CONFIG_SYS_SER_FLASH_BASE	0x01000000
+#define CONFIG_SYS_SBFHDR_SIZE		0x13
 #ifdef CONFIG_CMD_SPI
 #	define CONFIG_SPI_FLASH
 #	define CONFIG_SPI_FLASH_STMICRO
 
-#	define CFG_DSPI_DCTAR0		(DSPI_DCTAR_TRSZ(7) | \
+#	define CONFIG_SYS_DSPI_DCTAR0		(DSPI_DCTAR_TRSZ(7) | \
 					 DSPI_DCTAR_CPOL | \
 					 DSPI_DCTAR_CPHA | \
 					 DSPI_DCTAR_PCSSCK_1CLK | \
@@ -228,27 +228,27 @@
 #define CONFIG_PCI_PNP		1
 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
 
-#define CFG_PCI_CACHE_LINE_SIZE	4
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	4
 
-#define CFG_PCI_MEM_BUS		0xA0000000
-#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BUS
-#define CFG_PCI_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCI_MEM_BUS		0xA0000000
+#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BUS
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000
 
-#define CFG_PCI_IO_BUS		0xB1000000
-#define CFG_PCI_IO_PHYS		CFG_PCI_IO_BUS
-#define CFG_PCI_IO_SIZE		0x01000000
+#define CONFIG_SYS_PCI_IO_BUS		0xB1000000
+#define CONFIG_SYS_PCI_IO_PHYS		CONFIG_SYS_PCI_IO_BUS
+#define CONFIG_SYS_PCI_IO_SIZE		0x01000000
 
-#define CFG_PCI_CFG_BUS		0xB0000000
-#define CFG_PCI_CFG_PHYS	CFG_PCI_CFG_BUS
-#define CFG_PCI_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCI_CFG_BUS		0xB0000000
+#define CONFIG_SYS_PCI_CFG_PHYS	CONFIG_SYS_PCI_CFG_BUS
+#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
 #endif
 
 /* FPGA - Spartan 2 */
 /* experiment
-#define CONFIG_FPGA		CFG_SPARTAN3
+#define CONFIG_FPGA		CONFIG_SYS_SPARTAN3
 #define CONFIG_FPGA_COUNT	1
-#define CFG_FPGA_PROG_FEEDBACK
-#define CFG_FPGA_CHECK_CTRLC
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_CHECK_CTRLC
 */
 
 /* Input, PCI, Flexbus, and VCO */
@@ -256,23 +256,23 @@
 
 #define CONFIG_PRAM		2048	/* 2048 KB */
 
-#define CFG_PROMPT		"-> "
-#define CFG_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE			1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE			1024	/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE			256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE			256	/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 
-#define CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 0x10000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)
 
-#define CFG_HZ			1000
+#define CONFIG_SYS_HZ			1000
 
-#define CFG_MBAR		0xFC000000
+#define CONFIG_SYS_MBAR		0xFC000000
 
 /*
  * Low Level Configuration Settings
@@ -283,40 +283,40 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x80000000
-#define CFG_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
-#define CFG_INIT_RAM_CTRL	0x221
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 32)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-#define CFG_SBFHDR_DATA_OFFSET	(CFG_INIT_RAM_END - 32)
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - 32)
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x40000000
-#define CFG_SDRAM_BASE1		0x48000000
-#define CFG_SDRAM_SIZE		256	/* SDRAM size in MB */
-#define CFG_SDRAM_CFG1		0x65311610
-#define CFG_SDRAM_CFG2		0x59670000
-#define CFG_SDRAM_CTRL		0xEA0B2000
-#define CFG_SDRAM_EMOD		0x40010000
-#define CFG_SDRAM_MODE		0x00010033
-#define CFG_SDRAM_DRV_STRENGTH	0xAA
-
-#define CFG_MEMTEST_START	CFG_SDRAM_BASE + 0x400
-#define CFG_MEMTEST_END		((CFG_SDRAM_SIZE - 3) << 20)
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_BASE1		0x48000000
+#define CONFIG_SYS_SDRAM_SIZE		256	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x65311610
+#define CONFIG_SYS_SDRAM_CFG2		0x59670000
+#define CONFIG_SYS_SDRAM_CTRL		0xEA0B2000
+#define CONFIG_SYS_SDRAM_EMOD		0x40010000
+#define CONFIG_SYS_SDRAM_MODE		0x00010033
+#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0xAA
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 
 #ifdef CONFIG_CF_SBF
-#	define CFG_MONITOR_BASE	(TEXT_BASE + 0x400)
+#	define CONFIG_SYS_MONITOR_BASE	(TEXT_BASE + 0x400)
 #else
-#	define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
 #endif
-#define CFG_BOOTPARAMS_LEN	64*1024
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
 
 /*
  * For booting Linux, the board info and command line data
@@ -324,7 +324,7 @@
  * the maximum mapped by the Linux kernel during initialization ??
  */
 /* Initial Memory map for Linux */
-#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 
 /*
  * Configuration for environment
@@ -342,49 +342,49 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#ifdef CFG_STMICRO_BOOT
-#	define CFG_FLASH_BASE		CFG_SER_FLASH_BASE
-#	define CFG_FLASH0_BASE		CFG_SER_FLASH_BASE
-#	define CFG_FLASH1_BASE		CFG_CS0_BASE
-#	define CFG_FLASH2_BASE		CFG_CS1_BASE
+#ifdef CONFIG_SYS_STMICRO_BOOT
+#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_SER_FLASH_BASE
+#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_SER_FLASH_BASE
+#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH2_BASE		CONFIG_SYS_CS1_BASE
 #	define CONFIG_ENV_OFFSET		0x30000
 #	define CONFIG_ENV_SIZE		0x2000
 #	define CONFIG_ENV_SECT_SIZE	0x10000
 #endif
-#ifdef CFG_ATMEL_BOOT
-#	define CFG_FLASH_BASE		CFG_CS0_BASE
-#	define CFG_FLASH0_BASE		CFG_CS0_BASE
-#	define CFG_FLASH1_BASE		CFG_CS1_BASE
-#	define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x4000)
+#ifdef CONFIG_SYS_ATMEL_BOOT
+#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS1_BASE
+#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
 #	define CONFIG_ENV_SECT_SIZE	0x2000
 #endif
-#ifdef CFG_INTEL_BOOT
-#	define CFG_FLASH_BASE		CFG_CS0_BASE
-#	define CFG_FLASH0_BASE		CFG_CS0_BASE
-#	define CFG_FLASH1_BASE		CFG_CS1_BASE
-#	define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x40000)
+#ifdef CONFIG_SYS_INTEL_BOOT
+#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS1_BASE
+#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
 #	define CONFIG_ENV_SIZE		0x2000
 #	define CONFIG_ENV_SECT_SIZE	0x20000
 #endif
 
-#define CFG_FLASH_CFI
-#ifdef CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
 
 #	define CONFIG_FLASH_CFI_DRIVER	1
-#	define CFG_FLASH_SIZE		0x1000000	/* Max size that the board might have */
-#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
-#	define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#	define CFG_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
-#	define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
-#	define CFG_FLASH_CHECKSUM
-#	define CFG_FLASH_BANKS_LIST	{ CFG_CS0_BASE, CFG_CS1_BASE }
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
 #	define CONFIG_FLASH_CFI_LEGACY
 
 #ifdef CONFIG_FLASH_CFI_LEGACY
-#	define CFG_ATMEL_REGION		4
-#	define CFG_ATMEL_TOTALSECT	11
-#	define CFG_ATMEL_SECT		{1, 2, 1, 7}
-#	define CFG_ATMEL_SECTSZ		{0x4000, 0x2000, 0x8000, 0x10000}
+#	define CONFIG_SYS_ATMEL_REGION		4
+#	define CONFIG_SYS_ATMEL_TOTALSECT	11
+#	define CONFIG_SYS_ATMEL_SECT		{1, 2, 1, 7}
+#	define CONFIG_SYS_ATMEL_SECTSZ		{0x4000, 0x2000, 0x8000, 0x10000}
 #endif
 #endif
 
@@ -396,24 +396,24 @@
 #ifdef CF_STMICRO_BOOT
 #	define CONFIG_JFFS2_DEV		"nor1"
 #	define CONFIG_JFFS2_PART_SIZE	0x01000000
-#	define CONFIG_JFFS2_PART_OFFSET	(CFG_FLASH2_BASE + 0x500000)
+#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH2_BASE + 0x500000)
 #endif
-#ifdef CFG_ATMEL_BOOT
+#ifdef CONFIG_SYS_ATMEL_BOOT
 #	define CONFIG_JFFS2_DEV		"nor1"
 #	define CONFIG_JFFS2_PART_SIZE	0x01000000
-#	define CONFIG_JFFS2_PART_OFFSET	(CFG_FLASH1_BASE + 0x500000)
+#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH1_BASE + 0x500000)
 #endif
-#ifdef CFG_INTEL_BOOT
+#ifdef CONFIG_SYS_INTEL_BOOT
 #	define CONFIG_JFFS2_DEV		"nor0"
 #	define CONFIG_JFFS2_PART_SIZE	(0x01000000 - 0x500000)
-#	define CONFIG_JFFS2_PART_OFFSET	(CFG_FLASH0_BASE + 0x500000)
+#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
 #endif
 #endif
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE		16
+#define CONFIG_SYS_CACHELINE_SIZE		16
 
 /*-----------------------------------------------------------------------
  * Memory bank definitions
@@ -427,38 +427,38 @@
  * CS5 - Available
  */
 
-#if defined(CFG_ATMEL_BOOT) || defined(CFG_STMICRO_BOOT)
+#if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
  /* Atmel Flash */
-#define CFG_CS0_BASE		0x04000000
-#define CFG_CS0_MASK		0x00070001
-#define CFG_CS0_CTRL		0x00001140
+#define CONFIG_SYS_CS0_BASE		0x04000000
+#define CONFIG_SYS_CS0_MASK		0x00070001
+#define CONFIG_SYS_CS0_CTRL		0x00001140
 /* Intel Flash */
-#define CFG_CS1_BASE		0x00000000
-#define CFG_CS1_MASK		0x01FF0001
-#define CFG_CS1_CTRL		0x00000D60
+#define CONFIG_SYS_CS1_BASE		0x00000000
+#define CONFIG_SYS_CS1_MASK		0x01FF0001
+#define CONFIG_SYS_CS1_CTRL		0x00000D60
 
-#define CFG_ATMEL_BASE		CFG_CS0_BASE
+#define CONFIG_SYS_ATMEL_BASE		CONFIG_SYS_CS0_BASE
 #else
 /* Intel Flash */
-#define CFG_CS0_BASE		0x00000000
-#define CFG_CS0_MASK		0x01FF0001
-#define CFG_CS0_CTRL		0x00000D60
+#define CONFIG_SYS_CS0_BASE		0x00000000
+#define CONFIG_SYS_CS0_MASK		0x01FF0001
+#define CONFIG_SYS_CS0_CTRL		0x00000D60
  /* Atmel Flash */
-#define CFG_CS1_BASE		0x04000000
-#define CFG_CS1_MASK		0x00070001
-#define CFG_CS1_CTRL		0x00001140
+#define CONFIG_SYS_CS1_BASE		0x04000000
+#define CONFIG_SYS_CS1_MASK		0x00070001
+#define CONFIG_SYS_CS1_CTRL		0x00001140
 
-#define CFG_ATMEL_BASE		CFG_CS1_BASE
+#define CONFIG_SYS_ATMEL_BASE		CONFIG_SYS_CS1_BASE
 #endif
 
 /* CPLD */
-#define CFG_CS2_BASE		0x08000000
-#define CFG_CS2_MASK		0x00070001
-#define CFG_CS2_CTRL		0x003f1140
+#define CONFIG_SYS_CS2_BASE		0x08000000
+#define CONFIG_SYS_CS2_MASK		0x00070001
+#define CONFIG_SYS_CS2_CTRL		0x003f1140
 
 /* FPGA */
-#define CFG_CS3_BASE		0x09000000
-#define CFG_CS3_MASK		0x00070001
-#define CFG_CS3_CTRL		0x00000020
+#define CONFIG_SYS_CS3_BASE		0x09000000
+#define CONFIG_SYS_CS3_MASK		0x00070001
+#define CONFIG_SYS_CS3_CTRL		0x00000020
 
 #endif				/* _M54455EVB_H */
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index 37b1c60..e48de15 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -39,9 +39,9 @@
 #define CONFIG_M5475		/* define processor type */
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
 
 #define CONFIG_HW_WATCHDOG
 #define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
@@ -72,27 +72,27 @@
 #	define CONFIG_MII_INIT		1
 #	define CONFIG_HAS_ETH1
 
-#	define CFG_DMA_USE_INTSRAM	1
-#	define CFG_DISCOVER_PHY
-#	define CFG_RX_ETH_BUFFER	32
-#	define CFG_TX_ETH_BUFFER	48
-#	define CFG_FAULT_ECHO_LINK_DOWN
+#	define CONFIG_SYS_DMA_USE_INTSRAM	1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	32
+#	define CONFIG_SYS_TX_ETH_BUFFER	48
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 
-#	define CFG_FEC0_PINMUX		0
-#	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
-#	define CFG_FEC1_PINMUX		0
-#	define CFG_FEC1_MIIBASE		CFG_FEC0_IOBASE
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#	define CONFIG_SYS_FEC1_PINMUX		0
+#	define CONFIG_SYS_FEC1_MIIBASE		CONFIG_SYS_FEC0_IOBASE
 
 #	define MCFFEC_TOUT_LOOP		50000
-/* If CFG_DISCOVER_PHY is not defined - hardcoded */
-#	ifndef CFG_DISCOVER_PHY
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
 #		define FECDUPLEX	FULL
 #		define FECSPEED		_100BASET
 #	else
-#		ifndef CFG_FAULT_ECHO_LINK_DOWN
-#			define CFG_FAULT_ECHO_LINK_DOWN
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #		endif
-#	endif			/* CFG_DISCOVER_PHY */
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
 
 #	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
 #	define CONFIG_ETH1ADDR	00:e0:0c:bc:e5:61
@@ -114,21 +114,21 @@
 #	define CONFIG_PCI_OHCI
 #	define CONFIG_DOS_PARTITION
 
-#	undef CFG_USB_OHCI_BOARD_INIT
-#	undef CFG_USB_OHCI_CPU_INIT
-#	define CFG_USB_OHCI_MAX_ROOT_PORTS	15
-#	define CFG_USB_OHCI_SLOT_NAME		"isp1561"
-#	define CFG_OHCI_SWAP_REG_ACCESS
+#	undef CONFIG_SYS_USB_OHCI_BOARD_INIT
+#	undef CONFIG_SYS_USB_OHCI_CPU_INIT
+#	define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+#	define CONFIG_SYS_USB_OHCI_SLOT_NAME		"isp1561"
+#	define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #endif
 
 /* I2C */
 #define CONFIG_FSL_I2C
 #define CONFIG_HARD_I2C		/* I2C with hw support */
 #undef CONFIG_SOFT_I2C		/* I2C bit-banged */
-#define CFG_I2C_SPEED		80000
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_OFFSET		0x00008F00
-#define CFG_IMMR		CFG_MBAR
+#define CONFIG_SYS_I2C_SPEED		80000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x00008F00
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
 
 /* PCI */
 #ifdef CONFIG_CMD_PCI
@@ -136,19 +136,19 @@
 #define CONFIG_PCI_PNP		1
 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
 
-#define CFG_PCI_CACHE_LINE_SIZE	8
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	8
 
-#define CFG_PCI_MEM_BUS		0x80000000
-#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BUS
-#define CFG_PCI_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCI_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BUS
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000
 
-#define CFG_PCI_IO_BUS		0x71000000
-#define CFG_PCI_IO_PHYS		CFG_PCI_IO_BUS
-#define CFG_PCI_IO_SIZE		0x01000000
+#define CONFIG_SYS_PCI_IO_BUS		0x71000000
+#define CONFIG_SYS_PCI_IO_PHYS		CONFIG_SYS_PCI_IO_BUS
+#define CONFIG_SYS_PCI_IO_SIZE		0x01000000
 
-#define CFG_PCI_CFG_BUS		0x70000000
-#define CFG_PCI_CFG_PHYS	CFG_PCI_CFG_BUS
-#define CFG_PCI_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCI_CFG_BUS		0x70000000
+#define CONFIG_SYS_PCI_CFG_PHYS	CONFIG_SYS_PCI_CFG_BUS
+#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
 #endif
 
 #define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
@@ -177,29 +177,29 @@
 	""
 
 #define CONFIG_PRAM		512	/* 512 KB */
-#define CFG_PROMPT		"-> "
-#define CFG_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
 
 #ifdef CONFIG_CMD_KGDB
-#	define CFG_CBSIZE	1024	/* Console I/O Buffer Size */
+#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
 #else
-#	define CFG_CBSIZE	256	/* Console I/O Buffer Size */
+#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
-#define CFG_LOAD_ADDR		0x00010000
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LOAD_ADDR		0x00010000
 
-#define CFG_HZ			1000
-#define CFG_CLK			CFG_BUSCLK
-#define CFG_CPU_CLK		CFG_CLK * 2
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CLK			CONFIG_SYS_BUSCLK
+#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2
 
-#define CFG_MBAR		0xF0000000
-#define CFG_INTSRAM		(CFG_MBAR + 0x10000)
-#define CFG_INTSRAMSZ		0x8000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_INTSRAM		(CONFIG_SYS_MBAR + 0x10000)
+#define CONFIG_SYS_INTSRAMSZ		0x8000
 
-/*#define CFG_LATCH_ADDR		(CFG_CS1_BASE + 0x80000)*/
+/*#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)*/
 
 /*
  * Low Level Configuration Settings
@@ -209,68 +209,68 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0xF2000000
-#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM */
-#define CFG_INIT_RAM_CTRL	0x21
-#define CFG_INIT_RAM1_ADDR	(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_END)
-#define CFG_INIT_RAM1_END	0x1000	/* End of used area in internal SRAM */
-#define CFG_INIT_RAM1_CTRL	0x21
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0xF2000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x21
+#define CONFIG_SYS_INIT_RAM1_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_END)
+#define CONFIG_SYS_INIT_RAM1_END	0x1000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM1_CTRL	0x21
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_CFG1		0x73711630
-#define CFG_SDRAM_CFG2		0x46770000
-#define CFG_SDRAM_CTRL		0xE10B0000
-#define CFG_SDRAM_EMOD		0x40010000
-#define CFG_SDRAM_MODE		0x018D0000
-#define CFG_SDRAM_DRVSTRENGTH	0x000002AA
-#ifdef CFG_DRAMSZ1
-#	define CFG_SDRAM_SIZE	(CFG_DRAMSZ + CFG_DRAMSZ1)
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_CFG1		0x73711630
+#define CONFIG_SYS_SDRAM_CFG2		0x46770000
+#define CONFIG_SYS_SDRAM_CTRL		0xE10B0000
+#define CONFIG_SYS_SDRAM_EMOD		0x40010000
+#define CONFIG_SYS_SDRAM_MODE		0x018D0000
+#define CONFIG_SYS_SDRAM_DRVSTRENGTH	0x000002AA
+#ifdef CONFIG_SYS_DRAMSZ1
+#	define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
 #else
-#	define CFG_SDRAM_SIZE	CFG_DRAMSZ
+#	define CONFIG_SYS_SDRAM_SIZE	CONFIG_SYS_DRAMSZ
 #endif
 
-#define CFG_MEMTEST_START	CFG_SDRAM_BASE + 0x400
-#define CFG_MEMTEST_END		((CFG_SDRAM_SIZE - 3) << 20)
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
 
-#define CFG_BOOTPARAMS_LEN	64*1024
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_FLASH_CFI
-#ifdef CFG_FLASH_CFI
-#	define CFG_FLASH_BASE		(CFG_CS0_BASE)
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
 #	define CONFIG_FLASH_CFI_DRIVER	1
-#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#	define CFG_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
-#	define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
-#	define CFG_FLASH_USE_BUFFER_WRITE
-#ifdef CFG_NOR1SZ
-#	define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#	define CFG_FLASH_SIZE		((CFG_NOR1SZ + CFG_BOOTSZ) << 20)
-#	define CFG_FLASH_BANKS_LIST	{ CFG_CS0_BASE, CFG_CS1_BASE }
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_NOR1SZ
+#	define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#	define CONFIG_SYS_FLASH_SIZE		((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
 #else
-#	define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#	define CFG_FLASH_SIZE		(CFG_BOOTSZ << 20)
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_FLASH_SIZE		(CONFIG_SYS_BOOTSZ << 20)
 #endif
 #endif
 
@@ -285,7 +285,7 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
@@ -298,14 +298,14 @@
  * CS4 - Available
  * CS5 - Available
  */
-#define CFG_CS0_BASE		0xFF800000
-#define CFG_CS0_MASK		(((CFG_BOOTSZ << 20) - 1) & 0xFFFF0001)
-#define CFG_CS0_CTRL		0x00101980
-
-#ifdef CFG_NOR1SZ
-#define CFG_CS1_BASE		0xE0000000
-#define CFG_CS1_MASK		(((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001)
-#define CFG_CS1_CTRL		0x00101D80
+#define CONFIG_SYS_CS0_BASE		0xFF800000
+#define CONFIG_SYS_CS0_MASK		(((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
+#define CONFIG_SYS_CS0_CTRL		0x00101980
+
+#ifdef CONFIG_SYS_NOR1SZ
+#define CONFIG_SYS_CS1_BASE		0xE0000000
+#define CONFIG_SYS_CS1_MASK		(((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
+#define CONFIG_SYS_CS1_CTRL		0x00101D80
 #endif
 
 #endif				/* _M5475EVB_H */
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index 482136e..28bf0ad 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -39,9 +39,9 @@
 #define CONFIG_M5485		/* define processor type */
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
 
 #define CONFIG_HW_WATCHDOG
 #define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
@@ -72,27 +72,27 @@
 #	define CONFIG_MII_INIT		1
 #	define CONFIG_HAS_ETH1
 
-#	define CFG_DMA_USE_INTSRAM	1
-#	define CFG_DISCOVER_PHY
-#	define CFG_RX_ETH_BUFFER	32
-#	define CFG_TX_ETH_BUFFER	48
-#	define CFG_FAULT_ECHO_LINK_DOWN
+#	define CONFIG_SYS_DMA_USE_INTSRAM	1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	32
+#	define CONFIG_SYS_TX_ETH_BUFFER	48
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 
-#	define CFG_FEC0_PINMUX		0
-#	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
-#	define CFG_FEC1_PINMUX		0
-#	define CFG_FEC1_MIIBASE		CFG_FEC0_IOBASE
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#	define CONFIG_SYS_FEC1_PINMUX		0
+#	define CONFIG_SYS_FEC1_MIIBASE		CONFIG_SYS_FEC0_IOBASE
 
 #	define MCFFEC_TOUT_LOOP		50000
-/* If CFG_DISCOVER_PHY is not defined - hardcoded */
-#	ifndef CFG_DISCOVER_PHY
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
 #		define FECDUPLEX	FULL
 #		define FECSPEED		_100BASET
 #	else
-#		ifndef CFG_FAULT_ECHO_LINK_DOWN
-#			define CFG_FAULT_ECHO_LINK_DOWN
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #		endif
-#	endif			/* CFG_DISCOVER_PHY */
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
 
 #	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
 #	define CONFIG_ETH1ADDR	00:e0:0c:bc:e5:61
@@ -112,20 +112,20 @@
 #		define CONFIG_CMD_PCI
 #	endif
 /*#	define CONFIG_PCI_OHCI*/
-#	define CFG_USB_OHCI_REGS_BASE		0x80041000
-#	define CFG_USB_OHCI_MAX_ROOT_PORTS	15
-#	define CFG_USB_OHCI_SLOT_NAME		"isp1561"
-#	define CFG_OHCI_SWAP_REG_ACCESS
+#	define CONFIG_SYS_USB_OHCI_REGS_BASE		0x80041000
+#	define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+#	define CONFIG_SYS_USB_OHCI_SLOT_NAME		"isp1561"
+#	define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #endif
 
 /* I2C */
 #define CONFIG_FSL_I2C
 #define CONFIG_HARD_I2C		/* I2C with hw support */
 #undef CONFIG_SOFT_I2C		/* I2C bit-banged */
-#define CFG_I2C_SPEED		80000
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_OFFSET		0x00008F00
-#define CFG_IMMR		CFG_MBAR
+#define CONFIG_SYS_I2C_SPEED		80000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x00008F00
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
 
 /* PCI */
 #ifdef CONFIG_CMD_PCI
@@ -133,17 +133,17 @@
 #define CONFIG_PCI_PNP		1
 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
 
-#define CFG_PCI_MEM_BUS		0x80000000
-#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BUS
-#define CFG_PCI_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCI_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BUS
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000
 
-#define CFG_PCI_IO_BUS		0x71000000
-#define CFG_PCI_IO_PHYS		CFG_PCI_IO_BUS
-#define CFG_PCI_IO_SIZE		0x01000000
+#define CONFIG_SYS_PCI_IO_BUS		0x71000000
+#define CONFIG_SYS_PCI_IO_PHYS		CONFIG_SYS_PCI_IO_BUS
+#define CONFIG_SYS_PCI_IO_SIZE		0x01000000
 
-#define CFG_PCI_CFG_BUS		0x70000000
-#define CFG_PCI_CFG_PHYS	CFG_PCI_CFG_BUS
-#define CFG_PCI_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCI_CFG_BUS		0x70000000
+#define CONFIG_SYS_PCI_CFG_PHYS	CONFIG_SYS_PCI_CFG_BUS
+#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
 #endif
 
 #define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
@@ -163,29 +163,29 @@
 	""
 
 #define CONFIG_PRAM		512	/* 512 KB */
-#define CFG_PROMPT		"-> "
-#define CFG_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
 
 #ifdef CONFIG_CMD_KGDB
-#	define CFG_CBSIZE	1024	/* Console I/O Buffer Size */
+#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
 #else
-#	define CFG_CBSIZE	256	/* Console I/O Buffer Size */
+#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
-#define CFG_LOAD_ADDR		0x00010000
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LOAD_ADDR		0x00010000
 
-#define CFG_HZ			1000
-#define CFG_CLK			CFG_BUSCLK
-#define CFG_CPU_CLK		CFG_CLK * 2
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CLK			CONFIG_SYS_BUSCLK
+#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2
 
-#define CFG_MBAR		0xF0000000
-#define CFG_INTSRAM		(CFG_MBAR + 0x10000)
-#define CFG_INTSRAMSZ		0x8000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_INTSRAM		(CONFIG_SYS_MBAR + 0x10000)
+#define CONFIG_SYS_INTSRAMSZ		0x8000
 
-/*#define CFG_LATCH_ADDR		(CFG_CS1_BASE + 0x80000)*/
+/*#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)*/
 
 /*
  * Low Level Configuration Settings
@@ -195,68 +195,68 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0xF2000000
-#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM */
-#define CFG_INIT_RAM_CTRL	0x21
-#define CFG_INIT_RAM1_ADDR	(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_END)
-#define CFG_INIT_RAM1_END	0x1000	/* End of used area in internal SRAM */
-#define CFG_INIT_RAM1_CTRL	0x21
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0xF2000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x21
+#define CONFIG_SYS_INIT_RAM1_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_END)
+#define CONFIG_SYS_INIT_RAM1_END	0x1000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM1_CTRL	0x21
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_CFG1		0x73711630
-#define CFG_SDRAM_CFG2		0x46770000
-#define CFG_SDRAM_CTRL		0xE10B0000
-#define CFG_SDRAM_EMOD		0x40010000
-#define CFG_SDRAM_MODE		0x018D0000
-#define CFG_SDRAM_DRVSTRENGTH	0x000002AA
-#ifdef CFG_DRAMSZ1
-#	define CFG_SDRAM_SIZE	(CFG_DRAMSZ + CFG_DRAMSZ1)
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_CFG1		0x73711630
+#define CONFIG_SYS_SDRAM_CFG2		0x46770000
+#define CONFIG_SYS_SDRAM_CTRL		0xE10B0000
+#define CONFIG_SYS_SDRAM_EMOD		0x40010000
+#define CONFIG_SYS_SDRAM_MODE		0x018D0000
+#define CONFIG_SYS_SDRAM_DRVSTRENGTH	0x000002AA
+#ifdef CONFIG_SYS_DRAMSZ1
+#	define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
 #else
-#	define CFG_SDRAM_SIZE	CFG_DRAMSZ
+#	define CONFIG_SYS_SDRAM_SIZE	CONFIG_SYS_DRAMSZ
 #endif
 
-#define CFG_MEMTEST_START	CFG_SDRAM_BASE + 0x400
-#define CFG_MEMTEST_END		((CFG_SDRAM_SIZE - 3) << 20)
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
 
-#define CFG_BOOTPARAMS_LEN	64*1024
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_FLASH_CFI
-#ifdef CFG_FLASH_CFI
-#	define CFG_FLASH_BASE		(CFG_CS0_BASE)
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
 #	define CONFIG_FLASH_CFI_DRIVER	1
-#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#	define CFG_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
-#	define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
-#	define CFG_FLASH_USE_BUFFER_WRITE
-#ifdef CFG_NOR1SZ
-#	define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#	define CFG_FLASH_SIZE		((CFG_NOR1SZ + CFG_BOOTSZ) << 20)
-#	define CFG_FLASH_BANKS_LIST	{ CFG_CS0_BASE, CFG_CS1_BASE }
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_NOR1SZ
+#	define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#	define CONFIG_SYS_FLASH_SIZE		((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
 #else
-#	define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#	define CFG_FLASH_SIZE		(CFG_BOOTSZ << 20)
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_FLASH_SIZE		(CONFIG_SYS_BOOTSZ << 20)
 #endif
 #endif
 
@@ -271,7 +271,7 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
@@ -284,14 +284,14 @@
  * CS4 - Available
  * CS5 - Available
  */
-#define CFG_CS0_BASE		0xFF800000
-#define CFG_CS0_MASK		(((CFG_BOOTSZ << 20) - 1) & 0xFFFF0001)
-#define CFG_CS0_CTRL		0x00101980
-
-#ifdef CFG_NOR1SZ
-#define CFG_CS1_BASE		0xE0000000
-#define CFG_CS1_MASK		(((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001)
-#define CFG_CS1_CTRL		0x00101D80
+#define CONFIG_SYS_CS0_BASE		0xFF800000
+#define CONFIG_SYS_CS0_MASK		(((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
+#define CONFIG_SYS_CS0_CTRL		0x00101980
+
+#ifdef CONFIG_SYS_NOR1SZ
+#define CONFIG_SYS_CS1_BASE		0xE0000000
+#define CONFIG_SYS_CS1_MASK		(((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
+#define CONFIG_SYS_CS1_CTRL		0x00101D80
 #endif
 
 #endif				/* _M5485EVB_H */
diff --git a/include/configs/MBX.h b/include/configs/MBX.h
index fed4d73..5f7c7a8 100644
--- a/include/configs/MBX.h
+++ b/include/configs/MBX.h
@@ -67,7 +67,7 @@
 				"nfsaddrs=10.0.0.99:10.0.0.2"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE   /* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE   /* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -96,29 +96,29 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#undef	CFG_HUSH_PARSER			/* Hush parse for U-Boot	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#undef	CONFIG_SYS_HUSH_PARSER			/* Hush parse for U-Boot	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -129,62 +129,62 @@
 /*-----------------------------------------------------------------------
  * Physical memory map as defined by the MBX PGM
  */
-#define CFG_IMMR		0xFA200000 /* Internal Memory Mapped Register*/
-#define CFG_NVRAM_BASE		0xFA000000 /* NVRAM			     */
-#define CFG_NVRAM_OR		0xffe00000 /* w/o speed dependent flags!!    */
-#define CFG_CSR_BASE		0xFA100000 /* Control/Status Registers	     */
-#define CFG_PCIMEM_BASE		0x80000000 /* PCI I/O and Memory Spaces	     */
-#define CFG_PCIMEM_OR		0xA0000108
-#define CFG_PCIBRIDGE_BASE	0xFA210000 /* PCI-Bus Bridge Registers	     */
-#define CFG_PCIBRIDGE_OR	0xFFFF0108
+#define CONFIG_SYS_IMMR		0xFA200000 /* Internal Memory Mapped Register*/
+#define CONFIG_SYS_NVRAM_BASE		0xFA000000 /* NVRAM			     */
+#define CONFIG_SYS_NVRAM_OR		0xffe00000 /* w/o speed dependent flags!!    */
+#define CONFIG_SYS_CSR_BASE		0xFA100000 /* Control/Status Registers	     */
+#define CONFIG_SYS_PCIMEM_BASE		0x80000000 /* PCI I/O and Memory Spaces	     */
+#define CONFIG_SYS_PCIMEM_OR		0xA0000108
+#define CONFIG_SYS_PCIBRIDGE_BASE	0xFA210000 /* PCI-Bus Bridge Registers	     */
+#define CONFIG_SYS_PCIBRIDGE_OR	0xFFFF0108
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2f00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_VPD_SIZE	256 /* size in bytes reserved for vpd buffer */
-#define CFG_INIT_VPD_OFFSET	(CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE)
-#define CFG_INIT_SP_OFFSET	(CFG_INIT_VPD_OFFSET-8)
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2f00	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_VPD_SIZE	256 /* size in bytes reserved for vpd buffer */
+#define CONFIG_SYS_INIT_VPD_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_VPD_OFFSET-8)
 
 /*-----------------------------------------------------------------------
  * Offset in DPMEM where we keep the VPD data
  */
-#define CFG_DPRAMVPD		(CFG_INIT_VPD_OFFSET - 0x2000)
+#define CONFIG_SYS_DPRAMVPD		(CONFIG_SYS_INIT_VPD_OFFSET - 0x2000)
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xfe000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xfe000000
 #ifdef	DEBUG
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #endif
-#undef	CFG_MONITOR_BASE	/* 0x200000	   to run U-Boot from RAM */
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#undef	CONFIG_SYS_MONITOR_BASE	/* 0x200000	   to run U-Boot from RAM */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	16	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	16	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 /*-----------------------------------------------------------------------
  * NVRAM Configuration
@@ -194,15 +194,15 @@
  * access the NVRAM at the offset 0x1000.
  */
 #define CONFIG_ENV_IS_IN_NVRAM	1	/* turn on NVRAM env feature */
-#define CONFIG_ENV_ADDR		(CFG_NVRAM_BASE + 0x1000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_NVRAM_BASE + 0x1000)
 #define CONFIG_ENV_SIZE		0x1000
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -212,10 +212,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -223,22 +223,22 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-/* #define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC )
+/* #define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC )
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -246,7 +246,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit - leave PLL multiplication factor unchanged !
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -255,23 +255,23 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	(SCCR_RTDIV | SCCR_RTSEL)
-#define CFG_SCCR	SCCR_TBS
+#define CONFIG_SYS_SCCR	SCCR_TBS
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
-#define CFG_PCMCIA_INTERRUPT	SIU_LEVEL6
+#define CONFIG_SYS_PCMCIA_INTERRUPT	SIU_LEVEL6
 
 #define CONFIG_PCMCIA_SLOT_A	1
 
@@ -287,28 +287,28 @@
 #undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O */
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses */
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers */
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  * Debug Entry Mode
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER 0
+#define CONFIG_SYS_DER 0
 
 /*
  * Internal Definitions
diff --git a/include/configs/MBX860T.h b/include/configs/MBX860T.h
index cc05111..4cb3a69 100644
--- a/include/configs/MBX860T.h
+++ b/include/configs/MBX860T.h
@@ -56,21 +56,21 @@
 /*
  * Miscellaneous configurable options
  */
-#undef	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		":>"		/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#undef	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		":>"		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0800000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0800000	/* 4 ... 8 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -80,61 +80,61 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR			0xFFA00000
-#define CFG_IMMR_SIZE		((uint)(64 * 1024))
-#define CFG_NVRAM_BASE		0xFA000000 /* NVRAM                          */
-#define CFG_NVRAM_OR		0xffe00000 /* w/o speed dependent flags!!    */
-#define CFG_CSR_BASE		0xFA100000 /* Control/Status Registers       */
-#define CFG_PCIMEM_BASE		0x80000000 /* PCI I/O and Memory Spaces      */
-#define CFG_PCIMEM_OR		0xA0000108
-#define CFG_PCIBRIDGE_BASE	0xFA210000 /* PCI-Bus Bridge Registers       */
-#define CFG_PCIBRIDGE_OR	0xFFFF0108
+#define CONFIG_SYS_IMMR			0xFFA00000
+#define CONFIG_SYS_IMMR_SIZE		((uint)(64 * 1024))
+#define CONFIG_SYS_NVRAM_BASE		0xFA000000 /* NVRAM                          */
+#define CONFIG_SYS_NVRAM_OR		0xffe00000 /* w/o speed dependent flags!!    */
+#define CONFIG_SYS_CSR_BASE		0xFA100000 /* Control/Status Registers       */
+#define CONFIG_SYS_PCIMEM_BASE		0x80000000 /* PCI I/O and Memory Spaces      */
+#define CONFIG_SYS_PCIMEM_OR		0xA0000108
+#define CONFIG_SYS_PCIBRIDGE_BASE	0xFA210000 /* PCI-Bus Bridge Registers       */
+#define CONFIG_SYS_PCIBRIDGE_OR	0xFFFF0108
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2f00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_VPD_SIZE	256 /* size in bytes reserved for vpd buffer */
-#define CFG_INIT_VPD_OFFSET	(CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE)
-#define	CFG_INIT_SP_OFFSET	(CFG_INIT_VPD_OFFSET-8)
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2f00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_VPD_SIZE	256 /* size in bytes reserved for vpd buffer */
+#define CONFIG_SYS_INIT_VPD_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_VPD_OFFSET-8)
 
 /*-----------------------------------------------------------------------
  * Offset in DPMEM where we keep the VPD data
  */
-#define CFG_DPRAMVPD		(CFG_INIT_VPD_OFFSET - 0x2000)
+#define CONFIG_SYS_DPRAMVPD		(CONFIG_SYS_INIT_VPD_OFFSET - 0x2000)
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x00000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x00000000
 /*0xFE000000*/
-#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_HWINFO_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_HWINFO_LEN)
-#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
+#define CONFIG_SYS_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_HWINFO_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_SYS_HWINFO_LEN)
+#define	CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	4	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	16	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	4	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	16	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 /*-----------------------------------------------------------------------
  * NVRAM Configuration
@@ -144,15 +144,15 @@
  * access the NVRAM at the offset 0x1000.
  */
 #define CONFIG_ENV_IS_IN_NVRAM	1	/* turn on NVRAM env feature */
-#define CONFIG_ENV_ADDR		(CFG_NVRAM_BASE + 0x1000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_NVRAM_BASE + 0x1000)
 #define CONFIG_ENV_SIZE		0x1000
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -162,10 +162,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -173,21 +173,21 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -195,7 +195,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit - leave PLL multiplication factor unchanged !
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -204,14 +204,14 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	(SCCR_RTDIV | SCCR_RTSEL)
-#define CFG_SCCR	SCCR_TBS
+#define CONFIG_SYS_SCCR	SCCR_TBS
 
  /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER		0
+#define CONFIG_SYS_DER		0
 
 /* Because of the way the 860 starts up and assigns CS0 the
 * entire address space, we have to set the memory controller
@@ -235,20 +235,20 @@
 #define FLASH_BASE0_PRELIM	0xFE000000	/* FLASH bank #0	*/
 #define FLASH_BASE1_PRELIM	0xFF010000	/* FLASH bank #0	*/
 
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFFF00000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFFF00000	/* OR addr mask */
 
 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(0xFF800000 | OR_CSNT_SAM | OR_BI | OR_SCY_3_CLK)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
-#define CFG_BR0_PRELIM	(0xFE000000 | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(0xFF800000 | OR_CSNT_SAM | OR_BI | OR_SCY_3_CLK)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
+#define CONFIG_SYS_BR0_PRELIM	(0xFE000000 | BR_V )
 
 /* BCSRx - Board Control and Status Registers */
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	0xFFC00000 | OR_ACS_DIV4
-#define CFG_BR1_PRELIM	(0x00000000 | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	0xFFC00000 | OR_ACS_DIV4
+#define CONFIG_SYS_BR1_PRELIM	(0x00000000 | BR_MS_UPMA | BR_V )
 
 
 /*
@@ -256,30 +256,30 @@
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA		97		/* start with divider for 100 MHz	*/
+#define CONFIG_SYS_MAMR_PTA		97		/* start with divider for 100 MHz	*/
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
-#define CFG_MAMR		0x13821000
+#define CONFIG_SYS_MAMR		0x13821000
 /*
  * Internal Definitions
  *
diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h
index 16d2363..518173a 100644
--- a/include/configs/METROBOX.h
+++ b/include/configs/METROBOX.h
@@ -109,7 +109,7 @@
 #define CONFIG_BOARD_EARLY_INIT_F 1	     /* Call board_pre_init	*/
 #define CONFIG_MISC_INIT_F	  1	     /* Call board misc_init_f	*/
 #define CONFIG_MISC_INIT_R	  1	     /* Call board misc_init_r	*/
-#undef	CFG_DRAM_TEST			     /* Disable-takes long time!*/
+#undef	CONFIG_SYS_DRAM_TEST			     /* Disable-takes long time!*/
 #define CONFIG_SYS_CLK_FREQ	  66666666   /* external freq to pll	*/
 
 #define CONFIG_VERY_BIG_RAM 1
@@ -121,34 +121,34 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE	       0x00000000    /* _must_ be 0		*/
-#define CFG_FLASH_BASE	       0xfff80000    /* start of FLASH		*/
-#define CFG_MONITOR_BASE       0xfff80000    /* start of monitor	*/
-#define CFG_PCI_MEMBASE	       0x80000000    /* mapped pci memory	*/
-#define CFG_PERIPHERAL_BASE    0xe0000000    /* internal peripherals	*/
-#define CFG_ISRAM_BASE	       0xc0000000    /* internal SRAM		*/
-#define CFG_PCI_BASE	       0xd0000000    /* internal PCI regs	*/
-
-#define CFG_NVRAM_BASE_ADDR   (CFG_PERIPHERAL_BASE + 0x08000000)
-#define CFG_FPGA_BASE	      (CFG_PERIPHERAL_BASE + 0x08200000)
-#define CFG_BME32_BASE	      (CFG_PERIPHERAL_BASE + 0x08500000)
-#define CFG_GPIO_BASE	      (CFG_PERIPHERAL_BASE + 0x00000700)
+#define CONFIG_SYS_SDRAM_BASE	       0x00000000    /* _must_ be 0		*/
+#define CONFIG_SYS_FLASH_BASE	       0xfff80000    /* start of FLASH		*/
+#define CONFIG_SYS_MONITOR_BASE       0xfff80000    /* start of monitor	*/
+#define CONFIG_SYS_PCI_MEMBASE	       0x80000000    /* mapped pci memory	*/
+#define CONFIG_SYS_PERIPHERAL_BASE    0xe0000000    /* internal peripherals	*/
+#define CONFIG_SYS_ISRAM_BASE	       0xc0000000    /* internal SRAM		*/
+#define CONFIG_SYS_PCI_BASE	       0xd0000000    /* internal PCI regs	*/
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR   (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
+#define CONFIG_SYS_FPGA_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
+#define CONFIG_SYS_BME32_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
+#define CONFIG_SYS_GPIO_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
-#define CFG_TEMP_STACK_OCM    1
-#define CFG_OCM_DATA_ADDR     CFG_ISRAM_BASE
-#define CFG_INIT_RAM_ADDR     CFG_ISRAM_BASE /* Initial RAM address	*/
-#define CFG_INIT_RAM_END      0x2000	     /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE     128	     /* num bytes initial data	*/
+#define CONFIG_SYS_TEMP_STACK_OCM    1
+#define CONFIG_SYS_OCM_DATA_ADDR     CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR     CONFIG_SYS_ISRAM_BASE /* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_END      0x2000	     /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE     128	     /* num bytes initial data	*/
 
-#define CFG_GBL_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR    (CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET    CFG_POST_WORD_ADDR
+#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_POST_WORD_ADDR    (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_POST_WORD_ADDR
 
-#define CFG_MONITOR_LEN	      (256 * 1024)   /* Rsrv 256kB for Mon	*/
-#define CFG_MALLOC_LEN	      (128 * 1024)   /* Rsrv 128kB for malloc	*/
+#define CONFIG_SYS_MONITOR_LEN	      (256 * 1024)   /* Rsrv 256kB for Mon	*/
+#define CONFIG_SYS_MALLOC_LEN	      (128 * 1024)   /* Rsrv 128kB for malloc	*/
 
 /*-----------------------------------------------------------------------
  * Serial Port
@@ -157,7 +157,7 @@
 #define CONFIG_SERIAL_MULTI   1
 #define CONFIG_BAUDRATE	      9600
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
 /*-----------------------------------------------------------------------
@@ -167,21 +167,21 @@
  * The DS1743 code assumes this condition (i.e. -- it assumes the base
  * address for the RTC registers is:
  *
- *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *	CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
  *
  *----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE	      (0x2000 - 8)   /* NVRAM size(8k)- RTC regs*/
+#define CONFIG_SYS_NVRAM_SIZE	      (0x2000 - 8)   /* NVRAM size(8k)- RTC regs*/
 #define CONFIG_RTC_DS174x     1		     /* DS1743 RTC		*/
 
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS   1		     /* number of banks		*/
-#define CFG_MAX_FLASH_SECT    8		     /* sectors per device	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS   1		     /* number of banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT    8		     /* sectors per device	*/
 
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT  120000	     /* Flash Erase TO (in ms)	 */
-#define CFG_FLASH_WRITE_TOUT  500	     /* Flash Write TO(in ms)	 */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT  120000	     /* Flash Erase TO (in ms)	 */
+#define CONFIG_SYS_FLASH_WRITE_TOUT  500	     /* Flash Write TO(in ms)	 */
 
 /*-----------------------------------------------------------------------
  * DDR SDRAM
@@ -194,9 +194,9 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C	      1		     /* I2C hardware support	*/
 #undef	CONFIG_SOFT_I2C			     /* I2C !bit-banged		*/
-#define CFG_I2C_SPEED	      400000	     /* I2C speed 400kHz	*/
-#define CFG_I2C_SLAVE	      0x7F	     /* I2C slave address	*/
-#define CFG_I2C_NOPROBES      {0x69}	     /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_SPEED	      400000	     /* I2C speed 400kHz	*/
+#define CONFIG_SYS_I2C_SLAVE	      0x7F	     /* I2C slave address	*/
+#define CONFIG_SYS_I2C_NOPROBES      {0x69}	     /* Don't probe these addrs */
 #define CONFIG_I2C_BUS1	      1		     /* Include i2c bus 1 supp	*/
 
 
@@ -209,18 +209,19 @@
 #define CONFIG_ENV_OVERWRITE  1		     /* allow env overwrite	*/
 
 #define CONFIG_ENV_SIZE	      0x1000	     /* Size of Env vars	*/
-#define CONFIG_ENV_ADDR	      (CFG_NVRAM_BASE_ADDR)
+#define CONFIG_ENV_ADDR	      (CONFIG_SYS_NVRAM_BASE_ADDR)
 
 #define CONFIG_BOOTARGS	      "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none "
 #define CONFIG_BOOTCOMMAND    "tftp 8000000 pImage.metrobox;bootm 8000000"
 #define CONFIG_BOOTDELAY      5		    /* disable autoboot */
 
 #define CONFIG_LOADS_ECHO     1		     /* echo on for serial dnld */
-#define CFG_LOADS_BAUD_CHANGE 1		     /* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1		     /* allow baudrate change	*/
 
 /*-----------------------------------------------------------------------
  * Networking
  *----------------------------------------------------------------------*/
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII	      1		     /* MII PHY management	*/
 #define CONFIG_NET_MULTI      1
 #define CONFIG_PHY_ADDR	      0xff	     /* no phy on EMAC0		*/
@@ -239,7 +240,7 @@
 #define CONFIG_NETMASK	      255.255.0.0
 #define CONFIG_ETHADDR	      00:00:00:00:00:00 /* No EMAC 0 support	*/
 #define CONFIG_ETH1ADDR	      00:00:00:00:00:00 /* No EMAC 1 support	*/
-#define CFG_RX_ETH_BUFFER     32	     /* #eth rx buff & descrs	*/
+#define CONFIG_SYS_RX_ETH_BUFFER     32	     /* #eth rx buff & descrs	*/
 
 
 /*
@@ -277,33 +278,33 @@
 /* Include auto complete with tabs */
 #define CONFIG_AUTO_COMPLETE 1
 #define CONFIG_AUTO_COMPLETE 1
-#define CFG_ALT_MEMTEST	     1	     /* use real memory test	 */
+#define CONFIG_SYS_ALT_MEMTEST	     1	     /* use real memory test	 */
 
-#define CFG_LONGHELP			     /* undef to save memory	*/
-#define CFG_PROMPT	      "MetroBox=> "  /* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			     /* undef to save memory	*/
+#define CONFIG_SYS_PROMPT	      "MetroBox=> "  /* Monitor Command Prompt	*/
 
-#define CFG_HUSH_PARSER	       1	     /* HUSH for ext'd cli	*/
-#define CFG_PROMPT_HUSH_PS2    "> "
+#define CONFIG_SYS_HUSH_PARSER	       1	     /* HUSH for ext'd cli	*/
+#define CONFIG_SYS_PROMPT_HUSH_PS2    "> "
 
 
 /*-----------------------------------------------------------------------
  * Console Buffer
  *----------------------------------------------------------------------*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	      1024	     /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	      1024	     /* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE	      256	     /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	      256	     /* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 					     /* Print Buffer Size	*/
-#define CFG_MAXARGS	      16	     /* max number of cmd args	*/
-#define CFG_BARGSIZE	      CFG_CBSIZE     /* Boot Arg Buffer Size	*/
+#define CONFIG_SYS_MAXARGS	      16	     /* max number of cmd args	*/
+#define CONFIG_SYS_BARGSIZE	      CONFIG_SYS_CBSIZE     /* Boot Arg Buffer Size	*/
 
 /*-----------------------------------------------------------------------
  * Memory Test
  *----------------------------------------------------------------------*/
-#define CFG_MEMTEST_START     0x0400000	     /* memtest works on	*/
-#define CFG_MEMTEST_END	      0x0C00000	     /* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START     0x0400000	     /* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END	      0x0C00000	     /* 4 ... 12 MB in DRAM	*/
 
 /*-----------------------------------------------------------------------
  * Compact Flash (in true IDE mode)
@@ -312,16 +313,16 @@
 #undef	CONFIG_IDE_LED			/* no led for ide supported	*/
 
 #define CONFIG_IDE_RESET		/* reset for ide supported	*/
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR	0xF0000000
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#define CFG_ATA_DATA_OFFSET	0x0000	 /* Offset for data I/O */
-#define CFG_ATA_REG_OFFSET	0x0000	 /* Offset for normal register accesses*/
-#define CFG_ATA_ALT_OFFSET	0x100000 /* Offset for alternate registers */
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0000000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	 /* Offset for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	 /* Offset for normal register accesses*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x100000 /* Offset for alternate registers */
 
-#define CFG_ATA_STRIDE		2	 /* Directly connected CF, needs a stride
+#define CONFIG_SYS_ATA_STRIDE		2	 /* Directly connected CF, needs a stride
 					    to get to the correct offset */
 #define CONFIG_DOS_PARTITION  1		     /* Include dos partition	*/
 
@@ -332,20 +333,20 @@
 #define CONFIG_PCI			     /* include pci support	*/
 #define CONFIG_PCI_PNP			     /* do pci plug-and-play	*/
 #define CONFIG_PCI_SCAN_SHOW		     /* show pci devices	*/
-#define CFG_PCI_TARGBASE      (CFG_PCI_MEMBASE)
+#define CONFIG_SYS_PCI_TARGBASE      (CONFIG_SYS_PCI_MEMBASE)
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT		     /* let board init pci target*/
+#define CONFIG_SYS_PCI_TARGET_INIT		     /* let board init pci target*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x17BA	     /* Sandburst */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	     /* Whatever */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA	     /* Sandburst */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	     /* Whatever */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*
  * Internal Definitions
@@ -364,10 +365,10 @@
  * Miscellaneous configurable options
  *----------------------------------------------------------------------*/
 #undef CONFIG_WATCHDOG			     /* watchdog disabled	*/
-#define CFG_LOAD_ADDR	      0x8000000	     /* default load address	*/
-#define CFG_EXTBDINFO	      1		     /* use extended board_info */
+#define CONFIG_SYS_LOAD_ADDR	      0x8000000	     /* default load address	*/
+#define CONFIG_SYS_EXTBDINFO	      1		     /* use extended board_info */
 
-#define CFG_HZ		      100	     /* decr freq: 1 ms ticks	*/
+#define CONFIG_SYS_HZ		      100	     /* decr freq: 1 ms ticks	*/
 
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h
index a7901e5..8e7f9cd 100644
--- a/include/configs/MHPC.h
+++ b/include/configs/MHPC.h
@@ -63,7 +63,7 @@
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 #define CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
@@ -89,14 +89,14 @@
 			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
 #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
 
-#define CFG_I2C_SPEED			50000
-#define CFG_I2C_SLAVE			0xFE
-#define CFG_I2C_EEPROM_ADDR		0x50	/* EEPROM X24C04		*/
-#define CFG_I2C_EEPROM_ADDR_LEN		1	/* bytes of address		*/
+#define CONFIG_SYS_I2C_SPEED			50000
+#define CONFIG_SYS_I2C_SLAVE			0xFE
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* EEPROM X24C04		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1	/* bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 
 #define LCD_VIDEO_ADDR		(SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
 #define LCD_VIDEO_SIZE		SDRAM_RES_SIZE	/* 2MB */
@@ -142,25 +142,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x300000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x300000	/* default load address */
 
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -171,29 +171,29 @@
 /*-----------------------------------------------------------------------
  * Physical memory map
  */
-#define CFG_IMMR		0xFFF00000 /* Internal Memory Mapped Register*/
+#define CONFIG_SYS_IMMR		0xFFF00000 /* Internal Memory Mapped Register*/
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xfe000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xfe000000
 
-#define CFG_MONITOR_LEN		0x40000		/* Reserve 256 kB for Monitor	*/
-#undef	CFG_MONITOR_BASE		    /* to run U-Boot from RAM */
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_LEN		0x40000		/* Reserve 256 kB for Monitor	*/
+#undef	CONFIG_SYS_MONITOR_BASE		    /* to run U-Boot from RAM */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * JFFS2 partitions
@@ -218,26 +218,26 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map- for Linux	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map- for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET		CFG_MONITOR_LEN /* Offset of Environment */
+#define CONFIG_ENV_OFFSET		CONFIG_SYS_MONITOR_LEN /* Offset of Environment */
 #define CONFIG_ENV_SIZE		0x20000 /* Total Size of Environment	*/
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -247,10 +247,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWP)
 #endif
 
@@ -259,27 +259,27 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_SEME)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_SEME)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		12-18
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -290,7 +290,7 @@
 #define MPC8XX_SPEED	50000000L
 #define MPC8XX_XIN	5000000L      /* ref clk */
 #define MPC8XX_FACT	(MPC8XX_SPEED/MPC8XX_XIN)
-#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
 			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
@@ -301,7 +301,7 @@
  */
 
 #define SCCR_MASK	(SCCR_RTDIV | SCCR_RTSEL)     /* SCCR_EBDF11 */
-#define CFG_SCCR	(SCCR_TBS | SCCR_DFLCD001)
+#define CONFIG_SYS_SCCR	(SCCR_TBS | SCCR_DFLCD001)
 
 
 /*-----------------------------------------------------------------------
@@ -310,8 +310,8 @@
  *-----------------------------------------------------------------------
  * periodic timer for refresh
  */
-#define CFG_MAMR_PTA	0xC0
-#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)
+#define CONFIG_SYS_MAMR_PTA	0xC0
+#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)
 
 /*
  * BR0 and OR0 (FLASH) used to re-map FLASH
@@ -320,14 +320,14 @@
 /* allow for max 8 MB of Flash */
 #define FLASH_BASE		0xFE000000	/* FLASH bank #0*/
 #define FLASH_BASE0_PRELIM	0xFE000000	/* FLASH bank #0*/
-#define CFG_REMAP_OR_AM		0xFF800000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0xFF800000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
 
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )
 
 /*
  * BR1 and OR1 (SDRAM)
@@ -337,46 +337,46 @@
 #define SDRAM_RES_SIZE		0x00200000	/* 2 MB for framebuffer */
 
 /* SDRAM timing: drive GPL5 high on first cycle */
-#define CFG_OR_TIMING_SDRAM	(OR_G5LS)
+#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_G5LS)
 
-#define CFG_OR1_PRELIM	((~(SDRAM_MAX_SIZE)+1)| CFG_OR_TIMING_SDRAM )
-#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR1_PRELIM	((~(SDRAM_MAX_SIZE)+1)| CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /*
  * BR2/OR2 - DIMM
  */
-#define CFG_OR2		(OR_ACS_DIV4)
-#define CFG_BR2		(BR_MS_UPMA)
+#define CONFIG_SYS_OR2		(OR_ACS_DIV4)
+#define CONFIG_SYS_BR2		(BR_MS_UPMA)
 
 /*
  * BR3/OR3 - DIMM
  */
-#define CFG_OR3		(OR_ACS_DIV4)
-#define CFG_BR3		(BR_MS_UPMA)
+#define CONFIG_SYS_OR3		(OR_ACS_DIV4)
+#define CONFIG_SYS_BR3		(BR_MS_UPMA)
 
 /*
  * BR4/OR4
  */
-#define CFG_OR4		0
-#define CFG_BR4		0
+#define CONFIG_SYS_OR4		0
+#define CONFIG_SYS_BR4		0
 
 /*
  * BR5/OR5
  */
-#define CFG_OR5		0
-#define CFG_BR5		0
+#define CONFIG_SYS_OR5		0
+#define CONFIG_SYS_BR5		0
 
 /*
  * BR6/OR6
  */
-#define CFG_OR6		0
-#define CFG_BR6		0
+#define CONFIG_SYS_OR6		0
+#define CONFIG_SYS_BR6		0
 
 /*
  * BR7/OR7
  */
-#define CFG_OR7		0
-#define CFG_BR7		0
+#define CONFIG_SYS_OR7		0
+#define CONFIG_SYS_BR7		0
 
 
 /*-----------------------------------------------------------------------
@@ -384,7 +384,7 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER 0
+#define CONFIG_SYS_DER 0
 
 /*
  * Internal Definitions
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 4527c17..c58ce05 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -90,8 +90,8 @@
 
 #define CONFIG_NAND_LEGACY
 
-#define	 CFG_HUSH_PARSER
-#define	 CFG_PROMPT_HUSH_PS2 "> "
+#define	 CONFIG_SYS_HUSH_PARSER
+#define	 CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 /**************************************************************
  * I2C Stuff:
  * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
@@ -100,18 +100,17 @@
  ***************************************************************/
 
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		50000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		50000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x53	/* EEPROM 24C128/256		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x53	/* EEPROM 24C128/256		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"    */
-#undef CFG_I2C_EEPROM_ADDR_OVERFLOW
-#define CFG_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel 24C128/256 has	*/
+#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel 24C128/256 has	*/
 					/* 64 byte page write mode using*/
 					/* last	6 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_ENABLE	/* enable Page write */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
 
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
@@ -143,54 +142,54 @@
 /***************************************************************
  * defines if the console is stored in the environment
  ***************************************************************/
-#define CFG_CONSOLE_IS_IN_ENV	/* stdin, stdout and stderr are in evironment */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* stdin, stdout and stderr are in evironment */
 /***************************************************************
  * defines if an overwrite_console function exists
  *************************************************************/
-#define CFG_CONSOLE_OVERWRITE_ROUTINE
-#define CFG_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
 /***************************************************************
  * defines if the overwrite_console should be stored in the
  * environment
  **************************************************************/
-#undef CFG_CONSOLE_ENV_OVERWRITE
+#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 
 /**************************************************************
  * loads config
  *************************************************************/
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MISC_INIT_R
 /***********************************************************
  * Miscellaneous configurable options
  **********************************************************/
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 1 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 1 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_BASE_BAUD       916667
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD       916667
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x400000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x400000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -204,40 +203,40 @@
 #define CONFIG_PCI_HOST PCI_HOST_FORCE	/* configure as pci-host	*/
 #define CONFIG_PCI_PNP			/* pci plug-and-play		*/
 					/* resource configuration	*/
-#define CFG_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFF80000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserve 1024 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFF80000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserve 1024 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 /*
  * JFFS2 partitions
@@ -270,10 +269,10 @@
  * POST Configuration
  */
 #if 0 /* enable this if POST is desired (is supported but not enabled) */
-#define CONFIG_POST		(CFG_POST_MEMORY	| \
-				 CFG_POST_CPU		| \
-				 CFG_POST_RTC		| \
-				 CFG_POST_I2C)
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY	| \
+				 CONFIG_SYS_POST_CPU		| \
+				 CONFIG_SYS_POST_RTC		| \
+				 CONFIG_SYS_POST_I2C)
 
 #endif
 /*
@@ -298,22 +297,22 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in On Chip SRAM)
  */
-#define CFG_TEMP_STACK_OCM      1
-#define CFG_OCM_DATA_ADDR	0xF0000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE	/* End of On Chip SRAM	       */
-#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_TEMP_STACK_OCM      1
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE	/* End of On Chip SRAM	       */
+#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 /* reserve some memory for POST and BOOT limit info */
-#define CFG_INIT_SP_OFFSET	(CFG_GBL_DATA_OFFSET - 32)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 32)
 
 #ifdef  CONFIG_POST		/* reserve one word for POST Info */
-#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 4)
+#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 4)
 #endif
 
 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
-#define CFG_BOOTCOUNT_ADDR (CFG_GBL_DATA_OFFSET - 12)
+#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
 #endif
 
 /*
@@ -328,7 +327,7 @@
 /***********************************************************************
  * External peripheral base address
  ***********************************************************************/
-#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
 
 /***********************************************************************
  * Last Stage Init
@@ -337,6 +336,7 @@
 /************************************************************
  * Ethernet Stuff
  ***********************************************************/
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		1	/* PHY address			*/
 #define CONFIG_PHY_RESET_DELAY	300	/* Intel LXT971A needs this */
@@ -351,19 +351,19 @@
  * IDE/ATA stuff
  ************************************************************/
 #if defined(CONFIG_MIP405T)
-#define CFG_IDE_MAXBUS		1   /* MIP405T has only one IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1   /* MIP405T has only one IDE bus	*/
 #else
-#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
 #endif
 
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR	CFG_ISA_IO_BASE_ADDRESS /* base address */
-#define CFG_ATA_IDE0_OFFSET	0x01F0		/* ide0 offste */
-#define CFG_ATA_IDE1_OFFSET	0x0170		/* ide1 offset */
-#define CFG_ATA_DATA_OFFSET	0		/* data reg offset	*/
-#define CFG_ATA_REG_OFFSET	0		/* reg offset */
-#define CFG_ATA_ALT_OFFSET	0x200		/* alternate register offset */
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x01F0		/* ide0 offste */
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0x0170		/* ide1 offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0		/* data reg offset	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0		/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x200		/* alternate register offset */
 
 #undef	CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
 #undef	CONFIG_IDE_LED	       /* no led for ide supported     */
@@ -385,10 +385,10 @@
 /************************************************************
  * Disk-On-Chip configuration
  ************************************************************/
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
-#define CFG_DOC_SHORT_TIMEOUT
-#define CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
+#define CONFIG_SYS_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
+#define CONFIG_SYS_DOC_SHORT_TIMEOUT
+#define CONFIG_SYS_DOC_SUPPORT_2000
+#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
 /************************************************************
  * Keyboard support
  ************************************************************/
@@ -414,7 +414,7 @@
 #define CONFIG_USB_STORAGE
 
 /* Enable needed helper functions */
-#define CFG_DEVICE_DEREGISTER		/* needs device_deregister */
+#define CONFIG_SYS_DEVICE_DEREGISTER		/* needs device_deregister */
 #endif
 /************************************************************
  * Debug support
diff --git a/include/configs/ML2.h b/include/configs/ML2.h
index 11323db..1902397 100644
--- a/include/configs/ML2.h
+++ b/include/configs/ML2.h
@@ -73,7 +73,7 @@
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 
 /*
@@ -111,77 +111,77 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
 /*
- * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
  * The Linux BASE_BAUD define should match this configuration.
  *    baseBaud = cpuClock/(uartDivisor*16)
- * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  * set Linux BASE_BAUD to 403200.
  */
-#undef  CFG_EXT_SERIAL_CLOCK           /* external serial clock */
-#undef  CFG_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
-
-#define CFG_BASE_BAUD       (3125000*16)
-#define CFG_NS16550_CLK CFG_BASE_BAUD
-#define CFG_DUART_CHAN		0
-#define CFG_NS16550_COM1	0xa0001003
-#define CFG_NS16550_COM2	0xa0011003
-#define CFG_NS16550_REG_SIZE -4
-#define CFG_NS16550 1
-#define CFG_INIT_CHAN1	 1
-#define CFG_INIT_CHAN2	 1
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
+#undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
+
+#define CONFIG_SYS_BASE_BAUD       (3125000*16)
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_BASE_BAUD
+#define CONFIG_SYS_DUART_CHAN		0
+#define CONFIG_SYS_NS16550_COM1	0xa0001003
+#define CONFIG_SYS_NS16550_COM2	0xa0011003
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550 1
+#define CONFIG_SYS_INIT_CHAN1	 1
+#define CONFIG_SYS_INIT_CHAN2	 1
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x18000000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x18000000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 /* BEG ENVIRONNEMENT FLASH */
 #ifdef CONFIG_ENV_IS_IN_FLASH
@@ -193,13 +193,13 @@
 /*-----------------------------------------------------------------------
  * NVRAM organization
  */
-#define CFG_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
 
 #ifdef CONFIG_ENV_IS_IN_NVRAM
 #define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
 #define CONFIG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
 #endif
 
 /*
@@ -208,7 +208,7 @@
  * BR0/1 and OR0/1 (FLASH)
  */
 
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	*/
 #define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
 
 
@@ -219,11 +219,11 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 
-#define CFG_INIT_RAM_ADDR       0x800000  /* inside of SDRAM                     */
-#define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR       0x800000  /* inside of SDRAM                     */
+#define CONFIG_SYS_INIT_RAM_END        0x2000  /* End of used area in RAM             */
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for Serial Presence Detect EEPROM address
diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h
index b69ced6..986590a 100644
--- a/include/configs/MOUSSE.h
+++ b/include/configs/MOUSSE.h
@@ -48,7 +48,7 @@
 #define CONFIG_MPC824X      1
 #define CONFIG_MPC8240      1
 #define CONFIG_MOUSSE       1
-#define CFG_ADDR_MAP_B      1
+#define CONFIG_SYS_ADDR_MAP_B      1
 #define CONFIG_CONS_INDEX   1
 #define CONFIG_BAUDRATE     9600
 #if 1
@@ -88,75 +88,75 @@
 /*
  * Miscellaneous configurable options
  */
-#undef CFG_LONGHELP                /* undef to save memory     */
-#define CFG_PROMPT      "=>"  /* Monitor Command Prompt   */
-#define CFG_CBSIZE      256        /* Console I/O Buffer Size  */
-#define CFG_PBSIZE      (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS     8           /* Max number of command args   */
+#undef CONFIG_SYS_LONGHELP                /* undef to save memory     */
+#define CONFIG_SYS_PROMPT      "=>"  /* Monitor Command Prompt   */
+#define CONFIG_SYS_CBSIZE      256        /* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE      (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS     8           /* Max number of command args   */
 
-#define CFG_BARGSIZE    CFG_CBSIZE  /* Boot Argument Buffer Size    */
-#define CFG_LOAD_ADDR   0x00100000  /* Default load address         */
+#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LOAD_ADDR   0x00100000  /* Default load address         */
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE      0x00000000
+#define CONFIG_SYS_SDRAM_BASE      0x00000000
 
 #ifdef DEBUG
-#define CFG_MONITOR_BASE    CFG_SDRAM_BASE
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_SDRAM_BASE
 #else
-#define CFG_MONITOR_BASE    CFG_FLASH_BASE
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_FLASH_BASE
 #endif
 
 #ifdef DEBUG
-#define CFG_MONITOR_LEN     (4 << 20)	/* lots of mem ... */
+#define CONFIG_SYS_MONITOR_LEN     (4 << 20)	/* lots of mem ... */
 #else
-#define CFG_MONITOR_LEN     (512 << 10)	/* 512K PLCC bootrom */
+#define CONFIG_SYS_MONITOR_LEN     (512 << 10)	/* 512K PLCC bootrom */
 #endif
-#define CFG_MALLOC_LEN      (2*(4096 << 10))    /* 2*4096kB for malloc()  */
+#define CONFIG_SYS_MALLOC_LEN      (2*(4096 << 10))    /* 2*4096kB for malloc()  */
 
-#define CFG_MEMTEST_START   0x00004000	/* memtest works on      */
-#define CFG_MEMTEST_END     0x02000000	/* 0 ... 32 MB in DRAM   */
+#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on      */
+#define CONFIG_SYS_MEMTEST_END     0x02000000	/* 0 ... 32 MB in DRAM   */
 
 
-#define CFG_EUMB_ADDR       0xFC000000
+#define CONFIG_SYS_EUMB_ADDR       0xFC000000
 
-#define CFG_ISA_MEM         0xFD000000
-#define CFG_ISA_IO          0xFE000000
+#define CONFIG_SYS_ISA_MEM         0xFD000000
+#define CONFIG_SYS_ISA_IO          0xFE000000
 
-#define CFG_FLASH_BASE      0xFFF00000
-#define CFG_FLASH_SIZE      ((uint)(512 * 1024))
-#define CFG_RESET_ADDRESS   0xFFF00100
+#define CONFIG_SYS_FLASH_BASE      0xFFF00000
+#define CONFIG_SYS_FLASH_SIZE      ((uint)(512 * 1024))
+#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 #define FLASH_BASE0_PRELIM  0xFFF00000  /* 512K PLCC FLASH/AM29F040*/
 #define FLASH_BASE0_SIZE    0x80000     /* 512K */
 #define FLASH_BASE1_PRELIM  0xFFE10000  /* AMD 29LV160DB
 					   1MB - 64K FLASH0 SEG =960K
 					   (size=0xf0000)*/
 
-#define CFG_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
 
-#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_REG_SIZE	1
 
-#define CFG_NS16550_CLK		18432000
+#define CONFIG_SYS_NS16550_CLK		18432000
 
-#define CFG_NS16550_COM1	0xFFE08080
+#define CONFIG_SYS_NS16550_COM1	0xFFE08080
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN
-#define CFG_INIT_RAM_END   0x2F00  /* End of used area in DPRAM  */
-#define CFG_GBL_DATA_SIZE  64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET  CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
+#define CONFIG_SYS_INIT_RAM_END   0x2F00  /* End of used area in DPRAM  */
+#define CONFIG_SYS_GBL_DATA_SIZE  64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Low Level Configuration Settings
@@ -167,24 +167,24 @@
 
 #define CONFIG_SYS_CLK_FREQ  33000000	/* external frequency to pll */
 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2
-#define CFG_HZ               1000
+#define CONFIG_SYS_HZ               1000
 
-#define CFG_ETH_DEV_FN       0x00
-#define CFG_ETH_IOBASE       0x00104000
+#define CONFIG_SYS_ETH_DEV_FN       0x00
+#define CONFIG_SYS_ETH_IOBASE       0x00104000
 
 
 	/* Bit-field values for MCCR1.
 	 */
-#define CFG_ROMNAL          8
-#define CFG_ROMFAL          8
+#define CONFIG_SYS_ROMNAL          8
+#define CONFIG_SYS_ROMFAL          8
 
 	/* Bit-field values for MCCR2.
 	 */
-#define CFG_REFINT          0xf5     /* Refresh interval               */
+#define CONFIG_SYS_REFINT          0xf5     /* Refresh interval               */
 
 	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 	 */
-#define CFG_BSTOPRE         0x79
+#define CONFIG_SYS_BSTOPRE         0x79
 
 #ifdef INCLUDE_ECC
 #define USE_ECC				1
@@ -195,18 +195,18 @@
 
 	/* Bit-field values for MCCR3.
 	 */
-#define CFG_REFREC          8       /* Refresh to activate interval   */
-#define CFG_RDLAT           (4+USE_ECC)   /* Data latancy from read command */
+#define CONFIG_SYS_REFREC          8       /* Refresh to activate interval   */
+#define CONFIG_SYS_RDLAT           (4+USE_ECC)   /* Data latancy from read command */
 
 	/* Bit-field values for MCCR4.
 	 */
-#define CFG_PRETOACT        3       /* Precharge to activate interval */
-#define CFG_ACTTOPRE        5       /* Activate to Precharge interval */
-#define CFG_SDMODE_CAS_LAT  3       /* SDMODE CAS latancy             */
-#define CFG_SDMODE_WRAP     0       /* SDMODE wrap type               */
-#define CFG_SDMODE_BURSTLEN 2       /* SDMODE Burst length            */
-#define CFG_ACTORW          2
-#define CFG_REGISTERD_TYPE_BUFFER (1-USE_ECC)
+#define CONFIG_SYS_PRETOACT        3       /* Precharge to activate interval */
+#define CONFIG_SYS_ACTTOPRE        5       /* Activate to Precharge interval */
+#define CONFIG_SYS_SDMODE_CAS_LAT  3       /* SDMODE CAS latancy             */
+#define CONFIG_SYS_SDMODE_WRAP     0       /* SDMODE wrap type               */
+#define CONFIG_SYS_SDMODE_BURSTLEN 2       /* SDMODE Burst length            */
+#define CONFIG_SYS_ACTORW          2
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER (1-USE_ECC)
 
 /* Memory bank settings.
  * Only bits 20-29 are actually used from these vales to set the
@@ -214,71 +214,71 @@
  * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
  * address. Refer to the MPC8240 book.
  */
-#define CFG_RAM_SIZE        0x04000000  /* 64MB */
-
-
-#define CFG_BANK0_START     0x00000000
-#define CFG_BANK0_END       (CFG_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START     0x3ff00000
-#define CFG_BANK1_END       0x3fffffff
-#define CFG_BANK1_ENABLE    0
-#define CFG_BANK2_START     0x3ff00000
-#define CFG_BANK2_END       0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START     0x3ff00000
-#define CFG_BANK3_END       0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START     0x3ff00000
-#define CFG_BANK4_END       0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START     0x3ff00000
-#define CFG_BANK5_END       0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START     0x3ff00000
-#define CFG_BANK6_END       0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START     0x3ff00000
-#define CFG_BANK7_END       0x3fffffff
-#define CFG_BANK7_ENABLE    0
-
-#define CFG_ODCR            0x7f
-
-
-#define CFG_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory
+#define CONFIG_SYS_RAM_SIZE        0x04000000  /* 64MB */
+
+
+#define CONFIG_SYS_BANK0_START     0x00000000
+#define CONFIG_SYS_BANK0_END       (CONFIG_SYS_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE    1
+#define CONFIG_SYS_BANK1_START     0x3ff00000
+#define CONFIG_SYS_BANK1_END       0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE    0
+#define CONFIG_SYS_BANK2_START     0x3ff00000
+#define CONFIG_SYS_BANK2_END       0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE    0
+#define CONFIG_SYS_BANK3_START     0x3ff00000
+#define CONFIG_SYS_BANK3_END       0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE    0
+#define CONFIG_SYS_BANK4_START     0x3ff00000
+#define CONFIG_SYS_BANK4_END       0x3fffffff
+#define CONFIG_SYS_BANK4_ENABLE    0
+#define CONFIG_SYS_BANK5_START     0x3ff00000
+#define CONFIG_SYS_BANK5_END       0x3fffffff
+#define CONFIG_SYS_BANK5_ENABLE    0
+#define CONFIG_SYS_BANK6_START     0x3ff00000
+#define CONFIG_SYS_BANK6_END       0x3fffffff
+#define CONFIG_SYS_BANK6_ENABLE    0
+#define CONFIG_SYS_BANK7_START     0x3ff00000
+#define CONFIG_SYS_BANK7_END       0x3fffffff
+#define CONFIG_SYS_BANK7_ENABLE    0
+
+#define CONFIG_SYS_ODCR            0x7f
+
+
+#define CONFIG_SYS_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory
 				    see 8240 book for details*/
 #define PCI_MEM_SPACE1_START	0x80000000
 #define PCI_MEM_SPACE2_START	0xfd000000
 
 /* IBAT/DBAT Configuration */
 /* Ram: 64MB, starts at address-0, r/w instruction/data */
-#define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
-#define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_DBAT0U      CFG_IBAT0U
-#define CFG_DBAT0L      CFG_IBAT0L
+#define CONFIG_SYS_IBAT0U      (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT0U      CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT0L      CONFIG_SYS_IBAT0L
 
 /* MPLD/Port-X I/O Space : data and instruction read/write,  cache-inhibit */
-#define CFG_IBAT1U      (PORTX_DEV_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1U      (PORTX_DEV_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
 #if 0
-#define CFG_IBAT1L      (PORTX_DEV_BASE | BATL_PP_10  | BATL_MEMCOHERENCE |\
+#define CONFIG_SYS_IBAT1L      (PORTX_DEV_BASE | BATL_PP_10  | BATL_MEMCOHERENCE |\
 			 BATL_WRITETHROUGH | BATL_CACHEINHIBIT)
 #else
-#define CFG_IBAT1L      (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1L      (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT)
 #endif
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT1L	CFG_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
 
 /* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */
-#define CFG_IBAT2U	(PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_IBAT2L	(PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT)
-#define CFG_DBAT2U      CFG_IBAT2U
-#define CFG_DBAT2L      CFG_IBAT2L
+#define CONFIG_SYS_IBAT2U	(PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT2U      CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT2L      CONFIG_SYS_IBAT2L
 
 /* PCI Memory region 2: PCI Devices in 0xFD space */
-#define CFG_IBAT3U	(PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_IBAT3L	(PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
-#define CFG_DBAT3U      CFG_IBAT3U
-#define CFG_DBAT3L      CFG_IBAT3L
+#define CONFIG_SYS_IBAT3U	(PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT3U      CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT3L      CONFIG_SYS_IBAT3L
 
 
 /*
@@ -286,16 +286,16 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ       (8 << 20)   /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ       (8 << 20)   /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS     3       /* Max number of flash banks         */
-#define CFG_MAX_FLASH_SECT      64      /* Max number of sectors in one bank */
+#define CONFIG_SYS_MAX_FLASH_BANKS     3       /* Max number of flash banks         */
+#define CONFIG_SYS_MAX_FLASH_SECT      64      /* Max number of sectors in one bank */
 
-#define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)   */
-#define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)   */
+#define CONFIG_SYS_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)   */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)   */
 
 #if 0
 #define	CONFIG_ENV_IS_IN_FLASH	    1
@@ -310,7 +310,7 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE  16
+#define CONFIG_SYS_CACHELINE_SIZE  16
 
 
 /*
diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h
index 763ad4c..42fbe90 100644
--- a/include/configs/MPC8260ADS.h
+++ b/include/configs/MPC8260ADS.h
@@ -52,24 +52,24 @@
  * Figure out if we are booting low via flash HRCW or high via the BCSR.
  */
 #if (TEXT_BASE != 0xFFF00000)		/* Boot low (flash HRCW) */
-#   define CFG_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT		1
 #endif
 
 /* ADS flavours */
-#define CFG_8260ADS		1	/* MPC8260ADS */
-#define CFG_8266ADS		2	/* MPC8266ADS */
-#define CFG_PQ2FADS		3	/* PQ2FADS-ZU or PQ2FADS-VR */
-#define CFG_8272ADS		4	/* MPC8272ADS */
+#define CONFIG_SYS_8260ADS		1	/* MPC8260ADS */
+#define CONFIG_SYS_8266ADS		2	/* MPC8266ADS */
+#define CONFIG_SYS_PQ2FADS		3	/* PQ2FADS-ZU or PQ2FADS-VR */
+#define CONFIG_SYS_8272ADS		4	/* MPC8272ADS */
 
 #ifndef CONFIG_ADSTYPE
-#define CONFIG_ADSTYPE		CFG_8260ADS
+#define CONFIG_ADSTYPE		CONFIG_SYS_8260ADS
 #endif /* CONFIG_ADSTYPE */
 
-#if CONFIG_ADSTYPE == CFG_8272ADS
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 #define CONFIG_MPC8272		1
 #else
 #define CONFIG_MPC8260		1
-#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 
@@ -113,26 +113,26 @@
 
 #if   CONFIG_ETHER_INDEX == 1
 
-# define CFG_PHY_ADDR		0
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
-# define CFG_CMXFCR_MASK	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
+# define CONFIG_SYS_PHY_ADDR		0
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
 
 #elif CONFIG_ETHER_INDEX == 2
 
-#if CONFIG_ADSTYPE == CFG_8272ADS	/* RxCLK is CLK15, TxCLK is CLK16 */
-# define CFG_PHY_ADDR		3
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS	/* RxCLK is CLK15, TxCLK is CLK16 */
+# define CONFIG_SYS_PHY_ADDR		3
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
 #else					/* RxCLK is CLK13, TxCLK is CLK14 */
-# define CFG_PHY_ADDR		0
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
+# define CONFIG_SYS_PHY_ADDR		0
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
 
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 
 #endif	/* CONFIG_ETHER_INDEX */
 
-#define CFG_CPMFCR_RAMTYPE	0		/* BDs and buffers on 60x bus */
-#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)  /* Full duplex */
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0		/* BDs and buffers on 60x bus */
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)  /* Full duplex */
 
 #define CONFIG_MII			/* MII PHY management		*/
 #define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
@@ -141,39 +141,39 @@
  */
 #define MDIO_PORT	2		/* Port C */
 
-#if CONFIG_ADSTYPE == CFG_8272ADS
-#define CFG_MDIO_PIN	0x00002000	/* PC18 */
-#define CFG_MDC_PIN	0x00001000	/* PC19 */
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
+#define CONFIG_SYS_MDIO_PIN	0x00002000	/* PC18 */
+#define CONFIG_SYS_MDC_PIN	0x00001000	/* PC19 */
 #else
-#define CFG_MDIO_PIN	0x00400000	/* PC9	*/
-#define CFG_MDC_PIN	0x00200000	/* PC10 */
-#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
+#define CONFIG_SYS_MDIO_PIN	0x00400000	/* PC9	*/
+#define CONFIG_SYS_MDC_PIN	0x00200000	/* PC10 */
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
 
-#define MDIO_ACTIVE	(iop->pdir |=  CFG_MDIO_PIN)
-#define MDIO_TRISTATE	(iop->pdir &= ~CFG_MDIO_PIN)
-#define MDIO_READ	((iop->pdat &  CFG_MDIO_PIN) != 0)
+#define MDIO_ACTIVE	(iop->pdir |=  CONFIG_SYS_MDIO_PIN)
+#define MDIO_TRISTATE	(iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
+#define MDIO_READ	((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 
-#define MDIO(bit)	if(bit) iop->pdat |=  CFG_MDIO_PIN; \
-			else	iop->pdat &= ~CFG_MDIO_PIN
+#define MDIO(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
+			else	iop->pdat &= ~CONFIG_SYS_MDIO_PIN
 
-#define MDC(bit)	if(bit) iop->pdat |=  CFG_MDC_PIN; \
-			else	iop->pdat &= ~CFG_MDC_PIN
+#define MDC(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
+			else	iop->pdat &= ~CONFIG_SYS_MDC_PIN
 
 #define MIIDELAY	udelay(1)
 
 #endif /* CONFIG_ETHER_ON_FCC */
 
-#if CONFIG_ADSTYPE >= CFG_PQ2FADS
+#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
 #undef CONFIG_SPD_EEPROM	/* On new boards, SDRAM is soldered */
 #else
 #define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
 #define CONFIG_SPD_ADDR		0x50
 #endif
-#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
+#endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
 
 /*PCI*/
 #ifdef CONFIG_MPC8272
@@ -188,7 +188,7 @@
 #endif
 
 #ifndef CONFIG_8260_CLKIN
-#if CONFIG_ADSTYPE >= CFG_PQ2FADS
+#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
 #define CONFIG_8260_CLKIN	100000000	/* in Hz */
 #else
 #define CONFIG_8260_CLKIN	66000000	/* in Hz */
@@ -237,11 +237,11 @@
 
 #undef CONFIG_CMD_XIMG
 
-#if CONFIG_ADSTYPE == CFG_8272ADS
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
     #undef CONFIG_CMD_SDRAM
     #undef CONFIG_CMD_I2C
 
-#elif CONFIG_ADSTYPE >= CFG_PQ2FADS
+#elif CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
     #undef CONFIG_CMD_SDRAM
     #undef CONFIG_CMD_I2C
     #undef CONFIG_CMD_PCI
@@ -249,7 +249,7 @@
 #else
     #undef CONFIG_CMD_PCI
 
-#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
+#endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
 
 
 #define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds */
@@ -270,37 +270,37 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt   */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE	256			/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE	256			/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS	16			/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16			/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x400000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#define CFG_FLASH_BASE		0xff800000
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	32	/* max num of sects on one chip */
-#define CFG_FLASH_SIZE		8
-#define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)    */
-#define CFG_FLASH_WRITE_TOUT	5	/* Timeout for Flash Write (in ms)    */
-#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_BASE		0xff800000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	32	/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_SIZE		8
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)    */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	5	/* Timeout for Flash Write (in ms)    */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
 
 /*
  * JFFS2 partitions
@@ -309,20 +309,20 @@
  */
 #define MTDIDS_DEFAULT		"nor0=mpc8260ads-0"
 #define MTDPARTS_DEFAULT	"mtdparts=mpc8260ads-0:-@1m(jffs2)"
-#define CFG_JFFS2_SORT_FRAGMENTS
+#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
 
 /* this is stuff came out of the Motorola docs */
-#ifndef CFG_LOWBOOT
-#define CFG_DEFAULT_IMMR	0x0F010000
+#ifndef CONFIG_SYS_LOWBOOT
+#define CONFIG_SYS_DEFAULT_IMMR	0x0F010000
 #endif
 
-#define CFG_IMMR		0xF0000000
-#define CFG_BCSR		0xF4500000
-#if CONFIG_ADSTYPE == CFG_8272ADS
-#define CFG_PCI_INT		0xF8200000
+#define CONFIG_SYS_IMMR		0xF0000000
+#define CONFIG_SYS_BCSR		0xF4500000
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
+#define CONFIG_SYS_PCI_INT		0xF8200000
 #endif
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_LSDRAM_BASE		0xFD000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_LSDRAM_BASE		0xFD000000
 
 #define RS232EN_1		0x02000002
 #define RS232EN_2		0x01000001
@@ -332,127 +332,127 @@
 #define FETH2_RST		0x08000000
 #define BCSR_PCI_MODE		0x01000000
 
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#ifdef CFG_LOWBOOT
+#ifdef CONFIG_SYS_LOWBOOT
 /* PQ2FADS flash HRCW = 0x0EB4B645 */
-#define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )			    |\
+#define CONFIG_SYS_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )			    |\
 			    ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 )    |\
 			    ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
 			    ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )	     \
 			)
 #else
 /* PQ2FADS BCSR HRCW = 0x0CB23645 */
-#define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )			    |\
+#define CONFIG_SYS_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )			    |\
 			    ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 )    |\
 			    ( HRCW_BMS | HRCW_APPC10 )			    |\
 			    ( HRCW_MODCK_H0101 )			     \
 			)
 #endif
 /* no slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
+#define CONFIG_SYS_HRCW_SLAVE1 0
+#define CONFIG_SYS_HRCW_SLAVE2 0
+#define CONFIG_SYS_HRCW_SLAVE3 0
+#define CONFIG_SYS_HRCW_SLAVE4 0
+#define CONFIG_SYS_HRCW_SLAVE5 0
+#define CONFIG_SYS_HRCW_SLAVE6 0
+#define CONFIG_SYS_HRCW_SLAVE7 0
 
 #define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM	0x02	/* Software reboot	     */
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 #ifdef CONFIG_BZIP2
-#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
 #else
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()	*/
 #endif /* CONFIG_BZIP2 */
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 #  define CONFIG_ENV_IS_IN_FLASH	1
 #  define CONFIG_ENV_SECT_SIZE	0x40000
-#  define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
+#  define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
 #else
 #  define CONFIG_ENV_IS_IN_NVRAM	1
-#  define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#  define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #  define CONFIG_ENV_SIZE		0x200
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE )
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE )
 
-#define CFG_HID2		0
+#define CONFIG_SYS_HID2		0
 
-#define CFG_SYPCR		0xFFFFFFC3
-#define CFG_BCR			0x100C0000
-#define CFG_SIUMCR		0x0A200000
-#define CFG_SCCR		SCCR_DFBRG01
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | 0x00001801)
-#define CFG_OR0_PRELIM		0xFF800876
-#define CFG_BR1_PRELIM		(CFG_BCSR | 0x00001801)
-#define CFG_OR1_PRELIM		0xFFFF8010
+#define CONFIG_SYS_SYPCR		0xFFFFFFC3
+#define CONFIG_SYS_BCR			0x100C0000
+#define CONFIG_SYS_SIUMCR		0x0A200000
+#define CONFIG_SYS_SCCR		SCCR_DFBRG01
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | 0x00001801)
+#define CONFIG_SYS_OR0_PRELIM		0xFF800876
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR | 0x00001801)
+#define CONFIG_SYS_OR1_PRELIM		0xFFFF8010
 
 /*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
 
-#if CONFIG_ADSTYPE == CFG_8272ADS
-#define CFG_BR3_PRELIM	(CFG_PCI_INT | 0x1801)	/* PCI interrupt controller */
-#define CFG_OR3_PRELIM	0xFFFF8010
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_PCI_INT | 0x1801)	/* PCI interrupt controller */
+#define CONFIG_SYS_OR3_PRELIM	0xFFFF8010
 #endif
 
-#define CFG_RMR			RMR_CSRE
-#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CFG_RCCR		0
-
-#if (CONFIG_ADSTYPE == CFG_8266ADS) || (CONFIG_ADSTYPE == CFG_8272ADS)
-#undef CFG_LSDRAM_BASE		/* No local bus SDRAM on these boards */
-#endif /* CONFIG_ADSTYPE == CFG_8266ADS */
-
-#if CONFIG_ADSTYPE == CFG_PQ2FADS
-#define CFG_OR2			0xFE002EC0
-#define CFG_PSDMR		0x824B36A3
-#define CFG_PSRT		0x13
-#define CFG_LSDMR		0x828737A3
-#define CFG_LSRT		0x13
-#define CFG_MPTPR		0x2800
-#elif CONFIG_ADSTYPE == CFG_8272ADS
-#define CFG_OR2			0xFC002CC0
-#define CFG_PSDMR		0x834E24A3
-#define CFG_PSRT		0x13
-#define CFG_MPTPR		0x2800
+#define CONFIG_SYS_RMR			RMR_CSRE
+#define CONFIG_SYS_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_RCCR		0
+
+#if (CONFIG_ADSTYPE == CONFIG_SYS_8266ADS) || (CONFIG_ADSTYPE == CONFIG_SYS_8272ADS)
+#undef CONFIG_SYS_LSDRAM_BASE		/* No local bus SDRAM on these boards */
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8266ADS */
+
+#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
+#define CONFIG_SYS_OR2			0xFE002EC0
+#define CONFIG_SYS_PSDMR		0x824B36A3
+#define CONFIG_SYS_PSRT		0x13
+#define CONFIG_SYS_LSDMR		0x828737A3
+#define CONFIG_SYS_LSRT		0x13
+#define CONFIG_SYS_MPTPR		0x2800
+#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
+#define CONFIG_SYS_OR2			0xFC002CC0
+#define CONFIG_SYS_PSDMR		0x834E24A3
+#define CONFIG_SYS_PSRT		0x13
+#define CONFIG_SYS_MPTPR		0x2800
 #else
-#define CFG_OR2			0xFF000CA0
-#define CFG_PSDMR		0x016EB452
-#define CFG_PSRT		0x21
-#define CFG_LSDMR		0x0086A522
-#define CFG_LSRT		0x21
-#define CFG_MPTPR		0x1900
-#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
+#define CONFIG_SYS_OR2			0xFF000CA0
+#define CONFIG_SYS_PSDMR		0x016EB452
+#define CONFIG_SYS_PSRT		0x21
+#define CONFIG_SYS_LSDMR		0x0086A522
+#define CONFIG_SYS_LSRT		0x21
+#define CONFIG_SYS_MPTPR		0x1900
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
 
-#define CFG_RESET_ADDRESS	0x04400000
+#define CONFIG_SYS_RESET_ADDRESS	0x04400000
 
-#if CONFIG_ADSTYPE == CFG_8272ADS
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 
 /* PCI Memory map (if different from default map */
-#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */
-#define CFG_PCI_SLV_MEM_BUS		0x00000000		/* PCI base */
-#define CFG_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE		/* Local base */
+#define CONFIG_SYS_PCI_SLV_MEM_BUS		0x00000000		/* PCI base */
+#define CONFIG_SYS_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
 				 PICMR_PREFETCH_EN)
 
 /*
@@ -468,11 +468,11 @@
  * in the bridge.
  */
 
-#define CFG_PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
-#define CFG_PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
-#define	CFG_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
-#define CFG_PCI_MSTR_MEM_SIZE	0x20000000          /* 512MB */
-#define CFG_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
+#define CONFIG_SYS_PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
+#define	CONFIG_SYS_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
+#define CONFIG_SYS_PCI_MSTR_MEM_SIZE	0x20000000          /* 512MB */
+#define CONFIG_SYS_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 
 /*
  * Master window that allows the CPU to access PCI Memory (non-prefetch).
@@ -480,11 +480,11 @@
  * in the bridge.
  */
 
-#define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
-#define CFG_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
-#define CFG_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
-#define CFG_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
-#define CFG_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
+#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
+#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
+#define CONFIG_SYS_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
+#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
+#define CONFIG_SYS_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
 
 /*
  * Master window that allows the CPU to access PCI IO space.
@@ -492,23 +492,23 @@
  * in the bridge.
  */
 
-#define CFG_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
-#define CFG_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
-#define CFG_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
-#define CFG_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
-#define CFG_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
+#define CONFIG_SYS_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
+#define CONFIG_SYS_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
+#define CONFIG_SYS_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
+#define CONFIG_SYS_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
+#define CONFIG_SYS_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
 
 
 /* PCIBR0 - for PCI IO*/
-#define CFG_PCI_MSTR0_LOCAL		CFG_PCI_MSTR_IO_LOCAL		/* Local base */
-#define CFG_PCIMSK0_MASK		~(CFG_PCI_MSTR_IO_SIZE - 1U)	/* Size of window */
+#define CONFIG_SYS_PCI_MSTR0_LOCAL		CONFIG_SYS_PCI_MSTR_IO_LOCAL		/* Local base */
+#define CONFIG_SYS_PCIMSK0_MASK		~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U)	/* Size of window */
 /* PCIBR1 - prefetch and non-prefetch regions joined together */
-#define CFG_PCI_MSTR1_LOCAL		CFG_PCI_MSTR_MEM_LOCAL
-#define CFG_PCIMSK1_MASK		~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U)
+#define CONFIG_SYS_PCI_MSTR1_LOCAL		CONFIG_SYS_PCI_MSTR_MEM_LOCAL
+#define CONFIG_SYS_PCIMSK1_MASK		~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
 
 #endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
 
-#if CONFIG_ADSTYPE == CFG_8272ADS
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 #define CONFIG_HAS_ETH1
 #endif
 
diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
index 26c6fbe..fe1cc17 100644
--- a/include/configs/MPC8266ADS.h
+++ b/include/configs/MPC8266ADS.h
@@ -36,7 +36,7 @@
    !!  To make it work for the default, the TEXT_BASE define in	      !!
    !!  board/mpc8266ads/config.mk must be changed from 0xfe000000 to  !!
    !!  0xfff00000						      !!
-   !!  The CFG_HRCW_MASTER define below must also be changed to match !!
+   !!  The CONFIG_SYS_HRCW_MASTER define below must also be changed to match !!
    !!								      !!
    !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
  */
@@ -115,18 +115,18 @@
  * - Select bus for bd/buffers (see 28-13)
  * - Half duplex
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 
 #endif	/* CONFIG_ETHER_INDEX */
 
 /* other options */
 #define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 
 /* PCI */
 #define CONFIG_PCI
@@ -218,47 +218,47 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE	256			/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE	256			/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS	16			/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16			/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
 #undef CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in MHz */
 					/* for versions < 2.4.5-pre5	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#define CFG_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
 #define FLASH_BASE		0xFE000000
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	32	/* max num of sects on one chip */
-#define CFG_FLASH_SIZE		8
-#define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)    */
-#define CFG_FLASH_WRITE_TOUT	5	/* Timeout for Flash Write (in ms)    */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	32	/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_SIZE		8
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)    */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	5	/* Timeout for Flash Write (in ms)    */
 
-#undef	CFG_FLASH_CHECKSUM
+#undef	CONFIG_SYS_FLASH_CHECKSUM
 
 /* this is stuff came out of the Motorola docs */
 /* Only change this if you also change the Hardware configuration Word */
-#define CFG_DEFAULT_IMMR	0x0F010000
+#define CONFIG_SYS_DEFAULT_IMMR	0x0F010000
 
 /* Set IMMR to 0xF0000000 or above to boot Linux  */
-#define CFG_IMMR		0xF0000000
-#define CFG_BCSR		0xF8000000
-#define CFG_PCI_INT		0xF8200000	/* PCI interrupt controller */
+#define CONFIG_SYS_IMMR		0xF0000000
+#define CONFIG_SYS_BCSR		0xF8000000
+#define CONFIG_SYS_PCI_INT		0xF8200000	/* PCI interrupt controller */
 
 /* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
  */
@@ -267,8 +267,8 @@
 /* What should be the base address of SDRAM DIMM and how big is
  * it (in Mbytes)?  This will normally auto-configure via the SPD.
 */
-#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 16
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_SIZE 16
 
 #define SDRAM_SPD_ADDR 0x50
 
@@ -295,12 +295,12 @@
  *     - No data pipelining is done
  *     - Valid
  */
-#define CFG_BR2_PRELIM	((CFG_SDRAM_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
 			 BRx_PS_64			|\
 			 BRx_MS_SDRAM_P			|\
 			 BRx_V)
 
-#define CFG_BR3_PRELIM	((CFG_SDRAM_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
 			 BRx_PS_64			|\
 			 BRx_MS_SDRAM_P			|\
 			 BRx_V)
@@ -314,13 +314,13 @@
  *     - Back-to-back page mode
  *     - Internal bank interleaving within save device enabled
  */
-#if (CFG_SDRAM_SIZE == 64)
-#define CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM_SIZE)	|\
+#if (CONFIG_SYS_SDRAM_SIZE == 64)
+#define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE)	|\
 			 ORxS_BPD_4			|\
 			 ORxS_ROWST_PBI0_A8		|\
 			 ORxS_NUMR_12)
-#elif (CFG_SDRAM_SIZE == 16)
-#define CFG_OR2_PRELIM	(0xFF000C80)
+#elif (CONFIG_SYS_SDRAM_SIZE == 16)
+#define CONFIG_SYS_OR2_PRELIM	(0xFF000C80)
 #else
 #error "INVALID SDRAM CONFIGURATION"
 #endif
@@ -331,7 +331,7 @@
  *-----------------------------------------------------------------------
  */
 
-#if (CFG_SDRAM_SIZE == 64)
+#if (CONFIG_SYS_SDRAM_SIZE == 64)
 /* With a 64 MB DIMM, the PSDMR is configured as follows:
  *
  *     - Bank Based Interleaving,
@@ -349,7 +349,7 @@
  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
  *     - CAS Latency is 2.
  */
-#define CFG_PSDMR	(PSDMR_RFEN	      |\
+#define CONFIG_SYS_PSDMR	(PSDMR_RFEN	      |\
 			 PSDMR_SDAM_A14_IS_A5 |\
 			 PSDMR_BSMA_A14_A16   |\
 			 PSDMR_SDA10_PBI0_A9  |\
@@ -359,12 +359,12 @@
 			 PSDMR_LDOTOPRE_1C    |\
 			 PSDMR_WRC_1C	      |\
 			 PSDMR_CL_2)
-#elif (CFG_SDRAM_SIZE == 16)
+#elif (CONFIG_SYS_SDRAM_SIZE == 16)
 /* With a 16 MB DIMM, the PSDMR is configured as follows:
  *
  *   configuration parameters found in Motorola documentation
  */
-#define CFG_PSDMR	(0x016EB452)
+#define CONFIG_SYS_PSDMR	(0x016EB452)
 #else
 #error "INVALID SDRAM CONFIGURATION"
 #endif
@@ -374,22 +374,22 @@
 #define FETHIEN			0x08000008
 #define FETH_RST		0x04000004
 
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2)  */
 /* 0x0EB2B645 */
-#define CFG_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP )				|\
+#define CONFIG_SYS_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP )				|\
 			 ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 )		|\
 			 ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 )	|\
 			 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )			\
 			)
 
 /* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3)  */
-/* #define CFG_HRCW_MASTER 0x0cb23645 */
+/* #define CONFIG_SYS_HRCW_MASTER 0x0cb23645 */
 
 /* This value should actually be situated in the first 256 bytes of the FLASH
 	which on the standard MPC8266ADS board is at address 0xFF800000
@@ -406,39 +406,39 @@
 */
 
 /* no slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
+#define CONFIG_SYS_HRCW_SLAVE1 0
+#define CONFIG_SYS_HRCW_SLAVE2 0
+#define CONFIG_SYS_HRCW_SLAVE3 0
+#define CONFIG_SYS_HRCW_SLAVE4 0
+#define CONFIG_SYS_HRCW_SLAVE5 0
+#define CONFIG_SYS_HRCW_SLAVE6 0
+#define CONFIG_SYS_HRCW_SLAVE7 0
 
 #define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM	0x02	/* Software reboot	     */
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 #  define CONFIG_ENV_IS_IN_FLASH	1
-#    define CONFIG_ENV_ADDR	(CFG_MONITOR_BASE + 0x40000)
+#    define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE + 0x40000)
 #    define CONFIG_ENV_SECT_SIZE	0x40000
 #else
 #  define CONFIG_ENV_IS_IN_NVRAM	1
-#  define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#  define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #  define CONFIG_ENV_SIZE		0x200
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -451,22 +451,22 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-/*#define CFG_HID0_INIT		0 */
-#define CFG_HID0_INIT	(HID0_ICE  |\
+/*#define CONFIG_SYS_HID0_INIT		0 */
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE  |\
 			 HID0_DCE  |\
 			 HID0_ICFI |\
 			 HID0_DCI  |\
 			 HID0_IFEM |\
 			 HID0_ABE)
 
-#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE )
+#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE )
 
-#define CFG_HID2		0
+#define CONFIG_SYS_HID2		0
 
-#define CFG_SYPCR		0xFFFFFFC3
-#define CFG_BCR			0x004C0000
-#define CFG_SIUMCR		0x4E64C000
-#define CFG_SCCR		0x00000000
+#define CONFIG_SYS_SYPCR		0xFFFFFFC3
+#define CONFIG_SYS_BCR			0x004C0000
+#define CONFIG_SYS_SIUMCR		0x4E64C000
+#define CONFIG_SYS_SCCR		0x00000000
 
 /*	local bus memory map
  *
@@ -481,31 +481,31 @@
  *	0xF8300000-0xF8307FFF	 32KB	EEPROM
  *	0xFE000000-0xFFFFFFFF	 32MB	flash
  */
-#define CFG_BR0_PRELIM	0xFE001801		/* flash */
-#define CFG_OR0_PRELIM	0xFE000836
-#define CFG_BR1_PRELIM	(CFG_BCSR | 0x1801)	/* BCSR */
-#define CFG_OR1_PRELIM	0xFFFF8010
-#define CFG_BR4_PRELIM	0xF8300801		/* EEPROM */
-#define CFG_OR4_PRELIM	0xFFFF8846
-#define CFG_BR5_PRELIM	0xF8100801		/* PM5350 ATM UNI */
-#define CFG_OR5_PRELIM	0xFFFF8E36
-#define CFG_BR8_PRELIM	(CFG_PCI_INT | 0x1801)	/* PCI interrupt controller */
-#define CFG_OR8_PRELIM	0xFFFF8010
-
-#define CFG_RMR			0x0001
-#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CFG_RCCR		0
-#define CFG_MPTPR		0x00001900
-#define CFG_PSRT		0x00000021
+#define CONFIG_SYS_BR0_PRELIM	0xFE001801		/* flash */
+#define CONFIG_SYS_OR0_PRELIM	0xFE000836
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_BCSR | 0x1801)	/* BCSR */
+#define CONFIG_SYS_OR1_PRELIM	0xFFFF8010
+#define CONFIG_SYS_BR4_PRELIM	0xF8300801		/* EEPROM */
+#define CONFIG_SYS_OR4_PRELIM	0xFFFF8846
+#define CONFIG_SYS_BR5_PRELIM	0xF8100801		/* PM5350 ATM UNI */
+#define CONFIG_SYS_OR5_PRELIM	0xFFFF8E36
+#define CONFIG_SYS_BR8_PRELIM	(CONFIG_SYS_PCI_INT | 0x1801)	/* PCI interrupt controller */
+#define CONFIG_SYS_OR8_PRELIM	0xFFFF8010
+
+#define CONFIG_SYS_RMR			0x0001
+#define CONFIG_SYS_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_RCCR		0
+#define CONFIG_SYS_MPTPR		0x00001900
+#define CONFIG_SYS_PSRT		0x00000021
 
 /* This address must not exist */
-#define CFG_RESET_ADDRESS	0xFCFFFF00
+#define CONFIG_SYS_RESET_ADDRESS	0xFCFFFF00
 
 /* PCI Memory map (if different from default map */
-#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */
-#define CFG_PCI_SLV_MEM_BUS		0x00000000		/* PCI base */
-#define CFG_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE		/* Local base */
+#define CONFIG_SYS_PCI_SLV_MEM_BUS		0x00000000		/* PCI base */
+#define CONFIG_SYS_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
 				 PICMR_PREFETCH_EN)
 
 /*
@@ -516,11 +516,11 @@
  */
 
 /* PCIBR0 */
-#define CFG_PCI_MSTR0_LOCAL		0x80000000		/* Local base */
-#define CFG_PCIMSK0_MASK		PCIMSK_1GB		/* Size of window */
+#define CONFIG_SYS_PCI_MSTR0_LOCAL		0x80000000		/* Local base */
+#define CONFIG_SYS_PCIMSK0_MASK		PCIMSK_1GB		/* Size of window */
 /* PCIBR1 */
-#define CFG_PCI_MSTR1_LOCAL		0xF4000000		/* Local base */
-#define CFG_PCIMSK1_MASK		PCIMSK_64MB		/* Size of window */
+#define CONFIG_SYS_PCI_MSTR1_LOCAL		0xF4000000		/* Local base */
+#define CONFIG_SYS_PCIMSK1_MASK		PCIMSK_64MB		/* Size of window */
 
 /*
  * Master window that allows the CPU to access PCI Memory (prefetch).
@@ -528,11 +528,11 @@
  * in the bridge.
  */
 
-#define CFG_PCI_MSTR_MEM_LOCAL	0x80000000			/* Local base */
-#define CFG_PCI_MSTR_MEM_BUS	0x80000000			/* PCI base   */
-#define CFG_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
-#define CFG_PCI_MSTR_MEM_SIZE	0x20000000			/* 512MB */
-#define CFG_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL	0x80000000			/* Local base */
+#define CONFIG_SYS_PCI_MSTR_MEM_BUS	0x80000000			/* PCI base   */
+#define CONFIG_SYS_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
+#define CONFIG_SYS_PCI_MSTR_MEM_SIZE	0x20000000			/* 512MB */
+#define CONFIG_SYS_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 
 /*
  * Master window that allows the CPU to access PCI Memory (non-prefetch).
@@ -540,11 +540,11 @@
  * in the bridge.
  */
 
-#define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000			/* Local base */
-#define CFG_PCI_MSTR_MEMIO_BUS	    0xA0000000			/* PCI base   */
-#define CFG_CPU_PCI_MEMIO_START	    PCI_MSTR_MEMIO_LOCAL
-#define CFG_PCI_MSTR_MEMIO_SIZE	    0x20000000			/* 512MB */
-#define CFG_POCMR1_MASK_ATTRIB	    (POCMR_MASK_512MB | POCMR_ENABLE)
+#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL    0xA0000000			/* Local base */
+#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS	    0xA0000000			/* PCI base   */
+#define CONFIG_SYS_CPU_PCI_MEMIO_START	    PCI_MSTR_MEMIO_LOCAL
+#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE	    0x20000000			/* 512MB */
+#define CONFIG_SYS_POCMR1_MASK_ATTRIB	    (POCMR_MASK_512MB | POCMR_ENABLE)
 
 /*
  * Master window that allows the CPU to access PCI IO space.
@@ -552,11 +552,11 @@
  * in the bridge.
  */
 
-#define CFG_PCI_MSTR_IO_LOCAL	    0xF4000000			/* Local base */
-#define CFG_PCI_MSTR_IO_BUS	    0xF4000000			/* PCI base   */
-#define CFG_CPU_PCI_IO_START	    PCI_MSTR_IO_LOCAL
-#define CFG_PCI_MSTR_IO_SIZE	    0x04000000			/* 64MB */
-#define CFG_POCMR2_MASK_ATTRIB	    (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
+#define CONFIG_SYS_PCI_MSTR_IO_LOCAL	    0xF4000000			/* Local base */
+#define CONFIG_SYS_PCI_MSTR_IO_BUS	    0xF4000000			/* PCI base   */
+#define CONFIG_SYS_CPU_PCI_IO_START	    PCI_MSTR_IO_LOCAL
+#define CONFIG_SYS_PCI_MSTR_IO_SIZE	    0x04000000			/* 64MB */
+#define CONFIG_SYS_POCMR2_MASK_ATTRIB	    (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
 
 /*
  * JFFS2 partitions
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 55d7852..0ef4eba 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -49,9 +49,9 @@
 #define CONFIG_VSC7385_ENET
 #define CONFIG_TSEC2
 
-#ifdef CFG_66MHZ
+#ifdef CONFIG_SYS_66MHZ
 #define CONFIG_83XX_CLKIN	66666667	/* in Hz */
-#elif defined(CFG_33MHZ)
+#elif defined(CONFIG_SYS_33MHZ)
 #define CONFIG_83XX_CLKIN	33333333	/* in Hz */
 #else
 #error Unknown oscillator frequency.
@@ -61,23 +61,23 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
 
-#define CFG_IMMR		0xE0000000
+#define CONFIG_SYS_IMMR		0xE0000000
 
 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-#define CONFIG_DEFAULT_IMMR	CFG_IMMR
+#define CONFIG_DEFAULT_IMMR	CONFIG_SYS_IMMR
 #endif
 
-#define CFG_MEMTEST_START	0x00001000
-#define CFG_MEMTEST_END		0x07f00000
+#define CONFIG_SYS_MEMTEST_START	0x00001000
+#define CONFIG_SYS_MEMTEST_END		0x07f00000
 
 /* Early revs of this board will lock up hard when attempting
  * to access the PMC registers, unless a JTAG debugger is
  * connected, or some resistor modifications are made.
  */
-#define CFG_8313ERDB_BROKEN_PMC 1
+#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
 
-#define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
-#define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
+#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
 
 /*
  * Device configurations
@@ -98,22 +98,22 @@
 /*
  * DDR Setup
  */
-#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
 
 /*
  * Manually set up DDR parameters, as this board does not
  * seem to have the SPD connected to I2C.
  */
-#define CFG_DDR_SIZE		128		/* MB */
-#define CFG_DDR_CONFIG		( CSCONFIG_EN \
+#define CONFIG_SYS_DDR_SIZE		128		/* MB */
+#define CONFIG_SYS_DDR_CONFIG		( CSCONFIG_EN \
 				| 0x00010000 /* TODO */ \
 				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
 				/* 0x80010102 */
 
-#define CFG_DDR_TIMING_3	0x00000000
-#define CFG_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
 				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
 				| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
 				| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
@@ -122,7 +122,7 @@
 				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
 				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
 				/* 0x00220802 */
-#define CFG_DDR_TIMING_1	( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
+#define CONFIG_SYS_DDR_TIMING_1	( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
 				| ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
 				| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
 				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
@@ -131,7 +131,7 @@
 				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
 				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
 				/* 0x3835a322 */
-#define CFG_DDR_TIMING_2	( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+#define CONFIG_SYS_DDR_TIMING_2	( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
 				| ( 5 << TIMING_CFG2_CPO_SHIFT ) \
 				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
 				| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
@@ -139,30 +139,30 @@
 				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
 				| ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) )
 				/* 0x129048c6 */ /* P9-45,may need tuning */
-#define CFG_DDR_INTERVAL	( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+#define CONFIG_SYS_DDR_INTERVAL	( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \
 				| ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
 				/* 0x05100500 */
 #if defined(CONFIG_DDR_2T_TIMING)
-#define CFG_SDRAM_CFG		( SDRAM_CFG_SREN \
+#define CONFIG_SYS_SDRAM_CFG		( SDRAM_CFG_SREN \
 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
 				| SDRAM_CFG_2T_EN \
 				| SDRAM_CFG_DBW_32 )
 #else
-#define CFG_SDRAM_CFG		( SDRAM_CFG_SREN \
+#define CONFIG_SYS_SDRAM_CFG		( SDRAM_CFG_SREN \
 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
 				| SDRAM_CFG_32_BE )
 				/* 0x43080000 */
 #endif
-#define CFG_SDRAM_CFG2		0x00401000;
+#define CONFIG_SYS_SDRAM_CFG2		0x00401000
 /* set burst length to 8 for 32-bit data path */
-#define CFG_DDR_MODE		( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
+#define CONFIG_SYS_DDR_MODE		( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
 				| ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
 				/* 0x44480632 */
-#define CFG_DDR_MODE_2		0x8000C000;
+#define CONFIG_SYS_DDR_MODE_2		0x8000C000
 
-#define CFG_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 				/*0x02000000*/
-#define CFG_DDRCDR_VALUE	( DDRCDR_EN \
+#define CONFIG_SYS_DDRCDR_VALUE	( DDRCDR_EN \
 				| DDRCDR_PZ_NOMZ \
 				| DDRCDR_NZ_NOMZ \
 				| DDRCDR_M_ODR )
@@ -170,85 +170,85 @@
 /*
  * FLASH on the Local Bus
  */
-#define CFG_FLASH_CFI				/* use the Common Flash Interface */
+#define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
-#define CFG_FLASH_BASE		0xFE000000	/* start of FLASH   */
-#define CFG_FLASH_SIZE		8		/* flash size in MB */
-#define CFG_FLASH_EMPTY_INFO			/* display empty sectors */
-#define CFG_FLASH_USE_BUFFER_WRITE		/* buffer up multiple bytes */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		8		/* flash size in MB */
+#define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
+#define CONFIG_SYS_FLASH_EMPTY_INFO			/* display empty sectors */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE		/* buffer up multiple bytes */
 
-#define CFG_NOR_BR_PRELIM	(CFG_FLASH_BASE |	/* flash Base address */ \
+#define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE |	/* flash Base address */ \
 				(2 << BR_PS_SHIFT) |	/* 16 bit port size */ \
 				BR_V)			/* valid */
-#define CFG_NOR_OR_PRELIM	( 0xFF800000		/* 8 MByte */ \
+#define CONFIG_SYS_NOR_OR_PRELIM	( 0xFF800000		/* 8 MByte */ \
 				| OR_GPCM_XACS \
 				| OR_GPCM_SCY_9 \
 				| OR_GPCM_EHTR \
 				| OR_GPCM_EAD )
 				/* 0xFF006FF7	TODO SLOW 16 MB flash size */
-#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* window base at flash base */
-#define CFG_LBLAWAR0_PRELIM	0x80000017	/* 16 MB window size */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE	/* window base at flash base */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000017	/* 16 MB window size */
 
-#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_MAX_FLASH_SECT	135		/* sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	135		/* sectors per device */
 
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) && !defined(CONFIG_NAND_SPL)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/
 
-#define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-/* CFG_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */
 
 /*
  * Local Bus LCRR and LBCR regs
  */
-#define CFG_LCRR	LCRR_EADC_1 | LCRR_CLKDIV_4
-#define CFG_LBC_LBCR	( 0x00040000 /* TODO */ \
+#define CONFIG_SYS_LCRR	LCRR_EADC_1 | LCRR_CLKDIV_4
+#define CONFIG_SYS_LBC_LBCR	( 0x00040000 /* TODO */ \
 			| (0xFF << LBCR_BMT_SHIFT) \
 			| 0xF )	/* 0x0004ff0f */
 
-#define CFG_LBC_MRTPR	0x20000000  /*TODO */	/* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR	0x20000000  /*TODO */	/* LB refresh timer prescal, 266MHz/32 */
 
 /* drivers/mtd/nand/nand.c */
 #ifdef CONFIG_NAND_SPL
-#define CFG_NAND_BASE		0xFFF00000
+#define CONFIG_SYS_NAND_BASE		0xFFF00000
 #else
-#define CFG_NAND_BASE		0xE2800000
+#define CONFIG_SYS_NAND_BASE		0xE2800000
 #endif
 
-#define CFG_MAX_NAND_DEVICE	1
-#define NAND_MAX_CHIPS		1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_CMD_NAND 1
 #define CONFIG_NAND_FSL_ELBC 1
-#define CFG_NAND_BLOCK_SIZE 16384
+#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 
-#define CFG_NAND_U_BOOT_SIZE  (512 << 10)
-#define CFG_NAND_U_BOOT_DST   0x00100000
-#define CFG_NAND_U_BOOT_START 0x00100100
-#define CFG_NAND_U_BOOT_OFFS  16384
-#define CFG_NAND_U_BOOT_RELOC 0x00010000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
+#define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
+#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
 
-#define CFG_NAND_BR_PRELIM	( CFG_NAND_BASE \
+#define CONFIG_SYS_NAND_BR_PRELIM	( CONFIG_SYS_NAND_BASE \
 				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 				| BR_PS_8		/* Port Size = 8 bit */ \
 				| BR_MS_FCM		/* MSEL = FCM */ \
 				| BR_V )		/* valid */
-#define CFG_NAND_OR_PRELIM	( 0xFFFF8000		/* length 32K */ \
+#define CONFIG_SYS_NAND_OR_PRELIM	( 0xFFFF8000		/* length 32K */ \
 				| OR_FCM_CSCT \
 				| OR_FCM_CST \
 				| OR_FCM_CHT \
@@ -258,39 +258,39 @@
 				/* 0xFFFF8396 */
 
 #ifdef CONFIG_NAND_U_BOOT
-#define CFG_BR0_PRELIM CFG_NAND_BR_PRELIM
-#define CFG_OR0_PRELIM CFG_NAND_OR_PRELIM
-#define CFG_BR1_PRELIM CFG_NOR_BR_PRELIM
-#define CFG_OR1_PRELIM CFG_NOR_OR_PRELIM
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 #else
-#define CFG_BR0_PRELIM CFG_NOR_BR_PRELIM
-#define CFG_OR0_PRELIM CFG_NOR_OR_PRELIM
-#define CFG_BR1_PRELIM CFG_NAND_BR_PRELIM
-#define CFG_OR1_PRELIM CFG_NAND_OR_PRELIM
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 #endif
 
-#define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
-#define CFG_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
 
-#define CFG_NAND_LBLAWBAR_PRELIM CFG_LBLAWBAR1_PRELIM
-#define CFG_NAND_LBLAWAR_PRELIM CFG_LBLAWAR1_PRELIM
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 
 /* local bus read write buffer mapping */
-#define CFG_BR3_PRELIM		0xFA000801	/* map at 0xFA000000 */
-#define CFG_OR3_PRELIM		0xFFFF8FF7	/* 32kB */
-#define CFG_LBLAWBAR3_PRELIM	0xFA000000
-#define CFG_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
+#define CONFIG_SYS_BR3_PRELIM		0xFA000801	/* map at 0xFA000000 */
+#define CONFIG_SYS_OR3_PRELIM		0xFFFF8FF7	/* 32kB */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	0xFA000000
+#define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
 
 /* Vitesse 7385 */
 
-#define CFG_VSC7385_BASE	0xF0000000
+#define CONFIG_SYS_VSC7385_BASE	0xF0000000
 
 #ifdef CONFIG_VSC7385_ENET
 
-#define CFG_BR2_PRELIM		0xf0000801	/* VSC7385 Base address */
-#define CFG_OR2_PRELIM		0xfffe09ff	/* VSC7385, 128K bytes*/
-#define CFG_LBLAWBAR2_PRELIM	CFG_VSC7385_BASE/* Access window base at VSC7385 base */
-#define CFG_LBLAWAR2_PRELIM	0x80000010	/* Access window size 128K */
+#define CONFIG_SYS_BR2_PRELIM		0xf0000801	/* VSC7385 Base address */
+#define CONFIG_SYS_OR2_PRELIM		0xfffe09ff	/* VSC7385, 128K bytes*/
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE/* Access window base at VSC7385 base */
+#define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000010	/* Access window size 128K */
 
 #endif
 
@@ -303,47 +303,47 @@
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
 
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 
-#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
-#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support*/
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{{0,0x69}} /* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
-#define CFG_I2C2_OFFSET		0x3100
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
 
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCI1_MMIO_BASE	0x90000000
-#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
-#define CFG_PCI1_MMIO_SIZE	0x10000000	/* 256M */
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xE2000000
-#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
 
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
 
 /*
  * TSEC
@@ -356,7 +356,7 @@
 #ifdef CONFIG_TSEC1
 #define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME	"TSEC0"
-#define CFG_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
 #define TSEC1_PHY_ADDR		0x1c
 #define TSEC1_FLAGS		TSEC_GIGABIT
 #define TSEC1_PHYIDX		0
@@ -365,7 +365,7 @@
 #ifdef CONFIG_TSEC2
 #define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME	"TSEC1"
-#define CFG_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
 #define TSEC2_PHY_ADDR		4
 #define TSEC2_FLAGS		TSEC_GIGABIT
 #define TSEC2_PHYIDX		0
@@ -379,7 +379,7 @@
  * Configure on-board RTC
  */
 #define CONFIG_RTC_DS1337
-#define CFG_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
 
 /*
  * Environment
@@ -387,26 +387,26 @@
 #if defined(CONFIG_NAND_U_BOOT)
 	#define CONFIG_ENV_IS_IN_NAND	1
 	#define CONFIG_ENV_OFFSET		(512 * 1024)
-	#define CONFIG_ENV_SECT_SIZE	CFG_NAND_BLOCK_SIZE
+	#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
 	#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
 	#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
 	#define CONFIG_ENV_RANGE		(CONFIG_ENV_SECT_SIZE * 4)
 	#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
-#elif !defined(CFG_RAMBOOT)
+#elif !defined(CONFIG_SYS_RAMBOOT)
 	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K(one sector) for env */
 	#define CONFIG_ENV_SIZE		0x2000
 
 /* Address and size of Redundant Environment Sector */
 #else
 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 	#define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -429,8 +429,8 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_PCI
 
-#if defined(CFG_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
-    #undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 
@@ -440,30 +440,30 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory */
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
-#define CFG_RCWH_PCIHOST 0x80000000	/* PCIHOST  */
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000	/* PCIHOST  */
 
-#ifdef CFG_66MHZ
+#ifdef CONFIG_SYS_66MHZ
 
 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
 /* 0x62040000 */
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	0x20000000 /* reserved, must be set */ |\
 	HRCWL_DDRCM |\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
@@ -471,13 +471,13 @@
 	HRCWL_CSB_TO_CLKIN_2X1 |\
 	HRCWL_CORE_TO_CSB_2X1)
 
-#define CFG_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
+#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
 
-#elif defined(CFG_33MHZ)
+#elif defined(CONFIG_SYS_33MHZ)
 
 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
 /* 0x65040000 */
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	0x20000000 /* reserved, must be set */ |\
 	HRCWL_DDRCM |\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
@@ -485,11 +485,11 @@
 	HRCWL_CSB_TO_CLKIN_5X1 |\
 	HRCWL_CORE_TO_CSB_2X1)
 
-#define CFG_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
+#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
 
 #endif
 
-#define CFG_HRCW_HIGH_BASE (\
+#define CONFIG_SYS_HRCW_HIGH_BASE (\
 	HRCWH_PCI_HOST |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_CORE_ENABLE |\
@@ -500,72 +500,72 @@
 	HRCWH_BIG_ENDIAN)
 
 #ifdef CONFIG_NAND_SPL
-#define CFG_HRCW_HIGH (CFG_HRCW_HIGH_BASE |\
+#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 		       HRCWH_FROM_0XFFF00100 |\
 		       HRCWH_ROM_LOC_NAND_SP_8BIT |\
 		       HRCWH_RL_EXT_NAND)
 #else
-#define CFG_HRCW_HIGH (CFG_HRCW_HIGH_BASE |\
+#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 		       HRCWH_FROM_0X00000100 |\
 		       HRCWH_ROM_LOC_LOCAL_16BIT |\
 		       HRCWH_RL_EXT_LEGACY)
 #endif
 
 /* System IO Config */
-#define CFG_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2)	/* RGMII */
-#define CFG_SICRL	SICRL_USBDR			/* Enable Internal USB Phy  */
+#define CONFIG_SYS_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2)	/* RGMII */
+#define CONFIG_SYS_SICRL	SICRL_USBDR			/* Enable Internal USB Phy  */
 
-#define CFG_HID0_INIT	0x000000000
-#define CFG_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
 			 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 
-#define CFG_HID2 HID2_HBE
+#define CONFIG_SYS_HID2 HID2_HBE
 
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR @ 0x00000000 */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* PCI @ 0x80000000 */
-#define CFG_IBAT1L	(CFG_PCI1_MEM_BASE | BATL_PP_10)
-#define CFG_IBAT1U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT2L	(CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT2U	(CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* PCI2 not supported on 8313 */
-#define CFG_IBAT3L	(0)
-#define CFG_IBAT3U	(0)
-#define CFG_IBAT4L	(0)
-#define CFG_IBAT4U	(0)
+#define CONFIG_SYS_IBAT3L	(0)
+#define CONFIG_SYS_IBAT3U	(0)
+#define CONFIG_SYS_IBAT4L	(0)
+#define CONFIG_SYS_IBAT4U	(0)
 
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CFG_IBAT5L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT5U	(CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CFG_IBAT6L	(0xF0000000 | BATL_PP_10)
-#define CFG_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT7L	(0)
-#define CFG_IBAT7U	(0)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
-#define CFG_DBAT4L	CFG_IBAT4L
-#define CFG_DBAT4U	CFG_IBAT4U
-#define CFG_DBAT5L	CFG_IBAT5L
-#define CFG_DBAT5U	CFG_IBAT5U
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 
 /*
  * Internal Definitions
@@ -596,7 +596,7 @@
 #define CONFIG_FDTFILE		mpc8313erdb.dtb
 
 #define CONFIG_LOADADDR		500000	/* default location for tftp and bootm */
-#define CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
+#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 
 #define XMK_STR(x)	#x
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 5879a82..9fa91f4 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -45,13 +45,13 @@
  * if CLKIN is 66.66MHz, then
  * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
  */
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
 	HRCWL_SVCOD_DIV_2 |\
 	HRCWL_CSB_TO_CLKIN_2X1 |\
 	HRCWL_CORE_TO_CSB_3X1)
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_CORE_ENABLE |\
@@ -68,31 +68,31 @@
 /*
  * System IO Config
  */
-#define CFG_SICRH		0x00000000
-#define CFG_SICRL		0x00000000 /* 3.3V, no delay */
+#define CONFIG_SYS_SICRH		0x00000000
+#define CONFIG_SYS_SICRL		0x00000000 /* 3.3V, no delay */
 
 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
 
 /*
  * IMMR new address
  */
-#define CFG_IMMR		0xE0000000
+#define CONFIG_SYS_IMMR		0xE0000000
 
 /*
  * Arbiter Setup
  */
-#define CFG_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
-#define CFG_ACR_RPTCNT		3 /* Arbiter repeat count is 4 */
-#define CFG_SPCR_TSECEP		3 /* eTSEC emergency priority is highest */
+#define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
+#define CONFIG_SYS_ACR_RPTCNT		3 /* Arbiter repeat count is 4 */
+#define CONFIG_SYS_SPCR_TSECEP		3 /* eTSEC emergency priority is highest */
 
 /*
  * DDR Setup
  */
-#define CFG_DDR_BASE		0x00000000 /* DDR is system memory */
-#define CFG_SDRAM_BASE		CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
-#define CFG_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-#define CFG_DDRCDR_VALUE	( DDRCDR_EN \
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDRCDR_VALUE	( DDRCDR_EN \
 				| DDRCDR_PZ_LOZ \
 				| DDRCDR_NZ_LOZ \
 				| DDRCDR_ODT \
@@ -102,14 +102,14 @@
  * Manually set up DDR parameters
  * consist of two chips HY5PS12621BFP-C4 from HYNIX
  */
-#define CFG_DDR_SIZE		128 /* MB */
-#define CFG_DDR_CS0_BNDS	0x00000007
-#define CFG_DDR_CS0_CONFIG	( CSCONFIG_EN \
+#define CONFIG_SYS_DDR_SIZE		128 /* MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
+#define CONFIG_SYS_DDR_CS0_CONFIG	( CSCONFIG_EN \
 				| 0x00010000  /* ODT_WR to CSn */ \
 				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
 				/* 0x80010102 */
-#define CFG_DDR_TIMING_3	0x00000000
-#define CFG_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
 				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
 				| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
 				| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
@@ -118,89 +118,90 @@
 				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
 				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
 				/* 0x00220802 */
-#define CFG_DDR_TIMING_1	( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
-				| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
-				| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
+#define CONFIG_SYS_DDR_TIMING_1	( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
+				| ( 7 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
+				| ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
 				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
 				| ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
 				| ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
 				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
 				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
-				/* 0x39356222 */
-#define CFG_DDR_TIMING_2	( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+				/* 0x27256222 */
+#define CONFIG_SYS_DDR_TIMING_2	( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
 				| ( 4 << TIMING_CFG2_CPO_SHIFT ) \
 				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
 				| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
 				| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
 				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
-				| ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
-				/* 0x121048c7 */
-#define CFG_DDR_INTERVAL	( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+				| ( 5 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+				/* 0x121048c5 */
+#define CONFIG_SYS_DDR_INTERVAL	( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \
 				| ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
 				/* 0x03600100 */
-#define CFG_DDR_SDRAM_CFG	( SDRAM_CFG_SREN \
+#define CONFIG_SYS_DDR_SDRAM_CFG	( SDRAM_CFG_SREN \
 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
 				| SDRAM_CFG_32_BE )
 				/* 0x43080000 */
-#define CFG_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
-#define CFG_DDR_MODE		( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE		( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
 				| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
 				/* ODT 150ohm CL=3, AL=1 on SDRAM */
-#define CFG_DDR_MODE2		0x00000000
+#define CONFIG_SYS_DDR_MODE2		0x00000000
 
 /*
  * Memory test
  */
-#undef CFG_DRAM_TEST		/* memory test, takes time */
-#define CFG_MEMTEST_START	0x00040000 /* memtest region */
-#define CFG_MEMTEST_END		0x00140000
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00140000
 
 /*
  * The reserved memory
  */
-#define CFG_MONITOR_BASE	TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE /* start of monitor */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef CFG_RAMBOOT
+#undef CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(512 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024) /* Reserved for malloc */
 
 /*
  * Initial RAM Base Address Setup
  */
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CFG_INIT_RAM_END	0x1000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE	0x100 /* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_2)
-#define CFG_LBC_LBCR		0x00040000
+#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_2)
+#define CONFIG_SYS_LBC_LBCR		0x00040000
 
 /*
  * FLASH on the Local Bus
  */
-#define CFG_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
-#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 
-#define CFG_FLASH_BASE		0xFE000000 /* FLASH base address */
-#define CFG_FLASH_SIZE		8 /* FLASH size is 8M */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is 8M */
+#define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
 
-#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE /* Window base at flash base */
-#define CFG_LBLAWAR0_PRELIM	0x80000016 /* 8MB window size */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE /* Window base at flash base */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016 /* 8MB window size */
 
-#define CFG_BR0_PRELIM		( CFG_FLASH_BASE	/* Flash Base address */ \
+#define CONFIG_SYS_BR0_PRELIM		( CONFIG_SYS_FLASH_BASE	/* Flash Base address */ \
 				| (2 << BR_PS_SHIFT)	/* 16 bit port size */ \
 				| BR_V )		/* valid */
-#define CFG_OR0_PRELIM		( (~(CFG_FLASH_SIZE - 1) << 20) \
+#define CONFIG_SYS_OR0_PRELIM		( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
 				| OR_UPM_XAM \
 				| OR_GPCM_CSNT \
 				| OR_GPCM_ACS_DIV2 \
@@ -210,27 +211,28 @@
 				| OR_GPCM_EHTR \
 				| OR_GPCM_EAD )
 
-#define CFG_MAX_FLASH_BANKS	1 /* number of banks */
-#define CFG_MAX_FLASH_SECT	135 /* 127 64KB sectors and 8 8KB top sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	135 /* 127 64KB sectors and 8 8KB top sectors per device */
 
-#undef CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
 
 /*
  * NAND Flash on the Local Bus
  */
-#define CFG_NAND_BASE		0xE0600000	/* 0xE0600000 */
-#define CFG_MAX_NAND_DEVICE	1
-#define NAND_MAX_CHIPS		1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_SYS_NAND_BASE		0xE0600000	/* 0xE0600000 */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE	1
+#define CONFIG_CMD_NAND			1
+#define CONFIG_NAND_FSL_ELBC		1
 
-#define CFG_BR1_PRELIM		( CFG_NAND_BASE \
+#define CONFIG_SYS_BR1_PRELIM	( CONFIG_SYS_NAND_BASE \
 				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 				| BR_PS_8		/* Port Size = 8 bit */ \
 				| BR_MS_FCM		/* MSEL = FCM */ \
 				| BR_V )		/* valid */
-#define CFG_OR1_PRELIM		( 0xFFFF8000		/* length 32K */ \
+#define CONFIG_SYS_OR1_PRELIM	( 0xFFFF8000		/* length 32K */ \
 				| OR_FCM_CSCT \
 				| OR_FCM_CST \
 				| OR_FCM_CHT \
@@ -239,29 +241,29 @@
 				| OR_FCM_EHTR )
 				/* 0xFFFF8396 */
 
-#define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
-#define CFG_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
 
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
-#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
-#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* Pass open firmware flat tree */
@@ -272,50 +274,71 @@
 /* I2C */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #define CONFIG_FSL_I2C
-#define CFG_I2C_SPEED		400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x51} /* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
-#define CFG_I2C2_OFFSET		0x3100
+#define CONFIG_SYS_I2C_SPEED		400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{0x51} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
 
 /*
  * Board info - revision and where boot from
  */
-#define CFG_I2C_PCF8574A_ADDR	0x39
+#define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39
 
 /*
  * Config on-board RTC
  */
 #define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
-#define CFG_I2C_RTC_ADDR	0x68 /* at address 0x68 */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
 
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI_MEM_BASE	0x80000000
-#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BASE
-#define CFG_PCI_MEM_SIZE	0x10000000 /* 256M */
-#define CFG_PCI_MMIO_BASE	0x90000000
-#define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
-#define CFG_PCI_MMIO_SIZE	0x10000000 /* 256M */
-#define CFG_PCI_IO_BASE		0x00000000
-#define CFG_PCI_IO_PHYS		0xE0300000
-#define CFG_PCI_IO_SIZE		0x100000 /* 1M */
-
-#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE
-#define CFG_PCI_SLV_MEM_BUS	0x00000000
-#define CFG_PCI_SLV_MEM_SIZE	0x80000000
+#define CONFIG_SYS_PCI_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
+#define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
+
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
+#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
+
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
+
+#define CONFIG_SYS_PCIE2_BASE		0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_BASE	0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE2_CFG_BASE	0xD0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xD1000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
 
 #define CONFIG_PCI
 #define CONFIG_83XX_GENERIC_PCI	1 /* Use generic PCI setup */
+#define CONFIG_83XX_GENERIC_PCIE	1
 
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
 
 #define CONFIG_EEPRO100
 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
 
 #ifndef CONFIG_NET_MULTI
 #define CONFIG_NET_MULTI	1
@@ -327,10 +350,10 @@
  * TSEC
  */
 #define CONFIG_TSEC_ENET	/* TSEC ethernet support */
-#define CFG_TSEC1_OFFSET	0x24000
-#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
-#define CFG_TSEC2_OFFSET	0x25000
-#define CFG_TSEC2		(CFG_IMMR+CFG_TSEC2_OFFSET)
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1		(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2		(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 
 /*
  * TSEC ethernet configuration
@@ -356,15 +379,15 @@
 #define CONFIG_LIBATA
 #define CONFIG_FSL_SATA
 
-#define CFG_SATA_MAX_DEVICE	2
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
-#define CFG_SATA1_OFFSET	0x18000
-#define CFG_SATA1		(CFG_IMMR + CFG_SATA1_OFFSET)
-#define CFG_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SYS_SATA1_OFFSET	0x18000
+#define CONFIG_SYS_SATA1		(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
-#define CFG_SATA2_OFFSET	0x19000
-#define CFG_SATA2		(CFG_IMMR + CFG_SATA2_OFFSET)
-#define CFG_SATA2_FLAGS		FLAGS_DMA
+#define CONFIG_SYS_SATA2_OFFSET	0x19000
+#define CONFIG_SYS_SATA2		(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 
 #ifdef CONFIG_FSL_SATA
 #define CONFIG_LBA48
@@ -376,20 +399,20 @@
 /*
  * Environment
  */
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 	#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
 	#define CONFIG_ENV_SIZE		0x2000
 #else
-	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 	#define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -410,8 +433,8 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_PCI
 
-#if defined(CFG_RAMBOOT)
-    #undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 
@@ -422,35 +445,35 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory */
-#define CFG_LOAD_ADDR		0x2000000 /* default load address */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-	#define CFG_CBSIZE	1024 /* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
 #else
-	#define CFG_CBSIZE	256 /* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*
  * Core HID Setup
  */
-#define CFG_HID0_INIT		0x000000000
-#define CFG_HID0_FINAL		(HID0_ENABLE_MACHINE_CHECK | \
+#define CONFIG_SYS_HID0_INIT		0x000000000
+#define CONFIG_SYS_HID0_FINAL		(HID0_ENABLE_MACHINE_CHECK | \
 				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-#define CFG_HID2		HID2_HBE
+#define CONFIG_SYS_HID2		HID2_HBE
 
 /*
  * MMU Setup
@@ -458,53 +481,53 @@
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR: cache cacheable */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 
 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CFG_IBAT1L	(CFG_IMMR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT1U	(CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CFG_IBAT2L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT2U	(CFG_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP)
-#define CFG_DBAT2L	(CFG_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U	CFG_IBAT2U
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 
 /* Stack in dcache: cacheable, no memory coherence */
-#define CFG_IBAT3L	(CFG_INIT_RAM_ADDR | BATL_PP_10)
-#define CFG_IBAT3U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 /* PCI MEM space: cacheable */
-#define CFG_IBAT4L	(CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT4U	(CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT4L	CFG_IBAT4L
-#define CFG_DBAT4U	CFG_IBAT4U
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 
 /* PCI MMIO space: cache-inhibit and guarded */
-#define CFG_IBAT5L	(CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT5U	(CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT5L	CFG_IBAT5L
-#define CFG_DBAT5U	CFG_IBAT5U
-
-#define CFG_IBAT6L	0
-#define CFG_IBAT6U	0
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-
-#define CFG_IBAT7L	0
-#define CFG_IBAT7U	0
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+
+#define CONFIG_SYS_IBAT6L	0
+#define CONFIG_SYS_IBAT6U	0
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+
+#define CONFIG_SYS_IBAT7L	0
+#define CONFIG_SYS_IBAT7U	0
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 977142b..4eab285 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -32,7 +32,7 @@
 /*
  * Hardware Reset Configuration Word
  */
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
 	HRCWL_VCO_1X2 |\
@@ -42,7 +42,7 @@
 	HRCWL_CE_PLL_DIV_1X1 |\
 	HRCWL_CE_TO_PLL_1X3)
 
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_CORE_ENABLE |\
@@ -56,29 +56,29 @@
 /*
  * System IO Config
  */
-#define CFG_SICRL		0x00000000
+#define CONFIG_SYS_SICRL		0x00000000
 
 #define CONFIG_BOARD_EARLY_INIT_F	/* call board_pre_init */
 
 /*
  * IMMR new address
  */
-#define CFG_IMMR		0xE0000000
+#define CONFIG_SYS_IMMR		0xE0000000
 
 /*
  * System performance
  */
-#define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
-#define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
-#define CFG_SPCR_OPT		1	/* (0-1) Optimize transactions between  CSB and the SEC and QUICC Engine block */
+#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
+#define CONFIG_SYS_SPCR_OPT		1	/* (0-1) Optimize transactions between  CSB and the SEC and QUICC Engine block */
 
 /*
  * DDR Setup
  */
-#define CFG_DDR_BASE		0x00000000	/* DDR is system memory */
-#define CFG_SDRAM_BASE		CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
-#define CFG_DDRCDR		0x73000002	/* DDR II voltage is 1.8V */
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDRCDR		0x73000002	/* DDR II voltage is 1.8V */
 
 #undef CONFIG_SPD_EEPROM
 #if defined(CONFIG_SPD_EEPROM)
@@ -88,12 +88,12 @@
 #else
 /* Manually set up DDR parameters
  */
-#define CFG_DDR_SIZE		64	/* MB */
-#define CFG_DDR_CS0_CONFIG	( CSCONFIG_EN \
+#define CONFIG_SYS_DDR_SIZE		64	/* MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG	( CSCONFIG_EN \
 				| CSCONFIG_ODT_WR_ACS \
 				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 )
 				/* 0x80010101 */
-#define CFG_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
+#define CONFIG_SYS_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
 				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
 				| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
 				| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
@@ -102,7 +102,7 @@
 				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
 				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
 				/* 0x00220802 */
-#define CFG_DDR_TIMING_1	( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
+#define CONFIG_SYS_DDR_TIMING_1	( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
 				| ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
 				| ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
 				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
@@ -111,7 +111,7 @@
 				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
 				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
 				/* 0x26253222 */
-#define CFG_DDR_TIMING_2	( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+#define CONFIG_SYS_DDR_TIMING_2	( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
 				| (31 << TIMING_CFG2_CPO_SHIFT ) \
 				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
 				| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
@@ -119,98 +119,99 @@
 				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
 				| ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
 				/* 0x1f9048c7 */
-#define CFG_DDR_TIMING_3	0x00000000
-#define CFG_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 				/* 0x02000000 */
-#define CFG_DDR_MODE		( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
+#define CONFIG_SYS_DDR_MODE		( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
 				| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
 				/* 0x44480232 */
-#define CFG_DDR_MODE2		0x8000c000
-#define CFG_DDR_INTERVAL	( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+#define CONFIG_SYS_DDR_MODE2		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL	( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
 				| ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
 				/* 0x03200064 */
-#define CFG_DDR_CS0_BNDS	0x00000003
-#define CFG_DDR_SDRAM_CFG	( SDRAM_CFG_SREN \
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000003
+#define CONFIG_SYS_DDR_SDRAM_CFG	( SDRAM_CFG_SREN \
 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
 				| SDRAM_CFG_32_BE )
 				/* 0x43080000 */
-#define CFG_DDR_SDRAM_CFG2	0x00401000
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
 #endif
 
 /*
  * Memory test
  */
-#undef CFG_DRAM_TEST		/* memory test, takes time */
-#define CFG_MEMTEST_START	0x00030000	/* memtest region */
-#define CFG_MEMTEST_END		0x03f00000
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00030000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x03f00000
 
 /*
  * The reserved memory
  */
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef  CFG_RAMBOOT
+#undef  CONFIG_SYS_RAMBOOT
 #endif
 
-/* CFG_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /*
  * Initial RAM Base Address Setup
  */
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xE6000000	/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_2)
-#define CFG_LBC_LBCR		0x00000000
+#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_2)
+#define CONFIG_SYS_LBC_LBCR		0x00000000
 
 /*
  * FLASH on the Local Bus
  */
-#define CFG_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
-#define CFG_FLASH_BASE		0xFE000000	/* FLASH base address */
-#define CFG_FLASH_SIZE		16	/* FLASH size is 16M */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		16	/* FLASH size is 16M */
+#define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
 
-#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* Window base at flash base */
-#define CFG_LBLAWAR0_PRELIM	0x80000018	/* 32MB window size */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE	/* Window base at flash base */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000018	/* 32MB window size */
 
-#define CFG_BR0_PRELIM	(CFG_FLASH_BASE |	/* Flash Base address */ \
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE |	/* Flash Base address */ \
 			(2 << BR_PS_SHIFT) |	/* 16 bit port size */ \
 			BR_V)			/* valid */
-#define CFG_OR0_PRELIM		0xfe006ff7	/* 16MB Flash size */
+#define CONFIG_SYS_OR0_PRELIM		0xfe006ff7	/* 16MB Flash size */
 
-#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
 
-#undef CFG_FLASH_CHECKSUM
+#undef CONFIG_SYS_FLASH_CHECKSUM
 
 /*
  * SDRAM on the Local Bus
  */
-#undef CFG_LB_SDRAM		/* The board has not SRDAM on local bus */
+#undef CONFIG_SYS_LB_SDRAM		/* The board has not SRDAM on local bus */
 
-#ifdef CFG_LB_SDRAM
-#define CFG_LBC_SDRAM_BASE	0xF0000000	/* SDRAM base address */
-#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+#ifdef CONFIG_SYS_LB_SDRAM
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xF0000000	/* SDRAM base address */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
 
-#define CFG_LBLAWBAR2_PRELIM	CFG_LBC_SDRAM_BASE
-#define CFG_LBLAWAR2_PRELIM	0x80000019	/* 64MB */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_LBC_SDRAM_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000019	/* 64MB */
 
 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
 /*
  * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  *
  * For BR2, need:
  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
@@ -222,14 +223,14 @@
  * 0    4    8    12   16   20   24   28
  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  *
- * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  * the top 17 bits of BR2.
  */
 
-#define CFG_BR2_PRELIM	0xf0001861	/*Port size=32bit, MSEL=SDRAM */
+#define CONFIG_SYS_BR2_PRELIM	0xf0001861	/*Port size=32bit, MSEL=SDRAM */
 
 /*
- * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  *
  * For OR2, need:
  *    64MB mask for AM, OR2[0:7] = 1111 1100
@@ -242,68 +243,68 @@
  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  */
 
-#define CFG_OR2_PRELIM	0xfc006901
+#define CONFIG_SYS_OR2_PRELIM	0xfc006901
 
-#define CFG_LBC_LSRT	0x32000000	/* LB sdram refresh timer, about 6us */
-#define CFG_LBC_MRTPR	0x20000000	/* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_LSRT	0x32000000	/* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_MRTPR	0x20000000	/* LB refresh timer prescal, 266MHz/32 */
 
 /*
  * LSDMR masks
  */
-#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
 
-#define CFG_LBC_LSDMR_COMMON	0x0063b723
+#define CONFIG_SYS_LBC_LSDMR_COMMON	0x0063b723
 
 /*
  * SDRAM Controller configuration sequence.
  */
-#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_PCHALL)
-#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_MRW)
-#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_NORMAL)
+#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
 
 #endif
 
 /*
  * Windows to access PIB via local bus
  */
-#define CFG_LBLAWBAR3_PRELIM	0xf8008000	/* windows base 0xf8008000 */
-#define CFG_LBLAWAR3_PRELIM	0x8000000f	/* windows size 64KB */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	0xf8008000	/* windows base 0xf8008000 */
+#define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000000f	/* windows size 64KB */
 
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
-#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* pass open firmware flat tree */
@@ -315,33 +316,32 @@
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #undef CONFIG_SOFT_I2C		/* I2C bit-banged */
 #define CONFIG_FSL_I2C
-#define CFG_I2C_SPEED	400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE	0x7F
-#define CFG_I2C_NOPROBES	{0x51}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{0x51}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET	0x3000
 
 /*
  * Config on-board EEPROM
  */
-#define CFG_I2C_EEPROM_ADDR		0x50
-#define CFG_I2C_EEPROM_ADDR_LEN		2
-#define CFG_EEPROM_PAGE_WRITE_BITS	6
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCI1_MMIO_BASE	0x90000000
-#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
-#define CFG_PCI1_MMIO_SIZE	0x10000000	/* 256M */
-#define CFG_PCI1_IO_BASE		0xd0000000
-#define CFG_PCI1_IO_PHYS		CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE		0x04000000	/* 64M */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0xd0000000
+#define CONFIG_SYS_PCI1_IO_PHYS		CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_SIZE		0x04000000	/* 64M */
 
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_SKIP_HOST_BRIDGE
@@ -350,7 +350,7 @@
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
 
 #endif	/* CONFIG_PCI */
 
@@ -368,42 +368,42 @@
 #define CONFIG_UEC_ETH1		/* ETH3 */
 
 #ifdef CONFIG_UEC_ETH1
-#define CFG_UEC1_UCC_NUM	2	/* UCC3 */
-#define CFG_UEC1_RX_CLK		QE_CLK9
-#define CFG_UEC1_TX_CLK		QE_CLK10
-#define CFG_UEC1_ETH_TYPE	FAST_ETH
-#define CFG_UEC1_PHY_ADDR	4
-#define CFG_UEC1_INTERFACE_MODE	ENET_100_MII
+#define CONFIG_SYS_UEC1_UCC_NUM	2	/* UCC3 */
+#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
+#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
+#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	4
+#define CONFIG_SYS_UEC1_INTERFACE_MODE	ENET_100_MII
 #endif
 
 #define CONFIG_UEC_ETH2		/* ETH4 */
 
 #ifdef CONFIG_UEC_ETH2
-#define CFG_UEC2_UCC_NUM	1	/* UCC2 */
-#define CFG_UEC2_RX_CLK		QE_CLK16
-#define CFG_UEC2_TX_CLK		QE_CLK3
-#define CFG_UEC2_ETH_TYPE	FAST_ETH
-#define CFG_UEC2_PHY_ADDR	0
-#define CFG_UEC2_INTERFACE_MODE	ENET_100_MII
+#define CONFIG_SYS_UEC2_UCC_NUM	1	/* UCC2 */
+#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK16
+#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK3
+#define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR	0
+#define CONFIG_SYS_UEC2_INTERFACE_MODE	ENET_100_MII
 #endif
 
 /*
  * Environment
  */
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 	#define CONFIG_ENV_SECT_SIZE	0x20000
 	#define CONFIG_ENV_SIZE		0x2000
 #else
-	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 	#define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -426,8 +426,8 @@
 #if defined(CONFIG_PCI)
 	#define CONFIG_CMD_PCI
 #endif
-#if defined(CFG_RAMBOOT)
-	#undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT)
+	#undef CONFIG_CMD_SAVEENV
 	#undef CONFIG_CMD_LOADS
 #endif
 
@@ -436,34 +436,34 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory */
-#define CFG_LOAD_ADDR		0x2000000	/* default load address */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 
 #if (CONFIG_CMD_KGDB)
-	#define CFG_CBSIZE	1024	/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
 #else
-	#define CFG_CBSIZE	256	/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Core HID Setup
  */
-#define CFG_HID0_INIT		0x000000000
-#define CFG_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
-#define CFG_HID2		HID2_HBE
+#define CONFIG_SYS_HID0_INIT		0x000000000
+#define CONFIG_SYS_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID2		HID2_HBE
 
 /*
  * MMU Setup
@@ -471,64 +471,64 @@
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR: cache cacheable */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 
 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CFG_IBAT1L	(CFG_IMMR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT1U	(CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CFG_IBAT2L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT2U	(CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_DBAT2L	(CFG_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U	CFG_IBAT2U
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 
-#define CFG_IBAT3L	(0)
-#define CFG_IBAT3U	(0)
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L	(0)
+#define CONFIG_SYS_IBAT3U	(0)
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 /* Stack in dcache: cacheable, no memory coherence */
-#define CFG_IBAT4L	(CFG_INIT_RAM_ADDR | BATL_PP_10)
-#define CFG_IBAT4U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_DBAT4L	CFG_IBAT4L
-#define CFG_DBAT4U	CFG_IBAT4U
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 
 #ifdef CONFIG_PCI
 /* PCI MEM space: cacheable */
-#define CFG_IBAT5L	(CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT5U	(CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT5L	CFG_IBAT5L
-#define CFG_DBAT5U	CFG_IBAT5U
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 /* PCI MMIO space: cache-inhibit and guarded */
-#define CFG_IBAT6L	(CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT6U	(CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 #else
-#define CFG_IBAT5L	(0)
-#define CFG_IBAT5U	(0)
-#define CFG_IBAT6L	(0)
-#define CFG_IBAT6U	(0)
-#define CFG_DBAT5L	CFG_IBAT5L
-#define CFG_DBAT5U	CFG_IBAT5U
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
+#define CONFIG_SYS_IBAT5L	(0)
+#define CONFIG_SYS_IBAT5U	(0)
+#define CONFIG_SYS_IBAT6L	(0)
+#define CONFIG_SYS_IBAT6U	(0)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 #endif
 
 /* Nothing in BAT7 */
-#define CFG_IBAT7L	(0)
-#define CFG_IBAT7U	(0)
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 
 /*
  * Internal Definitions
@@ -553,8 +553,8 @@
 #define CONFIG_HAS_ETH1				/* add support for "eth1addr" */
 #define CONFIG_ETH1ADDR	00:04:9f:ef:03:02
 
-/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CFG_I2C_EEPROM) */
-#define CFG_I2C_MAC_OFFSET	0x7f00	/* MAC address offset in I2C EEPROM */
+/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
+#define CONFIG_SYS_I2C_MAC_OFFSET	0x7f00	/* MAC address offset in I2C EEPROM */
 
 #define CONFIG_IPADDR		10.0.0.2
 #define CONFIG_SERVERIP		10.0.0.1
@@ -570,7 +570,7 @@
 #define CONFIG_FDTFILE		mpc832x_rdb.dtb
 
 #define CONFIG_LOADADDR		500000	/* default location for tftp and bootm */
-#define CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
+#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 
 #define XMK_STR(x)	#x
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 01cf557..ea1928e 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -8,7 +8,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -47,7 +47,7 @@
 /*
  * Hardware Reset Configuration Word
  */
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
 	HRCWL_VCO_1X2 |\
@@ -58,7 +58,7 @@
 	HRCWL_CE_TO_PLL_1X3)
 
 #ifdef CONFIG_PCISLAVE
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_AGENT |\
 	HRCWH_PCI1_ARBITER_DISABLE |\
 	HRCWH_CORE_ENABLE |\
@@ -69,7 +69,7 @@
 	HRCWH_BIG_ENDIAN |\
 	HRCWH_LALE_NORMAL)
 #else
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_CORE_ENABLE |\
@@ -84,7 +84,7 @@
 /*
  * System IO Config
  */
-#define CFG_SICRL		0x00000000
+#define CONFIG_SYS_SICRL		0x00000000
 
 #define CONFIG_BOARD_EARLY_INIT_F	/* call board_pre_init */
 #define CONFIG_BOARD_EARLY_INIT_R
@@ -92,15 +92,15 @@
 /*
  * IMMR new address
  */
-#define CFG_IMMR		0xE0000000
+#define CONFIG_SYS_IMMR		0xE0000000
 
 /*
  * DDR Setup
  */
-#define CFG_DDR_BASE		0x00000000	/* DDR is system memory */
-#define CFG_SDRAM_BASE		CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
-#define CFG_DDRCDR		0x73000002	/* DDR II voltage is 1.8V */
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDRCDR		0x73000002	/* DDR II voltage is 1.8V */
 
 #undef CONFIG_SPD_EEPROM
 #if defined(CONFIG_SPD_EEPROM)
@@ -110,105 +110,106 @@
 #else
 /* Manually set up DDR parameters
  */
-#define CFG_DDR_SIZE		128	/* MB */
-#define CFG_DDR_CS0_CONFIG	0x80840102
-#define CFG_DDR_TIMING_0	0x00220802
-#define CFG_DDR_TIMING_1	0x3935d322
-#define CFG_DDR_TIMING_2	0x0f9048ca
-#define CFG_DDR_TIMING_3	0x00000000
-#define CFG_DDR_CLK_CNTL	0x02000000
-#define CFG_DDR_MODE		0x44400232
-#define CFG_DDR_MODE2		0x8000c000
-#define CFG_DDR_INTERVAL	0x03200064
-#define CFG_DDR_CS0_BNDS	0x00000007
-#define CFG_DDR_SDRAM_CFG	0x43080000
-#define CFG_DDR_SDRAM_CFG2	0x00401000
+#define CONFIG_SYS_DDR_SIZE		128	/* MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80840102
+#define CONFIG_SYS_DDR_TIMING_0	0x00220802
+#define CONFIG_SYS_DDR_TIMING_1	0x3935d322
+#define CONFIG_SYS_DDR_TIMING_2	0x0f9048ca
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL	0x02000000
+#define CONFIG_SYS_DDR_MODE		0x44400232
+#define CONFIG_SYS_DDR_MODE2		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL	0x03200064
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
+#define CONFIG_SYS_DDR_SDRAM_CFG	0x43080000
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
 #endif
 
 /*
  * Memory test
  */
-#undef CFG_DRAM_TEST		/* memory test, takes time */
-#define CFG_MEMTEST_START	0x00000000	/* memtest region */
-#define CFG_MEMTEST_END		0x00100000
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
 
 /*
  * The reserved memory
  */
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef  CFG_RAMBOOT
+#undef  CONFIG_SYS_RAMBOOT
 #endif
 
-/* CFG_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /*
  * Initial RAM Base Address Setup
  */
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xE6000000	/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_2)
-#define CFG_LBC_LBCR		0x00000000
+#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_2)
+#define CONFIG_SYS_LBC_LBCR		0x00000000
 
 /*
  * FLASH on the Local Bus
  */
-#define CFG_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
-#define CFG_FLASH_BASE		0xFE000000	/* FLASH base address */
-#define CFG_FLASH_SIZE		16	/* FLASH size is 16M */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		16	/* FLASH size is 16M */
+#define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
 
-#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* Window base at flash base */
-#define CFG_LBLAWAR0_PRELIM	0x80000018	/* 32MB window size */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE	/* Window base at flash base */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000018	/* 32MB window size */
 
-#define CFG_BR0_PRELIM	(CFG_FLASH_BASE |	/* Flash Base address */ \
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE |	/* Flash Base address */ \
 			(2 << BR_PS_SHIFT) |	/* 16 bit port size */ \
 			BR_V)			/* valid */
-#define CFG_OR0_PRELIM		0xfe006ff7	/* 16MB Flash size */
+#define CONFIG_SYS_OR0_PRELIM		0xfe006ff7	/* 16MB Flash size */
 
-#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
 
-#undef CFG_FLASH_CHECKSUM
+#undef CONFIG_SYS_FLASH_CHECKSUM
 
 /*
  * BCSR on the Local Bus
  */
-#define CFG_BCSR		0xF8000000
-#define CFG_LBLAWBAR1_PRELIM	CFG_BCSR	/* Access window base at BCSR base */
-#define CFG_LBLAWAR1_PRELIM	0x8000000E	/* Access window size 32K */
+#define CONFIG_SYS_BCSR		0xF8000000
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR	/* Access window base at BCSR base */
+#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E	/* Access window size 32K */
 
-#define CFG_BR1_PRELIM		(CFG_BCSR|0x00000801)	/* Port size=8bit, MSEL=GPCM */
-#define CFG_OR1_PRELIM		0xFFFFE9f7	/* length 32K */
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR|0x00000801)	/* Port size=8bit, MSEL=GPCM */
+#define CONFIG_SYS_OR1_PRELIM		0xFFFFE9f7	/* length 32K */
 
 /*
  * SDRAM on the Local Bus
  */
-#undef CFG_LB_SDRAM		/* The board has not SRDAM on local bus */
+#undef CONFIG_SYS_LB_SDRAM		/* The board has not SRDAM on local bus */
 
-#ifdef CFG_LB_SDRAM
-#define CFG_LBC_SDRAM_BASE	0xF0000000	/* SDRAM base address */
-#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+#ifdef CONFIG_SYS_LB_SDRAM
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xF0000000	/* SDRAM base address */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
 
-#define CFG_LBLAWBAR2_PRELIM	CFG_LBC_SDRAM_BASE
-#define CFG_LBLAWAR2_PRELIM	0x80000019	/* 64MB */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_LBC_SDRAM_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000019	/* 64MB */
 
 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
 /*
  * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  *
  * For BR2, need:
  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
@@ -220,14 +221,14 @@
  * 0    4    8    12   16   20   24   28
  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  *
- * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  * the top 17 bits of BR2.
  */
 
-#define CFG_BR2_PRELIM	0xf0001861	/*Port size=32bit, MSEL=SDRAM */
+#define CONFIG_SYS_BR2_PRELIM	0xf0001861	/*Port size=32bit, MSEL=SDRAM */
 
 /*
- * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  *
  * For OR2, need:
  *    64MB mask for AM, OR2[0:7] = 1111 1100
@@ -240,80 +241,80 @@
  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  */
 
-#define CFG_OR2_PRELIM	0xfc006901
+#define CONFIG_SYS_OR2_PRELIM	0xfc006901
 
-#define CFG_LBC_LSRT	0x32000000	/* LB sdram refresh timer, about 6us */
-#define CFG_LBC_MRTPR	0x20000000	/* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_LSRT	0x32000000	/* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_MRTPR	0x20000000	/* LB refresh timer prescal, 266MHz/32 */
 
 /*
  * LSDMR masks
  */
-#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
 
-#define CFG_LBC_LSDMR_COMMON	0x0063b723
+#define CONFIG_SYS_LBC_LSDMR_COMMON	0x0063b723
 
 /*
  * SDRAM Controller configuration sequence.
  */
-#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_PCHALL)
-#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_MRW)
-#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_NORMAL)
+#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
 
 #endif
 
 /*
  * Windows to access PIB via local bus
  */
-#define CFG_LBLAWBAR3_PRELIM	0xf8008000	/* windows base 0xf8008000 */
-#define CFG_LBLAWAR3_PRELIM	0x8000000f	/* windows size 64KB */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	0xf8008000	/* windows base 0xf8008000 */
+#define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000000f	/* windows size 64KB */
 
 /*
  * CS2 on Local Bus, to PIB
  */
-#define CFG_BR2_PRELIM	0xf8008801	/* CS2 base address at 0xf8008000 */
-#define CFG_OR2_PRELIM	0xffffe9f7	/* size 32KB, port size 8bit, GPCM */
+#define CONFIG_SYS_BR2_PRELIM	0xf8008801	/* CS2 base address at 0xf8008000 */
+#define CONFIG_SYS_OR2_PRELIM	0xffffe9f7	/* size 32KB, port size 8bit, GPCM */
 
 /*
  * CS3 on Local Bus, to PIB
  */
-#define CFG_BR3_PRELIM	0xf8010801	/* CS3 base address at 0xf8010000 */
-#define CFG_OR3_PRELIM	0xffffe9f7	/* size 32KB, port size 8bit, GPCM */
+#define CONFIG_SYS_BR3_PRELIM	0xf8010801	/* CS3 base address at 0xf8010000 */
+#define CONFIG_SYS_OR3_PRELIM	0xffffe9f7	/* size 32KB, port size 8bit, GPCM */
 
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
-#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* pass open firmware flat tree */
@@ -325,34 +326,34 @@
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #undef CONFIG_SOFT_I2C		/* I2C bit-banged */
 #define CONFIG_FSL_I2C
-#define CFG_I2C_SPEED	400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE	0x7F
-#define CFG_I2C_NOPROBES	{0x51}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{0x51}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET	0x3000
 
 /*
  * Config on-board RTC
  */
 #define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
-#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68 */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68 */
 
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI_MEM_BASE	0x80000000
-#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BASE
-#define CFG_PCI_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCI_MMIO_BASE	0x90000000
-#define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
-#define CFG_PCI_MMIO_SIZE	0x10000000	/* 256M */
-#define CFG_PCI_IO_BASE		0x00000000
-#define CFG_PCI_IO_PHYS		0xE0300000
-#define CFG_PCI_IO_SIZE		0x100000	/* 1M */
+#define CONFIG_SYS_PCI_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
+#define CONFIG_SYS_PCI_IO_SIZE		0x100000	/* 1M */
 
-#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE
-#define CFG_PCI_SLV_MEM_BUS	0x00000000
-#define CFG_PCI_SLV_MEM_SIZE	0x80000000
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
+#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
 
 
 #ifdef CONFIG_PCI
@@ -362,7 +363,7 @@
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
 
 #endif	/* CONFIG_PCI */
 
@@ -380,42 +381,42 @@
 #define CONFIG_UEC_ETH1		/* ETH3 */
 
 #ifdef CONFIG_UEC_ETH1
-#define CFG_UEC1_UCC_NUM	2	/* UCC3 */
-#define CFG_UEC1_RX_CLK		QE_CLK9
-#define CFG_UEC1_TX_CLK		QE_CLK10
-#define CFG_UEC1_ETH_TYPE	FAST_ETH
-#define CFG_UEC1_PHY_ADDR	3
-#define CFG_UEC1_INTERFACE_MODE	ENET_100_MII
+#define CONFIG_SYS_UEC1_UCC_NUM	2	/* UCC3 */
+#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
+#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
+#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	3
+#define CONFIG_SYS_UEC1_INTERFACE_MODE	ENET_100_MII
 #endif
 
 #define CONFIG_UEC_ETH2		/* ETH4 */
 
 #ifdef CONFIG_UEC_ETH2
-#define CFG_UEC2_UCC_NUM	3	/* UCC4 */
-#define CFG_UEC2_RX_CLK		QE_CLK7
-#define CFG_UEC2_TX_CLK		QE_CLK8
-#define CFG_UEC2_ETH_TYPE	FAST_ETH
-#define CFG_UEC2_PHY_ADDR	4
-#define CFG_UEC2_INTERFACE_MODE	ENET_100_MII
+#define CONFIG_SYS_UEC2_UCC_NUM	3	/* UCC4 */
+#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK7
+#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK8
+#define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR	4
+#define CONFIG_SYS_UEC2_INTERFACE_MODE	ENET_100_MII
 #endif
 
 /*
  * Environment
  */
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 	#define CONFIG_ENV_SECT_SIZE	0x20000
 	#define CONFIG_ENV_SIZE		0x2000
 #else
-	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 	#define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -439,8 +440,8 @@
     #define CONFIG_CMD_PCI
 #endif
 
-#if defined(CFG_RAMBOOT)
-    #undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 
@@ -450,34 +451,34 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory */
-#define CFG_LOAD_ADDR		0x2000000	/* default load address */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-	#define CFG_CBSIZE	1024	/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
 #else
-	#define CFG_CBSIZE	256	/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Core HID Setup
  */
-#define CFG_HID0_INIT		0x000000000
-#define CFG_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
-#define CFG_HID2		HID2_HBE
+#define CONFIG_SYS_HID0_INIT		0x000000000
+#define CONFIG_SYS_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID2		HID2_HBE
 
 /*
  * MMU Setup
@@ -486,64 +487,64 @@
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR: cache cacheable */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 
 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CFG_IBAT1L	(CFG_IMMR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT1U	(CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 
 /* BCSR: cache-inhibit and guarded */
-#define CFG_IBAT2L	(CFG_BCSR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_BCSR | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT2U	(CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CFG_IBAT3L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT3U	(CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_DBAT3L	(CFG_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
-#define CFG_IBAT4L	(0)
-#define CFG_IBAT4U	(0)
-#define CFG_DBAT4L	CFG_IBAT4L
-#define CFG_DBAT4U	CFG_IBAT4U
+#define CONFIG_SYS_IBAT4L	(0)
+#define CONFIG_SYS_IBAT4U	(0)
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 
 /* Stack in dcache: cacheable, no memory coherence */
-#define CFG_IBAT5L	(CFG_INIT_RAM_ADDR | BATL_PP_10)
-#define CFG_IBAT5U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_DBAT5L	CFG_IBAT5L
-#define CFG_DBAT5U	CFG_IBAT5U
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 
 #ifdef CONFIG_PCI
 /* PCI MEM space: cacheable */
-#define CFG_IBAT6L	(CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U	(CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 /* PCI MMIO space: cache-inhibit and guarded */
-#define CFG_IBAT7L	(CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT7U	(CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #else
-#define CFG_IBAT6L	(0)
-#define CFG_IBAT6U	(0)
-#define CFG_IBAT7L	(0)
-#define CFG_IBAT7U	(0)
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT6L	(0)
+#define CONFIG_SYS_IBAT6U	(0)
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #endif
 
 /*
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 87f1672..b3c0e2d 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -65,11 +65,11 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
 
-#define CFG_IMMR		0xE0000000
+#define CONFIG_SYS_IMMR		0xE0000000
 
-#undef CFG_DRAM_TEST				/* memory test, takes time */
-#define CFG_MEMTEST_START	0x00000000      /* memtest region */
-#define CFG_MEMTEST_END		0x00100000
+#undef CONFIG_SYS_DRAM_TEST				/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000      /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
 
 /*
  * DDR Setup
@@ -90,17 +90,17 @@
  */
 #undef CONFIG_DDR_32BIT
 
-#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
-#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 #undef  CONFIG_DDR_2T_TIMING
 
 /*
  * DDRCDR - DDR Control Driver Register
  */
-#define CFG_DDRCDR_VALUE	0x80080001
+#define CONFIG_SYS_DDRCDR_VALUE	0x80080001
 
 #if defined(CONFIG_SPD_EEPROM)
 /*
@@ -111,34 +111,34 @@
 /*
  * Manually set up DDR parameters
  */
-#define CFG_DDR_SIZE		256		/* MB */
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
 #if defined(CONFIG_DDR_II)
-#define CFG_DDRCDR		0x80080001
-#define CFG_DDR_CS2_BNDS	0x0000000f
-#define CFG_DDR_CS2_CONFIG	0x80330102
-#define CFG_DDR_TIMING_0	0x00220802
-#define CFG_DDR_TIMING_1	0x38357322
-#define CFG_DDR_TIMING_2	0x2f9048c8
-#define CFG_DDR_TIMING_3	0x00000000
-#define CFG_DDR_CLK_CNTL	0x02000000
-#define CFG_DDR_MODE		0x47d00432
-#define CFG_DDR_MODE2		0x8000c000
-#define CFG_DDR_INTERVAL	0x03cf0080
-#define CFG_DDR_SDRAM_CFG	0x43000000
-#define CFG_DDR_SDRAM_CFG2	0x00401000
+#define CONFIG_SYS_DDRCDR		0x80080001
+#define CONFIG_SYS_DDR_CS2_BNDS	0x0000000f
+#define CONFIG_SYS_DDR_CS2_CONFIG	0x80330102
+#define CONFIG_SYS_DDR_TIMING_0	0x00220802
+#define CONFIG_SYS_DDR_TIMING_1	0x38357322
+#define CONFIG_SYS_DDR_TIMING_2	0x2f9048c8
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL	0x02000000
+#define CONFIG_SYS_DDR_MODE		0x47d00432
+#define CONFIG_SYS_DDR_MODE2		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL	0x03cf0080
+#define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
 #else
-#define CFG_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
-#define CFG_DDR_TIMING_1	0x36332321
-#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
-#define CFG_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
-#define CFG_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
+#define CONFIG_SYS_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_TIMING_1	0x36332321
+#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
 
 #if defined(CONFIG_DDR_32BIT)
 /* set burst length to 8 for 32-bit data path */
-#define CFG_DDR_MODE		0x00000023	/* DLL,normal,seq,4/2.5, 8 burst len */
+#define CONFIG_SYS_DDR_MODE		0x00000023	/* DLL,normal,seq,4/2.5, 8 burst len */
 #else
 /* the default burst length is 4 - for 64-bit data path */
-#define CFG_DDR_MODE		0x00000022	/* DLL,normal,seq,4/2.5, 4 burst len */
+#define CONFIG_SYS_DDR_MODE		0x00000022	/* DLL,normal,seq,4/2.5, 4 burst len */
 #endif
 #endif
 #endif
@@ -146,63 +146,63 @@
 /*
  * SDRAM on the Local Bus
  */
-#define CFG_LBC_SDRAM_BASE	0xF0000000	/* Localbus SDRAM */
-#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xF0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
 
 /*
  * FLASH on the Local Bus
  */
-#define CFG_FLASH_CFI				/* use the Common Flash Interface */
+#define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
-#define CFG_FLASH_BASE		0xFE000000	/* start of FLASH   */
-#define CFG_FLASH_SIZE		32		/* max flash size in MB */
-/* #define CFG_FLASH_USE_BUFFER_WRITE */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		32		/* max flash size in MB */
+#define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
+/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE |	/* flash Base address */ \
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE |	/* flash Base address */ \
 				(2 << BR_PS_SHIFT) |	/* 16 bit port size */	 \
 				BR_V)			/* valid */
-#define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
+#define CONFIG_SYS_OR0_PRELIM		((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
-#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* window base at flash base */
-#define CFG_LBLAWAR0_PRELIM	0x80000018	/* 32 MB window size */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE	/* window base at flash base */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000018	/* 32 MB window size */
 
-#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_MAX_FLASH_SECT	256		/* max sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max sectors per device */
 
-#undef CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MID_FLASH_JUMP	0x7F000000
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MID_FLASH_JUMP	0x7F000000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef  CFG_RAMBOOT
+#undef  CONFIG_SYS_RAMBOOT
 #endif
 
 /*
  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
  */
-#define CFG_BCSR		0xE2400000
-#define CFG_LBLAWBAR1_PRELIM	CFG_BCSR		/* Access window base at BCSR base */
-#define CFG_LBLAWAR1_PRELIM	0x8000000E		/* Access window size 32K */
-#define CFG_BR1_PRELIM		(CFG_BCSR|0x00000801)	/* Port-size=8bit, MSEL=GPCM */
-#define CFG_OR1_PRELIM		0xFFFFE8F0		/* length 32K */
+#define CONFIG_SYS_BCSR		0xE2400000
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR		/* Access window base at BCSR base */
+#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E		/* Access window size 32K */
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR|0x00000801)	/* Port-size=8bit, MSEL=GPCM */
+#define CONFIG_SYS_OR1_PRELIM		0xFFFFE8F0		/* length 32K */
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xFD000000		/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x1000			/* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000		/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x1000			/* End of used area in RAM*/
 
-#define CFG_GBL_DATA_SIZE	0x100			/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100			/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)		/* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)		/* Reserved for malloc */
 
 /*
  * Local Bus LCRR and LBCR regs
@@ -210,20 +210,20 @@
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CFG_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
-#define CFG_LBC_LBCR	0x00000000
+#define CONFIG_SYS_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LBC_LBCR	0x00000000
 
 /*
  * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
- * if board has SRDAM on local bus, you can define CFG_LB_SDRAM
+ * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
  */
-#undef CFG_LB_SDRAM
+#undef CONFIG_SYS_LB_SDRAM
 
-#ifdef CFG_LB_SDRAM
+#ifdef CONFIG_SYS_LB_SDRAM
 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
 /*
  * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  *
  * For BR2, need:
  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
@@ -235,16 +235,16 @@
  * 0    4    8    12   16   20   24   28
  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
  *
- * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  * FIXME: the top 17 bits of BR2.
  */
 
-#define CFG_BR2_PRELIM		0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
-#define CFG_LBLAWBAR2_PRELIM	0xF0000000
-#define CFG_LBLAWAR2_PRELIM	0x80000019 /* 64M */
+#define CONFIG_SYS_BR2_PRELIM		0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	0xF0000000
+#define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000019 /* 64M */
 
 /*
- * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  *
  * For OR2, need:
  *    64MB mask for AM, OR2[0:7] = 1111 1100
@@ -257,65 +257,65 @@
  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
  */
 
-#define CFG_OR2_PRELIM	0xFC006901
+#define CONFIG_SYS_OR2_PRELIM	0xFC006901
 
-#define CFG_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
-#define CFG_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32 */
 
 /*
  * LSDMR masks
  */
-#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CFG_LBC_LSDMR_RFCR5	(3 << (31 - 16))
-#define CFG_LBC_LSDMR_RFCR8	(5 << (31 - 16))
-#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CFG_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
-#define CFG_LBC_LSDMR_PRETOACT6	(5 << (31 - 19))
-#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CFG_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CFG_LBC_LSDMR_WRC2	(2 << (31 - 27))
-#define CFG_LBC_LSDMR_WRC3	(3 << (31 - 27))
-#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CFG_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
-#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
-#define CFG_LBC_LSDMR_COMMON    ( CFG_LBC_LSDMR_RFEN            \
-				| CFG_LBC_LSDMR_BSMA1516	\
-				| CFG_LBC_LSDMR_RFCR8		\
-				| CFG_LBC_LSDMR_PRETOACT6	\
-				| CFG_LBC_LSDMR_ACTTORW3	\
-				| CFG_LBC_LSDMR_BL8		\
-				| CFG_LBC_LSDMR_WRC3		\
-				| CFG_LBC_LSDMR_CL3		\
+#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_RFCR5	(3 << (31 - 16))
+#define CONFIG_SYS_LBC_LSDMR_RFCR8	(5 << (31 - 16))
+#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CONFIG_SYS_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
+#define CONFIG_SYS_LBC_LSDMR_PRETOACT6	(5 << (31 - 19))
+#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CONFIG_SYS_LBC_LSDMR_WRC2	(2 << (31 - 27))
+#define CONFIG_SYS_LBC_LSDMR_WRC3	(3 << (31 - 27))
+#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CONFIG_SYS_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
+#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+#define CONFIG_SYS_LBC_LSDMR_COMMON    ( CONFIG_SYS_LBC_LSDMR_RFEN            \
+				| CONFIG_SYS_LBC_LSDMR_BSMA1516	\
+				| CONFIG_SYS_LBC_LSDMR_RFCR8		\
+				| CONFIG_SYS_LBC_LSDMR_PRETOACT6	\
+				| CONFIG_SYS_LBC_LSDMR_ACTTORW3	\
+				| CONFIG_SYS_LBC_LSDMR_BL8		\
+				| CONFIG_SYS_LBC_LSDMR_WRC3		\
+				| CONFIG_SYS_LBC_LSDMR_CL3		\
 				)
 
 /*
  * SDRAM Controller configuration sequence.
  */
-#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_PCHALL)
-#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_MRW)
-#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_NORMAL)
+#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
 #endif
 
 /*
@@ -323,22 +323,22 @@
  */
 #define CONFIG_CONS_INDEX     1
 #undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
-#define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* pass open firmware flat tree */
@@ -352,53 +352,53 @@
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
-#define CFG_I2C2_OFFSET		0x3100
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
 
 /* SPI */
 #define CONFIG_MPC8XXX_SPI
 #undef CONFIG_SOFT_SPI			/* SPI bit-banged */
 
 /* GPIOs.  Used as SPI chip selects */
-#define CFG_GPIO1_PRELIM
-#define CFG_GPIO1_DIR		0xC0000000  /* SPI CS on 0, LED on 1 */
-#define CFG_GPIO1_DAT		0xC0000000  /* Both are active LOW */
+#define CONFIG_SYS_GPIO1_PRELIM
+#define CONFIG_SYS_GPIO1_DIR		0xC0000000  /* SPI CS on 0, LED on 1 */
+#define CONFIG_SYS_GPIO1_DAT		0xC0000000  /* Both are active LOW */
 
 /* TSEC */
-#define CFG_TSEC1_OFFSET 0x24000
-#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
-#define CFG_TSEC2_OFFSET 0x25000
-#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 
 /* USB */
-#define CFG_USE_MPC834XSYS_USB_PHY	1 /* Use SYS board PHY */
+#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY	1 /* Use SYS board PHY */
 
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCI1_MMIO_BASE	0x90000000
-#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
-#define CFG_PCI1_MMIO_SIZE	0x10000000	/* 256M */
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xE2000000
-#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
-
-#define CFG_PCI2_MEM_BASE	0xA0000000
-#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCI2_MMIO_BASE	0xB0000000
-#define CFG_PCI2_MMIO_PHYS	CFG_PCI2_MMIO_BASE
-#define CFG_PCI2_MMIO_SIZE	0x10000000	/* 256M */
-#define CFG_PCI2_IO_BASE	0x00000000
-#define CFG_PCI2_IO_PHYS	0xE2100000
-#define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
+#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS	0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE	0x00100000	/* 1M */
 
 #if defined(CONFIG_PCI)
 
@@ -424,7 +424,7 @@
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 
 #endif	/* CONFIG_PCI */
 
@@ -459,14 +459,14 @@
  * Configure on-board RTC
  */
 #define CONFIG_RTC_DS1374			/* use ds1374 rtc via i2c	*/
-#define CFG_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
 
 /*
  * Environment
  */
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
 	#define CONFIG_ENV_SIZE		0x2000
 
@@ -475,14 +475,14 @@
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
 #else
-	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 	#define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 
 /*
@@ -508,8 +508,8 @@
     #define CONFIG_CMD_PCI
 #endif
 
-#if defined(CFG_RAMBOOT)
-    #undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 
@@ -519,60 +519,60 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory */
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-	#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
-#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 
 #if 1 /*528/264*/
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X2 |\
 	HRCWL_CORE_TO_CSB_2X1)
 #elif 0 /*396/132*/
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X4 |\
 	HRCWL_CORE_TO_CSB_3X1)
 #elif 0 /*264/132*/
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X4 |\
 	HRCWL_CORE_TO_CSB_2X1)
 #elif 0 /*132/132*/
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X4 |\
 	HRCWL_CORE_TO_CSB_1X1)
 #elif 0 /*264/264 */
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
@@ -581,7 +581,7 @@
 #endif
 
 #ifdef CONFIG_PCISLAVE
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_AGENT |\
 	HRCWH_64_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_DISABLE |\
@@ -595,7 +595,7 @@
 	HRCWH_TSEC2M_IN_GMII )
 #else
 #if defined(PCI_64BIT)
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_64_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
@@ -608,7 +608,7 @@
 	HRCWH_TSEC1M_IN_GMII |\
 	HRCWH_TSEC2M_IN_GMII )
 #else
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_32_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
@@ -626,85 +626,85 @@
 /*
  * System performance
  */
-#define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
-#define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
-#define CFG_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
-#define CFG_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
-#define CFG_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
-#define CFG_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
+#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
+#define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
+#define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
+#define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
 
 /* System IO Config */
-#define CFG_SICRH SICRH_TSOBI1
-#define CFG_SICRL SICRL_LDP_A
+#define CONFIG_SYS_SICRH SICRH_TSOBI1
+#define CONFIG_SYS_SICRL SICRL_LDP_A
 
-#define CFG_HID0_INIT	0x000000000
-#define CFG_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
 
-/* #define CFG_HID0_FINAL		(\
+/* #define CONFIG_SYS_HID0_FINAL		(\
 	HID0_ENABLE_INSTRUCTION_CACHE |\
 	HID0_ENABLE_M_BIT |\
 	HID0_ENABLE_ADDRESS_BROADCAST ) */
 
 
-#define CFG_HID2 HID2_HBE
+#define CONFIG_SYS_HID2 HID2_HBE
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR @ 0x00000000 */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* PCI @ 0x80000000 */
 #ifdef CONFIG_PCI
-#define CFG_IBAT1L	(CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT2L	(CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT2U	(CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #else
-#define CFG_IBAT1L	(0)
-#define CFG_IBAT1U	(0)
-#define CFG_IBAT2L	(0)
-#define CFG_IBAT2U	(0)
+#define CONFIG_SYS_IBAT1L	(0)
+#define CONFIG_SYS_IBAT1U	(0)
+#define CONFIG_SYS_IBAT2L	(0)
+#define CONFIG_SYS_IBAT2U	(0)
 #endif
 
 #ifdef CONFIG_MPC83XX_PCI2
-#define CFG_IBAT3L	(CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT3U	(CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT4L	(CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT4U	(CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #else
-#define CFG_IBAT3L	(0)
-#define CFG_IBAT3U	(0)
-#define CFG_IBAT4L	(0)
-#define CFG_IBAT4U	(0)
+#define CONFIG_SYS_IBAT3L	(0)
+#define CONFIG_SYS_IBAT3U	(0)
+#define CONFIG_SYS_IBAT4L	(0)
+#define CONFIG_SYS_IBAT4U	(0)
 #endif
 
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CFG_IBAT5L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT5U	(CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CFG_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT7L	(0)
-#define CFG_IBAT7U	(0)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
-#define CFG_DBAT4L	CFG_IBAT4L
-#define CFG_DBAT4U	CFG_IBAT4U
-#define CFG_DBAT5L	CFG_IBAT5L
-#define CFG_DBAT5U	CFG_IBAT5U
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index fa0c0a7..14cbc45 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -57,7 +57,7 @@
 #define __CONFIG_H
 
 #if (TEXT_BASE == 0xFE000000)
-#define CFG_LOWBOOT
+#define CONFIG_SYS_LOWBOOT
 #endif
 
 /*
@@ -66,7 +66,7 @@
 #define CONFIG_MPC834X		/* MPC834x family (8343, 8347, 8349) */
 #define CONFIG_MPC8349		/* MPC8349 specific */
 
-#define CFG_IMMR		0xE0000000	/* The IMMR is relocated to here */
+#define CONFIG_SYS_IMMR		0xE0000000	/* The IMMR is relocated to here */
 
 #define CONFIG_MISC_INIT_F
 #define CONFIG_MISC_INIT_R
@@ -95,26 +95,26 @@
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
-#define CFG_I2C_OFFSET		0x3000
-#define CFG_I2C2_OFFSET		0x3100
-#define CFG_SPD_BUS_NUM		1	/* The I2C bus for SPD */
-
-#define CFG_I2C_8574_ADDR1	0x20	/* I2C1, PCF8574 */
-#define CFG_I2C_8574_ADDR2	0x21	/* I2C1, PCF8574 */
-#define CFG_I2C_8574A_ADDR1	0x38	/* I2C1, PCF8574A */
-#define CFG_I2C_8574A_ADDR2	0x39	/* I2C1, PCF8574A */
-#define CFG_I2C_EEPROM_ADDR	0x50	/* I2C0, Board EEPROM */
-#define CFG_I2C_RTC_ADDR	0x68	/* I2C1, DS1339 RTC*/
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
+#define CONFIG_SYS_SPD_BUS_NUM		1	/* The I2C bus for SPD */
+
+#define CONFIG_SYS_I2C_8574_ADDR1	0x20	/* I2C1, PCF8574 */
+#define CONFIG_SYS_I2C_8574_ADDR2	0x21	/* I2C1, PCF8574 */
+#define CONFIG_SYS_I2C_8574A_ADDR1	0x38	/* I2C1, PCF8574A */
+#define CONFIG_SYS_I2C_8574A_ADDR2	0x39	/* I2C1, PCF8574A */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* I2C0, Board EEPROM */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* I2C1, DS1339 RTC*/
 #define SPD_EEPROM_ADDRESS	0x51	/* I2C1, DDR */
 
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /* Don't probe these addresses: */
-#define CFG_I2C_NOPROBES	{{1, CFG_I2C_8574_ADDR1}, \
-				 {1, CFG_I2C_8574_ADDR2}, \
-				 {1, CFG_I2C_8574A_ADDR1}, \
-				 {1, CFG_I2C_8574A_ADDR2}}
+#define CONFIG_SYS_I2C_NOPROBES	{{1, CONFIG_SYS_I2C_8574_ADDR1}, \
+				 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
+				 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
+				 {1, CONFIG_SYS_I2C_8574A_ADDR2}}
 /* Bit definitions for the 8574[A] I2C expander */
 #define I2C_8574_REVISION	0x03	/* Board revision, 00=0.0, 01=0.1, 10=1.0 */
 #define I2C_8574_CF		0x08	/* 1=Compact flash absent, 0=present */
@@ -129,15 +129,15 @@
 /* Compact Flash */
 #ifdef CONFIG_COMPACT_FLASH
 
-#define CFG_IDE_MAXBUS		1
-#define CFG_IDE_MAXDEVICE	1
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	1
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#define CFG_ATA_BASE_ADDR	CFG_CF_BASE
-#define CFG_ATA_DATA_OFFSET	0x0000
-#define CFG_ATA_REG_OFFSET	0
-#define CFG_ATA_ALT_OFFSET	0x0200
-#define CFG_ATA_STRIDE		2
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_CF_BASE
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000
+#define CONFIG_SYS_ATA_REG_OFFSET	0
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0200
+#define CONFIG_SYS_ATA_STRIDE		2
 
 #define ATA_RESET_TIME	1	/* If a CF card is not inserted, time out quickly */
 
@@ -148,14 +148,14 @@
 /*
  * DDR Setup
  */
-#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
-#define CFG_83XX_DDR_USES_CS0
-#define CFG_MEMTEST_START	0x1000		/* memtest region */
-#define CFG_MEMTEST_END		0x2000
-
-#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_83XX_DDR_USES_CS0
+#define CONFIG_SYS_MEMTEST_START	0x1000		/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x2000
+
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 
 #ifdef CONFIG_HARD_I2C
@@ -163,33 +163,34 @@
 #endif
 
 #ifndef CONFIG_SPD_EEPROM	/* No SPD? Then manually set up DDR parameters */
-    #define CFG_DDR_SIZE	256		/* Mb */
-    #define CFG_DDR_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+    #define CONFIG_SYS_DDR_SIZE	256		/* Mb */
+    #define CONFIG_SYS_DDR_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 
-    #define CFG_DDR_TIMING_1	0x26242321
-    #define CFG_DDR_TIMING_2	0x00000800  /* P9-45, may need tuning */
+    #define CONFIG_SYS_DDR_TIMING_1	0x26242321
+    #define CONFIG_SYS_DDR_TIMING_2	0x00000800  /* P9-45, may need tuning */
 #endif
 
 /*
  *Flash on the Local Bus
  */
 
-#define CFG_FLASH_CFI				/* use the Common Flash Interface */
+#define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
-#define CFG_FLASH_BASE		0xFE000000	/* start of FLASH   */
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_MAX_FLASH_SECT	135	/* 127 64KB sectors + 8 8KB sectors per device */
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_MAX_FLASH_SECT	135	/* 127 64KB sectors + 8 8KB sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 
 /* The ITX has two flash chips, but the ITX-GP has only one.  To support both
 boards, we say we have two, but don't display a message if we find only one. */
-#define CFG_FLASH_QUIET_TEST
-#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
-#define CFG_FLASH_BANKS_LIST	{CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000}
-#define CFG_FLASH_SIZE		16		/* FLASH size in MB */
-#define CFG_FLASH_SIZE_SHIFT	4		/* log2 of the above value */
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
+#define CONFIG_SYS_FLASH_SIZE		16		/* FLASH size in MB */
+#define CONFIG_SYS_FLASH_SIZE_SHIFT	4		/* log2 of the above value */
+#define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
 
 /* Vitesse 7385 */
 
@@ -209,34 +210,34 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 /* Flash */
 
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_PS_16 | BR_V)
-#define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR0_PRELIM		((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
-#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE
-#define CFG_LBLAWAR0_PRELIM	(LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT))
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
 
 /* Vitesse 7385 */
 
-#define CFG_VSC7385_BASE	0xF8000000
+#define CONFIG_SYS_VSC7385_BASE	0xF8000000
 
 #ifdef CONFIG_VSC7385_ENET
 
-#define CFG_BR1_PRELIM		(CFG_VSC7385_BASE | BR_PS_8 | BR_V)
-#define CFG_OR1_PRELIM		(OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM		(OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 				OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
 				OR_GPCM_EHTR | OR_GPCM_EAD)
 
-#define CFG_LBLAWBAR1_PRELIM	CFG_VSC7385_BASE
-#define CFG_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_VSC7385_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
 
 #endif
 
 /* LED */
 
-#define CFG_LED_BASE		0xF9000000
-#define CFG_BR2_PRELIM		(CFG_LED_BASE | BR_PS_8 | BR_V)
-#define CFG_OR2_PRELIM		(OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
+#define CONFIG_SYS_LED_BASE		0xF9000000
+#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR2_PRELIM		(OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 				OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \
 				OR_GPCM_EHTR | OR_GPCM_EAD)
 
@@ -244,39 +245,38 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 #ifdef CONFIG_COMPACT_FLASH
 
-#define CFG_CF_BASE		0xF0000000
+#define CONFIG_SYS_CF_BASE		0xF0000000
 
-#define CFG_BR3_PRELIM		(CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V)
-#define CFG_OR3_PRELIM		(OR_UPM_AM | OR_UPM_BI)
+#define CONFIG_SYS_BR3_PRELIM		(CONFIG_SYS_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V)
+#define CONFIG_SYS_OR3_PRELIM		(OR_UPM_AM | OR_UPM_BI)
 
-#define CFG_LBLAWBAR3_PRELIM	CFG_CF_BASE
-#define CFG_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_64KB)
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_CF_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_64KB)
 
 #endif
 
 /*
  * U-Boot memory configuration
  */
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef	CFG_RAMBOOT
+#undef	CONFIG_SYS_RAMBOOT
 #endif
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK
-#define CFG_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/
 
-#define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-/* CFG_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
 
 /*
  * Local Bus LCRR and LBCR regs
@@ -284,30 +284,30 @@ boards, we say we have two, but don't display a message if we find only one. */
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CFG_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
-#define CFG_LBC_LBCR	0x00000000
+#define CONFIG_SYS_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LBC_LBCR	0x00000000
 
-#define CFG_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
-#define CFG_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32*/
+#define CONFIG_SYS_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32*/
 
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 
 #define CONFIG_CONSOLE		ttyS0
 #define CONFIG_BAUDRATE		115200
 
-#define CFG_NS16550_COM1	(CFG_IMMR + 0x4500)
-#define CFG_NS16550_COM2	(CFG_IMMR + 0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
 
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
@@ -325,26 +325,26 @@ boards, we say we have two, but don't display a message if we find only one. */
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCI1_MMIO_BASE	(CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE)
-#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
-#define CFG_PCI1_MMIO_SIZE	0x10000000	/* 256M */
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xE2000000
-#define CFG_PCI1_IO_SIZE	0x01000000	/* 16M */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000	/* 16M */
 
 #ifdef CONFIG_MPC83XX_PCI2
-#define CFG_PCI2_MEM_BASE	(CFG_PCI1_MMIO_BASE + CFG_PCI1_MMIO_SIZE)
-#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCI2_MMIO_BASE	(CFG_PCI2_MEM_BASE + CFG_PCI2_MEM_SIZE)
-#define CFG_PCI2_MMIO_PHYS	CFG_PCI2_MMIO_BASE
-#define CFG_PCI2_MMIO_SIZE	0x10000000	/* 256M */
-#define CFG_PCI2_IO_BASE	0x00000000
-#define CFG_PCI2_IO_PHYS	(CFG_PCI1_IO_PHYS + CFG_PCI1_IO_SIZE)
-#define CFG_PCI2_IO_SIZE	0x01000000	/* 16M */
+#define CONFIG_SYS_PCI2_MEM_BASE	(CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE	(CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
+#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS	(CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
+#define CONFIG_SYS_PCI2_IO_SIZE	0x01000000	/* 16M */
 #endif
 
 #define _IO_BASE		0x00000000	/* points to PCI I/O space */
@@ -359,7 +359,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 #ifndef CONFIG_PCI_PNP
     #define PCI_ENET0_IOADDR	0x00000000
-    #define PCI_ENET0_MEMADDR	CFG_PCI2_MEM_BASE
+    #define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI2_MEM_BASE
     #define PCI_IDSEL_NUMBER	0x0f	/* IDSEL = AD15 */
 #endif
 
@@ -387,7 +387,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 #ifdef CONFIG_TSEC1
 #define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME  "TSEC0"
-#define CFG_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
 #define TSEC1_PHY_ADDR		0x1c	/* VSC8201 uses address 0x1c */
 #define TSEC1_PHYIDX		0
 #define TSEC1_FLAGS		TSEC_GIGABIT
@@ -396,7 +396,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 #ifdef CONFIG_TSEC2
 #define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME  "TSEC1"
-#define CFG_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
 
 #define TSEC2_PHY_ADDR		4
 #define TSEC2_PHYIDX		0
@@ -412,21 +412,21 @@ boards, we say we have two, but don't display a message if we find only one. */
  */
 #define CONFIG_ENV_OVERWRITE
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
   #define CONFIG_ENV_IS_IN_FLASH
-  #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
   #define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K (one sector) for environment */
   #define CONFIG_ENV_SIZE		0x2000
 #else
-  #define CFG_NO_FLASH		/* Flash is not usable now */
+  #define CONFIG_SYS_NO_FLASH		/* Flash is not usable now */
   #undef  CONFIG_FLASH_CFI_DRIVER
   #define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
-  #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
   #define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -468,47 +468,47 @@ boards, we say we have two, but don't display a message if we find only one. */
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
-#define CFG_HUSH_PARSER			/* Use the HUSH parser */
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER			/* Use the HUSH parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_LOADADDR	500000	/* default location for tftp and bootm */
 
 #ifdef CONFIG_MPC8349ITX
-#define CFG_PROMPT	"MPC8349E-mITX> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT	"MPC8349E-mITX> "	/* Monitor Command Prompt */
 #else
-#define CFG_PROMPT	"MPC8349E-mITX-GP> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT	"MPC8349E-mITX-GP> "	/* Monitor Command Prompt */
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN_4X1 |\
 	HRCWL_VCO_1X2 |\
 	HRCWL_CORE_TO_CSB_2X1)
 
-#ifdef CFG_LOWBOOT
-#define CFG_HRCW_HIGH (\
+#ifdef CONFIG_SYS_LOWBOOT
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_32_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
@@ -521,7 +521,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 	HRCWH_TSEC1M_IN_GMII |\
 	HRCWH_TSEC2M_IN_GMII )
 #else
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_32_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
@@ -538,81 +538,81 @@ boards, we say we have two, but don't display a message if we find only one. */
 /*
  * System performance
  */
-#define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
-#define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
-#define CFG_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
-#define CFG_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
-#define CFG_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
-#define CFG_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
+#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
+#define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
+#define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
+#define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
 
 /*
  * System IO Config
  */
-#define CFG_SICRH SICRH_TSOBI1	/* Needed for gigabit to work on TSEC 1 */
-#define CFG_SICRL (SICRL_LDP_A | SICRL_USB1)
+#define CONFIG_SYS_SICRH SICRH_TSOBI1	/* Needed for gigabit to work on TSEC 1 */
+#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
 
-#define CFG_HID0_INIT	0x000000000
-#define CFG_HID0_FINAL	CFG_HID0_INIT
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	CONFIG_SYS_HID0_INIT
 
-#define CFG_HID2	HID2_HBE
+#define CONFIG_SYS_HID2	HID2_HBE
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR  */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* PCI  */
 #ifdef CONFIG_PCI
-#define CFG_IBAT1L	(CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT2L	(CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT2U	(CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #else
-#define CFG_IBAT1L	0
-#define CFG_IBAT1U	0
-#define CFG_IBAT2L	0
-#define CFG_IBAT2U	0
+#define CONFIG_SYS_IBAT1L	0
+#define CONFIG_SYS_IBAT1U	0
+#define CONFIG_SYS_IBAT2L	0
+#define CONFIG_SYS_IBAT2U	0
 #endif
 
 #ifdef CONFIG_MPC83XX_PCI2
-#define CFG_IBAT3L	(CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT3U	(CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT4L	(CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT4U	(CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #else
-#define CFG_IBAT3L	0
-#define CFG_IBAT3U	0
-#define CFG_IBAT4L	0
-#define CFG_IBAT4U	0
+#define CONFIG_SYS_IBAT3L	0
+#define CONFIG_SYS_IBAT3U	0
+#define CONFIG_SYS_IBAT4L	0
+#define CONFIG_SYS_IBAT4U	0
 #endif
 
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CFG_IBAT5L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT5U	(CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CFG_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT7L	0
-#define CFG_IBAT7U	0
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
-#define CFG_DBAT4L	CFG_IBAT4L
-#define CFG_DBAT4U	CFG_IBAT4U
-#define CFG_DBAT5L	CFG_IBAT5L
-#define CFG_DBAT5U	CFG_IBAT5U
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT7L	0
+#define CONFIG_SYS_IBAT7U	0
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index f60d7a7..bdd6b87 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -49,7 +49,7 @@
 /*
  * Hardware Reset Configuration Word
  */
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN_4X1 |\
@@ -60,7 +60,7 @@
 	HRCWL_CORE_TO_CSB_2X1)
 
 #ifdef CONFIG_PCISLAVE
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_AGENT |\
 	HRCWH_PCI1_ARBITER_DISABLE |\
 	HRCWH_PCICKDRV_DISABLE |\
@@ -70,7 +70,7 @@
 	HRCWH_SW_WATCHDOG_DISABLE |\
 	HRCWH_ROM_LOC_LOCAL_16BIT)
 #else
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_PCICKDRV_ENABLE |\
@@ -84,8 +84,8 @@
 /*
  * System IO Config
  */
-#define CFG_SICRH		0x00000000
-#define CFG_SICRL		0x40000000
+#define CONFIG_SYS_SICRH		0x00000000
+#define CONFIG_SYS_SICRL		0x40000000
 
 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
 #define CONFIG_BOARD_EARLY_INIT_R
@@ -93,18 +93,19 @@
 /*
  * IMMR new address
  */
-#define CFG_IMMR		0xE0000000
+#define CONFIG_SYS_IMMR		0xE0000000
 
 /*
  * DDR Setup
  */
-#define CFG_DDR_BASE		0x00000000 /* DDR is system memory */
-#define CFG_SDRAM_BASE		CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
-#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE2		(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* + 256M */
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 
-#define CFG_83XX_DDR_USES_CS0
+#define CONFIG_SYS_83XX_DDR_USES_CS0
 
 #define CONFIG_DDR_ECC		/* support DDR ECC function */
 #define CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
@@ -112,7 +113,7 @@
 /*
  * DDRCDR - DDR Control Driver Register
  */
-#define CFG_DDRCDR_VALUE	0x80080001
+#define CONFIG_SYS_DDRCDR_VALUE	0x80080001
 
 #define CONFIG_SPD_EEPROM	/* Use SPD EEPROM for DDR setup */
 #if defined(CONFIG_SPD_EEPROM)
@@ -124,138 +125,135 @@
 /*
  * Manually set up DDR parameters
  */
-#define CFG_DDR_SIZE		256 /* MB */
+#define CONFIG_SYS_DDR_SIZE		256 /* MB */
 #if defined(CONFIG_DDR_II)
-#define CFG_DDRCDR		0x80080001
-#define CFG_DDR_CS0_BNDS	0x0000000f
-#define CFG_DDR_CS0_CONFIG	0x80330102
-#define CFG_DDR_TIMING_0	0x00220802
-#define CFG_DDR_TIMING_1	0x38357322
-#define CFG_DDR_TIMING_2	0x2f9048c8
-#define CFG_DDR_TIMING_3	0x00000000
-#define CFG_DDR_CLK_CNTL	0x02000000
-#define CFG_DDR_MODE		0x47d00432
-#define CFG_DDR_MODE2		0x8000c000
-#define CFG_DDR_INTERVAL	0x03cf0080
-#define CFG_DDR_SDRAM_CFG	0x43000000
-#define CFG_DDR_SDRAM_CFG2	0x00401000
+#define CONFIG_SYS_DDRCDR		0x80080001
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000f
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80330102
+#define CONFIG_SYS_DDR_TIMING_0	0x00220802
+#define CONFIG_SYS_DDR_TIMING_1	0x38357322
+#define CONFIG_SYS_DDR_TIMING_2	0x2f9048c8
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL	0x02000000
+#define CONFIG_SYS_DDR_MODE		0x47d00432
+#define CONFIG_SYS_DDR_MODE2		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL	0x03cf0080
+#define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
 #else
-#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
-#define CFG_DDR_TIMING_1	0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
-#define CFG_DDR_TIMING_2	0x00000800 /* may need tuning */
-#define CFG_DDR_CONTROL		0x42008000 /* Self refresh,2T timing */
-#define CFG_DDR_MODE		0x20000162 /* DLL,normal,seq,4/2.5 */
-#define CFG_DDR_INTERVAL	0x045b0100 /* page mode */
+#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
+#define CONFIG_SYS_DDR_TIMING_1	0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
+#define CONFIG_SYS_DDR_TIMING_2	0x00000800 /* may need tuning */
+#define CONFIG_SYS_DDR_CONTROL		0x42008000 /* Self refresh,2T timing */
+#define CONFIG_SYS_DDR_MODE		0x20000162 /* DLL,normal,seq,4/2.5 */
+#define CONFIG_SYS_DDR_INTERVAL	0x045b0100 /* page mode */
 #endif
 #endif
 
 /*
  * Memory test
  */
-#undef CFG_DRAM_TEST		/* memory test, takes time */
-#define CFG_MEMTEST_START	0x00000000 /* memtest region */
-#define CFG_MEMTEST_END		0x00100000
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
 
 /*
  * The reserved memory
  */
 
-#define CFG_MONITOR_BASE	TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE /* start of monitor */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef	CFG_RAMBOOT
+#undef	CONFIG_SYS_RAMBOOT
 #endif
 
-/* CFG_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
 
 /*
  * Initial RAM Base Address Setup
  */
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CFG_INIT_RAM_END	0x1000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE	0x100 /* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_4)
-#define CFG_LBC_LBCR		0x00000000
+#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LBC_LBCR		0x00000000
 
 /*
  * FLASH on the Local Bus
  */
-#define CFG_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
-#define CFG_FLASH_BASE		0xFE000000 /* FLASH base address */
-#define CFG_FLASH_SIZE		32 /* max FLASH size is 32M */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		32 /* max FLASH size is 32M */
+#define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 
-#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE /* Window base at flash base */
-#define CFG_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE /* Window base at flash base */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */
 
-#define CFG_BR0_PRELIM	(CFG_FLASH_BASE | /* Flash Base address */ \
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
 			(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 			BR_V)	/* valid */
-#define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
+#define CONFIG_SYS_OR0_PRELIM		((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 
-#define CFG_MAX_FLASH_BANKS	1 /* number of banks */
-#define CFG_MAX_FLASH_SECT	256 /* max sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
 
-#undef	CFG_FLASH_CHECKSUM
+#undef	CONFIG_SYS_FLASH_CHECKSUM
 
 /*
  * BCSR on the Local Bus
  */
-#define CFG_BCSR		0xF8000000
-#define CFG_LBLAWBAR1_PRELIM	CFG_BCSR /* Access window base at BCSR base */
-#define CFG_LBLAWAR1_PRELIM	0x8000000F /* Access window size 64K */
+#define CONFIG_SYS_BCSR		0xF8000000
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR /* Access window base at BCSR base */
+#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000F /* Access window size 64K */
 
-#define CFG_BR1_PRELIM		(CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
-#define CFG_OR1_PRELIM		0xFFFFE9f7 /* length 32K */
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
+#define CONFIG_SYS_OR1_PRELIM		0xFFFFE9f7 /* length 32K */
 
 /*
  * SDRAM on the Local Bus
  */
-#define CFG_LBC_SDRAM_BASE	0xF0000000	/* SDRAM base address */
-#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xF0000000	/* SDRAM base address */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
 
-#define CFG_LB_SDRAM		/* if board has SRDAM on local bus */
+#define CONFIG_SYS_LB_SDRAM		/* if board has SRDAM on local bus */
 
-#ifdef CFG_LB_SDRAM
-#define CFG_LBLAWBAR2_PRELIM	CFG_LBC_SDRAM_BASE
-#define CFG_LBLAWAR2_PRELIM	0x80000019 /* 64MB */
+#ifdef CONFIG_SYS_LB_SDRAM
+#define CONFIG_SYS_LBLAWBAR2		0
+#define CONFIG_SYS_LBLAWAR2		0x80000019 /* 64MB */
 
 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
 /*
  * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
  *
  * For BR2, need:
- *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    Base address = BR[0:16] = dynamic
  *    port size = 32-bits = BR2[19:20] = 11
  *    no parity checking = BR2[21:22] = 00
  *    SDRAM for MSEL = BR2[24:26] = 011
  *    Valid = BR[31] = 1
  *
  * 0	4    8	  12   16   20	 24   28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
- *
- * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
- * the top 17 bits of BR2.
+ * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861
  */
 
-#define CFG_BR2_PRELIM	0xf0001861 /*Port size=32bit, MSEL=SDRAM */
+#define CONFIG_SYS_BR2		0x00001861 /*Port size=32bit, MSEL=SDRAM */
 
 /*
- * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  *
  * For OR2, need:
  *    64MB mask for AM, OR2[0:7] = 1111 1100
@@ -268,80 +266,80 @@
  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  */
 
-#define CFG_OR2_PRELIM	0xfc006901
+#define CONFIG_SYS_OR2		0xfc006901
 
-#define CFG_LBC_LSRT	0x32000000 /* LB sdram refresh timer, about 6us */
-#define CFG_LBC_MRTPR	0x20000000 /* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_LSRT	0x32000000 /* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_MRTPR	0x20000000 /* LB refresh timer prescal, 266MHz/32 */
 
 /*
  * LSDMR masks
  */
-#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
 
-#define CFG_LBC_LSDMR_COMMON	0x0063b723
+#define CONFIG_SYS_LBC_LSDMR_COMMON	0x0063b723
 
 /*
  * SDRAM Controller configuration sequence.
  */
-#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_PCHALL)
-#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_MRW)
-#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_NORMAL)
+#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
 
 #endif
 
 /*
  * Windows to access PIB via local bus
  */
-#define CFG_LBLAWBAR3_PRELIM	0xf8010000 /* windows base 0xf8010000 */
-#define CFG_LBLAWAR3_PRELIM	0x8000000e /* windows size 32KB */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	0xf8010000 /* windows base 0xf8010000 */
+#define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000000e /* windows size 32KB */
 
 /*
  * CS4 on Local Bus, to PIB
  */
-#define CFG_BR4_PRELIM	0xf8010801 /* CS4 base address at 0xf8010000 */
-#define CFG_OR4_PRELIM	0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
+#define CONFIG_SYS_BR4_PRELIM	0xf8010801 /* CS4 base address at 0xf8010000 */
+#define CONFIG_SYS_OR4_PRELIM	0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
 
 /*
  * CS5 on Local Bus, to PIB
  */
-#define CFG_BR5_PRELIM	0xf8008801 /* CS5 base address at 0xf8008000 */
-#define CFG_OR5_PRELIM	0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
+#define CONFIG_SYS_BR5_PRELIM	0xf8008801 /* CS5 base address at 0xf8008000 */
+#define CONFIG_SYS_OR5_PRELIM	0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
 
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
-#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* pass open firmware flat tree */
@@ -353,35 +351,35 @@
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
 #define CONFIG_FSL_I2C
-#define CFG_I2C_SPEED	400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE	0x7F
-#define CFG_I2C_NOPROBES	{0x52} /* Don't probe these addrs */
-#define CFG_I2C_OFFSET	0x3000
-#define CFG_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{0x52} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
 
 /*
  * Config on-board RTC
  */
 #define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
-#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68 */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68 */
 
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI_MEM_BASE	0x80000000
-#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BASE
-#define CFG_PCI_MEM_SIZE	0x10000000 /* 256M */
-#define CFG_PCI_MMIO_BASE	0x90000000
-#define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
-#define CFG_PCI_MMIO_SIZE	0x10000000 /* 256M */
-#define CFG_PCI_IO_BASE		0x00000000
-#define CFG_PCI_IO_PHYS		0xE0300000
-#define CFG_PCI_IO_SIZE		0x100000 /* 1M */
+#define CONFIG_SYS_PCI_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
+#define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
 
-#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE
-#define CFG_PCI_SLV_MEM_BUS	0x00000000
-#define CFG_PCI_SLV_MEM_SIZE	0x80000000
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
+#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
 
 
 #ifdef CONFIG_PCI
@@ -391,7 +389,7 @@
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
 
 #endif	/* CONFIG_PCI */
 
@@ -410,43 +408,43 @@
 #define CONFIG_UEC_ETH1		/* GETH1 */
 
 #ifdef CONFIG_UEC_ETH1
-#define CFG_UEC1_UCC_NUM	0	/* UCC1 */
-#define CFG_UEC1_RX_CLK		QE_CLK_NONE
-#define CFG_UEC1_TX_CLK		QE_CLK9
-#define CFG_UEC1_ETH_TYPE	GIGA_ETH
-#define CFG_UEC1_PHY_ADDR	0
-#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
+#define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE
+#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK9
+#define CONFIG_SYS_UEC1_ETH_TYPE	GIGA_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	0
+#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_GMII
 #endif
 
 #define CONFIG_UEC_ETH2		/* GETH2 */
 
 #ifdef CONFIG_UEC_ETH2
-#define CFG_UEC2_UCC_NUM	1	/* UCC2 */
-#define CFG_UEC2_RX_CLK		QE_CLK_NONE
-#define CFG_UEC2_TX_CLK		QE_CLK4
-#define CFG_UEC2_ETH_TYPE	GIGA_ETH
-#define CFG_UEC2_PHY_ADDR	1
-#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
+#define CONFIG_SYS_UEC2_UCC_NUM	1	/* UCC2 */
+#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK_NONE
+#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK4
+#define CONFIG_SYS_UEC2_ETH_TYPE	GIGA_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR	1
+#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_GMII
 #endif
 
 /*
  * Environment
  */
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 	#define CONFIG_ENV_SECT_SIZE	0x20000
 	#define CONFIG_ENV_SIZE		0x2000
 #else
-	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 	#define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -471,8 +469,8 @@
     #define CONFIG_CMD_PCI
 #endif
 
-#if defined(CFG_RAMBOOT)
-    #undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 
@@ -482,34 +480,34 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory */
-#define CFG_LOAD_ADDR		0x2000000 /* default load address */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-	#define CFG_CBSIZE	1024 /* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
 #else
-	#define CFG_CBSIZE	256 /* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*
  * Core HID Setup
  */
-#define CFG_HID0_INIT		0x000000000
-#define CFG_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
-#define CFG_HID2		HID2_HBE
+#define CONFIG_SYS_HID0_INIT		0x000000000
+#define CONFIG_SYS_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID2		HID2_HBE
 
 /*
  * MMU Setup
@@ -517,66 +515,66 @@
 
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
-/* DDR: cache cacheable */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
+/* DDR/LBC SDRAM: cacheable */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 
 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CFG_IBAT1L	(CFG_IMMR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT1U	(CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 
 /* BCSR: cache-inhibit and guarded */
-#define CFG_IBAT2L	(CFG_BCSR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_BCSR | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT2U	(CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CFG_IBAT3L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT3U	(CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_DBAT3L	(CFG_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
-/* Local bus SDRAM: cacheable */
-#define CFG_IBAT4L	(CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT4U	(CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
-#define CFG_DBAT4L	CFG_IBAT4L
-#define CFG_DBAT4U	CFG_IBAT4U
+/* DDR/LBC SDRAM next 256M: cacheable */
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_SDRAM_BASE2 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_SDRAM_BASE2 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 
 /* Stack in dcache: cacheable, no memory coherence */
-#define CFG_IBAT5L	(CFG_INIT_RAM_ADDR | BATL_PP_10)
-#define CFG_IBAT5U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_DBAT5L	CFG_IBAT5L
-#define CFG_DBAT5U	CFG_IBAT5U
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 
 #ifdef CONFIG_PCI
 /* PCI MEM space: cacheable */
-#define CFG_IBAT6L	(CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U	(CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 /* PCI MMIO space: cache-inhibit and guarded */
-#define CFG_IBAT7L	(CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT7U	(CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #else
-#define CFG_IBAT6L	(0)
-#define CFG_IBAT6U	(0)
-#define CFG_IBAT7L	(0)
-#define CFG_IBAT7U	(0)
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT6L	(0)
+#define CONFIG_SYS_IBAT6U	(0)
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #endif
 
 /*
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index b2e6b3b..f7ebdaa 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -44,14 +44,14 @@
 /*
  * Hardware Reset Configuration Word
  */
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
 	HRCWL_CORE_TO_CSB_2X1 |\
 	HRCWL_CE_TO_PLL_1X15)
 
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_PCICKDRV_ENABLE |\
@@ -67,8 +67,8 @@
 /*
  * System IO Config
  */
-#define CFG_SICRH		0x00000000
-#define CFG_SICRL		0x40000000
+#define CONFIG_SYS_SICRH		0x00000000
+#define CONFIG_SYS_SICRL		0x40000000
 
 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
 #define CONFIG_BOARD_EARLY_INIT_R
@@ -76,18 +76,18 @@
 /*
  * IMMR new address
  */
-#define CFG_IMMR		0xE0000000
+#define CONFIG_SYS_IMMR		0xE0000000
 
 /*
  * DDR Setup
  */
-#define CFG_DDR_BASE		0x00000000 /* DDR is system memory */
-#define CFG_SDRAM_BASE		CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
-#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 
-#define CFG_83XX_DDR_USES_CS0
+#define CONFIG_SYS_83XX_DDR_USES_CS0
 
 #define CONFIG_DDR_ECC		/* support DDR ECC function */
 #define CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
@@ -95,7 +95,7 @@
 /*
  * DDRCDR - DDR Control Driver Register
  */
-#define CFG_DDRCDR_VALUE	0x80080001
+#define CONFIG_SYS_DDRCDR_VALUE	0x80080001
 
 #undef CONFIG_SPD_EEPROM	/* Do not use SPD EEPROM for DDR setup */
 
@@ -103,19 +103,19 @@
  * Manually set up DDR parameters
  */
 #define CONFIG_DDR_II
-#define CFG_DDR_SIZE		256 /* MB */
-#define CFG_DDR_CS0_BNDS	0x0000000f
-#define CFG_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
+#define CONFIG_SYS_DDR_SIZE		256 /* MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000f
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
 				 CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
-#define CFG_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN)
-#define CFG_DDR_SDRAM_CFG2	0x00001000
-#define CFG_DDR_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CFG_DDR_INTERVAL	((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN)
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000
+#define CONFIG_SYS_DDR_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL	((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 				 (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
-#define CFG_DDR_MODE		0x47800432
-#define CFG_DDR_MODE2		0x8000c000
+#define CONFIG_SYS_DDR_MODE		0x47800432
+#define CONFIG_SYS_DDR_MODE2		0x8000c000
 
-#define CFG_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 				 (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 				 (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 				 (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
@@ -124,7 +124,7 @@
 				 (0 << TIMING_CFG0_WRT_SHIFT) | \
 				 (0 << TIMING_CFG0_RWT_SHIFT))
 
-#define CFG_DDR_TIMING_1	((      TIMING_CFG1_CASLAT_30) | \
+#define CONFIG_SYS_DDR_TIMING_1	((      TIMING_CFG1_CASLAT_30) | \
 				 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
 				 ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 				 ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
@@ -133,7 +133,7 @@
 				 ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 				 ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
 
-#define CFG_DDR_TIMING_2	((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+#define CONFIG_SYS_DDR_TIMING_2	((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 				 (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
@@ -141,119 +141,118 @@
 				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 				 (0 << TIMING_CFG2_CPO_SHIFT))
 
-#define CFG_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
 
 /*
  * Memory test
  */
-#undef CFG_DRAM_TEST		/* memory test, takes time */
-#define CFG_MEMTEST_START	0x00000000 /* memtest region */
-#define CFG_MEMTEST_END		0x00100000
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
 
 /*
  * The reserved memory
  */
-#define CFG_MONITOR_BASE	TEXT_BASE /* start of monitor */
-#define CFG_FLASH_BASE		0xFF800000 /* FLASH base address */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_FLASH_BASE		0xFF800000 /* FLASH base address */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef	CFG_RAMBOOT
+#undef	CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
 
 /*
  * Initial RAM Base Address Setup
  */
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CFG_INIT_RAM_END	0x1000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE	0x100 /* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_4)
-#define CFG_LBC_LBCR		0x00000000
+#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LBC_LBCR		0x00000000
 
 /*
  * FLASH on the Local Bus
  */
-#define CFG_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
-#define CFG_FLASH_SIZE		8 /* max FLASH size is 32M */
-#define CFG_FLASH_PROTECTION	1 /* Use intel Flash protection. */
+#define CONFIG_SYS_FLASH_SIZE		8 /* max FLASH size is 32M */
+#define CONFIG_SYS_FLASH_PROTECTION	1 /* Use intel Flash protection. */
 
-#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE /* Window base at flash base */
-#define CFG_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE /* Window base at flash base */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */
 
-#define CFG_BR0_PRELIM	(CFG_FLASH_BASE | /* Flash Base address */ \
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
 			(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 			BR_V)	/* valid */
-#define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
+#define CONFIG_SYS_OR0_PRELIM		((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 				OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 
-#define CFG_MAX_FLASH_BANKS	1 /* number of banks */
-#define CFG_MAX_FLASH_SECT	256 /* max sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
 
-#undef	CFG_FLASH_CHECKSUM
+#undef	CONFIG_SYS_FLASH_CHECKSUM
 
 /*
  * NAND flash on the local bus
  */
-#define CFG_NAND_BASE		0x60000000
+#define CONFIG_SYS_NAND_BASE		0x60000000
 #define CONFIG_CMD_NAND		1
 #define CONFIG_NAND_FSL_UPM	1
-#define CFG_MAX_NAND_DEVICE	1
-#define NAND_MAX_CHIPS		1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
-#define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
-#define CFG_LBLAWAR1_PRELIM	0x8000001b /* Access window size 4K */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000001b /* Access window size 4K */
 
 /* Port size 8 bit, UPMA */
-#define CFG_BR1_PRELIM		(CFG_NAND_BASE | 0x00000881)
-#define CFG_OR1_PRELIM		0xfc000001
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_NAND_BASE | 0x00000881)
+#define CONFIG_SYS_OR1_PRELIM		0xfc000001
 
 /*
  * Fujitsu MB86277 (MINT) graphics controller
  */
-#define CFG_VIDEO_BASE		0x70000000
+#define CONFIG_SYS_VIDEO_BASE		0x70000000
 
-#define CFG_LBLAWBAR2_PRELIM	CFG_VIDEO_BASE
-#define CFG_LBLAWAR2_PRELIM	0x80000019 /* Access window size 64MB */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VIDEO_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000019 /* Access window size 64MB */
 
 /* Port size 32 bit, UPMB */
-#define CFG_BR2_PRELIM		(CFG_VIDEO_BASE | 0x000018a1) /* PS=11, UPMB */
-#define CFG_OR2_PRELIM		0xfc000001 /* (64MB, EAD=1) */
+#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_VIDEO_BASE | 0x000018a1) /* PS=11, UPMB */
+#define CONFIG_SYS_OR2_PRELIM		0xfc000001 /* (64MB, EAD=1) */
 
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200,}
 
-#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
-#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* Pass open firmware flat tree */
@@ -267,11 +266,11 @@
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
-#define CFG_I2C_SPEED	400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE	0x7F
-#define CFG_I2C_NOPROBES	{{0x52}} /* Don't probe these addrs */
-#define CFG_I2C_OFFSET	0x3000
-#define CFG_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{{0x52}} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
 
 /*
  * General PCI
@@ -280,15 +279,15 @@
 #define CONFIG_PCI
 #define CONFIG_83XX_GENERIC_PCI	1
 
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x10000000 /* 256M */
-#define CFG_PCI1_MMIO_BASE	0x90000000
-#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
-#define CFG_PCI1_MMIO_SIZE	0x10000000 /* 256M */
-#define CFG_PCI1_IO_BASE	0xE0300000
-#define CFG_PCI1_IO_PHYS	0xE0300000
-#define CFG_PCI1_IO_SIZE	0x100000 /* 1M */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE	0xE0300000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xE0300000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x100000 /* 1M */
 
 #ifdef CONFIG_PCI
 
@@ -297,7 +296,7 @@
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
 
 #endif	/* CONFIG_PCI */
 
@@ -315,43 +314,43 @@
 #define CONFIG_UEC_ETH1		/* GETH1 */
 
 #ifdef CONFIG_UEC_ETH1
-#define CFG_UEC1_UCC_NUM	0	/* UCC1 */
-#define CFG_UEC1_RX_CLK		QE_CLK_NONE
-#define CFG_UEC1_TX_CLK		QE_CLK9
-#define CFG_UEC1_ETH_TYPE	GIGA_ETH
-#define CFG_UEC1_PHY_ADDR	2
-#define CFG_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
+#define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE
+#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK9
+#define CONFIG_SYS_UEC1_ETH_TYPE	GIGA_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	2
+#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
 #endif
 
 #define CONFIG_UEC_ETH2		/* GETH2 */
 
 #ifdef CONFIG_UEC_ETH2
-#define CFG_UEC2_UCC_NUM	1	/* UCC2 */
-#define CFG_UEC2_RX_CLK		QE_CLK_NONE
-#define CFG_UEC2_TX_CLK		QE_CLK4
-#define CFG_UEC2_ETH_TYPE	GIGA_ETH
-#define CFG_UEC2_PHY_ADDR	4
-#define CFG_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
+#define CONFIG_SYS_UEC2_UCC_NUM	1	/* UCC2 */
+#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK_NONE
+#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK4
+#define CONFIG_SYS_UEC2_ETH_TYPE	GIGA_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR	4
+#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
 #endif
 
 /*
  * Environment
  */
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
 #define CONFIG_ENV_SIZE		0x20000
-#else /* CFG_RAMBOOT */
-#define CFG_NO_FLASH		1	/* Flash is not usable now */
+#else /* CONFIG_SYS_RAMBOOT */
+#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
 #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #define CONFIG_ENV_SIZE		0x2000
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -376,8 +375,8 @@
 #define CONFIG_CMD_PCI
 #endif
 
-#if defined(CFG_RAMBOOT)
-#undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT)
+#undef CONFIG_CMD_SAVEENV
 #undef CONFIG_CMD_LOADS
 #endif
 
@@ -386,34 +385,34 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory */
-#define CFG_LOAD_ADDR		0x2000000 /* default load address */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-	#define CFG_CBSIZE	1024 /* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
 #else
-	#define CFG_CBSIZE	256 /* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*
  * Core HID Setup
  */
-#define CFG_HID0_INIT		0x000000000
-#define CFG_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
-#define CFG_HID2		HID2_HBE
+#define CONFIG_SYS_HID0_INIT		0x000000000
+#define CONFIG_SYS_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID2		HID2_HBE
 
 /*
  * MMU Setup
@@ -422,65 +421,65 @@
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR: cache cacheable */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 
 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CFG_IBAT1L	(CFG_IMMR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT1U	(CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 
 /* NAND: cache-inhibit and guarded */
-#define CFG_IBAT2L	(CFG_NAND_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_NAND_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
 			 BATL_GUARDEDSTORAGE)
-#define CFG_IBAT2U	(CFG_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CFG_IBAT3L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT3U	(CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_DBAT3L	(CFG_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 			 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 /* Stack in dcache: cacheable, no memory coherence */
-#define CFG_IBAT4L	(CFG_INIT_RAM_ADDR | BATL_PP_10)
-#define CFG_IBAT4U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_DBAT4L	CFG_IBAT4L
-#define CFG_DBAT4U	CFG_IBAT4U
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 
-#define CFG_IBAT5L	(CFG_VIDEO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_VIDEO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \
 			 BATL_GUARDEDSTORAGE)
-#define CFG_IBAT5U	(CFG_VIDEO_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
-#define CFG_DBAT5L	CFG_IBAT5L
-#define CFG_DBAT5U	CFG_IBAT5U
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_VIDEO_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 
 #ifdef CONFIG_PCI
 /* PCI MEM space: cacheable */
-#define CFG_IBAT6L	(CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U	(CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 /* PCI MMIO space: cache-inhibit and guarded */
-#define CFG_IBAT7L	(CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
 			 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT7U	(CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #else /* CONFIG_PCI */
-#define CFG_IBAT6L	(0)
-#define CFG_IBAT6U	(0)
-#define CFG_IBAT7L	(0)
-#define CFG_IBAT7U	(0)
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT6L	(0)
+#define CONFIG_SYS_IBAT6U	(0)
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #endif /* CONFIG_PCI */
 
 /*
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 7c87388..a62d805 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -47,7 +47,7 @@
  * if CLKIN is 66MHz, then
  * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
  */
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_SVCOD_DIV_2 |\
@@ -55,7 +55,7 @@
 	HRCWL_CORE_TO_CSB_1_5X1)
 
 #ifdef CONFIG_PCISLAVE
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_AGENT |\
 	HRCWH_PCI1_ARBITER_DISABLE |\
 	HRCWH_CORE_ENABLE |\
@@ -69,7 +69,7 @@
 	HRCWH_BIG_ENDIAN |\
 	HRCWH_LDP_CLEAR)
 #else
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_CORE_ENABLE |\
@@ -85,29 +85,29 @@
 #endif
 
 /* Arbiter Configuration Register */
-#define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth is 4 */
-#define CFG_ACR_RPTCNT		3	/* Arbiter repeat count is 4 */
+#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth is 4 */
+#define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count is 4 */
 
 /* System Priority Control Register */
-#define CFG_SPCR_TSECEP		3	/* eTSEC1/2 emergency has highest priority */
+#define CONFIG_SYS_SPCR_TSECEP		3	/* eTSEC1/2 emergency has highest priority */
 
 /*
  * IP blocks clock configuration
  */
-#define CFG_SCCR_TSEC1CM	1	/* CSB:eTSEC1 = 1:1 */
-#define CFG_SCCR_TSEC2CM	1	/* CSB:eTSEC2 = 1:1 */
-#define CFG_SCCR_SATACM		SCCR_SATACM_2	/* CSB:SATA[0:3] = 2:1 */
+#define CONFIG_SYS_SCCR_TSEC1CM	1	/* CSB:eTSEC1 = 1:1 */
+#define CONFIG_SYS_SCCR_TSEC2CM	1	/* CSB:eTSEC2 = 1:1 */
+#define CONFIG_SYS_SCCR_SATACM		SCCR_SATACM_2	/* CSB:SATA[0:3] = 2:1 */
 
 /*
  * System IO Config
  */
-#define CFG_SICRH		0x00000000
-#define CFG_SICRL		0x00000000
+#define CONFIG_SYS_SICRH		0x00000000
+#define CONFIG_SYS_SICRL		0x00000000
 
 /*
  * Output Buffer Impedance
  */
-#define CFG_OBIR		0x31100000
+#define CONFIG_SYS_OBIR		0x31100000
 
 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
 #define CONFIG_BOARD_EARLY_INIT_R
@@ -115,17 +115,17 @@
 /*
  * IMMR new address
  */
-#define CFG_IMMR		0xE0000000
+#define CONFIG_SYS_IMMR		0xE0000000
 
 /*
  * DDR Setup
  */
-#define CFG_DDR_BASE		0x00000000 /* DDR is system memory */
-#define CFG_SDRAM_BASE		CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
-#define CFG_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-#define CFG_83XX_DDR_USES_CS0
-#define CFG_DDRCDR_VALUE	0x80080001 /* ODT 150ohm on SoC */
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_83XX_DDR_USES_CS0
+#define CONFIG_SYS_DDRCDR_VALUE	0x80080001 /* ODT 150ohm on SoC */
 
 #undef CONFIG_DDR_ECC		/* support DDR ECC function */
 #undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
@@ -141,14 +141,14 @@
  * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
  * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
  */
-#define CFG_DDR_SIZE		512 /* MB */
-#define CFG_DDR_CS0_BNDS	0x0000001f
-#define CFG_DDR_CS0_CONFIG	( CSCONFIG_EN \
+#define CONFIG_SYS_DDR_SIZE		512 /* MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000001f
+#define CONFIG_SYS_DDR_CS0_CONFIG	( CSCONFIG_EN \
 				| 0x00010000  /* ODT_WR to CSn */ \
 				| CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 )
 				/* 0x80010202 */
-#define CFG_DDR_TIMING_3	0x00000000
-#define CFG_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
 				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
 				| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
 				| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
@@ -157,7 +157,7 @@
 				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
 				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
 				/* 0x00620802 */
-#define CFG_DDR_TIMING_1	( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
+#define CONFIG_SYS_DDR_TIMING_1	( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
 				| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
 				| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
 				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
@@ -166,7 +166,7 @@
 				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
 				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
 				/* 0x3935d322 */
-#define CFG_DDR_TIMING_2	( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+#define CONFIG_SYS_DDR_TIMING_2	( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
 				| ( 6 << TIMING_CFG2_CPO_SHIFT ) \
 				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
 				| ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
@@ -174,69 +174,70 @@
 				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
 				| ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) )
 				/* 0x131088c8 */
-#define CFG_DDR_INTERVAL	( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+#define CONFIG_SYS_DDR_INTERVAL	( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \
 				| ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
 				/* 0x03E00100 */
-#define CFG_DDR_SDRAM_CFG	0x43000000
-#define CFG_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
-#define CFG_DDR_MODE		( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
+#define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE		( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
 				| ( 0x1432 << SDRAM_MODE_SD_SHIFT ) )
 				/* ODT 150ohm CL=3, AL=1 on SDRAM */
-#define CFG_DDR_MODE2		0x00000000
+#define CONFIG_SYS_DDR_MODE2		0x00000000
 #endif
 
 /*
  * Memory test
  */
-#undef CFG_DRAM_TEST		/* memory test, takes time */
-#define CFG_MEMTEST_START	0x00040000 /* memtest region */
-#define CFG_MEMTEST_END		0x00140000
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00140000
 
 /*
  * The reserved memory
  */
-#define CFG_MONITOR_BASE	TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE /* start of monitor */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef CFG_RAMBOOT
+#undef CONFIG_SYS_RAMBOOT
 #endif
 
-/* CFG_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(512 * 1024) /* Reserved for malloc */
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024) /* Reserved for malloc */
 
 /*
  * Initial RAM Base Address Setup
  */
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CFG_INIT_RAM_END	0x1000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE	0x100 /* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)
-#define CFG_LBC_LBCR		0x00000000
+#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)
+#define CONFIG_SYS_LBC_LBCR		0x00000000
 
 /*
  * FLASH on the Local Bus
  */
-#define CFG_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
-#define CFG_FLASH_BASE		0xFE000000 /* FLASH base address */
-#define CFG_FLASH_SIZE		32 /* max FLASH size is 32M */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		32 /* max FLASH size is 32M */
+#define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
 
-#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE /* Window base at flash base */
-#define CFG_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE /* Window base at flash base */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */
 
-#define CFG_BR0_PRELIM		( CFG_FLASH_BASE	/* Flash Base address */ \
+#define CONFIG_SYS_BR0_PRELIM		( CONFIG_SYS_FLASH_BASE	/* Flash Base address */ \
 				| (2 << BR_PS_SHIFT)	/* 16 bit port size */ \
 				| BR_V )		/* valid */
-#define CFG_OR0_PRELIM		( (~(CFG_FLASH_SIZE - 1) << 20) \
+#define CONFIG_SYS_OR0_PRELIM		( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
 				| OR_UPM_XAM \
 				| OR_GPCM_CSNT \
 				| OR_GPCM_ACS_DIV2 \
@@ -247,64 +248,70 @@
 				| OR_GPCM_EAD )
 				/* 0xFE000FF7 */
 
-#define CFG_MAX_FLASH_BANKS	1 /* number of banks */
-#define CFG_MAX_FLASH_SECT	256 /* max sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
 
-#undef CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
 
 /*
  * BCSR on the Local Bus
  */
-#define CFG_BCSR		0xF8000000
-#define CFG_LBLAWBAR1_PRELIM	CFG_BCSR /* Access window base at BCSR base */
-#define CFG_LBLAWAR1_PRELIM	0x8000000E /* Access window size 32K */
+#define CONFIG_SYS_BCSR		0xF8000000
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR /* Access window base at BCSR base */
+#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E /* Access window size 32K */
 
-#define CFG_BR1_PRELIM		(CFG_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */
-#define CFG_OR1_PRELIM		0xFFFFE9f7 /* length 32K */
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */
+#define CONFIG_SYS_OR1_PRELIM		0xFFFFE9f7 /* length 32K */
 
 /*
  * NAND Flash on the Local Bus
  */
-#define CFG_NAND_BASE		0xE0600000	/* 0xE0600000 */
-#define CFG_BR3_PRELIM		( CFG_NAND_BASE \
+#define CONFIG_CMD_NAND		1
+#define CONFIG_MTD_NAND_VERIFY_WRITE	1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_NAND_FSL_ELBC 	1
+
+#define CONFIG_SYS_NAND_BASE		0xE0600000	/* 0xE0600000 */
+#define CONFIG_SYS_BR3_PRELIM		( CONFIG_SYS_NAND_BASE \
 				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 				| BR_PS_8		/* Port Size = 8 bit */ \
 				| BR_MS_FCM		/* MSEL = FCM */ \
 				| BR_V )		/* valid */
-#define CFG_OR3_PRELIM		( 0xFFFF8000		/* length 32K */ \
-				| OR_FCM_CSCT \
+#define CONFIG_SYS_OR3_PRELIM		( 0xFFFF8000		/* length 32K */ \
+				| OR_FCM_BCTLD \
 				| OR_FCM_CST \
 				| OR_FCM_CHT \
 				| OR_FCM_SCY_1 \
+				| OR_FCM_RST \
 				| OR_FCM_TRLX \
 				| OR_FCM_EHTR )
-				/* 0xFFFF8396 */
+				/* 0xFFFF919E */
 
-#define CFG_LBLAWBAR3_PRELIM	CFG_NAND_BASE
-#define CFG_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
 
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
-#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
-#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* Pass open firmware flat tree */
@@ -312,50 +319,79 @@
 #define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
+#define CONFIG_SYS_64BIT_STRTOUL		1
+#define CONFIG_SYS_64BIT_VSPRINTF		1
+
 /* I2C */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #undef CONFIG_SOFT_I2C		/* I2C bit-banged */
 #define CONFIG_FSL_I2C
-#define CFG_I2C_SPEED		400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x51} /* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
-#define CFG_I2C2_OFFSET		0x3100
+#define CONFIG_SYS_I2C_SPEED		400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{0x51} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
 
 /*
  * Config on-board RTC
  */
 #define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
-#define CFG_I2C_RTC_ADDR	0x68 /* at address 0x68 */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
 
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI_MEM_BASE	0x80000000
-#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BASE
-#define CFG_PCI_MEM_SIZE	0x10000000 /* 256M */
-#define CFG_PCI_MMIO_BASE	0x90000000
-#define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
-#define CFG_PCI_MMIO_SIZE	0x10000000 /* 256M */
-#define CFG_PCI_IO_BASE		0x00000000
-#define CFG_PCI_IO_PHYS		0xE0300000
-#define CFG_PCI_IO_SIZE		0x100000 /* 1M */
-
-#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE
-#define CFG_PCI_SLV_MEM_BUS	0x00000000
-#define CFG_PCI_SLV_MEM_SIZE	0x80000000
+#define CONFIG_SYS_PCI_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
+#define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
+
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
+#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
+
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	0x08000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
+
+#define CONFIG_SYS_PCIE2_BASE		0xC0000000
+#define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE	0x08000000
+#define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
 
 #ifdef CONFIG_PCI
+#ifndef __ASSEMBLY__
+extern int board_pci_host_broken(void);
+#endif
 #define CONFIG_83XX_GENERIC_PCI	1 /* Use generic PCI setup */
+#define CONFIG_83XX_GENERIC_PCIE	1
 #define CONFIG_PQ_MDS_PIB	1 /* PQ MDS Platform IO Board */
 
+#define CONFIG_HAS_FSL_DR_USB	1 /* fixup device tree for the DR USB */
+
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
 #endif /* CONFIG_PCI */
 
 #ifndef CONFIG_NET_MULTI
@@ -366,10 +402,10 @@
  * TSEC
  */
 #define CONFIG_TSEC_ENET	/* TSEC ethernet support */
-#define CFG_TSEC1_OFFSET	0x24000
-#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
-#define CFG_TSEC2_OFFSET	0x25000
-#define CFG_TSEC2		(CFG_IMMR+CFG_TSEC2_OFFSET)
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1		(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2		(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 
 /*
  * TSEC ethernet configuration
@@ -381,6 +417,8 @@
 #define CONFIG_TSEC2_NAME	"eTSEC1"
 #define TSEC1_PHY_ADDR		2
 #define TSEC2_PHY_ADDR		3
+#define TSEC1_PHY_ADDR_SGMII	8
+#define TSEC2_PHY_ADDR_SGMII	4
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
@@ -400,15 +438,15 @@
 #define CONFIG_LIBATA
 #define CONFIG_FSL_SATA
 
-#define CFG_SATA_MAX_DEVICE	2
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
-#define CFG_SATA1_OFFSET	0x18000
-#define CFG_SATA1		(CFG_IMMR + CFG_SATA1_OFFSET)
-#define CFG_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SYS_SATA1_OFFSET	0x18000
+#define CONFIG_SYS_SATA1		(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
-#define CFG_SATA2_OFFSET	0x19000
-#define CFG_SATA2		(CFG_IMMR + CFG_SATA2_OFFSET)
-#define CFG_SATA2_FLAGS		FLAGS_DMA
+#define CONFIG_SYS_SATA2_OFFSET	0x19000
+#define CONFIG_SYS_SATA2		(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 
 #ifdef CONFIG_FSL_SATA
 #define CONFIG_LBA48
@@ -420,20 +458,20 @@
 /*
  * Environment
  */
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
 	#define CONFIG_ENV_SIZE		0x2000
 #else
-	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 	#define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -458,8 +496,8 @@
     #define CONFIG_CMD_PCI
 #endif
 
-#if defined(CFG_RAMBOOT)
-    #undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 
@@ -467,37 +505,49 @@
 
 #undef CONFIG_WATCHDOG		/* watchdog disabled */
 
+#define CONFIG_MMC     1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory */
-#define CFG_LOAD_ADDR		0x2000000 /* default load address */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-	#define CFG_CBSIZE	1024 /* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
 #else
-	#define CFG_CBSIZE	256 /* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*
  * Core HID Setup
  */
-#define CFG_HID0_INIT		0x000000000
-#define CFG_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
-#define CFG_HID2		HID2_HBE
+#define CONFIG_SYS_HID0_INIT		0x000000000
+#define CONFIG_SYS_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID2		HID2_HBE
 
 /*
  * MMU Setup
@@ -505,67 +555,67 @@
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR: cache cacheable */
-#define CFG_SDRAM_LOWER		CFG_SDRAM_BASE
-#define CFG_SDRAM_UPPER		(CFG_SDRAM_BASE + 0x10000000)
+#define CONFIG_SYS_SDRAM_LOWER		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_UPPER		(CONFIG_SYS_SDRAM_BASE + 0x10000000)
 
-#define CFG_IBAT0L	(CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 
-#define CFG_IBAT1L	(CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 
 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CFG_IBAT2L	(CFG_IMMR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT2U	(CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 
 /* BCSR: cache-inhibit and guarded */
-#define CFG_IBAT3L	(CFG_BCSR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_BCSR | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT3U	(CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CFG_IBAT4L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT4U	(CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_DBAT4L	(CFG_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT4U	CFG_IBAT4U
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 
 /* Stack in dcache: cacheable, no memory coherence */
-#define CFG_IBAT5L	(CFG_INIT_RAM_ADDR | BATL_PP_10)
-#define CFG_IBAT5U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_DBAT5L	CFG_IBAT5L
-#define CFG_DBAT5U	CFG_IBAT5U
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 
 #ifdef CONFIG_PCI
 /* PCI MEM space: cacheable */
-#define CFG_IBAT6L	(CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U	(CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 /* PCI MMIO space: cache-inhibit and guarded */
-#define CFG_IBAT7L	(CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT7U	(CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #else
-#define CFG_IBAT6L	(0)
-#define CFG_IBAT6U	(0)
-#define CFG_IBAT7L	(0)
-#define CFG_IBAT7U	(0)
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT6L	(0)
+#define CONFIG_SYS_IBAT6U	(0)
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #endif
 
 /*
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 2ac4ad0..2e31dd0 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -58,7 +58,7 @@
 /*
  * Hardware Reset Configuration Word
  */
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_SVCOD_DIV_2 |\
@@ -66,7 +66,7 @@
 	HRCWL_CORE_TO_CSB_2X1)
 
 #ifdef CONFIG_PCISLAVE
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_AGENT |\
 	HRCWH_PCI1_ARBITER_DISABLE |\
 	HRCWH_CORE_ENABLE |\
@@ -80,7 +80,7 @@
 	HRCWH_BIG_ENDIAN |\
 	HRCWH_LDP_CLEAR)
 #else
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_CORE_ENABLE |\
@@ -95,36 +95,36 @@
 	HRCWH_LDP_CLEAR)
 #endif
 
-/* System performance - define the value i.e. CFG_XXX
+/* System performance - define the value i.e. CONFIG_SYS_XXX
 */
 
 /* Arbiter Configuration Register */
-#define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
-#define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
+#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
 
 /* System Priority Control Regsiter */
-#define CFG_SPCR_TSECEP		3	/* eTSEC1&2 emergency priority (0-3) */
+#define CONFIG_SYS_SPCR_TSECEP		3	/* eTSEC1&2 emergency priority (0-3) */
 
 /* System Clock Configuration Register */
-#define CFG_SCCR_TSEC1CM	1		/* eTSEC1 clock mode (0-3) */
-#define CFG_SCCR_TSEC2CM	1		/* eTSEC2 clock mode (0-3) */
-#define CFG_SCCR_SATACM		SCCR_SATACM_2	/* SATA1-4 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_TSEC1CM	1		/* eTSEC1 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_TSEC2CM	1		/* eTSEC2 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_SATACM		SCCR_SATACM_2	/* SATA1-4 clock mode (0-3) */
 
 /*
  * System IO Config
  */
-#define CFG_SICRH		0x08200000
-#define CFG_SICRL		0x00000000
+#define CONFIG_SYS_SICRH		0x08200000
+#define CONFIG_SYS_SICRL		0x00000000
 
 /*
  * Output Buffer Impedance
  */
-#define CFG_OBIR		0x30100000
+#define CONFIG_SYS_OBIR		0x30100000
 
 /*
  * IMMR new address
  */
-#define CFG_IMMR		0xE0000000
+#define CONFIG_SYS_IMMR		0xE0000000
 
 /*
  * Device configurations
@@ -145,13 +145,13 @@
 /*
  * DDR Setup
  */
-#define CFG_DDR_BASE		0x00000000 /* DDR is system memory */
-#define CFG_SDRAM_BASE		CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
-#define CFG_DDR_SDRAM_CLK_CNTL	0x03000000
-#define CFG_83XX_DDR_USES_CS0
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x03000000
+#define CONFIG_SYS_83XX_DDR_USES_CS0
 
-#define CFG_DDRCDR_VALUE	(DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
 
 #undef CONFIG_DDR_ECC		/* support DDR ECC function */
 #undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
@@ -161,13 +161,13 @@
 /*
  * Manually set up DDR parameters
  */
-#define CFG_DDR_SIZE		256		/* MB */
-#define CFG_DDR_CS0_BNDS	0x0000000f
-#define CFG_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000f
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \
 				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 
-#define CFG_DDR_TIMING_3	0x00000000
-#define CFG_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
 				| (0 << TIMING_CFG0_WRT_SHIFT) \
 				| (0 << TIMING_CFG0_RRT_SHIFT) \
 				| (0 << TIMING_CFG0_WWT_SHIFT) \
@@ -177,7 +177,7 @@
 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 				/* 0x00220802 */
 				/* 0x00260802 */ /* DDR400 */
-#define CFG_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+#define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 				| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 				| (7 << TIMING_CFG1_CASLAT_SHIFT) \
@@ -187,124 +187,125 @@
 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
 				/* 0x3935d322 */
 				/* 0x3937d322 */
-#define CFG_DDR_TIMING_2	0x02984cc8
+#define CONFIG_SYS_DDR_TIMING_2	0x02984cc8
 
-#define CFG_DDR_INTERVAL	((1545 << SDRAM_INTERVAL_REFINT_SHIFT) \
+#define CONFIG_SYS_DDR_INTERVAL	((1545 << SDRAM_INTERVAL_REFINT_SHIFT) \
 				| (256 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 				/* 0x06090100 */
 
 #if defined(CONFIG_DDR_2T_TIMING)
-#define CFG_DDR_SDRAM_CFG		(SDRAM_CFG_SREN \
+#define CONFIG_SYS_DDR_SDRAM_CFG		(SDRAM_CFG_SREN \
 				| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
 				| SDRAM_CFG_2T_EN \
 				| SDRAM_CFG_DBW_32)
 #else
-#define CFG_DDR_SDRAM_CFG		(SDRAM_CFG_SREN \
+#define CONFIG_SYS_DDR_SDRAM_CFG		(SDRAM_CFG_SREN \
 				| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT)
 				/* 0x43000000 */
 #endif
-#define CFG_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
-#define CFG_DDR_MODE		((0x0440 << SDRAM_MODE_ESD_SHIFT) \
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE		((0x0440 << SDRAM_MODE_ESD_SHIFT) \
 				| (0x0442 << SDRAM_MODE_SD_SHIFT))
 				/* 0x04400442 */ /* DDR400 */
-#define CFG_DDR_MODE2		0x00000000;
+#define CONFIG_SYS_DDR_MODE2		0x00000000
 
 /*
  * Memory test
  */
-#undef CFG_DRAM_TEST		/* memory test, takes time */
-#define CFG_MEMTEST_START	0x00040000 /* memtest region */
-#define CFG_MEMTEST_END		0x0ef70010
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x0ef70010
 
 /*
  * The reserved memory
  */
-#define CFG_MONITOR_BASE	TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE /* start of monitor */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef	CFG_RAMBOOT
+#undef	CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(512 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024) /* Reserved for malloc */
 
 /*
  * Initial RAM Base Address Setup
  */
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CFG_INIT_RAM_END	0x1000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE	0x100 /* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)
-#define CFG_LBC_LBCR		0x00000000
+#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)
+#define CONFIG_SYS_LBC_LBCR		0x00000000
 
 /*
  * FLASH on the Local Bus
  */
-#define CFG_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
-#define CFG_FLASH_BASE		0xFE000000 /* FLASH base address */
-#define CFG_FLASH_SIZE		8 /* max FLASH size is 32M */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		8 /* max FLASH size is 32M */
 
-#define CFG_FLASH_EMPTY_INFO			/* display empty sectors */
-#define CFG_FLASH_USE_BUFFER_WRITE		/* buffer up multiple bytes */
+#define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
+#define CONFIG_SYS_FLASH_EMPTY_INFO			/* display empty sectors */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE		/* buffer up multiple bytes */
 
-#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE /* Window base at flash base */
-#define CFG_LBLAWAR0_PRELIM	0x80000016	/* 8 MB window size */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE /* Window base at flash base */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016	/* 8 MB window size */
 
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | /* Flash Base address */ \
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
 				(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 				BR_V) /* valid */
-#define CFG_OR0_PRELIM		(0xFF800000		/* 8 MByte */ \
+#define CONFIG_SYS_OR0_PRELIM		(0xFF800000		/* 8 MByte */ \
 				| OR_GPCM_XACS \
 				| OR_GPCM_SCY_9 \
 				| OR_GPCM_EHTR \
 				| OR_GPCM_EAD)
 				/* 0xFF806FF7	TODO SLOW 8 MB flash size */
 
-#define CFG_MAX_FLASH_BANKS	1 /* number of banks */
-#define CFG_MAX_FLASH_SECT	256 /* max sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
 
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
 /*
  * NAND Flash on the Local Bus
  */
-#define CFG_NAND_BASE		0xE0600000	/* 0xE0600000 */
-#define CFG_BR1_PRELIM		(CFG_NAND_BASE | \
+#define CONFIG_SYS_NAND_BASE		0xE0600000	/* 0xE0600000 */
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_NAND_BASE | \
 				 (2 << BR_DECC_SHIFT) |	/* Use HW ECC */ \
 				 BR_PS_8 |		/* Port Size = 8 bit */ \
 				 BR_MS_FCM |		/* MSEL = FCM */ \
 				 BR_V)			/* valid */
-#define CFG_OR1_PRELIM		(0xFFFF8000 |		/* length 32K */ \
+#define CONFIG_SYS_OR1_PRELIM		(0xFFFF8000 |		/* length 32K */ \
 				 OR_FCM_CSCT | \
 				 OR_FCM_CST | \
 				 OR_FCM_CHT | \
 				 OR_FCM_SCY_1 | \
 				 OR_FCM_TRLX | \
 				 OR_FCM_EHTR)
-#define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
-#define CFG_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
 
 /* Vitesse 7385 */
 
-#define CFG_VSC7385_BASE	0xF0000000
+#define CONFIG_SYS_VSC7385_BASE	0xF0000000
 
 #ifdef CONFIG_VSC7385_ENET
 
-#define CFG_BR2_PRELIM		0xf0000801		/* Base address */
-#define CFG_OR2_PRELIM		0xfffe09ff		/* 128K bytes*/
-#define CFG_LBLAWBAR2_PRELIM	CFG_VSC7385_BASE	/* Access Base */
-#define CFG_LBLAWAR2_PRELIM	0x80000010		/* Access Size 128K */
+#define CONFIG_SYS_BR2_PRELIM		0xf0000801		/* Base address */
+#define CONFIG_SYS_OR2_PRELIM		0xfffe09ff		/* 128K bytes*/
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE	/* Access Base */
+#define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000010		/* Access Size 128K */
 
 #endif
 
@@ -313,16 +314,16 @@
  */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE \
+#define CONFIG_SYS_BAUDRATE_TABLE \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 
-#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
-#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 
 /* SERDES */
 #define CONFIG_FSL_SERDES
@@ -330,9 +331,9 @@
 #define CONFIG_FSL_SERDES2	0xe3100
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* Pass open firmware flat tree */
@@ -344,42 +345,42 @@
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
 #define CONFIG_FSL_I2C
-#define CFG_I2C_SPEED		400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x51} /* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
-#define CFG_I2C2_OFFSET		0x3100
+#define CONFIG_SYS_I2C_SPEED		400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{0x51} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
 
 /*
  * Config on-board RTC
  */
 #define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
-#define CFG_I2C_RTC_ADDR	0x68 /* at address 0x68 */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
 
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI_MEM_BASE	0x80000000
-#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BASE
-#define CFG_PCI_MEM_SIZE	0x10000000 /* 256M */
-#define CFG_PCI_MMIO_BASE	0x90000000
-#define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
-#define CFG_PCI_MMIO_SIZE	0x10000000 /* 256M */
-#define CFG_PCI_IO_BASE		0x00000000
-#define CFG_PCI_IO_PHYS		0xE0300000
-#define CFG_PCI_IO_SIZE		0x100000 /* 1M */
-
-#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE
-#define CFG_PCI_SLV_MEM_BUS	0x00000000
-#define CFG_PCI_SLV_MEM_SIZE	0x80000000
+#define CONFIG_SYS_PCI_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
+#define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
+
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
+#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
 
 #ifdef CONFIG_PCI
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
 
 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
 #endif	/* CONFIG_PCI */
 
 /*
@@ -395,7 +396,7 @@
 #ifdef CONFIG_TSEC1
 #define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME		"TSEC0"
-#define CFG_TSEC1_OFFSET		0x24000
+#define CONFIG_SYS_TSEC1_OFFSET		0x24000
 #define TSEC1_PHY_ADDR			2
 #define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC1_PHYIDX			0
@@ -404,7 +405,7 @@
 #ifdef CONFIG_TSEC2
 #define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME		"TSEC1"
-#define CFG_TSEC2_OFFSET		0x25000
+#define CONFIG_SYS_TSEC2_OFFSET		0x25000
 #define TSEC2_PHY_ADDR			0x1c
 #define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC2_PHYIDX			0
@@ -421,15 +422,15 @@
 #define CONFIG_LIBATA
 #define CONFIG_FSL_SATA
 
-#define CFG_SATA_MAX_DEVICE	2
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
-#define CFG_SATA1_OFFSET	0x18000
-#define CFG_SATA1		(CFG_IMMR + CFG_SATA1_OFFSET)
-#define CFG_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SYS_SATA1_OFFSET	0x18000
+#define CONFIG_SYS_SATA1		(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
-#define CFG_SATA2_OFFSET	0x19000
-#define CFG_SATA2		(CFG_IMMR + CFG_SATA2_OFFSET)
-#define CFG_SATA2_FLAGS		FLAGS_DMA
+#define CONFIG_SYS_SATA2_OFFSET	0x19000
+#define CONFIG_SYS_SATA2		(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 
 #ifdef CONFIG_FSL_SATA
 #define CONFIG_LBA48
@@ -441,20 +442,20 @@
 /*
  * Environment
  */
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE+CFG_MONITOR_LEN)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
 	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K (one sector) for env */
 	#define CONFIG_ENV_SIZE		0x4000
 #else
-	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE-0x1000)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-0x1000)
 	#define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -479,8 +480,8 @@
 #define CONFIG_CMD_PCI
 #endif
 
-#if defined(CFG_RAMBOOT)
-#undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT)
+#undef CONFIG_CMD_SAVEENV
 #undef CONFIG_CMD_LOADS
 #endif
 
@@ -491,34 +492,34 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory */
-#define CFG_LOAD_ADDR		0x2000000 /* default load address */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-	#define CFG_CBSIZE	1024 /* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
 #else
-	#define CFG_CBSIZE	256 /* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*
  * Core HID Setup
  */
-#define CFG_HID0_INIT		0x000000000
-#define CFG_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
-#define CFG_HID2		HID2_HBE
+#define CONFIG_SYS_HID0_INIT		0x000000000
+#define CONFIG_SYS_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID2		HID2_HBE
 
 /*
  * MMU Setup
@@ -527,67 +528,67 @@
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR: cache cacheable */
-#define CFG_SDRAM_LOWER		CFG_SDRAM_BASE
-#define CFG_SDRAM_UPPER		(CFG_SDRAM_BASE + 0x10000000)
+#define CONFIG_SYS_SDRAM_LOWER		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_UPPER		(CONFIG_SYS_SDRAM_BASE + 0x10000000)
 
-#define CFG_IBAT0L	(CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 
-#define CFG_IBAT1L	(CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 
 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CFG_IBAT2L	(CFG_IMMR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT2U	(CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 
 /* L2 Switch: cache-inhibit and guarded */
-#define CFG_IBAT3L	(CFG_VSC7385_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_VSC7385_BASE | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT3U	(CFG_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CFG_IBAT4L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT4U	(CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_DBAT4L	(CFG_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT4U	CFG_IBAT4U
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 
 /* Stack in dcache: cacheable, no memory coherence */
-#define CFG_IBAT5L	(CFG_INIT_RAM_ADDR | BATL_PP_10)
-#define CFG_IBAT5U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_DBAT5L	CFG_IBAT5L
-#define CFG_DBAT5U	CFG_IBAT5U
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 
 #ifdef CONFIG_PCI
 /* PCI MEM space: cacheable */
-#define CFG_IBAT6L	(CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U	(CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 /* PCI MMIO space: cache-inhibit and guarded */
-#define CFG_IBAT7L	(CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT7U	(CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #else
-#define CFG_IBAT6L	(0)
-#define CFG_IBAT6U	(0)
-#define CFG_IBAT7L	(0)
-#define CFG_IBAT7U	(0)
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT6L	(0)
+#define CONFIG_SYS_IBAT6U	(0)
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #endif
 
 /*
@@ -632,7 +633,7 @@
 #define CONFIG_FDTFILE		mpc8379_rdb.dtb
 
 #define CONFIG_LOADADDR		500000	/* default location for tftp and bootm */
-#define CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
+#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 
 #define XMK_STR(x)	#x
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 2578bef..bbb448d 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -34,6 +34,7 @@
 #define CONFIG_MPC8536		1
 #define CONFIG_MPC8536DS	1
 
+#define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCI1		1	/* Enable PCI controller 1 */
 #define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
@@ -41,6 +42,7 @@
 #define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
@@ -59,7 +61,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #endif
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
-/* #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /\* ddrclk for MPC85xx *\/ FIXME-8536*/
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0)
 #define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
 #define CONFIG_GET_CLK_FROM_ICS307	  /* decode sysclk and ddrclk freq
 					     from ICS307 instead of switches */
@@ -69,27 +71,28 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
 
 #define CONFIG_ENABLE_36BIT_PHYS	1
 
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on */
-#define CFG_MEMTEST_END		0x7fffffff
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x7fffffff
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
-#define CFG_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
-#define CFG_PCI1_ADDR		(CFG_CCSRBAR+0x8000)
-#define CFG_PCIE1_ADDR		(CFG_CCSRBAR+0xa000)
-#define CFG_PCIE2_ADDR		(CFG_CCSRBAR+0x9000)
-#define CFG_PCIE3_ADDR		(CFG_CCSRBAR+0xb000)
+#define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)
+#define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR+0xa000)
+#define CONFIG_SYS_PCIE2_ADDR		(CONFIG_SYS_CCSRBAR+0x9000)
+#define CONFIG_SYS_PCIE3_ADDR		(CONFIG_SYS_CCSRBAR+0xb000)
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR2
@@ -98,11 +101,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_DDR_SPD
 #undef CONFIG_DDR_DLL
 
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
@@ -110,37 +113,29 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 
 /* I2C addresses of SPD EEPROMs */
 #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
-#define CFG_SPD_BUS_NUM		1
+#define CONFIG_SYS_SPD_BUS_NUM		1
 
 /* These are used when DDR doesn't use SPD. */
-#define CFG_SDRAM_SIZE		256		/* DDR is 256MB */
-#define CFG_DDR_CS0_BNDS	0x0000001F
-#define CFG_DDR_CS0_CONFIG	0x80010102	/* Enable, no interleaving */
-#define CFG_DDR_TIMING_3	0x00000000
-#define CFG_DDR_TIMING_0	0x00260802
-#define CFG_DDR_TIMING_1	0x3935d322
-#define CFG_DDR_TIMING_2	0x14904cc8
-#define CFG_DDR_MODE_1		0x00480432
-#define CFG_DDR_MODE_2		0x00000000
-#define CFG_DDR_INTERVAL	0x06180100
-#define CFG_DDR_DATA_INIT	0xdeadbeef
-#define CFG_DDR_CLK_CTRL	0x03800000
-#define CFG_DDR_OCD_CTRL	0x00000000
-#define CFG_DDR_OCD_STATUS	0x00000000
-#define CFG_DDR_CONTROL		0xC3008000	/* Type = DDR2 */
-#define CFG_DDR_CONTROL2	0x04400010
-
-#define CFG_DDR_ERR_INT_EN	0x0000000d
-#define CFG_DDR_ERR_DIS		0x00000000
-#define CFG_DDR_SBE		0x00010000
-
-/* FIXME: Not used in fixed_sdram function */
-#define CFG_DDR_MODE		0x00000022
-#define CFG_DDR_CS1_BNDS	0x00000000
-#define CFG_DDR_CS2_BNDS	0x00000FFF	/* Not done */
-#define CFG_DDR_CS3_BNDS	0x00000FFF	/* Not done */
-#define CFG_DDR_CS4_BNDS	0x00000FFF	/* Not done */
-#define CFG_DDR_CS5_BNDS	0x00000FFF	/* Not done */
+#define CONFIG_SYS_SDRAM_SIZE		256		/* DDR is 256MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000001F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102	/* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	0x00260802
+#define CONFIG_SYS_DDR_TIMING_1	0x3935d322
+#define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
+#define CONFIG_SYS_DDR_MODE_1		0x00480432
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_INTERVAL	0x06180100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
+#define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xC3008000	/* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2	0x04400010
+
+#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
+#define CONFIG_SYS_DDR_SBE		0x00010000
 
 /* Make sure required options are set */
 #ifndef CONFIG_SPD_EEPROM
@@ -162,8 +157,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
  *
  * Localbus non-cacheable
- * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
+ * 0xe000_0000	0xe7ff_ffff	Promjet/free		128M non-cacheable
  * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
+ * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
  * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
@@ -172,38 +168,40 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 /*
  * Local Bus Definitions
  */
-#define CFG_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
+#define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 
-#define CFG_BR0_PRELIM		0xe8001001
-#define CFG_OR0_PRELIM		0xf8000ff7
+#define CONFIG_SYS_BR0_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR0_PRELIM	0xf8000ff7
 
-#define CFG_BR1_PRELIM		0xe0001001
-#define CFG_OR1_PRELIM		0xf8000ff7
+#define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
 
-#define CFG_FLASH_BANKS_LIST	{CFG_FLASH_BASE + 0x8000000, CFG_FLASH_BASE}
-#define CFG_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 
-#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
-#define CFG_MAX_FLASH_SECT	1024		/* sectors per device */
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_AMD_CHECK_DQ7
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
 
 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
 #define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
+#define PIXIS_BASE_PHYS	PIXIS_BASE
 
-#define CFG_BR3_PRELIM	(PIXIS_BASE | 0x0801)	/* port size 8bit */
-#define CFG_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
 
 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
 #define PIXIS_VER		0x1	/* Board version at offset 1 */
@@ -235,20 +233,68 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 /* old pixis referenced names */
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
-#define CFG_PIXIS_VBOOT_MASK	0xc0
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
-#define CFG_INIT_RAM_END	0x00004000	/* End of used area in RAM */
-
-#define CFG_GBL_DATA_SIZE	128	/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	0xc0
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+#define CONFIG_SYS_NAND_BASE           0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS      CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
+				CONFIG_SYS_NAND_BASE + 0x40000, \
+				CONFIG_SYS_NAND_BASE + 0x80000, \
+				CONFIG_SYS_NAND_BASE + 0xC0000}
+#define CONFIG_SYS_MAX_NAND_DEVICE	4
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND		1
+#define CONFIG_NAND_FSL_ELBC	1
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8              /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CONFIG_NAND_OR_PRELIM	(0xFFFC0000            /* length 256K */ \
+				| OR_FCM_PGS            /* Large Page*/ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
+
+#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8              /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CONFIG_SYS_OR4_PRELIM	CONFIG_NAND_OR_PRELIM     /* NAND Options */
+#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8              /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CONFIG_SYS_OR5_PRELIM	CONFIG_NAND_OR_PRELIM     /* NAND Options */
+
+#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8              /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CONFIG_SYS_OR6_PRELIM	CONFIG_NAND_OR_PRELIM     /* NAND Options */
 
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
@@ -256,21 +302,21 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /*
@@ -280,8 +326,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
-#define CFG_64BIT_STRTOUL		1
-#define CFG_64BIT_VSPRINTF		1
+#define CONFIG_SYS_64BIT_STRTOUL		1
+#define CONFIG_SYS_64BIT_VSPRINTF		1
 
 
 /*
@@ -292,64 +338,66 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{{0, 0x29}}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
-#define CFG_I2C2_OFFSET		0x3100
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{{0, 0x29}}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
 
 /*
  * I2C2 EEPROM
  */
 #define CONFIG_ID_EEPROM
 #ifdef CONFIG_ID_EEPROM
-#define CONFIG_ID_EEPROM
-#define CFG_I2C_EEPROM_NXID
+#define CONFIG_SYS_I2C_EEPROM_NXID
 #endif
-#define CFG_I2C_EEPROM_ADDR	0x57
-#define CFG_I2C_EEPROM_ADDR_LEN	1
-#define CFG_EEPROM_BUS_NUM	1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_BUS_NUM	1
 
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 
-/* PCI view of System Memory */
-#define CFG_PCI_MEMORY_BUS	0x00000000
-#define CFG_PCI_MEMORY_PHYS	0x00000000
-#define CFG_PCI_MEMORY_SIZE	0x80000000
-
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xffc00000
-#define CFG_PCI1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xffc00000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CFG_PCIE1_MEM_BASE	0x90000000
-#define CFG_PCIE1_MEM_PHYS	CFG_PCIE1_MEM_BASE
-#define CFG_PCIE1_MEM_SIZE	0x08000000	/* 128M */
-#define CFG_PCIE1_IO_BASE	0x00000000
-#define CFG_PCIE1_IO_PHYS	0xffc10000
-#define CFG_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x90000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x90000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x90000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x08000000	/* 128M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc10000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CFG_PCIE2_MEM_BASE	0x98000000
-#define CFG_PCIE2_MEM_PHYS	CFG_PCIE2_MEM_BASE
-#define CFG_PCIE2_MEM_SIZE	0x08000000	/* 128M */
-#define CFG_PCIE2_IO_BASE	0x00000000
-#define CFG_PCIE2_IO_PHYS	0xffc20000
-#define CFG_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0x98000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0x98000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0x98000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x08000000	/* 128M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc20000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
-#define CFG_PCIE3_MEM_BASE	0xa0000000
-#define CFG_PCIE3_MEM_PHYS	CFG_PCIE3_MEM_BASE
-#define CFG_PCIE3_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCIE3_IO_BASE	0x00000000
-#define CFG_PCIE3_IO_PHYS	0xffc30000
-#define CFG_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc30000
+#define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc30000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 
 #if defined(CONFIG_PCI)
 
@@ -357,10 +405,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
 /*PCIE video card used*/
-#define VIDEO_IO_OFFSET		CFG_PCIE3_IO_PHYS
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE3_IO_VIRT
 
 /*PCI video card used*/
-/*#define VIDEO_IO_OFFSET	CFG_PCI1_IO_PHYS*/
+/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_VIRT*/
 
 /* video */
 #define CONFIG_VIDEO
@@ -373,7 +421,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_ATI_RADEON_FB
 #define CONFIG_VIDEO_LOGO
 /*#define CONFIG_CONSOLE_CURSOR*/
-#define CFG_ISA_IO_BASE_ADDRESS CFG_PCIE3_IO_PHYS
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
 #endif
 
 #undef CONFIG_EEPRO100
@@ -387,8 +435,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #endif
 
 #ifndef CONFIG_PCI_PNP
-	#define PCI_ENET0_IOADDR	CFG_PCI1_IO_BASE
-	#define PCI_ENET0_MEMADDR	CFG_PCI1_IO_BASE
+	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BUS
+	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_IO_BUS
 	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
 #endif
 
@@ -400,13 +448,13 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_LIBATA
 #define CONFIG_FSL_SATA
 
-#define CFG_SATA_MAX_DEVICE	2
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
-#define CFG_SATA1		CFG_MPC85xx_SATA1_ADDR
-#define CFG_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
-#define CFG_SATA2		CFG_MPC85xx_SATA2_ADDR
-#define CFG_SATA2_FLAGS		FLAGS_DMA
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
 
 #ifdef CONFIG_FSL_SATA
 #define CONFIG_LBA48
@@ -428,6 +476,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_TSEC3	1
 #define CONFIG_TSEC3_NAME	"eTSEC3"
 
+#define CONFIG_FSL_SGMII_RISER	1
+#define SGMII_RISER_PHY_OFFSET	0x1c
+
 #define TSEC1_PHY_ADDR		1	/* TSEC1 -> PHY1 */
 #define TSEC3_PHY_ADDR		0	/* TSEC3 -> PHY0 */
 
@@ -447,16 +498,16 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#if CFG_MONITOR_BASE > 0xfff80000
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 #define CONFIG_ENV_ADDR		0xfff80000
 #else
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x60000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #endif
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
  * Command line configuration.
@@ -468,6 +519,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
@@ -477,29 +530,41 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 
+#define CONFIG_MMC     1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 0f5f834..4aaad55 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -46,6 +46,7 @@
 #endif
 
 #define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
@@ -78,20 +79,19 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 
-#define CFG_MEMTEST_START	0x00200000	/* memtest region */
-#define CFG_MEMTEST_END		0x00400000
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
 
 
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
-#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR1
@@ -101,8 +101,8 @@
 
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
@@ -112,42 +112,42 @@
 #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
 
 /* These are used when DDR doesn't use SPD. */
-#define CFG_SDRAM_SIZE	128		/* DDR is 128MB */
-#define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
-#define CFG_DDR_CS0_CONFIG	0x80000002
-#define CFG_DDR_TIMING_1	0x37344321
-#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
-#define CFG_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
-#define CFG_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
-#define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
+#define CONFIG_SYS_SDRAM_SIZE	128		/* DDR is 128MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000002
+#define CONFIG_SYS_DDR_TIMING_1	0x37344321
+#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
+#define CONFIG_SYS_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
 
 /*
  * SDRAM on the Local Bus
  */
-#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
-#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
 
-#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 16M */
-#define CFG_BR0_PRELIM		0xff001801	/* port size 32bit */
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
+#define CONFIG_SYS_BR0_PRELIM		0xff001801	/* port size 32bit */
 
-#define CFG_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
-#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_MAX_FLASH_SECT	64		/* sectors per device */
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef  CFG_RAMBOOT
+#undef  CONFIG_SYS_RAMBOOT
 #endif
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
@@ -158,7 +158,7 @@
 
 /*
  * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  *
  * For BR2, need:
  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
@@ -170,14 +170,14 @@
  * 0    4    8    12   16   20   24   28
  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  *
- * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  * FIXME: the top 17 bits of BR2.
  */
 
-#define CFG_BR2_PRELIM		0xf0001861
+#define CONFIG_SYS_BR2_PRELIM		0xf0001861
 
 /*
- * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  *
  * For OR2, need:
  *    64MB mask for AM, OR2[0:7] = 1111 1100
@@ -190,103 +190,102 @@
  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  */
 
-#define CFG_OR2_PRELIM		0xfc006901
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
 
-#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
-#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
-#define CFG_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
-#define CFG_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
+#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
 
 /*
  * LSDMR masks
  */
-#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CFG_LBC_LSDMR_RFCR5	(3 << (31 - 16))
-#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CFG_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
-#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CFG_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CFG_LBC_LSDMR_WRC2	(2 << (31 - 27))
-#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CFG_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
-#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
-#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_BSMA1516	\
-				| CFG_LBC_LSDMR_RFCR5		\
-				| CFG_LBC_LSDMR_PRETOACT3	\
-				| CFG_LBC_LSDMR_ACTTORW3	\
-				| CFG_LBC_LSDMR_BL8		\
-				| CFG_LBC_LSDMR_WRC2		\
-				| CFG_LBC_LSDMR_CL3		\
-				| CFG_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_RFCR5	(3 << (31 - 16))
+#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CONFIG_SYS_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
+#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CONFIG_SYS_LBC_LSDMR_WRC2	(2 << (31 - 27))
+#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CONFIG_SYS_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
+#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_BSMA1516	\
+				| CONFIG_SYS_LBC_LSDMR_RFCR5		\
+				| CONFIG_SYS_LBC_LSDMR_PRETOACT3	\
+				| CONFIG_SYS_LBC_LSDMR_ACTTORW3	\
+				| CONFIG_SYS_LBC_LSDMR_BL8		\
+				| CONFIG_SYS_LBC_LSDMR_WRC2		\
+				| CONFIG_SYS_LBC_LSDMR_CL3		\
+				| CONFIG_SYS_LBC_LSDMR_RFEN		\
 				)
 
 /*
  * SDRAM Controller configuration sequence.
  */
-#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_PCHALL)
-#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_MRW)
-#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_NORMAL)
+#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
 
 
 /*
  * 32KB, 8-bit wide for ADS config reg
  */
-#define CFG_BR4_PRELIM          0xf8000801
-#define CFG_OR4_PRELIM		0xffffe1f1
-#define CFG_BCSR		(CFG_BR4_PRELIM & 0xffff8000)
+#define CONFIG_SYS_BR4_PRELIM          0xf8000801
+#define CONFIG_SYS_OR4_PRELIM		0xffffe1f1
+#define CONFIG_SYS_BCSR		(CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* pass open firmware flat tree */
@@ -294,8 +293,8 @@
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
-#define CFG_64BIT_VSPRINTF	1
-#define CFG_64BIT_STRTOUL	1
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
 
 /*
  * I2C
@@ -303,26 +302,29 @@
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
 
 /* RapidIO MMU */
-#define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
-#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
-#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M */
+#define CONFIG_SYS_RIO_MEM_VIRT	0xc0000000	/* base address */
+#define CONFIG_SYS_RIO_MEM_BUS	0xc0000000	/* base address */
+#define CONFIG_SYS_RIO_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
 
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xe2000000
-#define CFG_PCI1_IO_SIZE	0x100000	/* 1M */
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x100000	/* 1M */
 
 #if defined(CONFIG_PCI)
 
@@ -339,7 +341,7 @@
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
 #endif	/* CONFIG_PCI */
 
@@ -380,20 +382,20 @@
 /*
  * Environment
  */
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
   #define CONFIG_ENV_IS_IN_FLASH	1
-  #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
   #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
   #define CONFIG_ENV_SIZE		0x2000
 #else
-  #define CFG_NO_FLASH		1	/* Flash is not usable now */
+  #define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
   #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-  #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
   #define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 
 /*
@@ -413,13 +415,15 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
 #endif
 
-#if defined(CFG_RAMBOOT)
-    #undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 
@@ -429,28 +433,28 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index ee4f41f..95ea275 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -62,13 +62,12 @@
 /* below can be toggled for performance analysis. otherwise use default */
 #define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
 #undef  CONFIG_BTB			    /* toggle branch predition */
-#undef  CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
 
 #define CONFIG_BOARD_PRE_INIT	1	    /* Call board_pre_init	*/
 
-#undef	CFG_DRAM_TEST			    /* memory test, takes time  */
-#define CFG_MEMTEST_START	0x00200000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00400000
+#undef	CONFIG_SYS_DRAM_TEST			    /* memory test, takes time  */
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00400000
 
 #if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
 #error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
@@ -78,42 +77,42 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
-#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR	*/
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
+#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR	*/
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR	*/
 
-#define CFG_SDRAM_SIZE		256             /* DDR is now 256MB     */
+#define CONFIG_SYS_SDRAM_SIZE		256             /* DDR is now 256MB     */
 
 #if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
 #else
-#define CFG_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
 #endif
-#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 0MB	*/
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 0MB	*/
 
 #if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_FLASH_BASE          0xf8000000      /* start of FLASH  16M  */
-#define CFG_BR0_PRELIM          0xf8001801      /* port size 32bit */
+#define CONFIG_SYS_FLASH_BASE          0xf8000000      /* start of FLASH  16M  */
+#define CONFIG_SYS_BR0_PRELIM          0xf8001801      /* port size 32bit */
 #else /* Boot from real Flash */
-#define CFG_FLASH_BASE		0xff800000	/* start of FLASH 8M    */
-#define CFG_BR0_PRELIM		0xff801001	/* port size 16bit	*/
+#define CONFIG_SYS_FLASH_BASE		0xff800000	/* start of FLASH 8M    */
+#define CONFIG_SYS_BR0_PRELIM		0xff801001	/* port size 16bit	*/
 #endif
 
-#define	CFG_OR0_PRELIM		0xff806f67	/* 8MB Flash		*/
-#define CFG_MAX_FLASH_BANKS	1		/* number of banks	*/
-#define CFG_MAX_FLASH_SECT	64		/* sectors per device   */
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Timeout for Flash Erase (in ms)*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)*/
-#define CFG_FLASH_CFI		1
+#define	CONFIG_SYS_OR0_PRELIM		0xff806f67	/* 8MB Flash		*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device   */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Timeout for Flash Erase (in ms)*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)*/
+#define CONFIG_SYS_FLASH_CFI		1
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef  CFG_RAMBOOT
+#undef  CONFIG_SYS_RAMBOOT
 #endif
 
 /* DDR Setup */
@@ -127,8 +126,8 @@
 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_VERY_BIG_RAM
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
@@ -141,57 +140,56 @@
 #undef CONFIG_CLOCKS_IN_MHZ
 
 /* local bus definitions */
-#define CFG_BR2_PRELIM		0xf0001861	/* 64MB localbus SDRAM  */
-#define CFG_OR2_PRELIM		0xfc006901
-#define CFG_LBC_LCRR		0x00030004	/* local bus freq divider*/
-#define CFG_LBC_LBCR		0x00000000
-#define CFG_LBC_LSRT		0x20000000
-#define CFG_LBC_MRTPR		0x20000000
-#define CFG_LBC_LSDMR_1		0x2861b723
-#define CFG_LBC_LSDMR_2		0x0861b723
-#define CFG_LBC_LSDMR_3		0x0861b723
-#define CFG_LBC_LSDMR_4		0x1861b723
-#define CFG_LBC_LSDMR_5		0x4061b723
+#define CONFIG_SYS_BR2_PRELIM		0xf0001861	/* 64MB localbus SDRAM  */
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
+#define CONFIG_SYS_LBC_LCRR		0x00030004	/* local bus freq divider*/
+#define CONFIG_SYS_LBC_LBCR		0x00000000
+#define CONFIG_SYS_LBC_LSRT		0x20000000
+#define CONFIG_SYS_LBC_MRTPR		0x20000000
+#define CONFIG_SYS_LBC_LSDMR_1		0x2861b723
+#define CONFIG_SYS_LBC_LSDMR_2		0x0861b723
+#define CONFIG_SYS_LBC_LSDMR_3		0x0861b723
+#define CONFIG_SYS_LBC_LSDMR_4		0x1861b723
+#define CONFIG_SYS_LBC_LSDMR_5		0x4061b723
 
 #if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
+#define CONFIG_SYS_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
 #else
-#define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
+#define CONFIG_SYS_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
 #endif
-#define CFG_OR4_PRELIM          0xffffe1f1
-#define CFG_BCSR                (CFG_BR4_PRELIM & 0xffff8000)
+#define CONFIG_SYS_OR4_PRELIM          0xffffe1f1
+#define CONFIG_SYS_BCSR                (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0x40000000	/* Initial RAM address	*/
-#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000	/* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #define CONFIG_BAUDRATE		115200
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /*
@@ -200,16 +198,16 @@
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
 
 /* General PCI */
-#define CFG_PCI_MEM_BASE	0x80000000
-#define CFG_PCI_MEM_PHYS	0x80000000
-#define CFG_PCI_MEM_SIZE	0x20000000
-#define CFG_PCI_IO_BASE         0xe2000000
+#define CONFIG_SYS_PCI_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI_MEM_SIZE	0x20000000
+#define CONFIG_SYS_PCI_IO_BASE         0xe2000000
 
 #if defined(CONFIG_PCI)
 #define CONFIG_NET_MULTI
@@ -222,8 +220,8 @@
 #define PCI_IDSEL_NUMBER      0x0c	/*slot0->3(IDSEL)=12->15*/
 #endif
 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0008
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0008
 #elif defined(CONFIG_TSEC_ENET)
 #define CONFIG_NET_MULTI	1
 #define CONFIG_MII		1	/* MII PHY management	*/
@@ -254,21 +252,21 @@
 #endif
 
 /* Environment */
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 #if defined(CONFIG_RAM_AS_FLASH)
 #define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x100000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x100000)
 #define CONFIG_ENV_SIZE		0x2000
 #else
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
 #endif
 #define CONFIG_ENV_SIZE		0x2000
 #else
-/* #define CFG_NO_FLASH		1 */	/* Flash is not usable now	*/
+/* #define CONFIG_SYS_NO_FLASH		1 */	/* Flash is not usable now	*/
 #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #define CONFIG_ENV_SIZE		0x2000
 #endif
 
@@ -277,7 +275,7 @@
 #define CONFIG_BOOTDELAY	3	/* -1 disable autoboot */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 
 /*
@@ -301,8 +299,8 @@
     #define CONFIG_CMD_PCI
 #endif
 
-#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
-    #undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 
@@ -312,25 +310,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_LOAD_ADDR   0x2000000       /* default load address */
-#define CFG_PROMPT	"MPC8540EVAL=> "/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
+#define CONFIG_SYS_PROMPT	"MPC8540EVAL=> "/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 6a400f5..fa82fbc 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -38,6 +38,7 @@
 #define CONFIG_MPC8541CDS	1	/* MPC8541CDS board specific */
 
 #define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 
@@ -62,19 +63,18 @@ extern unsigned long get_clock_freq(void);
  */
 #define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
 #define CONFIG_BTB			    /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
 
-#define CFG_MEMTEST_START	0x00200000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00400000
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
 
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
-#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR1
@@ -84,8 +84,8 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
@@ -137,37 +137,37 @@ extern unsigned long get_clock_freq(void);
  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
  */
 
-#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 8M */
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 8M */
 
-#define CFG_BR0_PRELIM		0xff801001
-#define CFG_BR1_PRELIM		0xff001001
+#define CONFIG_SYS_BR0_PRELIM		0xff801001
+#define CONFIG_SYS_BR1_PRELIM		0xff001001
 
-#define	CFG_OR0_PRELIM		0xff806e65
-#define	CFG_OR1_PRELIM		0xff806e65
+#define	CONFIG_SYS_OR0_PRELIM		0xff806e65
+#define	CONFIG_SYS_OR1_PRELIM		0xff806e65
 
-#define CFG_FLASH_BANKS_LIST	{0xff800000, CFG_FLASH_BASE}
-#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
-#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{0xff800000, CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 
 /*
  * SDRAM on the Local Bus
  */
-#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
-#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
 
 /*
  * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  *
  * For BR2, need:
  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
@@ -179,14 +179,14 @@ extern unsigned long get_clock_freq(void);
  * 0    4    8    12   16   20   24   28
  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  *
- * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  * FIXME: the top 17 bits of BR2.
  */
 
-#define CFG_BR2_PRELIM          0xf0001861
+#define CONFIG_SYS_BR2_PRELIM          0xf0001861
 
 /*
- * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  *
  * For OR2, need:
  *    64MB mask for AM, OR2[0:7] = 1111 1100
@@ -199,35 +199,35 @@ extern unsigned long get_clock_freq(void);
  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  */
 
-#define CFG_OR2_PRELIM		0xfc006901
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
 
-#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
-#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
-#define CFG_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
-#define CFG_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
+#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
 
 /*
  * LSDMR masks
  */
-#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
 
 /*
  * Common settings for all Local Bus SDRAM commands.
@@ -235,13 +235,13 @@ extern unsigned long get_clock_freq(void);
  *                  or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
-#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_RFCR16		\
-				| CFG_LBC_LSDMR_PRETOACT7	\
-				| CFG_LBC_LSDMR_ACTTORW7	\
-				| CFG_LBC_LSDMR_BL8		\
-				| CFG_LBC_LSDMR_WRC4		\
-				| CFG_LBC_LSDMR_CL3		\
-				| CFG_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_RFCR16		\
+				| CONFIG_SYS_LBC_LSDMR_PRETOACT7	\
+				| CONFIG_SYS_LBC_LSDMR_ACTTORW7	\
+				| CONFIG_SYS_LBC_LSDMR_BL8		\
+				| CONFIG_SYS_LBC_LSDMR_WRC4		\
+				| CONFIG_SYS_LBC_LSDMR_CL3		\
+				| CONFIG_SYS_LBC_LSDMR_RFEN		\
 				)
 
 /*
@@ -277,39 +277,38 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_FSL_CADMUS
 
 #define CADMUS_BASE_ADDR 0xf8000000
-#define CFG_BR3_PRELIM   0xf8000801
-#define CFG_OR3_PRELIM   0xfff00ff7
+#define CONFIG_SYS_BR3_PRELIM   0xf8000801
+#define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x4000	    /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x4000	    /* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE	128	    /* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	    /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     2
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* pass open firmware flat tree */
@@ -317,8 +316,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
-#define CFG_64BIT_VSPRINTF	1
-#define CFG_64BIT_STRTOUL	1
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
 
 /*
  * I2C
@@ -326,35 +325,39 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
 
 /* EEPROM */
 #define CONFIG_ID_EEPROM
-#define CFG_I2C_EEPROM_CCID
-#define CFG_ID_EEPROM
-#define CFG_I2C_EEPROM_ADDR     0x57
-#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_EEPROM_CCID
+#define CONFIG_SYS_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xe2000000
-#define CFG_PCI1_IO_SIZE	0x100000	/* 1M */
-
-#define CFG_PCI2_MEM_BASE	0xa0000000
-#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI2_IO_BASE	0x00000000
-#define CFG_PCI2_IO_PHYS	0xe2100000
-#define CFG_PCI2_IO_SIZE	0x100000	/* 1M */
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x100000	/* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI2_IO_VIRT	0xe2100000
+#define CONFIG_SYS_PCI2_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS	0xe2100000
+#define CONFIG_SYS_PCI2_IO_SIZE	0x100000	/* 1M */
 
 #ifdef CONFIG_LEGACY
 #define BRIDGE_ID 17
@@ -374,7 +377,7 @@ extern unsigned long get_clock_freq(void);
 #undef CONFIG_TULIP
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
 #endif	/* CONFIG_PCI */
 
@@ -406,12 +409,12 @@ extern unsigned long get_clock_freq(void);
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
 #define CONFIG_ENV_SIZE		0x2000
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -431,6 +434,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
@@ -442,26 +447,26 @@ extern unsigned long get_clock_freq(void);
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index b650874..59cfde6 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -41,6 +41,7 @@
 #define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
@@ -65,30 +66,29 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 
 /*
  * Only possible on E500 Version 2 or newer cores.
  */
 #define CONFIG_ENABLE_36BIT_PHYS	1
 
-#define CFG_MEMTEST_START	0x00200000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00400000
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
-#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
-#define CFG_PCI1_ADDR		(CFG_CCSRBAR+0x8000)
-#define CFG_PCIE1_ADDR		(CFG_CCSRBAR+0xa000)
-#define CFG_PCIE2_ADDR		(CFG_CCSRBAR+0x9000)
-#define CFG_PCIE3_ADDR		(CFG_CCSRBAR+0xb000)
+#define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)
+#define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR+0xa000)
+#define CONFIG_SYS_PCIE2_ADDR		(CONFIG_SYS_CCSRBAR+0x9000)
+#define CONFIG_SYS_PCIE3_ADDR		(CONFIG_SYS_CCSRBAR+0xb000)
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR2
@@ -96,11 +96,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
 
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_VERY_BIG_RAM
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
@@ -145,39 +145,39 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * Local Bus Definitions
  */
-#define CFG_BOOT_BLOCK		0xfc000000	/* boot TLB */
+#define CONFIG_SYS_BOOT_BLOCK		0xfc000000	/* boot TLB */
 
-#define CFG_FLASH_BASE		0xff800000	/* start of FLASH 8M */
+#define CONFIG_SYS_FLASH_BASE		0xff800000	/* start of FLASH 8M */
 
-#define CFG_BR0_PRELIM		0xff801001
-#define CFG_BR1_PRELIM		0xfe801001
+#define CONFIG_SYS_BR0_PRELIM		0xff801001
+#define CONFIG_SYS_BR1_PRELIM		0xfe801001
 
-#define CFG_OR0_PRELIM		0xff806e65
-#define CFG_OR1_PRELIM		0xff806e65
+#define CONFIG_SYS_OR0_PRELIM		0xff806e65
+#define CONFIG_SYS_OR1_PRELIM		0xff806e65
 
-#define CFG_FLASH_BANKS_LIST	{CFG_FLASH_BASE}
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
 
-#define CFG_FLASH_QUIET_TEST
-#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
-#define CFG_LBC_NONCACHE_BASE	0xf8000000
+#define CONFIG_SYS_LBC_NONCACHE_BASE	0xf8000000
 
-#define CFG_BR2_PRELIM		0xf8201001	/* port size 16bit */
-#define CFG_OR2_PRELIM		0xfff06ff7	/* 1MB Compact Flash area*/
+#define CONFIG_SYS_BR2_PRELIM		0xf8201001	/* port size 16bit */
+#define CONFIG_SYS_OR2_PRELIM		0xfff06ff7	/* 1MB Compact Flash area*/
 
-#define CFG_BR3_PRELIM		0xf8100801	/* port size 8bit */
-#define CFG_OR3_PRELIM		0xfff06ff7	/* 1MB PIXIS area*/
+#define CONFIG_SYS_BR3_PRELIM		0xf8100801	/* port size 8bit */
+#define CONFIG_SYS_OR3_PRELIM		0xfff06ff7	/* 1MB PIXIS area*/
 
 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
 #define PIXIS_BASE	0xf8100000	/* PIXIS registers */
@@ -197,26 +197,26 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
 #define PIXIS_VSPEED2		0x1d	/* VELA VSpeed 2 */
-#define CFG_PIXIS_VBOOT_MASK	0x40    /* Reset altbank mask*/
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40    /* Reset altbank mask*/
 #define PIXIS_VSPEED2_TSEC1SER	0x2
 #define PIXIS_VSPEED2_TSEC3SER	0x1
 #define PIXIS_VCFGEN1_TSEC1SER	0x20
 #define PIXIS_VCFGEN1_TSEC3SER	0x40
+#define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
+#define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
 
 
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK      1
-#define CFG_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
-#define CFG_INIT_RAM_END       0x00004000      /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_LOCK      1
+#define CONFIG_SYS_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_END       0x00004000      /* End of used area in RAM */
 
 
-#define CFG_GBL_DATA_SIZE	128	/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
 
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
@@ -224,21 +224,21 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* pass open firmware flat tree */
@@ -246,72 +246,78 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
-#define CFG_64BIT_STRTOUL		1
-#define CFG_64BIT_VSPRINTF		1
+#define CONFIG_SYS_64BIT_STRTOUL		1
+#define CONFIG_SYS_64BIT_VSPRINTF		1
 
 /* I2C */
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_EEPROM_ADDR	0x57
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3100
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3100
 
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CFG_PCIE_PHYS		0x80000000	/* 1G PCIE TLB */
-#define CFG_PCI_PHYS		0xc0000000	/* 512M PCI TLB */
-
-#define CFG_PCI1_MEM_BASE	0xc0000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xe1000000
-#define CFG_PCI1_IO_SIZE	0x00010000	/* 64k */
-
-/* PCI view of System Memory */
-#define CFG_PCI_MEMORY_BUS	0x00000000
-#define CFG_PCI_MEMORY_PHYS	0x00000000
-#define CFG_PCI_MEMORY_SIZE	0x80000000
+#define CONFIG_SYS_PCIE_VIRT		0x80000000	/* 1G PCIE TLB */
+#define CONFIG_SYS_PCIE_PHYS		0x80000000	/* 1G PCIE TLB */
+#define CONFIG_SYS_PCI_VIRT		0xc0000000	/* 512M PCI TLB */
+#define CONFIG_SYS_PCI_PHYS		0xc0000000	/* 512M PCI TLB */
+
+#define CONFIG_SYS_PCI1_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_PCI1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe1000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 2, Slot 1, tgtid 1, Base address 9000 */
-#define CFG_PCIE2_MEM_BASE	0x80000000
-#define CFG_PCIE2_MEM_PHYS	CFG_PCIE2_MEM_BASE
-#define CFG_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCIE2_IO_BASE	0x00000000
-#define CFG_PCIE2_IO_PHYS	0xe1010000
-#define CFG_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xe1010000
+#define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xe1010000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 1, Slot 2,tgtid 2, Base address a000 */
-#define CFG_PCIE1_MEM_BASE	0xa0000000
-#define CFG_PCIE1_MEM_PHYS	CFG_PCIE1_MEM_BASE
-#define CFG_PCIE1_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCIE1_IO_BASE	0x00000000
-#define CFG_PCIE1_IO_PHYS	0xe1020000
-#define CFG_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xe1020000
+#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe1020000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 3, direct to uli, tgtid 3, Base address b000 */
-#define CFG_PCIE3_MEM_BASE	0xb0000000
-#define CFG_PCIE3_MEM_PHYS	CFG_PCIE3_MEM_BASE
-#define CFG_PCIE3_MEM_SIZE	0x00100000	/* 1M */
-#define CFG_PCIE3_IO_BASE	0x00000000
-#define CFG_PCIE3_IO_PHYS	0xb0100000	/* reuse mem LAW */
-#define CFG_PCIE3_IO_SIZE	0x00100000	/* 1M */
-#define CFG_PCIE3_MEM_BASE2	0xb0200000
-#define CFG_PCIE3_MEM_PHYS2	CFG_PCIE3_MEM_BASE2
-#define CFG_PCIE3_MEM_SIZE2	0x00200000	/* 1M */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xb0100000	/* reuse mem LAW */
+#define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xb0100000	/* reuse mem LAW */
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCIE3_MEM_VIRT2	0xb0200000
+#define CONFIG_SYS_PCIE3_MEM_BUS2	0xb0200000
+#define CONFIG_SYS_PCIE3_MEM_PHYS2	0xb0200000
+#define CONFIG_SYS_PCIE3_MEM_SIZE2	0x00200000	/* 1M */
 
 #if defined(CONFIG_PCI)
 
 /*PCIE video card used*/
-#define VIDEO_IO_OFFSET		CFG_PCIE2_IO_PHYS
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT
 
 /*PCI video card used*/
-/*#define VIDEO_IO_OFFSET	CFG_PCI1_IO_PHYS*/
+/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_VIRT*/
 
 /* video */
 #define CONFIG_VIDEO
@@ -324,7 +330,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_ATI_RADEON_FB
 #define CONFIG_VIDEO_LOGO
 /*#define CONFIG_CONSOLE_CURSOR*/
-#define CFG_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 #endif
 
 #define CONFIG_NET_MULTI
@@ -341,8 +347,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
 
 #ifndef CONFIG_PCI_PNP
-	#define PCI_ENET0_IOADDR	CFG_PCI1_IO_BASE
-	#define PCI_ENET0_MEMADDR	CFG_PCI1_IO_BASE
+	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BUS
+	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_IO_BUS
 	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
 #endif
 
@@ -352,10 +358,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #ifdef CONFIG_SCSI_AHCI
 #define CONFIG_SATA_ULI5288
-#define CFG_SCSI_MAX_SCSI_ID	4
-#define CFG_SCSI_MAX_LUN	1
-#define CFG_SCSI_MAX_DEVICE	(CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
-#define CFG_SCSI_MAXDEVICE	CFG_SCSI_MAX_DEVICE
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
+#define CONFIG_SYS_SCSI_MAX_LUN	1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
 #endif /* SCSCI */
 
 #endif	/* CONFIG_PCI */
@@ -374,6 +380,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_TSEC3	1
 #define CONFIG_TSEC3_NAME	"eTSEC3"
 
+#define CONFIG_PIXIS_SGMII_CMD
 #define CONFIG_FSL_SGMII_RISER	1
 #define SGMII_RISER_PHY_OFFSET	0x1c
 
@@ -395,16 +402,16 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#if CFG_MONITOR_BASE > 0xfff80000
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 #define CONFIG_ENV_ADDR		0xfff80000
 #else
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x70000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x70000)
 #endif
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K (one sector) */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -424,6 +431,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
@@ -439,26 +448,26 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 68bc106..95bce95 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -43,6 +43,7 @@
 #undef CONFIG_PCI2
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
@@ -68,7 +69,6 @@ extern unsigned long get_clock_freq(void);
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 #define CONFIG_CLEAR_LAW0		/* Clear LAW0 in cpu_init_r */
 
 /*
@@ -76,21 +76,21 @@ extern unsigned long get_clock_freq(void);
  */
 #define CONFIG_ENABLE_36BIT_PHYS	1
 
-#define CFG_MEMTEST_START	0x00200000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00400000
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
 
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
-#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
-#define CFG_PCI1_ADDR	(CFG_CCSRBAR+0x8000)
-#define CFG_PCI2_ADDR	(CFG_CCSRBAR+0x9000)
-#define CFG_PCIE1_ADDR	(CFG_CCSRBAR+0xa000)
+#define CONFIG_SYS_PCI1_ADDR	(CONFIG_SYS_CCSRBAR+0x8000)
+#define CONFIG_SYS_PCI2_ADDR	(CONFIG_SYS_CCSRBAR+0x9000)
+#define CONFIG_SYS_PCIE1_ADDR	(CONFIG_SYS_CCSRBAR+0xa000)
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR2
@@ -99,11 +99,11 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_DDR_SPD
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
 
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
@@ -153,43 +153,43 @@ extern unsigned long get_clock_freq(void);
  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65	 ORx
  */
 
-#define CFG_BOOT_BLOCK		0xff000000	/* boot TLB block */
-#define CFG_FLASH_BASE		CFG_BOOT_BLOCK	/* start of FLASH 16M */
+#define CONFIG_SYS_BOOT_BLOCK		0xff000000	/* boot TLB block */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_BOOT_BLOCK	/* start of FLASH 16M */
 
-#define CFG_BR0_PRELIM		0xff801001
-#define CFG_BR1_PRELIM		0xff001001
+#define CONFIG_SYS_BR0_PRELIM		0xff801001
+#define CONFIG_SYS_BR1_PRELIM		0xff001001
 
-#define	CFG_OR0_PRELIM		0xff806e65
-#define	CFG_OR1_PRELIM		0xff806e65
+#define	CONFIG_SYS_OR0_PRELIM		0xff806e65
+#define	CONFIG_SYS_OR1_PRELIM		0xff806e65
 
-#define CFG_FLASH_BANKS_LIST	{0xff800000, CFG_FLASH_BASE}
-#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
-#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{0xff800000, CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 
 /*
  * SDRAM on the Local Bus
  */
-#define CFG_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable */
-#define CFG_LBC_CACHE_SIZE	64
-#define CFG_LBC_NONCACHE_BASE	0xf8000000	/* Localbus non-cacheable */
-#define CFG_LBC_NONCACHE_SIZE	64
+#define CONFIG_SYS_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable */
+#define CONFIG_SYS_LBC_CACHE_SIZE	64
+#define CONFIG_SYS_LBC_NONCACHE_BASE	0xf8000000	/* Localbus non-cacheable */
+#define CONFIG_SYS_LBC_NONCACHE_SIZE	64
 
-#define CFG_LBC_SDRAM_BASE	CFG_LBC_CACHE_BASE	/* Localbus SDRAM */
-#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+#define CONFIG_SYS_LBC_SDRAM_BASE	CONFIG_SYS_LBC_CACHE_BASE	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
 
 /*
  * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  *
  * For BR2, need:
  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
@@ -201,14 +201,14 @@ extern unsigned long get_clock_freq(void);
  * 0	4    8	  12   16   20	 24   28
  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  *
- * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  * FIXME: the top 17 bits of BR2.
  */
 
-#define CFG_BR2_PRELIM		0xf0001861
+#define CONFIG_SYS_BR2_PRELIM		0xf0001861
 
 /*
- * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  *
  * For OR2, need:
  *    64MB mask for AM, OR2[0:7] = 1111 1100
@@ -221,35 +221,35 @@ extern unsigned long get_clock_freq(void);
  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  */
 
-#define CFG_OR2_PRELIM		0xfc006901
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
 
-#define CFG_LBC_LCRR		0x00030004	/* LB clock ratio reg */
-#define CFG_LBC_LBCR		0x00000000	/* LB config reg */
-#define CFG_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
-#define CFG_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
+#define CONFIG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
 
 /*
  * LSDMR masks
  */
-#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
 
 /*
  * Common settings for all Local Bus SDRAM commands.
@@ -257,13 +257,13 @@ extern unsigned long get_clock_freq(void);
  *		    or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
-#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_RFCR16		\
-				| CFG_LBC_LSDMR_PRETOACT7	\
-				| CFG_LBC_LSDMR_ACTTORW7	\
-				| CFG_LBC_LSDMR_BL8		\
-				| CFG_LBC_LSDMR_WRC4		\
-				| CFG_LBC_LSDMR_CL3		\
-				| CFG_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_RFCR16		\
+				| CONFIG_SYS_LBC_LSDMR_PRETOACT7	\
+				| CONFIG_SYS_LBC_LSDMR_ACTTORW7	\
+				| CONFIG_SYS_LBC_LSDMR_BL8		\
+				| CONFIG_SYS_LBC_LSDMR_WRC4		\
+				| CONFIG_SYS_LBC_LSDMR_CL3		\
+				| CONFIG_SYS_LBC_LSDMR_RFEN		\
 				)
 
 /*
@@ -299,41 +299,40 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_FSL_CADMUS
 
 #define CADMUS_BASE_ADDR 0xf8000000
-#define CFG_BR3_PRELIM	 0xf8000801
-#define CFG_OR3_PRELIM	 0xfff00ff7
+#define CONFIG_SYS_BR3_PRELIM	 0xf8000801
+#define CONFIG_SYS_OR3_PRELIM	 0xfff00ff7
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_INIT_L2_ADDR	0xf8f80000	/* relocate boot L2SRAM */
+#define CONFIG_SYS_INIT_L2_ADDR	0xf8f80000	/* relocate boot L2SRAM */
 
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX	2
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE \
+#define CONFIG_SYS_BAUDRATE_TABLE \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* pass open firmware flat tree */
@@ -341,8 +340,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
-#define CFG_64BIT_VSPRINTF	1
-#define CFG_64BIT_STRTOUL	1
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
 
 /*
  * I2C
@@ -350,55 +349,63 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
 
 /* EEPROM */
 #define CONFIG_ID_EEPROM
-#define CFG_I2C_EEPROM_CCID
-#define CFG_ID_EEPROM
-#define CFG_I2C_EEPROM_ADDR     0x57
-#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_EEPROM_CCID
+#define CONFIG_SYS_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CFG_PCI_PHYS		0x80000000	/* 1G PCI TLB */
-
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xe2000000
-#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCI_VIRT		0x80000000	/* 1G PCI TLB */
+#define CONFIG_SYS_PCI_PHYS		0x80000000	/* 1G PCI TLB */
+
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
 
 #ifdef CONFIG_PCI2
-#define CFG_PCI2_MEM_BASE	0xa0000000
-#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI2_IO_BASE	0x00000000
-#define CFG_PCI2_IO_PHYS	0xe2800000
-#define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCI2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI2_IO_VIRT	0xe2800000
+#define CONFIG_SYS_PCI2_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS	0xe2800000
+#define CONFIG_SYS_PCI2_IO_SIZE	0x00100000	/* 1M */
 #endif
 
 #ifdef CONFIG_PCIE1
-#define CFG_PCIE1_MEM_BASE	0xa0000000
-#define CFG_PCIE1_MEM_PHYS	CFG_PCIE1_MEM_BASE
-#define CFG_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCIE1_IO_BASE	0x00000000
-#define CFG_PCIE1_IO_PHYS	0xe3000000
-#define CFG_PCIE1_IO_SIZE	0x00100000	/*   1M */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xe3000000
+#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/*   1M */
 #endif
 
 #ifdef CONFIG_RIO
 /*
  * RapidIO MMU
  */
-#define CFG_RIO_MEM_BASE	0xC0000000
-#define CFG_RIO_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_RIO_MEM_VIRT	0xC0000000
+#define CONFIG_SYS_RIO_MEM_BUS	0xC0000000
+#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 512M */
 #endif
 
 #ifdef CONFIG_LEGACY
@@ -419,11 +426,6 @@ extern unsigned long get_clock_freq(void);
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 
-/* PCI view of System Memory */
-#define CFG_PCI_MEMORY_BUS	0x00000000
-#define CFG_PCI_MEMORY_PHYS	0x00000000
-#define CFG_PCI_MEMORY_SIZE	0x80000000
-
 #endif	/* CONFIG_PCI */
 
 
@@ -467,12 +469,12 @@ extern unsigned long get_clock_freq(void);
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
 #define CONFIG_ENV_SIZE		0x2000
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -492,6 +494,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
@@ -503,26 +507,26 @@ extern unsigned long get_clock_freq(void);
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index ab4bc86..6bf0961 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -38,6 +38,7 @@
 #define CONFIG_MPC8555CDS	1	/* MPC8555CDS board specific */
 
 #define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
@@ -62,19 +63,18 @@ extern unsigned long get_clock_freq(void);
  */
 #define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
 #define CONFIG_BTB			    /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
 
-#define CFG_MEMTEST_START	0x00200000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00400000
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
 
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
-#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR1
@@ -84,8 +84,8 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
@@ -135,37 +135,37 @@ extern unsigned long get_clock_freq(void);
  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
  */
 
-#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 8M */
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 8M */
 
-#define CFG_BR0_PRELIM		0xff801001
-#define CFG_BR1_PRELIM		0xff001001
+#define CONFIG_SYS_BR0_PRELIM		0xff801001
+#define CONFIG_SYS_BR1_PRELIM		0xff001001
 
-#define	CFG_OR0_PRELIM		0xff806e65
-#define	CFG_OR1_PRELIM		0xff806e65
+#define	CONFIG_SYS_OR0_PRELIM		0xff806e65
+#define	CONFIG_SYS_OR1_PRELIM		0xff806e65
 
-#define CFG_FLASH_BANKS_LIST	{0xff800000, CFG_FLASH_BASE}
-#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
-#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{0xff800000, CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 
 /*
  * SDRAM on the Local Bus
  */
-#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
-#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
 
 /*
  * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  *
  * For BR2, need:
  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
@@ -177,14 +177,14 @@ extern unsigned long get_clock_freq(void);
  * 0    4    8    12   16   20   24   28
  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  *
- * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  * FIXME: the top 17 bits of BR2.
  */
 
-#define CFG_BR2_PRELIM          0xf0001861
+#define CONFIG_SYS_BR2_PRELIM          0xf0001861
 
 /*
- * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  *
  * For OR2, need:
  *    64MB mask for AM, OR2[0:7] = 1111 1100
@@ -197,35 +197,35 @@ extern unsigned long get_clock_freq(void);
  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  */
 
-#define CFG_OR2_PRELIM		0xfc006901
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
 
-#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
-#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
-#define CFG_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
-#define CFG_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
+#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
 
 /*
  * LSDMR masks
  */
-#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
 
 /*
  * Common settings for all Local Bus SDRAM commands.
@@ -233,13 +233,13 @@ extern unsigned long get_clock_freq(void);
  *                  or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
-#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_RFCR16		\
-				| CFG_LBC_LSDMR_PRETOACT7	\
-				| CFG_LBC_LSDMR_ACTTORW7	\
-				| CFG_LBC_LSDMR_BL8		\
-				| CFG_LBC_LSDMR_WRC4		\
-				| CFG_LBC_LSDMR_CL3		\
-				| CFG_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_RFCR16		\
+				| CONFIG_SYS_LBC_LSDMR_PRETOACT7	\
+				| CONFIG_SYS_LBC_LSDMR_ACTTORW7	\
+				| CONFIG_SYS_LBC_LSDMR_BL8		\
+				| CONFIG_SYS_LBC_LSDMR_WRC4		\
+				| CONFIG_SYS_LBC_LSDMR_CL3		\
+				| CONFIG_SYS_LBC_LSDMR_RFEN		\
 				)
 
 /*
@@ -275,39 +275,38 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_FSL_CADMUS
 
 #define CADMUS_BASE_ADDR 0xf8000000
-#define CFG_BR3_PRELIM   0xf8000801
-#define CFG_OR3_PRELIM   0xfff00ff7
+#define CONFIG_SYS_BR3_PRELIM   0xf8000801
+#define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x4000	    /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x4000	    /* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE	128	    /* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	    /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     2
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* pass open firmware flat tree */
@@ -315,8 +314,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
-#define CFG_64BIT_VSPRINTF	1
-#define CFG_64BIT_STRTOUL	1
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
 
 /*
  * I2C
@@ -324,35 +323,39 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
 
 /* EEPROM */
 #define CONFIG_ID_EEPROM
-#define CFG_I2C_EEPROM_CCID
-#define CFG_ID_EEPROM
-#define CFG_I2C_EEPROM_ADDR     0x57
-#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_EEPROM_CCID
+#define CONFIG_SYS_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xe2000000
-#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
-
-#define CFG_PCI2_MEM_BASE	0xa0000000
-#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI2_IO_BASE	0x00000000
-#define CFG_PCI2_IO_PHYS	0xe2100000
-#define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI2_IO_VIRT	0xe2100000
+#define CONFIG_SYS_PCI2_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS	0xe2100000
+#define CONFIG_SYS_PCI2_IO_SIZE	0x00100000	/* 1M */
 
 #ifdef CONFIG_LEGACY
 #define BRIDGE_ID 17
@@ -372,7 +375,7 @@ extern unsigned long get_clock_freq(void);
 #undef CONFIG_TULIP
 
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
 #endif	/* CONFIG_PCI */
 
@@ -404,12 +407,12 @@ extern unsigned long get_clock_freq(void);
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
 #define CONFIG_ENV_SIZE		0x2000
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -429,6 +432,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
@@ -440,26 +445,26 @@ extern unsigned long get_clock_freq(void);
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 2bd8724..a41f50a 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -43,6 +43,7 @@
 #define CONFIG_MPC8560		1
 
 #define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
 #define CONFIG_ENV_OVERWRITE
@@ -72,22 +73,21 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 
-#define CFG_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions */
+#define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions */
 
-#define CFG_MEMTEST_START	0x00200000	/* memtest region */
-#define CFG_MEMTEST_END		0x00400000
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
 
 
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
-#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR1
@@ -97,8 +97,8 @@
 
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
@@ -108,42 +108,42 @@
 #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
 
 /* These are used when DDR doesn't use SPD.  */
-#define CFG_SDRAM_SIZE	128		/* DDR is 128MB */
-#define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
-#define CFG_DDR_CS0_CONFIG	0x80000002
-#define CFG_DDR_TIMING_1	0x37344321
-#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
-#define CFG_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
-#define CFG_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
-#define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
+#define CONFIG_SYS_SDRAM_SIZE	128		/* DDR is 128MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000002
+#define CONFIG_SYS_DDR_TIMING_1	0x37344321
+#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
+#define CONFIG_SYS_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
 
 /*
  * SDRAM on the Local Bus
  */
-#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
-#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
 
-#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 16M */
-#define CFG_BR0_PRELIM		0xff001801	/* port size 32bit */
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
+#define CONFIG_SYS_BR0_PRELIM		0xff001801	/* port size 32bit */
 
-#define CFG_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
-#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_MAX_FLASH_SECT	64		/* sectors per device */
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef  CFG_RAMBOOT
+#undef  CONFIG_SYS_RAMBOOT
 #endif
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
@@ -154,7 +154,7 @@
 
 /*
  * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  *
  * For BR2, need:
  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
@@ -166,14 +166,14 @@
  * 0    4    8    12   16   20   24   28
  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  *
- * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  * FIXME: the top 17 bits of BR2.
  */
 
-#define CFG_BR2_PRELIM		0xf0001861
+#define CONFIG_SYS_BR2_PRELIM		0xf0001861
 
 /*
- * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  *
  * For OR2, need:
  *    64MB mask for AM, OR2[0:7] = 1111 1100
@@ -186,84 +186,83 @@
  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  */
 
-#define CFG_OR2_PRELIM		0xfc006901
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
 
-#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
-#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
-#define CFG_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
-#define CFG_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
+#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
 
 /*
  * LSDMR masks
  */
-#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CFG_LBC_LSDMR_RFCR5	(3 << (31 - 16))
-#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CFG_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
-#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CFG_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CFG_LBC_LSDMR_WRC2	(2 << (31 - 27))
-#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CFG_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
-#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
-#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_BSMA1516	\
-				| CFG_LBC_LSDMR_RFCR5		\
-				| CFG_LBC_LSDMR_PRETOACT3	\
-				| CFG_LBC_LSDMR_ACTTORW3	\
-				| CFG_LBC_LSDMR_BL8		\
-				| CFG_LBC_LSDMR_WRC2		\
-				| CFG_LBC_LSDMR_CL3		\
-				| CFG_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_RFCR5	(3 << (31 - 16))
+#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CONFIG_SYS_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
+#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CONFIG_SYS_LBC_LSDMR_WRC2	(2 << (31 - 27))
+#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CONFIG_SYS_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
+#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_BSMA1516	\
+				| CONFIG_SYS_LBC_LSDMR_RFCR5		\
+				| CONFIG_SYS_LBC_LSDMR_PRETOACT3	\
+				| CONFIG_SYS_LBC_LSDMR_ACTTORW3	\
+				| CONFIG_SYS_LBC_LSDMR_BL8		\
+				| CONFIG_SYS_LBC_LSDMR_WRC2		\
+				| CONFIG_SYS_LBC_LSDMR_CL3		\
+				| CONFIG_SYS_LBC_LSDMR_RFEN		\
 				)
 
 /*
  * SDRAM Controller configuration sequence.
  */
-#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_PCHALL)
-#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_MRW)
-#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_NORMAL)
+#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
 
 
 /*
  * 32KB, 8-bit wide for ADS config reg
  */
-#define CFG_BR4_PRELIM          0xf8000801
-#define CFG_OR4_PRELIM		0xffffe1f1
-#define CFG_BCSR		(CFG_BR4_PRELIM & 0xffff8000)
+#define CONFIG_SYS_BR4_PRELIM          0xf8000801
+#define CONFIG_SYS_OR4_PRELIM		0xffffe1f1
+#define CONFIG_SYS_BCSR		(CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_ON_SCC	/* define if console on SCC */
@@ -272,13 +271,13 @@
 
 #define CONFIG_BAUDRATE		115200
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* pass open firmware flat tree */
@@ -286,8 +285,8 @@
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
-#define CFG_64BIT_VSPRINTF	1
-#define CFG_64BIT_STRTOUL	1
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
 
 /*
  * I2C
@@ -295,26 +294,29 @@
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
 
 /* RapidIO MMU */
-#define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
-#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
-#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M */
+#define CONFIG_SYS_RIO_MEM_VIRT	0xc0000000	/* base address */
+#define CONFIG_SYS_RIO_MEM_BUS	0xc0000000	/* base address */
+#define CONFIG_SYS_RIO_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
 
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xe2000000
-#define CFG_PCI1_IO_SIZE	0x100000	/* 1M */
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x100000	/* 1M */
 
 #if defined(CONFIG_PCI)
 
@@ -331,7 +333,7 @@
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
 #endif	/* CONFIG_PCI */
 
@@ -373,10 +375,10 @@
    * - Select bus for bd/buffers
    * - Full duplex
    */
-  #define CFG_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-  #define CFG_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-  #define CFG_CPMFCR_RAMTYPE    0
-  #define CFG_FCC_PSMR          (FCC_PSMR_FDE)
+  #define CONFIG_SYS_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+  #define CONFIG_SYS_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+  #define CONFIG_SYS_CPMFCR_RAMTYPE    0
+  #define CONFIG_SYS_FCC_PSMR          (FCC_PSMR_FDE)
   #define FETH2_RST		0x01
 #elif (CONFIG_ETHER_INDEX == 3)
   /* need more definitions here for FE3 */
@@ -411,20 +413,20 @@
 /*
  * Environment
  */
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
   #define CONFIG_ENV_IS_IN_FLASH	1
-  #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
   #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
   #define CONFIG_ENV_SIZE		0x2000
 #else
-  #define CFG_NO_FLASH		1	/* Flash is not usable now */
+  #define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
   #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-  #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
   #define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -443,6 +445,8 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
@@ -452,8 +456,8 @@
     #define CONFIG_CMD_MII
 #endif
 
-#if defined(CFG_RAMBOOT)
-    #undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 
@@ -463,28 +467,28 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
-#define CFG_LOAD_ADDR	0x1000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 80697a5..58ff52b 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -38,6 +38,7 @@
 #define CONFIG_PCIE1		1	/* PCIE controller */
 #define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_QE			/* Enable QE */
 #define CONFIG_ENV_OVERWRITE
@@ -60,7 +61,6 @@ extern unsigned long get_clock_freq(void);
  */
 #define CONFIG_L2_CACHE				/* toggle L2 cache	*/
 #define CONFIG_BTB				/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING			/* toggle addr streaming   */
 
 /*
  * Only possible on E500 Version 2 or newer cores.
@@ -70,20 +70,20 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
 
-#define CFG_MEMTEST_START	0x00200000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00400000
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
 
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
-#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
-#define CFG_PCI1_ADDR           (CFG_CCSRBAR+0x8000)
-#define CFG_PCIE1_ADDR          (CFG_CCSRBAR+0xa000)
+#define CONFIG_SYS_PCI1_ADDR           (CONFIG_SYS_CCSRBAR+0x8000)
+#define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR+0xa000)
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR2
@@ -91,12 +91,12 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
@@ -145,70 +145,70 @@ extern unsigned long get_clock_freq(void);
  * 0    4    8    12   16   20   24   28
  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
  */
-#define CFG_BCSR_BASE		0xf8000000
+#define CONFIG_SYS_BCSR_BASE		0xf8000000
 
-#define CFG_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
+#define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
 
 /*Chip select 0 - Flash*/
-#define CFG_BR0_PRELIM		0xfe001001
-#define	CFG_OR0_PRELIM		0xfe006ff7
+#define CONFIG_SYS_BR0_PRELIM		0xfe001001
+#define	CONFIG_SYS_OR0_PRELIM		0xfe006ff7
 
 /*Chip slelect 1 - BCSR*/
-#define CFG_BR1_PRELIM		0xf8000801
-#define	CFG_OR1_PRELIM		0xffffe9f7
+#define CONFIG_SYS_BR1_PRELIM		0xf8000801
+#define	CONFIG_SYS_OR1_PRELIM		0xffffe9f7
 
-/*#define CFG_FLASH_BANKS_LIST	{0xff800000, CFG_FLASH_BASE} */
-#define CFG_MAX_FLASH_BANKS		1		/* number of banks */
-#define CFG_MAX_FLASH_SECT		512		/* sectors per device */
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+/*#define CONFIG_SYS_FLASH_BANKS_LIST	{0xff800000, CONFIG_SYS_FLASH_BASE} */
+#define CONFIG_SYS_MAX_FLASH_BANKS		1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT		512		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 
 /*
  * SDRAM on the LocalBus
  */
-#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM	 */
-#define CFG_LBC_SDRAM_SIZE	64			/* LBC SDRAM is 64MB */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM	 */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64			/* LBC SDRAM is 64MB */
 
 
 /*Chip select 2 - SDRAM*/
-#define CFG_BR2_PRELIM      0xf0001861
-#define CFG_OR2_PRELIM		0xfc006901
+#define CONFIG_SYS_BR2_PRELIM      0xf0001861
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
 
-#define CFG_LBC_LCRR		0x00030004	/* LB clock ratio reg */
-#define CFG_LBC_LBCR		0x00000000	/* LB config reg */
-#define CFG_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
-#define CFG_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
+#define CONFIG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
 
 /*
  * LSDMR masks
  */
-#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
 
 /*
  * Common settings for all Local Bus SDRAM commands.
@@ -216,13 +216,13 @@ extern unsigned long get_clock_freq(void);
  *                  or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
-#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_RFCR16		\
-				| CFG_LBC_LSDMR_PRETOACT7	\
-				| CFG_LBC_LSDMR_ACTTORW7	\
-				| CFG_LBC_LSDMR_BL8		\
-				| CFG_LBC_LSDMR_WRC4		\
-				| CFG_LBC_LSDMR_CL3		\
-				| CFG_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_RFCR16		\
+				| CONFIG_SYS_LBC_LSDMR_PRETOACT7	\
+				| CONFIG_SYS_LBC_LSDMR_ACTTORW7	\
+				| CONFIG_SYS_LBC_LSDMR_BL8		\
+				| CONFIG_SYS_LBC_LSDMR_WRC4		\
+				| CONFIG_SYS_LBC_LSDMR_CL3		\
+				| CONFIG_SYS_LBC_LSDMR_RFEN		\
 				)
 
 /*
@@ -254,46 +254,45 @@ extern unsigned long get_clock_freq(void);
  * 0    4    8    12   16   20   24   28
  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  */
-#define CFG_BCSR (0xf8000000)
+#define CONFIG_SYS_BCSR (0xf8000000)
 
 /*Chip slelect 4 - PIB*/
-#define CFG_BR4_PRELIM   0xf8008801
-#define CFG_OR4_PRELIM   0xffffe9f7
+#define CONFIG_SYS_BR4_PRELIM   0xf8008801
+#define CONFIG_SYS_OR4_PRELIM   0xffffe9f7
 
 /*Chip select 5 - PIB*/
-#define CFG_BR5_PRELIM	 0xf8010801
-#define CFG_OR5_PRELIM	 0xffff69f7
+#define CONFIG_SYS_BR5_PRELIM	 0xf8010801
+#define CONFIG_SYS_OR5_PRELIM	 0xffff69f7
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x4000	    /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x4000	    /* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE	128	    /* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	    /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX		1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 
 /* Use the HUSH parser*/
-#define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* pass open firmware flat tree */
@@ -301,8 +300,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
-#define CFG_64BIT_VSPRINTF	1
-#define CFG_64BIT_STRTOUL	1
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
 
 /*
  * I2C
@@ -312,32 +311,38 @@ extern unsigned long get_clock_freq(void);
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_EEPROM_ADDR	0x52
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES        {{0,0x69}}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
-#define CFG_I2C2_OFFSET		0x3100
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES        {{0,0x69}}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
 
 /*
  * General PCI
  * Memory Addresses are mapped 1-1. I/O is mapped from 0
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xe2000000
-#define CFG_PCI1_IO_SIZE	0x00800000	/* 8M */
-
-#define CFG_PCIE1_MEM_BASE	0xa0000000
-#define CFG_PCIE1_MEM_PHYS	CFG_PCIE1_MEM_BASE
-#define CFG_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCIE1_IO_BASE	0x00000000
-#define CFG_PCIE1_IO_PHYS	0xe2800000
-#define CFG_PCIE1_IO_SIZE	0x00800000	/* 8M */
-
-#define CFG_SRIO_MEM_BASE	0xc0000000
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00800000	/* 8M */
+
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
+#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
+
+#define CONFIG_SYS_SRIO_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_SRIO_MEM_BUS	0xc0000000
+#define CONFIG_SYS_SRIO_MEM_PHYS	0xc0000000
 
 #ifdef CONFIG_QE
 /*
@@ -357,23 +362,23 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_UEC_ETH1         /* GETH1 */
 
 #ifdef CONFIG_UEC_ETH1
-#define CFG_UEC1_UCC_NUM        0       /* UCC1 */
-#define CFG_UEC1_RX_CLK         QE_CLK_NONE
-#define CFG_UEC1_TX_CLK         QE_CLK16
-#define CFG_UEC1_ETH_TYPE       GIGA_ETH
-#define CFG_UEC1_PHY_ADDR       7
-#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
+#define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16
+#define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR       7
+#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
 #endif
 
 #define CONFIG_UEC_ETH2         /* GETH2 */
 
 #ifdef CONFIG_UEC_ETH2
-#define CFG_UEC2_UCC_NUM        1       /* UCC2 */
-#define CFG_UEC2_RX_CLK         QE_CLK_NONE
-#define CFG_UEC2_TX_CLK         QE_CLK16
-#define CFG_UEC2_ETH_TYPE       GIGA_ETH
-#define CFG_UEC2_PHY_ADDR       1
-#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
+#define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
+#define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16
+#define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR       1
+#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
 #endif
 #endif /* CONFIG_QE */
 
@@ -386,12 +391,7 @@ extern unsigned long get_clock_freq(void);
 #undef CONFIG_TULIP
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
-
-/* PCI view of System Memory */
-#define CFG_PCI_MEMORY_BUS      0x00000000
-#define CFG_PCI_MEMORY_PHYS     0x00000000
-#define CFG_PCI_MEMORY_SIZE     0x80000000
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
 #endif	/* CONFIG_PCI */
 
@@ -425,12 +425,12 @@ extern unsigned long get_clock_freq(void);
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
 #define CONFIG_ENV_SIZE		0x2000
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 
 /*
@@ -451,6 +451,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
@@ -462,26 +464,26 @@ extern unsigned long get_clock_freq(void);
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE	256			/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	256			/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index d7e3a88..b60b364 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -36,12 +36,14 @@
 #define CONFIG_MP		1	/* support multiple processors */
 #define CONFIG_NUM_CPUS		2	/* Number of CPUs in the system */
 
+#define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
 #define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
 #define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
@@ -61,7 +63,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #endif
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */
-#define CONFIG_ICS307_REFCLK_HZ	33333333  /* ICS307 clock chip ref freq */
+#define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
 #define CONFIG_GET_CLK_FROM_ICS307	  /* decode sysclk and ddrclk freq
 					     from ICS307 instead of switches */
 
@@ -70,78 +72,80 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 
 #define CONFIG_ENABLE_36BIT_PHYS	1
 
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on */
-#define CFG_MEMTEST_END		0x7fffffff
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x7fffffff
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
-#define CFG_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS		0xfffe00000ull	/* physical addr of CCSRBAR */
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#endif
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
-#define CFG_PCIE3_ADDR		(CFG_CCSRBAR+0x8000)
-#define CFG_PCIE2_ADDR		(CFG_CCSRBAR+0x9000)
-#define CFG_PCIE1_ADDR		(CFG_CCSRBAR+0xa000)
+#define CONFIG_SYS_PCIE3_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)
+#define CONFIG_SYS_PCIE2_ADDR		(CONFIG_SYS_CCSRBAR+0x9000)
+#define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR+0xa000)
 
 /* DDR Setup */
+#define CONFIG_SYS_DDR_TLB_START 9
+#define CONFIG_VERY_BIG_RAM
 #define CONFIG_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
 #undef CONFIG_DDR_DLL
 
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 
 #define CONFIG_NUM_DDR_CONTROLLERS	2
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
 
 /* I2C addresses of SPD EEPROMs */
+#define CONFIG_SYS_SPD_BUS_NUM		1	/* SPD EEPROMS locate on I2C bus 1 */
 #define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
 #define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 1 DIMM 0 */
 
 /* These are used when DDR doesn't use SPD.  */
-#define CFG_SDRAM_SIZE		256		/* DDR is 256MB */
-#define CFG_DDR_CS0_BNDS	0x0000001F
-#define CFG_DDR_CS0_CONFIG	0x80010102	/* Enable, no interleaving */
-#define CFG_DDR_TIMING_3	0x00000000
-#define CFG_DDR_TIMING_0	0x00260802
-#define CFG_DDR_TIMING_1	0x3935d322
-#define CFG_DDR_TIMING_2	0x14904cc8
-#define CFG_DDR_MODE_1		0x00480432
-#define CFG_DDR_MODE_2		0x00000000
-#define CFG_DDR_INTERVAL	0x06180100
-#define CFG_DDR_DATA_INIT	0xdeadbeef
-#define CFG_DDR_CLK_CTRL	0x03800000
-#define CFG_DDR_OCD_CTRL	0x00000000
-#define CFG_DDR_OCD_STATUS	0x00000000
-#define CFG_DDR_CONTROL		0xC3008000	/* Type = DDR2 */
-#define CFG_DDR_CONTROL2	0x04400010
-
-#define CFG_DDR_ERR_INT_EN	0x0000000d
-#define CFG_DDR_ERR_DIS		0x00000000
-#define CFG_DDR_SBE		0x00010000
-
-/*
- * FIXME: Not used in fixed_sdram function
- */
-#define CFG_DDR_MODE		0x00000022
-#define CFG_DDR_CS1_BNDS	0x00000000
-#define CFG_DDR_CS2_BNDS	0x00000FFF	/* Not done */
-#define CFG_DDR_CS3_BNDS	0x00000FFF	/* Not done */
-#define CFG_DDR_CS4_BNDS	0x00000FFF	/* Not done */
-#define CFG_DDR_CS5_BNDS	0x00000FFF	/* Not done */
+#define CONFIG_SYS_SDRAM_SIZE		512		/* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000001F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0		0x00260802
+#define CONFIG_SYS_DDR_TIMING_1		0x626b2634
+#define CONFIG_SYS_DDR_TIMING_2		0x062874cf
+#define CONFIG_SYS_DDR_MODE_1		0x00440462
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_INTERVAL		0x0c300100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL		0x00800000
+#define CONFIG_SYS_DDR_OCD_CTRL		0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xc3000008	/* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2		0x24400000
+
+#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
+#define CONFIG_SYS_DDR_SBE		0x00010000
 
 /*
  * Make sure required options are set
@@ -166,6 +170,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Localbus non-cacheable
  * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
  * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
+ * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
  * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
@@ -174,38 +179,48 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 /*
  * Local Bus Definitions
  */
-#define CFG_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
+#define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
 
-#define CFG_BR0_PRELIM		0xe8001001
-#define CFG_OR0_PRELIM		0xf8000ff7
+#define CONFIG_SYS_BR0_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR0_PRELIM	0xf8000ff7
 
-#define CFG_BR1_PRELIM		0xe0001001
-#define CFG_OR1_PRELIM		0xf8000ff7
+#define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
 
-#define CFG_FLASH_BANKS_LIST	{CFG_FLASH_BASE + 0x8000000, CFG_FLASH_BASE}
-#define CFG_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 
-#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
-#define CFG_MAX_FLASH_SECT	1024		/* sectors per device */
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_AMD_CHECK_DQ7
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
 
 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
 #define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
+#ifdef CONFIG_PHYS_64BIT
+#define PIXIS_BASE_PHYS	0xfffdf0000ull
+#else
+#define PIXIS_BASE_PHYS	PIXIS_BASE
+#endif
 
-#define CFG_BR3_PRELIM	(PIXIS_BASE | 0x0801)	/* port size 8bit */
-#define CFG_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
 
 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
 #define PIXIS_VER		0x1	/* Board version at offset 1 */
@@ -237,20 +252,89 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 /* old pixis referenced names */
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
-#define CFG_PIXIS_VBOOT_MASK	0xc0
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
-#define CFG_INIT_RAM_END	0x00004000	/* End of used area in RAM */
-
-#define CFG_GBL_DATA_SIZE	128	/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	0xc0
+#define PIXIS_VSPEED2_TSEC1SER	0x8
+#define PIXIS_VSPEED2_TSEC2SER	0x4
+#define PIXIS_VSPEED2_TSEC3SER	0x2
+#define PIXIS_VSPEED2_TSEC4SER	0x1
+#define PIXIS_VCFGEN1_TSEC1SER	0x20
+#define PIXIS_VCFGEN1_TSEC2SER	0x20
+#define PIXIS_VCFGEN1_TSEC3SER	0x20
+#define PIXIS_VCFGEN1_TSEC4SER	0x20
+#define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER \
+					| PIXIS_VSPEED2_TSEC2SER \
+					| PIXIS_VSPEED2_TSEC3SER \
+					| PIXIS_VSPEED2_TSEC4SER)
+#define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER \
+					| PIXIS_VCFGEN1_TSEC2SER \
+					| PIXIS_VCFGEN1_TSEC3SER \
+					| PIXIS_VCFGEN1_TSEC4SER)
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+#define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
+				CONFIG_SYS_NAND_BASE + 0x40000, \
+				CONFIG_SYS_NAND_BASE + 0x80000,\
+				CONFIG_SYS_NAND_BASE + 0xC0000}
+#define CONFIG_SYS_MAX_NAND_DEVICE    4
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND		1
+#define CONFIG_NAND_FSL_ELBC	1
+#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+#define CONFIG_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
+			       | OR_FCM_PGS	       /* Large Page*/ \
+			       | OR_FCM_CSCT \
+			       | OR_FCM_CST \
+			       | OR_FCM_CHT \
+			       | OR_FCM_SCY_1 \
+			       | OR_FCM_TRLX \
+			       | OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
+
+#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
+			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+#define CONFIG_SYS_OR4_PRELIM  CONFIG_NAND_OR_PRELIM	 /* NAND Options */
+#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
+			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+#define CONFIG_SYS_OR5_PRELIM  CONFIG_NAND_OR_PRELIM	 /* NAND Options */
+
+#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
+			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+#define CONFIG_SYS_OR6_PRELIM  CONFIG_NAND_OR_PRELIM	 /* NAND Options */
 
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
 
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
@@ -258,21 +342,21 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /*
@@ -282,8 +366,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
-#define CFG_64BIT_VSPRINTF	1
-#define CFG_64BIT_STRTOUL	1
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
 
 /* new uImage format support */
 #define CONFIG_FIT		1
@@ -293,50 +377,92 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_EEPROM_ADDR	0x57
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3100
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{{0,0x29}}/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM	1
 
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 
-/* PCI view of System Memory */
-#define CFG_PCI_MEMORY_BUS	0x00000000
-#define CFG_PCI_MEMORY_PHYS	0x00000000
-#define CFG_PCI_MEMORY_SIZE	0x80000000
-
 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
-#define CFG_PCIE3_MEM_BASE	0x80000000
-#define CFG_PCIE3_MEM_PHYS	CFG_PCIE3_MEM_BASE
-#define CFG_PCIE3_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCIE3_IO_BASE	0x00000000
-#define CFG_PCIE3_IO_PHYS	0xffc00000
-#define CFG_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc00000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CFG_PCIE2_MEM_BASE	0xa0000000
-#define CFG_PCIE2_MEM_PHYS	CFG_PCIE2_MEM_BASE
-#define CFG_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCIE2_IO_BASE	0x00000000
-#define CFG_PCIE2_IO_PHYS	0xffc10000
-#define CFG_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CFG_PCIE1_MEM_BASE	0xc0000000
-#define CFG_PCIE1_MEM_PHYS	CFG_PCIE1_MEM_BASE
-#define CFG_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCIE1_IO_BASE	0x00000000
-#define CFG_PCIE1_IO_PHYS	0xffc20000
-#define CFG_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 
 #if defined(CONFIG_PCI)
 
 /*PCIE video card used*/
-#define VIDEO_IO_OFFSET		CFG_PCIE1_IO_PHYS
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE1_IO_VIRT
 
 /* video */
 #define CONFIG_VIDEO
@@ -349,7 +475,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_ATI_RADEON_FB
 #define CONFIG_VIDEO_LOGO
 /*#define CONFIG_CONSOLE_CURSOR*/
-#define CFG_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 #endif
 
 #define CONFIG_NET_MULTI
@@ -366,8 +492,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #endif
 
 #ifndef CONFIG_PCI_PNP
-	#define PCI_ENET0_IOADDR	CFG_PCIE3_IO_BASE
-	#define PCI_ENET0_MEMADDR	CFG_PCIE3_IO_BASE
+	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCIE3_IO_BUS
+	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCIE3_IO_BUS
 	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
 #endif
 
@@ -377,10 +503,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 
 #ifdef CONFIG_SCSI_AHCI
 #define CONFIG_SATA_ULI5288
-#define CFG_SCSI_MAX_SCSI_ID	4
-#define CFG_SCSI_MAX_LUN	1
-#define CFG_SCSI_MAX_DEVICE	(CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
-#define CFG_SCSI_MAXDEVICE	CFG_SCSI_MAX_DEVICE
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
+#define CONFIG_SYS_SCSI_MAX_LUN	1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
 #endif /* SCSI */
 
 #endif	/* CONFIG_PCI */
@@ -403,6 +529,14 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_TSEC4	1
 #define CONFIG_TSEC4_NAME	"eTSEC4"
 
+#define CONFIG_PIXIS_SGMII_CMD
+#define CONFIG_FSL_SGMII_RISER	1
+#define SGMII_RISER_PHY_OFFSET	0x1c
+
+#ifdef CONFIG_FSL_SGMII_RISER
+#define CONFIG_SYS_TBIPA_VALUE		0x10 /* avoid conflict with eTSEC4 paddr */
+#endif
+
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC3_PHY_ADDR		2
@@ -427,16 +561,16 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#if CFG_MONITOR_BASE > 0xfff80000
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 #define CONFIG_ENV_ADDR		0xfff80000
 #else
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x70000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #endif
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
  * Command line configuration.
@@ -448,6 +582,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
@@ -462,26 +598,26 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
@@ -532,6 +668,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_BAUDRATE	115200
 
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
+ "memctl_intlv_ctl=2\0"						\
  "netdev=eth0\0"						\
  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
  "tftpflash=tftpboot $loadaddr $uboot; "			\
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 4eee21c..1091043 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -31,16 +31,21 @@
 #endif
 
 #ifdef RUN_DIAG
-#define CFG_DIAG_ADDR		0xff800000
+#define CONFIG_SYS_DIAG_ADDR		0xff800000
 #endif
 
-#define CFG_RESET_ADDRESS	0xfff00100
+/*
+ * virtual address to be used for temporary mappings.  There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA	0xc0000000
 
 #define CONFIG_PCI		1	/* Enable PCI/PCIE*/
 #define CONFIG_PCI1		1	/* PCI controler 1 */
 #define CONFIG_PCIE1		1	/* PCIe 1 connected to ULI bridge */
 #define CONFIG_PCIE2		1	/* PCIe 2 connected to slot */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
 #define CONFIG_ENV_OVERWRITE
@@ -52,7 +57,7 @@
 /*
  * L2CR setup -- make sure this is right for your board!
  */
-#define CFG_L2
+#define CONFIG_SYS_L2
 #define L2_INIT		0
 #define L2_ENABLE	(L2CR_L2E |0x00100000 )
 
@@ -63,22 +68,25 @@
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
 #define CONFIG_MISC_INIT_R		1
 
-#define CFG_MEMTEST_START	0x00200000	/* memtest region */
-#define CFG_MEMTEST_END		0x00400000
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
 
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
-#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
-#define CFG_PCI1_ADDR		(CFG_CCSRBAR+0x8000)
-#define CFG_PCIE1_ADDR		(CFG_CCSRBAR+0xa000)
-#define CFG_PCIE2_ADDR		(CFG_CCSRBAR+0x9000)
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
 
-#define CFG_DIU_ADDR		(CFG_CCSRBAR+0x2c000)
+#define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)
+#define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR+0xa000)
+#define CONFIG_SYS_PCIE2_ADDR		(CONFIG_SYS_CCSRBAR+0x9000)
+
+#define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_CCSRBAR+0x2c000)
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR2
@@ -89,8 +97,9 @@
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
 #define CONFIG_VERY_BIG_RAM
 
 #define MPC86xx_DDR_SDRAM_CLK_CNTL
@@ -102,64 +111,55 @@
 #define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
 
 /* These are used when DDR doesn't use SPD.  */
-#define CFG_SDRAM_SIZE	256		/* DDR is 256MB */
+#define CONFIG_SYS_SDRAM_SIZE	256		/* DDR is 256MB */
 
 #if 0 /* TODO */
-#define CFG_DDR_CS0_BNDS	0x0000000F
-#define CFG_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
-#define CFG_DDR_TIMING_3	0x00000000
-#define CFG_DDR_TIMING_0	0x00260802
-#define CFG_DDR_TIMING_1	0x3935d322
-#define CFG_DDR_TIMING_2	0x14904cc8
-#define CFG_DDR_MODE_1		0x00480432
-#define CFG_DDR_MODE_2		0x00000000
-#define CFG_DDR_INTERVAL	0x06180100
-#define CFG_DDR_DATA_INIT	0xdeadbeef
-#define CFG_DDR_CLK_CTRL	0x03800000
-#define CFG_DDR_OCD_CTRL	0x00000000
-#define CFG_DDR_OCD_STATUS	0x00000000
-#define CFG_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
-#define CFG_DDR_CONTROL2	0x04400010
-
-#define CFG_DDR_ERR_INT_EN	0x00000000
-#define CFG_DDR_ERR_DIS		0x00000000
-#define CFG_DDR_SBE		0x000f0000
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	0x00260802
+#define CONFIG_SYS_DDR_TIMING_1	0x3935d322
+#define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
+#define CONFIG_SYS_DDR_MODE_1		0x00480432
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_INTERVAL	0x06180100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
+#define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2	0x04400010
+
+#define CONFIG_SYS_DDR_ERR_INT_EN	0x00000000
+#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
+#define CONFIG_SYS_DDR_SBE		0x000f0000
 
-/*
- * FIXME: Not used in fixed_sdram function
- */
-#define CFG_DDR_MODE		0x00000022
-#define CFG_DDR_CS1_BNDS	0x00000000
-#define CFG_DDR_CS2_BNDS	0x00000FFF	/* Not done */
-#define CFG_DDR_CS3_BNDS	0x00000FFF	/* Not done */
-#define CFG_DDR_CS4_BNDS	0x00000FFF	/* Not done */
-#define CFG_DDR_CS5_BNDS	0x00000FFF	/* Not done */
 #endif
 
 
 #define CONFIG_ID_EEPROM
-#define CFG_I2C_EEPROM_NXID
+#define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_ID_EEPROM
-#define CFG_I2C_EEPROM_ADDR     0x57
-#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 
 
-#define CFG_FLASH_BASE		0xf0000000 /* start of FLASH 128M */
-#define CFG_FLASH_BASE2		0xf8000000
+#define CONFIG_SYS_FLASH_BASE		0xf0000000 /* start of FLASH 128M */
+#define CONFIG_SYS_FLASH_BASE2		0xf8000000
 
-#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 
-#define CFG_BR0_PRELIM		0xf8001001 /* port size 16bit */
-#define CFG_OR0_PRELIM		0xf8006e65 /* 128MB NOR Flash*/
+#define CONFIG_SYS_BR0_PRELIM		0xf8001001 /* port size 16bit */
+#define CONFIG_SYS_OR0_PRELIM		0xf8006e65 /* 128MB NOR Flash*/
 
-#define CFG_BR1_PRELIM		0xf0001001 /* port size 16bit */
-#define CFG_OR1_PRELIM		0xf8006e65 /* 128MB Promjet */
+#define CONFIG_SYS_BR1_PRELIM		0xf0001001 /* port size 16bit */
+#define CONFIG_SYS_OR1_PRELIM		0xf8006e65 /* 128MB Promjet */
 #if 0 /* TODO */
-#define CFG_BR2_PRELIM		0xf0000000
-#define CFG_OR2_PRELIM		0xf0000000 /* 256MB NAND Flash - bank 1 */
+#define CONFIG_SYS_BR2_PRELIM		0xf0000000
+#define CONFIG_SYS_OR2_PRELIM		0xf0000000 /* 256MB NAND Flash - bank 1 */
 #endif
-#define CFG_BR3_PRELIM		0xe8000801 /* port size 8bit */
-#define CFG_OR3_PRELIM		0xfff06ff7 /* 1MB PIXIS area*/
+#define CONFIG_SYS_BR3_PRELIM		0xe8000801 /* port size 8bit */
+#define CONFIG_SYS_OR3_PRELIM		0xfff06ff7 /* 1MB PIXIS area*/
 
 
 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
@@ -179,67 +179,67 @@
 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
-#define CFG_PIXIS_VBOOT_MASK	0x0C    /* Reset altbank mask*/
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	0x0C    /* Reset altbank mask*/
 
-#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
-#define CFG_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
 
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef	CFG_RAMBOOT
+#undef	CONFIG_SYS_RAMBOOT
 #endif
 
-#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
 #undef CONFIG_SPD_EEPROM
-#define CFG_SDRAM_SIZE	256
+#define CONFIG_SYS_SDRAM_SIZE	256
 #endif
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#ifndef CFG_INIT_RAM_LOCK
-#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#ifndef CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
 #else
-#define CFG_INIT_RAM_ADDR	0xe4000000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4000000	/* Initial RAM address */
 #endif
-#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
-#define CFG_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE \
+#define CONFIG_SYS_BAUDRATE_TABLE \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 
-#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /*
@@ -253,8 +253,8 @@
 /* maximum size of the flat tree (8K) */
 #define OF_FLAT_TREE_MAX_SIZE	8192
 
-#define CFG_64BIT_VSPRINTF	1
-#define CFG_64BIT_STRTOUL	1
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
 
 /*
  * I2C
@@ -262,46 +262,43 @@
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
 
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xe1000000
-#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
-
-/* PCI view of System Memory */
-#define CFG_PCI_MEMORY_BUS	0x00000000
-#define CFG_PCI_MEMORY_PHYS	0x00000000
-#define CFG_PCI_MEMORY_SIZE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_VIRT	CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BUS	0x0000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe1000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
 
 /* For RTL8139 */
 #define KSEG1ADDR(x)	({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); })
 #define _IO_BASE		0x00000000
 
 /* controller 1, Base address 0xa000 */
-#define CFG_PCIE1_MEM_BASE	0xa0000000
-#define CFG_PCIE1_MEM_PHYS	CFG_PCIE1_MEM_BASE
-#define CFG_PCIE1_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCIE1_IO_BASE	0x00000000
-#define CFG_PCIE1_IO_PHYS	0xe3000000
-#define CFG_PCIE1_IO_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/* 1M */
 
 /* controller 2, Base Address 0x9000 */
-#define CFG_PCIE2_MEM_BASE	0x90000000
-#define CFG_PCIE2_MEM_PHYS	CFG_PCIE2_MEM_BASE
-#define CFG_PCIE2_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCIE2_IO_BASE	0x00000000	/* reuse mem LAW */
-#define CFG_PCIE2_IO_PHYS	0xe2000000
-#define CFG_PCIE2_IO_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCIE2_MEM_BUS	0x90000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000	/* reuse mem LAW */
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00100000	/* 1M */
 
 
 #if defined(CONFIG_PCI)
@@ -324,11 +321,11 @@
 #define CONFIG_PCI_OHCI		1
 #define CONFIG_USB_OHCI_NEW		1
 #define CONFIG_USB_KEYBOARD	1
-#define CFG_DEVICE_DEREGISTER
-#define CFG_USB_EVENT_POLL	1
-#define CFG_USB_OHCI_SLOT_NAME	"ohci_pci"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
-#define CFG_OHCI_SWAP_REG_ACCESS	1
+#define CONFIG_SYS_DEVICE_DEREGISTER
+#define CONFIG_SYS_USB_EVENT_POLL	1
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ohci_pci"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
 
 #if !defined(CONFIG_PCI_PNP)
 #define PCI_ENET0_IOADDR	0xe0000000
@@ -341,10 +338,10 @@
 
 #ifdef CONFIG_SCSI_AHCI
 #define CONFIG_SATA_ULI5288
-#define CFG_SCSI_MAX_SCSI_ID	4
-#define CFG_SCSI_MAX_LUN	1
-#define CFG_SCSI_MAX_DEVICE	(CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
-#define CFG_SCSI_MAXDEVICE	CFG_SCSI_MAX_DEVICE
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
+#define CONFIG_SYS_SCSI_MAX_LUN	1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
 #endif
 
 #endif	/* CONFIG_PCI */
@@ -353,10 +350,10 @@
  * BAT0		2G	Cacheable, non-guarded
  * 0x0000_0000	2G	DDR
  */
-#define CFG_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_DBAT0U	(BATU_BL_2G | BATU_VS | BATU_VP)
-#define CFG_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE )
-#define CFG_IBAT0U	CFG_DBAT0U
+#define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT0U	(BATU_BL_2G | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE )
+#define CONFIG_SYS_IBAT0U	CONFIG_SYS_DBAT0U
 
 /*
  * BAT1		1G	Cache-inhibited, guarded
@@ -365,91 +362,112 @@
  * 0x9000_0000	256M	PCI-Express 2 Memory
  */
 
-#define CFG_DBAT1L	(CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
+#define CONFIG_SYS_DBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 			| BATL_GUARDEDSTORAGE)
-#define CFG_DBAT1U	(CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
-#define CFG_IBAT1L	(CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT1U	CFG_DBAT1U
+#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
 
 /*
  * BAT2		16M	Cache-inhibited, guarded
  * 0xe100_0000	1M	PCI-1 I/O
  */
 
-#define CFG_DBAT2L	(CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 			| BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U	(CFG_PCI1_IO_PHYS | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_IBAT2L	(CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	CFG_DBAT2U
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
 
 /*
- * BAT3		32M	Cache-inhibited, guarded
- * 0xe200_0000	1M	PCI-Express 2 I/O
- * 0xe300_0000	1M	PCI-Express 1 I/O
+ * BAT3		4M	Cache-inhibited, guarded
+ * 0xe000_0000	4M	CCSR
  */
 
-#define CFG_DBAT3L	(CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
 			| BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U	(CFG_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_IBAT3L	(CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	CFG_DBAT3U
+#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
+
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT \
+				       | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
 
 /*
- * BAT4		4M	Cache-inhibited, guarded
- * 0xe000_0000	4M	CCSR
+ * BAT4		32M	Cache-inhibited, guarded
+ * 0xe200_0000	1M	PCI-Express 2 I/O
+ * 0xe300_0000	1M	PCI-Express 1 I/O
  */
-#define CFG_DBAT4L	(CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
+
+#define CONFIG_SYS_DBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 			| BATL_GUARDEDSTORAGE)
-#define CFG_DBAT4U	(CFG_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CFG_IBAT4L	(CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT4U	CFG_DBAT4U
+#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
+
 
 /*
  * BAT5		128K	Cacheable, non-guarded
  * 0xe400_0000	128K	Init RAM for stack in the CPU DCache (no backing memory)
  */
-#define CFG_DBAT5L	(CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_DBAT5U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_IBAT5L	CFG_DBAT5L
-#define CFG_IBAT5U	CFG_DBAT5U
+#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
+#define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
 
 /*
  * BAT6		256M	Cache-inhibited, guarded
  * 0xf000_0000	256M	FLASH
  */
-#define CFG_DBAT6L	(CFG_FLASH_BASE	 | BATL_PP_RW | BATL_CACHEINHIBIT \
+#define CONFIG_SYS_DBAT6L	(CONFIG_SYS_FLASH_BASE	 | BATL_PP_RW | BATL_CACHEINHIBIT \
 			| BATL_GUARDEDSTORAGE)
-#define CFG_DBAT6U	(CFG_FLASH_BASE	 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT6L	(CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U	CFG_DBAT6U
+#define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE	 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
+
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY	(TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
 
 /*
  * BAT7		4M	Cache-inhibited, guarded
  * 0xe800_0000	4M	PIXIS
  */
-#define CFG_DBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
+#define CONFIG_SYS_DBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
 			| BATL_GUARDEDSTORAGE)
-#define CFG_DBAT7U	(PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CFG_IBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT7U	CFG_DBAT7U
+#define CONFIG_SYS_DBAT7U	(PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT7U	CONFIG_SYS_DBAT7U
 
 
 /*
  * Environment
  */
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* 126k (one sector) for env */
 #define CONFIG_ENV_SIZE		0x2000
 #else
 #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 
 /*
@@ -470,8 +488,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 
-#if defined(CFG_RAMBOOT)
-#undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT)
+#undef CONFIG_CMD_SAVEENV
 #endif
 
 #if defined(CONFIG_PCI)
@@ -483,7 +501,7 @@
 
 
 #define CONFIG_WATCHDOG			/* watchdog enabled */
-#define CFG_WATCHDOG_FREQ	5000	/* Feed interval, 5s */
+#define CONFIG_SYS_WATCHDOG_FREQ	5000	/* Feed interval, 5s */
 
 /*DIU Configuration*/
 #define DIU_CONNECT_TO_DVI		/* DIU controller connects to DVI encoder*/
@@ -491,28 +509,28 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index fc55feb..9d66101 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -38,30 +38,45 @@
 #define CONFIG_MPC8641HPCN	1	/* MPC8641HPCN board specific */
 #define CONFIG_NUM_CPUS		2	/* Number of CPUs in the system */
 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
+/*#define CONFIG_PHYS_64BIT	1*/	/* Place devices in 36-bit space */
+#define CONFIG_ADDR_MAP		1	/* Use addr map */
 
 #ifdef RUN_DIAG
-#define CFG_DIAG_ADDR	     0xff800000
+#define CONFIG_SYS_DIAG_ADDR	     CONFIG_SYS_FLASH_BASE
 #endif
 
-#define CFG_RESET_ADDRESS    0xfff00100
+/*
+ * virtual address to be used for temporary mappings.  There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA	0xe0000000
+
+/*
+ * set this to enable Rapid IO.  PCI and RIO are mutually exclusive
+ */
+/*#define CONFIG_RIO		1*/
 
+#ifndef CONFIG_RIO			/* RIO/PCI are mutually exclusive */
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCI1		1	/* PCIE controler 1 (ULI bridge) */
 #define CONFIG_PCI2		1	/* PCIE controler 2 (slot) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#endif
 #define CONFIG_FSL_LAW		1	/* Use common FSL law init code */
 
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_HIGH_BATS	1	/* High BATs supported and enabled */
+#define CONFIG_SYS_NUM_ADDR_MAP 8	/* Number of addr map slots = 8 dbats */
 
 #define CONFIG_ALTIVEC		1
 
 /*
  * L2CR setup -- make sure this is right for your board!
  */
-#define CFG_L2
+#define CONFIG_SYS_L2
 #define L2_INIT		0
 #define L2_ENABLE	(L2CR_L2E)
 
@@ -74,19 +89,41 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
 
-#define CFG_MEMTEST_START	0x00200000	/* memtest region */
-#define CFG_MEMTEST_END		0x00400000
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * With the exception of PCI Memory and Rapid IO, most devices will simply
+ * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
+ * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
+ */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL
+#else
+#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0
+#endif
 
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
-#define CFG_CCSRBAR		0xf8000000	/* relocated CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
+
+/* Physical addresses */
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0xf
+#define CONFIG_SYS_CCSRBAR_PHYS		(CONFIG_SYS_CCSRBAR_PHYS_LOW \
+					 | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32))
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
+#define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR_PHYS_LOW
+#endif
 
-#define CFG_PCI1_ADDR		(CFG_CCSRBAR+0x8000)
-#define CFG_PCI2_ADDR		(CFG_CCSRBAR+0x9000)
+#define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)
+#define CONFIG_SYS_PCI2_ADDR		(CONFIG_SYS_CCSRBAR+0x9000)
 
 /*
  * DDR Setup
@@ -99,8 +136,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
 #define CONFIG_VERY_BIG_RAM
 
 #define MPC86xx_DDR_SDRAM_CLK_CNTL
@@ -121,72 +159,60 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * These are used when DDR doesn't use SPD.
  */
-#define CFG_SDRAM_SIZE		256		/* DDR is 256MB */
-#define CFG_DDR_CS0_BNDS	0x0000000F
-#define CFG_DDR_CS0_CONFIG	0x80010102      /* Enable, no interleaving */
-#define CFG_DDR_TIMING_3	0x00000000
-#define CFG_DDR_TIMING_0	0x00260802
-#define CFG_DDR_TIMING_1	0x39357322
-#define CFG_DDR_TIMING_2	0x14904cc8
-#define CFG_DDR_MODE_1		0x00480432
-#define CFG_DDR_MODE_2		0x00000000
-#define CFG_DDR_INTERVAL	0x06090100
-#define CFG_DDR_DATA_INIT	0xdeadbeef
-#define CFG_DDR_CLK_CTRL	0x03800000
-#define CFG_DDR_OCD_CTRL	0x00000000
-#define CFG_DDR_OCD_STATUS	0x00000000
-#define CFG_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
-#define CFG_DDR_CONTROL2	0x04400000
-
-/*
- * FIXME: Not used in fixed_sdram function
- */
-#define CFG_DDR_MODE		0x00000022
-#define CFG_DDR_CS1_BNDS	0x00000000
-#define CFG_DDR_CS2_BNDS	0x00000FFF	/* Not done */
-#define CFG_DDR_CS3_BNDS	0x00000FFF	/* Not done */
-#define CFG_DDR_CS4_BNDS	0x00000FFF	/* Not done */
-#define CFG_DDR_CS5_BNDS	0x00000FFF	/* Not done */
-
+#define CONFIG_SYS_SDRAM_SIZE		256		/* DDR is 256MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102      /* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	0x00260802
+#define CONFIG_SYS_DDR_TIMING_1	0x39357322
+#define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
+#define CONFIG_SYS_DDR_MODE_1		0x00480432
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_INTERVAL	0x06090100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
+#define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2	0x04400000
 
 #define CONFIG_ID_EEPROM
-#define CFG_I2C_EEPROM_NXID
+#define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_ID_EEPROM
-#define CFG_I2C_EEPROM_ADDR     0x57
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-
-/*
- * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000.
- * There is an 8MB flash.  In effect, the addresses from fe000000 to fe7fffff
- * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff.
- * However, when u-boot comes up, the flash_init needs hard start addresses
- * to build its info table.  For user convenience, the flash addresses is
- * fe800000 and ff800000.  That way, u-boot knows where the flash is
- * and the user can download u-boot code from promjet to fef00000, a
- * more intuitive location than fe700000.
- *
- * Note that, on switching the boot location, fef00000 becomes fff00000.
- */
-#define CFG_FLASH_BASE		0xfe800000     /* start of FLASH 32M */
-#define CFG_FLASH_BASE2		0xff800000
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 
-#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
+#define CONFIG_SYS_FLASH_BASE		0xef800000     /* start of FLASH 8M */
+#define CONFIG_SYS_FLASH_BASE_PHYS	(CONFIG_SYS_FLASH_BASE \
+					 | CONFIG_SYS_PHYS_ADDR_HIGH)
 
-#define CFG_BR0_PRELIM		0xff001001	/* port size 16bit */
-#define CFG_OR0_PRELIM		0xff006ff7	/* 16MB Boot Flash area*/
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
 
-#define CFG_BR1_PRELIM		0xfe001001	/* port size 16bit */
-#define CFG_OR1_PRELIM		0xff006ff7	/* 16MB Alternate Boot Flash area*/
+#define CONFIG_SYS_BR0_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+				 | 0x00001001)	/* port size 16bit */
+#define CONFIG_SYS_OR0_PRELIM	0xff806ff7	/* 8MB Boot Flash area*/
 
-#define CFG_BR2_PRELIM		0xf8201001	/* port size 16bit */
-#define CFG_OR2_PRELIM		0xfff06ff7	/* 1MB Compact Flash area*/
+#define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(CF_BASE_PHYS)		\
+				 | 0x00001001)	/* port size 16bit */
+#define CONFIG_SYS_OR2_PRELIM	0xffffeff7	/* 32k Compact Flash */
 
-#define CFG_BR3_PRELIM		0xf8100801	/* port size 8bit */
-#define CFG_OR3_PRELIM		0xfff06ff7	/* 1MB PIXIS area*/
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS)	\
+				 | 0x00000801) /* port size 8bit */
+#define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32k PIXIS area*/
 
+/*
+ * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
+ * The PIXIS and CF by themselves aren't large enough to take up the 128k
+ * required for the smallest BAT mapping, so there's a 64k hole.
+ */
+#define CONFIG_SYS_LBC_BASE		0xffde0000
+#define CONFIG_SYS_LBC_BASE_PHYS	(CONFIG_SYS_LBC_BASE \
+					 | CONFIG_SYS_PHYS_ADDR_HIGH)
 
 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
-#define PIXIS_BASE	0xf8100000	/* PIXIS registers */
+#define PIXIS_BASE		(CONFIG_SYS_LBC_BASE + 0x00010000)
+#define PIXIS_BASE_PHYS 	(CONFIG_SYS_LBC_BASE_PHYS + 0x00010000)
+#define PIXIS_SIZE		0x00008000	/* 32k */
 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
 #define PIXIS_VER		0x1	/* Board version at offset 1 */
 #define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
@@ -201,67 +227,71 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
-#define CFG_PIXIS_VBOOT_MASK	0x40	/* Reset altbank mask*/
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40	/* Reset altbank mask*/
+
+/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
+#define CF_BASE			(PIXIS_BASE + PIXIS_SIZE)
+#define CF_BASE_PHYS		(PIXIS_BASE_PHYS + PIXIS_SIZE)
 
-#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
-#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
 
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef	CFG_RAMBOOT
+#undef	CONFIG_SYS_RAMBOOT
 #endif
 
-#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
 #undef CONFIG_SPD_EEPROM
-#define CFG_SDRAM_SIZE	256
+#define CONFIG_SYS_SDRAM_SIZE	256
 #endif
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#ifndef CFG_INIT_RAM_LOCK
-#define CFG_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#ifndef CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
 #else
-#define CFG_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
 #endif
-#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(1024 * 1024)	 /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	 /* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /*
@@ -272,8 +302,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
 
-#define CFG_64BIT_VSPRINTF	1
-#define CFG_64BIT_STRTOUL	1
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
 
 /*
  * I2C
@@ -281,50 +311,74 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3100
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3100
 
 /*
  * RapidIO MMU
  */
-#define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
-#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
-#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M */
+#define CONFIG_SYS_RIO_MEM_BASE	0x80000000	/* base address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_RIO_MEM_PHYS  0x0000000c00000000ULL
+#else
+#define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BASE
+#endif
+#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
 
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xe2000000
-#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
-
-/* PCI view of System Memory */
-#define CFG_PCI_MEMORY_BUS	0x00000000
-#define CFG_PCI_MEMORY_PHYS	0x00000000
-#define CFG_PCI_MEMORY_SIZE	0x80000000
+
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_MEM_BUS		0xc0000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x0000000c00000000ULL
+#else
+#define CONFIG_SYS_PCI1_MEM_BUS		CONFIG_SYS_PCI1_MEM_VIRT
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_VIRT
+#endif
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCI1_IO_PHYS	(CONFIG_SYS_PCI1_IO_VIRT \
+				 | CONFIG_SYS_PHYS_ADDR_HIGH)
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64K */
 
 /* For RTL8139 */
 #define KSEG1ADDR(x)		({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
 #define _IO_BASE		0x00000000
 
-#define CFG_PCI2_MEM_BASE	0xa0000000
-#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI2_IO_BASE	0x00000000
-#define CFG_PCI2_IO_PHYS	0xe3000000
-#define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */
+#ifdef CONFIG_PHYS_64BIT
+/*
+ * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT.
+ * This will increase the amount of PCI address space available for
+ * for mapping RAM.
+ */
+#define CONFIG_SYS_PCI2_MEM_BUS		CONFIG_SYS_PCI1_MEM_BUS
+#else
+#define CONFIG_SYS_PCI2_MEM_BUS		(CONFIG_SYS_PCI1_MEM_BUS \
+					 + CONFIG_SYS_PCI1_MEM_SIZE)
+#endif
+#define CONFIG_SYS_PCI2_MEM_VIRT 	(CONFIG_SYS_PCI1_MEM_VIRT \
+					 + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCI2_MEM_PHYS	(CONFIG_SYS_PCI1_MEM_PHYS \
+					 + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI2_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \
+				 + CONFIG_SYS_PCI1_IO_SIZE)
+#define CONFIG_SYS_PCI2_IO_PHYS	(CONFIG_SYS_PCI1_IO_PHYS \
+				 + CONFIG_SYS_PCI1_IO_SIZE)
+#define CONFIG_SYS_PCI2_IO_SIZE	CONFIG_SYS_PCI1_IO_SIZE
 
 #if defined(CONFIG_PCI)
 
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 
-#undef CFG_SCSI_SCAN_BUS_REVERSE
+#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
 
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
@@ -340,23 +394,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_PCI_OHCI			1
 #define CONFIG_USB_OHCI_NEW		1
 #define CONFIG_USB_KEYBOARD		1
-#define CFG_DEVICE_DEREGISTER
-#define CFG_USB_EVENT_POLL		1
-#define CFG_USB_OHCI_SLOT_NAME		"ohci_pci"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS	15
-#define CFG_OHCI_SWAP_REG_ACCESS	1
-
-#if !defined(CONFIG_PCI_PNP)
-    #define PCI_ENET0_IOADDR	0xe0000000
-    #define PCI_ENET0_MEMADDR	0xe0000000
-    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
-#endif
+#define CONFIG_SYS_DEVICE_DEREGISTER
+#define CONFIG_SYS_USB_EVENT_POLL		1
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ohci_pci"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
 
 /*PCIE video card used*/
-#define VIDEO_IO_OFFSET		CFG_PCI2_IO_PHYS
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCI2_IO_VIRT
 
 /*PCI video card used*/
-/*#define VIDEO_IO_OFFSET	CFG_PCI1_IO_PHYS*/
+/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_VIRT*/
 
 /* video */
 #define CONFIG_VIDEO
@@ -369,7 +417,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_ATI_RADEON_FB
 #define CONFIG_VIDEO_LOGO
 /*#define CONFIG_CONSOLE_CURSOR*/
-#define CFG_ISA_IO_BASE_ADDRESS CFG_PCI2_IO_PHYS
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
@@ -379,10 +427,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #ifdef CONFIG_SCSI_AHCI
 #define CONFIG_SATA_ULI5288
-#define CFG_SCSI_MAX_SCSI_ID	4
-#define CFG_SCSI_MAX_LUN	1
-#define CFG_SCSI_MAX_DEVICE	(CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
-#define CFG_SCSI_MAXDEVICE	CFG_SCSI_MAX_DEVICE
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
+#define CONFIG_SYS_SCSI_MAX_LUN	1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
 #endif
 
 #define CONFIG_MPC86XX_PCI2
@@ -423,99 +471,163 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #endif	/* CONFIG_TSEC_ENET */
 
+/*  Contort an addr into the format needed for BATs */
+#ifdef CONFIG_PHYS_64BIT
+#define BAT_PHYS_ADDR(x)         ((unsigned long) \
+				  ((x & 0x00000000ffffffffULL) |	\
+				   ((x & 0x0000000e00000000ULL) >> 24) | \
+				   ((x & 0x0000000100000000ULL) >> 30)))
+#else
+#define BAT_PHYS_ADDR(x)        (x)
+#endif
+
+
+/* Put high physical address bits into the BAT format */
+#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
+#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
+
 /*
- * BAT0		2G     Cacheable, non-guarded
- * 0x0000_0000	2G     DDR
+ * BAT0		DDR
  */
-#define CFG_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_DBAT0U	(BATU_BL_2G | BATU_VS | BATU_VP)
-#define CFG_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE )
-#define CFG_IBAT0U	CFG_DBAT0U
+#define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT0U	(BATU_BL_2G | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE )
+#define CONFIG_SYS_IBAT0U	CONFIG_SYS_DBAT0U
 
 /*
- * BAT1		1G     Cache-inhibited, guarded
- * 0x8000_0000	512M   PCI-Express 1 Memory
- * 0xa000_0000	512M   PCI-Express 2 Memory
- *	Changed it for operating from 0xd0000000
+ * BAT1		LBC (PIXIS/CF)
  */
-#define CFG_DBAT1L	( CFG_PCI1_MEM_PHYS | BATL_PP_RW \
+#define CONFIG_SYS_DBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_LBC_BASE | BATU_BL_128K \
+				 | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
+				 | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
+
+/* if CONFIG_PCI:
+ * BAT2		PCI1 and PCI1 MEM
+ * if CONFIG_RIO
+ * BAT2		Rapidio Memory
+ */
+#ifdef CONFIG_PCI
+#define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT \
+				 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G \
+				 | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
+#else /* CONFIG_RIO */
+#define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \
+				 | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT)
+
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT1U	(CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
-#define CFG_IBAT1L	(CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT1U	CFG_DBAT1U
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
+#endif
 
 /*
- * BAT2		512M   Cache-inhibited, guarded
- * 0xc000_0000	512M   RapidIO Memory
+ * BAT3		CCSR Space
+ * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs
+ * instead.  The assembler chokes on ULL.
  */
-#define CFG_DBAT2L	(CFG_RIO_MEM_PHYS | BATL_PP_RW \
-			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U	(CFG_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
-#define CFG_IBAT2L	(CFG_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	CFG_DBAT2U
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_CCSRBAR_PHYS_LOW \
+				 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+				 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT \
+				 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
+				 | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR_PHYS_LOW \
+				 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+				 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
+
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT \
+				       | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
 
 /*
- * BAT3		4M     Cache-inhibited, guarded
- * 0xf800_0000	4M     CCSR
+ * BAT4		PCI1_IO and PCI2_IO
  */
-#define CFG_DBAT3L	( CFG_CCSRBAR | BATL_PP_RW \
-			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U	(CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
-#define CFG_IBAT3L	(CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	CFG_DBAT3U
+#define CONFIG_SYS_DBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT \
+				 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \
+				 | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
 
 /*
- * BAT4		32M    Cache-inhibited, guarded
- * 0xe200_0000	16M    PCI-Express 1 I/O
- * 0xe300_0000	16M    PCI-Express 2 I/0
- *    Note that this is at 0xe0000000
+ * BAT5		Init RAM for stack in the CPU DCache (no backing memory)
  */
-#define CFG_DBAT4L	( CFG_PCI1_IO_PHYS | BATL_PP_RW \
-			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT4U	(CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_IBAT4L	(CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT4U	CFG_DBAT4U
+#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
+#define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
 
 /*
- * BAT5		128K   Cacheable, non-guarded
- * 0xe401_0000	128K   Init RAM for stack in the CPU DCache (no backing memory)
+ * BAT6		FLASH
  */
-#define CFG_DBAT5L	(CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_DBAT5U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_IBAT5L	CFG_DBAT5L
-#define CFG_IBAT5U	CFG_DBAT5U
+#define CONFIG_SYS_DBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT \
+				 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
+				 | BATU_VP)
+#define CONFIG_SYS_IBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+				 | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
+
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY	(TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
 
 /*
- * BAT6		32M    Cache-inhibited, guarded
- * 0xfe00_0000	32M    FLASH
+ * BAT7		FREE - used later for tmp mappings
  */
-#define CFG_DBAT6L	((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
-			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT6U	((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_IBAT6L	((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U	CFG_DBAT6U
-
-#define CFG_DBAT7L 0x00000000
-#define CFG_DBAT7U 0x00000000
-#define CFG_IBAT7L 0x00000000
-#define CFG_IBAT7U 0x00000000
+#define CONFIG_SYS_DBAT7L 0x00000000
+#define CONFIG_SYS_DBAT7U 0x00000000
+#define CONFIG_SYS_IBAT7L 0x00000000
+#define CONFIG_SYS_IBAT7U 0x00000000
 
 /*
  * Environment
  */
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
     #define CONFIG_ENV_IS_IN_FLASH	1
-    #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x60000)
+    #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x60000)
     #define CONFIG_ENV_SECT_SIZE		0x10000	/* 64K(one sector) for env */
-    #define CONFIG_ENV_SIZE		0x2000
 #else
     #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-    #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
-    #define CONFIG_ENV_SIZE		0x2000
+    #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #endif
+#define CONFIG_ENV_SIZE		0x2000
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 
 /*
@@ -536,8 +648,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_REGINFO
 
-#if defined(CFG_RAMBOOT)
-    #undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
 #endif
 
 #if defined(CONFIG_PCI)
@@ -553,28 +665,28 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
@@ -639,8 +751,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 	"ramdiskfile=your.ramdisk.u-boot\0"				\
 	"fdtaddr=c00000\0"						\
 	"fdtfile=mpc8641_hpcn.dtb\0"					\
-	"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
-	"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+	"en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"			\
+	"dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
 	"maxcpus=2"
 
 
diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h
index 233a8d1..85c6890 100644
--- a/include/configs/MPC86xADS.h
+++ b/include/configs/MPC86xADS.h
@@ -35,15 +35,15 @@
 
 #define CONFIG_8xx_OSCLK		10000000 /* 10MHz oscillator on EXTCLK  */
 #define CONFIG_8xx_CPUCLK_DEFAULT	50000000
-#define CFG_8xx_CPUCLK_MIN		40000000
-#define CFG_8xx_CPUCLK_MAX		80000000
+#define CONFIG_SYS_8xx_CPUCLK_MIN		40000000
+#define CONFIG_SYS_8xx_CPUCLK_MAX		80000000
 
 #define CONFIG_DRAM_50MHZ       1
 #define CONFIG_SDRAM_50MHZ      1
 
 #include "../../board/fads/fads.h"
 
-#define CFG_OR5_PRELIM		0xFFFF8110	/* 64Kbyte address space */
-#define CFG_BR5_PRELIM		(CFG_PHYDEV_ADDR | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR5_PRELIM		0xFFFF8110	/* 64Kbyte address space */
+#define CONFIG_SYS_BR5_PRELIM		(CONFIG_SYS_PHYDEV_ADDR | BR_PS_8 | BR_V)
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/MPC885ADS.h b/include/configs/MPC885ADS.h
index f4d1842..8ffc1b2 100644
--- a/include/configs/MPC885ADS.h
+++ b/include/configs/MPC885ADS.h
@@ -22,15 +22,15 @@
 
 #define CONFIG_8xx_OSCLK		10000000 /* 10 MHz oscillator on EXTCLK  */
 #define CONFIG_8xx_CPUCLK_DEFAULT	50000000
-#define CFG_8xx_CPUCLK_MIN		40000000
-#define CFG_8xx_CPUCLK_MAX		133000000
+#define CONFIG_SYS_8xx_CPUCLK_MIN		40000000
+#define CONFIG_SYS_8xx_CPUCLK_MAX		133000000
 
 #define CONFIG_SDRAM_50MHZ      1
 
 #include "../../board/fads/fads.h"
 
-#define CFG_OR5_PRELIM		0xFFFF8110	/* 64Kbyte address space */
-#define CFG_BR5_PRELIM		(CFG_PHYDEV_ADDR | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR5_PRELIM		0xFFFF8110	/* 64Kbyte address space */
+#define CONFIG_SYS_BR5_PRELIM		(CONFIG_SYS_PHYDEV_ADDR | BR_PS_8 | BR_V)
 
 #define CONFIG_HAS_ETH1
 
diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h
index 88d8072..ec9e1ec 100644
--- a/include/configs/MUSENKI.h
+++ b/include/configs/MUSENKI.h
@@ -48,7 +48,7 @@
 
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		9600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_BOOTDELAY	5
 
@@ -71,16 +71,16 @@
 /*
  * Miscellaneous configurable options
  */
-#undef CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#undef CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 
 /* Print Buffer Size
  */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS	8		/* Max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	8		/* Max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -102,63 +102,63 @@
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE	    0x00000000
+#define CONFIG_SYS_SDRAM_BASE	    0x00000000
 
-#define CFG_FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank on RCS#0 */
-#define CFG_FLASH_BASE1_PRELIM      0xFF000000      /* FLASH bank on RCS#1 */
-#define CFG_FLASH_BASE  CFG_FLASH_BASE0_PRELIM
+#define CONFIG_SYS_FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank on RCS#0 */
+#define CONFIG_SYS_FLASH_BASE1_PRELIM      0xFF000000      /* FLASH bank on RCS#1 */
+#define CONFIG_SYS_FLASH_BASE  CONFIG_SYS_FLASH_BASE0_PRELIM
 
 /* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
  * reset vector is actually located at FFB00100, but the 8245
  * takes care of us.
  */
-#define CFG_RESET_ADDRESS   0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 
-#define CFG_EUMB_ADDR	    0xFC000000
+#define CONFIG_SYS_EUMB_ADDR	    0xFC000000
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
 
-#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
 
 	/* Maximum amount of RAM.
 	 */
-#define CFG_MAX_RAM_SIZE    0x08000000	/* 0 .. 128 MB of (S)DRAM */
+#define CONFIG_SYS_MAX_RAM_SIZE    0x08000000	/* 0 .. 128 MB of (S)DRAM */
 
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#undef CFG_RAMBOOT
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#undef CONFIG_SYS_RAMBOOT
 #else
-#define CFG_RAMBOOT
+#define CONFIG_SYS_RAMBOOT
 #endif
 
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
 
-#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_REG_SIZE	1
 
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
-#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_EUMB_ADDR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4600)
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area
  */
 
-/* #define CFG_MONITOR_BASE        TEXT_BASE */
-/*#define CFG_GBL_DATA_SIZE    256*/
-#define CFG_GBL_DATA_SIZE      128
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+/* #define CONFIG_SYS_MONITOR_BASE        TEXT_BASE */
+/*#define CONFIG_SYS_GBL_DATA_SIZE    256*/
+#define CONFIG_SYS_GBL_DATA_SIZE      128
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_END      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 
 /*
@@ -169,41 +169,41 @@
  */
 
 #define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
-#define CFG_HZ		     1000
+#define CONFIG_SYS_HZ		     1000
 
 	/* Bit-field values for MCCR1.
 	 */
-#define CFG_ROMNAL	    7
-#define CFG_ROMFAL	    11
-#define CFG_DBUS_SIZE       0x3
+#define CONFIG_SYS_ROMNAL	    7
+#define CONFIG_SYS_ROMFAL	    11
+#define CONFIG_SYS_DBUS_SIZE       0x3
 
 	/* Bit-field values for MCCR2.
 	 */
-#define CFG_TSWAIT	    0x5		    /* Transaction Start Wait States timer */
-#define CFG_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
+#define CONFIG_SYS_TSWAIT	    0x5		    /* Transaction Start Wait States timer */
+#define CONFIG_SYS_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
 
 	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 	 */
-#define CFG_BSTOPRE	    121
+#define CONFIG_SYS_BSTOPRE	    121
 
 	/* Bit-field values for MCCR3.
 	 */
-#define CFG_REFREC	    8	    /* Refresh to activate interval */
+#define CONFIG_SYS_REFREC	    8	    /* Refresh to activate interval */
 
 	/* Bit-field values for MCCR4.
 	 */
-#define CFG_PRETOACT	    3	    /* Precharge to activate interval FIXME: was 2	*/
-#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval FIXME: was 5	*/
-#define CFG_ACTORW	    3		/* FIXME was 2 */
-#define CFG_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
-#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
-#define CFG_REGISTERD_TYPE_BUFFER 1
-#define CFG_EXTROM	    1
-#define CFG_REGDIMM	    0
+#define CONFIG_SYS_PRETOACT	    3	    /* Precharge to activate interval FIXME: was 2	*/
+#define CONFIG_SYS_ACTTOPRE	    5	    /* Activate to Precharge interval FIXME: was 5	*/
+#define CONFIG_SYS_ACTORW	    3		/* FIXME was 2 */
+#define CONFIG_SYS_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
+#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
+#define CONFIG_SYS_EXTROM	    1
+#define CONFIG_SYS_REGDIMM	    0
 
-#define CFG_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
+#define CONFIG_SYS_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
 
-#define CFG_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
+#define CONFIG_SYS_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
 
 /* Memory bank settings.
  * Only bits 20-29 are actually used from these vales to set the
@@ -212,69 +212,69 @@
  * address. Refer to the MPC8240 book.
  */
 
-#define CFG_BANK0_START	    0x00000000
-#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START	    0x3ff00000
-#define CFG_BANK1_END	    0x3fffffff
-#define CFG_BANK1_ENABLE    0
-#define CFG_BANK2_START	    0x3ff00000
-#define CFG_BANK2_END	    0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START	    0x3ff00000
-#define CFG_BANK3_END	    0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START	    0x3ff00000
-#define CFG_BANK4_END	    0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START	    0x3ff00000
-#define CFG_BANK5_END	    0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START	    0x3ff00000
-#define CFG_BANK6_END	    0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START	    0x3ff00000
-#define CFG_BANK7_END	    0x3fffffff
-#define CFG_BANK7_ENABLE    0
-
-#define CFG_ODCR	    0xff
-
-#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L  CFG_IBAT0L
-#define CFG_DBAT0U  CFG_IBAT0U
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-#define CFG_DBAT2L  CFG_IBAT2L
-#define CFG_DBAT2U  CFG_IBAT2U
-#define CFG_DBAT3L  CFG_IBAT3L
-#define CFG_DBAT3U  CFG_IBAT3U
+#define CONFIG_SYS_BANK0_START	    0x00000000
+#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE    1
+#define CONFIG_SYS_BANK1_START	    0x3ff00000
+#define CONFIG_SYS_BANK1_END	    0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE    0
+#define CONFIG_SYS_BANK2_START	    0x3ff00000
+#define CONFIG_SYS_BANK2_END	    0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE    0
+#define CONFIG_SYS_BANK3_START	    0x3ff00000
+#define CONFIG_SYS_BANK3_END	    0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE    0
+#define CONFIG_SYS_BANK4_START	    0x3ff00000
+#define CONFIG_SYS_BANK4_END	    0x3fffffff
+#define CONFIG_SYS_BANK4_ENABLE    0
+#define CONFIG_SYS_BANK5_START	    0x3ff00000
+#define CONFIG_SYS_BANK5_END	    0x3fffffff
+#define CONFIG_SYS_BANK5_ENABLE    0
+#define CONFIG_SYS_BANK6_START	    0x3ff00000
+#define CONFIG_SYS_BANK6_END	    0x3fffffff
+#define CONFIG_SYS_BANK6_ENABLE    0
+#define CONFIG_SYS_BANK7_START	    0x3ff00000
+#define CONFIG_SYS_BANK7_END	    0x3fffffff
+#define CONFIG_SYS_BANK7_ENABLE    0
+
+#define CONFIG_SYS_ODCR	    0xff
+
+#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT	64	/* Max number of sectors per flash	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* Max number of flash banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* Max number of sectors per flash	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
 
 
 	/* Warining: environment is not EMBEDDED in the U-Boot code.
@@ -288,9 +288,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SIZE	32
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /*
diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h
index 21475fb..cd910ea 100644
--- a/include/configs/MVBC_P.h
+++ b/include/configs/MVBC_P.h
@@ -32,21 +32,21 @@
 #define CONFIG_MPC5xxx	1
 #define CONFIG_MPC5200 	1
 
-#define CFG_MPC5XXX_CLKIN	33000000
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
 
 #define BOOTFLAG_COLD		0x01
 #define BOOTFLAG_WARM		0x02
 
 #define CONFIG_MISC_INIT_R	1
 
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SIZE	32
 #ifdef CONFIG_CMD_KGDB
-#define CFG_CACHELINE_SHIFT	5
+#define CONFIG_SYS_CACHELINE_SHIFT	5
 #endif
 
 #define CONFIG_PSC_CONSOLE	1
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200, 230400}
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200, 230400}
 
 #define CONFIG_PCI		1
 #define CONFIG_PCI_PNP		1
@@ -61,7 +61,7 @@
 #define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
 #define CONFIG_PCI_IO_SIZE	0x01000000
 
-#define CFG_XLB_PIPELINING	1
+#define CONFIG_SYS_XLB_PIPELINING	1
 #define CONFIG_HIGH_BATS	1
 
 #define MV_CI			mvBlueCOUGAR-P
@@ -190,33 +190,33 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBCLK_EQUALS_XLBCLK
-#define CFG_PCICLK_EQUALS_IPBCLK_DIV2
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
+#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
 
 /*
  * Flash configuration
  */
 #undef 	CONFIG_FLASH_16BIT
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI_AMD_RESET 1
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
-#define CFG_FLASH_ERASE_TOUT	50000
-#define CFG_FLASH_WRITE_TOUT	1000
+#define CONFIG_SYS_FLASH_ERASE_TOUT	50000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000
 
-#define CFG_MAX_FLASH_BANKS	1
-#define CFG_MAX_FLASH_SECT	256
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
 
-#define CFG_LOWBOOT
-#define CFG_FLASH_BASE		TEXT_BASE
-#define CFG_FLASH_SIZE		0x00800000
+#define CONFIG_SYS_LOWBOOT
+#define CONFIG_SYS_FLASH_BASE		TEXT_BASE
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
 
 /*
  * Environment settings
  */
 #define CONFIG_ENV_IS_IN_FLASH
-#undef	CFG_FLASH_PROTECTION
+#undef	CONFIG_SYS_FLASH_PROTECTION
 
 #define CONFIG_ENV_ADDR		0xFFFE0000
 #define CONFIG_ENV_SIZE		0x10000
@@ -227,26 +227,26 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
 
-#define CFG_GBL_DATA_SIZE	128
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT		1
 #endif
 
-/* CFG_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CFG_MONITOR_LEN		(512 << 10)
-#define CFG_MALLOC_LEN		(512 << 10)
-#define CFG_BOOTMAPSZ		(8 << 20)
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
 
 /*
  * Ethernet configuration
@@ -263,52 +263,52 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_HUSH_PARSER
+#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_CMDLINE_EDITING
-#define CFG_PROMPT_HUSH_PS2 	"> "
-#undef 	CFG_LONGHELP
-#define CFG_PROMPT		"=> "
+#define CONFIG_SYS_PROMPT_HUSH_PS2 	"> "
+#undef 	CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"=> "
 #ifdef CONFIG_CMD_KGDB
-#define CFG_CBSIZE		1024
+#define CONFIG_SYS_CBSIZE		1024
 #else
-#define CFG_CBSIZE		256
+#define CONFIG_SYS_CBSIZE		256
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS		16
-#define CFG_BARGSIZE		CFG_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
-#define CFG_MEMTEST_START	0x00800000
-#define CFG_MEMTEST_END		0x02f00000
+#define CONFIG_SYS_MEMTEST_START	0x00800000
+#define CONFIG_SYS_MEMTEST_END		0x02f00000
 
-#define CFG_HZ			1000
+#define CONFIG_SYS_HZ			1000
 
 /* default load address */
-#define CFG_LOAD_ADDR		0x02000000
+#define CONFIG_SYS_LOAD_ADDR		0x02000000
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR 	0x00200000
 
 /*
  * Various low-level settings
  */
-#define CFG_GPS_PORT_CONFIG	0x20000004
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x20000004
 
-#define CFG_HID0_INIT		(HID0_ICE | HID0_ICFI)
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		(HID0_ICE | HID0_ICFI)
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x00047800
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047800
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
-#define CFG_CS_BURST		0x000000f0
-#define CFG_CS_DEADCYCLE	0x33333303
+#define CONFIG_SYS_CS_BURST		0x000000f0
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333303
 
-#define CFG_RESET_ADDRESS	0x00000100
+#define CONFIG_SYS_RESET_ADDRESS	0x00000100
 
 #undef FPGA_DEBUG
-#undef CFG_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGA		CFG_ALTERA_CYCLON2
+#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA		CONFIG_SYS_ALTERA_CYCLON2
 #define CONFIG_FPGA_ALTERA	1
 #define CONFIG_FPGA_CYCLON2	1
 #define CONFIG_FPGA_COUNT	1
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index ec36f55..4ecf806 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -37,7 +37,7 @@
 #define CONFIG_MPC834X	1
 #define CONFIG_MPC8343	1
 
-#define CFG_IMMR		0xE0000000
+#define CONFIG_SYS_IMMR		0xE0000000
 
 #define CONFIG_PCI
 #define CONFIG_83XX_GENERIC_PCI
@@ -54,94 +54,93 @@
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
-#define CFG_I2C_OFFSET		0x3000
-#define CFG_I2C2_OFFSET		0x3100
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
 
-#define CFG_I2C_SPEED		100000
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * DDR Setup
  */
-#define CFG_DDR_BASE		0x00000000
-#define CFG_SDRAM_BASE		CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
-#define CFG_83XX_DDR_USES_CS0	1
-#define CFG_MEMTEST_START	(60<<20)
-#define CFG_MEMTEST_END		(70<<20)
-
-#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+#define CONFIG_SYS_DDR_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_83XX_DDR_USES_CS0	1
+#define CONFIG_SYS_MEMTEST_START	(60<<20)
+#define CONFIG_SYS_MEMTEST_END		(70<<20)
+
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 
-#define CFG_DDR_SIZE		256
+#define CONFIG_SYS_DDR_SIZE		256
 
 /* HC, 75Ohm, DDR-II, DRQ */
-#define CFG_DDRCDR		0x80000001
+#define CONFIG_SYS_DDRCDR		0x80000001
 /* EN, ODT_WR, 3BA, 14row, 10col */
-#define CFG_DDR_CS0_CONFIG	0x80014102
-#define CFG_DDR_CS1_CONFIG	0x0
-#define CFG_DDR_CS2_CONFIG	0x0
-#define CFG_DDR_CS3_CONFIG	0x0
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014102
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x0
+#define CONFIG_SYS_DDR_CS2_CONFIG	0x0
+#define CONFIG_SYS_DDR_CS3_CONFIG	0x0
 
-#define CFG_DDR_CS0_BNDS	0x0000000f
-#define CFG_DDR_CS1_BNDS	0x0
-#define CFG_DDR_CS2_BNDS	0x0
-#define CFG_DDR_CS3_BNDS	0x0
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000f
+#define CONFIG_SYS_DDR_CS1_BNDS	0x0
+#define CONFIG_SYS_DDR_CS2_BNDS	0x0
+#define CONFIG_SYS_DDR_CS3_BNDS	0x0
 
-#define CFG_DDR_CLK_CNTL	0x02000000
+#define CONFIG_SYS_DDR_CLK_CNTL	0x02000000
 
-#define CFG_DDR_TIMING_0	0x00260802
-#define CFG_DDR_TIMING_1	0x2625b221
-#define CFG_DDR_TIMING_2	0x1f9820c7
-#define CFG_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	0x00260802
+#define CONFIG_SYS_DDR_TIMING_1	0x2625b221
+#define CONFIG_SYS_DDR_TIMING_2	0x1f9820c7
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
 
 /* ~MEM_EN, SREN, DDR-II, 32_BE */
-#define CFG_DDR_SDRAM_CFG	0x43080000
-#define CFG_DDR_SDRAM_CFG2	0x00401000
-#define CFG_DDR_INTERVAL	0x04060100
+#define CONFIG_SYS_DDR_SDRAM_CFG	0x43080000
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#define CONFIG_SYS_DDR_INTERVAL	0x04060100
 
-#define CFG_DDR_MODE		0x078e0232
+#define CONFIG_SYS_DDR_MODE		0x078e0232
 
 /* Flash */
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-
-#define CFG_FLASH_BASE		0xFF800000
-#define CFG_FLASH_SIZE		8
-#define CFG_FLASH_SIZE_SHIFT	3
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_ERASE_TOUT	60000
-#define CFG_FLASH_WRITE_TOUT	500
-#define CFG_MAX_FLASH_BANKS	1
-#define CFG_MAX_FLASH_SECT	256
-
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_PS_16 | BR_V)
-#define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM |  \
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_BASE		0xFF800000
+#define CONFIG_SYS_FLASH_SIZE		8
+#define CONFIG_SYS_FLASH_SIZE_SHIFT	3
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR0_PRELIM		((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM |  \
 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\
 				OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \
 				OR_GPCM_EAD)
-#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE
-#define CFG_LBLAWAR0_PRELIM	(LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT))
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
 
 /*
  * U-Boot memory configuration
  */
-#define CFG_MONITOR_BASE	TEXT_BASE
-#undef	CFG_RAMBOOT
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#undef	CONFIG_SYS_RAMBOOT
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK
-#define CFG_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/
 
-#define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-/* CFG_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CFG_MONITOR_LEN		(512 * 1024)
-#define CFG_MALLOC_LEN		(512 * 1024)
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
 
 /*
  * Local Bus LCRR and LBCR regs
@@ -149,32 +148,32 @@
  * External Local Bus rate is
  *  CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CFG_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
-#define CFG_LBC_LBCR	0x00000000
+#define CONFIG_SYS_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LBC_LBCR	0x00000000
 
 /* LB sdram refresh timer, about 6us */
-#define CFG_LBC_LSRT	0x32000000
+#define CONFIG_SYS_LBC_LSRT	0x32000000
 /* LB refresh timer prescal, 266MHz/32*/
-#define CFG_LBC_MRTPR	0x20000000
+#define CONFIG_SYS_LBC_MRTPR	0x20000000
 
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 
 #define CONFIG_CONSOLE		ttyS0
 #define CONFIG_BAUDRATE		115200
 
-#define CFG_NS16550_COM1	(CFG_IMMR + 0x4500)
-#define CFG_NS16550_COM2	(CFG_IMMR + 0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
 
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT		1
@@ -185,15 +184,15 @@
 /*
  * PCI
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x10000000
-#define CFG_PCI1_MMIO_BASE	(CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE)
-#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
-#define CFG_PCI1_MMIO_SIZE	0x10000000
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xE2000000
-#define CFG_PCI1_IO_SIZE	0x01000000
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCI1_MMIO_BASE	(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000
+#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000
 
 #define _IO_BASE		0x00000000
 
@@ -207,9 +206,9 @@
 
 /* TSEC */
 #define CONFIG_GMII
-#define CFG_VSC8601_SKEWFIX
-#define	CFG_VSC8601_SKEW_TX	3
-#define	CFG_VSC8601_SKEW_RX	3
+#define CONFIG_SYS_VSC8601_SKEWFIX
+#define	CONFIG_SYS_VSC8601_SKEW_TX	3
+#define	CONFIG_SYS_VSC8601_SKEW_RX	3
 
 #define CONFIG_TSEC1
 #define CONFIG_TSEC2
@@ -217,8 +216,8 @@
 #define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME	"TSEC0"
 #define CONFIG_FEC1_PHY_NORXERR
-#define CFG_TSEC1_OFFSET	0x24000
-#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1		(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 #define TSEC1_PHY_ADDR		0x10
 #define TSEC1_PHYIDX		0
 #define TSEC1_FLAGS		(TSEC_GIGABIT|TSEC_REDUCED)
@@ -226,8 +225,8 @@
 #define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME  	"TSEC1"
 #define CONFIG_FEC2_PHY_NORXERR
-#define CFG_TSEC2_OFFSET	0x25000
-#define CFG_TSEC2 		(CFG_IMMR+CFG_TSEC2_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2 		(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 #define TSEC2_PHY_ADDR		0x11
 #define TSEC2_PHYIDX		0
 #define TSEC2_FLAGS		(TSEC_GIGABIT|TSEC_REDUCED)
@@ -252,7 +251,7 @@
 /*
  * Environment
  */
-#undef  CFG_FLASH_PROTECTION
+#undef  CONFIG_SYS_FLASH_PROTECTION
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_ENV_IS_IN_FLASH	1
@@ -263,7 +262,7 @@
 #define CONFIG_ENV_SIZE_REDUND 	CONFIG_ENV_SIZE
 
 #define CONFIG_LOADS_ECHO
-#define CFG_LOADS_BAUD_CHANGE
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
 
 /*
  * Command line configuration.
@@ -286,102 +285,102 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP
+#define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
 /* default load address */
-#define CFG_LOAD_ADDR	0x2000000
+#define CONFIG_SYS_LOAD_ADDR	0x2000000
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR	0x200000
 
-#define CFG_PROMPT	"mvBL-M7> "
-#define CFG_CBSIZE	256
+#define CONFIG_SYS_PROMPT	"mvBL-M7> "
+#define CONFIG_SYS_CBSIZE	256
 
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS	16
-#define CFG_BARGSIZE	CFG_CBSIZE
-#define CFG_HZ		1000
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ		1000
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
-#define CFG_HRCW_LOW	0x0
-#define CFG_HRCW_HIGH	0x0
+#define CONFIG_SYS_HRCW_LOW	0x0
+#define CONFIG_SYS_HRCW_HIGH	0x0
 
 /*
  * System performance
  */
-#define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
-#define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
-#define CFG_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
-#define CFG_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
+#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
+#define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
+#define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
 
 /* clocking */
-#define CFG_SCCR_ENCCM		0
-#define CFG_SCCR_USBMPHCM	0
-#define	CFG_SCCR_USBDRCM	2
-#define CFG_SCCR_TSEC1CM	1
-#define CFG_SCCR_TSEC2CM	1
+#define CONFIG_SYS_SCCR_ENCCM		0
+#define CONFIG_SYS_SCCR_USBMPHCM	0
+#define	CONFIG_SYS_SCCR_USBDRCM	2
+#define CONFIG_SYS_SCCR_TSEC1CM	1
+#define CONFIG_SYS_SCCR_TSEC2CM	1
 
-#define CFG_SICRH	0x1fff8003
-#define CFG_SICRL	(SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
+#define CONFIG_SYS_SICRH	0x1fff8003
+#define CONFIG_SYS_SICRL	(SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
 
-#define CFG_HID0_INIT	0x000000000
-#define CFG_HID0_FINAL	CFG_HID0_INIT
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	CONFIG_SYS_HID0_INIT
 
-#define CFG_HID2	HID2_HBE
+#define CONFIG_SYS_HID2	HID2_HBE
 #define CONFIG_HIGH_BATS	1
 
 /* DDR  */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* PCI  */
-#define CFG_IBAT1L	(CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT2L	(CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
 				BATL_GUARDEDSTORAGE)
-#define CFG_IBAT2U	(CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* no PCI2 */
-#define CFG_IBAT3L	0
-#define CFG_IBAT3U	0
-#define CFG_IBAT4L	0
-#define CFG_IBAT4U	0
+#define CONFIG_SYS_IBAT3L	0
+#define CONFIG_SYS_IBAT3U	0
+#define CONFIG_SYS_IBAT4L	0
+#define CONFIG_SYS_IBAT4U	0
 
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CFG_IBAT5L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \
 				BATL_GUARDEDSTORAGE)
-#define CFG_IBAT5U	(CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
-#define CFG_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT7L	0
-#define CFG_IBAT7U	0
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
-#define CFG_DBAT4L	CFG_IBAT4L
-#define CFG_DBAT4U	CFG_IBAT4U
-#define CFG_DBAT5L	CFG_IBAT5L
-#define CFG_DBAT5U	CFG_IBAT5U
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT7L	0
+#define CONFIG_SYS_IBAT7U	0
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 
 /*
  * Internal Definitions
@@ -475,7 +474,7 @@
 	""
 
 #define CONFIG_FPGA_COUNT	1
-#define CONFIG_FPGA		CFG_ALTERA_CYCLON2
+#define CONFIG_FPGA		CONFIG_SYS_ALTERA_CYCLON2
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 
diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h
index 2518dbe..79c2069 100644
--- a/include/configs/MVBLUE.h
+++ b/include/configs/MVBLUE.h
@@ -63,7 +63,7 @@
 
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOT_RETRY_TIME	-1
@@ -85,7 +85,7 @@
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ECHO
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_IMI
 #define CONFIG_CMD_IRQ
@@ -117,14 +117,14 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS	16		/* Max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00100000	/* Default load address			*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16		/* Max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address			*/
 
 #define CONFIG_BOOTCOMMAND	"run nfsboot"
 #define CONFIG_BOOTARGS			"root=/dev/mtdblock5 ro rootfstype=jffs2"
@@ -168,54 +168,54 @@
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE	    0x00000000
+#define CONFIG_SYS_SDRAM_BASE	    0x00000000
 
-#define CFG_FLASH_BASE      0xFFF00000
-#define CFG_MONITOR_BASE    TEXT_BASE
+#define CONFIG_SYS_FLASH_BASE      0xFFF00000
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
 
-#define CFG_RESET_ADDRESS   0xFFF00100
-#define CFG_EUMB_ADDR	    0xFC000000
+#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
+#define CONFIG_SYS_EUMB_ADDR	    0xFC000000
 
-#define CFG_MONITOR_LEN     0x00100000
-#define CFG_MALLOC_LEN      (512 << 10) /* Reserve some kB for malloc()  */
+#define CONFIG_SYS_MONITOR_LEN     0x00100000
+#define CONFIG_SYS_MALLOC_LEN      (512 << 10) /* Reserve some kB for malloc()  */
 
-#define CFG_MEMTEST_START   0x00100000	/* memtest works on		*/
-#define CFG_MEMTEST_END	    0x00800000	/* 1M ... 8M in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START   0x00100000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END	    0x00800000	/* 1M ... 8M in DRAM		*/
 
 /* Maximum amount of RAM.  */
-#define CFG_MAX_RAM_SIZE    0x10000000	/* 0 .. 256MB of (S)DRAM */
+#define CONFIG_SYS_MAX_RAM_SIZE    0x10000000	/* 0 .. 256MB of (S)DRAM */
 
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#undef CFG_RAMBOOT
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#undef CONFIG_SYS_RAMBOOT
 #else
-#define CFG_RAMBOOT
+#define CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_ISA_IO      0xFE000000
+#define CONFIG_SYS_ISA_IO      0xFE000000
 
 /*
  * serial configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
 
-#define CFG_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_REG_SIZE    1
 
-#define CFG_NS16550_CLK     get_bus_freq(0)
+#define CONFIG_SYS_NS16550_CLK     get_bus_freq(0)
 
-#define CFG_NS16550_COM1    (CFG_EUMB_ADDR + 0x4500)
-#define CFG_NS16550_COM2    (CFG_EUMB_ADDR + 0x4600)
+#define CONFIG_SYS_NS16550_COM1    (CONFIG_SYS_EUMB_ADDR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2    (CONFIG_SYS_EUMB_ADDR + 0x4600)
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area
  */
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_SIZE     128
-#define CFG_GBL_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_END      0x1000
+#define CONFIG_SYS_GBL_DATA_SIZE     128
+#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 /*
  * Low Level Configuration Settings
@@ -225,35 +225,35 @@
  */
 
 #define CONFIG_SYS_CLK_FREQ  33000000
-#define CFG_HZ			 10000
+#define CONFIG_SYS_HZ			 10000
 
 /* Bit-field values for MCCR1.  */
-#define CFG_ROMNAL      7
-#define CFG_ROMFAL      11
+#define CONFIG_SYS_ROMNAL      7
+#define CONFIG_SYS_ROMFAL      11
 
 /* Bit-field values for MCCR2.  */
-#define CFG_TSWAIT      0x5
-#define CFG_REFINT      430
+#define CONFIG_SYS_TSWAIT      0x5
+#define CONFIG_SYS_REFINT      430
 
 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.  */
-#define CFG_BSTOPRE     121
+#define CONFIG_SYS_BSTOPRE     121
 
 /* Bit-field values for MCCR3.  */
-#define CFG_REFREC      8
+#define CONFIG_SYS_REFREC      8
 
 /* Bit-field values for MCCR4.  */
-#define CFG_PRETOACT    3
-#define CFG_ACTTOPRE    5
-#define CFG_ACTORW      3
-#define CFG_SDMODE_CAS_LAT  3
-#define CFG_REGISTERD_TYPE_BUFFER 1
-#define CFG_EXTROM      1
-#define CFG_REGDIMM     0
-#define CFG_DBUS_SIZE2  1
-#define CFG_SDMODE_WRAP 0
-
-#define CFG_PGMAX       0x32
-#define CFG_SDRAM_DSCD  0x20
+#define CONFIG_SYS_PRETOACT    3
+#define CONFIG_SYS_ACTTOPRE    5
+#define CONFIG_SYS_ACTORW      3
+#define CONFIG_SYS_SDMODE_CAS_LAT  3
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
+#define CONFIG_SYS_EXTROM      1
+#define CONFIG_SYS_REGDIMM     0
+#define CONFIG_SYS_DBUS_SIZE2  1
+#define CONFIG_SYS_SDMODE_WRAP 0
+
+#define CONFIG_SYS_PGMAX       0x32
+#define CONFIG_SYS_SDRAM_DSCD  0x20
 
 /* Memory bank settings.
  * Only bits 20-29 are actually used from these vales to set the
@@ -262,70 +262,70 @@
  * address. Refer to the MPC8240 book.
  */
 
-#define CFG_BANK0_START	    0x00000000
-#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START     0x3ff00000
-#define CFG_BANK1_END       0x3fffffff
-#define CFG_BANK1_ENABLE    0
-#define CFG_BANK2_START     0x3ff00000
-#define CFG_BANK2_END       0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START     0x3ff00000
-#define CFG_BANK3_END       0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START     0x3ff00000
-#define CFG_BANK4_END       0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START     0x3ff00000
-#define CFG_BANK5_END       0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START     0x3ff00000
-#define CFG_BANK6_END       0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START     0x3ff00000
-#define CFG_BANK7_END       0x3fffffff
-#define CFG_BANK7_ENABLE    0
-
-#define CFG_ODCR	    0xff
-
-#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L  CFG_IBAT0L
-#define CFG_DBAT0U  CFG_IBAT0U
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-#define CFG_DBAT2L  CFG_IBAT2L
-#define CFG_DBAT2U  CFG_IBAT2U
-#define CFG_DBAT3L  CFG_IBAT3L
-#define CFG_DBAT3U  CFG_IBAT3U
+#define CONFIG_SYS_BANK0_START	    0x00000000
+#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE    1
+#define CONFIG_SYS_BANK1_START     0x3ff00000
+#define CONFIG_SYS_BANK1_END       0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE    0
+#define CONFIG_SYS_BANK2_START     0x3ff00000
+#define CONFIG_SYS_BANK2_END       0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE    0
+#define CONFIG_SYS_BANK3_START     0x3ff00000
+#define CONFIG_SYS_BANK3_END       0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE    0
+#define CONFIG_SYS_BANK4_START     0x3ff00000
+#define CONFIG_SYS_BANK4_END       0x3fffffff
+#define CONFIG_SYS_BANK4_ENABLE    0
+#define CONFIG_SYS_BANK5_START     0x3ff00000
+#define CONFIG_SYS_BANK5_END       0x3fffffff
+#define CONFIG_SYS_BANK5_ENABLE    0
+#define CONFIG_SYS_BANK6_START     0x3ff00000
+#define CONFIG_SYS_BANK6_END       0x3fffffff
+#define CONFIG_SYS_BANK6_ENABLE    0
+#define CONFIG_SYS_BANK7_START     0x3ff00000
+#define CONFIG_SYS_BANK7_END       0x3fffffff
+#define CONFIG_SYS_BANK7_ENABLE    0
+
+#define CONFIG_SYS_ODCR	    0xff
+
+#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#undef  CFG_FLASH_PROTECTION
-#define CFG_MAX_FLASH_BANKS		1	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT		63	/* Max number of sectors per flash	*/
+#undef  CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS		1	/* Max number of flash banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT		63	/* Max number of sectors per flash	*/
 
-#define CFG_FLASH_ERASE_TOUT	12000
-#define CFG_FLASH_WRITE_TOUT	1000
+#define CONFIG_SYS_FLASH_ERASE_TOUT	12000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000
 
 
 #define CONFIG_ENV_IS_IN_FLASH
@@ -337,9 +337,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SIZE	32
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /*
diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h
index da8231c..10210f0 100644
--- a/include/configs/MVS1.h
+++ b/include/configs/MVS1.h
@@ -58,7 +58,7 @@
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #define	CONFIG_WATCHDOG			/* watchdog disabled/enabled	*/
 
@@ -92,7 +92,7 @@
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_BOOTD
 #define CONFIG_CMD_RUN
 
@@ -100,31 +100,31 @@
 /*
  * Miscellaneous configurable options
  */
-#undef	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#undef	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
-#undef	CFG_HUSH_PARSER			/* Hush parse for U-Boot ?? */
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef	CONFIG_SYS_HUSH_PARSER			/* Hush parse for U-Boot ?? */
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -134,45 +134,45 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
 
-#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 192 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 192 kB for Monitor	*/
 
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip (for AMD320DB chip)	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip (for AMD320DB chip)	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 
@@ -183,9 +183,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -195,10 +195,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 	     SYPCR_SWE	| SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -206,27 +206,27 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR  (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR  (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -235,7 +235,7 @@
  * interrupt status bit
  *
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -244,7 +244,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS     | \
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -254,14 +254,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -274,30 +274,30 @@
 #undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		0	/* max. no. of IDE buses			*/
-#define CFG_IDE_MAXDEVICE	0	/* max. no. of drives per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		0	/* max. no. of IDE buses			*/
+#define CONFIG_SYS_IDE_MAXDEVICE	0	/* max. no. of drives per IDE bus	*/
 
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -312,33 +312,33 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 
 /*
  * FLASH timing:
  */
 /* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
 /*
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
 				 OR_SCY_5_CLK | OR_EHTR)
 */
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 #ifdef CONFIG_MVS_16BIT_FLASH
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 #else
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
 #endif
 
-#undef CFG_OR1_REMAP
-#undef CFG_OR1_PRELIM
-#undef CFG_BR1_PRELIM
+#undef CONFIG_SYS_OR1_REMAP
+#undef CONFIG_SYS_OR1_PRELIM
+#undef CONFIG_SYS_BR1_PRELIM
 /*
  * BR2/3 and OR2/3 (SDRAM)
  *
@@ -348,13 +348,13 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
-#undef CFG_OR3_PRELIM
-#undef CFG_BR3_PRELIM
+#undef CONFIG_SYS_OR3_PRELIM
+#undef CONFIG_SYS_BR3_PRELIM
 
 
 /*
@@ -383,26 +383,26 @@
  * 66 Mhz => 66.000.000 / Divider = 129
  * 80 Mhz => 80.000.000 / Divider = 156
  */
-#define CFG_MAMR_PTA		 98
+#define CONFIG_SYS_MAMR_PTA		 98
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
index 7d90e16..c9589bd 100644
--- a/include/configs/MigoR.h
+++ b/include/configs/MigoR.h
@@ -40,7 +40,7 @@
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_DFL
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTDELAY	3
@@ -58,90 +58,90 @@
 #define MIGO_R_FLASH_BASE_1	(0xA0000000)
 #define MIGO_R_FLASH_BANK_SIZE	(64 * 1024 * 1024)
 
-#define CFG_LONGHELP			/* undef to save memory	*/
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
-#define CFG_CBSIZE		256		/* Buffer size for input from the Console */
-#define CFG_PBSIZE		256		/* Buffer size for Console output */
-#define CFG_MAXARGS		16		/* max args accepted for monitor commands */
-#define CFG_BARGSIZE	512		/* Buffer size for Boot Arguments passed to kernel */
-#define CFG_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		256		/* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE		256		/* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS		16		/* max args accepted for monitor commands */
+#define CONFIG_SYS_BARGSIZE	512		/* Buffer size for Boot Arguments passed to kernel */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */
 
 /* SCIF */
 #define CONFIG_SCIF_CONSOLE	1
 #define CONFIG_CONS_SCIF0	1
-#undef  CFG_CONSOLE_INFO_QUIET	/* Suppress display of console
+#undef  CONFIG_SYS_CONSOLE_INFO_QUIET	/* Suppress display of console
 								   information at boot */
-#undef  CFG_CONSOLE_OVERWRITE_ROUTINE
-#undef  CFG_CONSOLE_ENV_OVERWRITE
+#undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 
-#define CFG_MEMTEST_START	(MIGO_R_SDRAM_BASE)
-#define CFG_MEMTEST_END		(CFG_MEMTEST_START + (60 * 1024 * 1024))
+#define CONFIG_SYS_MEMTEST_START	(MIGO_R_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
 
 /* Enable alternate, more extensive, memory test */
-#undef  CFG_ALT_MEMTEST
+#undef  CONFIG_SYS_ALT_MEMTEST
 /* Scratch address used by the alternate memory test */
-#undef  CFG_MEMTEST_SCRATCH
+#undef  CONFIG_SYS_MEMTEST_SCRATCH
 
 /* Enable temporary baudrate change while serial download */
-#undef  CFG_LOADS_BAUD_CHANGE
+#undef  CONFIG_SYS_LOADS_BAUD_CHANGE
 
-#define CFG_SDRAM_BASE	(MIGO_R_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_BASE	(MIGO_R_SDRAM_BASE)
 /* maybe more, but if so u-boot doesn't know about it... */
-#define CFG_SDRAM_SIZE	(64 * 1024 * 1024)
+#define CONFIG_SYS_SDRAM_SIZE	(64 * 1024 * 1024)
 /* default load address for scripts ?!? */
-#define CFG_LOAD_ADDR	(CFG_SDRAM_BASE + 16 * 1024 * 1024)
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
 
 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
-#define CFG_MONITOR_BASE	(MIGO_R_FLASH_BASE_1)
+#define CONFIG_SYS_MONITOR_BASE	(MIGO_R_FLASH_BASE_1)
 /* Monitor size */
-#define CFG_MONITOR_LEN	(128 * 1024)
+#define CONFIG_SYS_MONITOR_LEN	(128 * 1024)
 /* Size of DRAM reserved for malloc() use */
-#define CFG_MALLOC_LEN	(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_SIZE	(256)
-#define CFG_BOOTMAPSZ	(8 * 1024 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	(256)
+#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
 
 /* FLASH */
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#undef  CFG_FLASH_QUIET_TEST
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
 /* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 /* Physical start address of Flash memory */
-#define CFG_FLASH_BASE	(MIGO_R_FLASH_BASE_1)
+#define CONFIG_SYS_FLASH_BASE	(MIGO_R_FLASH_BASE_1)
 /* Max number of sectors on each Flash chip */
-#define CFG_MAX_FLASH_SECT	512
+#define CONFIG_SYS_MAX_FLASH_SECT	512
 
 /* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
-#define CFG_MAX_FLASH_BANKS	1
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
 
 /* Timeout for Flash erase operations (in ms) */
-#define CFG_FLASH_ERASE_TOUT	(3 * 1000)
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
 /* Timeout for Flash write operations (in ms) */
-#define CFG_FLASH_WRITE_TOUT	(3 * 1000)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
 /* Timeout for Flash set sector lock bit operations (in ms) */
-#define CFG_FLASH_LOCK_TOUT	(3 * 1000)
+#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
 /* Timeout for Flash clear lock bit operations (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	(3 * 1000)
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
 
 /* Use hardware flash sectors protection instead of U-Boot software protection */
-#undef  CFG_FLASH_PROTECTION
-#undef  CFG_DIRECT_FLASH_TFTP
+#undef  CONFIG_SYS_FLASH_PROTECTION
+#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
 
 /* ENV setting */
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_OVERWRITE	1
 #define CONFIG_ENV_SECT_SIZE	(128 * 1024)
 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN)
-/* Offset of env Flash sector relative to CFG_FLASH_BASE */
-#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CFG_FLASH_BASE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
+#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
 #define TMU_CLK_DIVIDER		(4)	/* 4 (default), 16, 64, 256 or 1024 */
-#define CFG_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
 
 #endif	/* __MIGO_R_H */
diff --git a/include/configs/NC650.h b/include/configs/NC650.h
index 3e64a7e..0b97f0c 100644
--- a/include/configs/NC650.h
+++ b/include/configs/NC650.h
@@ -55,15 +55,15 @@
 /*
  * 15 MHz - CPU minimum clock
  */
-#define CFG_8xx_CPUCLK_MIN		15000000
+#define CONFIG_SYS_8xx_CPUCLK_MIN		15000000
 
 /*
  * 133 MHz - CPU maximum clock
  */
-#define CFG_8xx_CPUCLK_MAX		133000000
+#define CONFIG_SYS_8xx_CPUCLK_MAX		133000000
 
-#define CFG_MEASURE_CPUCLK
-#define CFG_8XX_XIN			CONFIG_8xx_OSCLK
+#define CONFIG_SYS_MEASURE_CPUCLK
+#define CONFIG_SYS_8XX_XIN			CONFIG_8xx_OSCLK
 
 #define CONFIG_BOOTDELAY		5	/* autoboot after 5 seconds	*/
 #define CONFIG_AUTOBOOT_KEYED
@@ -99,14 +99,14 @@
 #define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
 #define FEC_ENET
 #define CONFIG_MII
-#define CFG_DISCOVER_PHY	1
+#define CONFIG_SYS_DISCOVER_PHY	1
 
 
 /* enable I2C and select the hardware/software driver */
 #undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		100000	/* 100 kHz			*/
-#define CFG_I2C_SLAVE		0x7f
+#define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz			*/
+#define CONFIG_SYS_I2C_SLAVE		0x7f
 
 /*
  * Software (bit-bang) I2C driver configuration
@@ -141,7 +141,7 @@
 #define	I2C_TRISTATE	{ __I2C_DIR &= ~SDA; }
 
 #define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR		0x51
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
 
 
 /*
@@ -162,25 +162,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x00100000
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -190,46 +190,46 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xF0000000
-#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+#define CONFIG_SYS_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR_SIZE		((uint)(64 * 1024))
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
 
-#define CFG_RESET_ADDRESS	0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
@@ -241,16 +241,15 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*
  * NAND flash support
  */
-#define CFG_MAX_NAND_DEVICE	1
-#define NAND_MAX_CHIPS		1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
 
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control					11-9
@@ -259,31 +258,31 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration					11-6
  *-----------------------------------------------------------------------
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control					11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -292,7 +291,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00	| SCCR_DFSYNC00	| \
+#define CONFIG_SYS_SCCR	(SCCR_COM00	| SCCR_DFSYNC00	| \
 			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
 			 SCCR_DFLCD000	| SCCR_DFALCD00)
 
@@ -301,7 +300,7 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER		0
+#define CONFIG_SYS_DER		0
 
 /*
  * Init Memory Controller:
@@ -311,29 +310,29 @@
 
 #define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
 
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /* FLASH timing: Default value of OR0 after reset */
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_MSK | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_MSK | OR_BI | \
 				 OR_SCY_15_CLK | OR_TRLX)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
 
 /*
  * BR2 and OR2 (NAND Flash) - addressed through UPMB on rev 1
  * rev2 only uses the chipselect
  */
-#define CFG_NAND_BASE		0x50000000
-#define CFG_NAND_SIZE		0x04000000
+#define CONFIG_SYS_NAND_BASE		0x50000000
+#define CONFIG_SYS_NAND_SIZE		0x04000000
 
-#define CFG_OR_TIMING_NAND	(OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_NAND	(OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
 				 OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
 
-#define CFG_BR2_PRELIM  ((CFG_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V  )
-#define CFG_OR2_PRELIM  (((-CFG_NAND_SIZE) & OR_AM_MSK) | OR_BI )
+#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V  )
+#define CONFIG_SYS_OR2_PRELIM  (((-CONFIG_SYS_NAND_SIZE) & OR_AM_MSK) | OR_BI )
 
 /*
  * BR3 and OR3 (SDRAM)
@@ -344,41 +343,41 @@
  /*
   * SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)
   */
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR3_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+#define CONFIG_SYS_OR3_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM)
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 
 /*
  * BR4 and OR4 (CPLD)
  */
-#define CFG_CPLD_BASE           0x80000000      /* CPLD                 */
-#define CFG_CPLD_SIZE           0x10000         /* only 16 used         */
+#define CONFIG_SYS_CPLD_BASE           0x80000000      /* CPLD                 */
+#define CONFIG_SYS_CPLD_SIZE           0x10000         /* only 16 used         */
 
-#define CFG_OR_TIMING_CPLD	(OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_CPLD	(OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
 				 OR_SCY_1_CLK)
 
-#define CFG_BR4_PRELIM  ((CFG_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-#define CFG_OR4_PRELIM  (((-CFG_CPLD_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_CPLD)
+#define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR4_PRELIM  (((-CONFIG_SYS_CPLD_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_CPLD)
 
 /*
  * BR5 and OR5 (SRAM)
  */
-#define CFG_SRAM_BASE		0x60000000
-#define CFG_SRAM_SIZE		0x00080000
+#define CONFIG_SYS_SRAM_BASE		0x60000000
+#define CONFIG_SYS_SRAM_SIZE		0x00080000
 
-#define CFG_OR_TIMING_SRAM	(OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_SRAM	(OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
 				 OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
 
-#define CFG_BR5_PRELIM  ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-#define CFG_OR5_PRELIM  (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM)
+#define CONFIG_SYS_BR5_PRELIM  ((CONFIG_SYS_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR5_PRELIM  (((-CONFIG_SYS_SRAM_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_SRAM)
 
 #if defined(CONFIG_CP850)
 /*
  *  BR6 and OR6 (DPRAM) - only on CP850
  */
-#define CFG_OR6_PRELIM          0xffff8170
-#define CFG_BR6_PRELIM          0xa0000401
+#define CONFIG_SYS_OR6_PRELIM          0xffff8170
+#define CONFIG_SYS_BR6_PRELIM          0xa0000401
 #define DPRAM_BASE_ADDR         0xa0000000
 
 #define CONFIG_MISC_INIT_R      1
@@ -391,31 +390,31 @@
  * 4    Number of refresh cycles per period
  * 64   Refresh cycle in ms per number of rows
  */
-#define CFG_PTA_PER_CLK		((4096 * 64 * 1000) / (4 * 64))
+#define CONFIG_SYS_PTA_PER_CLK		((4096 * 64 * 1000) / (4 * 64))
 
 /*
  * Memory Periodic Timer Prescaler
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA		39
+#define CONFIG_SYS_MAMR_PTA		39
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
 			 MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
 			 MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 
@@ -423,7 +422,7 @@
  * MBMR settings for NAND flash
  */
 
-#define CFG_MBMR_NAND ( MBMR_WLFB_5X )
+#define CONFIG_SYS_MBMR_NAND ( MBMR_WLFB_5X )
 
 /*
  * Internal Definitions
diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h
index 7cc6364..2d04d89 100644
--- a/include/configs/NETPHONE.h
+++ b/include/configs/NETPHONE.h
@@ -73,7 +73,7 @@
 
 #define CONFIG_AUTOSCRIPT
 #define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -99,7 +99,7 @@
 
 #define	CONFIG_NET_MULTI	1	/* the only way to get the FEC in */
 #define	FEC_ENET		1	/* eth.c needs it that way... */
-#undef CFG_DISCOVER_PHY
+#undef CONFIG_SYS_DISCOVER_PHY
 #define CONFIG_MII		1
 #define CONFIG_MII_INIT		1
 #define CONFIG_RMII		1	/* use RMII interface */
@@ -133,29 +133,29 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#define CFG_HUSH_PARSER	1
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER	1
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0300000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -165,74 +165,74 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFF000000
+#define CONFIG_SYS_IMMR		0xFF000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
 #if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 #if CONFIG_NETPHONE_VERSION == 2
-#define CFG_FLASH_BASE4		0x40080000
+#define CONFIG_SYS_FLASH_BASE4		0x40080000
 #endif
 
-#define CFG_RESET_ADDRESS   0x80000000
+#define CONFIG_SYS_RESET_ADDRESS   0x80000000
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #if CONFIG_NETPHONE_VERSION == 1
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
 #elif CONFIG_NETPHONE_VERSION == 2
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
 #endif
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SECT_SIZE	0x10000
 
-#define	CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x60000)
+#define	CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x60000)
 #define CONFIG_ENV_OFFSET		0
 #define	CONFIG_ENV_SIZE		0x4000
 
-#define CONFIG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + 0x70000)
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + 0x70000)
 #define CONFIG_ENV_OFFSET_REDUND	0
 #define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -242,10 +242,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -254,9 +254,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -264,20 +264,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -290,27 +290,27 @@
 #if CONFIG_XIN == 10000000
 
 #if MPC8XX_HZ == 120000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 100000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 50000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 25000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 40000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 75000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #else
@@ -320,15 +320,15 @@
 #elif CONFIG_XIN == 50000000
 
 #if MPC8XX_HZ == 120000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 100000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ ==  66666666
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #else
@@ -353,12 +353,12 @@
 
 #define SCCR_MASK	SCCR_EBDF11
 #if MPC8XX_HZ > 66666666
-#define CFG_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00 | SCCR_EBDF01)
 #else
-#define CFG_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -369,8 +369,8 @@
  *-----------------------------------------------------------------------
  *
  */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -384,23 +384,23 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 
 #if CONFIG_NETPHONE_VERSION == 2
 
 #define FLASH_BASE4_PRELIM	0x40080000	/* FLASH bank #1	*/
 
-#define CFG_OR4_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR4_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR4_PRELIM	((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR4_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR4_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR4_PRELIM	((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 
 #endif
 
@@ -412,10 +412,10 @@
 #define	SDRAM_MAX_SIZE		(256 << 20)	/* max 256MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
+#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
 
-#define CFG_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
 
 /*
  * Memory Periodic Timer Prescaler
@@ -448,34 +448,34 @@
  * 80 Mhz => 80.000.000 / Divider = 156
  */
 
-#define CFG_MAMR_PTA		 234
+#define CONFIG_SYS_MAMR_PTA		 234
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
@@ -501,12 +501,12 @@
 
 /* NAND */
 #define CONFIG_NAND_LEGACY
-#define CFG_NAND_BASE		NAND_BASE
+#define CONFIG_SYS_NAND_BASE		NAND_BASE
 #define CONFIG_MTD_NAND_ECC_JFFS2
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_MTD_NAND_UNSAFE
 
-#define CFG_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
 
 #define SECTORSIZE		512
 #define ADDR_COLUMN		1
@@ -514,44 +514,43 @@
 #define ADDR_COLUMN_PAGE	3
 #define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS		1
-#define NAND_MAX_CHIPS		1
 
 /* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
 #define NAND_DISABLE_CE(nand) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 20)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 20)); \
 	} while(0)
 
 #define NAND_ENABLE_CE(nand) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
 	} while(0)
 
 #define NAND_CTL_CLRALE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
 	} while(0)
 
 #define NAND_CTL_SETALE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 17)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 17)); \
 	} while(0)
 
 #define NAND_CTL_CLRCLE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
 	} while(0)
 
 #define NAND_CTL_SETCLE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 18)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 18)); \
 	} while(0)
 
 #if CONFIG_NETPHONE_VERSION == 1
 #define NAND_WAIT_READY(nand) \
 	do { \
 		int _tries = 0; \
-		while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
+		while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
 			if (++_tries > 100000) \
 				break; \
 	} while (0)
@@ -559,7 +558,7 @@
 #define NAND_WAIT_READY(nand) \
 	do { \
 		int _tries = 0; \
-		while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
+		while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
 			if (++_tries > 100000) \
 				break; \
 	} while (0)
@@ -585,8 +584,8 @@
 
 /*****************************************************************************/
 
-#define CFG_DIRECT_FLASH_TFTP
-#define CFG_DIRECT_NAND_TFTP
+#define CONFIG_SYS_DIRECT_FLASH_TFTP
+#define CONFIG_SYS_DIRECT_NAND_TFTP
 
 /*****************************************************************************/
 
@@ -596,7 +595,7 @@
 #define STATUS_LED_BIT		0x00000080		/* bit 24 */
 #endif
 
-#define STATUS_LED_PERIOD	(CFG_HZ / 2)
+#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
 #define STATUS_LED_STATE	STATUS_LED_BLINKING
 
 #define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
@@ -611,15 +610,15 @@ typedef unsigned int led_id_t;
 
 #define __led_toggle(_msk) \
 	do { \
-		((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat ^= (_msk); \
+		((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \
 	} while(0)
 
 #define __led_set(_msk, _st) \
 	do { \
 		if ((_st)) \
-			((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat |= (_msk); \
+			((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \
 		else \
-			((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
+			((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
 	} while(0)
 
 #define __led_init(msk, st) __led_set(msk, st)
@@ -759,26 +758,26 @@ typedef unsigned int led_id_t;
 
 /* serial interfacing macros */
 
-#define SED156X_SPI_RXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define SED156X_SPI_RXD_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
 #define SED156X_SPI_RXD_MASK	0x00000008
 
-#define SED156X_SPI_TXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define SED156X_SPI_TXD_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
 #define SED156X_SPI_TXD_MASK	0x00000004
 
-#define SED156X_SPI_CLK_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define SED156X_SPI_CLK_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
 #define SED156X_SPI_CLK_MASK	0x00000002
 
-#define SED156X_CS_PORT		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define SED156X_CS_PORT		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
 #define SED156X_CS_MASK		0x00000010
 
-#define SED156X_A0_PORT		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
+#define SED156X_A0_PORT		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
 #define SED156X_A0_MASK		0x0020
 
 /*************************************************************************************************/
 
-#define CFG_CONSOLE_IS_IN_ENV		1
-#define CFG_CONSOLE_OVERWRITE_ROUTINE	1
-#define CFG_CONSOLE_ENV_OVERWRITE	1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE	1
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE	1
 
 /*************************************************************************************************/
 
@@ -791,7 +790,7 @@ typedef unsigned int led_id_t;
 
 /* phone console configuration */
 
-#define PHONE_CONSOLE_POLL_HZ		(CFG_HZ/200)	/* poll every 5ms */
+#define PHONE_CONSOLE_POLL_HZ		(CONFIG_SYS_HZ/200)	/* poll every 5ms */
 
 /*************************************************************************************************/
 
@@ -799,7 +798,7 @@ typedef unsigned int led_id_t;
 #define CONFIG_CDP_DEVICE_ID_PREFIX	"NP"	/* netphone */
 #define CONFIG_CDP_PORT_ID		"eth%d"
 #define CONFIG_CDP_CAPABILITIES		0x00000010
-#define CONFIG_CDP_VERSION		"u-boot" " " __DATE__ " " __TIME__
+#define CONFIG_CDP_VERSION		"u-boot" " " U_BOOT_DATE " " U_BOOT_TIME
 #define CONFIG_CDP_PLATFORM		"Intracom NetPhone"
 #define CONFIG_CDP_TRIGGER		0x20020001
 #define CONFIG_CDP_POWER_CONSUMPTION	4300	/* 90 mA @ 48V */
diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
index 805b82a..34fdba5 100644
--- a/include/configs/NETTA.h
+++ b/include/configs/NETTA.h
@@ -70,7 +70,7 @@
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 #define CONFIG_HW_WATCHDOG
@@ -95,7 +95,7 @@
 
 #define	CONFIG_NET_MULTI	1	/* the only way to get the FEC in */
 #define	FEC_ENET		1	/* eth.c needs it that way... */
-#undef  CFG_DISCOVER_PHY		/* do not discover phys */
+#undef  CONFIG_SYS_DISCOVER_PHY		/* do not discover phys */
 #define CONFIG_MII		1
 #define CONFIG_MII_INIT		1
 #define CONFIG_RMII		1	/* use RMII interface */
@@ -117,9 +117,9 @@
 #define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */
 
 /* POST support */
-#define CONFIG_POST		(CFG_POST_MEMORY   | \
-				 CFG_POST_CODEC	   | \
-				 CFG_POST_DSP	   )
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_CODEC	   | \
+				 CONFIG_SYS_POST_DSP	   )
 
 
 /*
@@ -146,29 +146,29 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#define CFG_HUSH_PARSER	1
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER	1
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0300000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -178,65 +178,65 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFF000000
+#define CONFIG_SYS_IMMR		0xFF000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
 #if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SECT_SIZE	0x10000
 
-#define	CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x60000)
+#define	CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x60000)
 #define CONFIG_ENV_OFFSET		0
 #define	CONFIG_ENV_SIZE		0x4000
 
-#define CONFIG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + 0x70000)
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + 0x70000)
 #define CONFIG_ENV_OFFSET_REDUND	0
 #define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -246,10 +246,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -258,9 +258,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -268,20 +268,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -294,27 +294,27 @@
 #if CONFIG_XIN == 10000000
 
 #if MPC8XX_HZ == 120000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 100000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 50000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 25000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 40000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 75000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #else
@@ -324,19 +324,19 @@
 #elif CONFIG_XIN == 50000000
 
 #if MPC8XX_HZ == 120000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 100000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ ==  80000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ ==  50000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #else
@@ -361,12 +361,12 @@
 
 #define SCCR_MASK	SCCR_EBDF11
 #if MPC8XX_HZ > 66666666
-#define CFG_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL111 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00 | SCCR_EBDF01)
 #else
-#define CFG_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL111 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -377,8 +377,8 @@
  *-----------------------------------------------------------------------
  *
  */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -392,15 +392,15 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 
 /*
  * BR3 and OR3 (SDRAM)
@@ -410,10 +410,10 @@
 #define	SDRAM_MAX_SIZE		(256 << 20)	/* max 256MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
+#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
 
-#define CFG_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
 
 /*
  * Memory Periodic Timer Prescaler
@@ -447,13 +447,13 @@
  */
 
 #if   MPC8XX_HZ == 120000000
-#define CFG_MAMR_PTA		 234
+#define CONFIG_SYS_MAMR_PTA		 234
 #elif MPC8XX_HZ == 100000000
-#define CFG_MAMR_PTA		 195
+#define CONFIG_SYS_MAMR_PTA		 195
 #elif MPC8XX_HZ ==  80000000
-#define CFG_MAMR_PTA		 156
+#define CONFIG_SYS_MAMR_PTA		 156
 #elif MPC8XX_HZ ==  50000000
-#define CFG_MAMR_PTA		  98
+#define CONFIG_SYS_MAMR_PTA		  98
 #else
 #error Unknown frequency
 #endif
@@ -464,27 +464,27 @@
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
@@ -620,11 +620,11 @@
 
 /* NAND */
 #define CONFIG_NAND_LEGACY
-#define CFG_NAND_BASE			NAND_BASE
+#define CONFIG_SYS_NAND_BASE			NAND_BASE
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_MTD_NAND_UNSAFE
 
-#define CFG_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
 /* #define NAND_NO_RB */
 
 #define SECTORSIZE		512
@@ -633,43 +633,42 @@
 #define ADDR_COLUMN_PAGE	3
 #define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS		1
-#define NAND_MAX_CHIPS		1
 
 /* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */
 #define NAND_DISABLE_CE(nand) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  (1 << (15 - 5)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |=  (1 << (15 - 5)); \
 	} while(0)
 
 #define NAND_ENABLE_CE(nand) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 5)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 5)); \
 	} while(0)
 
 #define NAND_CTL_CLRALE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 3)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 3)); \
 	} while(0)
 
 #define NAND_CTL_SETALE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  (1 << (15 - 3)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |=  (1 << (15 - 3)); \
 	} while(0)
 
 #define NAND_CTL_CLRCLE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 4)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 4)); \
 	} while(0)
 
 #define NAND_CTL_SETCLE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  (1 << (15 - 4)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |=  (1 << (15 - 4)); \
 	} while(0)
 
 #ifndef NAND_NO_RB
 #define NAND_WAIT_READY(nand) \
 	do { \
-		while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 13))) == 0) { \
+		while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 13))) == 0) { \
 			WATCHDOG_RESET(); \
 		} \
 	} while (0)
@@ -718,8 +717,8 @@
 
 /*****************************************************************************/
 
-#define CFG_DIRECT_FLASH_TFTP
-#define CFG_DIRECT_NAND_TFTP
+#define CONFIG_SYS_DIRECT_FLASH_TFTP
+#define CONFIG_SYS_DIRECT_NAND_TFTP
 
 /*****************************************************************************/
 
@@ -729,14 +728,14 @@
  *-----------------------------------------------------------------------
  */
 
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -749,21 +748,21 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -775,7 +774,7 @@
 #define CONFIG_CDP_DEVICE_ID_PREFIX	"NT"	/* netta */
 #define CONFIG_CDP_PORT_ID		"eth%d"
 #define CONFIG_CDP_CAPABILITIES		0x00000010
-#define CONFIG_CDP_VERSION		"u-boot 1.0" " " __DATE__ " " __TIME__
+#define CONFIG_CDP_VERSION		"u-boot 1.0" " " U_BOOT_DATE " " U_BOOT_TIME
 #define CONFIG_CDP_PLATFORM		"Intracom NetTA"
 #define CONFIG_CDP_TRIGGER		0x20020001
 #define CONFIG_CDP_POWER_CONSUMPTION	4300	/* 90 mA @ 48V */
diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h
index 687db1d..4a27027 100644
--- a/include/configs/NETTA2.h
+++ b/include/configs/NETTA2.h
@@ -73,7 +73,7 @@
 
 #define CONFIG_AUTOSCRIPT
 #define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -100,7 +100,7 @@
 
 #define	CONFIG_NET_MULTI	1	/* the only way to get the FEC in */
 #define	FEC_ENET		1	/* eth.c needs it that way... */
-#undef CFG_DISCOVER_PHY
+#undef CONFIG_SYS_DISCOVER_PHY
 #define CONFIG_MII		1
 #define CONFIG_MII_INIT		1
 #define CONFIG_RMII		1	/* use RMII interface */
@@ -134,29 +134,29 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#define CFG_HUSH_PARSER	1
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER	1
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0300000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -166,74 +166,74 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFF000000
+#define CONFIG_SYS_IMMR		0xFF000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
 #if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 #if CONFIG_NETTA2_VERSION == 2
-#define CFG_FLASH_BASE4		0x40080000
+#define CONFIG_SYS_FLASH_BASE4		0x40080000
 #endif
 
-#define CFG_RESET_ADDRESS   0x80000000
+#define CONFIG_SYS_RESET_ADDRESS   0x80000000
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #if CONFIG_NETTA2_VERSION == 1
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
 #elif CONFIG_NETTA2_VERSION == 2
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
 #endif
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SECT_SIZE	0x10000
 
-#define	CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x60000)
+#define	CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x60000)
 #define CONFIG_ENV_OFFSET		0
 #define	CONFIG_ENV_SIZE		0x4000
 
-#define CONFIG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + 0x70000)
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + 0x70000)
 #define CONFIG_ENV_OFFSET_REDUND	0
 #define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -243,10 +243,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -255,9 +255,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -265,20 +265,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -291,27 +291,27 @@
 #if CONFIG_XIN == 10000000
 
 #if MPC8XX_HZ == 120000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 100000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 50000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 25000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 40000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 75000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #else
@@ -321,15 +321,15 @@
 #elif CONFIG_XIN == 50000000
 
 #if MPC8XX_HZ == 120000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 100000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ ==  66666666
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #else
@@ -354,12 +354,12 @@
 
 #define SCCR_MASK	SCCR_EBDF11
 #if MPC8XX_HZ > 66666666
-#define CFG_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00 | SCCR_EBDF01)
 #else
-#define CFG_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -370,8 +370,8 @@
  *-----------------------------------------------------------------------
  *
  */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -385,23 +385,23 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 
 #if CONFIG_NETTA2_VERSION == 2
 
 #define FLASH_BASE4_PRELIM	0x40080000	/* FLASH bank #1	*/
 
-#define CFG_OR4_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR4_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR4_PRELIM	((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR4_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR4_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR4_PRELIM	((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 
 #endif
 
@@ -413,10 +413,10 @@
 #define	SDRAM_MAX_SIZE		(256 << 20)	/* max 256MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
+#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
 
-#define CFG_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
 
 /*
  * Memory Periodic Timer Prescaler
@@ -449,34 +449,34 @@
  * 80 Mhz => 80.000.000 / Divider = 156
  */
 
-#define CFG_MAMR_PTA		 234
+#define CONFIG_SYS_MAMR_PTA		 234
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
@@ -502,12 +502,12 @@
 
 /* NAND */
 #define CONFIG_NAND_LEGACY
-#define CFG_NAND_BASE		NAND_BASE
+#define CONFIG_SYS_NAND_BASE		NAND_BASE
 #define CONFIG_MTD_NAND_ECC_JFFS2
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_MTD_NAND_UNSAFE
 
-#define CFG_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
 
 #define SECTORSIZE		512
 #define ADDR_COLUMN		1
@@ -515,44 +515,43 @@
 #define ADDR_COLUMN_PAGE	3
 #define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS		1
-#define NAND_MAX_CHIPS		1
 
 /* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
 #define NAND_DISABLE_CE(nand) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 20)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 20)); \
 	} while(0)
 
 #define NAND_ENABLE_CE(nand) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
 	} while(0)
 
 #define NAND_CTL_CLRALE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
 	} while(0)
 
 #define NAND_CTL_SETALE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 17)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 17)); \
 	} while(0)
 
 #define NAND_CTL_CLRCLE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
 	} while(0)
 
 #define NAND_CTL_SETCLE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 18)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 18)); \
 	} while(0)
 
 #if CONFIG_NETTA2_VERSION == 1
 #define NAND_WAIT_READY(nand) \
 	do { \
 		int _tries = 0; \
-		while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
+		while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
 			if (++_tries > 100000) \
 				break; \
 	} while (0)
@@ -560,7 +559,7 @@
 #define NAND_WAIT_READY(nand) \
 	do { \
 		int _tries = 0; \
-		while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
+		while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
 			if (++_tries > 100000) \
 				break; \
 	} while (0)
@@ -586,8 +585,8 @@
 
 /*****************************************************************************/
 
-#define CFG_DIRECT_FLASH_TFTP
-#define CFG_DIRECT_NAND_TFTP
+#define CONFIG_SYS_DIRECT_FLASH_TFTP
+#define CONFIG_SYS_DIRECT_NAND_TFTP
 
 /*****************************************************************************/
 
@@ -597,7 +596,7 @@
 #define STATUS_LED_BIT		0x00000080		/* bit 24 */
 #endif
 
-#define STATUS_LED_PERIOD	(CFG_HZ / 2)
+#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
 #define STATUS_LED_STATE	STATUS_LED_BLINKING
 
 #define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
@@ -612,15 +611,15 @@ typedef unsigned int led_id_t;
 
 #define __led_toggle(_msk) \
 	do { \
-		((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat ^= (_msk); \
+		((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \
 	} while(0)
 
 #define __led_set(_msk, _st) \
 	do { \
 		if ((_st)) \
-			((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat |= (_msk); \
+			((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \
 		else \
-			((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
+			((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
 	} while(0)
 
 #define __led_init(msk, st) __led_set(msk, st)
@@ -734,9 +733,9 @@ typedef unsigned int led_id_t;
 
 **************************************************************************************************/
 
-#define CFG_CONSOLE_IS_IN_ENV		1
-#define CFG_CONSOLE_OVERWRITE_ROUTINE	1
-#define CFG_CONSOLE_ENV_OVERWRITE	1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE	1
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE	1
 
 /*************************************************************************************************/
 
@@ -750,7 +749,7 @@ typedef unsigned int led_id_t;
 #define CONFIG_CDP_DEVICE_ID_PREFIX	"NT"	/* netta2 */
 #define CONFIG_CDP_PORT_ID		"eth%d"
 #define CONFIG_CDP_CAPABILITIES		0x00000010
-#define CONFIG_CDP_VERSION		"u-boot" " " __DATE__ " " __TIME__
+#define CONFIG_CDP_VERSION		"u-boot" " " U_BOOT_DATE " " U_BOOT_TIME
 #define CONFIG_CDP_PLATFORM		"Intracom NetTA2"
 #define CONFIG_CDP_TRIGGER		0x20020001
 #define CONFIG_CDP_POWER_CONSUMPTION	4300	/* 90 mA @ 48V */
diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h
index e550030..f97bdcb 100644
--- a/include/configs/NETVIA.h
+++ b/include/configs/NETVIA.h
@@ -69,7 +69,7 @@
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -117,25 +117,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0300000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -145,65 +145,65 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFF000000
+#define CONFIG_SYS_IMMR		0xFF000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
 #if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SECT_SIZE	0x10000
 
-#define	CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x60000)
+#define	CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x60000)
 #define CONFIG_ENV_OFFSET		0
 #define	CONFIG_ENV_SIZE		0x4000
 
-#define CONFIG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + 0x70000)
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + 0x70000)
 #define CONFIG_ENV_OFFSET_REDUND	0
 #define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -213,10 +213,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -225,9 +225,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -235,20 +235,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -268,16 +268,16 @@
 
 #if CONFIG_8xx_GCLK_FREQ == 50000000
 
-#define CFG_PLPRCR	( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#define CFG_SCCR	(SCCR_TBS     | \
+#define CONFIG_SYS_PLPRCR	( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 
 #elif CONFIG_8xx_GCLK_FREQ == 80000000
 
-#define CFG_PLPRCR	( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#define CFG_SCCR	(SCCR_TBS     | \
+#define CONFIG_SYS_PLPRCR	( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00 | SCCR_EBDF01)
@@ -289,8 +289,8 @@
  *-----------------------------------------------------------------------
  *
  */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -304,15 +304,15 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 
 /*
  * BR3 and OR3 (SDRAM)
@@ -322,27 +322,27 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
+#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
 
-#define CFG_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
 
 /*
  * Memory Periodic Timer Prescaler
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	208
+#define CONFIG_SYS_MAMR_PTA	208
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
@@ -381,11 +381,11 @@
 #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
 
 #define STATUS_LED_BIT		0x00000001		/* bit 31 */
-#define STATUS_LED_PERIOD	(CFG_HZ / 2)
+#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
 #define STATUS_LED_STATE	STATUS_LED_BLINKING
 
 #define STATUS_LED_BIT1		0x00000002		/* bit 30 */
-#define STATUS_LED_PERIOD1	(CFG_HZ / 2)
+#define STATUS_LED_PERIOD1	(CONFIG_SYS_HZ / 2)
 #define STATUS_LED_STATE1	STATUS_LED_OFF
 
 #define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
@@ -400,10 +400,10 @@
 #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
 
 /* NAND */
-#define CFG_NAND_BASE			NAND_BASE
+#define CONFIG_SYS_NAND_BASE			NAND_BASE
 #define CONFIG_MTD_NAND_ECC_JFFS2
 
-#define CFG_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
 
 #define SECTORSIZE		512
 #define ADDR_COLUMN		1
@@ -411,41 +411,40 @@
 #define ADDR_COLUMN_PAGE	3
 #define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS		1
-#define NAND_MAX_CHIPS		1
 
 #define NAND_DISABLE_CE(nand) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  0x0040; \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |=  0x0040; \
 	} while(0)
 
 #define NAND_ENABLE_CE(nand) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0040; \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~0x0040; \
 	} while(0)
 
 #define NAND_CTL_CLRALE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0100; \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~0x0100; \
 	} while(0)
 
 #define NAND_CTL_SETALE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  0x0100; \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |=  0x0100; \
 	} while(0)
 
 #define NAND_CTL_CLRCLE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0080; \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~0x0080; \
 	} while(0)
 
 #define NAND_CTL_SETCLE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  0x0080; \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |=  0x0080; \
 	} while(0)
 
 #define NAND_WAIT_READY(nand) \
 	do { \
-		while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x100) == 0) \
+		while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & 0x100) == 0) \
 			; \
 	} while (0)
 
@@ -519,16 +518,16 @@ static inline void __led_set(led_id_t mask, int state)
 }
 
 /* MAX3100 console */
-#define MAX3100_SPI_RXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define MAX3100_SPI_RXD_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
 #define MAX3100_SPI_RXD_BIT	0x00000008
 
-#define MAX3100_SPI_TXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define MAX3100_SPI_TXD_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
 #define MAX3100_SPI_TXD_BIT	0x00000004
 
-#define MAX3100_SPI_CLK_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define MAX3100_SPI_CLK_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
 #define MAX3100_SPI_CLK_BIT	0x00000002
 
-#define MAX3100_CS_PORT		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat)
+#define MAX3100_CS_PORT		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
 #define MAX3100_CS_BIT		0x0010
 
 #endif
diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h
index e297c84..6abd3f1 100644
--- a/include/configs/NSCU.h
+++ b/include/configs/NSCU.h
@@ -83,7 +83,7 @@
 #define CONFIG_MISC_INIT_R	  1
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -129,33 +129,33 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history
 */
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -165,47 +165,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
@@ -215,21 +215,21 @@
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -239,10 +239,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -251,9 +251,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -261,20 +261,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -282,7 +282,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -291,7 +291,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 
@@ -303,14 +303,14 @@
 /* NSCU use both slots, SLOT_A as "primary". */
 #define	CONFIG_PCMCIA_SLOT_A 1
 
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 #define PCMCIA_MEM_WIN_NO	8 /* override default 4 in pcmcia.h */
 #define	PCMCIA_SOCKETS_NO	2 /* we have two sockets */
 #undef	NSCU_OE_INV		/* PCMCIA_GCRX_CXOE was inverted on early boards */
@@ -326,29 +326,29 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		2	/* max. 2 IDE buses		*/
-#define CFG_IDE_MAXDEVICE	4	/* max. 2 drives per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		2	/* max. 2 IDE buses		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	4	/* max. 2 drives per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#define CFG_ATA_IDE1_OFFSET	(4 * CFG_PCMCIA_MEM_SIZE) /* starts @ 4th window */
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE1_OFFSET	(4 * CONFIG_SYS_PCMCIA_MEM_SIZE) /* starts @ 4th window */
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -363,22 +363,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -389,28 +389,28 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 #ifndef	CONFIG_CAN_DRIVER
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 #endif	/* CONFIG_CAN_DRIVER */
 
 #ifdef	CONFIG_ISP1362_USB
-#define	CFG_ISP1362_BASE	0xD0000000	/* ISP1362 mapped at 0xD0000000 */
-#define CFG_ISP1362_OR_AM	0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR5_ISP1362		(CFG_ISP1362_OR_AM | OR_CSNT_SAM | \
+#define	CONFIG_SYS_ISP1362_BASE	0xD0000000	/* ISP1362 mapped at 0xD0000000 */
+#define CONFIG_SYS_ISP1362_OR_AM	0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR5_ISP1362		(CONFIG_SYS_ISP1362_OR_AM | OR_CSNT_SAM | \
 				 OR_ACS_DIV2       | OR_BI       | OR_SCY_5_CLK)
-#define CFG_BR5_ISP1362		((CFG_ISP1362_BASE & BR_BA_MSK) | \
+#define CONFIG_SYS_BR5_ISP1362		((CONFIG_SYS_ISP1362_BASE & BR_BA_MSK) | \
 				 BR_PS_16          | BR_MS_GPCM | BR_V )
 #endif	/* CONFIG_ISP1362_USB */
 
@@ -441,34 +441,34 @@
  * 80 Mhz => 80.000.000 / Divider = 156
  */
 
-#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
-#define CFG_MAMR_PTA	98
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/NX823.h b/include/configs/NX823.h
index 1f4c329..9182223 100644
--- a/include/configs/NX823.h
+++ b/include/configs/NX823.h
@@ -53,7 +53,7 @@
 #define CONFIG_BOOTCOMMAND	"bootm 400e0000"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 #undef	CONFIG_WATCHDOG			/* watchdog disabled, for now	    */
 #define CONFIG_AUTOSCRIPT
 
@@ -81,25 +81,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on */
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -109,64 +109,64 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	    */
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	    */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)  */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)  */
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define xEMBED
 #ifdef	EMBED
 #define CONFIG_ENV_SIZE		0x200	/* FIXME How big when embedded?? */
-#define CONFIG_ENV_ADDR		CFG_MONITOR_BASE
+#define CONFIG_ENV_ADDR		CONFIG_SYS_MONITOR_BASE
 #else
 #define CONFIG_ENV_ADDR		0x40020000	/* absolute address for now   */
 #define CONFIG_ENV_SIZE		0x20000 /* 8K ouch, this may later be */
 #endif
 
-#define CFG_FLASH_SN_BASE	0x4001fff0	/* programmer automagically puts    */
-#define CFG_FLASH_SN_SECTOR	0x40000000	/* a serial number here		    */
-#define CFG_FLASH_SN_BYTES	8
+#define CONFIG_SYS_FLASH_SN_BASE	0x4001fff0	/* programmer automagically puts    */
+#define CONFIG_SYS_FLASH_SN_SECTOR	0x40000000	/* a serial number here		    */
+#define CONFIG_SYS_FLASH_SN_BYTES	8
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs		*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs		*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value    */
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value    */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -176,10 +176,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -187,27 +187,27 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				12-16
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		12-18
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		12-23
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		5-7
@@ -218,8 +218,8 @@
 #define MPC8XX_SPEED	66666666L
 #define MPC8XX_XIN	32768	/* 32.768 kHz crystal */
 #define MPC8XX_FACT		(MPC8XX_SPEED/MPC8XX_XIN)
-#define CFG_PLPRCR_MF  ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT)
-#define CFG_PLPRCR		(CFG_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR_MF  ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT)
+#define CONFIG_SYS_PLPRCR		(CONFIG_SYS_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		5-3
@@ -228,7 +228,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS     | \
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -238,7 +238,7 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER		0
+#define CONFIG_SYS_DER		0
 
 /*
  * Init Memory Controller:
@@ -252,16 +252,16 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV1 | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV1 | OR_BI | \
 				 OR_SCY_8_CLK )
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 
 /*
  * BR1/2 and OR1/2 (SDRAM)
@@ -271,12 +271,12 @@
 #define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */
-#define CFG_OR_TIMING_SDRAM	(OR_G5LS | OR_CSNT_SAM)
+#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_G5LS | OR_CSNT_SAM)
 
-#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#define CFG_OR2_PRELIM	CFG_OR1_PRELIM
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR1_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_OR1_PRELIM
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /* IO and memory mapped stuff */
 #define NX823_IO_OR_AM		0xFFFF0000	/* mask for IO addresses */
@@ -292,24 +292,24 @@
  */
 #define GPOUT_BASE	(NX823_IO_BASE + GPOUT_OFFSET)
 #define GPOUT_TIMING	(OR_CSNT_SAM | OR_TRLX | OR_BI)
-#define CFG_OR3_PRELIM	(NX823_IO_OR_AM | GPOUT_TIMING)
-#define CFG_BR3_PRELIM	(GPOUT_BASE | BR_V)
+#define CONFIG_SYS_OR3_PRELIM	(NX823_IO_OR_AM | GPOUT_TIMING)
+#define CONFIG_SYS_BR3_PRELIM	(GPOUT_BASE | BR_V)
 
 /*
  * BR4 and OR4 (QUART)
  */
 #define QUART_BASE	(NX823_IO_BASE + QUART_OFFSET)
 #define QUART_TIMING	(OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX)
-#define CFG_OR4_PRELIM	(NX823_IO_OR_AM | QUART_TIMING | OR_BI)
-#define CFG_BR4_PRELIM	(QUART_BASE | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR4_PRELIM	(NX823_IO_OR_AM | QUART_TIMING | OR_BI)
+#define CONFIG_SYS_BR4_PRELIM	(QUART_BASE | BR_PS_8 | BR_V)
 
 /*
  * BR5 and OR5 (Video DAC)
  */
 #define VIDAC_BASE	(NX823_IO_BASE + VIDAC_OFFSET)
 #define VIDAC_TIMING	(OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
-#define CFG_OR5_PRELIM	(NX823_IO_OR_AM | VIDAC_TIMING | OR_BI)
-#define CFG_BR5_PRELIM	(VIDAC_BASE | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR5_PRELIM	(NX823_IO_OR_AM | VIDAC_TIMING | OR_BI)
+#define CONFIG_SYS_BR5_PRELIM	(VIDAC_BASE | BR_PS_8 | BR_V)
 
 /*
  * BR6 and OR6 (CPLD)
@@ -317,42 +317,42 @@
  */
 #define CPLD_BASE	(NX823_IO_BASE + CPLD_OFFSET)
 #define CPLD_TIMING	(OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
-#define CFG_OR6_PRELIM	(NX823_IO_OR_AM | CPLD_TIMING | OR_BI)
-#define CFG_BR6_PRELIM	(CPLD_BASE | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR6_PRELIM	(NX823_IO_OR_AM | CPLD_TIMING | OR_BI)
+#define CONFIG_SYS_BR6_PRELIM	(CPLD_BASE | BR_PS_8 | BR_V )
 
 /*
  * BR7 and OR7 (SED1386)
  * FIXME timing not verified for SED controller
  */
 #define SED1386_BASE	0xF7000000
-#define CFG_OR7_PRELIM	(0xFF000000 | OR_BI | OR_SETA)
-#define CFG_BR7_PRELIM	(SED1386_BASE | BR_PS_16 | BR_V )
+#define CONFIG_SYS_OR7_PRELIM	(0xFF000000 | OR_BI | OR_SETA)
+#define CONFIG_SYS_BR7_PRELIM	(SED1386_BASE | BR_PS_16 | BR_V )
 
 /*
  * Memory Periodic Timer Prescaler
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz   */
+#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz   */
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16 /* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32 /* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16 /* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32 /* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8	/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16 /* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8	/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16 /* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h
index 17b00a1..2591f1d 100644
--- a/include/configs/OCRTC.h
+++ b/include/configs/OCRTC.h
@@ -48,8 +48,9 @@
 #define CONFIG_BOOTCOMMAND "go fff00100"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
@@ -87,35 +88,34 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
@@ -136,66 +136,66 @@
 
 #define CONFIG_PCI_BOOTDELAY	1	/* enable pci bootdelay variable*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0410	/* PCI Device ID: OCRTC		*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0410	/* PCI Device ID: OCRTC		*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFD0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFD0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* Use NVRAM for environment variables */
 /*-----------------------------------------------------------------------
  * NVRAM organization
  */
 #define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
 #define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
 #define CONFIG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
-#define CFG_NVRAM_VXWORKS_OFFS	0x6900		/* Offset for VxWorks eth-addr	*/
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
+#define CONFIG_SYS_NVRAM_VXWORKS_OFFS	0x6900		/* Offset for VxWorks eth-addr	*/
 
 #else /* Use EEPROM for environment variables */
 
@@ -209,18 +209,17 @@
  * I2C EEPROM (CAT24WC08) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 /*
  * Init Memory Controller:
@@ -236,62 +235,62 @@
  */
 
 /* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (Flash Bank 1) initialization					*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 2 (PLD - FPGA-boot) initialization				*/
-#define CFG_EBC_PB2AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+#define CONFIG_SYS_EBC_PB2AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 3 (PLD - OSL) initialization					*/
-#define CFG_EBC_PB3AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+#define CONFIG_SYS_EBC_PB3AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB3CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB3CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 4 (Spartan2 1) initialization					*/
-#define CFG_EBC_PB4AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+#define CONFIG_SYS_EBC_PB4AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB4CR		0xF209C000  /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
+#define CONFIG_SYS_EBC_PB4CR		0xF209C000  /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
 
 /* Memory Bank 5 (Spartan2 2) initialization					*/
-#define CFG_EBC_PB5AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+#define CONFIG_SYS_EBC_PB5AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB5CR		0xF309C000  /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
+#define CONFIG_SYS_EBC_PB5CR		0xF309C000  /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
 
 /* Memory Bank 6 (Virtex 1) initialization					*/
-#define CFG_EBC_PB6AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+#define CONFIG_SYS_EBC_PB6AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB6CR		0xF409A000  /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB6CR		0xF409A000  /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
 
 /* Memory Bank 7 (Virtex 2) initialization					*/
-#define CFG_EBC_PB7AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+#define CONFIG_SYS_EBC_PB7AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB7CR		0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB7CR		0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
 
 
-#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 
 /*
diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h
index 4f4b13d..13d6e04 100644
--- a/include/configs/ORSG.h
+++ b/include/configs/ORSG.h
@@ -48,8 +48,9 @@
 #define CONFIG_BOOTCOMMAND "go fff00100"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
@@ -87,35 +88,34 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
@@ -134,66 +134,66 @@
 
 #undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0411	/* PCI Device ID: ORSG		*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0411	/* PCI Device ID: ORSG		*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFD0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFD0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* Use NVRAM for environment variables */
 /*-----------------------------------------------------------------------
  * NVRAM organization
  */
 #define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
 #define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
 #define CONFIG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
-#define CFG_NVRAM_VXWORKS_OFFS	0x6900		/* Offset for VxWorks eth-addr	*/
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
+#define CONFIG_SYS_NVRAM_VXWORKS_OFFS	0x6900		/* Offset for VxWorks eth-addr	*/
 
 #else /* Use EEPROM for environment variables */
 
@@ -207,18 +207,17 @@
  * I2C EEPROM (CAT24WC08) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 /*
  * Init Memory Controller:
@@ -234,62 +233,62 @@
  */
 
 /* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (Flash Bank 1) initialization					*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 2 (PLD - FPGA-boot) initialization				*/
-#define CFG_EBC_PB2AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+#define CONFIG_SYS_EBC_PB2AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 3 (PLD - OSL) initialization					*/
-#define CFG_EBC_PB3AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+#define CONFIG_SYS_EBC_PB3AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB3CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB3CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 4 (Spartan2 1) initialization					*/
-#define CFG_EBC_PB4AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+#define CONFIG_SYS_EBC_PB4AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB4CR		0xF209C000  /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
+#define CONFIG_SYS_EBC_PB4CR		0xF209C000  /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
 
 /* Memory Bank 5 (Spartan2 2) initialization					*/
-#define CFG_EBC_PB5AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+#define CONFIG_SYS_EBC_PB5AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB5CR		0xF309C000  /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
+#define CONFIG_SYS_EBC_PB5CR		0xF309C000  /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
 
 /* Memory Bank 6 (Virtex 1) initialization					*/
-#define CFG_EBC_PB6AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+#define CONFIG_SYS_EBC_PB6AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB6CR		0xF409A000  /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB6CR		0xF409A000  /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
 
 /* Memory Bank 7 (Virtex 2) initialization					*/
-#define CFG_EBC_PB7AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+#define CONFIG_SYS_EBC_PB7AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB7CR		0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB7CR		0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
 
 
-#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 
 /*
diff --git a/include/configs/OXC.h b/include/configs/OXC.h
index 2ccaf47..104c23f 100644
--- a/include/configs/OXC.h
+++ b/include/configs/OXC.h
@@ -49,7 +49,7 @@
 
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		9600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 
 /*
@@ -72,14 +72,14 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		1		/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_MISC_INIT_R	1		/* call misc_init_r() on init	*/
 
@@ -95,8 +95,8 @@
 #define CONFIG_BOOTCOMMAND	"tftp 0x10000 ; bootelf 0x10000"
 #define CONFIG_BOOTDELAY	10
 
-#define CFG_OXC_GENERATE_IP	1		/* Generate IP automatically	*/
-#define CFG_OXC_IPMASK		0x0A000000	/* 10.0.0.x			*/
+#define CONFIG_SYS_OXC_GENERATE_IP	1		/* Generate IP automatically	*/
+#define CONFIG_SYS_OXC_IPMASK		0x0A000000	/* 10.0.0.x			*/
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -107,7 +107,7 @@
 #define CONFIG_NET_MULTI			/* Multi ethernet cards support */
 
 #define CONFIG_EEPRO100				/* Ethernet Express PRO 100	*/
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
 
 #define PCI_ENET0_IOADDR	0x80000000
 #define PCI_ENET0_MEMADDR	0x80000000
@@ -118,63 +118,63 @@
  * FLASH
  */
 
-#define CFG_FLASH_PRELIMBASE	0xFF800000
-#define CFG_FLASH_BASE		(0-flash_info[0].size)
+#define CONFIG_SYS_FLASH_PRELIMBASE	0xFF800000
+#define CONFIG_SYS_FLASH_BASE		(0-flash_info[0].size)
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	32	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	32	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 /*-----------------------------------------------------------------------
  * RAM
  */
 
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	0x10000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000
 
-#define CFG_RESET_ADDRESS	0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		0x00030000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		0x00030000
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_PRELIMBASE)
-# define CFG_RAMBOOT		1
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_PRELIMBASE)
+# define CONFIG_SYS_RAMBOOT		1
 #else
-# undef CFG_RAMBOOT
+# undef CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_INIT_RAM_ADDR	0x40000000
-#define CFG_INIT_RAM_END	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000
 
-#define CFG_GBL_DATA_SIZE	128
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
 
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
 
 /*-----------------------------------------------------------------------
  * Memory mapping
  */
 
-#define CFG_CPLD_BASE		0xff000000	/* CPLD registers */
-#define CFG_CPLD_WATCHDOG	(CFG_CPLD_BASE)			/* Watchdog */
-#define CFG_CPLD_RESET		(CFG_CPLD_BASE + 0x040000)	/* Minor resets */
-#define CFG_UART_BASE		(CFG_CPLD_BASE + 0x700000)	/* debug UART */
+#define CONFIG_SYS_CPLD_BASE		0xff000000	/* CPLD registers */
+#define CONFIG_SYS_CPLD_WATCHDOG	(CONFIG_SYS_CPLD_BASE)			/* Watchdog */
+#define CONFIG_SYS_CPLD_RESET		(CONFIG_SYS_CPLD_BASE + 0x040000)	/* Minor resets */
+#define CONFIG_SYS_UART_BASE		(CONFIG_SYS_CPLD_BASE + 0x700000)	/* debug UART */
 
 /*-----------------------------------------------------------------------
  * NS16550 Configuration
  */
 
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	-4
-#define CFG_NS16550_CLK		1843200
-#define CFG_NS16550_COM1	CFG_UART_BASE
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		1843200
+#define CONFIG_SYS_NS16550_COM1	CONFIG_SYS_UART_BASE
 
 /*-----------------------------------------------------------------------
  * I2C Bus
@@ -182,12 +182,12 @@
 
 #define CONFIG_I2C		1		/* I2C support on ... */
 #define CONFIG_HARD_I2C		1		/* ... hardware one */
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F		/* I2C slave address */
+#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F		/* I2C slave address */
 
-#define CFG_I2C_EXPANDER0_ADDR	0x20		/* PCF8574 expander 0 addrerr */
-#define CFG_I2C_EXPANDER1_ADDR	0x21		/* PCF8574 expander 1 addrerr */
-#define CFG_I2C_EXPANDER2_ADDR	0x26		/* PCF8574 expander 2 addrerr */
+#define CONFIG_SYS_I2C_EXPANDER0_ADDR	0x20		/* PCF8574 expander 0 addrerr */
+#define CONFIG_SYS_I2C_EXPANDER1_ADDR	0x21		/* PCF8574 expander 1 addrerr */
+#define CONFIG_SYS_I2C_EXPANDER2_ADDR	0x26		/* PCF8574 expander 2 addrerr */
 
 /*-----------------------------------------------------------------------
  * Environment
@@ -208,30 +208,30 @@
 #define CONFIG_SYS_CLK_FREQ  33000000	/* external frequency to pll */
 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2
 
-#define CFG_EUMB_ADDR		0xFC000000
+#define CONFIG_SYS_EUMB_ADDR		0xFC000000
 
 /* MCCR1 */
-#define CFG_ROMNAL		0	/* rom/flash next access time		*/
-#define CFG_ROMFAL		19	/* rom/flash access time		*/
+#define CONFIG_SYS_ROMNAL		0	/* rom/flash next access time		*/
+#define CONFIG_SYS_ROMFAL		19	/* rom/flash access time		*/
 
 /* MCCR2 */
-#define CFG_ASRISE		15	/* ASRISE=15 clocks			*/
-#define CFG_ASFALL		3	/* ASFALL=3 clocks			*/
-#define CFG_REFINT		1000	/* REFINT=1000 clocks			*/
+#define CONFIG_SYS_ASRISE		15	/* ASRISE=15 clocks			*/
+#define CONFIG_SYS_ASFALL		3	/* ASFALL=3 clocks			*/
+#define CONFIG_SYS_REFINT		1000	/* REFINT=1000 clocks			*/
 
 /* MCCR3 */
-#define CFG_BSTOPRE		0x35c	/* Burst To Precharge			*/
-#define CFG_REFREC		7	/* Refresh to activate interval		*/
-#define CFG_RDLAT		4	/* data latency from read command	*/
+#define CONFIG_SYS_BSTOPRE		0x35c	/* Burst To Precharge			*/
+#define CONFIG_SYS_REFREC		7	/* Refresh to activate interval		*/
+#define CONFIG_SYS_RDLAT		4	/* data latency from read command	*/
 
 /* MCCR4 */
-#define CFG_PRETOACT		2	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
-#define CFG_ACTORW		2	/* Activate to R/W			*/
-#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
-#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
-#define CFG_SDMODE_BURSTLEN	3	/* SDMODE Burst length 2=4, 3=8		*/
-#define CFG_REGISTERD_TYPE_BUFFER   1
+#define CONFIG_SYS_PRETOACT		2	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		2	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#define CONFIG_SYS_SDMODE_BURSTLEN	3	/* SDMODE Burst length 2=4, 3=8		*/
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
 
 /* memory bank settings*/
 /*
@@ -240,80 +240,80 @@
  * bits will be set to 0x00000 for a start address, or 0xfffff for an
  * end address
  */
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x00000000
-#define CFG_BANK1_END		0x00000000
-#define CFG_BANK1_ENABLE	0
-#define CFG_BANK2_START		0x00000000
-#define CFG_BANK2_END		0x00000000
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x00000000
-#define CFG_BANK3_END		0x00000000
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x00000000
-#define CFG_BANK4_END		0x00000000
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x00000000
-#define CFG_BANK5_END		0x00000000
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x00000000
-#define CFG_BANK6_END		0x00000000
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x00000000
-#define CFG_BANK7_END		0x00000000
-#define CFG_BANK7_ENABLE	0
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x00000000
+#define CONFIG_SYS_BANK1_END		0x00000000
+#define CONFIG_SYS_BANK1_ENABLE	0
+#define CONFIG_SYS_BANK2_START		0x00000000
+#define CONFIG_SYS_BANK2_END		0x00000000
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x00000000
+#define CONFIG_SYS_BANK3_END		0x00000000
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x00000000
+#define CONFIG_SYS_BANK4_END		0x00000000
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x00000000
+#define CONFIG_SYS_BANK5_END		0x00000000
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x00000000
+#define CONFIG_SYS_BANK6_END		0x00000000
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x00000000
+#define CONFIG_SYS_BANK7_END		0x00000000
+#define CONFIG_SYS_BANK7_ENABLE	0
 /*
  * Memory bank enable bitmask, specifying which of the banks defined above
  are actually present. MSB is for bank #7, LSB is for bank #0.
  */
-#define CFG_BANK_ENABLE		0x01
+#define CONFIG_SYS_BANK_ENABLE		0x01
 
-#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
+#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
 					/* see 8240 book for bit definitions	*/
-#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
 					/* currently accessed page in memory	*/
 					/* see 8240 book for details		*/
 
 /* SDRAM 0 - 256MB */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* stack in DCACHE @ 1GB (no backing mem) */
-#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 
 /* PCI memory */
-#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* Flash, config addrs, etc */
-#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*
diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h
index 8150091..971338a 100644
--- a/include/configs/P3G4.h
+++ b/include/configs/P3G4.h
@@ -40,7 +40,7 @@
  */
 
 #define CONFIG_P3G4		1	/* this is a P3G4  board	*/
-#define CFG_GT_6426x        GT_64260 /* with a 64260 system controller */
+#define CONFIG_SYS_GT_6426x        GT_64260 /* with a 64260 system controller */
 
 #define CONFIG_BAUDRATE		115200	/* console baudrate = 115200	*/
 
@@ -51,10 +51,10 @@
 #define CONFIG_MISC_INIT_R	1
 #define CONFIG_BOARD_EARLY_INIT_F 1
 
-#define CFG_BOARD_NAME		"P3G4"
+#define CONFIG_SYS_BOARD_NAME		"P3G4"
 
-#undef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 /*
  * The following defines let you select what serial you want to use
@@ -115,7 +115,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
-#define	CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+#define	CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 #undef	CONFIG_ALTIVEC                  /* undef to disable             */
@@ -151,27 +151,27 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x00300000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x00300000	/* default load address	*/
 
-#define	CFG_HZ			1000		/* decr freq: 1ms ticks	*/
-#define CFG_BUS_HZ		133000000	/* 133 MHz		*/
-#define CFG_BUS_CLK		CFG_BUS_HZ
+#define	CONFIG_SYS_HZ			1000		/* decr freq: 1ms ticks	*/
+#define CONFIG_SYS_BUS_HZ		133000000	/* 133 MHz		*/
+#define CONFIG_SYS_BUS_CLK		CONFIG_SYS_BUS_HZ
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 
 /*
@@ -183,63 +183,63 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area
  */
-#define CFG_INIT_RAM_ADDR	0x40000000
-#define	CFG_INIT_RAM_END	0x1000
-#define	CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define	CONFIG_SYS_INIT_RAM_END	0x1000
+#define	CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_LOCK
 
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xff000000
-#define CFG_RESET_ADDRESS	0xfff00100
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xff000000
+#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
 
 /* areas to map different things with the GT in physical space */
-#define CFG_DRAM_BANKS		1
-#define CFG_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */
+#define CONFIG_SYS_DRAM_BANKS		1
+#define CONFIG_SYS_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */
 
 /* What to put in the bats. */
-#define CFG_MISC_REGION_BASE	0xf0000000
+#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
 
 /* Peripheral Device section */
-#define CFG_GT_REGS		0xf8000000
-#define CFG_DEV_BASE		0xff000000
+#define CONFIG_SYS_GT_REGS		0xf8000000
+#define CONFIG_SYS_DEV_BASE		0xff000000
 
-#define CFG_DEV0_SPACE		CFG_DEV_BASE
-#define CFG_DEV1_SPACE		(CFG_DEV0_SPACE + CFG_DEV0_SIZE)
-#define CFG_DEV2_SPACE		(CFG_DEV1_SPACE + CFG_DEV1_SIZE)
-#define CFG_DEV3_SPACE		(CFG_DEV2_SPACE + CFG_DEV2_SIZE)
+#define CONFIG_SYS_DEV0_SPACE		CONFIG_SYS_DEV_BASE
+#define CONFIG_SYS_DEV1_SPACE		(CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
+#define CONFIG_SYS_DEV2_SPACE		(CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
+#define CONFIG_SYS_DEV3_SPACE		(CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
 
-#define CFG_DEV0_SIZE		 _8M /* Flash bank */
-#define CFG_DEV1_SIZE		 0   /* unused */
-#define CFG_DEV2_SIZE		 0   /* unused */
-#define CFG_DEV3_SIZE		 0   /* unused */
+#define CONFIG_SYS_DEV0_SIZE		 _8M /* Flash bank */
+#define CONFIG_SYS_DEV1_SIZE		 0   /* unused */
+#define CONFIG_SYS_DEV2_SIZE		 0   /* unused */
+#define CONFIG_SYS_DEV3_SIZE		 0   /* unused */
 
-#define CFG_16BIT_BOOT_PAR	0xc01b5e7c
-#define CFG_DEV0_PAR		CFG_16BIT_BOOT_PAR
+#define CONFIG_SYS_16BIT_BOOT_PAR	0xc01b5e7c
+#define CONFIG_SYS_DEV0_PAR		CONFIG_SYS_16BIT_BOOT_PAR
 
 #if 0 /* Wrong?? NTL */
-#define CFG_MPP_CONTROL_0	0x53541717	/* InitAct EOT[4] DBurst TCEn[1] */
+#define CONFIG_SYS_MPP_CONTROL_0	0x53541717	/* InitAct EOT[4] DBurst TCEn[1] */
 						/* DMAAck[1:0] GNT0[1:0] */
 #else
-#define CFG_MPP_CONTROL_0	0x53547777	/* InitAct EOT[4] DBurst TCEn[1] */
+#define CONFIG_SYS_MPP_CONTROL_0	0x53547777	/* InitAct EOT[4] DBurst TCEn[1] */
 						/* REQ0[1:0] GNT0[1:0] */
 #endif
-#define CFG_MPP_CONTROL_1	0x44009911	/* TCEn[4] TCTcnt[4] GPP[13:12] */
+#define CONFIG_SYS_MPP_CONTROL_1	0x44009911	/* TCEn[4] TCTcnt[4] GPP[13:12] */
 						/* DMAReq[4] DMAAck[4] WDNMI WDE */
 #if 0 /* Wrong?? NTL */
-#define CFG_MPP_CONTROL_2	0x40091818	/* TCTcnt[0] GPP[22:21] BClkIn */
+#define CONFIG_SYS_MPP_CONTROL_2	0x40091818	/* TCTcnt[0] GPP[22:21] BClkIn */
 						/* DMAAck[1:0] GNT1[1:0] */
 #else
-#define CFG_MPP_CONTROL_2	0x40098888	/* TCTcnt[0] */
+#define CONFIG_SYS_MPP_CONTROL_2	0x40098888	/* TCTcnt[0] */
 						/* GPP[22] (RS232IntB or PCI1Int) */
 						/* GPP[21] (RS323IntA) */
 						/* BClkIn */
@@ -247,10 +247,10 @@
 #endif
 
 #if 0 /* Wrong?? NTL */
-# define CFG_MPP_CONTROL_3	0x00090066	/* GPP[31:29] BClkOut0 */
+# define CONFIG_SYS_MPP_CONTROL_3	0x00090066	/* GPP[31:29] BClkOut0 */
 						/* GPP[27:26] Int[1:0] */
 #else
-# define CFG_MPP_CONTROL_3	0x22090066      /* MREQ MGNT */
+# define CONFIG_SYS_MPP_CONTROL_3	0x22090066      /* MREQ MGNT */
 						/* GPP[29]    (PCI1Int) */
 						/* BClkOut0 */
 						/* GPP[27]    (PCI0Int) */
@@ -258,17 +258,17 @@
 						/* CPUInt[25:24] */
 #endif
 
-#define CFG_SERIAL_PORT_MUX	0x00001102	/* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
+#define CONFIG_SYS_SERIAL_PORT_MUX	0x00001102	/* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
 
 #if 0 /* Wrong?? - NTL */
-# define CFG_GPP_LEVEL_CONTROL	0x000002c6
+# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x000002c6
 #else
-# define CFG_GPP_LEVEL_CONTROL	0x2c600000	/* 0010 1100 0110 0000 */
+# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x2c600000	/* 0010 1100 0110 0000 */
 						/* gpp[29] */
 						/* gpp[27:26] */
 						/* gpp[22:21] */
 
-# define CFG_SDRAM_CONFIG	0xd8e18200	/* 0x448 */
+# define CONFIG_SYS_SDRAM_CONFIG	0xd8e18200	/* 0x448 */
 				/* idmas use buffer 1,1
 				   comm use buffer 0
 				   pci use buffer 1,1
@@ -286,13 +286,13 @@
 #endif
 
 #if 0
-#define CFG_DUART_IO		CFG_DEV2_SPACE
-#define CFG_DUART_CHAN		1		/* channel to use for console */
+#define CONFIG_SYS_DUART_IO		CONFIG_SYS_DEV2_SPACE
+#define CONFIG_SYS_DUART_CHAN		1		/* channel to use for console */
 #endif
-#undef CFG_INIT_CHAN1
-#undef CFG_INIT_CHAN2
+#undef CONFIG_SYS_INIT_CHAN1
+#undef CONFIG_SYS_INIT_CHAN2
 #if 0
-#define SRAM_BASE		CFG_DEV0_SPACE
+#define SRAM_BASE		CONFIG_SYS_DEV0_SPACE
 #define SRAM_SIZE		0x00100000		/* 1 MB of sram */
 #endif
 
@@ -311,24 +311,24 @@
 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 
 /* PCI MEMORY MAP section */
-#define CFG_PCI0_MEM_BASE	0x80000000
-#define CFG_PCI0_MEM_SIZE	_128M
-#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
+#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
 
-#define CFG_PCI1_MEM_BASE	0x88000000
-#define CFG_PCI1_MEM_SIZE	_128M
-#define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
+#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
 
 /* PCI I/O MAP section */
-#define CFG_PCI0_IO_BASE	0xfa000000
-#define CFG_PCI0_IO_SIZE	_16M
-#define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
-#define CFG_PCI0_IO_SPACE_PCI	0x00000000
+#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
+#define CONFIG_SYS_PCI0_IO_SIZE	_16M
+#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
+#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000
 
-#define CFG_PCI1_IO_BASE	0xfb000000
-#define CFG_PCI1_IO_SIZE	_16M
-#define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
-#define CFG_PCI1_IO_SPACE_PCI	0x00000000
+#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
+#define CONFIG_SYS_PCI1_IO_SIZE	_16M
+#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
+#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000
 
 /*----------------------------------------------------------------------
  * Initial BAT mappings
@@ -340,32 +340,32 @@
  */
 
 /* SDRAM */
-#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT0U CFG_IBAT0U
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
 
 /* init ram */
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 
 /* PCI0, PCI1 in one BAT */
-#define CFG_IBAT2L BATL_NO_ACCESS
-#define CFG_IBAT2U CFG_DBAT2U
-#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
+#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* GT regs, bootrom, all the devices, PCI I/O */
-#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 
 /* I2C speed and slave address (for compatability) defaults */
-#define CFG_I2C_SPEED	400000
-#define CFG_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_SPEED	400000
+#define CONFIG_SYS_I2C_SLAVE	0x7F
 
 /* I2C addresses for the two DIMM SPD chips */
 #ifndef CONFIG_EVB64260_750CX
@@ -381,21 +381,21 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8<<20)	/* Initial Memory map for Linux */
+#define	CONFIG_SYS_BOOTMAPSZ		(8<<20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
 
-#define CFG_EXTRA_FLASH_DEVICE	BOOT_DEVICE
-#define CFG_EXTRA_FLASH_WIDTH	2	/* 16 bit */
-#define CFG_BOOT_FLASH_WIDTH	2	/* 16 bit */
+#define CONFIG_SYS_EXTRA_FLASH_DEVICE	BOOT_DEVICE
+#define CONFIG_SYS_EXTRA_FLASH_WIDTH	2	/* 16 bit */
+#define CONFIG_SYS_BOOT_FLASH_WIDTH	2	/* 16 bit */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_CFI		1
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_CFI		1
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
@@ -405,9 +405,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -415,7 +415,7 @@
  * look in include/74xx_7xx.h for the defines used here
  */
 
-#define CFG_L2
+#define CONFIG_SYS_L2
 
 #define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 			 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
@@ -430,7 +430,7 @@
 #define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02		/* Software reboot		    */
 
-#define CFG_BOARD_ASM_INIT      1
+#define CONFIG_SYS_BOARD_ASM_INIT      1
 
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/PATI.h b/include/configs/PATI.h
index 42b155e..88e9528 100644
--- a/include/configs/PATI.h
+++ b/include/configs/PATI.h
@@ -57,7 +57,7 @@
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_LOADS
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_BDI
 #define CONFIG_CMD_CONSOLE
@@ -87,28 +87,28 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_CONSOLE_IS_IN_ENV	/* stdin, stdout and stderr are in evironment */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* stdin, stdout and stderr are in evironment */
 #define CONFIG_PREBOOT
 
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"pati=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"pati=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	       /* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	       /* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00010000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x00A00000	/* 10 MB in SRAM			*/
+#define CONFIG_SYS_MEMTEST_START	0x00010000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x00A00000	/* 10 MB in SRAM			*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address		*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address		*/
 
-#define	CFG_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 1250000 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 1250000 }
 
 
 /***********************************************************************
@@ -123,41 +123,41 @@
 /*
  * Internal Memory Mapped (This is not the IMMR content)
  */
-#define CFG_IMMR		0x01C00000		/* Physical start adress of internal memory map */
+#define CONFIG_SYS_IMMR		0x01C00000		/* Physical start adress of internal memory map */
 
 /*
  * Definitions for initial stack pointer and data area
  */
-#define CFG_INIT_RAM_ADDR	(CFG_IMMR + 0x003f9800)	/* Physical start adress of internal MPC555 writable RAM */
-#define	CFG_INIT_RAM_END	(CFG_IMMR + 0x003fffff)	/* Physical end adress of internal MPC555 used RAM area	*/
-#define	CFG_GBL_DATA_SIZE	128			/* Size in bytes reserved for initial global data */
-#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
-#define	CFG_INIT_SP_ADDR	(CFG_IMMR + 0x03fa000)	/* Physical start adress of inital stack */
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_IMMR + 0x003f9800)	/* Physical start adress of internal MPC555 writable RAM */
+#define	CONFIG_SYS_INIT_RAM_END	(CONFIG_SYS_IMMR + 0x003fffff)	/* Physical end adress of internal MPC555 used RAM area	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	128			/* Size in bytes reserved for initial global data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_RAM_ADDR) - CONFIG_SYS_GBL_DATA_SIZE) /* Offset from the beginning of ram */
+#define	CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_IMMR + 0x03fa000)	/* Physical start adress of inital stack */
 /*
  * Start addresses for the final memory configuration
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000	/* Monitor won't change memory map			*/
-#define CFG_FLASH_BASE		0xffC00000	/* External flash */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000	/* Monitor won't change memory map			*/
+#define CONFIG_SYS_FLASH_BASE		0xffC00000	/* External flash */
 #define PCI_BASE		0x03000000	/* PCI Base (CS2) */
 #define PCI_CONFIG_BASE		0x04000000	/* PCI & PLD  (CS3) */
 #define PLD_CONFIG_BASE		0x04001000	/* PLD  (CS3) */
 
-#define	CFG_MONITOR_BASE	0xFFF00000
-/* CFG_FLASH_BASE	*/ /* TEXT_BASE is defined in the board config.mk file.	*/
+#define	CONFIG_SYS_MONITOR_BASE	0xFFF00000
+/* CONFIG_SYS_FLASH_BASE	*/ /* TEXT_BASE is defined in the board config.mk file.	*/
 						/* This adress is given to the linker with -Ttext to	*/
 						/* locate the text section at this adress.		*/
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 192 kB for Monitor				*/
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()				*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 192 kB for Monitor				*/
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()				*/
 
-#define CFG_RESET_ADDRESS	(PLD_CONFIG_BASE + 0x10)	 /* Adress which causes reset */
+#define CONFIG_SYS_RESET_ADDRESS	(PLD_CONFIG_BASE + 0x10)	 /* Adress which causes reset */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux		*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux		*/
 
 
 /*-----------------------------------------------------------------------
@@ -166,10 +166,10 @@
  *
  */
 
-#define CFG_MAX_FLASH_BANKS		1		/* Max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT		128		/* Max number of sectors on one chip	*/
-#define CFG_FLASH_ERASE_TOUT	180000		/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	600		/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS		1		/* Max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT		128		/* Max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	180000		/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	600		/* Timeout for Flash Write (in ms)	*/
 
 
 #define	CONFIG_ENV_IS_IN_EEPROM
@@ -181,14 +181,14 @@
 #undef  CONFIG_ENV_IS_IN_FLASH
 #ifdef	CONFIG_ENV_IS_IN_FLASH
 #define	CONFIG_ENV_SIZE		0x00002000		/* Set whole sector as env		*/
-#define CONFIG_ENV_OFFSET		((0 - CFG_FLASH_BASE) - CONFIG_ENV_SIZE)		/* Environment starts at this adress	*/
+#define CONFIG_ENV_OFFSET		((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE)		/* Environment starts at this adress	*/
 #endif
 
 
 #define CONFIG_SPI		1
-#define CFG_SPI_CS_USED	0x09 /* CS0 and CS3 are used */
-#define CFG_SPI_CS_BASE	0x08 /* CS3 is active low */
-#define CFG_SPI_CS_ACT	0x00 /* CS3 is active low */
+#define CONFIG_SYS_SPI_CS_USED	0x09 /* CS0 and CS3 are used */
+#define CONFIG_SYS_SPI_CS_BASE	0x08 /* CS3 is active low */
+#define CONFIG_SYS_SPI_CS_ACT	0x00 /* CS3 is active low */
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control
  * SYPCR can only be written once after reset!
@@ -197,10 +197,10 @@
  */
 #undef CONFIG_WATCHDOG
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWP)
 #endif	/* CONFIG_WATCHDOG */
 
@@ -209,14 +209,14 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register
@@ -225,7 +225,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF00
-#define CFG_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
 			 SCCR_COM01   | SCCR_DFNL000 | SCCR_DFNH000)
 
 /*-----------------------------------------------------------------------
@@ -233,7 +233,7 @@
  *-----------------------------------------------------------------------
  * Data show cycle
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle	*/
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle	*/
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register
@@ -241,47 +241,47 @@
  * Set all bits to 40 Mhz
  *
  */
-#define CFG_OSC_CLK	((uint)4000000)		/* Oscillator clock is 4MHz	*/
+#define CONFIG_SYS_OSC_CLK	((uint)4000000)		/* Oscillator clock is 4MHz	*/
 
 
-#define CFG_PLPRCR	(PLPRCR_MF_9 | PLPRCR_DIVF_0)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_MF_9 | PLPRCR_DIVF_0)
 
 /*-----------------------------------------------------------------------
  * UMCR - UIMB Module Configuration Register
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_UMCR	(UMCR_FSPEED)		/* IMB clock same as U-bus	*/
+#define CONFIG_SYS_UMCR	(UMCR_FSPEED)		/* IMB clock same as U-bus	*/
 
 /*-----------------------------------------------------------------------
  * ICTRL - I-Bus Support Control Register
  */
-#define CFG_ICTRL	(ICTRL_ISCT_SER_7)	/* Take out of serialized mode	*/
+#define CONFIG_SYS_ICTRL	(ICTRL_ISCT_SER_7)	/* Take out of serialized mode	*/
 
 /*-----------------------------------------------------------------------
  * USIU - Memory Controller Register
  *-----------------------------------------------------------------------
  */
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
-#define CFG_OR0_PRELIM		(0xffc00000) /* SCY is not used if external TA is set */
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
+#define CONFIG_SYS_OR0_PRELIM		(0xffc00000) /* SCY is not used if external TA is set */
 /* SDRAM */
-#define CFG_BR1_PRELIM		(CFG_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
-#define CFG_OR1_PRELIM		(OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
+#define CONFIG_SYS_OR1_PRELIM		(OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
 /* PCI */
-#define CFG_BR2_PRELIM		(PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
-#define CFG_OR2_PRELIM		(OR_ADDR_MK_FF)
+#define CONFIG_SYS_BR2_PRELIM		(PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
+#define CONFIG_SYS_OR2_PRELIM		(OR_ADDR_MK_FF)
 /* config registers: */
-#define CFG_BR3_PRELIM		(PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
-#define CFG_OR3_PRELIM		(0xffff0000)
+#define CONFIG_SYS_BR3_PRELIM		(PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
+#define CONFIG_SYS_OR3_PRELIM		(0xffff0000)
 
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* We don't realign the flash	*/
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* We don't realign the flash	*/
 
 /*-----------------------------------------------------------------------
  * DER - Timer Decrementer
  *-----------------------------------------------------------------------
  * Initialise to zero
  */
-#define CFG_DER			0x00000000
+#define CONFIG_SYS_DER			0x00000000
 
 
 /*
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
index 2837b51..4e39799 100644
--- a/include/configs/PCI405.h
+++ b/include/configs/PCI405.h
@@ -60,38 +60,24 @@
 
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-
-#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
 #define CONFIG_CMD_ELF
-#define CONFIG_CMD_DATE
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_EEPROM
 
-
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
@@ -101,43 +87,41 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#define CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #undef CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
@@ -158,98 +142,79 @@
 
 #define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0407	/* PCI Device ID: PCI-405	*/
-#define CFG_PCI_CLASSCODE	0x0280	/* PCI Class Code: Network/Other*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-
-#if 0 /* test-only */
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-#else
-#define CFG_PCI_PTM2LA	0xef600000	/* point to internal regs	*/
-#define CFG_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x00000000	/* Host: use this pci address	*/
-#endif
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0407	/* PCI Device ID: PCI-405	*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0280	/* PCI Class Code: Network/Other*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+
+#define CONFIG_SYS_PCI_PTM2LA	0xef600000	/* point to internal regs	*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x00000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFD0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFD0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#if 0 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#define CONFIG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
-#define CONFIG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))	/* Env	*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#else /* Use EEPROM for environment variables */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
 #define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
 #define CONFIG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars*/
 				   /* total size of a CAT24WC08 is 1024 bytes */
-#endif
 
-#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 /*
  * Init Memory Controller:
@@ -264,89 +229,80 @@
  */
 
 /* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (NVRAM/RTC) initialization					*/
-#define CFG_EBC_PB1AP		0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1	*/
-#define CFG_EBC_PB1CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB1AP		0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1	*/
+#define CONFIG_SYS_EBC_PB1CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 2 (CAN0, 1) initialization					*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-/*#define CFG_EBC_PB2AP		  0x038056C0  / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+/*#define CONFIG_SYS_EBC_PB2AP		  0x038056C0  / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 3 (FPGA internal) initialization					*/
-#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR		0xF041C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
-#define CFG_FPGA_BASE_ADDR	0xF0400000
+#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xF041C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
+#define CONFIG_SYS_FPGA_BASE_ADDR	0xF0400000
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
 /* FPGA internal regs */
-#define CFG_FPGA_MODE		0x00
-#define CFG_FPGA_STATUS		0x02
-#define CFG_FPGA_TS		0x04
-#define CFG_FPGA_TS_LOW		0x06
-#define CFG_FPGA_TS_CAP0	0x10
-#define CFG_FPGA_TS_CAP0_LOW	0x12
-#define CFG_FPGA_TS_CAP1	0x14
-#define CFG_FPGA_TS_CAP1_LOW	0x16
-#define CFG_FPGA_TS_CAP2	0x18
-#define CFG_FPGA_TS_CAP2_LOW	0x1a
-#define CFG_FPGA_TS_CAP3	0x1c
-#define CFG_FPGA_TS_CAP3_LOW	0x1e
+#define CONFIG_SYS_FPGA_MODE		0x00
+#define CONFIG_SYS_FPGA_STATUS		0x02
+#define CONFIG_SYS_FPGA_TS		0x04
+#define CONFIG_SYS_FPGA_TS_LOW		0x06
+#define CONFIG_SYS_FPGA_TS_CAP0	0x10
+#define CONFIG_SYS_FPGA_TS_CAP0_LOW	0x12
+#define CONFIG_SYS_FPGA_TS_CAP1	0x14
+#define CONFIG_SYS_FPGA_TS_CAP1_LOW	0x16
+#define CONFIG_SYS_FPGA_TS_CAP2	0x18
+#define CONFIG_SYS_FPGA_TS_CAP2_LOW	0x1a
+#define CONFIG_SYS_FPGA_TS_CAP3	0x1c
+#define CONFIG_SYS_FPGA_TS_CAP3_LOW	0x1e
 
 /* FPGA Mode Reg */
-#define CFG_FPGA_MODE_CF_RESET	0x0001
-#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
-#define CFG_FPGA_MODE_TS_CLEAR	0x2000
+#define CONFIG_SYS_FPGA_MODE_CF_RESET	0x0001
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CONFIG_SYS_FPGA_MODE_TS_CLEAR	0x2000
 
 /* FPGA Status Reg */
-#define CFG_FPGA_STATUS_DIP0	0x0001
-#define CFG_FPGA_STATUS_DIP1	0x0002
-#define CFG_FPGA_STATUS_DIP2	0x0004
-#define CFG_FPGA_STATUS_FLASH	0x0008
-#define CFG_FPGA_STATUS_TS_IRQ	0x1000
+#define CONFIG_SYS_FPGA_STATUS_DIP0	0x0001
+#define CONFIG_SYS_FPGA_STATUS_DIP1	0x0002
+#define CONFIG_SYS_FPGA_STATUS_DIP2	0x0004
+#define CONFIG_SYS_FPGA_STATUS_FLASH	0x0008
+#define CONFIG_SYS_FPGA_STATUS_TS_IRQ	0x1000
 
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00400000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00800000  /* FPGA done pin (ppc input)     */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00400000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00800000  /* FPGA done pin (ppc input)     */
 /* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support)   */
-#define CFG_FPGA_INIT_V12	0x00008000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE_V12	0x00010000  /* FPGA done pin (ppc input)     */
+#define CONFIG_SYS_FPGA_INIT_V12	0x00008000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE_V12	0x00010000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
-#if 0 /* test-only */
-#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
-#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-#else
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-#endif
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Internal Definitions
diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h
index b88a173..831a60d 100644
--- a/include/configs/PCI5441.h
+++ b/include/configs/PCI5441.h
@@ -30,27 +30,27 @@
 #define	CONFIG_PCI5441		1		/* PCI-5441 board	*/
 #define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
 
-#define CFG_RESET_ADDR		0x00000000	/* Hard-reset address	*/
-#define CFG_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
-#define CFG_NIOS_SYSID_BASE	0x00920828	/* System id address	*/
+#define CONFIG_SYS_RESET_ADDR		0x00000000	/* Hard-reset address	*/
+#define CONFIG_SYS_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
+#define CONFIG_SYS_NIOS_SYSID_BASE	0x00920828	/* System id address	*/
 #define	CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
 
 /*------------------------------------------------------------------------
  * CACHE -- the following will support II/s and II/f. The II/s does not
  * have dcache, so the cache instructions will behave as NOPs.
  *----------------------------------------------------------------------*/
-#define CFG_ICACHE_SIZE		4096		/* 4 KByte total	*/
-#define CFG_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
-#define CFG_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
-#define CFG_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
+#define CONFIG_SYS_ICACHE_SIZE		4096		/* 4 KByte total	*/
+#define CONFIG_SYS_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
+#define CONFIG_SYS_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
+#define CONFIG_SYS_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
 
 /*------------------------------------------------------------------------
  * MEMORY BASE ADDRESSES
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE		0x00000000	/* FLASH base addr	*/
-#define CFG_FLASH_SIZE		0x00800000	/* 8 MByte		*/
-#define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
-#define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
+#define CONFIG_SYS_FLASH_BASE		0x00000000	/* FLASH base addr	*/
+#define CONFIG_SYS_FLASH_SIZE		0x00800000	/* 8 MByte		*/
+#define CONFIG_SYS_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
+#define CONFIG_SYS_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
 
 /*------------------------------------------------------------------------
  * MEMORY ORGANIZATION
@@ -59,27 +59,27 @@
  *	-Global data is placed below the heap.
  *	-The stack is placed below global data (&grows down).
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(128 * 1024)	/* Reserve 128k		*/
-#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)	/* Reserve 128k		*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
 
 /*------------------------------------------------------------------------
  * FLASH (AM29LV065D)
  *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
-#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
-#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
-#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
-#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
 
 /*------------------------------------------------------------------------
- * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
- * CFG_RESET_ADDR, since we assume the monitor is stored at the
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
  * reset address, no? This will keep the environment in user region
  * of flash. NOTE: the monitor length must be multiple of sector size
  * (which is common practice).
@@ -87,22 +87,22 @@
 #define	CONFIG_ENV_IS_IN_FLASH	1		/* Environment in flash */
 #define CONFIG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
 #define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
-#define CONFIG_ENV_ADDR	(CFG_RESET_ADDR + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)
 
 /*------------------------------------------------------------------------
  * CONSOLE
  *----------------------------------------------------------------------*/
 #if defined(CONFIG_CONSOLE_JTAG)
-#define CFG_NIOS_CONSOLE	0x00920820	/* JTAG UART base addr	*/
+#define CONFIG_SYS_NIOS_CONSOLE	0x00920820	/* JTAG UART base addr	*/
 #else
-#define CFG_NIOS_CONSOLE	0x009208a0	/* UART base addr	*/
+#define CONFIG_SYS_NIOS_CONSOLE	0x009208a0	/* UART base addr	*/
 #endif
 
-#define CFG_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
+#define CONFIG_SYS_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
 #define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
-#define CFG_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
 
 /*------------------------------------------------------------------------
  * DEBUG
@@ -116,11 +116,11 @@
  * registers, we can slow it down to 10 msec using TMRCNT. If the default
  * period is acceptable, TMRCNT can be left undefined.
  *----------------------------------------------------------------------*/
-#define CFG_NIOS_TMRBASE	0x00920860	/* Tick timer base addr	*/
-#define CFG_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
-#define CFG_NIOS_TMRMS		10		/* 10 msec per tick	*/
-#define CFG_NIOS_TMRCNT	(CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define	CFG_HZ		(CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRBASE	0x00920860	/* Tick timer base addr	*/
+#define CONFIG_SYS_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
+#define CONFIG_SYS_NIOS_TMRMS		10		/* 10 msec per tick	*/
+#define CONFIG_SYS_NIOS_TMRCNT	(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
+#define	CONFIG_SYS_HZ		(CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
 
 
 /*
@@ -137,7 +137,7 @@
  */
 #define CONFIG_CMD_BDI
 #define CONFIG_CMD_ECHO
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_IMI
 #define CONFIG_CMD_IRQ
@@ -152,14 +152,14 @@
 /*------------------------------------------------------------------------
  * MISC
  *----------------------------------------------------------------------*/
-#define	CFG_LONGHELP				/* Provide extended help*/
-#define	CFG_PROMPT		"==> "		/* Command prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O buf size	*/
-#define	CFG_MAXARGS		16		/* Max command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot arg buf size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size	*/
-#define	CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* Default load address	*/
-#define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* Start addr for test	*/
-#define CFG_MEMTEST_END		CFG_INIT_SP - 0x00020000
+#define	CONFIG_SYS_LONGHELP				/* Provide extended help*/
+#define	CONFIG_SYS_PROMPT		"==> "		/* Command prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O buf size	*/
+#define	CONFIG_SYS_MAXARGS		16		/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot arg buf size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size	*/
+#define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE	/* Default load address	*/
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE	/* Start addr for test	*/
+#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_INIT_SP - 0x00020000
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h
index 048e896..5951d00 100644
--- a/include/configs/PCIPPC2.h
+++ b/include/configs/PCIPPC2.h
@@ -48,7 +48,7 @@
 
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		9600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_PREBOOT		""
 #define CONFIG_BOOTDELAY	5
@@ -89,51 +89,51 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 
 /* Print Buffer Size
  */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 
-#define	CFG_MAXARGS	64		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
+#define	CONFIG_SYS_MAXARGS	64		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE	    0x00000000
-#define CFG_FLASH_BASE	    0xFFF00000
-#define CFG_FLASH_MAX_SIZE  0x00100000
+#define CONFIG_SYS_SDRAM_BASE	    0x00000000
+#define CONFIG_SYS_FLASH_BASE	    0xFFF00000
+#define CONFIG_SYS_FLASH_MAX_SIZE  0x00100000
 /* Maximum amount of RAM.
  */
-#define CFG_MAX_RAM_SIZE    0x20000000  /* 512Mb			*/
+#define CONFIG_SYS_MAX_RAM_SIZE    0x20000000  /* 512Mb			*/
 
-#define CFG_RESET_ADDRESS   0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 
-#define CFG_MONITOR_BASE    TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
 
-#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
 
-#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \
-    CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE
-#define CFG_RAMBOOT
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \
+    CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef CFG_RAMBOOT
+#undef CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area
@@ -141,54 +141,54 @@
 
 /* Size in bytes reserved for initial data
  */
-#define CFG_GBL_DATA_SIZE    128
+#define CONFIG_SYS_GBL_DATA_SIZE    128
 
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x8000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET    CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_END      0x8000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_LOCK
 
 /*
  * Temporary buffer for serial data until the real serial driver
  * is initialised (memtest will destroy this buffer)
  */
-#define CFG_SCONSOLE_ADDR     CFG_INIT_RAM_ADDR
-#define CFG_SCONSOLE_SIZE     0x0002000
+#define CONFIG_SYS_SCONSOLE_ADDR     CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_SCONSOLE_SIZE     0x0002000
 
 /* SDRAM 0 - 256MB
  */
-#define CFG_DBAT0L	      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_DBAT0U	      (CFG_SDRAM_BASE | \
+#define CONFIG_SYS_DBAT0L	      (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT0U	      (CONFIG_SYS_SDRAM_BASE | \
 			       BATU_BL_256M | BATU_VS | BATU_VP)
 /* SDRAM 1 - 256MB
  */
-#define CFG_DBAT1L	      ((CFG_SDRAM_BASE + 0x10000000) | \
+#define CONFIG_SYS_DBAT1L	      ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
 			       BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_DBAT1U	      ((CFG_SDRAM_BASE + 0x10000000) | \
+#define CONFIG_SYS_DBAT1U	      ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
 			       BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* Init RAM in the CPU DCache (no backing memory)
  */
-#define CFG_DBAT2L	      (CFG_INIT_RAM_ADDR | \
+#define CONFIG_SYS_DBAT2L	      (CONFIG_SYS_INIT_RAM_ADDR | \
 			       BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_DBAT2U	      (CFG_INIT_RAM_ADDR | \
+#define CONFIG_SYS_DBAT2U	      (CONFIG_SYS_INIT_RAM_ADDR | \
 			       BATU_BL_128K | BATU_VS | BATU_VP)
 
 /* I/O and PCI memory at 0xf0000000
  */
-#define CFG_DBAT3L	      (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_DBAT3U	      (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT0L	      CFG_DBAT0L
-#define CFG_IBAT0U	      CFG_DBAT0U
-#define CFG_IBAT1L	      CFG_DBAT1L
-#define CFG_IBAT1U	      CFG_DBAT1U
-#define CFG_IBAT2L	      CFG_DBAT2L
-#define CFG_IBAT2U	      CFG_DBAT2U
-#define CFG_IBAT3L	      CFG_DBAT3L
-#define CFG_IBAT3U	      CFG_DBAT3U
+#define CONFIG_SYS_DBAT3L	      (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT3U	      (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT0L	      CONFIG_SYS_DBAT0L
+#define CONFIG_SYS_IBAT0U	      CONFIG_SYS_DBAT0U
+#define CONFIG_SYS_IBAT1L	      CONFIG_SYS_DBAT1L
+#define CONFIG_SYS_IBAT1U	      CONFIG_SYS_DBAT1U
+#define CONFIG_SYS_IBAT2L	      CONFIG_SYS_DBAT2L
+#define CONFIG_SYS_IBAT2U	      CONFIG_SYS_DBAT2U
+#define CONFIG_SYS_IBAT3L	      CONFIG_SYS_DBAT3L
+#define CONFIG_SYS_IBAT3U	      CONFIG_SYS_DBAT3U
 
 /*
  * Low Level Configuration Settings
@@ -196,48 +196,48 @@
  * You should know what you are doing if you make changes here.
  * For the detail description refer to the PCIPPC2 user's manual.
  */
-#define CFG_HZ		      1000
-#define CFG_BUS_HZ            100000000 /* bus speed - 100 mhz          */
-#define CFG_CPU_CLK	      300000000
-#define CFG_BUS_CLK	      100000000
+#define CONFIG_SYS_HZ		      1000
+#define CONFIG_SYS_BUS_HZ            100000000 /* bus speed - 100 mhz          */
+#define CONFIG_SYS_CPU_CLK	      300000000
+#define CONFIG_SYS_BUS_CLK	      100000000
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	      (8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	      (8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT	16	/* Max number of sectors in one bank	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	16	/* Max number of sectors in one bank	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
 /*
  * Note: environment is not EMBEDDED in the U-Boot code.
  * It's stored in flash separately.
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x70000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x70000)
 #define CONFIG_ENV_SIZE		0x1000	/* Size of the Environment		*/
 #define CONFIG_ENV_SECT_SIZE	0x10000 /* Size of the Environment Sector	*/
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SIZE	32
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /*
  * L2 cache
  */
-#undef CFG_L2
+#undef CONFIG_SYS_L2
 #define L2_INIT   (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 		   L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 #define L2_ENABLE (L2_INIT | L2CR_L2E)
@@ -254,10 +254,10 @@
  * Disk-On-Chip configuration
  */
 
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
+#define CONFIG_SYS_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
 
-#define CFG_DOC_SUPPORT_2000
-#undef CFG_DOC_SUPPORT_MILLENNIUM
+#define CONFIG_SYS_DOC_SUPPORT_2000
+#undef CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
 
 /*-----------------------------------------------------------------------
   RTC m48t59
@@ -269,7 +269,7 @@
 #define CONFIG_NET_MULTI			/* Multi ethernet cards support */
 
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
 #define CONFIG_TULIP
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h
index acaab7f..a683a8f 100644
--- a/include/configs/PCIPPC6.h
+++ b/include/configs/PCIPPC6.h
@@ -48,7 +48,7 @@
 
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		9600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_PREBOOT		""
 #define CONFIG_BOOTDELAY	5
@@ -91,51 +91,51 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 
 /* Print Buffer Size
  */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 
-#define CFG_MAXARGS	64		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
+#define CONFIG_SYS_MAXARGS	64		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE	    0x00000000
-#define CFG_FLASH_BASE	    0xFFF00000
-#define CFG_FLASH_MAX_SIZE  0x00100000
+#define CONFIG_SYS_SDRAM_BASE	    0x00000000
+#define CONFIG_SYS_FLASH_BASE	    0xFFF00000
+#define CONFIG_SYS_FLASH_MAX_SIZE  0x00100000
 /* Maximum amount of RAM.
  */
-#define CFG_MAX_RAM_SIZE    0x20000000	/* 512Mb			*/
+#define CONFIG_SYS_MAX_RAM_SIZE    0x20000000	/* 512Mb			*/
 
-#define CFG_RESET_ADDRESS   0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 
-#define CFG_MONITOR_BASE    TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
 
-#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
 
-#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \
-    CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE
-#define CFG_RAMBOOT
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \
+    CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef CFG_RAMBOOT
+#undef CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area
@@ -143,54 +143,54 @@
 
 /* Size in bytes reserved for initial data
  */
-#define CFG_GBL_DATA_SIZE    128
+#define CONFIG_SYS_GBL_DATA_SIZE    128
 
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x8000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET    CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_END      0x8000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_LOCK
 
 /*
  * Temporary buffer for serial data until the real serial driver
  * is initialised (memtest will destroy this buffer)
  */
-#define CFG_SCONSOLE_ADDR     CFG_INIT_RAM_ADDR
-#define CFG_SCONSOLE_SIZE     0x0002000
+#define CONFIG_SYS_SCONSOLE_ADDR     CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_SCONSOLE_SIZE     0x0002000
 
 /* SDRAM 0 - 256MB
  */
-#define CFG_DBAT0L	      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_DBAT0U	      (CFG_SDRAM_BASE | \
+#define CONFIG_SYS_DBAT0L	      (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT0U	      (CONFIG_SYS_SDRAM_BASE | \
 			       BATU_BL_256M | BATU_VS | BATU_VP)
 /* SDRAM 1 - 256MB
  */
-#define CFG_DBAT1L	      ((CFG_SDRAM_BASE + 0x10000000) | \
+#define CONFIG_SYS_DBAT1L	      ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
 			       BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_DBAT1U	      ((CFG_SDRAM_BASE + 0x10000000) | \
+#define CONFIG_SYS_DBAT1U	      ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
 			       BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* Init RAM in the CPU DCache (no backing memory)
  */
-#define CFG_DBAT2L	      (CFG_INIT_RAM_ADDR | \
+#define CONFIG_SYS_DBAT2L	      (CONFIG_SYS_INIT_RAM_ADDR | \
 			       BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_DBAT2U	      (CFG_INIT_RAM_ADDR | \
+#define CONFIG_SYS_DBAT2U	      (CONFIG_SYS_INIT_RAM_ADDR | \
 			       BATU_BL_128K | BATU_VS | BATU_VP)
 
 /* I/O and PCI memory at 0xf0000000
  */
-#define CFG_DBAT3L	      (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_DBAT3U	      (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT0L	      CFG_DBAT0L
-#define CFG_IBAT0U	      CFG_DBAT0U
-#define CFG_IBAT1L	      CFG_DBAT1L
-#define CFG_IBAT1U	      CFG_DBAT1U
-#define CFG_IBAT2L	      CFG_DBAT2L
-#define CFG_IBAT2U	      CFG_DBAT2U
-#define CFG_IBAT3L	      CFG_DBAT3L
-#define CFG_IBAT3U	      CFG_DBAT3U
+#define CONFIG_SYS_DBAT3L	      (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT3U	      (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT0L	      CONFIG_SYS_DBAT0L
+#define CONFIG_SYS_IBAT0U	      CONFIG_SYS_DBAT0U
+#define CONFIG_SYS_IBAT1L	      CONFIG_SYS_DBAT1L
+#define CONFIG_SYS_IBAT1U	      CONFIG_SYS_DBAT1U
+#define CONFIG_SYS_IBAT2L	      CONFIG_SYS_DBAT2L
+#define CONFIG_SYS_IBAT2U	      CONFIG_SYS_DBAT2U
+#define CONFIG_SYS_IBAT3L	      CONFIG_SYS_DBAT3L
+#define CONFIG_SYS_IBAT3U	      CONFIG_SYS_DBAT3U
 
 /*
  * Low Level Configuration Settings
@@ -198,48 +198,48 @@
  * You should know what you are doing if you make changes here.
  * For the detail description refer to the PCIPPC2 user's manual.
  */
-#define CFG_HZ		      1000
-#define CFG_BUS_HZ	      100000000 /* bus speed - 100 mhz		*/
-#define CFG_CPU_CLK	      300000000
-#define CFG_BUS_CLK	      100000000
+#define CONFIG_SYS_HZ		      1000
+#define CONFIG_SYS_BUS_HZ	      100000000 /* bus speed - 100 mhz		*/
+#define CONFIG_SYS_CPU_CLK	      300000000
+#define CONFIG_SYS_BUS_CLK	      100000000
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	      (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	      (8 << 20) /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT	16	/* Max number of sectors in one bank	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	16	/* Max number of sectors in one bank	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
 /*
  * Note: environment is not EMBEDDED in the U-Boot code.
  * It's stored in flash separately.
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x70000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x70000)
 #define CONFIG_ENV_SIZE		0x1000	/* Size of the Environment		*/
 #define CONFIG_ENV_SECT_SIZE	0x10000 /* Size of the Environment Sector	*/
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SIZE	32
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /*
  * L2 cache
  */
-#undef CFG_L2
+#undef CONFIG_SYS_L2
 #define L2_INIT	  (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 		   L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 #define L2_ENABLE (L2_INIT | L2CR_L2E)
@@ -256,10 +256,10 @@
  * Disk-On-Chip configuration
  */
 
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
+#define CONFIG_SYS_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
 
-#define CFG_DOC_SUPPORT_2000
-#undef CFG_DOC_SUPPORT_MILLENNIUM
+#define CONFIG_SYS_DOC_SUPPORT_2000
+#undef CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
 
 /*-----------------------------------------------------------------------
   RTC m48t59
@@ -271,17 +271,17 @@
 #define CONFIG_NET_MULTI		/* Multi ethernet cards support */
 
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
 #define CONFIG_TULIP
 
 
 #define CONFIG_SCSI_SYM53C8XX
 #define CONFIG_SCSI_DEV_ID	0x000B	/* 53c896 */
-#define CFG_SCSI_MAX_LUN	8	/* number of supported LUNs */
-#define CFG_SCSI_MAX_SCSI_ID	15	/* maximum SCSI ID (0..6) */
-#define CFG_SCSI_MAX_DEVICE	CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
-#define CFG_SCSI_SPIN_UP_TIME	2
-#define CFG_SCSI_SCAN_BUS_REVERSE 0
+#define CONFIG_SYS_SCSI_MAX_LUN	8	/* number of supported LUNs */
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	15	/* maximum SCSI ID (0..6) */
+#define CONFIG_SYS_SCSI_MAX_DEVICE	CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
+#define CONFIG_SYS_SCSI_SPIN_UP_TIME	2
+#define CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 0
 #define CONFIG_DOS_PARTITION
 #define CONFIG_MAC_PARTITION
 #define CONFIG_ISO_PARTITION
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index 895b89c..5c4d69b 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -79,8 +79,8 @@
 
 #define CONFIG_NAND_LEGACY
 
-#define	 CFG_HUSH_PARSER
-#define	 CFG_PROMPT_HUSH_PS2 "> "
+#define	 CONFIG_SYS_HUSH_PARSER
+#define	 CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 /**************************************************************
  * I2C Stuff:
  * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
@@ -90,21 +90,20 @@
  * The Atmel EEPROM uses 16Bit addressing.
  ***************************************************************/
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		50000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		50000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x53
-#define CFG_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
 #define CONFIG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 #define CONFIG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
 #define CONFIG_ENV_SIZE            0x800   /* 2 kBytes may be used for env vars */
 
-#undef CFG_I2C_EEPROM_ADDR_OVERFLOW
-#define CFG_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel 24C128/256 has	*/
+#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel 24C128/256 has	*/
 					/* 64 byte page write mode using*/
 					/* last	6 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_ENABLE	/* enable Page write */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
 
 /***************************************************************
@@ -135,54 +134,54 @@
 /***************************************************************
  * defines if the console is stored in the environment
  ***************************************************************/
-#define CFG_CONSOLE_IS_IN_ENV	/* stdin, stdout and stderr are in evironment */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* stdin, stdout and stderr are in evironment */
 /***************************************************************
  * defines if an overwrite_console function exists
  *************************************************************/
-#define CFG_CONSOLE_OVERWRITE_ROUTINE
-#define CFG_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
 /***************************************************************
  * defines if the overwrite_console should be stored in the
  * environment
  **************************************************************/
-#undef CFG_CONSOLE_ENV_OVERWRITE
+#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 
 /**************************************************************
  * loads config
  *************************************************************/
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MISC_INIT_R
 /***********************************************************
  * Miscellaneous configurable options
  **********************************************************/
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 1 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 1 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_BASE_BAUD       691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD       691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR		0x400000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -196,40 +195,40 @@
 #define CONFIG_PCI_HOST PCI_HOST_FORCE	/* configure as pci-host	*/
 #define CONFIG_PCI_PNP			/* pci plug-and-play		*/
 					/* resource configuration	*/
-#define CFG_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFF80000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserve 1024 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFF80000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserve 1024 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 /*
  * Init Memory Controller:
@@ -249,14 +248,14 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in On Chip SRAM)
  */
-#define CFG_TEMP_STACK_OCM	1
-#define CFG_OCM_DATA_ADDR	0xF0000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE	/* End of On Chip SRAM	       */
-#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE	/* End of On Chip SRAM	       */
+#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Internal Definitions
@@ -270,7 +269,7 @@
 /***********************************************************************
  * External peripheral base address
  ***********************************************************************/
-#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
 
 /***********************************************************************
  * Last Stage Init
@@ -279,6 +278,7 @@
 /************************************************************
  * Ethernet Stuff
  ***********************************************************/
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		1	/* PHY address			*/
 /************************************************************
@@ -290,15 +290,15 @@
 /************************************************************
  * IDE/ATA stuff
  ************************************************************/
-#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR	CFG_ISA_IO_BASE_ADDRESS /* base address */
-#define CFG_ATA_IDE0_OFFSET	0x01F0	/* ide0 offste */
-#define CFG_ATA_IDE1_OFFSET	0x0170	/* ide1 offset */
-#define CFG_ATA_DATA_OFFSET	0	/* data reg offset	*/
-#define CFG_ATA_REG_OFFSET	0	/* reg offset */
-#define CFG_ATA_ALT_OFFSET	0x200	/* alternate register offset */
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x01F0	/* ide0 offste */
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0x0170	/* ide1 offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0	/* data reg offset	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0	/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x200	/* alternate register offset */
 
 #undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
 #undef	CONFIG_IDE_LED			/* no led for ide supported	*/
@@ -315,18 +315,18 @@
  * SCSI support (experimental) only SYM53C8xx supported
  ************************************************************/
 #define CONFIG_SCSI_SYM53C8XX
-#define CFG_SCSI_MAX_LUN	8	/* number of supported LUNs */
-#define CFG_SCSI_MAX_SCSI_ID	7	/* maximum SCSI ID (0..6) */
-#define CFG_SCSI_MAX_DEVICE	CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
-#define CFG_SCSI_SPIN_UP_TIME	2
+#define CONFIG_SYS_SCSI_MAX_LUN	8	/* number of supported LUNs */
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	7	/* maximum SCSI ID (0..6) */
+#define CONFIG_SYS_SCSI_MAX_DEVICE	CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
+#define CONFIG_SYS_SCSI_SPIN_UP_TIME	2
 
 /************************************************************
  * Disk-On-Chip configuration
  ************************************************************/
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
-#define CFG_DOC_SHORT_TIMEOUT
-#define CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
+#define CONFIG_SYS_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
+#define CONFIG_SYS_DOC_SHORT_TIMEOUT
+#define CONFIG_SYS_DOC_SUPPORT_2000
+#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
 
 /************************************************************
  * DISK Partition support
@@ -360,7 +360,7 @@
 #define CONFIG_USB_STORAGE
 
 /* Enable needed helper functions */
-#define CFG_DEVICE_DEREGISTER		/* needs device_deregister */
+#define CONFIG_SYS_DEVICE_DEREGISTER		/* needs device_deregister */
 
 /************************************************************
  * Debug support
diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h
index 5d2bc2f..522349f 100644
--- a/include/configs/PK1C20.h
+++ b/include/configs/PK1C20.h
@@ -30,29 +30,29 @@
 #define CONFIG_PK1C20		1		/* PK1C20 board		*/
 #define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
 
-#define CFG_RESET_ADDR		0x00000000	/* Hard-reset address	*/
-#define CFG_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
-#define CFG_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
+#define CONFIG_SYS_RESET_ADDR		0x00000000	/* Hard-reset address	*/
+#define CONFIG_SYS_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
+#define CONFIG_SYS_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
 
 /*------------------------------------------------------------------------
  * CACHE -- the following will support II/s and II/f. The II/s does not
  * have dcache, so the cache instructions will behave as NOPs.
  *----------------------------------------------------------------------*/
-#define CFG_ICACHE_SIZE		4096		/* 4 KByte total	*/
-#define CFG_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
-#define CFG_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
-#define CFG_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
+#define CONFIG_SYS_ICACHE_SIZE		4096		/* 4 KByte total	*/
+#define CONFIG_SYS_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
+#define CONFIG_SYS_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
+#define CONFIG_SYS_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
 
 /*------------------------------------------------------------------------
  * MEMORY BASE ADDRESSES
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE		0x00000000	/* FLASH base addr	*/
-#define CFG_FLASH_SIZE		0x00800000	/* 8 MByte		*/
-#define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
-#define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
-#define CFG_SRAM_BASE		0x02000000	/* SRAM base addr	*/
-#define CFG_SRAM_SIZE		0x00100000	/* 1 MB (only 1M mapped)*/
+#define CONFIG_SYS_FLASH_BASE		0x00000000	/* FLASH base addr	*/
+#define CONFIG_SYS_FLASH_SIZE		0x00800000	/* 8 MByte		*/
+#define CONFIG_SYS_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
+#define CONFIG_SYS_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
+#define CONFIG_SYS_SRAM_BASE		0x02000000	/* SRAM base addr	*/
+#define CONFIG_SYS_SRAM_SIZE		0x00100000	/* 1 MB (only 1M mapped)*/
 
 /*------------------------------------------------------------------------
  * MEMORY ORGANIZATION
@@ -61,27 +61,27 @@
  *	-Global data is placed below the heap.
  *	-The stack is placed below global data (&grows down).
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 128k		*/
-#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 128k		*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
 
 /*------------------------------------------------------------------------
  * FLASH (AM29LV065D)
  *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
-#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
-#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
-#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
-#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
 
 /*------------------------------------------------------------------------
- * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
- * CFG_RESET_ADDR, since we assume the monitor is stored at the
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
  * reset address, no? This will keep the environment in user region
  * of flash. NOTE: the monitor length must be multiple of sector size
  * (which is common practice).
@@ -89,30 +89,30 @@
 #define CONFIG_ENV_IS_IN_FLASH	1		/* Environment in flash */
 #define CONFIG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
 #define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
-#define CONFIG_ENV_ADDR	(CFG_RESET_ADDR + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)
 
 /*------------------------------------------------------------------------
  * CONSOLE
  *----------------------------------------------------------------------*/
 #if defined(CONFIG_CONSOLE_JTAG)
-#define CFG_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
+#define CONFIG_SYS_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
 #else
-#define CFG_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
+#define CONFIG_SYS_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
 #endif
 
-#define CFG_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
+#define CONFIG_SYS_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
 #define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
-#define CFG_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
 
 /*------------------------------------------------------------------------
- * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for
+ * EPCS Device -- wne CONFIG_SYS_NIOS_EPCSBASE is defined code/commands for
  * epcs device access is enabled. The base address is the epcs
  * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
  * The register base is currently at offset 0x600 from the memory base.
  *----------------------------------------------------------------------*/
-#define CFG_NIOS_EPCSBASE	0x02100200	/* EPCS register base	*/
+#define CONFIG_SYS_NIOS_EPCSBASE	0x02100200	/* EPCS register base	*/
 
 /*------------------------------------------------------------------------
  * DEBUG
@@ -126,23 +126,23 @@
  * registers, we can slow it down to 10 msec using TMRCNT. If the default
  * period is acceptable, TMRCNT can be left undefined.
  *----------------------------------------------------------------------*/
-#define CFG_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
-#define CFG_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
-#define CFG_NIOS_TMRMS		10		/* 10 msec per tick	*/
-#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define CFG_HZ		(CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
+#define CONFIG_SYS_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
+#define CONFIG_SYS_NIOS_TMRMS		10		/* 10 msec per tick	*/
+#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
+#define CONFIG_SYS_HZ		(CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
 
 /*------------------------------------------------------------------------
  * STATUS LED -- Provides a simple blinking led. For Nios2 each board
  * must implement its own led routines -- leds are, after all,
  * board-specific, no?
  *----------------------------------------------------------------------*/
-#define CFG_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
+#define CONFIG_SYS_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
 #define CONFIG_STATUS_LED			/* Enable status driver */
 
 #define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
 #define STATUS_LED_STATE	1		/* Blinking		*/
-#define STATUS_LED_PERIOD	(500/CFG_NIOS_TMRMS) /* Every 500 msec	*/
+#define STATUS_LED_PERIOD	(500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec	*/
 
 /*------------------------------------------------------------------------
  * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
@@ -177,7 +177,7 @@
 #define CONFIG_CMD_BDI
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ECHO
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_IMI
 #define CONFIG_CMD_IRQ
@@ -196,21 +196,21 @@
  *----------------------------------------------------------------------*/
 #if defined(CONFIG_CMD_IDE)
 #define CONFIG_IDE_PREINIT			/* Implement id_preinit	*/
-#define CFG_IDE_MAXBUS		1		/* 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1		/* 1 drive per IDE bus	*/
-
-#define CFG_ATA_BASE_ADDR	0x00900800	/* ATA base addr	*/
-#define CFG_ATA_IDE0_OFFSET	0x0000		/* IDE0 offset		*/
-#define CFG_ATA_DATA_OFFSET	0x0040		/* Data IO offset	*/
-#define CFG_ATA_REG_OFFSET	0x0040		/* Register offset	*/
-#define CFG_ATA_ALT_OFFSET	0x0100		/* Alternate reg offset	*/
-#define CFG_ATA_STRIDE          4		/* Width betwix addrs	*/
+#define CONFIG_SYS_IDE_MAXBUS		1		/* 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1		/* 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0x00900800	/* ATA base addr	*/
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000		/* IDE0 offset		*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0040		/* Data IO offset	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0040		/* Register offset	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100		/* Alternate reg offset	*/
+#define CONFIG_SYS_ATA_STRIDE          4		/* Width betwix addrs	*/
 #define CONFIG_DOS_PARTITION
 
 /* Board-specific cf regs */
-#define CFG_CF_PRESENT		0x00900880	/* CF Present PIO base	*/
-#define CFG_CF_POWER		0x00900890	/* CF Power FET PIO base*/
-#define CFG_CF_ATASEL		0x009008a0	/* CF ATASEL PIO base	*/
+#define CONFIG_SYS_CF_PRESENT		0x00900880	/* CF Present PIO base	*/
+#define CONFIG_SYS_CF_POWER		0x00900890	/* CF Power FET PIO base*/
+#define CONFIG_SYS_CF_ATASEL		0x009008a0	/* CF ATASEL PIO base	*/
 
 #endif
 
@@ -218,23 +218,23 @@
  * JFFS2
  *----------------------------------------------------------------------*/
 #if defined(CONFIG_CMD_JFFS2)
-#define CFG_JFFS_CUSTOM_PART			/* board defined part	*/
+#define CONFIG_SYS_JFFS_CUSTOM_PART			/* board defined part	*/
 #endif
 
 /*------------------------------------------------------------------------
  * MISC
  *----------------------------------------------------------------------*/
-#define CFG_LONGHELP				/* Provide extended help*/
-#define CFG_PROMPT		"==> "		/* Command prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O buf size */
-#define CFG_MAXARGS		16		/* Max command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot arg buf size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
-#define CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* Default load address */
-#define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* Start addr for test	*/
-#define CFG_MEMTEST_END		CFG_INIT_SP - 0x00020000
-
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP				/* Provide extended help*/
+#define CONFIG_SYS_PROMPT		"==> "		/* Command prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16		/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot arg buf size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE	/* Default load address */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE	/* Start addr for test	*/
+#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_INIT_SP - 0x00020000
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 8463ed5..7f2337b 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -49,11 +49,12 @@
 
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_NET_MULTI	1
 #undef  CONFIG_HAS_ETH1
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
@@ -103,53 +104,52 @@
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
+#define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
 #undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
@@ -166,23 +166,22 @@
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*
  * NAND-FLASH stuff
  */
-#define CFG_NAND_BASE_LIST	{CFG_NAND_BASE}
-#define NAND_MAX_CHIPS          1
-#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
 #define NAND_BIG_DELAY_US	25
 
-#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
-#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
-#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
-#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
+#define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
-#define CFG_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
-#define CFG_NAND_QUIET          1
+#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
+#define CONFIG_SYS_NAND_QUIET          1
 
 /*
  * PCI stuff
@@ -200,15 +199,15 @@
 
 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xf8000001      /* 128MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x08000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  0xf8000001      /* 128MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI 0x08000000      /* Host: use this pci address   */
 
 /*
  * IDE/ATA stuff
@@ -217,58 +216,58 @@
 #undef	CONFIG_IDE_LED			/* no led for ide supported	*/
 #define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
 
-#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
 /* max. 1 drives per IDE bus */
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1)
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1)
 
-#define CFG_ATA_BASE_ADDR	0xF0100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
-#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register access */
-#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register access */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*
  * FLASH organization
  */
 #define FLASH_BASE0_PRELIM	0xFFC00000 /* FLASH bank #0 */
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms) */
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width) */
-#define CFG_FLASH_ADDR0		0x5555	/* 1st addr for flash config cycles */
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd addr for flash config cycles */
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width) */
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st addr for flash config cycles */
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd addr for flash config cycles */
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard */
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard */
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard */
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard */
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard */
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector */
 
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFA0000
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384kB for Monitor */
-#define CFG_MALLOC_LEN		(384 * 1024)	/* Reserve 384kB for malloc() */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFA0000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)	/* Reserve 384kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(384 * 1024)	/* Reserve 384kB for malloc() */
 
 /*
  * Environment Variable setup
@@ -281,21 +280,20 @@
  * I2C EEPROM (24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM 24WC16 */
-#define CFG_EEPROM_WREN         1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM 24WC16 */
+#define CONFIG_SYS_EEPROM_WREN         1
 
 /* 24WC16 */
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The 24WC16 has   */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The 24WC16 has   */
 					/* 16 byte page write mode using */
 					/* last 4 bits of the address   */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 /*
  * External Bus Controller (EBC) Setup
@@ -305,69 +303,69 @@
 #define DUART1_BA	0xF0000408	    /* DUART Base Address       */
 #define RTC_BA		0xF0000500	    /* RTC Base Address         */
 #define VGA_BA		0xF1000000	    /* Epson VGA Base Address   */
-#define CFG_NAND_BASE	0xF4000000	    /* NAND FLASH Base Address  */
+#define CONFIG_SYS_NAND_BASE	0xF4000000	    /* NAND FLASH Base Address  */
 
 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
 /* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CFG_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-#define CFG_EBC_PB0CR		0xFFC5A000
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000
 
 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
-#define CFG_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
-#define CFG_EBC_PB1CR		0xF4018000
+#define CONFIG_SYS_EBC_PB1CR		0xF4018000
 
 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2AP		0x010053C0
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0
 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-#define CFG_EBC_PB2CR		0xF0018000
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000
 
 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3AP		0x010053C0
+#define CONFIG_SYS_EBC_PB3AP		0x010053C0
 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-#define CFG_EBC_PB3CR		0xF011A000
+#define CONFIG_SYS_EBC_PB3CR		0xF011A000
 
 /*
  * FPGA stuff
  */
-#define CFG_FPGA_BASE_ADDR 0xF0100100	    /* FPGA internal Base Address */
+#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100	    /* FPGA internal Base Address */
 
 /* FPGA internal regs */
-#define CFG_FPGA_CTRL		0x000
+#define CONFIG_SYS_FPGA_CTRL		0x000
 
 /* FPGA Control Reg */
-#define CFG_FPGA_CTRL_CF_RESET	0x0001
-#define CFG_FPGA_CTRL_WDI	0x0002
-#define CFG_FPGA_CTRL_PS2_RESET 0x0020
+#define CONFIG_SYS_FPGA_CTRL_CF_RESET	0x0001
+#define CONFIG_SYS_FPGA_CTRL_WDI	0x0002
+#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
 
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now */
-#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now */
+#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output) */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output) */
-#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input) */
-#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input) */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output) */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output) */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input) */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input) */
 
 /*
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM */
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM  */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM  */
 
-#define CFG_GBL_DATA_SIZE      128 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE      128 /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Definitions for GPIO setup (PPC405EP specific)
@@ -381,16 +379,16 @@
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  */
-#define CFG_GPIO0_OSRH		0x00000550
-#define CFG_GPIO0_OSRL		0x00000110
-#define CFG_GPIO0_ISR1H		0x00000000
-#define CFG_GPIO0_ISR1L		0x15555445
-#define CFG_GPIO0_TSRH		0x00000000
-#define CFG_GPIO0_TSRL		0x00000000
-#define CFG_GPIO0_TCR		0x77FE0014
+#define CONFIG_SYS_GPIO0_OSRH		0x00000550
+#define CONFIG_SYS_GPIO0_OSRL		0x00000110
+#define CONFIG_SYS_GPIO0_ISR1H		0x00000000
+#define CONFIG_SYS_GPIO0_ISR1L		0x15555445
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0x77FE0014
 
-#define CFG_DUART_RST		(0x80000000 >> 14)
-#define CFG_EEPROM_WP		(0x80000000 >> 0)
+#define CONFIG_SYS_DUART_RST		(0x80000000 >> 14)
+#define CONFIG_SYS_EEPROM_WP		(0x80000000 >> 0)
 
 /*
  * Internal Definitions
@@ -422,9 +420,9 @@
  */
 #define CONFIG_USB_OHCI_NEW	1
 #define CONFIG_PCI_OHCI		1
-#define CFG_OHCI_SWAP_REG_ACCESS 1
-#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
-#define CFG_USB_OHCI_SLOT_NAME	"ohci_pci"
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ohci_pci"
 #define CONFIG_USB_STORAGE	1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
index 2676d7d..ff73ef9 100644
--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -33,7 +33,7 @@
 #define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
 #define CONFIG_PM520		1	/* ... on PM520 board */
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */
 
 #define CONFIG_MISC_INIT_R
 
@@ -47,7 +47,7 @@
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
 #define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 
 #ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
@@ -72,7 +72,7 @@
 #define CONFIG_NET_MULTI	1
 #define CONFIG_MII		1
 #define CONFIG_EEPRO100		1
-#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
 #undef  CONFIG_NS8382X
 
 #endif
@@ -161,42 +161,42 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 #endif
 /*
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
 
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration
  */
-#define CFG_I2C_EEPROM_ADDR		0x58
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 
 /*
  * RTC configuration
  */
 #define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR		0x51
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
 
 /*
  * Disk-On-Chip configuration
  */
 
-#define CFG_DOC_SHORT_TIMEOUT
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
+#define CONFIG_SYS_DOC_SHORT_TIMEOUT
+#define CONFIG_SYS_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
 
-#define CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
-#define CFG_DOC_BASE		0xE0000000
-#define CFG_DOC_SIZE		0x00100000
+#define CONFIG_SYS_DOC_SUPPORT_2000
+#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
+#define CONFIG_SYS_DOC_BASE		0xE0000000
+#define CONFIG_SYS_DOC_SIZE		0x00100000
 
 #if defined(CONFIG_BOOT_ROM)
 /*
@@ -208,10 +208,10 @@
  *               0xFD000000 for 16 MB
  *               0xFD800000 for  8 MB
  */
-#define CFG_FLASH_BASE		0xFA000000
-#define CFG_FLASH_SIZE		0x04000000
-#define CFG_BOOTROM_BASE	0xFFF00000
-#define CFG_BOOTROM_SIZE	0x00080000
+#define CONFIG_SYS_FLASH_BASE		0xFA000000
+#define CONFIG_SYS_FLASH_SIZE		0x04000000
+#define CONFIG_SYS_BOOTROM_BASE	0xFFF00000
+#define CONFIG_SYS_BOOTROM_SIZE	0x00080000
 #define CONFIG_ENV_ADDR		(0xFDF00000 + 0x40000)
 #else
 /*
@@ -223,19 +223,19 @@
  *               0xFF000000 for 16 MB
  *               0xFF800000 for  8 MB
  */
-#define CFG_FLASH_BASE		0xFC000000
-#define CFG_FLASH_SIZE		0x04000000
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_SIZE		0x04000000
 #define CONFIG_ENV_ADDR		(0xFFF00000 + 0x40000)
 #endif
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
 
-#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
 
 #define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
 
@@ -253,104 +253,105 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xf0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xf0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
 /*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
  */
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
 #define CONFIG_PHY_ADDR		0x00
 
 /*
  * GPIO configuration
  */
-#define CFG_GPS_PORT_CONFIG	0x10000004
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x10000004
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*
  * Various low-level settings
  */
 #if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 #else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
 #endif
 
 #if defined(CONFIG_BOOT_ROM)
-#define CFG_BOOTCS_START	CFG_BOOTROM_BASE
-#define CFG_BOOTCS_SIZE		CFG_BOOTROM_SIZE
-#define CFG_BOOTCS_CFG		0x00047800
-#define CFG_CS0_START		CFG_BOOTROM_BASE
-#define CFG_CS0_SIZE		CFG_BOOTROM_SIZE
-#define CFG_CS1_START		CFG_FLASH_BASE
-#define CFG_CS1_SIZE		CFG_FLASH_SIZE
-#define CFG_CS1_CFG		0x0004FF00
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_BOOTROM_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_BOOTROM_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047800
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_BOOTROM_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_BOOTROM_SIZE
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS1_CFG		0x0004FF00
 #else
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x0004FF00
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
-#define CFG_CS1_START		CFG_DOC_BASE
-#define CFG_CS1_SIZE		CFG_DOC_SIZE
-#define CFG_CS1_CFG		0x00047800
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x0004FF00
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_DOC_BASE
+#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_DOC_SIZE
+#define CONFIG_SYS_CS1_CFG		0x00047800
 #endif
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
 
-#define CFG_RESET_ADDRESS	0xff000000
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
 
 /*-----------------------------------------------------------------------
  * USB stuff
@@ -372,23 +373,23 @@
 #undef	CONFIG_IDE_RESET		/* reset for ide supported	*/
 #define CONFIG_IDE_PREINIT
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	2	/* max. 2 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(0x0060)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005C)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
 
 /* Interval between registers                                                */
-#define CFG_ATA_STRIDE          4
+#define CONFIG_SYS_ATA_STRIDE          4
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/PM826.h b/include/configs/PM826.h
index f625361..b58f529 100644
--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -28,7 +28,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#undef CFG_RAMBOOT
+#undef CONFIG_SYS_RAMBOOT
 
 /*
  * High Level Configuration Options
@@ -55,8 +55,8 @@
 /* enable I2C and select the hardware/software driver */
 #undef  CONFIG_HARD_I2C
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-# define CFG_I2C_SPEED		50000
-# define CFG_I2C_SLAVE		0xFE
+# define CONFIG_SYS_I2C_SPEED		50000
+# define CONFIG_SYS_I2C_SLAVE		0xFE
 /*
  * Software (bit-bang) I2C driver configuration
  */
@@ -72,7 +72,7 @@
 
 
 #define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR	0x51
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51
 
 /*
  * select serial console configuration
@@ -117,25 +117,25 @@
  * - Tx-CLK is CLK10
  */
 #define	CONFIG_ETHER_ON_FCC1
-# define CFG_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
 #ifndef CONFIG_DB_CR826_J30x_ON
-# define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
+# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
 #else
-# define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
+# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
 #endif
 /*
  * - Rx-CLK is CLK15
  * - Tx-CLK is CLK14
  */
 #define	CONFIG_ETHER_ON_FCC2
-# define CFG_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 /*
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 #define CONFIG_8260_CLKIN	64000000	/* in Hz */
@@ -147,7 +147,7 @@
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -186,88 +186,88 @@
  * Disk-On-Chip configuration
  */
 
-#define CFG_DOC_SHORT_TIMEOUT
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
+#define CONFIG_SYS_DOC_SHORT_TIMEOUT
+#define CONFIG_SYS_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
 
-#define CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
+#define CONFIG_SYS_DOC_SUPPORT_2000
+#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
 
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define	CFG_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
+#define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * Flash and Boot ROM mapping
  */
 #ifdef CONFIG_FLASH_32MB
-#define	CFG_FLASH0_BASE		0x40000000
-#define	CFG_FLASH0_SIZE		0x02000000
+#define	CONFIG_SYS_FLASH0_BASE		0x40000000
+#define	CONFIG_SYS_FLASH0_SIZE		0x02000000
 #else
-#define	CFG_FLASH0_BASE		0xFF000000
-#define	CFG_FLASH0_SIZE		0x00800000
+#define	CONFIG_SYS_FLASH0_BASE		0xFF000000
+#define	CONFIG_SYS_FLASH0_SIZE		0x00800000
 #endif
-#define	CFG_BOOTROM_BASE	0xFF800000
-#define	CFG_BOOTROM_SIZE	0x00080000
-#define CFG_DOC_BASE		0xFF800000
-#define CFG_DOC_SIZE		0x00100000
+#define	CONFIG_SYS_BOOTROM_BASE	0xFF800000
+#define	CONFIG_SYS_BOOTROM_SIZE	0x00080000
+#define CONFIG_SYS_DOC_BASE		0xFF800000
+#define CONFIG_SYS_DOC_SIZE		0x00100000
 
 /* Flash bank size (for preliminary settings)
  */
-#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
+#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
 #ifdef CONFIG_FLASH_32MB
-#define CFG_MAX_FLASH_SECT	135	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	135	/* max num of sects on one chip */
 #else
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
 #endif
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
 
 #if 0
 /* Start port with environment in flash; switch to EEPROM later */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE+0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x40000)
 #define CONFIG_ENV_SIZE		0x40000
 #define CONFIG_ENV_SECT_SIZE	0x40000
 #else
 /* Final version: environment in EEPROM */
 #define CONFIG_ENV_IS_IN_EEPROM	1
-#define CFG_I2C_EEPROM_ADDR	0x58
-#define CFG_I2C_EEPROM_ADDR_LEN	1
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x58
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 #define CONFIG_ENV_OFFSET		512
 #define CONFIG_ENV_SIZE		(2048 - 512)
 #endif
@@ -275,61 +275,61 @@
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  *
- * if you change bits in the HRCW, you must also change the CFG_*
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
  * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
  */
 #if defined(CONFIG_BOOT_ROM)
-#define CFG_HRCW_MASTER		(HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
 #else
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
 #endif
 
 /* no slaves so just fill with zeros */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR		0xF0000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  *
- * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
+ * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
  * is mapped at SDRAM_BASE2_PRELIM.
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		CFG_FLASH0_BASE
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-# define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT
 #endif
 
 #ifdef	CONFIG_PCI
 #define CONFIG_PCI_PNP
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
 #endif
 
 /*
@@ -344,9 +344,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -359,17 +359,17 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 				HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL  (HID0_ICE|HID0_IFEM|HID0_ABE)
-#define CFG_HID2        0
+#define CONFIG_SYS_HID0_FINAL  (HID0_ICE|HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2        0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register                                     5-5
  *-----------------------------------------------------------------------
  * turn on Checkstop Reset Enable
  */
-#define CFG_RMR         RMR_CSRE
+#define CONFIG_SYS_RMR         RMR_CSRE
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration                                       4-25
@@ -377,16 +377,16 @@
  */
 
 #define BCR_APD01       0x10000000
-#define CFG_BCR         (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
+#define CONFIG_SYS_BCR         (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration                             4-31
  *-----------------------------------------------------------------------
  */
 #if 0
-#define CFG_SIUMCR	(SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
 #else
-#define CFG_SIUMCR	(SIUMCR_DPPC10|SIUMCR_APPC10)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC10|SIUMCR_APPC10)
 #endif
 
 
@@ -397,10 +397,10 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
@@ -410,7 +410,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control                 4-42
@@ -418,19 +418,19 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control                                   9-8
  *-----------------------------------------------------------------------
  */
-#define CFG_SCCR        (SCCR_DFBRG00)
+#define CONFIG_SYS_SCCR        (SCCR_DFBRG00)
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration                         13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR        0
+#define CONFIG_SYS_RCCR        0
 
 /*
  * Init Memory Controller:
@@ -444,34 +444,34 @@
 
 	/* Initialize SDRAM on local bus
 	 */
-#define CFG_INIT_LOCAL_SDRAM
+#define CONFIG_SYS_INIT_LOCAL_SDRAM
 
 
 /* Minimum mask to separate preliminary
  * address ranges for CS[0:2]
  */
-#define CFG_MIN_AM_MASK	0xC0000000
+#define CONFIG_SYS_MIN_AM_MASK	0xC0000000
 
 /*
  * we use the same values for 32 MB and 128 MB SDRAM
  * refresh rate = 7.73 uS (64 MHz Bus Clock)
  */
-#define CFG_MPTPR       0x2000
-#define CFG_PSRT        0x0E
+#define CONFIG_SYS_MPTPR       0x2000
+#define CONFIG_SYS_PSRT        0x0E
 
-#define CFG_MRS_OFFS	0x00000000
+#define CONFIG_SYS_MRS_OFFS	0x00000000
 
 
 #if defined(CONFIG_BOOT_ROM)
 /*
  * Bank 0 - Boot ROM (8 bit wide)
  */
-#define CFG_BR0_PRELIM	((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 			 BRx_PS_8			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_BOOTROM_SIZE)	|\
+#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_3_CLK			|\
@@ -481,12 +481,12 @@
 /*
  * Bank 1 - Flash (64 bit wide)
  */
-#define CFG_BR1_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_64			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
+#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_3_CLK			|\
@@ -498,12 +498,12 @@
 /*
  * Bank 0 - Flash (64 bit wide)
  */
-#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_64                      |\
 			 BRx_MS_GPCM_P                  |\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
+#define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
 			 ORxG_CSNT                      |\
 			 ORxG_ACS_DIV1                  |\
 			 ORxG_SCY_3_CLK                 |\
@@ -513,12 +513,12 @@
 /*
  * Bank 1 - Disk-On-Chip
  */
-#define CFG_BR1_PRELIM	((CFG_DOC_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_8			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_DOC_SIZE)	|\
+#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_3_CLK			|\
@@ -530,20 +530,20 @@
 /* Bank 2 - SDRAM
  */
 
-#ifndef CFG_RAMBOOT
-#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_64                      |\
 			 BRx_MS_SDRAM_P                 |\
 			 BRx_V)
 
 	/* SDRAM initialization values for 8-column chips
 	 */
-#define CFG_OR2_8COL    (CFG_MIN_AM_MASK	        |\
+#define CONFIG_SYS_OR2_8COL    (CONFIG_SYS_MIN_AM_MASK	        |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI0_A9             |\
 			 ORxS_NUMR_12)
 
-#define CFG_PSDMR_8COL  (PSDMR_SDAM_A13_IS_A5           |\
+#define CONFIG_SYS_PSDMR_8COL  (PSDMR_SDAM_A13_IS_A5           |\
 			 PSDMR_BSMA_A14_A16             |\
 			 PSDMR_SDA10_PBI0_A10           |\
 			 PSDMR_RFRC_7_CLK               |\
@@ -555,12 +555,12 @@
 
 	/* SDRAM initialization values for 9-column chips
 	 */
-#define CFG_OR2_9COL    (CFG_MIN_AM_MASK                |\
+#define CONFIG_SYS_OR2_9COL    (CONFIG_SYS_MIN_AM_MASK                |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI0_A7             |\
 			 ORxS_NUMR_13)
 
-#define CFG_PSDMR_9COL  (PSDMR_SDAM_A14_IS_A5           |\
+#define CONFIG_SYS_PSDMR_9COL  (PSDMR_SDAM_A14_IS_A5           |\
 			 PSDMR_BSMA_A13_A15             |\
 			 PSDMR_SDA10_PBI0_A9            |\
 			 PSDMR_RFRC_7_CLK               |\
@@ -570,9 +570,9 @@
 			 PSDMR_WRC_1C                   |\
 			 PSDMR_CL_2)
 
-#define CFG_OR2_PRELIM   CFG_OR2_9COL
-#define CFG_PSDMR        CFG_PSDMR_9COL
+#define CONFIG_SYS_OR2_PRELIM   CONFIG_SYS_OR2_9COL
+#define CONFIG_SYS_PSDMR        CONFIG_SYS_PSDMR_9COL
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/PM828.h b/include/configs/PM828.h
index f437d21..96c86f7 100644
--- a/include/configs/PM828.h
+++ b/include/configs/PM828.h
@@ -28,7 +28,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#undef CFG_RAMBOOT
+#undef CONFIG_SYS_RAMBOOT
 
 /*
  * High Level Configuration Options
@@ -55,8 +55,8 @@
 /* enable I2C and select the hardware/software driver */
 #undef	CONFIG_HARD_I2C
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-# define CFG_I2C_SPEED		50000
-# define CFG_I2C_SLAVE		0xFE
+# define CONFIG_SYS_I2C_SPEED		50000
+# define CONFIG_SYS_I2C_SLAVE		0xFE
 /*
  * Software (bit-bang) I2C driver configuration
  */
@@ -72,7 +72,7 @@
 
 
 #define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR	0x51
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51
 
 /*
  * select serial console configuration
@@ -117,25 +117,25 @@
  * - Tx-CLK is CLK10
  */
 #define CONFIG_ETHER_ON_FCC1
-# define CFG_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
 #ifndef CONFIG_DB_CR826_J30x_ON
-# define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
+# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
 #else
-# define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
+# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
 #endif
 /*
  * - Rx-CLK is CLK15
  * - Tx-CLK is CLK14
  */
 #define CONFIG_ETHER_ON_FCC2
-# define CFG_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 /*
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 #define CONFIG_8260_CLKIN	100000000	/* in Hz */
@@ -147,7 +147,7 @@
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -185,82 +185,82 @@
  */
 #define CONFIG_NAND_LEGACY
 
-#define CFG_DOC_SHORT_TIMEOUT
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
+#define CONFIG_SYS_DOC_SHORT_TIMEOUT
+#define CONFIG_SYS_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
 
-#define CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
+#define CONFIG_SYS_DOC_SUPPORT_2000
+#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END 0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END 0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define CFG_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
+#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	     (8 << 20)	     /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	     (8 << 20)	     /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * Flash and Boot ROM mapping
  */
 
-#define CFG_BOOTROM_BASE	0xFF800000
-#define CFG_BOOTROM_SIZE	0x00080000
-#define CFG_FLASH0_BASE		0x40000000
-#define CFG_FLASH0_SIZE		0x02000000
-#define CFG_DOC_BASE		0xFF800000
-#define CFG_DOC_SIZE		0x00100000
+#define CONFIG_SYS_BOOTROM_BASE	0xFF800000
+#define CONFIG_SYS_BOOTROM_SIZE	0x00080000
+#define CONFIG_SYS_FLASH0_BASE		0x40000000
+#define CONFIG_SYS_FLASH0_SIZE		0x02000000
+#define CONFIG_SYS_DOC_BASE		0xFF800000
+#define CONFIG_SYS_DOC_SIZE		0x00100000
 
 
 /* Flash bank size (for preliminary settings)
  */
-#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
+#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	135	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	135	/* max num of sects on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
 
 #if 0
 /* Start port with environment in flash; switch to EEPROM later */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE+0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x40000)
 #define CONFIG_ENV_SIZE		0x40000
 #define CONFIG_ENV_SECT_SIZE	0x40000
 #else
 /* Final version: environment in EEPROM */
 #define CONFIG_ENV_IS_IN_EEPROM	1
-#define CFG_I2C_EEPROM_ADDR	0x58
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x58
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 #define CONFIG_ENV_OFFSET		512
 #define CONFIG_ENV_SIZE		(2048 - 512)
 #endif
@@ -268,61 +268,61 @@
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  *
- * if you change bits in the HRCW, you must also change the CFG_*
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
  * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
  */
 #if defined(CONFIG_BOOT_ROM)
-#define CFG_HRCW_MASTER		(HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
 #else
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
 #endif
 
 /* no slaves so just fill with zeros */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR		0xF0000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  *
- * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
+ * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
  * is mapped at SDRAM_BASE2_PRELIM.
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		CFG_FLASH0_BASE
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-# define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT
 #endif
 
 #ifdef	CONFIG_PCI
 #define CONFIG_PCI_PNP
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
+#define CONFIG_SYS_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
 #endif
 
 /*
@@ -337,9 +337,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -352,17 +352,17 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 				HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
-#define CFG_HID2	0
+#define CONFIG_SYS_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2	0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register					 5-5
  *-----------------------------------------------------------------------
  * turn on Checkstop Reset Enable
  */
-#define CFG_RMR		RMR_CSRE
+#define CONFIG_SYS_RMR		RMR_CSRE
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration					 4-25
@@ -370,16 +370,16 @@
  */
 
 #define BCR_APD01	0x10000000
-#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration				 4-31
  *-----------------------------------------------------------------------
  */
 #if 0
-#define CFG_SIUMCR	(SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
 #else
-#define CFG_SIUMCR	(SIUMCR_DPPC10|SIUMCR_APPC10)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC10|SIUMCR_APPC10)
 #endif
 
 
@@ -390,10 +390,10 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
@@ -403,7 +403,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		 4-42
@@ -411,19 +411,19 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control					 9-8
  *-----------------------------------------------------------------------
  */
-#define CFG_SCCR	(SCCR_DFBRG00)
+#define CONFIG_SYS_SCCR	(SCCR_DFBRG00)
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration				13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR	0
+#define CONFIG_SYS_RCCR	0
 
 /*
  * Init Memory Controller:
@@ -437,34 +437,34 @@
 
 	/* Initialize SDRAM on local bus
 	 */
-#define CFG_INIT_LOCAL_SDRAM
+#define CONFIG_SYS_INIT_LOCAL_SDRAM
 
 
 /* Minimum mask to separate preliminary
  * address ranges for CS[0:2]
  */
-#define CFG_MIN_AM_MASK 0xC0000000
+#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
 
 /*
  * we use the same values for 32 MB and 128 MB SDRAM
  * refresh rate = 7.68 uS (100 MHz Bus Clock)
  */
-#define CFG_MPTPR	0x2000
-#define CFG_PSRT	0x16
+#define CONFIG_SYS_MPTPR	0x2000
+#define CONFIG_SYS_PSRT	0x16
 
-#define CFG_MRS_OFFS	0x00000000
+#define CONFIG_SYS_MRS_OFFS	0x00000000
 
 
 #if defined(CONFIG_BOOT_ROM)
 /*
  * Bank 0 - Boot ROM (8 bit wide)
  */
-#define CFG_BR0_PRELIM	((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 			 BRx_PS_8			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_BOOTROM_SIZE)	|\
+#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_5_CLK			|\
@@ -474,12 +474,12 @@
 /*
  * Bank 1 - Flash (64 bit wide)
  */
-#define CFG_BR1_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_64			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
+#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_5_CLK			|\
@@ -491,12 +491,12 @@
 /*
  * Bank 0 - Flash (64 bit wide)
  */
-#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_64			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
+#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_5_CLK			|\
@@ -506,12 +506,12 @@
 /*
  * Bank 1 - Disk-On-Chip
  */
-#define CFG_BR1_PRELIM	((CFG_DOC_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_8			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_DOC_SIZE)	|\
+#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_5_CLK			|\
@@ -523,20 +523,20 @@
 /* Bank 2 - SDRAM
  */
 
-#ifndef CFG_RAMBOOT
-#define CFG_BR2_PRELIM	((CFG_SDRAM_BASE & BRx_BA_MSK)	|\
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_64			|\
 			 BRx_MS_SDRAM_P			|\
 			 BRx_V)
 
 	/* SDRAM initialization values for 8-column chips
 	 */
-#define CFG_OR2_8COL	(CFG_MIN_AM_MASK		|\
+#define CONFIG_SYS_OR2_8COL	(CONFIG_SYS_MIN_AM_MASK		|\
 			 ORxS_BPD_4			|\
 			 ORxS_ROWST_PBI0_A9		|\
 			 ORxS_NUMR_12)
 
-#define CFG_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
+#define CONFIG_SYS_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
 			 PSDMR_BSMA_A14_A16		|\
 			 PSDMR_SDA10_PBI0_A10		|\
 			 PSDMR_RFRC_7_CLK		|\
@@ -548,12 +548,12 @@
 
 	/* SDRAM initialization values for 9-column chips
 	 */
-#define CFG_OR2_9COL	(CFG_MIN_AM_MASK		|\
+#define CONFIG_SYS_OR2_9COL	(CONFIG_SYS_MIN_AM_MASK		|\
 			 ORxS_BPD_4			|\
 			 ORxS_ROWST_PBI0_A7		|\
 			 ORxS_NUMR_13)
 
-#define CFG_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
+#define CONFIG_SYS_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
 			 PSDMR_BSMA_A13_A15		|\
 			 PSDMR_SDA10_PBI0_A9		|\
 			 PSDMR_RFRC_7_CLK		|\
@@ -563,9 +563,9 @@
 			 PSDMR_WRC_1C			|\
 			 PSDMR_CL_2)
 
-#define CFG_OR2_PRELIM	 CFG_OR2_9COL
-#define CFG_PSDMR	 CFG_PSDMR_9COL
+#define CONFIG_SYS_OR2_PRELIM	 CONFIG_SYS_OR2_9COL
+#define CONFIG_SYS_PSDMR	 CONFIG_SYS_PSDMR_9COL
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index 1beee0f..3f943aa 100644
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -71,23 +71,22 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
 
-#undef	CFG_DRAM_TEST			/* memory test, takes time */
-#define CFG_MEMTEST_START	0x00200000	/* memtest region */
-#define CFG_MEMTEST_END		0x00400000
+#undef	CONFIG_SYS_DRAM_TEST			/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
 
 
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
-#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
 
 /* DDR Setup */
@@ -100,8 +99,8 @@
 
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_VERY_BIG_RAM
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
@@ -112,85 +111,84 @@
 #define SPD_EEPROM_ADDRESS	0x58	/* CTLR 0 DIMM 0 */
 
 /* Manually set up DDR parameters */
-#define CFG_SDRAM_SIZE	256		/* DDR is 256 MB */
-#define CFG_DDR_CS0_BNDS	0x0000000f	/* 0-256MB */
-#define CFG_DDR_CS0_CONFIG	0x80000102
-#define CFG_DDR_TIMING_1	0x47444321
-#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
-#define CFG_DDR_CONTROL	0xc2008000	/* unbuffered,no DYN_PWR */
-#define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
-#define CFG_DDR_INTERVAL	0x045b0100	/* autocharge,no open page */
+#define CONFIG_SYS_SDRAM_SIZE	256		/* DDR is 256 MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000f	/* 0-256MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000102
+#define CONFIG_SYS_DDR_TIMING_1	0x47444321
+#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_CONTROL	0xc2008000	/* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
+#define CONFIG_SYS_DDR_INTERVAL	0x045b0100	/* autocharge,no open page */
 
 /*
  * SDRAM on the Local Bus
  */
-#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
-#define CFG_LBC_SDRAM_SIZE	0		/* LBC SDRAM is 0 MB */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	0		/* LBC SDRAM is 0 MB */
 
-#define CFG_FLASH_BASE		0xfe000000	/* start of 32 MB FLASH */
-#define CFG_BR0_PRELIM		0xfe001801	/* port size 32bit */
+#define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of 32 MB FLASH */
+#define CONFIG_SYS_BR0_PRELIM		0xfe001801	/* port size 32bit */
 
-#define CFG_OR0_PRELIM		0xfe006f67	/* 32 MB Flash */
-#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_OR0_PRELIM		0xfe006f67	/* 32 MB Flash */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef	CFG_RAMBOOT
+#undef	CONFIG_SYS_RAMBOOT
 #endif
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
 /*
  * Local Bus Definitions
  */
-#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
-#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
-#define CFG_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
-#define CFG_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
+#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
 
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /*
@@ -199,40 +197,40 @@
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
 
 /*
  * EEPROM configuration
  */
-#define CFG_I2C_EEPROM_ADDR		0x58
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 
 /*
  * RTC configuration
  */
 #define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR		0x51
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
 
 /* RapidIO MMU */
-#define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
-#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
-#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M */
+#define CONFIG_SYS_RIO_MEM_BASE	0xc0000000	/* base address */
+#define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BASE
+#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
 
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0xe2000000
-#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_BASE	0xe2000000
+#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_SIZE	0x1000000	/* 16M */
 
 #if defined(CONFIG_PCI)
 
@@ -250,7 +248,7 @@
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
 
 #endif	/* CONFIG_PCI */
 
@@ -292,20 +290,20 @@
 /*
  * Environment
  */
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
   #define CONFIG_ENV_IS_IN_FLASH	1
-  #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x80000)
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x80000)
   #define CONFIG_ENV_SECT_SIZE	0x40000 /* 256K(one sector) for env */
   #define CONFIG_ENV_SIZE		0x2000
 #else
-  #define CFG_NO_FLASH		1	/* Flash is not usable now */
+  #define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
   #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-  #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
   #define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 
 /*
@@ -332,8 +330,8 @@
     #define CONFIG_CMD_PCI
 #endif
 
-#if defined(CFG_RAMBOOT)
-    #undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 
@@ -343,20 +341,20 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory */
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 #define CONFIG_LOOPW
 
 /*
@@ -364,7 +362,7 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index 9d535b6..43c2873 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -72,25 +72,24 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
 
-#define CFG_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions */
+#define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions */
 
-#undef	CFG_DRAM_TEST			/* memory test, takes time */
-#define CFG_MEMTEST_START	0x00200000	/* memtest region */
-#define CFG_MEMTEST_END		0x00400000
+#undef	CONFIG_SYS_DRAM_TEST			/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
 
 
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
-#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR1
@@ -102,8 +101,8 @@
 
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_VERY_BIG_RAM
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
@@ -114,42 +113,42 @@
 #define SPD_EEPROM_ADDRESS	0x58	/* CTLR 0 DIMM 0 */
 
 /* Manually set up DDR parameters */
-#define CFG_SDRAM_SIZE	256		/* DDR is 256 MB */
-#define CFG_DDR_CS0_BNDS	0x0000000f	/* 0-256MB */
-#define CFG_DDR_CS0_CONFIG	0x80000102
-#define CFG_DDR_TIMING_1	0x47444321
-#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
-#define CFG_DDR_CONTROL	0xc2008000	/* unbuffered,no DYN_PWR */
-#define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
-#define CFG_DDR_INTERVAL	0x045b0100	/* autocharge,no open page */
+#define CONFIG_SYS_SDRAM_SIZE	256		/* DDR is 256 MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000f	/* 0-256MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000102
+#define CONFIG_SYS_DDR_TIMING_1	0x47444321
+#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_CONTROL	0xc2008000	/* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
+#define CONFIG_SYS_DDR_INTERVAL	0x045b0100	/* autocharge,no open page */
 
 /*
  * SDRAM on the Local Bus
  */
-#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
-#define CFG_LBC_SDRAM_SIZE	0		/* LBC SDRAM is 0 MB */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	0		/* LBC SDRAM is 0 MB */
 
-#define CFG_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
-#define CFG_BR0_PRELIM		0xfe001801	/* port size 32bit */
+#define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
+#define CONFIG_SYS_BR0_PRELIM		0xfe001801	/* port size 32bit */
 
-#define CFG_OR0_PRELIM		0xfe006f67	/* 32MB Flash */
-#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_OR0_PRELIM		0xfe006f67	/* 32MB Flash */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef  CFG_RAMBOOT
+#undef  CONFIG_SYS_RAMBOOT
 #endif
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
@@ -158,36 +157,35 @@
  * Local Bus Definitions
  */
 
-#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
-#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
-#define CFG_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
-#define CFG_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
+#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
 
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(512 * 1024)    /* Reserve 512 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)    /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_ON_SCC	/* define if console on SCC */
 #undef  CONFIG_CONS_NONE	/* define if console on something else */
 #define CONFIG_CONS_INDEX       1  /* which serial channel for console */
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /*
@@ -196,40 +194,40 @@
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
 
 /*
  * EEPROM configuration
  */
-#define CFG_I2C_EEPROM_ADDR		0x58
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 
 /*
  * RTC configuration
  */
 #define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR		0x51
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
 
 /* RapidIO MMU */
-#define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
-#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
-#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M */
+#define CONFIG_SYS_RIO_MEM_BASE	0xc0000000	/* base address */
+#define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BASE
+#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
 
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0xe2000000
-#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_BASE	0xe2000000
+#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_SIZE	0x1000000	/* 16M */
 
 #if defined(CONFIG_PCI)
 
@@ -246,7 +244,7 @@
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
 #endif	/* CONFIG_PCI */
 
@@ -284,28 +282,28 @@
    * - Full duplex
  */
 #define CONFIG_ETHER_ON_FCC3
-#define CFG_CMXFCR_MASK3	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
-#define CFG_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
-#define CFG_CPMFCR_RAMTYPE	0
-#define CFG_FCC_PSMR		(FCC_PSMR_FDE)
+#define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE)
 
 /*
  * Environment
  */
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
   #define CONFIG_ENV_IS_IN_FLASH	1
-  #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x80000)
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x80000)
   #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
   #define CONFIG_ENV_SIZE		0x2000
 #else
-  #define CFG_NO_FLASH		1	/* Flash is not usable now */
+  #define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
   #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-  #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
   #define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 
 /*
@@ -331,8 +329,8 @@
     #define CONFIG_CMD_PCI
 #endif
 
-#if defined(CFG_RAMBOOT)
-    #undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 
@@ -342,20 +340,20 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	*/
-#define CFG_LOAD_ADDR	0x1000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 #define CONFIG_LOOPW
 
 /*
@@ -363,7 +361,7 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
index e543059..c598d00 100644
--- a/include/configs/PMC405.h
+++ b/include/configs/PMC405.h
@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -21,16 +21,11 @@
  * MA 02111-1307 USA
  */
 
-/*
- * board/config.h - configuration options, board specific
- */
-
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
 /*
  * High Level Configuration Options
- * (easy to change)
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
@@ -45,24 +40,31 @@
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
-#undef	CONFIG_BOOTARGS
-#undef	CONFIG_BOOTCOMMAND
+/* Only interrupt boot if space is pressed. */
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT	\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+#undef CONFIG_BOOTARGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT			/* enable preboot variable	*/
 
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
+#define CFG_BOOTM_LEN		0x1000000 /* support booting of huge images */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1	/* allow baudrate change	*/
 
 #define CONFIG_NET_MULTI	1
 #undef  CONFIG_HAS_ETH1
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-
+#define CONFIG_LXT971_NO_SLEEP	1	/* disable sleep mode in LXT971	*/
+#define CONFIG_RESET_PHY_R	1	/* use reset_phy()		*/
 
 /*
  * BOOTP options
@@ -72,7 +74,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -90,259 +91,252 @@
 #define CONFIG_CMD_UNIVERSE
 #define CONFIG_CMD_EEPROM
 
-
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address         */
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible */
+#define CONFIG_SYS_RTC_REG_BASE_ADDR	0xF0000500 /* RTC Base Address */
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser */
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Argument Buffer Sz */
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device */
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console info */
 
-#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+#define CONFIG_AUTO_COMPLETE		1       /* add autocompletion support */
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK		/* no external serial clock */
+#define CONFIG_SYS_BASE_BAUD	806400
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1	/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1 ms ticks */
 
-#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+#define CONFIG_LOOPW		1	/* enable loopw command */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+#define CONFIG_SYS_RX_ETH_BUFFER	16
 
-/*-----------------------------------------------------------------------
+/*
  * PCI stuff
- *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408  /* PCI Device ID: Non-Monarch */
-#define CFG_PCI_SUBSYS_DEVICEID_MONARCH 0x0409     /* PCI Device ID: Monarch */
-#define CFG_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
-
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-
-#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
-#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#if 1
-#define CFG_PCI_PTM2LA	0xef000000	/* point to internal regs       */
-#define CFG_PCI_PTM2MS  0xff000001      /* 16MB, enable                 */
-#define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
-#else /* old mapping */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-#endif
-/*-----------------------------------------------------------------------
+#define PCI_HOST_ADAPTER	0	/* configure as pci adapter	*/
+#define PCI_HOST_FORCE		1	/* configure as pci host	*/
+#define PCI_HOST_AUTO		2	/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1	/* don't skip host bridge config */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
+
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20 /* Processor/PPC */
+
+#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram	*/
+#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address */
+#define CONFIG_SYS_PCI_PTM2LA  0xef000000	/* point to internal regs */
+#define CONFIG_SYS_PCI_PTM2MS  0xff000001	/* 16MB, enable */
+#define CONFIG_SYS_PCI_PTM2PCI 0x00000000	/* Host: use this pci address */
+
+/*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MONITOR_BASE	0xFFFC0000
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* 128 kB for malloc() */
+
+#define CONFIG_PRAM			0 /* use pram variable to overwrite */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20) /* Initial Memory map for Linux */
 
-/*-----------------------------------------------------------------------
+/*
  * FLASH organization
  */
-#define CFG_FLASH_BASE		0xFE000000
-#define CFG_FLASH_INCREMENT	0x01000000
-
-#define CFG_FLASH_CFI         1       /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER  1       /* Use the common driver */
-#define CFG_FLASH_PROTECTION  1       /* don't use hardware protection        */
-#define CFG_FLASH_USE_BUFFER_WRITE 1  /* use buffered writes (20x faster)     */
-#define CFG_MAX_FLASH_BANKS   2       /* max num of flash banks */
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + CFG_FLASH_INCREMENT }
-#define CFG_MAX_FLASH_SECT    128     /* max num of sects on one chip */
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_INCREMENT	0x01000000
+
+#define CONFIG_SYS_FLASH_CFI		1 /* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER		1 /* Use the common driver */
+#define CONFIG_SYS_FLASH_PROTECTION	1 /* don't use hardware protection */
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}}
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2 /* max num of flash banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, \
+			CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT}
+#define CONFIG_SYS_MAX_FLASH_SECT	128 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on fli */
 
 /*
- * JFFS2 partitions - second bank contains u-boot
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0x01b00000
-#define CONFIG_JFFS2_PART_OFFSET	0x00400000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=pmc405-0"
-#define MTDPARTS_DEFAULT	"mtdparts=pmc405-0:-(jffs2)"
-*/
-
-/*-----------------------------------------------------------------------
  * Environment Variable setup
  */
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC16 is 2048 bytes */
 
-#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_OFFSET	0x000
+#define CONFIG_ENV_SIZE		0x800 /* 2048 bytes may be used for env vars */
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500	/* NVRAM base address */
+#define CONFIG_SYS_NVRAM_SIZE		242		/* NVRAM size */
 
-/*-----------------------------------------------------------------------
+/*
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+#define CONFIG_SYS_I2C_SPEED		100000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24W16 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24W16 has */
 					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+					/* last	4 bits of the address */
+
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
 
-/*-----------------------------------------------------------------------
+/*
  * External Bus Controller (EBC) Setup
  */
-#define FLASH0_BA	0xFF000000	    /* FLASH 0 Base Address		*/
-#define FLASH1_BA	0xFE000000	    /* FLASH 1 Base Address		*/
-#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
-#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
-#define NVRAM_BA        0xF0200000          /* NVRAM Base Address               */
-
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP	0x92015480
-#define CFG_EBC_PB0CR	FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 1 (Flash Bank 1) initialization					*/
-#define CFG_EBC_PB1AP	0x92015480
-#define CFG_EBC_PB1CR	FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 2 (CAN0, 1, RTC) initialization					*/
-#define CFG_EBC_PB2AP	0x03000440   /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0      */
-#define CFG_EBC_PB2CR	CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define FLASH0_BA	0xFF000000	/* FLASH 0 Base Address	*/
+#define FLASH1_BA	0xFE000000	/* FLASH 1 Base Address	*/
+#define CAN_BA		0xF0000000	/* CAN Base Addres	*/
+#define RTC_BA		0xF0000500	/* RTC Base Address	*/
+#define NVRAM_BA	0xF0200000	/* NVRAM Base Address	*/
+
+/* Memory Bank 0 (Flash Bank 0) initialization */
+#define CONFIG_SYS_EBC_PB0AP	0x92015480
+/* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0CR	(FLASH0_BA | 0x9A000)
+
+/* Memory Bank 1 (Flash Bank 1) initialization */
+#define CONFIG_SYS_EBC_PB1AP	0x92015480
+/* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB1CR	(FLASH1_BA | 0x9A000)
+
+/* Memory Bank 2 (CAN0, 1, RTC) initialization */
+/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0      */
+#define CONFIG_SYS_EBC_PB2AP	0x03000440
+/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB2CR	(CAN_BA | 0x18000)
 
 /* Memory Bank 3 -> unused */
 
-/* Memory Bank 4 (NVRAM) initialization					*/
-#define CFG_EBC_PB4AP	0x03000440   /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0      */
-#define CFG_EBC_PB4CR	NVRAM_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+/* Memory Bank 4 (NVRAM) initialization */
+/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
+#define CONFIG_SYS_EBC_PB4AP	0x03000440
+/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB4CR	(NVRAM_BA | 0x18000)
 
-/*-----------------------------------------------------------------------
+/*
  * FPGA stuff
  */
-#define CFG_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
-#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
+#define CONFIG_SYS_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD */
+#define CONFIG_SYS_FPGA_MAX_SIZE	(32 * 1024) /* 32kByte for CPLD */
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
-#define CFG_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
-#define CFG_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
-#define CFG_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
+#define CONFIG_SYS_FPGA_PRG		0x04000000 /* JTAG TMS pin (output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000 /* JTAG TCK pin (output) */
+#define CONFIG_SYS_FPGA_DATA		0x01000000 /* JTAG TDO pin (output) */
+#define CONFIG_SYS_FPGA_INIT		0x00010000 /* unused (ppc input) */
+#define CONFIG_SYS_FPGA_DONE		0x00008000 /* JTAG TDI pin (input) */
 
-#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+/* pass Ethernet MAC to VxWorks */
+#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000
 
-/*-----------------------------------------------------------------------
+/*
  * GPIOs
  */
-#define CFG_NONMONARCH		(0x80000000 >> 14)   /* GPIO24 */
-#define CFG_XEREADY		(0x80000000 >> 15)   /* GPIO15 */
-#define CFG_INTA_FAKE		(0x80000000 >> 19)   /* GPIO19 */
-#define CFG_SELF_RST		(0x80000000 >> 21)   /* GPIO21 */
-#define CFG_REV1_2		(0x80000000 >> 23)   /* GPIO23 */
+#define CONFIG_SYS_VPEN			(0x80000000 >>  3) /* GPIO3 */
+#define CONFIG_SYS_NONMONARCH		(0x80000000 >> 14) /* GPIO14 */
+#define CONFIG_SYS_XEREADY		(0x80000000 >> 15) /* GPIO15 */
+#define CONFIG_SYS_INTA_FAKE		(0x80000000 >> 19) /* GPIO19 */
+#define CONFIG_SYS_SELF_RST		(0x80000000 >> 21) /* GPIO21 */
+#define CONFIG_SYS_REV1_2		(0x80000000 >> 23) /* GPIO23 */
 
-/*-----------------------------------------------------------------------
+/*
  * Definitions for initial stack pointer and data area (in data cache)
  */
 
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	1
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+
+/* inside of SDRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR
 
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_END		CONFIG_SYS_OCM_DATA_SIZE
+
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
 
-#endif	/* __CONFIG_H */
+#endif /* __CONFIG_H */
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 467a11c..fc48bc1 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
  * Based on the sequoia configuration file.
  *
@@ -46,59 +46,61 @@
 #endif
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f */
+#define CONFIG_MISC_INIT_F	1
 #define CONFIG_MISC_INIT_R	1	/* Call misc_init_r     */
 #define CONFIG_BOARD_TYPES	1	/* support board types  */
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(384  * 1024)	/* Reserve 384 kB for Monitor   */
-#define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserve 256 kB for malloc()  */
+#define CONFIG_SYS_MONITOR_LEN		(384  * 1024)	/* Reserve 384 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserve 256 kB for malloc()  */
 
 #define CONFIG_PRAM		0	/* use pram variable to overwrite */
 
-#define CFG_BOOT_BASE_ADDR	0xf0000000
-#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0          */
-#define CFG_FLASH_BASE		0xfc000000	/* start of FLASH       */
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_NAND_ADDR		0xd0000000	/* NAND Flash           */
-#define CFG_OCM_BASE		0xe0010000	/* ocm                  */
-#define CFG_OCM_DATA_ADDR	CFG_OCM_BASE
-#define CFG_PCI_BASE		0xe0000000	/* Internal PCI regs    */
-#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory    */
-#define CFG_PCI_MEMBASE1	CFG_PCI_MEMBASE  + 0x10000000
-#define CFG_PCI_MEMBASE2	CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3	CFG_PCI_MEMBASE2 + 0x10000000
-#define CFG_PCI_MEMSIZE		0x80000000	/* 2GB! */
+#define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0          */
+#define CONFIG_SYS_FLASH_BASE		0xfc000000	/* start of FLASH       */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_NAND_ADDR		0xd0000000	/* NAND Flash           */
+#define CONFIG_SYS_OCM_BASE		0xe0010000	/* ocm                  */
+#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_OCM_BASE
+#define CONFIG_SYS_PCI_BASE		0xe0000000	/* Internal PCI regs    */
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory    */
+#define CONFIG_SYS_PCI_MEMBASE1	CONFIG_SYS_PCI_MEMBASE  + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2	CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3	CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
+#define CONFIG_SYS_PCI_MEMSIZE		0x80000000	/* 2GB! */
 
 /* Don't change either of these */
-#define CFG_PERIPHERAL_BASE	0xef600000	/* internal peripherals */
+#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000	/* internal peripherals */
 
-#define CFG_USB2D0_BASE		0xe0000100
-#define CFG_USB_DEVICE		0xe0000000
-#define CFG_USB_HOST		0xe0000400
-#define CFG_FPGA_BASE0		0xef000000	/* 32 bit */
-#define CFG_FPGA_BASE1		0xef100000	/* 16 bit */
+#define CONFIG_SYS_USB2D0_BASE		0xe0000100
+#define CONFIG_SYS_USB_DEVICE		0xe0000000
+#define CONFIG_SYS_USB_HOST		0xe0000400
+#define CONFIG_SYS_FPGA_BASE0		0xef000000	/* 32 bit */
+#define CONFIG_SYS_FPGA_BASE1		0xef100000	/* 16 bit */
+#define CONFIG_SYS_RESET_BASE		0xef200000
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer
  *----------------------------------------------------------------------*/
 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
-#define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM                  */
-#define CFG_INIT_RAM_END	(4 << 10)
-#define CFG_GBL_DATA_SIZE	256	/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM                  */
+#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_SIZE	256	/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_POST_WORD_ADDR
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#undef CFG_EXT_SERIAL_CLOCK
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SERIAL_MULTI	1
 #undef CONFIG_UART1_CONSOLE	/* console on front panel */
 
-#define CFG_BAUDRATE_TABLE						\
+#define CONFIG_SYS_BAUDRATE_TABLE						\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
 /*-----------------------------------------------------------------------
@@ -119,27 +121,27 @@
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI		/* The flash is CFI compatible  */
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible  */
 #define CONFIG_FLASH_CFI_DRIVER	/* Use common CFI driver        */
 
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks           */
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip    */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks           */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip    */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)      */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)      */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)      */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)      */
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)     */
-#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection        */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)     */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection        */
 
-#define CFG_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash        */
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash        */
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector          */
-#define CONFIG_ENV_ADDR		((-CFG_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector     */
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector     */
 
 /* Address and size of Redundant Environment Sector	*/
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
@@ -170,34 +172,34 @@
  * the NAND controller.	sr - 2006-08-25
  */
 #if defined (CONFIG_NAND_U_BOOT)
-#define CFG_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location                 */
-#define CFG_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size                     */
-#define CFG_NAND_BOOT_SPL_DST	(CFG_OCM_BASE + (12 << 10)) /* Copy SPL here    */
-#define CFG_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr        */
-#define CFG_NAND_U_BOOT_START	CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
-#define CFG_NAND_BOOT_SPL_DELTA	(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
+#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location                 */
+#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size                     */
+#define CONFIG_SYS_NAND_BOOT_SPL_DST	(CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here    */
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr        */
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
+#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 
 /*
  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
  */
-#define CFG_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image   */
-#define CFG_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image     */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image   */
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image     */
 
 /*
  * Now the NAND chip has to be defined (no autodetection used!)
  */
-#define CFG_NAND_PAGE_SIZE	512	/* NAND chip page size          */
-#define CFG_NAND_BLOCK_SIZE	(16 << 10) /* NAND chip block size      */
-#define CFG_NAND_PAGE_COUNT	32	/* NAND chip page count         */
-#define CFG_NAND_BAD_BLOCK_POS	5	/* Location of bad block marker */
-#undef CFG_NAND_4_ADDR_CYCLE		/* No fourth addr used (<=32MB) */
-
-#define CFG_NAND_ECCSIZE	256
-#define CFG_NAND_ECCBYTES	3
-#define CFG_NAND_ECCSTEPS	(CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
-#define CFG_NAND_OOBSIZE	16
-#define CFG_NAND_ECCTOTAL	(CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
-#define CFG_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
+#define CONFIG_SYS_NAND_PAGE_SIZE	512	/* NAND chip page size          */
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10) /* NAND chip block size      */
+#define CONFIG_SYS_NAND_PAGE_COUNT	32	/* NAND chip page count         */
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	5	/* Location of bad block marker */
+#undef CONFIG_SYS_NAND_4_ADDR_CYCLE		/* No fourth addr used (<=32MB) */
+
+#define CONFIG_SYS_NAND_ECCSIZE	256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_OOBSIZE	16
+#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
+#define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
 #endif
 
 #ifdef CONFIG_ENV_IS_IN_NAND
@@ -205,41 +207,42 @@
  * For NAND booting the environment is embedded in the U-Boot image. Please take
  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
  */
-#define CONFIG_ENV_SIZE		CFG_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(CFG_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 #endif
 
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
-#define CFG_MBYTES_SDRAM	(256)	/* 256MB                        */
+#define CONFIG_SYS_MBYTES_SDRAM	(256)	/* 256MB                        */
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_DDR_DATA_EYE	/* use DDR2 optimization        */
 #endif
+#define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes */
+						  /* 440EPx errata CHIP 11 */
 
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support    */
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged               */
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address  */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address  */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 #define CONFIG_I2C_CMD_TREE	1
 #define CONFIG_I2C_MULTI_BUS	1
 
-#define CFG_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
 
-#define CFG_I2C_EEPROM_ADDR		0x54
-#define CFG_I2C_EEPROM_ADDR_LEN		2
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS	5
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x01
 
-#define CFG_EEPROM_WREN			1
-#define CFG_I2C_BOOT_EEPROM_ADDR	0x52
+#define CONFIG_SYS_EEPROM_WREN			1
+#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR	0x52
 
 /*
  * standard dtt sensor configuration - bottom bit will determine local or
@@ -259,47 +262,60 @@
  * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
  */
 #define CONFIG_DTT_ADM1021
-#define CFG_DTT_ADM1021		{ { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
+#define CONFIG_SYS_DTT_ADM1021		{ { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
 
-#define CONFIG_PREBOOT		/* enable preboot variable */
+#define CONFIG_PREBOOT		"echo Add \\\"run fpga\\\" and "	\
+				"\\\"painit\\\" to preboot command"
 
 #undef	CONFIG_BOOTARGS
 
 /* Setup some board specific values for the default environment variables */
 #define CONFIG_HOSTNAME		pmc440
-#define CFG_BOOTFILE		"bootfile=/tftpboot/pmc440/uImage\0"
-#define CFG_ROOTPATH		"rootpath=/opt/eldk_410/ppc_4xx\0"
+#define CONFIG_SYS_BOOTFILE	"bootfile=/tftpboot/pmc440/uImage\0"
+#define CONFIG_SYS_ROOTPATH	"rootpath=/opt/eldk/ppc_4xxFP\0"
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
-	CFG_BOOTFILE							\
-	CFG_ROOTPATH							\
+	CONFIG_SYS_BOOTFILE						\
+	CONFIG_SYS_ROOTPATH						\
+	"fdt_file=/tftpboot/pmc440/pmc440.dtb\0"			\
 	"netdev=eth0\0"							\
 	"ethrotate=no\0"						\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 	"nfsroot=${serverip}:${rootpath}\0"				\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"addip=setenv bootargs ${bootargs} "				\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"		\
-	":${hostname}:${netdev}:off panic=1\0"				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
 	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
-	"flash_nfs=run nfsargs addip addtty;"				\
-	"bootm ${kernel_addr}\0"					\
-	"flash_self=run ramargs addip addtty;"				\
-	"bootm ${kernel_addr} ${ramdisk_addr}\0"			\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-	"bootm\0"							\
-	"kernel_addr=FC000000\0"					\
-	"ramdisk_addr=FC180000\0"					\
+	"addmisc=setenv bootargs ${bootargs} mem=${mem}\0"		\
+	"nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
+	"nand_boot=run nandargs addip addtty addmisc;bootm ${kernel_addr}\0" \
+	"nand_boot_fdt=run nandargs addip addtty addmisc;"		\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"run nfsargs addip addtty addmisc;"			\
+		"bootm\0"						\
+	"net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};"		\
+		"tftp  ${fdt_addr_r} ${fdt_file};"			\
+		"run nfsargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"kernel_addr=ffc00000\0"					\
+	"kernel_addr_r=200000\0"					\
+	"fpga_addr=fff00000\0"						\
+	"fdt_addr=fff80000\0"						\
+	"fdt_addr_r=800000\0"						\
+	"fpga=fpga loadb 0 ${fpga_addr}\0"				\
 	"load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0"		\
-	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
-	"cp.b 200000 FFFA0000 60000\0"					\
+	"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;"	\
+		"cp.b 200000 fffa0000 60000\0"				\
 	""
 
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds     */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download  */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change        */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change        */
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_IBM_EMAC4_V4	1
 #define CONFIG_MII		1	/* MII PHY management           */
 #define CONFIG_PHY_ADDR		0	/* PHY address, See schematics  */
@@ -307,7 +323,7 @@
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 
 #define CONFIG_HAS_ETH0
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+#define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
 
 #define CONFIG_NET_MULTI	1
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"   */
@@ -317,13 +333,13 @@
 /* USB */
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_STORAGE
-#define CFG_OHCI_BE_CONTROLLER
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
 
-#define CFG_USB_OHCI_BOARD_INIT 1
-#define CFG_USB_OHCI_CPU_INIT	1
-#define CFG_USB_OHCI_REGS_BASE	CFG_USB_HOST
-#define CFG_USB_OHCI_SLOT_NAME	"ppc440"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS	15
+#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	CONFIG_SYS_USB_HOST
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ppc440"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
 
 /* Comment this out to enable USB 1.1 device */
 #define USB_2_0_DEVICE
@@ -357,50 +373,44 @@
 #define CONFIG_CMD_SDRAM
 
 /* POST support */
-#define CONFIG_POST		(CFG_POST_MEMORY |	\
-				 CFG_POST_CPU    |	\
-				 CFG_POST_UART   |	\
-				 CFG_POST_I2C    |	\
-				 CFG_POST_CACHE  |	\
-				 CFG_POST_FPU    |	\
-				 CFG_POST_ETHER  |	\
-				 CFG_POST_SPR)
-
-#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
-
-/* esd expects pram at end of physical memory.
- * So no logbuffer at the moment.
- */
-#if 0
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY |	\
+				 CONFIG_SYS_POST_CPU    |	\
+				 CONFIG_SYS_POST_UART   |	\
+				 CONFIG_SYS_POST_I2C    |	\
+				 CONFIG_SYS_POST_CACHE  |	\
+				 CONFIG_SYS_POST_FPU    |	\
+				 CONFIG_SYS_POST_ETHER  |	\
+				 CONFIG_SYS_POST_SPR)
+
+#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 #define CONFIG_LOGBUFFER
-#endif
-#define CFG_POST_CACHE_ADDR	0x10000000	/* free virtual address     */
+#define CONFIG_SYS_POST_CACHE_ADDR	0x7fff0000	/* free virtual address     */
 
-#define CFG_CONSOLE_IS_IN_ENV	/* Otherwise it catches logbuffer as output */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* Otherwise it catches logbuffer as output */
 
 #define CONFIG_SUPPORT_VFAT
 
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  *----------------------------------------------------------------------*/
-#define CFG_LONGHELP			/* undef to save memory         */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt       */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory         */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt       */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size      */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size      */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
 #endif
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS		16	/* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on          */
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM       */
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on          */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM       */
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address      */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address      */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history     */
 #define CONFIG_LOOPW		1	/* enable loopw command         */
@@ -420,27 +430,27 @@
 /* General PCI */
 #define CONFIG_PCI		/* include pci support          */
 #define CONFIG_PCI_PNP		/* do (not) pci plug-and-play   */
-#define CFG_PCI_CACHE_LINE_SIZE	0	/* to avoid problems with PNP   */
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	0	/* to avoid problems with PNP   */
 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup  */
-#define CFG_PCI_TARGBASE	0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
+#define CONFIG_SYS_PCI_TARGBASE	0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT
-#define CFG_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
 
 /* PCI identification */
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_ID_NONMONARCH 0x0441	/* PCI Device ID: Non-Monarch */
-#define CFG_PCI_SUBSYS_ID_MONARCH 0x0440	/* PCI Device ID: Monarch */
-#define CFG_PCI_CLASSCODE_NONMONARCH	PCI_CLASS_PROCESSOR_POWERPC
-#define CFG_PCI_CLASSCODE_MONARCH	PCI_CLASS_BRIDGE_HOST
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441	/* PCI Device ID: Non-Monarch */
+#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440	/* PCI Device ID: Monarch */
+#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH	PCI_CLASS_PROCESSOR_POWERPC
+#define CONFIG_SYS_PCI_CLASSCODE_MONARCH	PCI_CLASS_BRIDGE_HOST
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
@@ -459,42 +469,45 @@
  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
  */
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-#define CFG_NAND_CS		2	/* NAND chip connected to CSx   */
+#define CONFIG_SYS_NAND_CS		2	/* NAND chip connected to CSx   */
 
 /* Memory Bank 0 (NOR-FLASH) initialization */
-#define CFG_EBC_PB0AP		0x03017200
-#define CFG_EBC_PB0CR		(CFG_FLASH_BASE | 0xda000)
+#define CONFIG_SYS_EBC_PB0AP		0x03017200
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
 
 /* Memory Bank 2 (NAND-FLASH) initialization */
-#define CFG_EBC_PB2AP		0x018003c0
-#define CFG_EBC_PB2CR		(CFG_NAND_ADDR | 0x1c000)
+#define CONFIG_SYS_EBC_PB2AP		0x018003c0
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
 #else
-#define CFG_NAND_CS		0	/* NAND chip connected to CSx   */
+#define CONFIG_SYS_NAND_CS		0	/* NAND chip connected to CSx   */
 /* Memory Bank 2 (NOR-FLASH) initialization */
-#define CFG_EBC_PB2AP		0x03017200
-#define CFG_EBC_PB2CR		(CFG_FLASH_BASE | 0xda000)
+#define CONFIG_SYS_EBC_PB2AP		0x03017200
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
 
 /* Memory Bank 0 (NAND-FLASH) initialization */
-#define CFG_EBC_PB0AP		0x018003c0
-#define CFG_EBC_PB0CR		(CFG_NAND_ADDR | 0x1c000)
+#define CONFIG_SYS_EBC_PB0AP		0x018003c0
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
 #endif
 
+/* Memory Bank 1 (RESET) initialization */
+#define CONFIG_SYS_EBC_PB1AP		0x7f817200 /* 0x03017200 */
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_RESET_BASE | 0x1c000)
+
 /* Memory Bank 4 (FPGA / 32Bit) initialization */
-#define CFG_EBC_PB4AP		0x03840f40	/* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
-#define CFG_EBC_PB4CR		(CFG_FPGA_BASE0 | 0x1c000)	/* BS=1M,BU=R/W,BW=32bit */
+#define CONFIG_SYS_EBC_PB4AP		0x03840f40	/* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
+#define CONFIG_SYS_EBC_PB4CR		(CONFIG_SYS_FPGA_BASE0 | 0x1c000)	/* BS=1M,BU=R/W,BW=32bit */
 
 /* Memory Bank 5 (FPGA / 16Bit) initialization */
-#define CFG_EBC_PB5AP		0x03840f40	/* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
-#define CFG_EBC_PB5CR		(CFG_FPGA_BASE1 | 0x1a000)	/* BS=1M,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB5AP		0x03840f40	/* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
+#define CONFIG_SYS_EBC_PB5CR		(CONFIG_SYS_FPGA_BASE1 | 0x1a000)	/* BS=1M,BU=R/W,BW=16bit */
 
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/
-#define CFG_MAX_NAND_DEVICE	1
-#define NAND_MAX_CHIPS		1
-#define CFG_NAND_BASE		(CFG_NAND_ADDR + CFG_NAND_CS)
-#define CFG_NAND_SELECT_DEVICE	1 /* nand driver supports mutipl. chips */
-#define CFG_NAND_QUIET_TEST	1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
+#define CONFIG_SYS_NAND_SELECT_DEVICE	1 /* nand driver supports mutipl. chips */
+#define CONFIG_SYS_NAND_QUIET_TEST	1
 
 /*
  * Internal Definitions
@@ -513,4 +526,6 @@
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 
+#define CONFIG_API		1
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/PN62.h b/include/configs/PN62.h
index 192cbd4..06c11e6 100644
--- a/include/configs/PN62.h
+++ b/include/configs/PN62.h
@@ -61,7 +61,7 @@
 
 #undef CONFIG_CMD_AUTOSCRIPT
 #undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
 #undef CONFIG_CMD_FLASH
 #undef CONFIG_CMD_IMLS
 
@@ -99,14 +99,14 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		1		/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_PRAM		1024		/* reserve 1 MB protected RAM	*/
 
@@ -139,50 +139,50 @@
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	0x10000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000
 
-#define CFG_RESET_ADDRESS	0xfff00100
+#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
 
-#undef	CFG_RAMBOOT
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	TEXT_BASE
+#undef	CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_MONITOR_LEN		0x00030000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 
-/*#define CFG_GBL_DATA_SIZE    256*/
-#define CFG_GBL_DATA_SIZE	128
+/*#define CONFIG_SYS_GBL_DATA_SIZE    256*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128
 
-#define CFG_INIT_RAM_ADDR	0x40000000
-#define CFG_INIT_RAM_END	0x1000
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 
-#define CFG_NO_FLASH		1		/* There is no FLASH memory	*/
+#define CONFIG_SYS_NO_FLASH		1		/* There is no FLASH memory	*/
 
 #define CONFIG_ENV_IS_NOWHERE	1		/* Store ENV in memory only	*/
 #define CONFIG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
 #define CONFIG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
 
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
 
-#define CFG_MEMTEST_START	0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x01f00000	/* 0 ... 32 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START	0x00004000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x01f00000	/* 0 ... 32 MB in DRAM		*/
 
 /*
  * Serial port configuration
  */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
 
-#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_REG_SIZE	1
 
-#define CFG_NS16550_CLK		1843200
+#define CONFIG_SYS_NS16550_CLK		1843200
 
-#define CFG_NS16550_COM1	0xff800008
-#define CFG_NS16550_COM2	0xff800000
+#define CONFIG_SYS_NS16550_COM1	0xff800008
+#define CONFIG_SYS_NS16550_COM2	0xff800000
 
 /*
  * Low Level Configuration Settings
@@ -193,30 +193,30 @@
 #define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  3
 
-#define CFG_EUMB_ADDR		0xFCE00000
+#define CONFIG_SYS_EUMB_ADDR		0xFCE00000
 
 /* MCCR1 */
-#define CFG_ROMNAL		3	/* rom/flash next access time		*/
-#define CFG_ROMFAL		7	/* rom/flash access time		*/
+#define CONFIG_SYS_ROMNAL		3	/* rom/flash next access time		*/
+#define CONFIG_SYS_ROMFAL		7	/* rom/flash access time		*/
 
 /* MCCR2 */
-#define CFG_ASRISE		6	/* ASRISE in clocks			*/
-#define CFG_ASFALL		12	/* ASFALL in clocks			*/
-#define CFG_REFINT		5600	/* REFINT in clocks			*/
+#define CONFIG_SYS_ASRISE		6	/* ASRISE in clocks			*/
+#define CONFIG_SYS_ASFALL		12	/* ASFALL in clocks			*/
+#define CONFIG_SYS_REFINT		5600	/* REFINT in clocks			*/
 
 /* MCCR3 */
-#define CFG_BSTOPRE		0x3cf	/* Burst To Precharge			*/
-#define CFG_REFREC		2	/* Refresh to activate interval		*/
-#define CFG_RDLAT		3	/* data latency from read command	*/
+#define CONFIG_SYS_BSTOPRE		0x3cf	/* Burst To Precharge			*/
+#define CONFIG_SYS_REFREC		2	/* Refresh to activate interval		*/
+#define CONFIG_SYS_RDLAT		3	/* data latency from read command	*/
 
 /* MCCR4 */
-#define CFG_PRETOACT		1	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE		3	/* Activate to Precharge interval	*/
-#define CFG_ACTORW		2	/* Activate to R/W			*/
-#define CFG_SDMODE_CAS_LAT	2	/* SDMODE CAS latency			*/
-#define CFG_SDMODE_WRAP		0	/* SDMODE Wrap type			*/
-#define CFG_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
-#define CFG_REGISTERD_TYPE_BUFFER   1
+#define CONFIG_SYS_PRETOACT		1	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE		3	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		2	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	2	/* SDMODE CAS latency			*/
+#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE Wrap type			*/
+#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
 
 /* Memory bank settings:
  *
@@ -225,80 +225,80 @@
  * bits will be set to 0x00000 for a start address, or 0xfffff for an
  * end address
  */
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x00000000
-#define CFG_BANK1_END		0x00000000
-#define CFG_BANK1_ENABLE	0
-#define CFG_BANK2_START		0x00000000
-#define CFG_BANK2_END		0x00000000
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x00000000
-#define CFG_BANK3_END		0x00000000
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x00000000
-#define CFG_BANK4_END		0x00000000
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x00000000
-#define CFG_BANK5_END		0x00000000
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x00000000
-#define CFG_BANK6_END		0x00000000
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x00000000
-#define CFG_BANK7_END		0x00000000
-#define CFG_BANK7_ENABLE	0
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x00000000
+#define CONFIG_SYS_BANK1_END		0x00000000
+#define CONFIG_SYS_BANK1_ENABLE	0
+#define CONFIG_SYS_BANK2_START		0x00000000
+#define CONFIG_SYS_BANK2_END		0x00000000
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x00000000
+#define CONFIG_SYS_BANK3_END		0x00000000
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x00000000
+#define CONFIG_SYS_BANK4_END		0x00000000
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x00000000
+#define CONFIG_SYS_BANK5_END		0x00000000
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x00000000
+#define CONFIG_SYS_BANK6_END		0x00000000
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x00000000
+#define CONFIG_SYS_BANK7_END		0x00000000
+#define CONFIG_SYS_BANK7_ENABLE	0
 
 /*
  * Memory bank enable bitmask, specifying which of the banks defined above
  * are actually present. MSB is for bank #7, LSB is for bank #0.
  */
-#define CFG_BANK_ENABLE		0x01
+#define CONFIG_SYS_BANK_ENABLE		0x01
 
-#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
+#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
 					/* see 8240 book for bit definitions	*/
-#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
 					/* currently accessed page in memory	*/
 					/* see 8240 book for details		*/
 
 /* SDRAM 0 - 256MB */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
-#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 
 /* PCI memory space */
-#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* Config addrs, etc */
-#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index cc3ef1c..d2eae1d 100644
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -63,7 +63,7 @@
 #define __DISABLE_MACHINE_EXCEPTION__
 
 #ifdef __DEBUG_START_FROM_SRAM__
-#define CFG_DUMMY_FLASH_SIZE		1024*1024*4
+#define CONFIG_SYS_DUMMY_FLASH_SIZE		1024*1024*4
 #endif
 
 /*
@@ -99,11 +99,12 @@
 #define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #undef CONFIG_EXT_PHY
 #define CONFIG_NET_MULTI	1
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #ifndef	 CONFIG_EXT_PHY
 #define CONFIG_PHY_ADDR		1	/* EMAC0 PHY address		*/
@@ -148,8 +149,8 @@
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_RTC_M41T11	1	/* uses a M41T00 RTC		*/
-#define CFG_I2C_RTC_ADDR	0x68
-#define CFG_M41T11_BASE_YEAR	1900
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	1900
 
 /*
  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
@@ -157,52 +158,51 @@
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /* SDRAM timings used in datasheet */
-#define CFG_SDRAM_CL            2
-#define CFG_SDRAM_tRP           20
-#define CFG_SDRAM_tRC           65
-#define CFG_SDRAM_tRCD          20
-#undef  CFG_SDRAM_tRFC
+#define CONFIG_SYS_SDRAM_CL            2
+#define CONFIG_SYS_SDRAM_tRP           20
+#define CONFIG_SYS_SDRAM_tRC           65
+#define CONFIG_SYS_SDRAM_tRCD          20
+#undef  CONFIG_SYS_SDRAM_tRFC
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK		/* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD		691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK		/* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD		691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
@@ -217,33 +217,31 @@
  */
 #define PPCHAMELON_NAND_TIMER_HACK
 
-#define CFG_NAND0_BASE 0xFF400000
-#define CFG_NAND1_BASE 0xFF000000
-#define CFG_NAND_BASE_LIST	{ CFG_NAND0_BASE, CFG_NAND1_BASE }
+#define CONFIG_SYS_NAND0_BASE 0xFF400000
+#define CONFIG_SYS_NAND1_BASE 0xFF000000
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND0_BASE, CONFIG_SYS_NAND1_BASE }
 #define NAND_BIG_DELAY_US	25
-#define CFG_MAX_NAND_DEVICE	2	/* Max number of NAND devices */
+#define CONFIG_SYS_MAX_NAND_DEVICE	2	/* Max number of NAND devices */
 
-#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND0_CE  (0x80000000 >> 1)	 /* our CE is GPIO1 */
+#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4)	 /* our RDY is GPIO4 */
+#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2)	 /* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3)	 /* our ALE is GPIO3 */
 
-#define CFG_NAND0_CE  (0x80000000 >> 1)	 /* our CE is GPIO1 */
-#define CFG_NAND0_RDY (0x80000000 >> 4)	 /* our RDY is GPIO4 */
-#define CFG_NAND0_CLE (0x80000000 >> 2)	 /* our CLE is GPIO2 */
-#define CFG_NAND0_ALE (0x80000000 >> 3)	 /* our ALE is GPIO3 */
-
-#define CFG_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
-#define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
-#define CFG_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
-#define CFG_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
+#define CONFIG_SYS_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
+#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
+#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
+#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
 
 #define MACRO_NAND_DISABLE_CE(nandptr) do \
 { \
 	switch((unsigned long)nandptr) \
 	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
 		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
 		break; \
 	} \
 } while(0)
@@ -252,11 +250,11 @@
 { \
 	switch((unsigned long)nandptr) \
 	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
 		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
 		break; \
 	} \
 } while(0)
@@ -265,11 +263,11 @@
 { \
 	switch((unsigned long)nandptr) \
 	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
 		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
 		break; \
 	} \
 } while(0)
@@ -278,11 +276,11 @@
 { \
 	switch((unsigned long)nandptr) \
 	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
 		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
 		break; \
 	} \
 } while(0)
@@ -291,22 +289,22 @@
 { \
 	switch((unsigned long)nandptr) \
 	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
 		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
 		break; \
 	} \
 } while(0)
 
 #define MACRO_NAND_CTL_SETCLE(nandptr) do { \
 	switch((unsigned long)nandptr) { \
-	case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
+	case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
 		break; \
-	case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
+	case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
 		break; \
 	} \
 } while(0)
@@ -352,65 +350,65 @@
 
 #define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* PCI Vendor ID: IBM	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: ---	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* PCI Vendor ID: IBM	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: ---	*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
 
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
 
 /* Reserve 256 kB for Monitor	*/
 /*
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
 */
 
 /* Reserve 320 kB for Monitor	*/
-#define CFG_FLASH_BASE		0xFFFB0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(320 * 1024)
+#define CONFIG_SYS_FLASH_BASE		0xFFFB0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(320 * 1024)
 
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 /*-----------------------------------------------------------------------
  * Environment Variable setup
@@ -429,30 +427,29 @@
 #define CONFIG_ENV_ADDR_REDUND	0xFFFFA000
 #define CONFIG_ENV_SIZE_REDUND	0x2000
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 #endif	/* ENVIRONMENT_IN_EEPROM */
 
 
-#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07*/
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 /*
  * Init Memory Controller:
@@ -467,21 +464,21 @@
  */
 
 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (External SRAM) initialization					*/
 /* Since this must replace NOR Flash, we use the same settings for CS0		*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization			*/
-#define CFG_EBC_PB2AP		0x92015480
-#define CFG_EBC_PB2CR		0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2AP		0x92015480
+#define CONFIG_SYS_EBC_PB2CR		0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization			*/
-#define CFG_EBC_PB3AP		0x92015480
-#define CFG_EBC_PB3CR		0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB3AP		0x92015480
+#define CONFIG_SYS_EBC_PB3CR		0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit	*/
 
 #ifdef CONFIG_PPCHAMELEON_SMI712
 /*
@@ -495,66 +492,66 @@
 #define CONFIG_CONSOLE_EXTRA_INFO
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
-#define CFG_ISA_IO 0xE8000000
+#define CONFIG_SYS_ISA_IO 0xE8000000
 /* see also drivers/video/videomodes.c */
-#define CFG_DEFAULT_VIDEO_MODE 0x303
+#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
 #endif
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
 /* FPGA internal regs */
-#define CFG_FPGA_MODE		0x00
-#define CFG_FPGA_STATUS		0x02
-#define CFG_FPGA_TS		0x04
-#define CFG_FPGA_TS_LOW		0x06
-#define CFG_FPGA_TS_CAP0	0x10
-#define CFG_FPGA_TS_CAP0_LOW	0x12
-#define CFG_FPGA_TS_CAP1	0x14
-#define CFG_FPGA_TS_CAP1_LOW	0x16
-#define CFG_FPGA_TS_CAP2	0x18
-#define CFG_FPGA_TS_CAP2_LOW	0x1a
-#define CFG_FPGA_TS_CAP3	0x1c
-#define CFG_FPGA_TS_CAP3_LOW	0x1e
+#define CONFIG_SYS_FPGA_MODE		0x00
+#define CONFIG_SYS_FPGA_STATUS		0x02
+#define CONFIG_SYS_FPGA_TS		0x04
+#define CONFIG_SYS_FPGA_TS_LOW		0x06
+#define CONFIG_SYS_FPGA_TS_CAP0	0x10
+#define CONFIG_SYS_FPGA_TS_CAP0_LOW	0x12
+#define CONFIG_SYS_FPGA_TS_CAP1	0x14
+#define CONFIG_SYS_FPGA_TS_CAP1_LOW	0x16
+#define CONFIG_SYS_FPGA_TS_CAP2	0x18
+#define CONFIG_SYS_FPGA_TS_CAP2_LOW	0x1a
+#define CONFIG_SYS_FPGA_TS_CAP3	0x1c
+#define CONFIG_SYS_FPGA_TS_CAP3_LOW	0x1e
 
 /* FPGA Mode Reg */
-#define CFG_FPGA_MODE_CF_RESET	0x0001
-#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
-#define CFG_FPGA_MODE_TS_CLEAR	0x2000
+#define CONFIG_SYS_FPGA_MODE_CF_RESET	0x0001
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CONFIG_SYS_FPGA_MODE_TS_CLEAR	0x2000
 
 /* FPGA Status Reg */
-#define CFG_FPGA_STATUS_DIP0	0x0001
-#define CFG_FPGA_STATUS_DIP1	0x0002
-#define CFG_FPGA_STATUS_DIP2	0x0004
-#define CFG_FPGA_STATUS_FLASH	0x0008
-#define CFG_FPGA_STATUS_TS_IRQ	0x1000
+#define CONFIG_SYS_FPGA_STATUS_DIP0	0x0001
+#define CONFIG_SYS_FPGA_STATUS_DIP1	0x0002
+#define CONFIG_SYS_FPGA_STATUS_DIP2	0x0004
+#define CONFIG_SYS_FPGA_STATUS_FLASH	0x0008
+#define CONFIG_SYS_FPGA_STATUS_TS_IRQ	0x1000
 
-#define CFG_FPGA_SPARTAN2	1		/* using Xilinx Spartan 2 now	 */
-#define CFG_FPGA_MAX_SIZE	128*1024	/* 128kByte is enough for XC2S50E*/
+#define CONFIG_SYS_FPGA_SPARTAN2	1		/* using Xilinx Spartan 2 now	 */
+#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024	/* 128kByte is enough for XC2S50E*/
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000	/* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000	/* FPGA clk pin (ppc output)	 */
-#define CFG_FPGA_DATA		0x01000000	/* FPGA data pin (ppc output)	 */
-#define CFG_FPGA_INIT		0x00010000	/* FPGA init pin (ppc input)	 */
-#define CFG_FPGA_DONE		0x00008000	/* FPGA done pin (ppc input)	 */
+#define CONFIG_SYS_FPGA_PRG		0x04000000	/* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000	/* FPGA clk pin (ppc output)	 */
+#define CONFIG_SYS_FPGA_DATA		0x01000000	/* FPGA data pin (ppc output)	 */
+#define CONFIG_SYS_FPGA_INIT		0x00010000	/* FPGA init pin (ppc input)	 */
+#define CONFIG_SYS_FPGA_DONE		0x00008000	/* FPGA done pin (ppc input)	 */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	1
+#define CONFIG_SYS_TEMP_STACK_OCM	1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
 
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup (PPC405EP specific)
@@ -569,14 +566,14 @@
  * GPIO0[30]	- EMAC0 input
  * GPIO0[31]	- EMAC1 reject packet as output
  */
-#define CFG_GPIO0_OSRH		0x40000550
-#define CFG_GPIO0_OSRL		0x00000110
-#define CFG_GPIO0_ISR1H		0x00000000
-/*#define CFG_GPIO0_ISR1L	0x15555445*/
-#define CFG_GPIO0_ISR1L		0x15555444
-#define CFG_GPIO0_TSRH		0x00000000
-#define CFG_GPIO0_TSRL		0x00000000
-#define CFG_GPIO0_TCR		0xF7FF8014
+#define CONFIG_SYS_GPIO0_OSRH		0x40000550
+#define CONFIG_SYS_GPIO0_OSRL		0x00000110
+#define CONFIG_SYS_GPIO0_ISR1H		0x00000000
+/*#define CONFIG_SYS_GPIO0_ISR1L	0x15555445*/
+#define CONFIG_SYS_GPIO0_ISR1L		0x15555444
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0xF7FF8014
 
 /*
  * Internal Definitions
@@ -784,17 +781,17 @@
 /* Model HI */
 #define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_333_111_37_55_55
 #define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_333_111_37_55_55
-#define CFG_OPB_FREQ	55555555
+#define CONFIG_SYS_OPB_FREQ	55555555
 /* Model ME */
 #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
 #define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_266_133_33_66_33
 #define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_266_133_33_66_33
-#define CFG_OPB_FREQ	66666666
+#define CONFIG_SYS_OPB_FREQ	66666666
 #else
 /* Model BA (default) */
 #define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_133_133_33_66_33
 #define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_133_133_33_66_33
-#define CFG_OPB_FREQ	66666666
+#define CONFIG_SYS_OPB_FREQ	66666666
 #endif
 
 #endif /* CONFIG_NO_SERIAL_EEPROM */
diff --git a/include/configs/QS823.h b/include/configs/QS823.h
index 2586058..c1416cb 100644
--- a/include/configs/QS823.h
+++ b/include/configs/QS823.h
@@ -35,14 +35,14 @@
 #define __CONFIG_H
 
 /* various debug settings */
-#undef CFG_DEVICE_NULLDEV		/* null device */
+#undef CONFIG_SYS_DEVICE_NULLDEV		/* null device */
 #undef CONFIG_SILENT_CONSOLE		/* silent console */
-#undef CFG_CONSOLE_INFO_QUIET		/* silent console ? */
+#undef CONFIG_SYS_CONSOLE_INFO_QUIET		/* silent console ? */
 #undef DEBUG_FLASH			/* debug flash code */
 #undef FLASH_DEBUG			/* debug fash code */
 #undef DEBUG_ENV			/* debug environment code */
 
-#define CFG_DIRECT_FLASH_TFTP	1	/* allow direct tftp to flash */
+#define CONFIG_SYS_DIRECT_FLASH_TFTP	1	/* allow direct tftp to flash */
 #define CONFIG_ENV_OVERWRITE	1	/* allow overwrite MAC address */
 
 /*
@@ -183,7 +183,7 @@
 #endif /* CONFIG_FLASH_8MB */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#undef CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change */
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change */
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 #undef CONFIG_STATUS_LED		/* Status LED disabled */
 #undef CONFIG_CAN_DRIVER		/* CAN Driver support disabled */
@@ -211,7 +211,7 @@
 #define CONFIG_CMD_BOOTD
 #define CONFIG_CMD_CONSOLE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_IMI
 #define CONFIG_CMD_IMMAP
@@ -231,29 +231,29 @@
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory */
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 
-#define CFG_HUSH_PARSER		1		/* use "hush" command parser */
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works */
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM */
 
-#define CFG_LOAD_ADDR		0x400000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
 
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Low Level Configuration Settings
@@ -264,56 +264,56 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFF000000
+#define CONFIG_SYS_IMMR		0xFF000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00		/* End of used area in DPRAM */
-#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00		/* End of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFF800000	/* Allow an 8Mbyte window */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF800000	/* Allow an 8Mbyte window */
 
 #define FLASH_BASE0_4M_PRELIM	0xFFC00000	/* Base for 4M Flash */
 #define FLASH_BASE0_8M_PRELIM	0xFF800000	/* Base for 8M Flash */
 
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
-#define CFG_MONITOR_BASE	0xFFF00000	/* U-boot location */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	0xFFF00000	/* U-boot location */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * TODO flash parameters
  * FLASH organization for Intel Strataflash
  */
-#undef  CFG_FLASH_16BIT				/* 32-bit wide flash memory */
-#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	71		/* max number of sectors on one chip */
+#undef  CONFIG_SYS_FLASH_16BIT				/* 32-bit wide flash memory */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71		/* max number of sectors on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	120000		/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000		/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms) */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16		/* For all MPC8xx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	16		/* For all MPC8xx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4		/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	4		/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -324,34 +324,34 @@
  */
 
 #ifdef CONFIG_WATCHDOG
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration 11-6
  *-----------------------------------------------------------------------
  */
-#define CFG_SIUMCR	(SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control 11-26
  *-----------------------------------------------------------------------
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register 11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control 11-31
  *-----------------------------------------------------------------------
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
@@ -361,36 +361,36 @@
 /* MF (Multiplication Factor of SPLL) */
 /* Sets the QS823 to specified clock from 32KHz clock at EXTAL. */
 #define vPLPRCR_MF	((CONFIG_CLOCK_MULT+1) << 20)
-#define CFG_PLPRCR	(vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE)
+#define CONFIG_SYS_PLPRCR	(vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
  *-----------------------------------------------------------------------
  */
 #if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
-#define CFG_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00)
-#define CFG_BRGCLK_PRESCALE	1
+#define CONFIG_SYS_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00)
+#define CONFIG_SYS_BRGCLK_PRESCALE	1
 #endif
 
 #if defined(CONFIG_CLOCK_66MHZ)
-#define CFG_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01)
-#define CFG_BRGCLK_PRESCALE	4
+#define CONFIG_SYS_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01)
+#define CONFIG_SYS_BRGCLK_PRESCALE	4
 #endif
 
 #if defined(CONFIG_CLOCK_80MHZ)
-#define CFG_SCCR		(SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01)
-#define CFG_BRGCLK_PRESCALE	4
+#define CONFIG_SYS_SCCR		(SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01)
+#define CONFIG_SYS_BRGCLK_PRESCALE	4
 #endif
 
-#define SCCR_MASK		CFG_SCCR
+#define SCCR_MASK		CONFIG_SYS_SCCR
 
 /*-----------------------------------------------------------------------
  * Debug Enable Register
  * 0x73E67C0F - All interrupts handled by BDM
  * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
  *-----------------------------------------------------------------------
-#define CFG_DER			0x73E67C0F
-#define CFG_DER			0x0082400F
+#define CONFIG_SYS_DER			0x73E67C0F
+#define CONFIG_SYS_DER			0x0082400F
 
  #-------------------------------------------------------------------------
  # Program the Debug Enable Register (DER). This register provides the user
@@ -400,7 +400,7 @@
  # MPC860 User Manual for a description of this register.
  #-------------------------------------------------------------------------
 */
-#define CFG_DER			0
+#define CONFIG_SYS_DER			0
 
 /*-----------------------------------------------------------------------
  * Memory Controller Initialization Constants
@@ -411,8 +411,8 @@
  * BR0 and OR0 (AMD dual FLASH devices)
  * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
  */
-#define CFG_PRELIM_OR_AM
-#define CFG_OR_TIMING_FLASH
+#define CONFIG_SYS_PRELIM_OR_AM
+#define CONFIG_SYS_OR_TIMING_FLASH
 
 /*
  *-----------------------------------------------------------------------
@@ -424,7 +424,7 @@
 /* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */
 /*                     represents a minumum 32K block size. */
 #define vBR0_BA			((0xFF80 << 16) + (0 << 15))
-#define CFG_BR0_PRELIM		(vBR0_BA | BR_V)
+#define CONFIG_SYS_BR0_PRELIM		(vBR0_BA | BR_V)
 
 /* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits        */
 /*                                 which defines a 8 Mbyte memory block. */
@@ -432,18 +432,18 @@
 
 #if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ)
 /*  0101 = Add a 5 clock cycle wait state */
-#define CFG_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK)
+#define CONFIG_SYS_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK)
 #endif
 
 #if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ)
 /*  0011 = Add a 3 clock cycle wait state */
 /*  29.8ns clock * (3 + 2) = 149ns cycle time */
-#define CFG_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK)
+#define CONFIG_SYS_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK)
 #endif
 
 #if defined(CONFIG_CLOCK_16MHZ)
 /*  0010 = Add a 2 clock cycle wait state */
-#define CFG_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK)
+#define CONFIG_SYS_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK)
 #endif
 
 /*
@@ -463,8 +463,8 @@
  */
 #define vOR1_AM			((0xF800 << 16) + (0 << 15))
 #define vBR1_BA			((0x0000 << 16) + (0 << 15))
-#define CFG_OR1			(vOR1_AM | OR_CSNT_SAM | OR_BI)
-#define CFG_BR1			(vBR1_BA | BR_MS_UPMA | BR_V)
+#define CONFIG_SYS_OR1			(vOR1_AM | OR_CSNT_SAM | OR_BI)
+#define CONFIG_SYS_BR1			(vBR1_BA | BR_MS_UPMA | BR_V)
 
 /* Machine A Mode Register */
 
@@ -492,12 +492,12 @@
 
 /* For boards with 16M of SDRAM */
 #define SDRAM_16M_MAX_SIZE	0x01000000	/* max 16MB SDRAM */
-#define CFG_16M_MAMR		(vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
+#define CONFIG_SYS_16M_MAMR		(vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
 
 /* For boards with 32M of SDRAM */
 #define SDRAM_32M_MAX_SIZE	0x02000000	/* max 32MB SDRAM */
-#define CFG_32M_MAMR		(vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
+#define CONFIG_SYS_32M_MAMR		(vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
 
 
@@ -505,12 +505,12 @@ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
 
 #if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ)
 /* Divide by 32 */
-#define CFG_MPTPR		0x02
+#define CONFIG_SYS_MPTPR		0x02
 #endif
 
 #if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
 /* Divide by 16 */
-#define CFG_MPTPR		0x04
+#define CONFIG_SYS_MPTPR		0x04
 #endif
 
 /*
@@ -518,24 +518,24 @@ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  * Base address = 0xF020_0000 - 0xF020_0FFF
  *
  */
-#define CFG_OR2_PRELIM		0xFFF00000
-#define CFG_BR2_PRELIM		0xF0200000
+#define CONFIG_SYS_OR2_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR2_PRELIM		0xF0200000
 
 /*
  * BR3 and OR3 (External Bus CS3)
  * Base address = 0xF030_0000 - 0xF030_0FFF
  *
  */
-#define CFG_OR3_PRELIM		0xFFF00000
-#define CFG_BR3_PRELIM		0xF0300000
+#define CONFIG_SYS_OR3_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR3_PRELIM		0xF0300000
 
 /*
  * BR4 and OR4 (External Bus CS3)
  * Base address = 0xF040_0000 - 0xF040_0FFF
  *
  */
-#define CFG_OR4_PRELIM		0xFFF00000
-#define CFG_BR4_PRELIM		0xF0400000
+#define CONFIG_SYS_OR4_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR4_PRELIM		0xF0400000
 
 
 /*
@@ -543,24 +543,24 @@ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  * Base address = 0xF050_0000 - 0xF050_0FFF
  *
  */
-#define CFG_OR5_PRELIM		0xFFF00000
-#define CFG_BR5_PRELIM		0xF0500000
+#define CONFIG_SYS_OR5_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR5_PRELIM		0xF0500000
 
 /*
  * BR6 and OR6 (Unused)
  * Base address = 0xF060_0000 - 0xF060_0FFF
  *
  */
-#define CFG_OR6_PRELIM		0xFFF00000
-#define CFG_BR6_PRELIM		0xF0600000
+#define CONFIG_SYS_OR6_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR6_PRELIM		0xF0600000
 
 /*
  * BR7 and OR7 (Unused)
  * Base address = 0xF070_0000 - 0xF070_0FFF
  *
  */
-#define CFG_OR7_PRELIM		0xFFF00000
-#define CFG_BR7_PRELIM		0xF0700000
+#define CONFIG_SYS_OR7_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR7_PRELIM		0xF0700000
 
 /*
  * Internal Definitions
diff --git a/include/configs/QS850.h b/include/configs/QS850.h
index 87a184b..de74fee 100644
--- a/include/configs/QS850.h
+++ b/include/configs/QS850.h
@@ -35,14 +35,14 @@
 #define __CONFIG_H
 
 /* various debug settings */
-#undef CFG_DEVICE_NULLDEV		/* null device */
+#undef CONFIG_SYS_DEVICE_NULLDEV		/* null device */
 #undef CONFIG_SILENT_CONSOLE		/* silent console */
-#undef CFG_CONSOLE_INFO_QUIET		/* silent console ? */
+#undef CONFIG_SYS_CONSOLE_INFO_QUIET		/* silent console ? */
 #undef DEBUG_FLASH			/* debug flash code */
 #undef FLASH_DEBUG			/* debug fash code */
 #undef DEBUG_ENV			/* debug environment code */
 
-#define CFG_DIRECT_FLASH_TFTP	1	/* allow direct tftp to flash */
+#define CONFIG_SYS_DIRECT_FLASH_TFTP	1	/* allow direct tftp to flash */
 #define CONFIG_ENV_OVERWRITE	1	/* allow overwrite MAC address */
 
 /*
@@ -183,7 +183,7 @@
 #endif /* CONFIG_FLASH_8MB */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#undef CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change */
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change */
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 #undef CONFIG_STATUS_LED		/* Status LED disabled */
 #undef CONFIG_CAN_DRIVER		/* CAN Driver support disabled */
@@ -211,7 +211,7 @@
 #define CONFIG_CMD_BOOTD
 #define CONFIG_CMD_CONSOLE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_IMI
 #define CONFIG_CMD_IMMAP
@@ -231,29 +231,29 @@
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory */
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 
-#define CFG_HUSH_PARSER		1		/* use "hush" command parser */
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works */
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM */
 
-#define CFG_LOAD_ADDR		0x400000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
 
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Low Level Configuration Settings
@@ -264,56 +264,56 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFF000000
+#define CONFIG_SYS_IMMR		0xFF000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00		/* End of used area in DPRAM */
-#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00		/* End of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFF800000	/* Allow an 8Mbyte window */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF800000	/* Allow an 8Mbyte window */
 
 #define FLASH_BASE0_4M_PRELIM	0xFFC00000	/* Base for 4M Flash */
 #define FLASH_BASE0_8M_PRELIM	0xFF800000	/* Base for 8M Flash */
 
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
-#define CFG_MONITOR_BASE	0xFFF00000	/* U-boot location */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	0xFFF00000	/* U-boot location */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * TODO flash parameters
  * FLASH organization for Intel Strataflash
  */
-#undef  CFG_FLASH_16BIT				/* 32-bit wide flash memory */
-#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	71		/* max number of sectors on one chip */
+#undef  CONFIG_SYS_FLASH_16BIT				/* 32-bit wide flash memory */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71		/* max number of sectors on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	120000		/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000		/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms) */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16		/* For all MPC8xx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	16		/* For all MPC8xx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4		/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	4		/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -324,34 +324,34 @@
  */
 
 #ifdef CONFIG_WATCHDOG
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration 11-6
  *-----------------------------------------------------------------------
  */
-#define CFG_SIUMCR	(SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control 11-26
  *-----------------------------------------------------------------------
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register 11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control 11-31
  *-----------------------------------------------------------------------
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
@@ -361,36 +361,36 @@
 /* MF (Multiplication Factor of SPLL) */
 /* Sets the QS850 to specified clock from 32KHz clock at EXTAL. */
 #define vPLPRCR_MF	((CONFIG_CLOCK_MULT+1) << 20)
-#define CFG_PLPRCR	(vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE)
+#define CONFIG_SYS_PLPRCR	(vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
  *-----------------------------------------------------------------------
  */
 #if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
-#define CFG_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00)
-#define CFG_BRGCLK_PRESCALE	1
+#define CONFIG_SYS_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00)
+#define CONFIG_SYS_BRGCLK_PRESCALE	1
 #endif
 
 #if defined(CONFIG_CLOCK_66MHZ)
-#define CFG_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01)
-#define CFG_BRGCLK_PRESCALE	4
+#define CONFIG_SYS_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01)
+#define CONFIG_SYS_BRGCLK_PRESCALE	4
 #endif
 
 #if defined(CONFIG_CLOCK_80MHZ)
-#define CFG_SCCR		(SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01)
-#define CFG_BRGCLK_PRESCALE	4
+#define CONFIG_SYS_SCCR		(SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01)
+#define CONFIG_SYS_BRGCLK_PRESCALE	4
 #endif
 
-#define SCCR_MASK		CFG_SCCR
+#define SCCR_MASK		CONFIG_SYS_SCCR
 
 /*-----------------------------------------------------------------------
  * Debug Enable Register
  * 0x73E67C0F - All interrupts handled by BDM
  * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
  *-----------------------------------------------------------------------
-#define CFG_DER			0x73E67C0F
-#define CFG_DER			0x0082400F
+#define CONFIG_SYS_DER			0x73E67C0F
+#define CONFIG_SYS_DER			0x0082400F
 
  #-------------------------------------------------------------------------
  # Program the Debug Enable Register (DER). This register provides the user
@@ -400,7 +400,7 @@
  # MPC860 User Manual for a description of this register.
  #-------------------------------------------------------------------------
 */
-#define CFG_DER			0
+#define CONFIG_SYS_DER			0
 
 /*-----------------------------------------------------------------------
  * Memory Controller Initialization Constants
@@ -411,8 +411,8 @@
  * BR0 and OR0 (AMD dual FLASH devices)
  * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
  */
-#define CFG_PRELIM_OR_AM
-#define CFG_OR_TIMING_FLASH
+#define CONFIG_SYS_PRELIM_OR_AM
+#define CONFIG_SYS_OR_TIMING_FLASH
 
 /*
  *-----------------------------------------------------------------------
@@ -424,7 +424,7 @@
 /* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */
 /*                     represents a minumum 32K block size. */
 #define vBR0_BA			((0xFF80 << 16) + (0 << 15))
-#define CFG_BR0_PRELIM		(vBR0_BA | BR_V)
+#define CONFIG_SYS_BR0_PRELIM		(vBR0_BA | BR_V)
 
 /* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits        */
 /*                                 which defines a 8 Mbyte memory block. */
@@ -432,18 +432,18 @@
 
 #if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ)
 /*  0101 = Add a 5 clock cycle wait state */
-#define CFG_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK)
+#define CONFIG_SYS_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK)
 #endif
 
 #if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ)
 /*  0011 = Add a 3 clock cycle wait state */
 /*  29.8ns clock * (3 + 2) = 149ns cycle time */
-#define CFG_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK)
+#define CONFIG_SYS_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK)
 #endif
 
 #if defined(CONFIG_CLOCK_16MHZ)
 /*  0010 = Add a 2 clock cycle wait state */
-#define CFG_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK)
+#define CONFIG_SYS_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK)
 #endif
 
 /*
@@ -463,8 +463,8 @@
  */
 #define vOR1_AM			((0xF800 << 16) + (0 << 15))
 #define vBR1_BA			((0x0000 << 16) + (0 << 15))
-#define CFG_OR1			(vOR1_AM | OR_CSNT_SAM | OR_BI)
-#define CFG_BR1			(vBR1_BA | BR_MS_UPMA | BR_V)
+#define CONFIG_SYS_OR1			(vOR1_AM | OR_CSNT_SAM | OR_BI)
+#define CONFIG_SYS_BR1			(vBR1_BA | BR_MS_UPMA | BR_V)
 
 /* Machine A Mode Register */
 
@@ -492,12 +492,12 @@
 
 /* For boards with 16M of SDRAM */
 #define SDRAM_16M_MAX_SIZE	0x01000000	/* max 16MB SDRAM */
-#define CFG_16M_MAMR		(vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
+#define CONFIG_SYS_16M_MAMR		(vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
 
 /* For boards with 32M of SDRAM */
 #define SDRAM_32M_MAX_SIZE	0x02000000	/* max 32MB SDRAM */
-#define CFG_32M_MAMR		(vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
+#define CONFIG_SYS_32M_MAMR		(vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
 
 
@@ -505,12 +505,12 @@ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
 
 #if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ)
 /* Divide by 32 */
-#define CFG_MPTPR		0x02
+#define CONFIG_SYS_MPTPR		0x02
 #endif
 
 #if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
 /* Divide by 16 */
-#define CFG_MPTPR		0x04
+#define CONFIG_SYS_MPTPR		0x04
 #endif
 
 /*
@@ -518,24 +518,24 @@ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  * Base address = 0xF020_0000 - 0xF020_0FFF
  *
  */
-#define CFG_OR2_PRELIM		0xFFF00000
-#define CFG_BR2_PRELIM		0xF0200000
+#define CONFIG_SYS_OR2_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR2_PRELIM		0xF0200000
 
 /*
  * BR3 and OR3 (External Bus CS3)
  * Base address = 0xF030_0000 - 0xF030_0FFF
  *
  */
-#define CFG_OR3_PRELIM		0xFFF00000
-#define CFG_BR3_PRELIM		0xF0300000
+#define CONFIG_SYS_OR3_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR3_PRELIM		0xF0300000
 
 /*
  * BR4 and OR4 (External Bus CS3)
  * Base address = 0xF040_0000 - 0xF040_0FFF
  *
  */
-#define CFG_OR4_PRELIM		0xFFF00000
-#define CFG_BR4_PRELIM		0xF0400000
+#define CONFIG_SYS_OR4_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR4_PRELIM		0xF0400000
 
 
 /*
@@ -543,24 +543,24 @@ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  * Base address = 0xF050_0000 - 0xF050_0FFF
  *
  */
-#define CFG_OR5_PRELIM		0xFFF00000
-#define CFG_BR5_PRELIM		0xF0500000
+#define CONFIG_SYS_OR5_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR5_PRELIM		0xF0500000
 
 /*
  * BR6 and OR6 (Unused)
  * Base address = 0xF060_0000 - 0xF060_0FFF
  *
  */
-#define CFG_OR6_PRELIM		0xFFF00000
-#define CFG_BR6_PRELIM		0xF0600000
+#define CONFIG_SYS_OR6_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR6_PRELIM		0xF0600000
 
 /*
  * BR7 and OR7 (Unused)
  * Base address = 0xF070_0000 - 0xF070_0FFF
  *
  */
-#define CFG_OR7_PRELIM		0xFFF00000
-#define CFG_BR7_PRELIM		0xF0700000
+#define CONFIG_SYS_OR7_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR7_PRELIM		0xF0700000
 
 /*
  * Internal Definitions
diff --git a/include/configs/QS860T.h b/include/configs/QS860T.h
index 54dbc30..705d375 100644
--- a/include/configs/QS860T.h
+++ b/include/configs/QS860T.h
@@ -35,14 +35,14 @@
 #define __CONFIG_H
 
 /* various debug settings */
-#undef CFG_DEVICE_NULLDEV		/* null device */
+#undef CONFIG_SYS_DEVICE_NULLDEV		/* null device */
 #undef CONFIG_SILENT_CONSOLE		/* silent console */
-#undef CFG_CONSOLE_INFO_QUIET		/* silent console ? */
+#undef CONFIG_SYS_CONSOLE_INFO_QUIET		/* silent console ? */
 #undef DEBUG_FLASH			/* debug flash code */
 #undef FLASH_DEBUG			/* debug fash code */
 #undef DEBUG_ENV			/* debug environment code */
 
-#define CFG_DIRECT_FLASH_TFTP	1	/* allow direct tftp to flash */
+#define CONFIG_SYS_DIRECT_FLASH_TFTP	1	/* allow direct tftp to flash */
 #define CONFIG_ENV_OVERWRITE	1	/* allow overwrite MAC address */
 
 
@@ -58,7 +58,7 @@
 #define CONFIG_MII
 #define FEC_INTERRUPT		SIU_LEVEL1
 #undef CONFIG_SCC1_ENET			/* SCC1 10BaseT ethernet */
-#define CFG_DISCOVER_PHY
+#define CONFIG_SYS_DISCOVER_PHY
 
 #undef CONFIG_8xx_CONS_SMC1
 #define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC */
@@ -83,7 +83,7 @@
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#undef CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change */
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change */
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 
@@ -139,30 +139,30 @@ CONFIG_SPI
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory */
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 
-#define CFG_HUSH_PARSER		1		/* use "hush" command parser */
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
 /* TODO - size? */
-#define CFG_MEMTEST_START	0x0400000	/* memtest works */
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM */
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Low Level Configuration Settings
@@ -172,55 +172,55 @@ CONFIG_SPI
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR		0xF0000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00		/* End of used area in DPRAM */
-#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00		/* End of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFF00000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFF00000
 
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /* TODO flash parameters */
 /*-----------------------------------------------------------------------
  * FLASH organization for Intel Strataflash
  */
-#define CFG_FLASH_16BIT		1		/* 16-bit wide flash memory */
-#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	64		/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_16BIT		1		/* 16-bit wide flash memory */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	64		/* max number of sectors on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	120000		/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000		/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms) */
 
 #undef	CONFIG_ENV_IS_IN_FLASH
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16		/* For all MPC8xx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	16		/* For all MPC8xx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4		/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	4		/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -230,47 +230,47 @@ CONFIG_SPI
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(0xFFFFFF88 | SYPCR_SWE | SYPCR_SWRI)
+#define CONFIG_SYS_SYPCR	(0xFFFFFF88 | SYPCR_SWE | SYPCR_SWRI)
 #else
-#define CFG_SYPCR	0xFFFFFF88
+#define CONFIG_SYS_SYPCR	0xFFFFFF88
 #endif
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration 11-6
  *-----------------------------------------------------------------------
  */
-#define CFG_SIUMCR	0x00620000
+#define CONFIG_SYS_SIUMCR	0x00620000
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control 11-26
  *-----------------------------------------------------------------------
  */
-#define CFG_TBSCR	0x00C3
+#define CONFIG_SYS_TBSCR	0x00C3
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register 11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control 11-31
  *-----------------------------------------------------------------------
  */
-#define CFG_PISCR	0x0082
+#define CONFIG_SYS_PISCR	0x0082
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
  *-----------------------------------------------------------------------
  */
-#define CFG_PLPRCR	0x0090D000
+#define CONFIG_SYS_PLPRCR	0x0090D000
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
  *-----------------------------------------------------------------------
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	0x02000000
+#define CONFIG_SYS_SCCR	0x02000000
 
 
 /*-----------------------------------------------------------------------
@@ -278,9 +278,9 @@ CONFIG_SPI
  * 0x73E67C0F - All interrupts handled by BDM
  * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
  *-----------------------------------------------------------------------
-#define CFG_DER			0x73E67C0F
+#define CONFIG_SYS_DER			0x73E67C0F
 */
-#define CFG_DER			0x0082400F
+#define CONFIG_SYS_DER			0x0082400F
 
 
 /*-----------------------------------------------------------------------
@@ -292,12 +292,12 @@ CONFIG_SPI
  * BR0 and OR0 (AMD 512K Socketed FLASH)
  * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
  */
-#define CFG_PRELIM_OR_AM
-#define CFG_OR_TIMING_FLASH
+#define CONFIG_SYS_PRELIM_OR_AM
+#define CONFIG_SYS_OR_TIMING_FLASH
 
 #define FLASH_BASE0_PRELIM	0xFFF00001
-#define CFG_OR0_PRELIM		0xFFF80D42
-#define CFG_BR0_PRELIM		0xFFF00401
+#define CONFIG_SYS_OR0_PRELIM		0xFFF80D42
+#define CONFIG_SYS_BR0_PRELIM		0xFFF00401
 
 
 /*
@@ -306,10 +306,10 @@ CONFIG_SPI
  */
 
 #define FLASH_BASE1_PRELIM	0xD0000000
-#define CFG_OR1_PRELIM		0xFF800D42
-#define CFG_BR1_PRELIM		0xD0000801
-/* #define CFG_OR1		0xFF800D42 */
-/* #define CFG_BR1		0xD0000801 */
+#define CONFIG_SYS_OR1_PRELIM		0xFF800D42
+#define CONFIG_SYS_BR1_PRELIM		0xD0000801
+/* #define CONFIG_SYS_OR1		0xFF800D42 */
+/* #define CONFIG_SYS_BR1		0xD0000801 */
 
 
 /*
@@ -327,15 +327,15 @@ CONFIG_SPI
 
 /* For boards with 16M of SDRAM */
 #define SDRAM_16M_MAX_SIZE	0x01000000	/* max 16MB SDRAM */
-#define CFG_16M_MBMR		0x18802114	/* Mem Periodic Timer Prescaler */
+#define CONFIG_SYS_16M_MBMR		0x18802114	/* Mem Periodic Timer Prescaler */
 
 /* For boards with 64M of SDRAM */
 #define SDRAM_64M_MAX_SIZE	0x04000000	/* max 64MB SDRAM */
 /* TODO - determine real value */
-#define CFG_64M_MBMR		0x18802114	/* Mem Period Timer Prescaler */
+#define CONFIG_SYS_64M_MBMR		0x18802114	/* Mem Period Timer Prescaler */
 
-#define CFG_OR2			(SDRAM_PRELIM_OR_AM | SDRAM_TIMING)
-#define CFG_BR2			(SDRAM_BASE | 0x000000C1)
+#define CONFIG_SYS_OR2			(SDRAM_PRELIM_OR_AM | SDRAM_TIMING)
+#define CONFIG_SYS_BR2			(SDRAM_BASE | 0x000000C1)
 
 
 /*
@@ -347,10 +347,10 @@ CONFIG_SPI
  *
  */
 
-#define CFG_OR3_PRELIM		0xFFC00DF6
-#define CFG_BR3_PRELIM		0xD1000401
-/* #define CFG_OR3		0xFFC00DF6 */
-/* #define CFG_BR3		0xD1000401 */
+#define CONFIG_SYS_OR3_PRELIM		0xFFC00DF6
+#define CONFIG_SYS_BR3_PRELIM		0xD1000401
+/* #define CONFIG_SYS_OR3		0xFFC00DF6 */
+/* #define CONFIG_SYS_BR3		0xD1000401 */
 
 
 /*
@@ -359,10 +359,10 @@ CONFIG_SPI
  *
  */
 
-#define CFG_OR4_PRELIM		0xFF000000
-#define CFG_BR4_PRELIM		0xE0000000
-/* #define CFG_OR4		0xFF000000 */
-/* #define CFG_BR4		0xE0000000 */
+#define CONFIG_SYS_OR4_PRELIM		0xFF000000
+#define CONFIG_SYS_BR4_PRELIM		0xE0000000
+/* #define CONFIG_SYS_OR4		0xFF000000 */
+/* #define CONFIG_SYS_BR4		0xE0000000 */
 
 
 /*
@@ -371,10 +371,10 @@ CONFIG_SPI
  *
  */
 
-#define CFG_OR5_PRELIM		0xFF000000
-#define CFG_BR5_PRELIM		0xE4000000
-/* #define CFG_OR5		0xFF000000 */
-/* #define CFG_BR5		0xE4000000 */
+#define CONFIG_SYS_OR5_PRELIM		0xFF000000
+#define CONFIG_SYS_BR5_PRELIM		0xE4000000
+/* #define CONFIG_SYS_OR5		0xFF000000 */
+/* #define CONFIG_SYS_BR5		0xE4000000 */
 
 
 /*
@@ -383,10 +383,10 @@ CONFIG_SPI
  *
  */
 
-#define CFG_OR6_PRELIM		0xFF000000
-#define CFG_BR6_PRELIM		0xE8000000
-/* #define CFG_OR6		0xFF000000 */
-/* #define CFG_BR6		0xE8000000 */
+#define CONFIG_SYS_OR6_PRELIM		0xFF000000
+#define CONFIG_SYS_BR6_PRELIM		0xE8000000
+/* #define CONFIG_SYS_OR6		0xFF000000 */
+/* #define CONFIG_SYS_BR6		0xE8000000 */
 
 
 /*
@@ -395,10 +395,10 @@ CONFIG_SPI
  *
  */
 
-#define CFG_OR7_PRELIM		0xFF000000
-#define CFG_BR7_PRELIM		0xE8000000
-/* #define CFG_OR7		0xFF000000 */
-/* #define CFG_BR7		0xE8000000 */
+#define CONFIG_SYS_OR7_PRELIM		0xFF000000
+#define CONFIG_SYS_BR7_PRELIM		0xE8000000
+/* #define CONFIG_SYS_OR7		0xFF000000 */
+/* #define CONFIG_SYS_BR7		0xE8000000 */
 
 
 /*
diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h
index 001ac1c..bab4460 100644
--- a/include/configs/R360MPI.h
+++ b/include/configs/R360MPI.h
@@ -71,7 +71,7 @@
 #define	CONFIG_SCC2_ENET
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #define	CONFIG_MISC_INIT_R		/* have misc_init_r() function	*/
 
@@ -95,8 +95,8 @@
 
 #define CONFIG_HARD_I2C		1	/* To I2C with hardware support */
 #undef CONFIG_SORT_I2C			/* To I2C with software support */
-#define CFG_I2C_SPEED		4700	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		4700	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * Software (bit-bang) I2C driver configuration
@@ -114,9 +114,9 @@
 				else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 #define I2C_DELAY		udelay(50)
 
-#define CFG_I2C_LCD_ADDR	0x8	/* LCD Control */
-#define CFG_I2C_KEY_ADDR	0x9	/* Keyboard coprocessor */
-#define CFG_I2C_TEM_ADDR	0x49	/* Temperature Sensors */
+#define CONFIG_SYS_I2C_LCD_ADDR	0x8	/* LCD Control */
+#define CONFIG_SYS_I2C_KEY_ADDR	0x9	/* Keyboard coprocessor */
+#define CONFIG_SYS_I2C_TEM_ADDR	0x49	/* Temperature Sensors */
 
 
 /*
@@ -139,28 +139,28 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_DEVICE_NULLDEV	1	/* we need the null device	*/
-#define CFG_CONSOLE_IS_IN_ENV	1	/* must set console from env	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* we need the null device	*/
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1	/* must set console from env	*/
 
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * JFFS2 partitions
@@ -187,60 +187,60 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFF000000
+#define CONFIG_SYS_IMMR		0xFF000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
 #if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x40000	/* Offset of Environment		*/
 #define	CONFIG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment sector	*/
 #define	CONFIG_ENV_SIZE		0x4000	/* Used Size of Environment sector	*/
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -250,10 +250,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -261,27 +261,27 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -292,10 +292,10 @@
  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  */
 #ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_PLPRCR							\
+#define CONFIG_SYS_PLPRCR							\
 		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
 #else			/* up to 50 MHz we use a 1:1 clock */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 #endif	/* CONFIG_80MHz */
 
 /*-----------------------------------------------------------------------
@@ -305,7 +305,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS     | \
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -315,14 +315,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -336,21 +336,21 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 #endif
 
 /*-----------------------------------------------------------------------
@@ -358,7 +358,7 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -372,17 +372,17 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFF000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFF000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 
 
 /*
@@ -392,23 +392,23 @@
 #define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
-#define CFG_PRELIM_OR2_AM	0xF8000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR2_AM	0xF8000000	/* OR addr mask */
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	(OR_ACS_DIV1  | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_ACS_DIV1  | OR_CSNT_SAM | \
 				 OR_SCY_0_CLK | OR_G5LS)
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR2_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR2_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /*
  * BR3 and OR3 (CAN Controller)
  */
 #ifdef CONFIG_CAN_DRIVER
-#define CFG_CAN_BASE		0xC0000000	/* CAN base address   */
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask */
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA |OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN base address   */
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask */
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA |OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 				 BR_PS_8 | BR_MS_UPMB | BR_V)
 #endif	/* CONFIG_CAN_DRIVER */
 
@@ -440,11 +440,11 @@
  * 80 Mhz => 80.000.000 / Divider = 156
  */
 #if   defined(CONFIG_80MHz)
-#define CFG_MAMR_PTA		156
+#define CONFIG_SYS_MAMR_PTA		156
 #elif defined(CONFIG_66MHz)
-#define CFG_MAMR_PTA		129
+#define CONFIG_SYS_MAMR_PTA		129
 #else		/*   50 MHz */
-#define CFG_MAMR_PTA		 98
+#define CONFIG_SYS_MAMR_PTA		 98
 #endif	/*CONFIG_??MHz */
 
 /*
@@ -452,26 +452,26 @@
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h
index aec204b..280175a 100644
--- a/include/configs/RBC823.h
+++ b/include/configs/RBC823.h
@@ -71,7 +71,7 @@
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -95,12 +95,12 @@
 #undef	CONFIG_RTC_MPC8xx		/* don't use internal RTC of MPC8xx (no battery)	*/
 
 #define CONFIG_HARD_I2C
-#define CFG_I2C_SPEED 40000
-#define CFG_I2C_SLAVE 0xfe
-#define CFG_I2C_EEPROM_ADDR		0x50
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_WRITE_BITS		4
-#define CFG_EEPROM_WRITE_DELAY_MS	10
+#define CONFIG_SYS_I2C_SPEED 40000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_WRITE_BITS		4
+#define CONFIG_SYS_EEPROM_WRITE_DELAY_MS	10
 
 /*
  * Command line configuration.
@@ -133,25 +133,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x0100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x0100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -161,47 +161,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFF000000
+#define CONFIG_SYS_IMMR		0xFF000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFF00000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFF00000
 #if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(384 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(384 << 10)	/* Reserve 192 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x10000	/*   Offset   of Environment Sector	*/
@@ -210,9 +210,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -222,13 +222,13 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
 /*
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 */
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -236,27 +236,27 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -269,7 +269,7 @@
 /*
  * for 48 MHz, we use a 4 MHz clock * 12
  */
-#define CFG_PLPRCR							\
+#define CONFIG_SYS_PLPRCR							\
 		( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE )
 
 /*-----------------------------------------------------------------------
@@ -279,7 +279,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_RTDIV   | SCCR_RTSEL    | SCCR_CRQEN    | \
+#define CONFIG_SYS_SCCR	(SCCR_RTDIV   | SCCR_RTSEL    | SCCR_CRQEN    | \
 		         SCCR_PRQEN   | SCCR_EBDF00   | \
 		         SCCR_COM01   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD001 | \
@@ -291,14 +291,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -311,39 +311,39 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 #endif
 
 /************************************************************
  * Disk-On-Chip configuration
  ************************************************************/
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
-#define CFG_DOC_SHORT_TIMEOUT
-#define CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
+#define CONFIG_SYS_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
+#define CONFIG_SYS_DOC_SHORT_TIMEOUT
+#define CONFIG_SYS_DOC_SUPPORT_2000
+#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -358,18 +358,18 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
 
 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH  (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
+#define CONFIG_SYS_OR_TIMING_FLASH  (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
 
-#define CFG_OR_TIMING_MSYS   (OR_ACS_DIV1 | OR_BI)
+#define CONFIG_SYS_OR_TIMING_MSYS   (OR_ACS_DIV1 | OR_BI)
 
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
 
-#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_MSYS)
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
+#define CONFIG_SYS_OR1_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_MSYS)
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
 		          BR_PS_8 | BR_V)
 
 /*
@@ -382,36 +382,36 @@
 /*
  * SDRAM timing:
  */
-#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM)
+#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_CSNT_SAM)
 
-#define CFG_OR4_PRELIM	(~(SDRAM_MAX_SIZE-1) | CFG_OR_TIMING_SDRAM )
-#define CFG_BR4_PRELIM	((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR4_PRELIM	(~(SDRAM_MAX_SIZE-1) | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR4_PRELIM	((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /*
  * Memory Periodic Timer Prescaler
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	187		/* start with divider for 48 MHz	*/
+#define CONFIG_SYS_MAMR_PTA	187		/* start with divider for 48 MHz	*/
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h
index 4fa21b8..162ef09 100644
--- a/include/configs/RPXClassic.h
+++ b/include/configs/RPXClassic.h
@@ -50,7 +50,7 @@
 /* Define CONFIG_FEC_ENET to use Fast ethernet instead of ethernet on SCC1   */
 #define CONFIG_FEC_ENET
 #ifdef CONFIG_FEC_ENET
-#define CFG_DISCOVER_PHY        1
+#define CONFIG_SYS_DISCOVER_PHY        1
 #define CONFIG_MII              1
 #endif /* CONFIG_FEC_ENET */
 
@@ -84,7 +84,7 @@
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -112,26 +112,26 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_RESET_ADDRESS	0x80000000
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_RESET_ADDRESS	0x80000000
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0040000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00C0000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0040000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00C0000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -141,15 +141,15 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFA200000
+#define CONFIG_SYS_IMMR		0xFA200000
 
 /*-----------------------------------------------------------------------------
  * I2C Configuration
  *-----------------------------------------------------------------------------
  */
 #define CONFIG_I2C              1
-#define CFG_I2C_SPEED           50000
-#define CFG_I2C_SLAVE           0x34
+#define CONFIG_SYS_I2C_SPEED           50000
+#define CONFIG_SYS_I2C_SLAVE           0x34
 
 
 /* enable I2C and select the hardware/software driver */
@@ -169,54 +169,54 @@
 #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
 
 
-# define CFG_I2C_SPEED		50000
-# define CFG_I2C_SLAVE		0x34
-# define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM X24C16		*/
-# define CFG_I2C_EEPROM_ADDR_LEN 1	/* bytes of address		*/
+# define CONFIG_SYS_I2C_SPEED		50000
+# define CONFIG_SYS_I2C_SLAVE		0x34
+# define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM X24C16		*/
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE	0xFF000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE	0xFF000000
 
 #if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || defined(CONFIG_CMD_IDE)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	0xFF000000
-/*%%% #define CFG_MONITOR_BASE	CFG_FLASH_BASE */
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	0xFF000000
+/*%%% #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE */
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #if 0
 #define	CONFIG_ENV_IS_IN_FLASH	1
@@ -232,9 +232,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -243,7 +243,7 @@
  *-----------------------------------------------------------------------
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWP)
 
 /*-----------------------------------------------------------------------
@@ -251,28 +251,28 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_MLRC10)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_MLRC10)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-/*%%%#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
-#define CFG_RTCSC	(RTCSC_SEC |  RTCSC_ALR | RTCSC_RTE)
+/*%%%#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC |  RTCSC_ALR | RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
+#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -283,7 +283,7 @@
  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  */
 /* up to 50 MHz we use a 1:1 clock */
-#define CFG_PLPRCR	( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -293,21 +293,21 @@
  */
 #define SCCR_MASK	SCCR_EBDF00
 /* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_COM00 | SCCR_TBS)
+#define CONFIG_SYS_SCCR	(SCCR_COM00 | SCCR_TBS)
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -320,29 +320,29 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-/* #define	CFG_DER	0x2002000F */
-#define CFG_DER	0
+/* #define	CONFIG_SYS_DER	0x2002000F */
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -351,13 +351,13 @@
  */
 
 #define FLASH_BASE_PRELIM	0xFE000000	/* FLASH base */
-#define CFG_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
 
 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
-#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
+#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
 
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
 
 /*
  * BR1 and OR1 (SDRAM)
@@ -367,16 +367,16 @@
 #define	SDRAM_MAX_SIZE		0x01000000	/* max 16 MB */
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000E00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000E00
 
-#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR1_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /* RPXLITE mem setting */
-#define	CFG_BR3_PRELIM	0xFA400001		/* BCSR */
-#define CFG_OR3_PRELIM	0xff7f8970
-#define	CFG_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
-#define CFG_OR4_PRELIM	0xFFF80970
+#define	CONFIG_SYS_BR3_PRELIM	0xFA400001		/* BCSR */
+#define CONFIG_SYS_OR3_PRELIM	0xff7f8970
+#define	CONFIG_SYS_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
+#define CONFIG_SYS_OR4_PRELIM	0xFFF80970
 
 /* ECCX CS settings                                                          */
 #define SED13806_OR             0xFFC00108     /* - 4 Mo
@@ -425,19 +425,19 @@
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	58
+#define CONFIG_SYS_MAMR_PTA	58
 
 /*
  * Refresh clock Prescalar
  */
-#define CFG_MPTPR	MPTPR_PTP_DIV8
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV8
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 10 column SDRAM */
-#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_10COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 |	\
 			 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
 
diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h
index 2870659..dd9134d 100644
--- a/include/configs/RPXlite.h
+++ b/include/configs/RPXlite.h
@@ -57,7 +57,7 @@
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #define CONFIG_BZIP2		/* Include support for bzip2 compressed images  */
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
@@ -81,27 +81,27 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_RESET_ADDRESS	0x09900000
+#define CONFIG_SYS_RESET_ADDRESS	0x09900000
 
-#define	CFG_LOAD_ADDR		0x400000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address	*/
 
-#define	CFG_HZ			1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -111,30 +111,30 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFA200000
+#define CONFIG_SYS_IMMR		0xFA200000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFC00000
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFC00000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #ifdef CONFIG_BZIP2
-#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve ~4 MB for malloc()   */
+#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve ~4 MB for malloc()   */
 #else
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()  */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()  */
 #endif /* CONFIG_BZIP2 */
 
 /*
@@ -142,31 +142,31 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	19	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	19	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define	CFG_DIRECT_FLASH_TFTP
+#define	CONFIG_SYS_DIRECT_FLASH_TFTP
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* We use one complete sector		*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 
 #define CONFIG_ENV_OVERWRITE
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -176,10 +176,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -187,28 +187,28 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_MLRC10)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_MLRC10)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-/*%%%#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_RTE)
+/*%%%#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -219,7 +219,7 @@
  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  */
 /* up to 50 MHz we use a 1:1 clock */
-#define CFG_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
+#define CONFIG_SYS_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -229,21 +229,21 @@
  */
 #define SCCR_MASK	SCCR_EBDF00
 /* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_COM11 | SCCR_TBS)
+#define CONFIG_SYS_SCCR	(SCCR_COM11 | SCCR_TBS)
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -256,29 +256,29 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -287,13 +287,13 @@
  */
 
 #define FLASH_BASE_PRELIM	0xFE000000	/* FLASH base */
-#define CFG_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
 
 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
-#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
+#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
 
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
 
 /*
  * BR1 and OR1 (SDRAM)
@@ -303,35 +303,35 @@
 #define	SDRAM_MAX_SIZE		0x01000000	/* max 16 MB */
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000E00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000E00
 
-#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR1_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /* RPXLITE mem setting */
-#define	CFG_BR3_PRELIM	0xFA400001		/* BCSR */
-#define CFG_OR3_PRELIM	0xFFFF8910
-#define	CFG_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
-#define CFG_OR4_PRELIM	0xFFFE0970
+#define	CONFIG_SYS_BR3_PRELIM	0xFA400001		/* BCSR */
+#define CONFIG_SYS_OR3_PRELIM	0xFFFF8910
+#define	CONFIG_SYS_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
+#define CONFIG_SYS_OR4_PRELIM	0xFFFE0970
 
 /*
  * Memory Periodic Timer Prescaler
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	58
+#define CONFIG_SYS_MAMR_PTA	58
 
 /*
  * Refresh clock Prescalar
  */
-#define CFG_MPTPR	MPTPR_PTP_DIV8
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV8
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 10 column SDRAM */
-#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_10COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 |	\
 			 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
 
diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h
index 6e72e96..a59053c 100644
--- a/include/configs/RPXlite_DW.h
+++ b/include/configs/RPXlite_DW.h
@@ -112,7 +112,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 #undef	CONFIG_STATUS_LED		/* disturbs display. Status LED disabled. */
 
@@ -148,8 +148,8 @@
 
 
 /* test-only */
-#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
 
 #define CONFIG_NETCONSOLE
 
@@ -158,25 +158,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"u-boot>"	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"u-boot>"	/* Monitor Command Prompt   */
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0040000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00C0000	/* 4 ... 12 MB in DRAM	*/
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_MEMTEST_START	0x0040000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00C0000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -186,48 +186,48 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFA200000
+#define CONFIG_SYS_IMMR		0xFA200000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00		/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00		/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
 
 #if defined(DEBUG) || defined(CONFIG_CMD_IDE)
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor */
 #endif
 
-#define CFG_MONITOR_BASE	0xFF000000
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	0xFF000000
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #ifdef	CONFIG_ENV_IS_IN_NVRAM
 #define CONFIG_ENV_ADDR		0xFA000100
@@ -238,14 +238,14 @@
 #define CONFIG_ENV_SIZE		0x8000	/* Total Size of Environment Sector	*/
 #endif	/* CONFIG_ENV_IS_IN_NVRAM */
 
-#define CFG_RESET_ADDRESS	((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
+#define CONFIG_SYS_RESET_ADDRESS	((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -255,10 +255,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif	/* We can get SYPCR: 0xFFFF0689. */
 
 /*-----------------------------------------------------------------------
@@ -266,14 +266,14 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_MLRC10)	       /* SIUMCR:0x00000800 */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_MLRC10)	       /* SIUMCR:0x00000800 */
 
 /*---------------------------------------------------------------------
  * TBSCR - Time Base Status and Control	 16-bit			 12-16
  *---------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
 /* TBSCR: 0x00C3 [SAM] */
 
 /*-----------------------------------------------------------------------
@@ -281,7 +281,7 @@
  *-----------------------------------------------------------------------
  * [RTC enabled but not stopped on FRZ]
  */
-#define CFG_RTCSC    (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1	*/
+#define CONFIG_SYS_RTCSC    (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1	*/
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control 16-bit		 12-23
@@ -289,7 +289,7 @@
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  * [Periodic timer enabled,Periodic timer interrupt disable. ]
  */
-#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)  /* PISCR:0x0083		*/
+#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)  /* PISCR:0x0083		*/
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register	32-bit	 5-7
@@ -299,9 +299,9 @@
  */
 /* up to 64 MHz we use a 1:2 clock */
 #if defined(RPXlite_64MHz)
-#define CFG_PLPRCR	( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )   /*PLPRCR: 0x00700000. */
+#define CONFIG_SYS_PLPRCR	( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )   /*PLPRCR: 0x00700000. */
 #else
-#define CFG_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
+#define CONFIG_SYS_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
 #endif
 
 /*-----------------------------------------------------------------------
@@ -313,23 +313,23 @@
 #define SCCR_MASK	SCCR_EBDF00
 /* Up to 48MHz system clock, we use 1:1 SYSTEM/BUS ratio */
 #if defined(RPXlite_64MHz)
-#define CFG_SCCR	( SCCR_TBS | SCCR_EBDF01 )  /* %%%SCCR:0x02020000 */
+#define CONFIG_SYS_SCCR	( SCCR_TBS | SCCR_EBDF01 )  /* %%%SCCR:0x02020000 */
 #else
-#define CFG_SCCR	( SCCR_TBS | SCCR_EBDF00 )  /* %%%SCCR:0x02000000 */
+#define CONFIG_SYS_SCCR	( SCCR_TBS | SCCR_EBDF00 )  /* %%%SCCR:0x02000000 */
 #endif
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -341,22 +341,22 @@
 #undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
-#define		CFG_DER		0
+#define		CONFIG_SYS_DER		0
 
 /*
  * Init Memory Controller:
@@ -364,12 +364,12 @@
  * BR0 and OR0 (FLASH)
  */
 #define FLASH_BASE_PRELIM	0xFC000000	/* FLASH base	*/
-#define CFG_PRELIM_OR_AM	0xFC000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFC000000	/* OR addr mask */
 
 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 8, ETHR = 0, BIH = 1 */
-#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
+#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
 
 /*
  * BR1 and OR1 (SDRAM)
@@ -379,40 +379,40 @@
 #define SDRAM_MAX_SIZE		0x08000000	/* max 128 MB in system */
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000E00
-#define CFG_OR_AM_SDRAM		(-(SDRAM_MAX_SIZE & OR_AM_MSK))
-#define CFG_OR1_PRELIM	( CFG_OR_AM_SDRAM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000E00
+#define CONFIG_SYS_OR_AM_SDRAM		(-(SDRAM_MAX_SIZE & OR_AM_MSK))
+#define CONFIG_SYS_OR1_PRELIM	( CONFIG_SYS_OR_AM_SDRAM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /* RPXlite mem setting */
-#define CFG_BR3_PRELIM	0xFA400001		/* BCSR */
-#define CFG_OR3_PRELIM	0xFF7F8900
-#define CFG_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
-#define CFG_OR4_PRELIM	0xFFFE0040
+#define CONFIG_SYS_BR3_PRELIM	0xFA400001		/* BCSR */
+#define CONFIG_SYS_OR3_PRELIM	0xFF7F8900
+#define CONFIG_SYS_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
+#define CONFIG_SYS_OR4_PRELIM	0xFFFE0040
 
 /*
  * Memory Periodic Timer Prescaler
  */
 /* periodic timer for refresh */
 #if defined(RPXlite_64MHz)
-#define CFG_MAMR_PTA	32
+#define CONFIG_SYS_MAMR_PTA	32
 #else
-#define CFG_MAMR_PTA	20
+#define CONFIG_SYS_MAMR_PTA	20
 #endif
 
 /*
  * Refresh clock Prescalar
  */
-#define CFG_MPTPR	MPTPR_PTP_DIV2
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV2
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL  ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
+#define CONFIG_SYS_MAMR_9COL  ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
 			MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10)
-/* CFG_MAMR_9COL:0x20904000 @ 64MHz */
+/* CONFIG_SYS_MAMR_9COL:0x20904000 @ 64MHz */
 
 /*
  * Internal Definitions
diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h
index e805213..e97ef95 100644
--- a/include/configs/RPXsuper.h
+++ b/include/configs/RPXsuper.h
@@ -8,7 +8,7 @@
  *
  *****************************************************************************/
 /* for the AY-Revision which does not use the HRCW */
-#define CFG_DEFAULT_IMMR	0x00010000
+#define CONFIG_SYS_DEFAULT_IMMR	0x00010000
 
 /* What is the oscillator's (UX2) frequency in Hz? */
 #define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
@@ -16,7 +16,7 @@
 /* How is switch S2 set? We really only want the MODCK[1-3] bits, so
  * only the 3 least significant bits are important.
 */
-#define CFG_SBC_S2  0x04
+#define CONFIG_SYS_SBC_S2  0x04
 
 /* What should MODCK_H be? It is dependent on the oscillator
  * frequency, MODCK[1-3], and desired CPM and core frequencies.
@@ -28,45 +28,45 @@
  * 0x5       0x5         66     133    133
  * 0x5       0x7         66     133    200
  */
-#define CFG_SBC_MODCK_H 0x06
+#define CONFIG_SYS_SBC_MODCK_H 0x06
 
-#define CFG_SBC_BOOT_LOW 1	/* only for HRCW */
-#undef CFG_SBC_BOOT_LOW
+#define CONFIG_SYS_SBC_BOOT_LOW 1	/* only for HRCW */
+#undef CONFIG_SYS_SBC_BOOT_LOW
 
 /* What should the base address of the main FLASH be and how big is
  * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
  * The main FLASH is whichever is connected to *CS0. U-Boot expects
  * this to be the SIMM.
  */
-#define CFG_FLASH0_BASE 0x80000000
-#define CFG_FLASH0_SIZE 16
+#define CONFIG_SYS_FLASH0_BASE 0x80000000
+#define CONFIG_SYS_FLASH0_SIZE 16
 
 /* What should the base address of the secondary FLASH be and how big
  * is it (in Mbytes)? The secondary FLASH is whichever is connected
  * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
  * want it enabled, don't define these constants.
  */
-#define CFG_FLASH1_BASE 0
-#define CFG_FLASH1_SIZE 0
-#undef CFG_FLASH1_BASE
-#undef CFG_FLASH1_SIZE
+#define CONFIG_SYS_FLASH1_BASE 0
+#define CONFIG_SYS_FLASH1_SIZE 0
+#undef CONFIG_SYS_FLASH1_BASE
+#undef CONFIG_SYS_FLASH1_SIZE
 
 /* What should be the base address of SDRAM DIMM and how big is
  * it (in Mbytes)?
 */
-#define CFG_SDRAM0_BASE 0x00000000
-#define CFG_SDRAM0_SIZE 64
+#define CONFIG_SYS_SDRAM0_BASE 0x00000000
+#define CONFIG_SYS_SDRAM0_SIZE 64
 
 /* What should be the base address of SDRAM DIMM and how big is
  * it (in Mbytes)?
 */
-#define CFG_SDRAM1_BASE 0x04000000
-#define CFG_SDRAM1_SIZE 32
+#define CONFIG_SYS_SDRAM1_BASE 0x04000000
+#define CONFIG_SYS_SDRAM1_SIZE 32
 
 /* What should be the base address of the LEDs and switch S0?
  * If you don't want them enabled, don't define this.
  */
-#define CFG_LED_BASE 0x00000000
+#define CONFIG_SYS_LED_BASE 0x00000000
 
 /*
  * select serial console configuration
@@ -106,19 +106,19 @@
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Half Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
-# define CFG_CPMFCR_RAMTYPE	0
-/*#define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB) */
-# define CFG_FCC_PSMR		0
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+/*#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB) */
+# define CONFIG_SYS_FCC_PSMR		0
 
 #else /* CONFIG_ETHER_INDEX */
 # error "on RPX Super ethernet must be FCC3"
 #endif /* CONFIG_ETHER_INDEX */
 
 #define CONFIG_HARD_I2C         1	/* I2C with hardware support	*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 
 /* Define this to reserve an entire FLASH sector (256 KB) for
@@ -144,10 +144,10 @@
 #define CONFIG_BOOTDELAY        -1
 
 /* undef this to save memory */
-#define CFG_LONGHELP
+#define CONFIG_SYS_LONGHELP
 
 /* Monitor Command Prompt       */
-#define CFG_PROMPT              "=> "
+#define CONFIG_SYS_PROMPT              "=> "
 
 
 /*
@@ -173,10 +173,10 @@
 
 
 /* Where do the internal registers live? */
-#define CFG_IMMR               0xF0000000
+#define CONFIG_SYS_IMMR               0xF0000000
 
 /* Where do the on board registers (CS4) live? */
-#define CFG_REGS_BASE          0xFA000000
+#define CONFIG_SYS_REGS_BASE          0xFA000000
 
 /*****************************************************************************
  *
@@ -194,28 +194,28 @@
  * Miscellaneous configurable options
  */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CBSIZE              1024       /* Console I/O Buffer Size      */
+#  define CONFIG_SYS_CBSIZE              1024       /* Console I/O Buffer Size      */
 #else
-#  define CFG_CBSIZE              256        /* Console I/O Buffer Size      */
+#  define CONFIG_SYS_CBSIZE              256        /* Console I/O Buffer Size      */
 #endif
 
 /* Print Buffer Size */
-#define CFG_PBSIZE        (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
+#define CONFIG_SYS_PBSIZE        (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 
-#define CFG_MAXARGS       8            /* max number of command args   */
+#define CONFIG_SYS_MAXARGS       8            /* max number of command args   */
 
-#define CFG_BARGSIZE      CFG_CBSIZE   /* Boot Argument Buffer Size    */
+#define CONFIG_SYS_BARGSIZE      CONFIG_SYS_CBSIZE   /* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START 0x04000000   /* memtest works on  */
-#define CFG_MEMTEST_END   0x06000000   /* 64-96 MB in SDRAM */
+#define CONFIG_SYS_MEMTEST_START 0x04000000   /* memtest works on  */
+#define CONFIG_SYS_MEMTEST_END   0x06000000   /* 64-96 MB in SDRAM */
 
 #define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
 
-#define CFG_LOAD_ADDR     0x100000     /* default load address */
-#define CFG_HZ            1000         /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_LOAD_ADDR     0x100000     /* default load address */
+#define CONFIG_SYS_HZ            1000         /* decrementer freq: 1 ms ticks */
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -223,106 +223,106 @@
  * You should know what you are doing if you make changes here.
  */
 
-#define CFG_FLASH_BASE    CFG_FLASH0_BASE
-#define CFG_SDRAM_BASE    CFG_SDRAM0_BASE
+#define CONFIG_SYS_FLASH_BASE    CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_SDRAM_BASE    CONFIG_SYS_SDRAM0_BASE
 
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  */
-#if defined(CFG_SBC_BOOT_LOW)
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#if defined(CONFIG_SYS_SBC_BOOT_LOW)
+#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 #else
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (0)
-#endif /* defined(CFG_SBC_BOOT_LOW) */
+#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (0)
+#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
 
-/* get the HRCW ISB field from CFG_IMMR */
-#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
-			    ((CFG_IMMR & 0x01000000) >> 7)  |\
-			    ((CFG_IMMR & 0x00100000) >> 4) )
+/* get the HRCW ISB field from CONFIG_SYS_IMMR */
+#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\
+			    ((CONFIG_SYS_IMMR & 0x01000000) >> 7)  |\
+			    ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
 
-#define CFG_HRCW_MASTER (HRCW_BPS11                           |\
+#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11                           |\
 			 HRCW_DPPC11                          |\
-			 CFG_SBC_HRCW_IMMR                    |\
+			 CONFIG_SYS_SBC_HRCW_IMMR                    |\
 			 HRCW_MMR00                           |\
 			 HRCW_LBPC11                          |\
 			 HRCW_APPC10                          |\
 			 HRCW_CS10PC00                        |\
-			 (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) |\
-			 CFG_SBC_HRCW_BOOT_FLAGS)
+			 (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) |\
+			 CONFIG_SYS_SBC_HRCW_BOOT_FLAGS)
 
 /* no slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
+#define CONFIG_SYS_HRCW_SLAVE1 0
+#define CONFIG_SYS_HRCW_SLAVE2 0
+#define CONFIG_SYS_HRCW_SLAVE3 0
+#define CONFIG_SYS_HRCW_SLAVE4 0
+#define CONFIG_SYS_HRCW_SLAVE5 0
+#define CONFIG_SYS_HRCW_SLAVE6 0
+#define CONFIG_SYS_HRCW_SLAVE7 0
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR       CFG_IMMR
-#define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE      128     /* bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_SIZE      128     /* bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
  */
-#define CFG_MONITOR_BASE        (CFG_FLASH0_BASE + 0x00F00000)
+#define CONFIG_SYS_MONITOR_BASE        (CONFIG_SYS_FLASH0_BASE + 0x00F00000)
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#  define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#  define CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */
-#define CFG_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS   1       /* max number of memory banks         */
-#define CFG_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */
+#define CONFIG_SYS_MAX_FLASH_BANKS   1       /* max number of memory banks         */
+#define CONFIG_SYS_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */
 
-#define CFG_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
-#define CFG_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */
+#define CONFIG_SYS_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
+#define CONFIG_SYS_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 #  define CONFIG_ENV_IS_IN_FLASH  1
 
 #  ifdef CONFIG_ENV_IN_OWN_SECT
-#    define CONFIG_ENV_ADDR       (CFG_MONITOR_BASE + 0x40000)
+#    define CONFIG_ENV_ADDR       (CONFIG_SYS_MONITOR_BASE + 0x40000)
 #    define CONFIG_ENV_SECT_SIZE  0x40000
 #  else
-#    define CONFIG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
+#    define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
 #    define CONFIG_ENV_SIZE       0x1000  /* Total Size of Environment Sector */
 #    define CONFIG_ENV_SECT_SIZE  0x10000 /* see README - env sect real size */
 #  endif /* CONFIG_ENV_IN_OWN_SECT */
 #else
 #  define CONFIG_ENV_IS_IN_NVRAM  1
-#  define CONFIG_ENV_ADDR         (CFG_MONITOR_BASE - 0x1000)
+#  define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 #  define CONFIG_ENV_SIZE         0x200
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
+#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT     5     /* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT     5     /* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -335,30 +335,30 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT   (/*HID0_ICE  |*/\
+#define CONFIG_SYS_HID0_INIT   (/*HID0_ICE  |*/\
 			 /*HID0_DCE  |*/\
 			 HID0_ICFI |\
 			 HID0_DCI  |\
 			 HID0_IFEM |\
 			 HID0_ABE)
 
-#define CFG_HID0_FINAL  (/*HID0_ICE  |*/\
+#define CONFIG_SYS_HID0_FINAL  (/*HID0_ICE  |*/\
 			 HID0_IFEM |\
 			 HID0_ABE  |\
 			 HID0_EMCP)
-#define CFG_HID2        0
+#define CONFIG_SYS_HID2        0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register
  *-----------------------------------------------------------------------
  */
-#define CFG_RMR         0
+#define CONFIG_SYS_RMR         0
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration                                       4-25
  *-----------------------------------------------------------------------
  */
-#define CFG_BCR         (BCR_EBM   |\
+#define CONFIG_SYS_BCR         (BCR_EBM   |\
 			 BCR_PLDP  |\
 			 BCR_EAV   |\
 			 BCR_NPQM0)
@@ -368,7 +368,7 @@
  *-----------------------------------------------------------------------
  */
 
-#define CFG_SIUMCR      (SIUMCR_L2CPC01 |\
+#define CONFIG_SYS_SIUMCR      (SIUMCR_L2CPC01 |\
 			 SIUMCR_APPC10  |\
 			 SIUMCR_CS10PC01)
 
@@ -379,7 +379,7 @@
  *-----------------------------------------------------------------------
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
-#define CFG_SYPCR       (SYPCR_SWTC |\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC |\
 			 SYPCR_BMT  |\
 			 SYPCR_PBME |\
 			 SYPCR_LBME |\
@@ -392,7 +392,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC     (TMCNTSC_SEC |\
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC |\
 			 TMCNTSC_ALR |\
 			 TMCNTSC_TCF |\
 			 TMCNTSC_TCE)
@@ -403,7 +403,7 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR       (PISCR_PS  |\
+#define CONFIG_SYS_PISCR       (PISCR_PS  |\
 			 PISCR_PTF |\
 			 PISCR_PTE)
 
@@ -411,13 +411,13 @@
  * SCCR - System Clock Control                                   9-8
  *-----------------------------------------------------------------------
  */
-#define CFG_SCCR        (SCCR_DFBRG01)
+#define CONFIG_SYS_SCCR        (SCCR_DFBRG01)
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration                         13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR        0
+#define CONFIG_SYS_RCCR        0
 
 /*
  * Init Memory Controller:
@@ -441,13 +441,13 @@
 /* Bank 0 - FLASH
  *
  */
-#define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
 			 BRx_PS_64                      |\
 			 BRx_DECC_NONE                  |\
 			 BRx_MS_GPCM_P                  |\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE)     |\
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE)     |\
 			 ORxG_CSNT                      |\
 			 ORxG_ACS_DIV1                  |\
 			 ORxG_SCY_6_CLK                 |\
@@ -456,48 +456,48 @@
 /* Bank 1 - SDRAM
  *
  */
-#define CFG_BR1_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
 			 BRx_PS_64                      |\
 			 BRx_MS_SDRAM_P                 |\
 			 BRx_V)
 
-#define CFG_OR1_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE)     |\
+#define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE)     |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI0_A8             |\
 			 ORxS_NUMR_12                   |\
 			 ORxS_IBID)
 
-#define CFG_PSDMR       0x014DA412
-#define CFG_PSRT	0x79
+#define CONFIG_SYS_PSDMR       0x014DA412
+#define CONFIG_SYS_PSRT	0x79
 
 
 /* Bank 2 - SDRAM
  *
  */
-#define CFG_BR2_PRELIM  ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
 			 BRx_PS_32                      |\
 			 BRx_MS_SDRAM_L                 |\
 			 BRx_V)
 
-#define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM1_SIZE)     |\
+#define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE)     |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI0_A9             |\
 			 ORxS_NUMR_12)
 
-#define CFG_LSDMR       0x0169A512
-#define CFG_LSRT	0x79
+#define CONFIG_SYS_LSDMR       0x0169A512
+#define CONFIG_SYS_LSRT	0x79
 
-#define CFG_MPTPR	(0x0800 & MPTPR_PTP_MSK)
+#define CONFIG_SYS_MPTPR	(0x0800 & MPTPR_PTP_MSK)
 
 /* Bank 4 - On board registers
  *
  */
-#define CFG_BR4_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
+#define CONFIG_SYS_BR4_PRELIM   ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK)  |\
 			   BRx_PS_8                     |\
 			   BRx_MS_GPCM_P                |\
 			   BRx_V)
 
-#define CFG_OR4_PRELIM    (ORxG_AM_MSK                 |\
+#define CONFIG_SYS_OR4_PRELIM    (ORxG_AM_MSK                 |\
 			   ORxG_CSNT                   |\
 			   ORxG_ACS_DIV1               |\
 			   ORxG_SCY_5_CLK              |\
diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h
index 541d586..6ec5be0 100644
--- a/include/configs/RRvision.h
+++ b/include/configs/RRvision.h
@@ -84,7 +84,7 @@
 
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -121,8 +121,8 @@
 #undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 
-# define CFG_I2C_SPEED		50000	/* 50 kHz is supposed to work	*/
-# define CFG_I2C_SLAVE		0xFE
+# define CONFIG_SYS_I2C_SPEED		50000	/* 50 kHz is supposed to work	*/
+# define CONFIG_SYS_I2C_SLAVE		0xFE
 
 #ifdef CONFIG_SOFT_I2C
 /*
@@ -160,25 +160,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -188,44 +188,44 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
 
 /* timeout values are in ticks = ms */
-#define CFG_FLASH_ERASE_TOUT	(120*CFG_HZ)	/* Timeout for Flash Erase	*/
-#define CFG_FLASH_WRITE_TOUT	(1 * CFG_HZ)	/* Timeout for Flash Write	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(120*CONFIG_SYS_HZ)	/* Timeout for Flash Erase	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(1 * CONFIG_SYS_HZ)	/* Timeout for Flash Write	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
@@ -235,14 +235,14 @@
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -252,10 +252,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -264,9 +264,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -274,20 +274,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -297,7 +297,7 @@
  */
 
 /* for 64 MHz, we use a 16 MHz clock * 4 */
-#define CFG_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+#define CONFIG_SYS_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -306,7 +306,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(/* SCCR_TBS  | */ SCCR_RTSEL | SCCR_RTDIV    | \
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS  | */ SCCR_RTSEL | SCCR_RTDIV    | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -316,14 +316,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -336,29 +336,29 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -372,19 +372,19 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
 /* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -395,19 +395,19 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 #ifndef	CONFIG_CAN_DRIVER
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 #endif	/* CONFIG_CAN_DRIVER */
 
@@ -437,33 +437,33 @@
  * 66 Mhz => 66.000.000 / Divider = 129
  * 80 Mhz => 80.000.000 / Divider = 156
  */
-#define CFG_MAMR_PTA		129
+#define CONFIG_SYS_MAMR_PTA		129
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h
index 6ec52e6..01d0d5f 100644
--- a/include/configs/Rattler.h
+++ b/include/configs/Rattler.h
@@ -78,10 +78,10 @@
  * - BDs/buffers on 60x bus
  * - Full duplex
  */
-#define CFG_CMXFCR_MASK	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
-#define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
-#define CFG_CPMFCR_RAMTYPE	0
-#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+#define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 
 #elif (CONFIG_ETHER_INDEX == 2)
 
@@ -90,10 +90,10 @@
  * - BDs/buffers on 60x bus
  * - Full duplex
  */
-#define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-#define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
-#define CFG_CPMFCR_RAMTYPE	0
-#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+#define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 
 #endif /* CONFIG_ETHER_INDEX */
 
@@ -163,39 +163,39 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size  */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size  */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#define CFG_FLASH_BASE		0xFE000000
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
-#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
 
-#define	CFG_DIRECT_FLASH_TFTP
+#define	CONFIG_SYS_DIRECT_FLASH_TFTP
 
 #if defined(CONFIG_CMD_JFFS2)
-#define CFG_JFFS2_NUM_BANKS	CFG_MAX_FLASH_BANKS
-#define CFG_JFFS2_SORT_FRAGMENTS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
 
 /*
  * JFFS2 partitions
@@ -216,83 +216,83 @@
 */
 #endif /* CONFIG_CMD_JFFS2 */
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 
 #define CONFIG_ENV_IS_IN_FLASH
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #endif /* CONFIG_ENV_IS_IN_FLASH */
 
-#define CFG_DEFAULT_IMMR	0xFF010000
+#define CONFIG_SYS_DEFAULT_IMMR	0xFF010000
 
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR		0xF0000000
 
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_SIZE		32
-#define CFG_SDRAM_BR		(CFG_SDRAM_BASE | 0x00000041)
-#define CFG_SDRAM_OR		0xFE002EC0
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		32
+#define CONFIG_SYS_SDRAM_BR		(CONFIG_SYS_SDRAM_BASE | 0x00000041)
+#define CONFIG_SYS_SDRAM_OR		0xFE002EC0
 
-#define CFG_BCSR		0xFC000000
+#define CONFIG_SYS_BCSR		0xFC000000
 
 /* Hard reset configuration word */
-#define CFG_HRCW_MASTER		0x0A06875A /* Not used - provided by FPGA */
+#define CONFIG_SYS_HRCW_MASTER		0x0A06875A /* Not used - provided by FPGA */
 /* No slaves */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot                  */
 
-#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
 
-#define CFG_HID2		0
+#define CONFIG_SYS_HID2		0
 
-#define CFG_SIUMCR		0x0E04C000
-#define CFG_SYPCR		0xFFFFFFC3
-#define CFG_BCR			0x00000000
-#define CFG_SCCR		SCCR_DFBRG01
+#define CONFIG_SYS_SIUMCR		0x0E04C000
+#define CONFIG_SYS_SYPCR		0xFFFFFFC3
+#define CONFIG_SYS_BCR			0x00000000
+#define CONFIG_SYS_SCCR		SCCR_DFBRG01
 
-#define CFG_RMR			RMR_CSRE
-#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CFG_RCCR		0
+#define CONFIG_SYS_RMR			RMR_CSRE
+#define CONFIG_SYS_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_RCCR		0
 
-#define CFG_PSDMR		0x8249A452
-#define CFG_PSRT		0x1F
-#define CFG_MPTPR		0x2000
+#define CONFIG_SYS_PSDMR		0x8249A452
+#define CONFIG_SYS_PSRT		0x1F
+#define CONFIG_SYS_MPTPR		0x2000
 
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | 0x00001001)
-#define CFG_OR0_PRELIM		0xFF001ED6
-#define CFG_BR7_PRELIM		(CFG_BCSR | 0x00000801)
-#define CFG_OR7_PRELIM		0xFFFF87F6
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | 0x00001001)
+#define CONFIG_SYS_OR0_PRELIM		0xFF001ED6
+#define CONFIG_SYS_BR7_PRELIM		(CONFIG_SYS_BCSR | 0x00000801)
+#define CONFIG_SYS_OR7_PRELIM		0xFFFF87F6
 
-#define CFG_RESET_ADDRESS	0xC0000000
+#define CONFIG_SYS_RESET_ADDRESS	0xC0000000
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index 2cf75e3..7239f84 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -75,13 +75,12 @@
 /* below can be toggled for performance analysis. otherwise use default */
 #define CONFIG_L2_CACHE			    /* toggle L2 cache		*/
 #undef	CONFIG_BTB			    /* toggle branch predition	*/
-#undef	CONFIG_ADDR_STREAMING		    /* toggle addr streaming	*/
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
 
-#undef	CFG_DRAM_TEST			    /* memory test, takes time	*/
-#define CFG_MEMTEST_START	0x00200000  /* memtest region */
-#define CFG_MEMTEST_END		0x00400000
+#undef	CONFIG_SYS_DRAM_TEST			    /* memory test, takes time	*/
+#define CONFIG_SYS_MEMTEST_START	0x00200000  /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
 
 #if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
      defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
@@ -93,17 +92,17 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
 
 #if XXX
-  #define CFG_CCSRBAR		0xfdf00000	/* relocated CCSRBAR	*/
+  #define CONFIG_SYS_CCSRBAR		0xfdf00000	/* relocated CCSRBAR	*/
 #else
-  #define CFG_CCSRBAR		0xff700000	/* default CCSRBAR	*/
+  #define CONFIG_SYS_CCSRBAR		0xff700000	/* default CCSRBAR	*/
 #endif
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR	*/
 
-#define CFG_SDRAM_SIZE		512		/* DDR is 512MB */
+#define CONFIG_SYS_SDRAM_SIZE		512		/* DDR is 512MB */
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR1
@@ -120,8 +119,8 @@
 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_VERY_BIG_RAM
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
@@ -134,69 +133,68 @@
 #undef CONFIG_CLOCKS_IN_MHZ
 
 #if defined(CONFIG_RAM_AS_FLASH)
-  #define CFG_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
-  #define CFG_FLASH_BASE	0xf8000000      /* start of FLASH 8M  */
-  #define CFG_BR0_PRELIM	0xf8000801      /* port size 8bit */
-  #define CFG_OR0_PRELIM	0xf8000ff7	/* 8MB Flash		*/
+  #define CONFIG_SYS_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
+  #define CONFIG_SYS_FLASH_BASE	0xf8000000      /* start of FLASH 8M  */
+  #define CONFIG_SYS_BR0_PRELIM	0xf8000801      /* port size 8bit */
+  #define CONFIG_SYS_OR0_PRELIM	0xf8000ff7	/* 8MB Flash		*/
 #else /* Boot from real Flash */
-  #define CFG_LBC_SDRAM_BASE	0xf8000000	/* Localbus SDRAM */
-  #define CFG_FLASH_BASE	0xff800000      /* start of FLASH 8M    */
-  #define CFG_BR0_PRELIM	0xff800801      /* port size 8bit      */
-  #define CFG_OR0_PRELIM	0xff800ff7	/* 8MB Flash		*/
+  #define CONFIG_SYS_LBC_SDRAM_BASE	0xf8000000	/* Localbus SDRAM */
+  #define CONFIG_SYS_FLASH_BASE	0xff800000      /* start of FLASH 8M    */
+  #define CONFIG_SYS_BR0_PRELIM	0xff800801      /* port size 8bit      */
+  #define CONFIG_SYS_OR0_PRELIM	0xff800ff7	/* 8MB Flash		*/
 #endif
-#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB	*/
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB	*/
 
 /* local bus definitions */
-#define CFG_BR1_PRELIM		0xe4001801	/* 64M, 32-bit flash */
-#define CFG_OR1_PRELIM		0xfc000ff7
+#define CONFIG_SYS_BR1_PRELIM		0xe4001801	/* 64M, 32-bit flash */
+#define CONFIG_SYS_OR1_PRELIM		0xfc000ff7
 
-#define CFG_BR2_PRELIM		0x00000000	/* CS2 not used */
-#define CFG_OR2_PRELIM		0x00000000
+#define CONFIG_SYS_BR2_PRELIM		0x00000000	/* CS2 not used */
+#define CONFIG_SYS_OR2_PRELIM		0x00000000
 
-#define CFG_BR3_PRELIM		0xf0001861	/* 64MB localbus SDRAM	*/
-#define CFG_OR3_PRELIM		0xfc000cc1
+#define CONFIG_SYS_BR3_PRELIM		0xf0001861	/* 64MB localbus SDRAM	*/
+#define CONFIG_SYS_OR3_PRELIM		0xfc000cc1
 
 #if defined(CONFIG_RAM_AS_FLASH)
-  #define CFG_BR4_PRELIM	0xf4001861	/* 64M localbus SDRAM */
+  #define CONFIG_SYS_BR4_PRELIM	0xf4001861	/* 64M localbus SDRAM */
 #else
-  #define CFG_BR4_PRELIM	0xf8001861	/* 64M localbus SDRAM */
+  #define CONFIG_SYS_BR4_PRELIM	0xf8001861	/* 64M localbus SDRAM */
 #endif
-#define CFG_OR4_PRELIM		0xfc000cc1
+#define CONFIG_SYS_OR4_PRELIM		0xfc000cc1
 
-#define CFG_BR5_PRELIM		0xfc000801	/* 16M CS5 misc devices */
+#define CONFIG_SYS_BR5_PRELIM		0xfc000801	/* 16M CS5 misc devices */
 #if 1
-  #define CFG_OR5_PRELIM	0xff000ff7
+  #define CONFIG_SYS_OR5_PRELIM	0xff000ff7
 #else
-  #define CFG_OR5_PRELIM	0xff0000f0
+  #define CONFIG_SYS_OR5_PRELIM	0xff0000f0
 #endif
 
-#define CFG_BR6_PRELIM		0xe0001801	/* 64M, 32-bit flash */
-#define CFG_OR6_PRELIM		0xfc000ff7
-#define CFG_LBC_LCRR		0x00030002	/* local bus freq	*/
-#define CFG_LBC_LBCR		0x00000000
-#define CFG_LBC_LSRT		0x20000000
-#define CFG_LBC_MRTPR		0x20000000
-#define CFG_LBC_LSDMR_1		0x2861b723
-#define CFG_LBC_LSDMR_2		0x0861b723
-#define CFG_LBC_LSDMR_3		0x0861b723
-#define CFG_LBC_LSDMR_4		0x1861b723
-#define CFG_LBC_LSDMR_5		0x4061b723
+#define CONFIG_SYS_BR6_PRELIM		0xe0001801	/* 64M, 32-bit flash */
+#define CONFIG_SYS_OR6_PRELIM		0xfc000ff7
+#define CONFIG_SYS_LBC_LCRR		0x00030002	/* local bus freq	*/
+#define CONFIG_SYS_LBC_LBCR		0x00000000
+#define CONFIG_SYS_LBC_LSRT		0x20000000
+#define CONFIG_SYS_LBC_MRTPR		0x20000000
+#define CONFIG_SYS_LBC_LSDMR_1		0x2861b723
+#define CONFIG_SYS_LBC_LSDMR_2		0x0861b723
+#define CONFIG_SYS_LBC_LSDMR_3		0x0861b723
+#define CONFIG_SYS_LBC_LSDMR_4		0x1861b723
+#define CONFIG_SYS_LBC_LSDMR_5		0x4061b723
 
 /* just hijack the MOT BCSR def for SBC8560 misc devices */
-#define CFG_BCSR		((CFG_BR5_PRELIM & 0xff000000)|0x00400000)
+#define CONFIG_SYS_BCSR		((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
 /* the size of CS5 needs to be >= 16M for TLB and LAW setups */
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0x70000000	/* Initial RAM address	*/
-#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000	/* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #undef  CONFIG_CONS_ON_SCC			/* define if console on SCC */
@@ -204,33 +202,33 @@
 
 #define CONFIG_CONS_INDEX     1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
 #if 0
-#define CFG_NS16550_CLK		1843200 /* get_bus_freq(0) */
+#define CONFIG_SYS_NS16550_CLK		1843200 /* get_bus_freq(0) */
 #else
-#define CFG_NS16550_CLK		264000000 /* get_bus_freq(0) */
+#define CONFIG_SYS_NS16550_CLK		264000000 /* get_bus_freq(0) */
 #endif
 
 #define CONFIG_BAUDRATE		9600
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
 #if 0
-#define CFG_NS16550_COM1	((CFG_BR5_PRELIM & 0xff000000)+0x00700000)
-#define CFG_NS16550_COM2	((CFG_BR5_PRELIM & 0xff000000)+0x00800000)
+#define CONFIG_SYS_NS16550_COM1	((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
+#define CONFIG_SYS_NS16550_COM2	((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
 #else
 /* SBC8540 uses internal COMM controller */
-#define CFG_NS16550_COM1	((CFG_CCSRBAR & 0xfff00000)+0x00004500)
-#define CFG_NS16550_COM2	((CFG_CCSRBAR & 0xfff00000)+0x00004600)
+#define CONFIG_SYS_NS16550_COM1	((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004500)
+#define CONFIG_SYS_NS16550_COM2	((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004600)
 #endif
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /*
@@ -239,14 +237,14 @@
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
 
-#define CFG_PCI_MEM_BASE	0xC0000000
-#define CFG_PCI_MEM_PHYS	0xC0000000
-#define CFG_PCI_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCI_MEM_BASE	0xC0000000
+#define CONFIG_SYS_PCI_MEM_PHYS	0xC0000000
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000
 
 #if defined(CONFIG_TSEC_ENET)		/* TSEC Ethernet port */
 
@@ -273,10 +271,10 @@
      * - Select bus for bd/buffers
      * - Full duplex
      */
-    #define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-    #define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-    #define CFG_CPMFCR_RAMTYPE	0
-    #define CFG_FCC_PSMR	(FCC_PSMR_FDE)
+    #define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+    #define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+    #define CONFIG_SYS_CPMFCR_RAMTYPE	0
+    #define CONFIG_SYS_FCC_PSMR	(FCC_PSMR_FDE)
 
   #elif (CONFIG_ETHER_INDEX == 3)
     /* need more definitions here for FE3 */
@@ -306,46 +304,46 @@
  * FLASH and environment organization
  */
 
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver		*/
 #if 0
-#define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
-#define CFG_FLASH_PROTECTION		/* use hardware protection		*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
+#define CONFIG_SYS_FLASH_PROTECTION		/* use hardware protection		*/
 #endif
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
 
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	200000		/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	50000		/* Timeout for Flash Write (in ms)	*/
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	200000		/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	50000		/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
 
 #if 0
 /* XXX This doesn't work and I don't want to fix it */
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-  #define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+  #define CONFIG_SYS_RAMBOOT
 #else
-  #undef  CFG_RAMBOOT
+  #undef  CONFIG_SYS_RAMBOOT
 #endif
 #endif
 
 /* Environment */
-#if !defined(CFG_RAMBOOT)
+#if !defined(CONFIG_SYS_RAMBOOT)
   #if defined(CONFIG_RAM_AS_FLASH)
     #define CONFIG_ENV_IS_NOWHERE
-    #define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + 0x100000)
+    #define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + 0x100000)
     #define CONFIG_ENV_SIZE	0x2000
   #else
     #define CONFIG_ENV_IS_IN_FLASH	1
     #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
-    #define CONFIG_ENV_ADDR	(CFG_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+    #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
     #define CONFIG_ENV_SIZE	0x2000 /* CONFIG_ENV_SECT_SIZE */
   #endif
 #else
-  #define CFG_NO_FLASH		1	/* Flash is not usable now	*/
+  #define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now	*/
   #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
-  #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
   #define CONFIG_ENV_SIZE		0x2000
 #endif
 
@@ -355,7 +353,7 @@
 #define CONFIG_BOOTDELAY	5	/* -1 disable autoboot */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 
 /*
@@ -383,8 +381,8 @@
     #define CONFIG_CMD_MII
 #endif
 
-#if defined(CFG_RAMBOOT)
-    #undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 
@@ -394,25 +392,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"SBC8540=> " /* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"SBC8540=> " /* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-  #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+  #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-  #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+  #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x1000000	/* default load address */
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*
  * Internal Definitions
diff --git a/include/configs/SCM.h b/include/configs/SCM.h
index 50cf499..c6fb074 100644
--- a/include/configs/SCM.h
+++ b/include/configs/SCM.h
@@ -75,8 +75,8 @@
 /* enable I2C and select the hardware/software driver */
 #undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * Software (bit-bang) I2C driver configuration
@@ -92,10 +92,10 @@
 			else    iop->pdat &= ~0x00020000
 #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
 
-#define CFG_I2C_EEPROM_ADDR	0x50
-#define CFG_I2C_EEPROM_ADDR_LEN 2
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
 #define CONFIG_I2C_X
 
@@ -151,10 +151,10 @@
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
 
@@ -164,10 +164,10 @@
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 
@@ -186,7 +186,7 @@
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -214,27 +214,27 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START 0x0400000	/* memtest works on		*/
-#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START 0x0400000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM		*/
 
-#define	CFG_LOAD_ADDR	0x100000	/* default load address		*/
+#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address		*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define	CFG_RESET_ADDRESS 0xFFFFFFFC	/* "bad" address		*/
+#define	CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC	/* "bad" address		*/
 
 #define CONFIG_MISC_INIT_R		/* have misc_init_r() function	*/
 
@@ -243,35 +243,35 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 
 
 /* What should the base address of the main FLASH be and how big is
  * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk
  * The main FLASH is whichever is connected to *CS0.
  */
-#define CFG_FLASH0_BASE 0x40000000
-#define CFG_FLASH1_BASE 0x60000000
-#define CFG_FLASH0_SIZE 32
-#define CFG_FLASH1_SIZE 32
+#define CONFIG_SYS_FLASH0_BASE 0x40000000
+#define CONFIG_SYS_FLASH1_BASE 0x60000000
+#define CONFIG_SYS_FLASH0_SIZE 32
+#define CONFIG_SYS_FLASH1_SIZE 32
 
 /* Flash bank size (for preliminary settings)
  */
-#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
+#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
 
 #if 0
 /* Start port with environment in flash; switch to EEPROM later */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE+0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x40000)
 #define CONFIG_ENV_SIZE		0x40000
 #define CONFIG_ENV_SECT_SIZE	0x40000
 #else
@@ -284,63 +284,63 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  *
- * if you change bits in the HRCW, you must also change the CFG_*
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
  * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
  */
 #if defined(CONFIG_266MHz)
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
 							      HRCW_MODCK_H0111)
 #elif defined(CONFIG_300MHz)
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
 							      HRCW_MODCK_H0110)
 #else
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
 #endif
 
 /* no slaves so just fill with zeros */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  *
- * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
+ * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
  * is mapped at SDRAM_BASE2_PRELIM.
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		CFG_FLASH0_BASE
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
 
 /*
  * Internal Definitions
@@ -354,16 +354,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 #if defined(CONFIG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -376,28 +376,28 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 				HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
-#define CFG_HID2        0
+#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2        0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register                                     5-5
  *-----------------------------------------------------------------------
  * turn on Checkstop Reset Enable
  */
-#define CFG_RMR         RMR_CSRE
+#define CONFIG_SYS_RMR         RMR_CSRE
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration                                       4-25
  *-----------------------------------------------------------------------
  */
 #ifdef	CONFIG_BUSMODE_60x
-#define CFG_BCR         (BCR_EBM|BCR_L2C|BCR_LETM|\
+#define CONFIG_SYS_BCR         (BCR_EBM|BCR_L2C|BCR_LETM|\
 			 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2)	/* 60x mode  */
 #else
 #define BCR_APD01	0x10000000
-#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -405,9 +405,9 @@
  *-----------------------------------------------------------------------
  */
 #if 0
-#define CFG_SIUMCR      (SIUMCR_DPPC10|SIUMCR_APPC10)
+#define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC10|SIUMCR_APPC10)
 #else
-#define CFG_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10)
+#define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10)
 #endif
 
 
@@ -418,10 +418,10 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
@@ -431,7 +431,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control                 4-42
@@ -439,20 +439,20 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control                                   9-8
  *-----------------------------------------------------------------------
  * Ensure DFBRG is Divide by 16
  */
-#define CFG_SCCR        0
+#define CONFIG_SYS_SCCR        0
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration                         13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR        0
+#define CONFIG_SYS_RCCR        0
 
 /*
  * Init Memory Controller:
@@ -467,17 +467,17 @@
 
 	/* Initialize SDRAM on local bus
 	 */
-#define CFG_INIT_LOCAL_SDRAM
+#define CONFIG_SYS_INIT_LOCAL_SDRAM
 
 #define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
 
 /* Minimum mask to separate preliminary
  * address ranges for CS[0:2]
  */
-#define CFG_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
-#define CFG_LOCAL_SDRAM_LIMIT	(128<<20)	/* less than 128 MB */
+#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
+#define CONFIG_SYS_LOCAL_SDRAM_LIMIT	(128<<20)	/* less than 128 MB */
 
-#define CFG_MPTPR       0x4000
+#define CONFIG_SYS_MPTPR       0x4000
 
 /*-----------------------------------------------------------------------------
  * Address for Mode Register Set (MRS) command
@@ -494,17 +494,17 @@
  *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
  *-----------------------------------------------------------------------------
  */
-#define CFG_MRS_OFFS	0x00000110
+#define CONFIG_SYS_MRS_OFFS	0x00000110
 
 
 /* Bank 0 - FLASH
  */
-#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_64                      |\
 			 BRx_MS_GPCM_P                  |\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 			 ORxG_CSNT                      |\
 			 ORxG_ACS_DIV1                  |\
 			 ORxG_SCY_3_CLK                 |\
@@ -517,25 +517,25 @@
 
 /* Bank 1 - 60x bus SDRAM
  */
-#define CFG_PSRT        0x20
-#define CFG_LSRT        0x20
-#ifndef CFG_RAMBOOT
-#define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+#define CONFIG_SYS_PSRT        0x20
+#define CONFIG_SYS_LSRT        0x20
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_64                      |\
 			 BRx_MS_SDRAM_P                 |\
 			 BRx_V)
 
-#define CFG_OR1_PRELIM	CFG_OR1_8COL
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR1_8COL
 
 
 	/* SDRAM initialization values for 8-column chips
 	 */
-#define CFG_OR1_8COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+#define CONFIG_SYS_OR1_8COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI1_A7             |\
 			 ORxS_NUMR_12)
 
-#define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
+#define CONFIG_SYS_PSDMR_8COL  (PSDMR_PBI                      |\
 			 PSDMR_SDAM_A15_IS_A5           |\
 			 PSDMR_BSMA_A12_A14             |\
 			 PSDMR_SDA10_PBI1_A8            |\
@@ -549,12 +549,12 @@
 
 	/* SDRAM initialization values for 9-column chips
 	 */
-#define CFG_OR1_9COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+#define CONFIG_SYS_OR1_9COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI1_A5             |\
 			 ORxS_NUMR_13)
 
-#define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
+#define CONFIG_SYS_PSDMR_9COL  (PSDMR_PBI                      |\
 			 PSDMR_SDAM_A16_IS_A5           |\
 			 PSDMR_BSMA_A12_A14             |\
 			 PSDMR_SDA10_PBI1_A7            |\
@@ -568,24 +568,24 @@
 
 /* Bank 2 - Local bus SDRAM
  */
-#ifdef CFG_INIT_LOCAL_SDRAM
-#define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
+#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
+#define CONFIG_SYS_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
 			 BRx_PS_32                      |\
 			 BRx_MS_SDRAM_L                 |\
 			 BRx_V)
 
-#define CFG_OR2_PRELIM	CFG_OR2_8COL
+#define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_OR2_8COL
 
 #define SDRAM_BASE2_PRELIM	0x80000000
 
 	/* SDRAM initialization values for 8-column chips
 	 */
-#define CFG_OR2_8COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+#define CONFIG_SYS_OR2_8COL    ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI1_A8             |\
 			 ORxS_NUMR_12)
 
-#define CFG_LSDMR_8COL  (PSDMR_PBI                      |\
+#define CONFIG_SYS_LSDMR_8COL  (PSDMR_PBI                      |\
 			 PSDMR_SDAM_A15_IS_A5           |\
 			 PSDMR_BSMA_A13_A15             |\
 			 PSDMR_SDA10_PBI1_A9            |\
@@ -599,12 +599,12 @@
 
 	/* SDRAM initialization values for 9-column chips
 	 */
-#define CFG_OR2_9COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+#define CONFIG_SYS_OR2_9COL    ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI1_A6             |\
 			 ORxS_NUMR_13)
 
-#define CFG_LSDMR_9COL  (PSDMR_PBI                      |\
+#define CONFIG_SYS_LSDMR_9COL  (PSDMR_PBI                      |\
 			 PSDMR_SDAM_A16_IS_A5           |\
 			 PSDMR_BSMA_A13_A15             |\
 			 PSDMR_SDA10_PBI1_A8            |\
@@ -616,53 +616,53 @@
 			 PSDMR_WRC_2C                   |\
 			 PSDMR_CL_2)
 
-#endif /* CFG_INIT_LOCAL_SDRAM */
+#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
-#define CFG_CAN0_BASE		0xc0000000
-#define CFG_CAN1_BASE		0xc0008000
-#define CFG_FIOX_BASE		0xc0010000
-#define CFG_FDOHM_BASE		0xc0018000
-#define CFG_EXTPROM_BASE	0xc2000000
+#define CONFIG_SYS_CAN0_BASE		0xc0000000
+#define CONFIG_SYS_CAN1_BASE		0xc0008000
+#define CONFIG_SYS_FIOX_BASE		0xc0010000
+#define CONFIG_SYS_FDOHM_BASE		0xc0018000
+#define CONFIG_SYS_EXTPROM_BASE	0xc2000000
 
-#define CFG_CAN_SIZE		0x00000100
-#define CFG_FIOX_SIZE		0x00000020
-#define CFG_FDOHM_SIZE		0x00002000
-#define CFG_EXTPROM_BANK_SIZE	0x01000000
+#define CONFIG_SYS_CAN_SIZE		0x00000100
+#define CONFIG_SYS_FIOX_SIZE		0x00000020
+#define CONFIG_SYS_FDOHM_SIZE		0x00002000
+#define CONFIG_SYS_EXTPROM_BANK_SIZE	0x01000000
 
 #define EXT_EEPROM_MAX_FLASH_BANKS	0x02
 
 /* CS3 - CAN 0
  */
-#define CFG_CAN0_BR3   ((CFG_CAN0_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_CAN0_BR3   ((CONFIG_SYS_CAN0_BASE & BRx_BA_MSK)	|\
 			BRx_PS_8			|\
 			BRx_MS_UPMA			|\
 			BRx_V)
 
-#define CFG_CAN0_OR3   (P2SZ_TO_AM(CFG_CAN_SIZE)	|\
+#define CONFIG_SYS_CAN0_OR3   (P2SZ_TO_AM(CONFIG_SYS_CAN_SIZE)	|\
 			ORxU_BI				|\
 			ORxU_EHTR_4IDLE)
 
 /* CS4 - CAN 1
  */
-#define CFG_CAN1_BR4   ((CFG_CAN1_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_CAN1_BR4   ((CONFIG_SYS_CAN1_BASE & BRx_BA_MSK)	|\
 			BRx_PS_8			|\
 			BRx_MS_UPMA			|\
 			BRx_V)
 
-#define CFG_CAN1_OR4   (P2SZ_TO_AM(CFG_CAN_SIZE)	|\
+#define CONFIG_SYS_CAN1_OR4   (P2SZ_TO_AM(CONFIG_SYS_CAN_SIZE)	|\
 			ORxU_BI				|\
 			ORxU_EHTR_4IDLE)
 
 /* CS5 - Extended PROM (16MB optional)
  */
-#define CFG_EXTPROM_BR5 ((CFG_EXTPROM_BASE & BRx_BA_MSK)|\
+#define CONFIG_SYS_EXTPROM_BR5 ((CONFIG_SYS_EXTPROM_BASE & BRx_BA_MSK)|\
 			BRx_PS_32			|\
 			BRx_MS_GPCM_P			|\
 			BRx_V)
 
-#define CFG_EXTPROM_OR5 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\
+#define CONFIG_SYS_EXTPROM_OR5 (P2SZ_TO_AM(CONFIG_SYS_EXTPROM_BANK_SIZE)|\
 			ORxG_CSNT			|\
 			ORxG_ACS_DIV4			|\
 			ORxG_SCY_5_CLK			|\
@@ -670,13 +670,13 @@
 
 /* CS6 - Extended PROM (16MB optional)
  */
-#define CFG_EXTPROM_BR6 (((CFG_EXTPROM_BASE + \
-			CFG_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\
+#define CONFIG_SYS_EXTPROM_BR6 (((CONFIG_SYS_EXTPROM_BASE + \
+			CONFIG_SYS_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\
 			BRx_PS_32			|\
 			BRx_MS_GPCM_P			|\
 			BRx_V)
 
-#define CFG_EXTPROM_OR6 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\
+#define CONFIG_SYS_EXTPROM_OR6 (P2SZ_TO_AM(CONFIG_SYS_EXTPROM_BANK_SIZE)|\
 			ORxG_CSNT			|\
 			ORxG_ACS_DIV4			|\
 			ORxG_SCY_5_CLK			|\
@@ -684,37 +684,37 @@
 
 /* CS7 - FPGA FIOX: Glue Logic
  */
-#define CFG_FIOX_BR7   ((CFG_FIOX_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_FIOX_BR7   ((CONFIG_SYS_FIOX_BASE & BRx_BA_MSK)	|\
 			BRx_PS_32			|\
 			BRx_MS_GPCM_P			|\
 			BRx_V)
 
-#define CFG_FIOX_OR7   (P2SZ_TO_AM(CFG_FIOX_SIZE)	|\
+#define CONFIG_SYS_FIOX_OR7   (P2SZ_TO_AM(CONFIG_SYS_FIOX_SIZE)	|\
 			ORxG_ACS_DIV4			|\
 			ORxG_SCY_5_CLK			|\
 			ORxG_TRLX)
 
 /* CS8 - FPGA DOH Master
  */
-#define CFG_FDOHM_BR8  ((CFG_FDOHM_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_FDOHM_BR8  ((CONFIG_SYS_FDOHM_BASE & BRx_BA_MSK)	|\
 			BRx_PS_16			|\
 			BRx_MS_GPCM_P			|\
 			BRx_V)
 
-#define CFG_FDOHM_OR8  (P2SZ_TO_AM(CFG_FDOHM_SIZE)	|\
+#define CONFIG_SYS_FDOHM_OR8  (P2SZ_TO_AM(CONFIG_SYS_FDOHM_SIZE)	|\
 			ORxG_ACS_DIV4			|\
 			ORxG_SCY_5_CLK			|\
 			ORxG_TRLX)
 
 
 /* FPGA configuration */
-#define CFG_PD_FIOX_PROG	(1 << (31- 5))	/* PD  5 */
-#define CFG_PD_FIOX_DONE	(1 << (31-28))	/* PD 28 */
-#define CFG_PD_FIOX_INIT	(1 << (31-29))	/* PD 29 */
+#define CONFIG_SYS_PD_FIOX_PROG	(1 << (31- 5))	/* PD  5 */
+#define CONFIG_SYS_PD_FIOX_DONE	(1 << (31-28))	/* PD 28 */
+#define CONFIG_SYS_PD_FIOX_INIT	(1 << (31-29))	/* PD 29 */
 
-#define CFG_PD_FDOHM_PROG	(1 << (31- 4))	/* PD  4 */
-#define CFG_PD_FDOHM_DONE	(1 << (31-26))	/* PD 26 */
-#define CFG_PD_FDOHM_INIT	(1 << (31-27))	/* PD 27 */
+#define CONFIG_SYS_PD_FDOHM_PROG	(1 << (31- 4))	/* PD  4 */
+#define CONFIG_SYS_PD_FDOHM_DONE	(1 << (31-26))	/* PD 26 */
+#define CONFIG_SYS_PD_FDOHM_INIT	(1 << (31-27))	/* PD 27 */
 
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
new file mode 100644
index 0000000..b939cfa
--- /dev/null
+++ b/include/configs/SIMPC8313.h
@@ -0,0 +1,547 @@
+/*
+ * Copyright (C) Sheldon Instruments, Inc. 2008
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * simpc8313 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_NAND_U_BOOT
+
+#define CONFIG_E300			1
+#define CONFIG_MPC83XX			1
+#define CONFIG_MPC831X			1
+#define CONFIG_MPC8313			1
+
+#define CONFIG_PCI
+#define CONFIG_83XX_GENERIC_PCI
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ *
+ * TSEC1 is Marvell PHY 88E1118
+ */
+
+#define CONFIG_SYS_33MHZ
+
+#define CONFIG_83XX_CLKIN		33333333	/* in Hz */
+
+#define CONFIG_SYS_CLK_FREQ		CONFIG_83XX_CLKIN
+
+#define CONFIG_SYS_IMMR			0xE0000000
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_DEFAULT_IMMR		CONFIG_SYS_IMMR
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00001000
+#define CONFIG_SYS_MEMTEST_END		0x07f00000
+
+#define CONFIG_SYS_ACR_PIPE_DEP		3	/* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
+
+/*
+ * Device configurations
+ */
+#define CONFIG_TSEC1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_MAX_MEM_MAPPED		(512 << 20)
+
+#define CONFIG_SYS_DDRCDR		( DDRCDR_EN \
+					| DDRCDR_PZ_NOMZ \
+					| DDRCDR_NZ_NOMZ \
+					| DDRCDR_M_ODR )
+					/* 0x73000002 TODO ODR & DRN ? */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#if !defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END		0x1000		/* End of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ */
+#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
+#define CONFIG_SYS_LBC_LBCR	(0x00040000 /* TODO */ \
+				| (0xFF << LBCR_BMT_SHIFT) \
+				| 0xF )	/* 0x0004ff0f */
+
+#define CONFIG_SYS_LBC_MRTPR	0x20000000	/* LB refresh timer prescal, 266MHz/32 */
+
+/* drivers/mtd/nand/nand.c */
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE		0xFFF00000
+#else
+#define CONFIG_SYS_NAND_BASE		0xE2800000
+#endif
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND 		1
+#define CONFIG_NAND_FSL_ELBC		1
+
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00100100
+#define CONFIG_SYS_NAND_U_BOOT_RELOC	0x00010000
+
+#define CONFIG_SYS_NAND_BR_PRELIM	( CONFIG_SYS_NAND_BASE \
+					| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+					| BR_PS_8		/* Port Size = 8 bit */ \
+					| BR_MS_FCM		/* MSEL = FCM */ \
+					| BR_V )		/* valid */
+
+#ifdef CONFIG_NAND_SP
+#define CONFIG_SYS_NAND_OR_PRELIM	( 0xFFFF8000	/* length 32K */ \
+					| OR_FCM_CSCT \
+					| OR_FCM_CST \
+					| OR_FCM_CHT \
+					| OR_FCM_SCY_1 \
+					| OR_FCM_TRLX \
+					| OR_FCM_EHTR )
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x8000000E	/* 32KB */
+#define CONFIG_SYS_NAND_PAGE_SIZE	(512)		/* NAND chip page size */
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size */
+#define NAND_CACHE_PAGES		32
+#elif defined(CONFIG_NAND_LP)
+#define CONFIG_SYS_NAND_OR_PRELIM	( 0xFFFC0000	/* length 256K */ \
+					| OR_FCM_PGS \
+					| OR_FCM_CSCT \
+					| OR_FCM_CST \
+					| OR_FCM_CHT \
+					| OR_FCM_SCY_1 \
+					| OR_FCM_TRLX \
+					| OR_FCM_EHTR )
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000011	/* 256KB */
+#define CONFIG_SYS_NAND_PAGE_SIZE	(2048)		/* NAND chip page size */
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)	/* NAND chip block size */
+#define NAND_CACHE_PAGES		64
+#else
+#error Page size of NAND not defined.
+#endif /* CONFIG_NAND_SP */
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SYS_NAND_BLOCK_SIZE
+
+#define CONFIG_SYS_BR0_PRELIM		CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR0_PRELIM		CONFIG_SYS_NAND_OR_PRELIM
+
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM	CONFIG_SYS_LBLAWBAR0_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM	CONFIG_SYS_LBLAWAR0_PRELIM
+
+/*
+ * JFFS2 configuration
+ */
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_DEV	"nand0"
+
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nand0=nand0"
+#define MTDPARTS_DEFAULT	"mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1		(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2		(CONFIG_SYS_IMMR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support*/
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES		{{0,0x69}} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1057	/* Motorola */
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET		/* TSEC ethernet support */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_GMII			/* MII PHY management */
+
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME		"TSEC0"
+#define CONFIG_SYS_TSEC1_OFFSET		0x24000
+#define TSEC1_PHY_ADDR			0x0
+#define TSEC1_FLAGS			TSEC_GIGABIT
+#define TSEC1_PHYIDX			0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME		"TSEC1"
+#define CONFIG_SYS_TSEC2_OFFSET		0x25000
+#define TSEC2_PHY_ADDR			4
+#define TSEC2_FLAGS			TSEC_GIGABIT
+#define TSEC2_PHYIDX			0
+#endif
+
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME			"TSEC1"
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_NAND_U_BOOT)
+	#define CONFIG_ENV_IS_IN_NAND		1
+	#define CONFIG_ENV_OFFSET		(768 * 1024)
+	#define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+	#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+	#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+	#define CONFIG_ENV_RANGE		(CONFIG_ENV_SECT_SIZE * 4)
+	#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+#elif !defined(CONFIG_SYS_RAMBOOT)
+	#define CONFIG_ENV_IS_IN_FLASH		1
+	#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_SECT_SIZE		0x10000	/* 64K(one sector) for env */
+	#define CONFIG_ENV_SIZE			0x2000
+
+/* Address and size of Redundant Environment Sector */
+#else
+	#define CONFIG_ENV_IS_NOWHERE		1	/* Store ENV in memory only */
+	#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE			0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO			1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE		1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_JFFS2
+
+#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
+	#undef CONFIG_CMD_SAVEENV
+	#undef CONFIG_CMD_LOADS
+#endif
+
+#define CONFIG_CMDLINE_EDITING		1
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size */
+
+#define CONFIG_SYS_PBSIZE		( CONFIG_SYS_CBSIZE		\
+					+ sizeof(CONFIG_SYS_PROMPT)	\
+					+ 16 )	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux*/
+
+#define CONFIG_SYS_RCWH_PCIHOST		0x80000000	/* PCIHOST */
+
+#define CONFIG_SYS_HRCW_LOW		( HRCWL_LCL_BUS_TO_SCB_CLK_1X1	\
+					| 0x20000000 /* reserved */	\
+					| HRCWL_DDR_TO_SCB_CLK_2X1	\
+					| HRCWL_CSB_TO_CLKIN_4X1	\
+					| HRCWL_CORE_TO_CSB_2_5X1 )
+
+#define CONFIG_SYS_NS16550_CLK		(CONFIG_83XX_CLKIN * 4)
+
+#define CONFIG_SYS_HRCW_HIGH_BASE	( HRCWH_PCI_HOST		\
+					| HRCWH_PCI1_ARBITER_ENABLE	\
+					| HRCWH_CORE_ENABLE		\
+					| HRCWH_BOOTSEQ_DISABLE		\
+					| HRCWH_SW_WATCHDOG_DISABLE	\
+					| HRCWH_TSEC1M_IN_RGMII		\
+					| HRCWH_TSEC2M_IN_RGMII		\
+					| HRCWH_BIG_ENDIAN		\
+					| HRCWH_LALE_NORMAL )
+
+#ifdef CONFIG_NAND_LP
+#define CONFIG_SYS_HRCW_HIGH	( CONFIG_SYS_HRCW_HIGH_BASE		\
+				| HRCWH_FROM_0XFFF00100			\
+				| HRCWH_ROM_LOC_NAND_LP_8BIT		\
+				| HRCWH_RL_EXT_NAND)
+#else
+#define CONFIG_SYS_HRCW_HIGH	( CONFIG_SYS_HRCW_HIGH_BASE		\
+				| HRCWH_FROM_0XFFF00100			\
+				| HRCWH_ROM_LOC_NAND_SP_8BIT		\
+				| HRCWH_RL_EXT_NAND )
+#endif
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH	( SICRH_ETSEC2_B	\
+				| SICRH_ETSEC2_C	\
+				| SICRH_ETSEC2_D	\
+				| SICRH_ETSEC2_E	\
+				| SICRH_ETSEC2_F	\
+				| SICRH_ETSEC2_G	\
+				| SICRH_TSOBI1		\
+				| SICRH_TSOBI2 )
+#define CONFIG_SYS_SICRL	(SICRL_USBDR		\
+				| SICRL_ETSEC2_A )
+
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK	\
+				| HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
+
+#define CONFIG_SYS_HID2		HID2_HBE
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* DDR @ 0x00000000 */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10)
+#define CONFIG_SYS_IBAT1U	((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI @ 0x80000000 */
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI2 not supported on 8313 */
+#define CONFIG_SYS_IBAT4L	(0)
+#define CONFIG_SYS_IBAT4U	(0)
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02	/* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NETDEV		eth1
+
+#define CONFIG_HOSTNAME		simpc8313
+#define CONFIG_ROOTPATH		/tftpboot/
+#define CONFIG_BOOTFILE		/tftpboot/uImage
+#define CONFIG_UBOOTPATH	u-boot-nand.bin	/* U-Boot image on TFTP server */
+#define CONFIG_FDTFILE		simpc8313.dtb
+
+#define CONFIG_LOADADDR		500000	/* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY	5	/* 5 second delay */
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_BOOTCOMMAND	"nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr"
+
+#define XMK_STR(x)	#x
+#define MK_STR(x)	XMK_STR(x)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" MK_STR(CONFIG_NETDEV) "\0"				\
+	"ethprime=TSEC1\0"						\
+	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
+	"tftpflash=tftpboot $loadaddr $uboot; "				\
+		"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
+		"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
+		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
+		"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
+		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
+	"fdtaddr=ae0000\0"						\
+	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"				\
+	"console=ttyS0\0"						\
+	"setbootargs=setenv bootargs "					\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	 \
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"	\
+	"load_uboot=tftp 100000 u-boot-nand.bin\0"			\
+	"burn_uboot=nand erase u-boot 80000; "				\
+		"nand write 100000 u-boot $filesize\0"			\
+	"update_uboot=run load_uboot;run burn_uboot\0"			\
+	"mtdids=nand0=nand0\0"						\
+	"mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0"	\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"	\
+	"bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw "		\
+		"console=ttyS0,115200\0"				\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv rootdev /dev/nfs;"					\
+	"run setbootargs;"						\
+	"run setipargs;"						\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv rootdev /dev/ram;"					\
+	"run setbootargs;"						\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#undef MK_STR
+#undef XMK_STR
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/SL8245.h b/include/configs/SL8245.h
index 89d1461..876d882 100644
--- a/include/configs/SL8245.h
+++ b/include/configs/SL8245.h
@@ -47,7 +47,7 @@
 
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_BOOTDELAY	5
 
@@ -74,70 +74,70 @@
 /*
  * Miscellaneous configurable options
  */
-#undef CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#undef CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 
 /* Print Buffer Size
  */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS	32		/* Max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00400000	/* Default load address		*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	32		/* Max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x00400000	/* Default load address		*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
 
-#define CFG_FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank on RCS#0 */
-#define CFG_FLASH_BASE		CFG_FLASH_BASE0_PRELIM
-#define CFG_FLASH_BANKS		{ CFG_FLASH_BASE0_PRELIM }
+#define CONFIG_SYS_FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank on RCS#0 */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH_BASE0_PRELIM
+#define CONFIG_SYS_FLASH_BANKS		{ CONFIG_SYS_FLASH_BASE0_PRELIM }
 
-#define CFG_RESET_ADDRESS   0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 
-#define CFG_EUMB_ADDR	    0xFC000000
+#define CONFIG_SYS_EUMB_ADDR	    0xFC000000
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
 
-#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
 
 	/* Maximum amount of RAM.
 	 */
-#define CFG_MAX_RAM_SIZE    0x10000000	/* 0 .. 256 MB of (S)DRAM */
+#define CONFIG_SYS_MAX_RAM_SIZE    0x10000000	/* 0 .. 256 MB of (S)DRAM */
 
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#undef CFG_RAMBOOT
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#undef CONFIG_SYS_RAMBOOT
 #else
-#define CFG_RAMBOOT
+#define CONFIG_SYS_RAMBOOT
 #endif
 
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
 
-#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_REG_SIZE	1
 
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_EUMB_ADDR + 0x4500)
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area
  */
 
-#define CFG_GBL_DATA_SIZE      128
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_SIZE      128
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_END      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 /*
  * Low Level Configuration Settings
@@ -147,40 +147,40 @@
  */
 
 #define CONFIG_SYS_CLK_FREQ  66666666	/* external frequency to pll */
-#define CFG_HZ		     1000
+#define CONFIG_SYS_HZ		     1000
 
 	/* Bit-field values for MCCR1.
 	 */
-#define CFG_ROMNAL	    0
-#define CFG_ROMFAL	    7
-#define CFG_BANK0_ROW       2
+#define CONFIG_SYS_ROMNAL	    0
+#define CONFIG_SYS_ROMFAL	    7
+#define CONFIG_SYS_BANK0_ROW       2
 
 	/* Bit-field values for MCCR2.
 	 */
-#define CFG_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
+#define CONFIG_SYS_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
 
 	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 	 */
-#define CFG_BSTOPRE	    192
+#define CONFIG_SYS_BSTOPRE	    192
 
 	/* Bit-field values for MCCR3.
 	 */
-#define CFG_REFREC	    2	    /* Refresh to activate interval */
+#define CONFIG_SYS_REFREC	    2	    /* Refresh to activate interval */
 
 	/* Bit-field values for MCCR4.
 	 */
-#define CFG_PRETOACT	    2	    /* Precharge to activate interval */
-#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval */
-#define CFG_ACTORW	    3       /* FIXME was 2 */
-#define CFG_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
-#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
-#define CFG_REGISTERD_TYPE_BUFFER 1
-#define CFG_EXTROM	    1
-#define CFG_REGDIMM	    0
-
-#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
+#define CONFIG_SYS_PRETOACT	    2	    /* Precharge to activate interval */
+#define CONFIG_SYS_ACTTOPRE	    5	    /* Activate to Precharge interval */
+#define CONFIG_SYS_ACTORW	    3       /* FIXME was 2 */
+#define CONFIG_SYS_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
+#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
+#define CONFIG_SYS_EXTROM	    1
+#define CONFIG_SYS_REGDIMM	    0
+
+#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
 					/* see 8245 book for bit definitions	*/
-#define CFG_PGMAX		0x32	/* how long the 8245 retains the	*/
+#define CONFIG_SYS_PGMAX		0x32	/* how long the 8245 retains the	*/
 					/* currently accessed page in memory	*/
 					/* see 8245 book for details		*/
 
@@ -191,67 +191,67 @@
  * address. Refer to the MPC8240 book.
  */
 
-#define CFG_BANK0_START	    0x00000000
-#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START	    0x3ff00000
-#define CFG_BANK1_END	    0x3fffffff
-#define CFG_BANK1_ENABLE    0
-#define CFG_BANK2_START	    0x3ff00000
-#define CFG_BANK2_END	    0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START	    0x3ff00000
-#define CFG_BANK3_END	    0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START	    0x3ff00000
-#define CFG_BANK4_END	    0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START	    0x3ff00000
-#define CFG_BANK5_END	    0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START	    0x3ff00000
-#define CFG_BANK6_END	    0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START	    0x3ff00000
-#define CFG_BANK7_END	    0x3fffffff
-#define CFG_BANK7_ENABLE    0
-
-#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L  CFG_IBAT0L
-#define CFG_DBAT0U  CFG_IBAT0U
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-#define CFG_DBAT2L  CFG_IBAT2L
-#define CFG_DBAT2U  CFG_IBAT2U
-#define CFG_DBAT3L  CFG_IBAT3L
-#define CFG_DBAT3U  CFG_IBAT3U
+#define CONFIG_SYS_BANK0_START	    0x00000000
+#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE    1
+#define CONFIG_SYS_BANK1_START	    0x3ff00000
+#define CONFIG_SYS_BANK1_END	    0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE    0
+#define CONFIG_SYS_BANK2_START	    0x3ff00000
+#define CONFIG_SYS_BANK2_END	    0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE    0
+#define CONFIG_SYS_BANK3_START	    0x3ff00000
+#define CONFIG_SYS_BANK3_END	    0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE    0
+#define CONFIG_SYS_BANK4_START	    0x3ff00000
+#define CONFIG_SYS_BANK4_END	    0x3fffffff
+#define CONFIG_SYS_BANK4_ENABLE    0
+#define CONFIG_SYS_BANK5_START	    0x3ff00000
+#define CONFIG_SYS_BANK5_END	    0x3fffffff
+#define CONFIG_SYS_BANK5_ENABLE    0
+#define CONFIG_SYS_BANK6_START	    0x3ff00000
+#define CONFIG_SYS_BANK6_END	    0x3fffffff
+#define CONFIG_SYS_BANK6_ENABLE    0
+#define CONFIG_SYS_BANK7_START	    0x3ff00000
+#define CONFIG_SYS_BANK7_END	    0x3fffffff
+#define CONFIG_SYS_BANK7_ENABLE    0
+
+#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT	35	/* Max number of sectors per flash	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	35	/* Max number of sectors per flash	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
 
 
 	/* Warining: environment is not EMBEDDED in the U-Boot code.
@@ -265,9 +265,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SIZE	32
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /*
diff --git a/include/configs/SM850.h b/include/configs/SM850.h
index c896b58..4c469e3 100644
--- a/include/configs/SM850.h
+++ b/include/configs/SM850.h
@@ -60,7 +60,7 @@
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -93,25 +93,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB) && defined(KGDB_DEBUG)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -121,50 +121,50 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
 #if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET	0x8000	/*   Offset   of Environment Sector	*/
@@ -175,16 +175,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -194,10 +194,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -206,9 +206,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -216,20 +216,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -240,10 +240,10 @@
  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  */
 #ifdef TQM8xxL_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_PLPRCR							\
+#define CONFIG_SYS_PLPRCR							\
 		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
 #else
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 #endif	/* TQM8xxL_80MHz */
 
 /*-----------------------------------------------------------------------
@@ -254,12 +254,12 @@
  */
 #define SCCR_MASK	SCCR_EBDF11
 #ifdef TQM8xxL_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_SCCR	(/* SCCR_TBS  | */ \
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS  | */ \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 #else			/* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -270,21 +270,21 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -299,20 +299,20 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
 				 OR_SCY_5_CLK | OR_EHTR)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -323,19 +323,19 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 #ifndef	CONFIG_CAN_DRIVER
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 #endif	/* CONFIG_CAN_DRIVER */
 
@@ -344,26 +344,26 @@
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/SMN42.h b/include/configs/SMN42.h
index 45fe14b..45e6a58 100644
--- a/include/configs/SMN42.h
+++ b/include/configs/SMN42.h
@@ -49,8 +49,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -80,13 +80,13 @@
 #undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
 /* this would be 0xAE if E0, E1 and E2 were pulled high */
-#define CFG_I2C_SLAVE		0xA0
-#define CFG_I2C_EEPROM_ADDR	(0xA0 >> 1)
-#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit address */
-#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes per write */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+#define CONFIG_SYS_I2C_SLAVE		0xA0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xA0 >> 1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes per write */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
 /* not used but required by devices.c */
-#define CFG_I2C_SPEED 10000
+#define CONFIG_SYS_I2C_SPEED 10000
 
 #ifdef CONFIG_SOFT_I2C
 /*
@@ -129,26 +129,26 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"SMN42 # " /* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"SMN42 # " /* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x81800000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x83000000	/* 24 MB in SRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x81800000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x83000000	/* 24 MB in SRAM	*/
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0x81000000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x81000000	/* default load address	*/
 						/* for uClinux img is here*/
 
-#define CFG_SYS_CLK_FREQ	58982400	/* Hz */
-#define	CFG_HZ			2048		/* decrementer freq in Hz */
+#define CONFIG_SYS_SYS_CLK_FREQ	58982400	/* Hz */
+#define	CONFIG_SYS_HZ			2048		/* decrementer freq in Hz */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -177,23 +177,23 @@
  */
 
 /*
- * The first entry in CFG_FLASH_BANKS_LIST is a dummy, but it must be present.
+ * The first entry in CONFIG_SYS_FLASH_BANKS_LIST is a dummy, but it must be present.
  */
-#define CFG_FLASH_BANKS_LIST	{ 0, PHYS_FLASH_1 }
-#define CFG_FLASH_ADDR0			0x555
-#define CFG_FLASH_ADDR1			0x2AA
-#define CFG_FLASH_ERASE_TOUT	16384	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	5	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ 0, PHYS_FLASH_1 }
+#define CONFIG_SYS_FLASH_ADDR0			0x555
+#define CONFIG_SYS_FLASH_ADDR1			0x2AA
+#define CONFIG_SYS_FLASH_ERASE_TOUT	16384	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	5	/* Timeout for Flash Write (in ms) */
 
-#define CFG_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
+#define CONFIG_SYS_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
 
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 /* The Environment Sector is in the CPU-internal flash */
-#define CFG_FLASH_BASE		0
+#define CONFIG_SYS_FLASH_BASE		0
 #define CONFIG_ENV_OFFSET		0x3C000
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_SIZE		0x2000 /* Total Size of Environment Sector	*/
 
 #define CONFIG_CMDLINE_TAG
diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h
index 929a4b6..4181a40 100644
--- a/include/configs/SPD823TS.h
+++ b/include/configs/SPD823TS.h
@@ -55,7 +55,7 @@
 				"nfsaddrs=10.0.0.99:10.0.0.2"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -67,6 +67,7 @@
 
 #define CONFIG_CMD_IDE
 
+#undef CONFIG_CMD_SAVEENV
 #undef CONFIG_CMD_FLASH
 
 
@@ -94,29 +95,29 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x00100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */
 
-#define CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+#define CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
 
-#define CFG_PC_IDE_RESET	((ushort)0x0008)	/* PC 12	*/
+#define CONFIG_SYS_PC_IDE_RESET	((ushort)0x0008)	/* PC 12	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -126,46 +127,46 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000 /* was: 0xFF000000 */
+#define CONFIG_SYS_IMMR		0xFFF00000 /* was: 0xFF000000 */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
 #ifdef	DEBUG
-#define CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
 #else
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	0	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	0	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	0	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	0	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	0	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	0	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	0	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	0	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
@@ -173,9 +174,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -185,10 +186,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -197,21 +198,21 @@
  * PCMCIA config., multi-function pin tri-state
  */
 /* 0x00000040 */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -220,7 +221,7 @@
  * interrupt status bit, set PLL multiplication factor !
  */
 /* 0x00b0c0c0 */
-#define CFG_PLPRCR							\
+#define CONFIG_SYS_PLPRCR							\
 		(	(11 << PLPRCR_MF_SHIFT) |			\
 			PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
 			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
@@ -235,7 +236,7 @@
  */
 #define SCCR_MASK	SCCR_EBDF11
 /* 0x01800014 */
-#define CFG_SCCR	(SCCR_COM00	| /*SCCR_TBS|*/		\
+#define CONFIG_SYS_SCCR	(SCCR_COM00	| /*SCCR_TBS|*/		\
 			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
 			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
 			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
@@ -248,7 +249,7 @@
  *-----------------------------------------------------------------------
  */
 /* 0x00C3 */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 
 /*-----------------------------------------------------------------------
@@ -256,46 +257,46 @@
  *-----------------------------------------------------------------------
  */
 /* TIMEP=2 */
-#define CFG_RCCR 0x0200
+#define CONFIG_SYS_RCCR 0x0200
 
 /*-----------------------------------------------------------------------
  * RMDS - RISC Microcode Development Support Control Register
  *-----------------------------------------------------------------------
  */
-#define CFG_RMDS 0
+#define CONFIG_SYS_RMDS 0
 
 /*-----------------------------------------------------------------------
  * SDSR - SDMA Status Register
  *-----------------------------------------------------------------------
  */
-#define CFG_SDSR ((u_char)0x83)
+#define CONFIG_SYS_SDSR ((u_char)0x83)
 
 /*-----------------------------------------------------------------------
  * SDMR - SDMA Mask Register
  *-----------------------------------------------------------------------
  */
-#define CFG_SDMR ((u_char)0x00)
+#define CONFIG_SYS_SDMR ((u_char)0x00)
 
 /*-----------------------------------------------------------------------
  *
  * Interrupt Levels
  *-----------------------------------------------------------------------
  */
-#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
+#define CONFIG_SYS_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
@@ -305,23 +306,23 @@
 #define CONFIG_IDE_LED		1	/* LED   for ide supported	*/
 #define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
 
-#define CFG_IDE_MAXBUS		2	/* max. 2 IDE busses		*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		2	/* max. 2 IDE busses		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR	0xFE100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#define CFG_ATA_IDE1_OFFSET	0x0C00
+#define CONFIG_SYS_ATA_BASE_ADDR	0xFE100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0x0C00
 
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*/
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER 0
+#define CONFIG_SYS_DER 0
 
 /*
  * Init Memory Controller:
@@ -337,22 +338,22 @@
  * but not too much to meddle with FLASH accesses
  */
 /* EPROMs are 512kb */
-#define CFG_REMAP_OR_AM		0xFFF80000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0xFFF80000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
 
 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
 				 OR_SCY_5_CLK | OR_EHTR)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 /* 16 bit, bank valid */
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
 /* 16 bit, bank valid */
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 
 /*
  * BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC)
@@ -373,44 +374,44 @@
 
 /* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
 
-#define CFG_OR_TIMING_SRAM	0x00000D42	/* SRAM-Timing */
-#define CFG_OR2 (SRAM_OR_AM | CFG_OR_TIMING_SRAM )
-#define CFG_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_OR_TIMING_SRAM	0x00000D42	/* SRAM-Timing */
+#define CONFIG_SYS_OR2 (SRAM_OR_AM | CONFIG_SYS_OR_TIMING_SRAM )
+#define CONFIG_SYS_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
 
-#define CFG_OR_TIMING_SDRAM	0x00000A00	/* SDRAM-Timing */
-#define CFG_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00	/* SDRAM-Timing */
+#define CONFIG_SYS_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
 
-#define CFG_OR_TIMING_PER8	0x00000F32	/* PER8-Timing */
-#define CFG_OR4 (PER8_OR_AM | CFG_OR_TIMING_PER8 )
-#define CFG_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR_TIMING_PER8	0x00000F32	/* PER8-Timing */
+#define CONFIG_SYS_OR4 (PER8_OR_AM | CONFIG_SYS_OR_TIMING_PER8 )
+#define CONFIG_SYS_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 
-#define CFG_OR_TIMING_SHARC	0x00000700	/* SHARC-Timing */
-#define CFG_OR5 (SHARC_OR_AM | CFG_OR_TIMING_SHARC )
-#define CFG_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR_TIMING_SHARC	0x00000700	/* SHARC-Timing */
+#define CONFIG_SYS_OR5 (SHARC_OR_AM | CONFIG_SYS_OR_TIMING_SHARC )
+#define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
 /*
  * Memory Periodic Timer Prescaler
  */
 
 /* periodic timer for refresh */
-#define CFG_MBMR_PTB	204
+#define CONFIG_SYS_MBMR_PTB	204
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MBMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+#define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 
diff --git a/include/configs/SX1.h b/include/configs/SX1.h
index ff4e1a0..78c5152 100644
--- a/include/configs/SX1.h
+++ b/include/configs/SX1.h
@@ -46,8 +46,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -56,11 +56,11 @@
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	(-4)
-#define CFG_NS16550_CLK		(CONFIG_SYS_CLK_FREQ)	/* can be 12M/32Khz or 48Mhz  */
-#define CFG_NS16550_COM1	0xfffb0000		/* uart1, bluetooth uart on helen */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		(CONFIG_SYS_CLK_FREQ)	/* can be 12M/32Khz or 48Mhz  */
+#define CONFIG_SYS_NS16550_COM1	0xfffb0000		/* uart1, bluetooth uart on helen */
 
 /*
  * select serial console configuration
@@ -82,8 +82,8 @@
  * I2C configuration
  */
 #define CONFIG_HARD_I2C
-#define CFG_I2C_SPEED		100000
-#define CFG_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
 #define CONFIG_DRIVER_OMAP1510_I2C
 
 #define CONFIG_ENV_OVERWRITE
@@ -91,7 +91,7 @@
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 
 /*
@@ -116,31 +116,33 @@
 #include <configs/omap1510.h>
 
 #define CONFIG_BOOTARGS		"mem=16M console=ttyS0,115200n8 root=/dev/mtdblock3 rw"
+#ifdef CONFIG_STDOUT_USBTTY
 #define CONFIG_PREBOOT		"setenv stdout usbtty;setenv stdin usbtty"
+#endif
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"SX1# " /* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"SX1# " /* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x10000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x12000000	/* 32 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x10000000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x12000000	/* 32 MB in DRAM	*/
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR		0x10000000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x10000000	/* default load address */
 
 /* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
  * This time is further subdivided by a local divisor.
  */
-#define CFG_TIMERBASE	0xFFFEC500	    /* use timer 1 */
-#define CFG_PVT		7		    /* 2^(pvt+1), divide by 256 */
-#define CFG_HZ			((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+#define CONFIG_SYS_TIMERBASE	0xFFFEC500	    /* use timer 1 */
+#define CONFIG_SYS_PVT		7		    /* 2^(pvt+1), divide by 256 */
+#define CONFIG_SYS_HZ			((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -163,36 +165,40 @@
 #define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
 #define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
+ * V1
+ * PHYS_FLASH_SIZE_1			(16 << 10)	16 MB
+ * PHYS_FLASH_SIZE_2			(8 << 10)	 8 MB
+ * V2 only 1 flash
+ * PHYS_FLASH_SIZE_1			(32 << 10)	32 MB
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define PHYS_FLASH_SIZE		(16 << 10) /* 16 MB */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
 #define PHYS_FLASH_SECT_SIZE	(128*1024) /* Size of a sector (128kB) */
-#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + PHYS_FLASH_SECT_SIZE) /* addr of environment */
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE	/* Monitor at beginning of flash */
-#define CFG_MONITOR_LEN		PHYS_FLASH_SECT_SIZE	/* Reserve 1 sector */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE }
+#define CONFIG_SYS_MAX_FLASH_SECT	(256)	/* max number of sectors on one chip */
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SECT_SIZE) /* addr of environment */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE	/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_LEN		PHYS_FLASH_SECT_SIZE	/* Reserve 1 sector */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, PHYS_FLASH_2 }
 
 /*-----------------------------------------------------------------------
  * FLASH driver setup
  */
-#define CFG_FLASH_CFI		1	/* Flash memory is CFI compliant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash memory is CFI compliant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use drivers/mtd/cfi_flash.c */
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
-#define CFG_FLASH_PROTECTION	1	/* Use hardware sector protection */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use hardware sector protection */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE
 #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE /* Total Size of Environment Sector */
-#define CONFIG_ENV_OFFSET	( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */
+#define CONFIG_ENV_OFFSET	( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */
 
 /* Address and size of Redundant Environment Sector	*/
 #define CONFIG_ENV_SIZE_REDUND	0x20000
diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h
index 0cc4fe4..9857bf6 100644
--- a/include/configs/SXNI855T.h
+++ b/include/configs/SXNI855T.h
@@ -94,7 +94,7 @@
 # define STATUS_LED_DAT		im_ioport.iop_padat
 
 # define STATUS_LED_BIT		0x8000		/* LED 0 is on PA.0 */
-# define STATUS_LED_PERIOD	((CFG_HZ / 2) / 5)	/* blink at 5 Hz */
+# define STATUS_LED_PERIOD	((CONFIG_SYS_HZ / 2) / 5)	/* blink at 5 Hz */
 # define STATUS_LED_STATE	STATUS_LED_BLINKING
 
 # define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
@@ -136,15 +136,15 @@
 			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
 
-# define CFG_I2C_SPEED		50000
-# define CFG_I2C_SLAVE		0xFE
-# define CFG_I2C_EEPROM_ADDR	0x50	/* Atmel 24C64			*/
-# define CFG_I2C_EEPROM_ADDR_LEN 2	/* two byte address		*/
+# define CONFIG_SYS_I2C_SPEED		50000
+# define CONFIG_SYS_I2C_SLAVE		0xFE
+# define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Atmel 24C64			*/
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2	/* two byte address		*/
 
 #define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
 #define	CONFIG_MII		1
 
-#define CFG_DISCOVER_PHY
+#define CONFIG_SYS_DISCOVER_PHY
 
 
 /*
@@ -167,7 +167,7 @@
 #define CONFIG_CMD_DATE
 
 
-#define CFG_JFFS2_SORT_FRAGMENTS
+#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
 
 /*
  * JFFS2 partitions
@@ -197,7 +197,7 @@
 /* NAND flash support */
 #define CONFIG_NAND_LEGACY
 #define CONFIG_MTD_NAND_ECC_JFFS2
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices	*/
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices	*/
 #define SECTORSIZE 512
 
 #define ADDR_COLUMN 1
@@ -206,11 +206,10 @@
 
 #define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
 
 /* DFBUSY is available on Port C, bit 12; 0 if busy */
 #define NAND_WAIT_READY(nand)	\
-	while (!(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x0008));
+	while (!(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & 0x0008));
 #define WRITE_NAND_COMMAND(d, adr) WRITE_NAND((d), (adr))
 #define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND((d), (adr))
 #define WRITE_NAND(d, adr)	\
@@ -236,25 +235,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save a little memory */
-#define	CFG_PROMPT		"=>"	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save a little memory */
+#define	CONFIG_SYS_PROMPT		"=>"	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x00100000
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -264,65 +263,65 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFF000000
-#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+#define CONFIG_SYS_IMMR		0xFF000000
+#define CONFIG_SYS_IMMR_SIZE		((uint)(64 * 1024))
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define	CFG_SRAM_BASE		0xF4000000
-#define	CFG_SRAM_SIZE		0x04000000	/* autosize up to 64Mbyte */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define	CONFIG_SYS_SRAM_BASE		0xF4000000
+#define	CONFIG_SYS_SRAM_SIZE		0x04000000	/* autosize up to 64Mbyte */
 
-#define CFG_FLASH_BASE		0xF8000000
-#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+#define CONFIG_SYS_FLASH_BASE		0xF8000000
+#define CONFIG_SYS_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
 
-#define CFG_DFLASH_BASE		0xff020000 /* DiskOnChip or NAND FLASH */
-#define CFG_DFLASH_SIZE		0x00010000
+#define CONFIG_SYS_DFLASH_BASE		0xff020000 /* DiskOnChip or NAND FLASH */
+#define CONFIG_SYS_DFLASH_SIZE		0x00010000
 
-#define CFG_FPGA_BASE		0xFF100000	/* Xilinx FPGA */
-#define CFG_FPGA_PROG		0xFF130000	/* Programming address */
-#define CFG_FPGA_SIZE		0x00040000	/* 256KiB usable */
+#define CONFIG_SYS_FPGA_BASE		0xFF100000	/* Xilinx FPGA */
+#define CONFIG_SYS_FPGA_PROG		0xFF130000	/* Programming address */
+#define CONFIG_SYS_FPGA_SIZE		0x00040000	/* 256KiB usable */
 
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
 /* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks.
  * AMD 29LV641 has 128 64K sectors in 8MB
  */
-#define CFG_MAX_FLASH_SECT	135	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	135	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -332,10 +331,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -343,28 +342,28 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control					11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
  *-----------------------------------------------------------------------
  * set the PLL, the low-power modes and the reset control (15-29)
  */
-#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
 				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
@@ -374,14 +373,14 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
+#define CONFIG_SYS_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
 
  /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER		0
+#define CONFIG_SYS_DER		0
 
 /* Because of the way the 860 starts up and assigns CS0 the
  * entire address space, we have to set the memory controller
@@ -398,47 +397,47 @@
  * BR0 and OR0 (FLASH)
  */
 
-#define CFG_PRELIM_OR0_AM	0xFC000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR0_AM	0xFC000000	/* OR addr mask */
 
 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR0_AM | CFG_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR0_AM | CONFIG_SYS_OR_TIMING_FLASH)
 
 #define CONFIG_FLASH_16BIT
-#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
-#define CFG_FLASH_PROTECTION	/* need to lock/unlock sectors in hardware */
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_FLASH_PROTECTION	/* need to lock/unlock sectors in hardware */
 
 /**********************************************************
  * BR1 and OR1 (FPGA)
  * These preliminary values are also the final values.
  */
-#define CFG_OR_TIMING_FPGA \
+#define CONFIG_SYS_OR_TIMING_FPGA \
 	(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX)
-#define CFG_BR1_PRELIM	((CFG_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-#define CFG_OR1_PRELIM	(((-CFG_FPGA_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_FPGA)
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR1_PRELIM	(((-CONFIG_SYS_FPGA_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_FPGA)
 
 /**********************************************************
  * BR4 and OR4 (data flash)
  * These preliminary values are also the final values.
  */
-#define CFG_OR_TIMING_DFLASH \
+#define CONFIG_SYS_OR_TIMING_DFLASH \
 	(OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX)
-#define CFG_BR4_PRELIM	((CFG_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-#define CFG_OR4_PRELIM	(((-CFG_DFLASH_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_DFLASH)
+#define CONFIG_SYS_BR4_PRELIM	((CONFIG_SYS_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR4_PRELIM	(((-CONFIG_SYS_DFLASH_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_DFLASH)
 
 /**********************************************************
  * BR5/6 and OR5/6 (Dual UART)
  */
-#define CFG_DUART_SIZE	0x8000	/* 32K window, only uses 8 bytes */
-#define CFG_DUARTA_BASE	0xff010000
-#define CFG_DUARTB_BASE	0xff018000
+#define CONFIG_SYS_DUART_SIZE	0x8000	/* 32K window, only uses 8 bytes */
+#define CONFIG_SYS_DUARTA_BASE	0xff010000
+#define CONFIG_SYS_DUARTB_BASE	0xff018000
 
 #define DUART_MBMR	0
-#define DUART_OR_VALUE (ORMASK(CFG_DUART_SIZE) | OR_G5LS| OR_BI)
+#define DUART_OR_VALUE (ORMASK(CONFIG_SYS_DUART_SIZE) | OR_G5LS| OR_BI)
 #define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V)
-#define DUART_BR5_VALUE ((CFG_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
-#define DUART_BR6_VALUE ((CFG_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
+#define DUART_BR5_VALUE ((CONFIG_SYS_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
+#define DUART_BR6_VALUE ((CONFIG_SYS_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
 
 /**********************************************************
  *
diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h
index 9898a8b..125b9a2 100644
--- a/include/configs/Sandpoint8240.h
+++ b/include/configs/Sandpoint8240.h
@@ -110,14 +110,14 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		1		/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -129,7 +129,7 @@
 #define CONFIG_NET_MULTI			/* Multi ethernet cards support */
 
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
 
 #define PCI_ENET0_IOADDR	0x80000000
 #define PCI_ENET0_MEMADDR	0x80000000
@@ -140,58 +140,58 @@
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	0x10000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000
 
-#define CFG_RESET_ADDRESS	0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
 
 #if defined (USE_DINK32)
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	0x00090000
-#define CFG_RAMBOOT		1
-#define CFG_INIT_RAM_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_INIT_RAM_END	0x10000
-#define CFG_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_LEN		0x00030000
+#define CONFIG_SYS_MONITOR_BASE	0x00090000
+#define CONFIG_SYS_RAMBOOT		1
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_INIT_RAM_END	0x10000
+#define CONFIG_SYS_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #else
-#undef	CFG_RAMBOOT
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	TEXT_BASE
+#undef	CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_MONITOR_LEN		0x00030000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 
-/*#define CFG_GBL_DATA_SIZE    256*/
-#define CFG_GBL_DATA_SIZE	128
+/*#define CONFIG_SYS_GBL_DATA_SIZE    256*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128
 
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_END      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 #endif
 
-#define CFG_FLASH_BASE		0xFFF00000
+#define CONFIG_SYS_FLASH_BASE		0xFFF00000
 #if 0
-#define CFG_FLASH_SIZE		(512 * 1024)	/* sandpoint has tiny eeprom	*/
+#define CONFIG_SYS_FLASH_SIZE		(512 * 1024)	/* sandpoint has tiny eeprom	*/
 #else
-#define CFG_FLASH_SIZE		(1024 * 1024)	/* Unity has onboard 1MByte flash */
+#define CONFIG_SYS_FLASH_SIZE		(1024 * 1024)	/* Unity has onboard 1MByte flash */
 #endif
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
 #define CONFIG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
 
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
 
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
 
-#define CFG_EUMB_ADDR		0xFC000000
+#define CONFIG_SYS_EUMB_ADDR		0xFC000000
 
-#define CFG_ISA_MEM		0xFD000000
-#define CFG_ISA_IO		0xFE000000
+#define CONFIG_SYS_ISA_MEM		0xFD000000
+#define CONFIG_SYS_ISA_IO		0xFE000000
 
-#define CFG_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
-#define CFG_FLASH_RANGE_SIZE	0x01000000
+#define CONFIG_SYS_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
+#define CONFIG_SYS_FLASH_RANGE_SIZE	0x01000000
 #define FLASH_BASE0_PRELIM	0xFFF00000	/* sandpoint flash		*/
 #define FLASH_BASE1_PRELIM	0xFF000000	/* PMC onboard flash		*/
 
@@ -204,8 +204,8 @@
  */
 #define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
 #undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 #ifdef CONFIG_SOFT_I2C
 #error "Soft I2C is not configured properly.  Please review!"
@@ -221,14 +221,14 @@
 #endif /* CONFIG_SOFT_I2C */
 
 
-#define CFG_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	3	/* write page size		*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3	/* write page size		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec		*/
 
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
@@ -236,46 +236,46 @@
 
 
 #define CONFIG_WINBOND_83C553	1	/*has a winbond bridge			*/
-#define CFG_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
-#define CFG_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
-#define CFG_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/
+#define CONFIG_SYS_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
+#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
+#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/
 
-#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 
 /*
  * NS87308 Configuration
  */
 #define CONFIG_NS87308			/* Nat Semi super-io controller on ISA bus */
 
-#define CFG_NS87308_BADDR_10	1
+#define CONFIG_SYS_NS87308_BADDR_10	1
 
-#define CFG_NS87308_DEVS	( CFG_NS87308_UART1   | \
-				  CFG_NS87308_UART2   | \
-				  CFG_NS87308_POWRMAN | \
-				  CFG_NS87308_RTC_APC )
+#define CONFIG_SYS_NS87308_DEVS	( CONFIG_SYS_NS87308_UART1   | \
+				  CONFIG_SYS_NS87308_UART2   | \
+				  CONFIG_SYS_NS87308_POWRMAN | \
+				  CONFIG_SYS_NS87308_RTC_APC )
 
-#undef  CFG_NS87308_PS2MOD
+#undef  CONFIG_SYS_NS87308_PS2MOD
 
-#define CFG_NS87308_CS0_BASE	0x0076
-#define CFG_NS87308_CS0_CONF	0x30
-#define CFG_NS87308_CS1_BASE	0x0075
-#define CFG_NS87308_CS1_CONF	0x30
-#define CFG_NS87308_CS2_BASE	0x0074
-#define CFG_NS87308_CS2_CONF	0x30
+#define CONFIG_SYS_NS87308_CS0_BASE	0x0076
+#define CONFIG_SYS_NS87308_CS0_CONF	0x30
+#define CONFIG_SYS_NS87308_CS1_BASE	0x0075
+#define CONFIG_SYS_NS87308_CS1_CONF	0x30
+#define CONFIG_SYS_NS87308_CS2_BASE	0x0074
+#define CONFIG_SYS_NS87308_CS2_CONF	0x30
 
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
 
-#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_REG_SIZE	1
 
-#define CFG_NS16550_CLK		1843200
+#define CONFIG_SYS_NS16550_CLK		1843200
 
-#define CFG_NS16550_COM1	(CFG_ISA_IO + CFG_NS87308_UART1_BASE)
-#define CFG_NS16550_COM2	(CFG_ISA_IO + CFG_NS87308_UART2_BASE)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
 
 /*
  * Low Level Configuration Settings
@@ -286,23 +286,23 @@
 #define CONFIG_SYS_CLK_FREQ  33000000	/* external frequency to pll */
 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  1
 
-#define CFG_ROMNAL		7	/*rom/flash next access time		*/
-#define CFG_ROMFAL		11	/*rom/flash access time			*/
+#define CONFIG_SYS_ROMNAL		7	/*rom/flash next access time		*/
+#define CONFIG_SYS_ROMFAL		11	/*rom/flash access time			*/
 
-#define CFG_REFINT	430	/* no of clock cycles between CBR refresh cycles */
+#define CONFIG_SYS_REFINT	430	/* no of clock cycles between CBR refresh cycles */
 
 /* the following are for SDRAM only*/
-#define CFG_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
-#define CFG_REFREC		8	/* Refresh to activate interval		*/
-#define CFG_RDLAT		4	/* data latency from read command	*/
-#define CFG_PRETOACT		3	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
-#define CFG_ACTORW		3	/* Activate to R/W			*/
-#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
-#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
-#define CFG_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
-
-#define CFG_REGISTERD_TYPE_BUFFER   1
+#define CONFIG_SYS_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
+#define CONFIG_SYS_REFREC		8	/* Refresh to activate interval		*/
+#define CONFIG_SYS_RDLAT		4	/* data latency from read command	*/
+#define CONFIG_SYS_PRETOACT		3	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
+
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
 
 /* memory bank settings*/
 /*
@@ -311,93 +311,93 @@
  * bits will be set to 0x00000 for a start address, or 0xfffff for an
  * end address
  */
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x3ff00000
-#define CFG_BANK1_END		0x3fffffff
-#define CFG_BANK1_ENABLE	0
-#define CFG_BANK2_START		0x3ff00000
-#define CFG_BANK2_END		0x3fffffff
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x3ff00000
-#define CFG_BANK3_END		0x3fffffff
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x00000000
-#define CFG_BANK4_END		0x00000000
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x00000000
-#define CFG_BANK5_END		0x00000000
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x00000000
-#define CFG_BANK6_END		0x00000000
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x00000000
-#define CFG_BANK7_END		0x00000000
-#define CFG_BANK7_ENABLE	0
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x3ff00000
+#define CONFIG_SYS_BANK1_END		0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE	0
+#define CONFIG_SYS_BANK2_START		0x3ff00000
+#define CONFIG_SYS_BANK2_END		0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x3ff00000
+#define CONFIG_SYS_BANK3_END		0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x00000000
+#define CONFIG_SYS_BANK4_END		0x00000000
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x00000000
+#define CONFIG_SYS_BANK5_END		0x00000000
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x00000000
+#define CONFIG_SYS_BANK6_END		0x00000000
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x00000000
+#define CONFIG_SYS_BANK7_END		0x00000000
+#define CONFIG_SYS_BANK7_ENABLE	0
 /*
  * Memory bank enable bitmask, specifying which of the banks defined above
  are actually present. MSB is for bank #7, LSB is for bank #0.
  */
-#define CFG_BANK_ENABLE		0x01
+#define CONFIG_SYS_BANK_ENABLE		0x01
 
-#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
+#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
 					/* see 8240 book for bit definitions	*/
-#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
 					/* currently accessed page in memory	*/
 					/* see 8240 book for details		*/
 
 /* SDRAM 0 - 256MB */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* stack in DCACHE @ 1GB (no backing mem) */
 #if defined(USE_DINK32)
-#define CFG_IBAT1L	(0x40000000 | BATL_PP_00 )
-#define CFG_IBAT1U	(0x40000000 | BATU_BL_128K )
+#define CONFIG_SYS_IBAT1L	(0x40000000 | BATL_PP_00 )
+#define CONFIG_SYS_IBAT1U	(0x40000000 | BATU_BL_128K )
 #else
-#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 #endif
 
 /* PCI memory */
-#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* Flash, config addrs, etc */
-#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 
diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h
index 41835f0..8cb920e 100644
--- a/include/configs/Sandpoint8245.h
+++ b/include/configs/Sandpoint8245.h
@@ -78,14 +78,14 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		1		/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -97,7 +97,7 @@
 #define CONFIG_NET_MULTI			/* Multi ethernet cards support */
 
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
 #define CONFIG_NATSEMI
 #define CONFIG_NS8382X
 
@@ -110,58 +110,58 @@
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	0x10000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000
 
-#define CFG_RESET_ADDRESS	0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
 
 #if defined (USE_DINK32)
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	0x00090000
-#define CFG_RAMBOOT		1
-#define CFG_INIT_RAM_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_INIT_RAM_END	0x10000
-#define CFG_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_LEN		0x00030000
+#define CONFIG_SYS_MONITOR_BASE	0x00090000
+#define CONFIG_SYS_RAMBOOT		1
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_INIT_RAM_END	0x10000
+#define CONFIG_SYS_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #else
-#undef	CFG_RAMBOOT
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	TEXT_BASE
+#undef	CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_MONITOR_LEN		0x00030000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 
-/*#define CFG_GBL_DATA_SIZE    256*/
-#define CFG_GBL_DATA_SIZE	128
+/*#define CONFIG_SYS_GBL_DATA_SIZE    256*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128
 
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_END      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 #endif
 
-#define CFG_FLASH_BASE		0xFFF00000
+#define CONFIG_SYS_FLASH_BASE		0xFFF00000
 #if 0
-#define CFG_FLASH_SIZE		(512 * 1024)	/* sandpoint has tiny eeprom	*/
+#define CONFIG_SYS_FLASH_SIZE		(512 * 1024)	/* sandpoint has tiny eeprom	*/
 #else
-#define CFG_FLASH_SIZE		(1024 * 1024)	/* Unity has onboard 1MByte flash */
+#define CONFIG_SYS_FLASH_SIZE		(1024 * 1024)	/* Unity has onboard 1MByte flash */
 #endif
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
 #define CONFIG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
 
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
 
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
 
-#define CFG_EUMB_ADDR		0xFC000000
+#define CONFIG_SYS_EUMB_ADDR		0xFC000000
 
-#define CFG_ISA_MEM		0xFD000000
-#define CFG_ISA_IO		0xFE000000
+#define CONFIG_SYS_ISA_MEM		0xFD000000
+#define CONFIG_SYS_ISA_IO		0xFE000000
 
-#define CFG_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
-#define CFG_FLASH_RANGE_SIZE	0x01000000
+#define CONFIG_SYS_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
+#define CONFIG_SYS_FLASH_RANGE_SIZE	0x01000000
 #define FLASH_BASE0_PRELIM	0xFFF00000	/* sandpoint flash		*/
 #define FLASH_BASE1_PRELIM	0xFF000000	/* PMC onboard flash		*/
 
@@ -174,8 +174,8 @@
  */
 #define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
 #undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 #ifdef CONFIG_SOFT_I2C
 #error "Soft I2C is not configured properly.  Please review!"
@@ -190,13 +190,13 @@
 #define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
 #endif /* CONFIG_SOFT_I2C */
 
-#define CFG_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
@@ -204,52 +204,52 @@
 
 
 #define CONFIG_WINBOND_83C553	1	/*has a winbond bridge			*/
-#define CFG_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
-#define CFG_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
-#define CFG_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/
+#define CONFIG_SYS_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
+#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
+#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/
 
-#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 
 /*
  * NS87308 Configuration
  */
 #define CONFIG_NS87308			/* Nat Semi super-io controller on ISA bus */
 
-#define CFG_NS87308_BADDR_10	1
+#define CONFIG_SYS_NS87308_BADDR_10	1
 
-#define CFG_NS87308_DEVS	( CFG_NS87308_UART1   | \
-				  CFG_NS87308_UART2   | \
-				  CFG_NS87308_POWRMAN | \
-				  CFG_NS87308_RTC_APC )
+#define CONFIG_SYS_NS87308_DEVS	( CONFIG_SYS_NS87308_UART1   | \
+				  CONFIG_SYS_NS87308_UART2   | \
+				  CONFIG_SYS_NS87308_POWRMAN | \
+				  CONFIG_SYS_NS87308_RTC_APC )
 
-#undef  CFG_NS87308_PS2MOD
+#undef  CONFIG_SYS_NS87308_PS2MOD
 
-#define CFG_NS87308_CS0_BASE	0x0076
-#define CFG_NS87308_CS0_CONF	0x30
-#define CFG_NS87308_CS1_BASE	0x0075
-#define CFG_NS87308_CS1_CONF	0x30
-#define CFG_NS87308_CS2_BASE	0x0074
-#define CFG_NS87308_CS2_CONF	0x30
+#define CONFIG_SYS_NS87308_CS0_BASE	0x0076
+#define CONFIG_SYS_NS87308_CS0_CONF	0x30
+#define CONFIG_SYS_NS87308_CS1_BASE	0x0075
+#define CONFIG_SYS_NS87308_CS1_CONF	0x30
+#define CONFIG_SYS_NS87308_CS2_BASE	0x0074
+#define CONFIG_SYS_NS87308_CS2_CONF	0x30
 
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
 
-#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_REG_SIZE	1
 
 #if (CONFIG_CONS_INDEX > 2)
-#define CFG_NS16550_CLK         CONFIG_DRAM_SPEED*1000000
+#define CONFIG_SYS_NS16550_CLK         CONFIG_DRAM_SPEED*1000000
 #else
-#define CFG_NS16550_CLK         1843200
+#define CONFIG_SYS_NS16550_CLK         1843200
 #endif
 
-#define CFG_NS16550_COM1	(CFG_ISA_IO + CFG_NS87308_UART1_BASE)
-#define CFG_NS16550_COM2	(CFG_ISA_IO + CFG_NS87308_UART2_BASE)
-#define CFG_NS16550_COM3	(CFG_EUMB_ADDR + 0x4500)
-#define CFG_NS16550_COM4	(CFG_EUMB_ADDR + 0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_EUMB_ADDR + 0x4500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_EUMB_ADDR + 0x4600)
 
 /*
  * Low Level Configuration Settings
@@ -259,27 +259,27 @@
 
 #define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
 
-#define CFG_ROMNAL		7	/*rom/flash next access time		*/
-#define CFG_ROMFAL		11	/*rom/flash access time			*/
+#define CONFIG_SYS_ROMNAL		7	/*rom/flash next access time		*/
+#define CONFIG_SYS_ROMFAL		11	/*rom/flash access time			*/
 
-#define CFG_REFINT	430	/* no of clock cycles between CBR refresh cycles */
+#define CONFIG_SYS_REFINT	430	/* no of clock cycles between CBR refresh cycles */
 
 /* the following are for SDRAM only*/
-#define CFG_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
-#define CFG_REFREC		8	/* Refresh to activate interval		*/
-#define CFG_RDLAT		4	/* data latency from read command	*/
-#define CFG_PRETOACT		3	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
-#define CFG_ACTORW		3	/* Activate to R/W			*/
-#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
-#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#define CONFIG_SYS_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
+#define CONFIG_SYS_REFREC		8	/* Refresh to activate interval		*/
+#define CONFIG_SYS_RDLAT		4	/* data latency from read command	*/
+#define CONFIG_SYS_PRETOACT		3	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
 #if 0
-#define CFG_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
+#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
 #endif
 
-#define CFG_REGISTERD_TYPE_BUFFER   1
-#define CFG_EXTROM 1
-#define CFG_REGDIMM 0
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
+#define CONFIG_SYS_EXTROM 1
+#define CONFIG_SYS_REGDIMM 0
 
 
 /* memory bank settings*/
@@ -289,93 +289,93 @@
  * bits will be set to 0x00000 for a start address, or 0xfffff for an
  * end address
  */
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x3ff00000
-#define CFG_BANK1_END		0x3fffffff
-#define CFG_BANK1_ENABLE	0
-#define CFG_BANK2_START		0x3ff00000
-#define CFG_BANK2_END		0x3fffffff
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x3ff00000
-#define CFG_BANK3_END		0x3fffffff
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x00000000
-#define CFG_BANK4_END		0x00000000
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x00000000
-#define CFG_BANK5_END		0x00000000
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x00000000
-#define CFG_BANK6_END		0x00000000
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x00000000
-#define CFG_BANK7_END		0x00000000
-#define CFG_BANK7_ENABLE	0
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x3ff00000
+#define CONFIG_SYS_BANK1_END		0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE	0
+#define CONFIG_SYS_BANK2_START		0x3ff00000
+#define CONFIG_SYS_BANK2_END		0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x3ff00000
+#define CONFIG_SYS_BANK3_END		0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x00000000
+#define CONFIG_SYS_BANK4_END		0x00000000
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x00000000
+#define CONFIG_SYS_BANK5_END		0x00000000
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x00000000
+#define CONFIG_SYS_BANK6_END		0x00000000
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x00000000
+#define CONFIG_SYS_BANK7_END		0x00000000
+#define CONFIG_SYS_BANK7_ENABLE	0
 /*
  * Memory bank enable bitmask, specifying which of the banks defined above
  are actually present. MSB is for bank #7, LSB is for bank #0.
  */
-#define CFG_BANK_ENABLE		0x01
+#define CONFIG_SYS_BANK_ENABLE		0x01
 
-#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
+#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
 					/* see 8240 book for bit definitions	*/
-#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
 					/* currently accessed page in memory	*/
 					/* see 8240 book for details		*/
 
 /* SDRAM 0 - 256MB */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* stack in DCACHE @ 1GB (no backing mem) */
 #if defined(USE_DINK32)
-#define CFG_IBAT1L	(0x40000000 | BATL_PP_00 )
-#define CFG_IBAT1U	(0x40000000 | BATU_BL_128K )
+#define CONFIG_SYS_IBAT1L	(0x40000000 | BATL_PP_00 )
+#define CONFIG_SYS_IBAT1U	(0x40000000 | BATU_BL_128K )
 #else
-#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 #endif
 
 /* PCI memory */
-#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* Flash, config addrs, etc */
-#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h
index dd074dc..25f3a26 100644
--- a/include/configs/TASREG.h
+++ b/include/configs/TASREG.h
@@ -46,9 +46,9 @@
 #define CONFIG_MCFTMR
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		19200
-#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef  CONFIG_WATCHDOG
 
@@ -78,51 +78,51 @@
 
 #define CONFIG_BOOTDELAY	3
 
-#define CFG_PROMPT		"=> "
-#define CFG_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 #define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
 #define CONFIG_LOOPW            1       /* enable loopw command         */
 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 
-#define CFG_LOAD_ADDR	        0x200000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR	        0x200000	/* default load address */
 
-#define CFG_MEMTEST_START	0x400
-#define CFG_MEMTEST_END		0x380000
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
 
-#define CFG_HZ			1000
+#define CONFIG_SYS_HZ			1000
 
 /*
  * Clock configuration: enable only one of the following options
  */
 
 #if 0 /* this setting will run the cpu at 11MHz */
-#define CFG_PLL_BYPASS          1                /* bypass PLL for test purpose */
-#undef  CFG_FAST_CLK                             /* MCF5249 can run at 140MHz   */
-#define CFG_CLK		        11289600         /* PLL bypass                  */
+#define CONFIG_SYS_PLL_BYPASS          1                /* bypass PLL for test purpose */
+#undef  CONFIG_SYS_FAST_CLK                             /* MCF5249 can run at 140MHz   */
+#define CONFIG_SYS_CLK		        11289600         /* PLL bypass                  */
 #endif
 
 #if 0 /* this setting will run the cpu at 70MHz */
-#undef  CFG_PLL_BYPASS                           /* bypass PLL for test purpose */
-#undef  CFG_FAST_CLK                             /* MCF5249 can run at 140MHz   */
-#define CFG_CLK		        72185018         /* The next lower speed        */
+#undef  CONFIG_SYS_PLL_BYPASS                           /* bypass PLL for test purpose */
+#undef  CONFIG_SYS_FAST_CLK                             /* MCF5249 can run at 140MHz   */
+#define CONFIG_SYS_CLK		        72185018         /* The next lower speed        */
 #endif
 
 #if 1 /* this setting will run the cpu at 140MHz */
-#undef  CFG_PLL_BYPASS                           /* bypass PLL for test purpose */
-#define CFG_FAST_CLK            1                /* MCF5249 can run at 140MHz   */
-#define	CFG_CLK		        132025600        /* MCF5249 can run at 140MHz   */
+#undef  CONFIG_SYS_PLL_BYPASS                           /* bypass PLL for test purpose */
+#define CONFIG_SYS_FAST_CLK            1                /* MCF5249 can run at 140MHz   */
+#define	CONFIG_SYS_CLK		        132025600        /* MCF5249 can run at 140MHz   */
 #endif
 
 /*
@@ -131,35 +131,34 @@
  * You should know what you are doing if you make changes here.
  */
 
-#define CFG_MBAR		0x10000000	/* Register Base Addrs */
-#define	CFG_MBAR2	        0x80000000
+#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+#define	CONFIG_SYS_MBAR2	        0x80000000
 
 /*-----------------------------------------------------------------------
  * I2C
  */
 #define	CONFIG_SOFT_I2C
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC32		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC32		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
-#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x01
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
 					/* 32 byte page write mode using*/
 					/* last 5 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 #if defined (CONFIG_SOFT_I2C)
 #if 0 /* push-pull */
 #define	SDA	        0x00800000
 #define	SCL	        0x00000008
-#define DIR0            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN))
-#define DIR1            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN))
-#define OUT0	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT))
-#define OUT1	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT))
-#define IN0	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ))
-#define IN1	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ))
+#define DIR0            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN))
+#define DIR1            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN))
+#define OUT0	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT))
+#define OUT1	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT))
+#define IN0	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ))
+#define IN1	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ))
 #define	I2C_INIT	{OUT1|=SDA;OUT0|=SCL;}
 #define	I2C_READ	((IN1&SDA)?1:0)
 #define	I2C_SDA(x)	{if(x)OUT1|=SDA;else OUT1&=~SDA;}
@@ -170,12 +169,12 @@
 #else /* open-collector */
 #define	SDA	        0x00800000
 #define	SCL	        0x00000008
-#define DIR0            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN))
-#define DIR1            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN))
-#define OUT0	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT))
-#define OUT1	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT))
-#define IN0	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ))
-#define IN1	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ))
+#define DIR0            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN))
+#define DIR1            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN))
+#define OUT0	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT))
+#define OUT1	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT))
+#define IN0	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ))
+#define IN1	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ))
 #define	I2C_INIT	{DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;}
 #define	I2C_READ	((IN1&SDA)?1:0)
 #define	I2C_SDA(x)	{if(x)DIR1&=~SDA;else DIR1|=SDA;}
@@ -189,11 +188,11 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x20000000
-#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
-#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		0xFFC40000	/* Address of Environment Sector*/
@@ -203,94 +202,94 @@
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_SIZE		16		/* SDRAM size in MB */
-#define CFG_FLASH_BASE		0xffc00000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
 
 #if 0 /* test-only */
 #define CONFIG_PRAM             512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
 #endif
 
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
 
-#define CFG_MONITOR_LEN		0x20000
-#define CFG_MALLOC_LEN		(1 * 1024*1024)	/* Reserve 1 MB for malloc()	*/
-#define CFG_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024*1024)	/* Reserve 1 MB for malloc()	*/
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
 
 /* CS0 - AMD Flash, address 0xffc00000 */
-#define	CFG_CSAR0               0xffc0
-#define	CFG_CSCR0               0x1980          /* WS=0110, AA=1, PS=10         */
+#define	CONFIG_SYS_CS0_BASE		0xffc00000
+#define	CONFIG_SYS_CS0_CTRL		0x00001980	/* WS=0110, AA=1, PS=10         */
 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
-#define	CFG_CSMR0               0x003f0021      /* 4MB, AA=0, WP=0, C/I=1, V=1  */
+#define	CONFIG_SYS_CS0_MASK		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
 
 /* CS1 - FPGA, address 0xe0000000 */
-#define	CFG_CSAR1               0xe000
-#define	CFG_CSCR1               0x0d80          /* WS=0011, AA=1, PS=10         */
-#define	CFG_CSMR1               0x00010001      /* 128kB, AA=0, WP=0, C/I=0, V=1*/
+#define	CONFIG_SYS_CS1_BASE		0xe0000000
+#define	CONFIG_SYS_CS1_CTRL		0x00000d80	/* WS=0011, AA=1, PS=10         */
+#define	CONFIG_SYS_CS1_MASK		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
 
 /*-----------------------------------------------------------------------
  * Port configuration
  */
-#define	CFG_GPIO_FUNC           0x00000008      /* Set gpio pins: none          */
-#define	CFG_GPIO1_FUNC          0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54*/
-#define	CFG_GPIO_EN             0x00000008      /* Set gpio output enable       */
-#define	CFG_GPIO1_EN            0x00c70000      /* Set gpio output enable       */
-#define	CFG_GPIO_OUT            0x00000008      /* Set outputs to default state */
-#define	CFG_GPIO1_OUT           0x00c70000      /* Set outputs to default state */
+#define	CONFIG_SYS_GPIO_FUNC           0x00000008      /* Set gpio pins: none          */
+#define	CONFIG_SYS_GPIO1_FUNC          0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54*/
+#define	CONFIG_SYS_GPIO_EN             0x00000008      /* Set gpio output enable       */
+#define	CONFIG_SYS_GPIO1_EN            0x00c70000      /* Set gpio output enable       */
+#define	CONFIG_SYS_GPIO_OUT            0x00000008      /* Set outputs to default state */
+#define	CONFIG_SYS_GPIO1_OUT           0x00c70000      /* Set outputs to default state */
 
-#define CFG_GPIO1_LED           0x00400000      /* user led                     */
+#define CONFIG_SYS_GPIO1_LED           0x00400000      /* user led                     */
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	512*1024    /* 512kByte is enough for XC2S200*/
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE	512*1024    /* 512kByte is enough for XC2S200*/
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x00010000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x00040000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x00020000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00080000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00100000  /* FPGA done pin (ppc input)     */
+#define CONFIG_SYS_FPGA_PRG		0x00010000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x00040000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x00020000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00080000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00100000  /* FPGA done pin (ppc input)     */
 
 #endif	/* _TASREG_H */
diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h
index e4e1367..b42d3d9 100644
--- a/include/configs/TB5200.h
+++ b/include/configs/TB5200.h
@@ -37,7 +37,7 @@
 #define CONFIG_TQM5200		1	/* ... on TQM5200 module */
 #define CONFIG_TB5200		1	/* ... on a TB5200 base board */
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
@@ -51,7 +51,7 @@
 #define CONFIG_SERIAL_MULTI	1	/* support multiple consoles */
 #define CONFIG_PSC_CONSOLE2	6	/* second console is on PSC6 */
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*
  * Video console
@@ -66,7 +66,7 @@
 #define CONFIG_CONSOLE_EXTRA_INFO
 #define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_SPLASH_SCREEN
-#define CFG_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #endif
 
 /* Partitions */
@@ -79,9 +79,9 @@
 #define CONFIG_USB_STORAGE
 
 /* POST support */
-#define CONFIG_POST		(CFG_POST_MEMORY   | \
-				 CFG_POST_CPU	   | \
-				 CFG_POST_I2C)
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_I2C)
 
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
@@ -133,7 +133,7 @@
 #define	CONFIG_TIMESTAMP		/* display image timestamps */
 
 #if (TEXT_BASE == 0xFC000000)		/* Boot low */
-#   define CFG_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT		1
 #endif
 
 /*
@@ -200,24 +200,24 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
-#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
+#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
  * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#define CFG_PCICLK_EQUALS_IPBCLK_DIV2		/* define for 66MHz speed */
+#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2		/* define for 66MHz speed */
 #endif
 
 /*
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		2	/* Select I2C module #2 */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #2 */
 
 /*
  * I2C clock frequency
@@ -225,11 +225,11 @@
  * Please notice, that the resulting clock frequency could differ from the
  * configured value. This is because the I2C clock is derived from system
  * clock over a frequency divider with only a few divider values. U-boot
- * calculates the best approximation for CFG_I2C_SPEED. However the calculated
+ * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
  * approximation allways lies below the configured value, never above.
  */
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
@@ -237,41 +237,41 @@
  * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
  * same configuration could be used.
  */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CFG_I2C_EEPROM_ADDR_LEN		2
-#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
 
 /* List of I2C addresses to be verified by POST */
 #undef I2C_ADDR_LIST
-#define I2C_ADDR_LIST	{	CFG_I2C_EEPROM_ADDR,	\
-				CFG_I2C_RTC_ADDR,	\
-				CFG_I2C_SLAVE }
+#define I2C_ADDR_LIST	{	CONFIG_SYS_I2C_EEPROM_ADDR,	\
+				CONFIG_SYS_I2C_RTC_ADDR,	\
+				CONFIG_SYS_I2C_SLAVE }
 
 /*
  * Flash configuration
  */
-#define CFG_FLASH_BASE		TEXT_BASE /* 0xFC000000 */
+#define CONFIG_SYS_FLASH_BASE		TEXT_BASE /* 0xFC000000 */
 
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
-#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-
-#if !defined(CFG_LOWBOOT)
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00760000 + 0x00800000)
-#else	/* CFG_LOWBOOT */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_BOOTCS_START }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MByte */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+
+#if !defined(CONFIG_SYS_LOWBOOT)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
+#else	/* CONFIG_SYS_LOWBOOT */
 #if defined(CONFIG_TQM5200_B)
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00080000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00080000)
 #else
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
 #endif /* CONFIG_TQM5200_B */
-#endif	/* CFG_LOWBOOT */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+#endif	/* CONFIG_SYS_LOWBOOT */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
 					   (= chip selects) */
 
 /* Dynamic MTD partition support */
@@ -309,45 +309,46 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /* Use ON-Chip SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
 #else
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
 #endif
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
 #if defined(CONFIG_TQM5200_B)
-#define CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
 #else
-#define CFG_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
 #endif /* CONFIG_TQM5200_B */
-#define CFG_MALLOC_LEN		(1024 << 10)	/* Reserve 1024 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)	/* Reserve 1024 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
 /*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
  */
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
 #define CONFIG_PHY_ADDR		0x00
 
 /*
@@ -379,45 +380,45 @@
  *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
  *   tests.
  */
-#define CFG_GPS_PORT_CONFIG	0x81500114
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x81500114
 
 /*
  * RTC configuration
  */
 #define CONFIG_RTC_M41T11	1
-#define CFG_I2C_RTC_ADDR	0x68
-#define CFG_M41T11_BASE_YEAR	1900    /* because Linux uses the same base
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	1900    /* because Linux uses the same base
 					   year */
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /* Enable an alternate, more extensive memory test */
-#define CFG_ALT_MEMTEST
+#define CONFIG_SYS_ALT_MEMTEST
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 /*
  * Enable loopw command.
@@ -428,22 +429,22 @@
  * Various low-level settings
  */
 #if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 #else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
 #endif
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
-#define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
+#define CONFIG_SYS_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
 #else
-#define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
+#define CONFIG_SYS_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
 #endif
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
 #define CONFIG_LAST_STAGE_INIT
 
@@ -451,24 +452,24 @@
  * SRAM - Do not map below 2 GB in address space, because this area is used
  * for SDRAM autosizing.
  */
-#define CFG_CS2_START		0xE5000000
-#define CFG_CS2_SIZE		0x100000	/* 1 MByte */
-#define CFG_CS2_CFG		0x0004D930
+#define CONFIG_SYS_CS2_START		0xE5000000
+#define CONFIG_SYS_CS2_SIZE		0x100000	/* 1 MByte */
+#define CONFIG_SYS_CS2_CFG		0x0004D930
 
 /*
  * Grafic controller - Do not map below 2 GB in address space, because this
  * area is used for SDRAM autosizing.
  */
 #define SM501_FB_BASE		0xE0000000
-#define CFG_CS1_START		(SM501_FB_BASE)
-#define CFG_CS1_SIZE		0x4000000	/* 64 MByte */
-#define CFG_CS1_CFG		0x8F48FF70
-#define SM501_MMIO_BASE		CFG_CS1_START + 0x03E00000
+#define CONFIG_SYS_CS1_START		(SM501_FB_BASE)
+#define CONFIG_SYS_CS1_SIZE		0x4000000	/* 64 MByte */
+#define CONFIG_SYS_CS1_CFG		0x8F48FF70
+#define SM501_MMIO_BASE		CONFIG_SYS_CS1_START + 0x03E00000
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
 
-#define CFG_RESET_ADDRESS	0xff000000
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
 
 /*-----------------------------------------------------------------------
  * USB stuff
@@ -490,23 +491,23 @@
 #define CONFIG_IDE_RESET		/* reset for ide supported	*/
 #define CONFIG_IDE_PREINIT
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(0x0060)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005C)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
 
 /* Interval between registers						     */
-#define CFG_ATA_STRIDE		4
+#define CONFIG_SYS_ATA_STRIDE		4
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/TK885D.h b/include/configs/TK885D.h
index 2efc10a..14ff62c 100644
--- a/include/configs/TK885D.h
+++ b/include/configs/TK885D.h
@@ -41,8 +41,8 @@
 #define CONFIG_TK885D		1	/* ...in a TK885D base board	*/
 
 #define CONFIG_8xx_OSCLK		10000000	/*  10 MHz - PLL input clock	*/
-#define CFG_8xx_CPUCLK_MIN		15000000	/*  15 MHz - CPU minimum clock	*/
-#define CFG_8xx_CPUCLK_MAX		133000000	/* 133 MHz - CPU maximum clock	*/
+#define CONFIG_SYS_8xx_CPUCLK_MIN		15000000	/*  15 MHz - CPU minimum clock	*/
+#define CONFIG_SYS_8xx_CPUCLK_MAX		133000000	/* 133 MHz - CPU maximum clock	*/
 #define CONFIG_8xx_CPUCLK_DEFAULT	66000000	/*  66 MHz - CPU default clock	*/
 						/* (it will be used if there is no	*/
 						/* 'cpuclk' variable with valid value)	*/
@@ -92,7 +92,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -104,8 +104,8 @@
 #undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
 
-#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
-#define CFG_I2C_SLAVE		0xFE
+#define CONFIG_SYS_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CONFIG_SYS_I2C_SLAVE		0xFE
 
 #ifdef CONFIG_SOFT_I2C
 /*
@@ -125,13 +125,13 @@
 #define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
 #endif	/* CONFIG_SOFT_I2C */
 
-#define CFG_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C??	*/
-#define CFG_I2C_EEPROM_ADDR_LEN 2		/* two byte address	*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C??	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2		/* two byte address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
 # define CONFIG_RTC_DS1337 1
-# define CFG_I2C_RTC_ADDR 0x68
+# define CONFIG_SYS_I2C_RTC_ADDR 0x68
 
 /*
  * BOOTP options
@@ -170,34 +170,34 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0300000	/* 1 ... 3 MB in DRAM	*/
-#define CFG_ALT_MEMTEST				/* alternate, more extensive
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0300000	/* 1 ... 3 MB in DRAM	*/
+#define CONFIG_SYS_ALT_MEMTEST				/* alternate, more extensive
 						   memory test.*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Enable loopw command.
@@ -212,47 +212,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
@@ -266,16 +266,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -285,10 +285,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -297,9 +297,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -307,14 +307,14 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -323,7 +323,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 
@@ -332,14 +332,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -352,28 +352,28 @@
 #undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER 0
+#define CONFIG_SYS_DER 0
 
 /*
  * Init Memory Controller:
@@ -388,22 +388,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing: Default value of OR0 after reset
  */
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
 				 OR_SCY_6_CLK | OR_TRLX)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -414,19 +414,19 @@
 #define SDRAM_MAX_SIZE		(256 << 20)	/* max 256 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 #ifndef CONFIG_CAN_DRIVER
-#define CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 #endif	/* CONFIG_CAN_DRIVER */
 
@@ -437,48 +437,48 @@
  * 4	Number of refresh cycles per period
  * 64	Refresh cycle in ms per number of rows
  */
-#define CFG_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))
 
 /*
  * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
  *
  *                        CPUclock(MHz) * 31.2
- * CFG_MAMR_PTA = -----------------------------------     with DFBRG = 0
+ * CONFIG_SYS_MAMR_PTA = -----------------------------------     with DFBRG = 0
  *                2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
  *
- * CPU clock =  15 MHz:  CFG_MAMR_PTA =  29   ->  4 * 7.73 us
- * CPU clock =  50 MHz:  CFG_MAMR_PTA =  97   ->  4 * 7.76 us
- * CPU clock =  66 MHz:  CFG_MAMR_PTA = 128   ->  4 * 7.75 us
- * CPU clock = 133 MHz:  CFG_MAMR_PTA = 255   ->  4 * 7.67 us
+ * CPU clock =  15 MHz:  CONFIG_SYS_MAMR_PTA =  29   ->  4 * 7.73 us
+ * CPU clock =  50 MHz:  CONFIG_SYS_MAMR_PTA =  97   ->  4 * 7.76 us
+ * CPU clock =  66 MHz:  CONFIG_SYS_MAMR_PTA = 128   ->  4 * 7.75 us
+ * CPU clock = 133 MHz:  CONFIG_SYS_MAMR_PTA = 255   ->  4 * 7.67 us
  *
  * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
  * be met also in the default configuration, i.e. if environment variable
  * 'cpuclk' is not set.
  */
-#define CFG_MAMR_PTA		128
+#define CONFIG_SYS_MAMR_PTA		128
 
 /*
  * Memory Periodic Timer Prescaler Register (MPTPR) values.
  */
 /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16
 /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 10 column SDRAM */
-#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_10COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
@@ -499,12 +499,12 @@
 
 #define CONFIG_LAST_STAGE_INIT		1 /* Have to configure PHYs for Linux */
 
-/* CFG_DISCOVER_PHY only works with FEC if only one interface is enabled */
+/* CONFIG_SYS_DISCOVER_PHY only works with FEC if only one interface is enabled */
 #if (!defined(CONFIG_ETHER_ON_FEC1) || !defined(CONFIG_ETHER_ON_FEC2))
-#define CFG_DISCOVER_PHY
+#define CONFIG_SYS_DISCOVER_PHY
 #endif
 
-#ifndef CFG_DISCOVER_PHY
+#ifndef CONFIG_SYS_DISCOVER_PHY
 /* PHY addresses - hard wired in hardware */
 #define CONFIG_FEC1_PHY	1
 #define CONFIG_FEC2_PHY	2
diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h
index 3818368..50197f4 100644
--- a/include/configs/TOP5200.h
+++ b/include/configs/TOP5200.h
@@ -45,7 +45,7 @@
 #define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
 #define CONFIG_TOP5200		1	/* ... on TOP5200 board - we need this for FEC.C */
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
@@ -57,7 +57,7 @@
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
 #define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 
 #if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
@@ -139,8 +139,8 @@
  * MUST be low boot - HIGHBOOT is not supported anymore
  */
 #if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
-#   define CFG_LOWBOOT		1
-#   define CFG_LOWBOOT16	1
+#   define CONFIG_SYS_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT16	1
 #else
 #   error "TEXT_BASE must be 0xff000000"
 #endif
@@ -178,7 +178,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * I2C configuration
@@ -186,11 +186,11 @@
 /*
  * EEPROM configuration
  */
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
 
-#define CFG_I2C_EEPROM_ADDR_LEN 2
-#define CFG_EEPROM_SIZE 0x2000
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_SIZE 0x2000
 
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_MISC_INIT_R
@@ -201,11 +201,11 @@
 #if defined (CONFIG_SOFT_I2C)
 #  define SDA0			0x40
 #  define SCL0			0x80
-#  define GPIOE0		*((volatile uchar*)(CFG_MBAR+0x0c00))
-#  define DDR0			*((volatile uchar*)(CFG_MBAR+0x0c08))
-#  define DVO0			*((volatile uchar*)(CFG_MBAR+0x0c0c))
-#  define DVI0			*((volatile uchar*)(CFG_MBAR+0x0c20))
-#  define ODE0			*((volatile uchar*)(CFG_MBAR+0x0c04))
+#  define GPIOE0		*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c00))
+#  define DDR0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c08))
+#  define DVO0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c0c))
+#  define DVI0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c20))
+#  define ODE0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c04))
 #  define I2C_INIT		{GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
 #  define I2C_READ		((DVI0&SDA0)?1:0)
 #  define I2C_SDA(x)	{if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
@@ -213,32 +213,32 @@
 #  define I2C_DELAY		{udelay(5);}
 #  define I2C_ACTIVE	{DDR0|=SDA0;}
 #  define I2C_TRISTATE	{DDR0&=~SDA0;}
-#  define CFG_I2C_SPEED		100000
-#  define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_EEPROM_ADDR 0x57
-#define CFG_I2C_FACT_ADDR	0x57
+#  define CONFIG_SYS_I2C_SPEED		100000
+#  define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_FACT_ADDR	0x57
 #endif
 
 #if defined (CONFIG_HARD_I2C)
-#  define CFG_I2C_MODULE	2		/* Select I2C module #1 or #2 */
-#  define CFG_I2C_SPEED		100000	/* 100 kHz */
-#  define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_EEPROM_ADDR 0x54
-#define CFG_I2C_FACT_ADDR	0x54
+#  define CONFIG_SYS_I2C_MODULE	2		/* Select I2C module #1 or #2 */
+#  define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
+#  define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
+#define CONFIG_SYS_I2C_FACT_ADDR	0x54
 #endif
 
 /*
  * Flash configuration, expect one 16 Megabyte Bank at most
  */
-#define CFG_FLASH_BASE		0xff000000
-#define CFG_FLASH_SIZE		0x01000000
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0)
+#define CONFIG_SYS_FLASH_BASE		0xff000000
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0)
 
-#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
 
 #undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */
 
@@ -247,25 +247,25 @@
  */
 #if 0
 /* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
-#define	CFG_DRAM_DDR		0
-#define CFG_DRAM_EMODE		0
-#define CFG_DRAM_MODE		0x008D
-#define CFG_DRAM_CONTROL	0x514F0000
-#define CFG_DRAM_CONFIG1	0xC2233A00
-#define CFG_DRAM_CONFIG2	0x88B70004
-#define	CFG_DRAM_TAP_DEL	0x08
-#define CFG_DRAM_RAM_SIZE	0x19
+#define	CONFIG_SYS_DRAM_DDR		0
+#define CONFIG_SYS_DRAM_EMODE		0
+#define CONFIG_SYS_DRAM_MODE		0x008D
+#define CONFIG_SYS_DRAM_CONTROL	0x514F0000
+#define CONFIG_SYS_DRAM_CONFIG1	0xC2233A00
+#define CONFIG_SYS_DRAM_CONFIG2	0x88B70004
+#define	CONFIG_SYS_DRAM_TAP_DEL	0x08
+#define CONFIG_SYS_DRAM_RAM_SIZE	0x19
 #endif
 #if 1
 /* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
-#define	CFG_DRAM_DDR		0
-#define CFG_DRAM_EMODE		0
-#define CFG_DRAM_MODE		0x00CD
-#define CFG_DRAM_CONTROL	0x514F0000
-#define CFG_DRAM_CONFIG1	0xD2333A00
-#define CFG_DRAM_CONFIG2	0x8AD70004
-#define	CFG_DRAM_TAP_DEL	0x08
-#define CFG_DRAM_RAM_SIZE	0x19
+#define	CONFIG_SYS_DRAM_DDR		0
+#define CONFIG_SYS_DRAM_EMODE		0
+#define CONFIG_SYS_DRAM_MODE		0x00CD
+#define CONFIG_SYS_DRAM_CONTROL	0x514F0000
+#define CONFIG_SYS_DRAM_CONFIG1	0xD2333A00
+#define CONFIG_SYS_DRAM_CONFIG2	0x8AD70004
+#define	CONFIG_SYS_DRAM_TAP_DEL	0x08
+#define CONFIG_SYS_DRAM_RAM_SIZE	0x19
 #endif
 
 /*
@@ -278,41 +278,41 @@
 /*
  * VPD settings
  */
-#define CFG_FACT_OFFSET		0x1800
-#define CFG_FACT_SIZE		0x0800
+#define CONFIG_SYS_FACT_OFFSET		0x1800
+#define CONFIG_SYS_FACT_SIZE		0x0800
 
 /*
  * Memory map
  *
  * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
  */
-#define CFG_MBAR			0xf0000000	/* DO NOT CHANGE this */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR			0xf0000000	/* DO NOT CHANGE this */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_FEC_10MBIT	1		/* Workaround for FEC 100Mbit problem */
+#define CONFIG_MPC5xxx_FEC_MII10	/* Workaround for FEC 100Mbit problem */
 #define	CONFIG_PHY_ADDR		0x1f
 #define	CONFIG_PHY_TYPE		0x79c874
 /*
@@ -321,32 +321,32 @@
  * PCI disabled
  * Ethernet 100 with MD
  */
-#define CFG_GPS_PORT_CONFIG	0x00058044
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x00058044
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#  define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#  define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x200000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 
@@ -354,12 +354,12 @@
   #define CONFIG_RTC_MK48T59	1	/* use M48T08 on EVAL5200 */
   #define RTC(reg)		(0xf0010000+reg)
   /* setup CS2 for M48T08. Must MAP 64kB */
-  #define CFG_CS2_START	RTC(0)
-  #define CFG_CS2_SIZE	0x10000
+  #define CONFIG_SYS_CS2_START	RTC(0)
+  #define CONFIG_SYS_CS2_SIZE	0x10000
   /* setup CS2 configuration register: */
   /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
   /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
-  #define CFG_CS2_CFG	0x00047800
+  #define CONFIG_SYS_CS2_CFG	0x00047800
 #else
   #define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
 #endif
@@ -367,19 +367,19 @@
 /*
  * Various low-level settings
  */
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x00047801
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047801
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
 
-#define CFG_RESET_ADDRESS	0x7f000000
+#define CONFIG_SYS_RESET_ADDRESS	0x7f000000
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff Supports IDE harddisk
@@ -394,23 +394,23 @@
 #define CONFIG_IDE_RESET	1
 #define CONFIG_IDE_PREINIT
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(0x0060)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005c)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005c)
 
 /* Interval between registers                                                */
-#define CFG_ATA_STRIDE          4
+#define CONFIG_SYS_ATA_STRIDE          4
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h
index b270832..8c2befb 100644
--- a/include/configs/TOP860.h
+++ b/include/configs/TOP860.h
@@ -60,7 +60,7 @@
  * CLOCK settings
  */
 #define	CONFIG_SYSCLK	49152000
-#define	CFG_XTAL		32768
+#define	CONFIG_SYS_XTAL		32768
 #define	CONFIG_EBDF		1
 #define	CONFIG_COM		3
 #define	CONFIG_RTC_MPC8xx
@@ -68,32 +68,32 @@
 /*-----------------------------------------------------------------------
  * Physical memory map as defined by EMK
  */
-#define CFG_IMMR		0xFFF00000	/* Internal Memory Mapped Register */
-#define	CFG_FLASH_BASE	0x80000000	/* FLASH in final mapping */
-#define	CFG_DRAM_BASE	0x00000000	/* DRAM in final mapping */
-#define	CFG_FLASH_MAX	0x00400000	/* max FLASH to expect */
-#define	CFG_DRAM_MAX	0x01000000	/* max DRAM to expect */
+#define CONFIG_SYS_IMMR		0xFFF00000	/* Internal Memory Mapped Register */
+#define	CONFIG_SYS_FLASH_BASE	0x80000000	/* FLASH in final mapping */
+#define	CONFIG_SYS_DRAM_BASE	0x00000000	/* DRAM in final mapping */
+#define	CONFIG_SYS_FLASH_MAX	0x00400000	/* max FLASH to expect */
+#define	CONFIG_SYS_DRAM_MAX	0x01000000	/* max DRAM to expect */
 
 /*-----------------------------------------------------------------------
  * derived values
  */
-#define	CFG_MF			(CONFIG_SYSCLK/CFG_XTAL)
-#define	CFG_CPUCLOCK	CONFIG_SYSCLK
-#define	CFG_BRGCLOCK	CONFIG_SYSCLK
-#define	CFG_BUSCLOCK	(CONFIG_SYSCLK >> CONFIG_EBDF)
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define	CONFIG_SYS_MF			(CONFIG_SYSCLK/CONFIG_SYS_XTAL)
+#define	CONFIG_SYS_CPUCLOCK	CONFIG_SYSCLK
+#define	CONFIG_SYS_BRGCLOCK	CONFIG_SYSCLK
+#define	CONFIG_SYS_BUSCLOCK	(CONFIG_SYSCLK >> CONFIG_EBDF)
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 #define	CONFIG_8xx_GCLK_FREQ	CONFIG_SYSCLK
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define	CFG_FLASH_CFI
+#define	CONFIG_SYS_FLASH_CFI
 
 /*-----------------------------------------------------------------------
  * Command interpreter
@@ -105,7 +105,7 @@
 /*
  * Allow partial commands to be matched to uniqueness.
  */
-#define CFG_MATCH_PARTIAL_CMD
+#define CONFIG_SYS_MATCH_PARTIAL_CMD
 
 
 /*
@@ -126,34 +126,34 @@
 
 
 #define	CONFIG_AUTOSCRIPT		1
-#define	CFG_LOADS_BAUD_CHANGE	1
+#define	CONFIG_SYS_LOADS_BAUD_CHANGE	1
 #undef	CONFIG_LOADS_ECHO			/* NO echo on for serial download	*/
 
 
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#undef	CFG_HUSH_PARSER			/* Hush parse for U-Boot	*/
+#undef	CONFIG_SYS_HUSH_PARSER			/* Hush parse for U-Boot	*/
 
-#ifdef	CFG_HUSH_PARSER
- #define CFG_PROMPT_HUSH_PS2	"> "
+#ifdef	CONFIG_SYS_HUSH_PARSER
+ #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
- #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+ #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
- #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+ #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
 /*-----------------------------------------------------------------------
  * Memory Test Command
  */
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
 /*-----------------------------------------------------------------------
  * Environment handler
@@ -163,16 +163,16 @@
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* turn on EEPROM env feature */
 #define CONFIG_ENV_OFFSET		0x1000
 #define CONFIG_ENV_SIZE		0x0700
-#define CFG_I2C_EEPROM_ADDR 0x57
-#define CFG_FACT_OFFSET		0x1800
-#define CFG_FACT_SIZE		0x0800
-#define CFG_I2C_FACT_ADDR	0x57
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_I2C_EEPROM_ADDR_LEN 2
-#define CFG_EEPROM_SIZE 0x2000
-#define	CFG_I2C_SPEED	100000
-#define	CFG_I2C_SLAVE	0xFE
-#define	CFG_EEPROM_PAGE_WRITE_DELAY_MS 12
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_FACT_OFFSET		0x1800
+#define CONFIG_SYS_FACT_SIZE		0x0800
+#define CONFIG_SYS_I2C_FACT_ADDR	0x57
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_SIZE 0x2000
+#define	CONFIG_SYS_I2C_SPEED	100000
+#define	CONFIG_SYS_I2C_SLAVE	0xFE
+#define	CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_MISC_INIT_R
 
@@ -195,7 +195,7 @@
 #define	I2C_TRISTATE	{ __I2C_DIR &= ~SDA; }
 #endif
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*-----------------------------------------------------------------------
  * defines we need to get FEC running
@@ -203,7 +203,7 @@
 #define	CONFIG_NET_MULTI	1	/* the only way to get the FEC in */
 #define CONFIG_FEC_ENET		1	/* Ethernet only via FEC	*/
 #define	FEC_ENET		1	/* eth.c needs it that way... */
-#define CFG_DISCOVER_PHY	1
+#define CONFIG_SYS_DISCOVER_PHY	1
 #define CONFIG_MII		1
 #define CONFIG_MII_INIT		1
 #define CONFIG_PHY_ADDR		31
@@ -211,35 +211,35 @@
 /*-----------------------------------------------------------------------
  * adresses
  */
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x80000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x80000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2f00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_VPD_SIZE	256 /* size in bytes reserved for vpd buffer */
-#define CFG_INIT_VPD_OFFSET	(CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE)
-#define CFG_INIT_SP_OFFSET	(CFG_INIT_VPD_OFFSET-8)
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2f00	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_VPD_SIZE	256 /* size in bytes reserved for vpd buffer */
+#define CONFIG_SYS_INIT_VPD_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_VPD_OFFSET-8)
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /* Interrupt level assignments.
@@ -259,7 +259,7 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER 0					/* used in start.S */
+#define CONFIG_SYS_DER 0					/* used in start.S */
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -279,7 +279,7 @@
  *	1	FIOPD	0			Force I/O pull down
  *	5	0		00000
  */
-#define CFG_PLPRCR	(PLPRCR_TEXPS | ((CFG_MF-1)<<20))
+#define CONFIG_SYS_PLPRCR	(PLPRCR_TEXPS | ((CONFIG_SYS_MF-1)<<20))
 
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control				11-9
@@ -296,10 +296,10 @@
  *	1	SWP		0/1			Software watchdog prescale (1=/2048)
  */
 #if defined (CONFIG_WATCHDOG)
- #define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ #define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 					 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
- #define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
+ #define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -328,21 +328,21 @@
  *	1	B3DD	0			Bank 3 double drive
  *	4	0		0000
  */
-#define CFG_SIUMCR	(SIUMCR_MLRC11)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_MLRC11)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -367,9 +367,9 @@
  */
 #define SCCR_MASK	0
 #ifdef CONFIG_EBDF
- #define CFG_SCCR	(SCCR_COM11 | SCCR_TBS | SCCR_EBDF01)
+ #define CONFIG_SYS_SCCR	(SCCR_COM11 | SCCR_TBS | SCCR_EBDF01)
 #else
- #define CFG_SCCR	(SCCR_COM11 | SCCR_TBS)
+ #define CONFIG_SYS_SCCR	(SCCR_COM11 | SCCR_TBS)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -378,9 +378,9 @@
  * Preliminary Values
  */
 /* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR)
-#define CFG_OR0_PRELIM	(-CFG_FLASH_MAX | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	(CFG_FLASH_BASE | BR_PS_16 | BR_V )
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR)
+#define CONFIG_SYS_OR0_PRELIM	(-CONFIG_SYS_FLASH_MAX | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V )
 
 /*-----------------------------------------------------------------------
  * misc
@@ -428,15 +428,15 @@
 /*-----------------------------------------------------------------------
  * Defaults for Autoscript
  */
-#define CFG_LOAD_ADDR		0x00100000	/* default load address */
-#define	CFG_TFTP_LOADADDR	0x00100000
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */
+#define	CONFIG_SYS_TFTP_LOADADDR	0x00100000
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index efc8da4..6850eba 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -42,7 +42,7 @@
 #define CONFIG_STK52XX		1	/* ... on a STK52XX board		*/
 #endif
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM		0x02	/* Software reboot			*/
@@ -54,11 +54,11 @@
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1			*/
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps			*/
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 #define CONFIG_BOOTCOUNT_LIMIT	1
 
 #ifdef CONFIG_FO300
-#define CFG_DEVICE_NULLDEV		1	/* enable null device */
+#define CONFIG_SYS_DEVICE_NULLDEV		1	/* enable null device */
 #define CONFIG_SILENT_CONSOLE		1	/* enable silent startup */
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* used to detect S1 switch position */
 #define CONFIG_USB_BIN_FIXUP		1	/* for a buggy USB device */
@@ -75,7 +75,7 @@
 #define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
 #define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
 #define CONFIG_PS2SERIAL	6	/* .. on PSC6			*/
-#define CONFIG_PS2MULT_DELAY	(CFG_HZ/2)	/* Initial delay	*/
+#define CONFIG_PS2MULT_DELAY	(CONFIG_SYS_HZ/2)	/* Initial delay	*/
 #define CONFIG_BOARD_EARLY_INIT_R
 #endif /* CONFIG_STK52XX */
 
@@ -99,7 +99,7 @@
 
 #define CONFIG_NET_MULTI	1
 #define CONFIG_EEPRO100		1
-#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
 #define CONFIG_NS8382X		1
 #endif	/* CONFIG_STK52XX */
 
@@ -122,7 +122,7 @@
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_SPLASH_SCREEN
-#define CFG_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #endif /* #ifndef CONFIG_TQM5200S */
 
 
@@ -134,24 +134,24 @@
 /* USB */
 #if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
 #define CONFIG_USB_OHCI_NEW
-#define CFG_OHCI_BE_CONTROLLER
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_USB
 
-#undef CFG_USB_OHCI_BOARD_INIT
-#define CFG_USB_OHCI_CPU_INIT
-#define CFG_USB_OHCI_REGS_BASE	MPC5XXX_USB
-#define CFG_USB_OHCI_SLOT_NAME	"mpc5200"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS	15
+#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	MPC5XXX_USB
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"mpc5200"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
 
 #endif
 
 #ifndef CONFIG_CAM5200
 /* POST support */
-#define CONFIG_POST		(CFG_POST_MEMORY   | \
-				 CFG_POST_CPU	   | \
-				 CFG_POST_I2C)
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_I2C)
 #endif
 
 #ifdef CONFIG_POST
@@ -215,7 +215,7 @@
 #define	CONFIG_TIMESTAMP		/* display image timestamps */
 
 #if (TEXT_BASE != 0xFFF00000)
-#   define CFG_LOWBOOT		1	/* Boot low */
+#   define CONFIG_SYS_LOWBOOT		1	/* Boot low */
 #endif
 
 /*
@@ -229,7 +229,7 @@
 
 #undef	CONFIG_BOOTARGS
 
-#if defined(CONFIG_TQM5200_B) && !defined(CFG_LOWBOOT)
+#if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT)
 # define ENV_UPDT							\
 	"update=protect off FFF00000 +${filesize};"			\
 		"erase FFF00000 +${filesize};"				\
@@ -307,17 +307,17 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
-#if defined(CFG_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
+#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
+ * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
  * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
+#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
 
 /*
@@ -325,9 +325,9 @@
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
 #ifdef CONFIG_TQM5200_REV100
-#define CFG_I2C_MODULE		1	/* Select I2C module #1 for rev. 100 board */
+#define CONFIG_SYS_I2C_MODULE		1	/* Select I2C module #1 for rev. 100 board */
 #else
-#define CFG_I2C_MODULE		2	/* Select I2C module #2 for all other revs */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #2 for all other revs */
 #endif
 
 /*
@@ -336,11 +336,11 @@
  * Please notice, that the resulting clock frequency could differ from the
  * configured value. This is because the I2C clock is derived from system
  * clock over a frequency divider with only a few divider values. U-boot
- * calculates the best approximation for CFG_I2C_SPEED. However the calculated
+ * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
  * approximation allways lies below the configured value, never above.
  */
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
@@ -348,62 +348,62 @@
  * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
  * same configuration could be used.
  */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CFG_I2C_EEPROM_ADDR_LEN		2
-#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
 
 /*
  * HW-Monitor configuration on Mini-FAP
  */
 #if defined (CONFIG_MINIFAP)
-#define CFG_I2C_HWMON_ADDR		0x2C
+#define CONFIG_SYS_I2C_HWMON_ADDR		0x2C
 #endif
 
 /* List of I2C addresses to be verified by POST */
 #if defined (CONFIG_MINIFAP)
 #undef I2C_ADDR_LIST
-#define I2C_ADDR_LIST	{	CFG_I2C_EEPROM_ADDR,	\
-				CFG_I2C_HWMON_ADDR,	\
-				CFG_I2C_SLAVE }
+#define I2C_ADDR_LIST	{	CONFIG_SYS_I2C_EEPROM_ADDR,	\
+				CONFIG_SYS_I2C_HWMON_ADDR,	\
+				CONFIG_SYS_I2C_SLAVE }
 #endif
 
 /*
  * Flash configuration
  */
-#define CFG_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
 
 #if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
-#define CFG_MAX_FLASH_BANKS	2	/* max num of flash banks
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of flash banks
 					   (= chip selects) */
-#define CFG_FLASH_WORD_SIZE	unsigned int /* main flash device with */
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-
-#define CFG_FLASH_ADDR0		0x555
-#define CFG_FLASH_ADDR1		0x2AA
-#define CFG_FLASH_2ND_16BIT_DEV	1	/* NIOS flash is a 16bit device */
-#define CFG_MAX_FLASH_SECT	128
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned int /* main flash device with */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+#define CONFIG_SYS_FLASH_ADDR0		0x555
+#define CONFIG_SYS_FLASH_ADDR1		0x2AA
+#define CONFIG_SYS_FLASH_2ND_16BIT_DEV	1	/* NIOS flash is a 16bit device */
+#define CONFIG_SYS_MAX_FLASH_SECT	128
 #else
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_BOOTCS_START }
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
 					   (= chip selects) */
-#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
 #endif
 
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
-#define CFG_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MByte */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
 
 #if defined (CONFIG_CAM5200)
-# define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000)
+# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
 #elif defined(CONFIG_TQM5200_B)
-# define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00080000)
+# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00080000)
 #else
-# define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
+# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
 #endif
 
 /* Dynamic MTD partition support */
@@ -412,7 +412,7 @@
 
 #ifdef CONFIG_STK52XX
 # if defined(CONFIG_TQM5200_B)
-#  if defined(CFG_LOWBOOT)
+#  if defined(CONFIG_SYS_LOWBOOT)
 #   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:1m(firmware),"	\
 						"256k(dtb),"		\
 						"2304k(kernel),"	\
@@ -427,7 +427,7 @@
 						"8m(misc),"		\
 						"15m(big-fs),"		\
 						"1m(firmware)"
-#  endif /* CFG_LOWBOOT */
+#  endif /* CONFIG_SYS_LOWBOOT */
 # else	/* !CONFIG_TQM5200_B */
 #   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
 						"128k(dtb),"		\
@@ -469,48 +469,49 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /* Use ON-Chip SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
 #else
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
 #endif
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
 #if defined (CONFIG_CAM5200)
-# define CFG_MONITOR_LEN	(256 << 10)	/* Reserve 256 kB for Monitor	*/
+# define CONFIG_SYS_MONITOR_LEN	(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #elif defined(CONFIG_TQM5200_B)
-# define CFG_MONITOR_LEN	(512 << 10)	/* Reserve 512 kB for Monitor	*/
+# define CONFIG_SYS_MONITOR_LEN	(512 << 10)	/* Reserve 512 kB for Monitor	*/
 #else
-# define CFG_MONITOR_LEN	(384 << 10)	/* Reserve 384 kB for Monitor	*/
+# define CONFIG_SYS_MONITOR_LEN	(384 << 10)	/* Reserve 384 kB for Monitor	*/
 #endif
 
-#define CFG_MALLOC_LEN		(1024 << 10)	/* Reserve 1024 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)	/* Reserve 1024 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
 /*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
  */
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
 #define CONFIG_PHY_ADDR		0x00
 
 /*
@@ -555,23 +556,23 @@
  *	 100 -> UART (on all boards).
  */
 #if defined (CONFIG_MINIFAP)
-# define CFG_GPS_PORT_CONFIG	0x91000004
+# define CONFIG_SYS_GPS_PORT_CONFIG	0x91000004
 #elif defined (CONFIG_STK52XX)
 # if defined (CONFIG_STK52XX_REV100)
-#  define CFG_GPS_PORT_CONFIG	0x81500014
+#  define CONFIG_SYS_GPS_PORT_CONFIG	0x81500014
 # else /* STK52xx REV200 and above */
 #  if defined (CONFIG_TQM5200_REV100)
 #   error TQM5200 REV100 not supported on STK52XX REV200 or above
 #  else/* TQM5200 REV200 and above */
-#   define CFG_GPS_PORT_CONFIG	0x91500404
+#   define CONFIG_SYS_GPS_PORT_CONFIG	0x91500404
 #  endif
 # endif
 #elif defined (CONFIG_FO300)
-# define CFG_GPS_PORT_CONFIG	0x91502c24
+# define CONFIG_SYS_GPS_PORT_CONFIG	0x91502c24
 #elif defined (CONFIG_CAM5200)
-# define CFG_GPS_PORT_CONFIG	0x8050A444
+# define CONFIG_SYS_GPS_PORT_CONFIG	0x8050A444
 #else  /* TMQ5200 Inbetriebnahme-Board */
-# define CFG_GPS_PORT_CONFIG	0x81000004
+# define CONFIG_SYS_GPS_PORT_CONFIG	0x81000004
 #endif
 
 /*
@@ -579,8 +580,8 @@
  */
 #if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
 # define CONFIG_RTC_M41T11 1
-# define CFG_I2C_RTC_ADDR 0x68
-# define CFG_M41T11_BASE_YEAR	1900    /* because Linux uses the same base
+# define CONFIG_SYS_I2C_RTC_ADDR 0x68
+# define CONFIG_SYS_M41T11_BASE_YEAR	1900    /* because Linux uses the same base
 					   year */
 #else
 # define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
@@ -589,36 +590,36 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
 /* Enable an alternate, more extensive memory test */
-#define CFG_ALT_MEMTEST
+#define CONFIG_SYS_ALT_MEMTEST
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 /*
  * Enable loopw command.
@@ -629,22 +630,22 @@
  * Various low-level settings
  */
 #if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 #else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
 #endif
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
-#define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
+#define CONFIG_SYS_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
 #else
-#define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
+#define CONFIG_SYS_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
 #endif
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
 #define CONFIG_LAST_STAGE_INIT
 
@@ -652,34 +653,34 @@
  * SRAM - Do not map below 2 GB in address space, because this area is used
  * for SDRAM autosizing.
  */
-#define CFG_CS2_START		0xE5000000
-#define CFG_CS2_SIZE		0x100000	/* 1 MByte */
-#define CFG_CS2_CFG		0x0004D930
+#define CONFIG_SYS_CS2_START		0xE5000000
+#define CONFIG_SYS_CS2_SIZE		0x100000	/* 1 MByte */
+#define CONFIG_SYS_CS2_CFG		0x0004D930
 
 /*
  * Grafic controller - Do not map below 2 GB in address space, because this
  * area is used for SDRAM autosizing.
  */
 #define SM501_FB_BASE		0xE0000000
-#define CFG_CS1_START		(SM501_FB_BASE)
-#define CFG_CS1_SIZE		0x4000000	/* 64 MByte */
-#define CFG_CS1_CFG		0x8F48FF70
-#define SM501_MMIO_BASE		CFG_CS1_START + 0x03E00000
+#define CONFIG_SYS_CS1_START		(SM501_FB_BASE)
+#define CONFIG_SYS_CS1_SIZE		0x4000000	/* 64 MByte */
+#define CONFIG_SYS_CS1_CFG		0x8F48FF70
+#define SM501_MMIO_BASE		CONFIG_SYS_CS1_START + 0x03E00000
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
 
 #if defined(CONFIG_CAM5200)
-#define CFG_CS4_START		0xB0000000
-#define CFG_CS4_SIZE		0x00010000
-#define CFG_CS4_CFG		0x01019C10
+#define CONFIG_SYS_CS4_START		0xB0000000
+#define CONFIG_SYS_CS4_SIZE		0x00010000
+#define CONFIG_SYS_CS4_CFG		0x01019C10
 
-#define CFG_CS5_START		0xD0000000
-#define CFG_CS5_SIZE		0x01208000
-#define CFG_CS5_CFG		0x1414BF10
+#define CONFIG_SYS_CS5_START		0xD0000000
+#define CONFIG_SYS_CS5_SIZE		0x01208000
+#define CONFIG_SYS_CS5_CFG		0x1414BF10
 #endif
 
-#define CFG_RESET_ADDRESS	0xff000000
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
 
 /*-----------------------------------------------------------------------
  * USB stuff
@@ -701,24 +702,27 @@
 #define CONFIG_IDE_RESET		/* reset for ide supported	*/
 #define CONFIG_IDE_PREINIT
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(0x0060)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005C)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
 
 /* Interval between registers						     */
-#define CFG_ATA_STRIDE		4
+#define CONFIG_SYS_ATA_STRIDE		4
+
+/* Support ATAPI devices */
+#define CONFIG_ATAPI            1
 
 /*-----------------------------------------------------------------------
  * Open firmware flat tree support
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index dc4582f..8934d51 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -86,7 +86,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -123,6 +123,7 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_NFS
@@ -138,32 +139,32 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -173,47 +174,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
@@ -223,7 +224,7 @@
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 #define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
 
@@ -242,16 +243,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -261,10 +262,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -273,9 +274,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -283,20 +284,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -304,7 +305,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -313,7 +314,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 
@@ -322,14 +323,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -342,28 +343,28 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -378,22 +379,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -404,19 +405,19 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 #ifndef	CONFIG_CAN_DRIVER
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 #endif	/* CONFIG_CAN_DRIVER */
 
@@ -447,34 +448,34 @@
  * 80 Mhz => 80.000.000 / Divider = 156
  */
 
-#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
-#define CFG_MAMR_PTA	98
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index 7ea7342..fd41573 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -84,7 +84,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -121,6 +121,7 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_NFS
@@ -133,32 +134,32 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -168,47 +169,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
@@ -219,7 +220,7 @@
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 #define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
 
@@ -238,16 +239,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -257,10 +258,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -269,9 +270,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -279,20 +280,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -300,7 +301,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -309,7 +310,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 
@@ -318,14 +319,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -338,28 +339,28 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -374,22 +375,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -400,19 +401,19 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 #ifndef	CONFIG_CAN_DRIVER
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 #endif	/* CONFIG_CAN_DRIVER */
 
@@ -443,34 +444,34 @@
  * 80 Mhz => 80.000.000 / Divider = 156
  */
 
-#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
-#define CFG_MAMR_PTA	98
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h
index 2d54d23..582e670 100644
--- a/include/configs/TQM8260.h
+++ b/include/configs/TQM8260.h
@@ -60,11 +60,7 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE		230400
-#else
-#define CONFIG_BAUDRATE		9600
-#endif
+#define CONFIG_BAUDRATE		115200
 
 #define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
 
@@ -83,18 +79,18 @@
 	"flash_self=run ramargs addip;"					\
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"rootpath=/opt/eldk/ppc_82xx\0"					\
-	"bootfile=/tftpboot/TQM8260/uImage\0"				\
-	"kernel_addr=40040000\0"					\
-	"ramdisk_addr=40100000\0"					\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"bootfile=tqm8260/uImage\0"				\
+	"kernel_addr=400C0000\0"					\
+	"ramdisk_addr=40240000\0"					\
 	""
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 /* enable I2C and select the hardware/software driver */
 #undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * Software (bit-bang) I2C driver configuration
@@ -126,10 +122,10 @@
 #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
 #endif
 
-#define CFG_I2C_EEPROM_ADDR	0x50
-#define CFG_I2C_EEPROM_ADDR_LEN 2
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
 #define CONFIG_I2C_X
 
@@ -183,7 +179,7 @@
  *  - RX clk is CLK11
  *  - TX clk is CLK12
  */
-# define CFG_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
+# define CONFIG_SYS_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
 
 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 
@@ -193,10 +189,10 @@
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 
@@ -213,7 +209,7 @@
 #endif	/* CONFIG_MPC8255 */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -245,142 +241,143 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define	CFG_RESET_ADDRESS 0xFFFFFFFC	/* "bad" address		*/
+#define	CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC	/* "bad" address		*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 
 
 /* What should the base address of the main FLASH be and how big is
  * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk
  * The main FLASH is whichever is connected to *CS0.
  */
-#define CFG_FLASH0_BASE 0x40000000
-#define CFG_FLASH1_BASE 0x60000000
-#define CFG_FLASH0_SIZE 32
-#define CFG_FLASH1_SIZE 32
+#define CONFIG_SYS_FLASH0_BASE 0x40000000
+#define CONFIG_SYS_FLASH1_BASE 0x60000000
+#define CONFIG_SYS_FLASH0_SIZE 32
+#define CONFIG_SYS_FLASH1_SIZE 32
 
 /* Flash bank size (for preliminary settings)
  */
-#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
+#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER		1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO	1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
 
-#if 0
-/* Start port with environment in flash; switch to EEPROM later */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE+0x40000)
-#define CONFIG_ENV_SIZE		0x40000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
+#define CONFIG_ENV_SIZE		0x08000
 #define CONFIG_ENV_SECT_SIZE	0x40000
-#else
-/* Final version: environment in EEPROM */
-#define CONFIG_ENV_IS_IN_EEPROM	1
-#define CONFIG_ENV_OFFSET		0
-#define CONFIG_ENV_SIZE		2048
-#endif
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
 
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  *
- * if you change bits in the HRCW, you must also change the CFG_*
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
  * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
  */
 #define	__HRCW__ALL__		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
 
 #if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
-#  define CFG_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
+#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
 #else	/* ! MPC8255 && !MPC8265 */
 # if defined(CONFIG_266MHz)
-#  define CFG_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
+#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
 # elif defined(CONFIG_300MHz)
-#  define CFG_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0110)
+#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0110)
 # else
-#  define CFG_HRCW_MASTER	(__HRCW__ALL__)
+#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__)
 # endif
 #endif	/* CONFIG_MPC8255 */
 
 /* no slaves so just fill with zeros */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  *
- * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
+ * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
  * is mapped at SDRAM_BASE2_PRELIM.
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		CFG_FLASH0_BASE
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()*/
 
 /*
  * Internal Definitions
@@ -394,9 +391,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 #if defined(CONFIG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -409,28 +406,28 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 				HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
-#define CFG_HID2        0
+#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2        0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register                                     5-5
  *-----------------------------------------------------------------------
  * turn on Checkstop Reset Enable
  */
-#define CFG_RMR         RMR_CSRE
+#define CONFIG_SYS_RMR         RMR_CSRE
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration                                       4-25
  *-----------------------------------------------------------------------
  */
 #ifdef	CONFIG_BUSMODE_60x
-#define CFG_BCR         (BCR_EBM|BCR_L2C|BCR_LETM|\
+#define CONFIG_SYS_BCR         (BCR_EBM|BCR_L2C|BCR_LETM|\
 			 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2)	/* 60x mode  */
 #else
 #define BCR_APD01	0x10000000
-#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -438,9 +435,9 @@
  *-----------------------------------------------------------------------
  */
 #if 0
-#define CFG_SIUMCR      (SIUMCR_DPPC10|SIUMCR_APPC10)
+#define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC10|SIUMCR_APPC10)
 #else
-#define CFG_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10)
+#define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10)
 #endif
 
 
@@ -451,10 +448,10 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
@@ -464,7 +461,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control                 4-42
@@ -472,20 +469,20 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control                                   9-8
  *-----------------------------------------------------------------------
  * Ensure DFBRG is Divide by 16
  */
-#define CFG_SCCR        0
+#define CONFIG_SYS_SCCR        0
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration                         13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR        0
+#define CONFIG_SYS_RCCR        0
 
 /*
  * Init Memory Controller:
@@ -500,17 +497,17 @@
 
 	/* Initialize SDRAM on local bus
 	 */
-#define CFG_INIT_LOCAL_SDRAM
+#define CONFIG_SYS_INIT_LOCAL_SDRAM
 
 #define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
 
 /* Minimum mask to separate preliminary
  * address ranges for CS[0:2]
  */
-#define CFG_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
-#define CFG_LOCAL_SDRAM_LIMIT	(128<<20)	/* less than 128 MB */
+#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
+#define CONFIG_SYS_LOCAL_SDRAM_LIMIT	(128<<20)	/* less than 128 MB */
 
-#define CFG_MPTPR       0x4000
+#define CONFIG_SYS_MPTPR       0x4000
 
 /*-----------------------------------------------------------------------------
  * Address for Mode Register Set (MRS) command
@@ -527,17 +524,17 @@
  *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
  *-----------------------------------------------------------------------------
  */
-#define CFG_MRS_OFFS	0x00000110
+#define CONFIG_SYS_MRS_OFFS	0x00000110
 
 
 /* Bank 0 - FLASH
  */
-#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_64                      |\
 			 BRx_MS_GPCM_P                  |\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 			 ORxG_CSNT                      |\
 			 ORxG_ACS_DIV1                  |\
 			 ORxG_SCY_3_CLK                 |\
@@ -550,25 +547,25 @@
 
 /* Bank 1 - 60x bus SDRAM
  */
-#define CFG_PSRT        0x20
-#define CFG_LSRT        0x20
-#ifndef CFG_RAMBOOT
-#define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+#define CONFIG_SYS_PSRT        0x20
+#define CONFIG_SYS_LSRT        0x20
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_64                      |\
 			 BRx_MS_SDRAM_P                 |\
 			 BRx_V)
 
-#define CFG_OR1_PRELIM	CFG_OR1_8COL
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR1_8COL
 
 
 	/* SDRAM initialization values for 8-column chips
 	 */
-#define CFG_OR1_8COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+#define CONFIG_SYS_OR1_8COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI1_A7             |\
 			 ORxS_NUMR_12)
 
-#define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
+#define CONFIG_SYS_PSDMR_8COL  (PSDMR_PBI                      |\
 			 PSDMR_SDAM_A15_IS_A5           |\
 			 PSDMR_BSMA_A12_A14             |\
 			 PSDMR_SDA10_PBI1_A8            |\
@@ -582,12 +579,12 @@
 
 	/* SDRAM initialization values for 9-column chips
 	 */
-#define CFG_OR1_9COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+#define CONFIG_SYS_OR1_9COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI1_A5             |\
 			 ORxS_NUMR_13)
 
-#define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
+#define CONFIG_SYS_PSDMR_9COL  (PSDMR_PBI                      |\
 			 PSDMR_SDAM_A16_IS_A5           |\
 			 PSDMR_BSMA_A12_A14             |\
 			 PSDMR_SDA10_PBI1_A7            |\
@@ -601,24 +598,24 @@
 
 /* Bank 2 - Local bus SDRAM
  */
-#ifdef CFG_INIT_LOCAL_SDRAM
-#define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
+#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
+#define CONFIG_SYS_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
 			 BRx_PS_32                      |\
 			 BRx_MS_SDRAM_L                 |\
 			 BRx_V)
 
-#define CFG_OR2_PRELIM	CFG_OR2_8COL
+#define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_OR2_8COL
 
 #define SDRAM_BASE2_PRELIM	0x80000000
 
 	/* SDRAM initialization values for 8-column chips
 	 */
-#define CFG_OR2_8COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+#define CONFIG_SYS_OR2_8COL    ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI1_A8             |\
 			 ORxS_NUMR_12)
 
-#define CFG_LSDMR_8COL  (PSDMR_PBI                      |\
+#define CONFIG_SYS_LSDMR_8COL  (PSDMR_PBI                      |\
 			 PSDMR_SDAM_A15_IS_A5           |\
 			 PSDMR_BSMA_A13_A15             |\
 			 PSDMR_SDA10_PBI1_A9            |\
@@ -632,12 +629,12 @@
 
 	/* SDRAM initialization values for 9-column chips
 	 */
-#define CFG_OR2_9COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+#define CONFIG_SYS_OR2_9COL    ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI1_A6             |\
 			 ORxS_NUMR_13)
 
-#define CFG_LSDMR_9COL  (PSDMR_PBI                      |\
+#define CONFIG_SYS_LSDMR_9COL  (PSDMR_PBI                      |\
 			 PSDMR_SDAM_A16_IS_A5           |\
 			 PSDMR_BSMA_A13_A15             |\
 			 PSDMR_SDA10_PBI1_A8            |\
@@ -649,8 +646,8 @@
 			 PSDMR_WRC_2C                   |\
 			 PSDMR_CL_2)
 
-#endif /* CFG_INIT_LOCAL_SDRAM */
+#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h
index 4e8cccd..9cac696 100644
--- a/include/configs/TQM8272.h
+++ b/include/configs/TQM8272.h
@@ -97,8 +97,8 @@
 /* enable I2C and select the hardware/software driver */
 #undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * Software (bit-bang) I2C driver configuration
@@ -116,22 +116,21 @@
 #define CONFIG_I2C_X
 
 /* EEPROM */
-#define CFG_I2C_EEPROM_ADDR_LEN 2
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE	/* necessary for the LM75 chip */
-#define CFG_I2C_MULTI_EEPROMS		1	/* more than one eeprom */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS		1	/* more than one eeprom */
 
 /* I2C RTC */
 #define CONFIG_RTC_DS1337		/* Use ds1337 rtc via i2c	*/
-#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68		*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68		*/
 
 /* I2C SYSMON (LM75) */
 #define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
 #define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
-#define CFG_DTT_MAX_TEMP	70
-#define CFG_DTT_LOW_TEMP	-30
-#define CFG_DTT_HYSTERESIS	3
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
 
 #else
 #undef CONFIG_HARD_I2C
@@ -177,9 +176,9 @@
  * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
  * X.29 connector, and FCC2 is hardwired to the X.1 connector)
  */
-#define CFG_FCC_ETHERNET
+#define CONFIG_SYS_FCC_ETHERNET
 
-#if defined(CFG_FCC_ETHERNET)
+#if defined(CONFIG_SYS_FCC_ETHERNET)
 #undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
 #define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
 #undef	CONFIG_ETHER_NONE		/* define if ether on something else */
@@ -197,7 +196,7 @@
  *  - RX clk is CLK11
  *  - TX clk is CLK12
  */
-# define CFG_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
+# define CONFIG_SYS_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
 
 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 
@@ -207,10 +206,10 @@
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 
@@ -222,35 +221,35 @@
 #define MDIO_PORT	2		/* Port C */
 
 #if STK82xx_150
-#define CFG_MDIO_PIN	0x00008000	/* PC16 */
-#define CFG_MDC_PIN	0x00004000	/* PC17 */
+#define CONFIG_SYS_MDIO_PIN	0x00008000	/* PC16 */
+#define CONFIG_SYS_MDC_PIN	0x00004000	/* PC17 */
 #endif
 
 #if STK82xx_100
-#define CFG_MDIO_PIN	0x00000002	/* PC30 */
-#define CFG_MDC_PIN	0x00000001	/* PC31 */
+#define CONFIG_SYS_MDIO_PIN	0x00000002	/* PC30 */
+#define CONFIG_SYS_MDC_PIN	0x00000001	/* PC31 */
 #endif
 
 #if 1
-#define MDIO_ACTIVE	(iop->pdir |=  CFG_MDIO_PIN)
-#define MDIO_TRISTATE	(iop->pdir &= ~CFG_MDIO_PIN)
-#define MDIO_READ	((iop->pdat &  CFG_MDIO_PIN) != 0)
+#define MDIO_ACTIVE	(iop->pdir |=  CONFIG_SYS_MDIO_PIN)
+#define MDIO_TRISTATE	(iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
+#define MDIO_READ	((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 
-#define MDIO(bit)	if(bit) iop->pdat |=  CFG_MDIO_PIN; \
-			else	iop->pdat &= ~CFG_MDIO_PIN
+#define MDIO(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
+			else	iop->pdat &= ~CONFIG_SYS_MDIO_PIN
 
-#define MDC(bit)	if(bit) iop->pdat |=  CFG_MDC_PIN; \
-			else	iop->pdat &= ~CFG_MDC_PIN
+#define MDC(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
+			else	iop->pdat &= ~CONFIG_SYS_MDC_PIN
 #else
-#define MDIO_ACTIVE	({unsigned long tmp; tmp = iop->pdir; tmp |=  CFG_MDIO_PIN; iop->pdir = tmp;})
-#define MDIO_TRISTATE	({unsigned long tmp; tmp = iop->pdir; tmp &= ~CFG_MDIO_PIN; iop->pdir = tmp;})
-#define MDIO_READ	((iop->pdat &  CFG_MDIO_PIN) != 0)
+#define MDIO_ACTIVE	({unsigned long tmp; tmp = iop->pdir; tmp |=  CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
+#define MDIO_TRISTATE	({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
+#define MDIO_READ	((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 
-#define MDIO(bit)	if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CFG_MDIO_PIN; iop->pdat = tmp;}\
-			else	{unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDIO_PIN; iop->pdat = tmp;}
+#define MDIO(bit)	if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\
+			else	{unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}
 
-#define MDC(bit)	if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CFG_MDC_PIN; iop->pdat = tmp;}\
-			else	{unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDC_PIN; iop->pdat = tmp;}
+#define MDC(bit)	if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\
+			else	{unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}
 #endif
 
 #define MIIDELAY	udelay(1)
@@ -260,7 +259,7 @@
 #define CONFIG_8260_CLKIN	66666666	/* in Hz */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -301,56 +300,56 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #if 0
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR	0x300000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR	0x300000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define	CFG_RESET_ADDRESS 0x40000104	/* "bad" address		*/
+#define	CONFIG_SYS_RESET_ADDRESS 0x40000104	/* "bad" address		*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * CAN stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_CAN_BASE	0x51000000
-#define	CFG_CAN_SIZE	1
-#define CFG_CAN_BR	((CFG_CAN_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_CAN_BASE	0x51000000
+#define	CONFIG_SYS_CAN_SIZE	1
+#define CONFIG_SYS_CAN_BR	((CONFIG_SYS_CAN_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_8			|\
 			 BRx_MS_UPMC			|\
 			 BRx_V)
 
-#define CFG_CAN_OR	(MEG_TO_AM(CFG_CAN_SIZE)	|\
+#define CONFIG_SYS_CAN_OR	(MEG_TO_AM(CONFIG_SYS_CAN_SIZE)	|\
 			 ORxU_BI)
 
 
@@ -358,31 +357,31 @@
  * it (in MBytes)? This must contain TEXT_BASE from board/tqm8272/config.mk
  * The main FLASH is whichever is connected to *CS0.
  */
-#define CFG_FLASH0_BASE 0x40000000
-#define CFG_FLASH0_SIZE 32	/* 32 MB */
+#define CONFIG_SYS_FLASH0_BASE 0x40000000
+#define CONFIG_SYS_FLASH0_SIZE 32	/* 32 MB */
 
 /* Flash bank size (for preliminary settings)
  */
-#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
+#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
 
-#define CFG_FLASH_CFI				/* flash is CFI compat.	*/
+#define CONFIG_SYS_FLASH_CFI				/* flash is CFI compat.	*/
 #define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver*/
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
-#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
 
-#define CFG_UPDATE_FLASH_SIZE
+#define CONFIG_SYS_UPDATE_FLASH_SIZE
 
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
 #define CONFIG_ENV_SIZE		0x20000
 #define CONFIG_ENV_SECT_SIZE	0x20000
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
@@ -390,14 +389,14 @@
 
 /* Where is the Hardwareinformation Block (from Monitor Sources) */
 #define MON_RES_LENGTH		(0x0003FC00)
-#define HWIB_INFO_START_ADDR    (CFG_FLASH_BASE + MON_RES_LENGTH)
+#define HWIB_INFO_START_ADDR    (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH)
 #define HWIB_INFO_LEN           512
-#define CIB_INFO_START_ADDR     (CFG_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
+#define CIB_INFO_START_ADDR     (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
 #define CIB_INFO_LEN            512
 
-#define CFG_HWINFO_OFFSET	0x3fc00	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000060	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x3fc00	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000060	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * NAND-FLASH stuff
@@ -405,32 +404,31 @@
  */
 #if defined(CONFIG_CMD_NAND)
 
-#define CFG_NAND_CS_DIST		0x80
-#define CFG_NAND_UPM_WRITE_CMD_OFS	0x20
-#define CFG_NAND_UPM_WRITE_ADDR_OFS	0x40
+#define CONFIG_SYS_NAND_CS_DIST		0x80
+#define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS	0x20
+#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS	0x40
 
-#define CFG_NAND_BR	((CFG_NAND0_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_NAND_BR	((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_8			|\
 			 BRx_MS_UPMB			|\
 			 BRx_V)
 
-#define CFG_NAND_OR	(MEG_TO_AM(CFG_NAND_SIZE)	|\
+#define CONFIG_SYS_NAND_OR	(MEG_TO_AM(CONFIG_SYS_NAND_SIZE)	|\
 			 ORxU_BI			|\
 			 ORxU_EHTR_8IDLE)
 
-#define CFG_NAND_SIZE	1
-#define CFG_NAND0_BASE 0x50000000
-#define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST)
-#define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST)
-#define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST)
+#define CONFIG_SYS_NAND_SIZE	1
+#define CONFIG_SYS_NAND0_BASE 0x50000000
+#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
+#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
+#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
 
-#define CFG_MAX_NAND_DEVICE     4       /* Max number of NAND devices           */
-#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE     4       /* Max number of NAND devices           */
 
-#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \
-			     CFG_NAND1_BASE, \
-			     CFG_NAND2_BASE, \
-			     CFG_NAND3_BASE, \
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
+			     CONFIG_SYS_NAND1_BASE, \
+			     CONFIG_SYS_NAND2_BASE, \
+			     CONFIG_SYS_NAND3_BASE, \
 			   }
 
 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
@@ -448,58 +446,58 @@
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 #define CONFIG_PCI_PNP
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
+#define CONFIG_SYS_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
 #define CONFIG_PCI_SCAN_SHOW
 #endif
 
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  *
- * if you change bits in the HRCW, you must also change the CFG_*
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
  * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
  */
 #if 0
 #define	__HRCW__ALL__		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
 
-#  define CFG_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
+#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
 #else
-#define CFG_HRCW_MASTER	(HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
+#define CONFIG_SYS_HRCW_MASTER	(HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
 #endif
 
 /* no slaves so just fill with zeros */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2000  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2000  /* End of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		CFG_FLASH0_BASE
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
 
 /*
  * Internal Definitions
@@ -512,9 +510,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 #if defined(CONFIG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -527,35 +525,35 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 				HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
-#define CFG_HID2        0
+#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2        0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register                                     5-5
  *-----------------------------------------------------------------------
  * turn on Checkstop Reset Enable
  */
-#define CFG_RMR         RMR_CSRE
+#define CONFIG_SYS_RMR         RMR_CSRE
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration                                       4-25
  *-----------------------------------------------------------------------
  */
-#define CFG_BCR_60x         (BCR_EBM|BCR_NPQM0|BCR_NPQM2)	/* 60x mode  */
+#define CONFIG_SYS_BCR_60x         (BCR_EBM|BCR_NPQM0|BCR_NPQM2)	/* 60x mode  */
 #define BCR_APD01	0x10000000
-#define CFG_BCR_SINGLE		(BCR_APD01|BCR_ETM)	/* 8260 mode */
+#define CONFIG_SYS_BCR_SINGLE		(BCR_APD01|BCR_ETM)	/* 8260 mode */
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration                             4-31
  *-----------------------------------------------------------------------
  */
 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
-#define CFG_SIUMCR_LOW		(SIUMCR_DPPC00)
-#define CFG_SIUMCR_HIGH		(SIUMCR_DPPC00 | SIUMCR_ABE)
+#define CONFIG_SYS_SIUMCR_LOW		(SIUMCR_DPPC00)
+#define CONFIG_SYS_SIUMCR_HIGH		(SIUMCR_DPPC00 | SIUMCR_ABE)
 #else
-#define CFG_SIUMCR		(SIUMCR_DPPC00)
+#define CONFIG_SYS_SIUMCR		(SIUMCR_DPPC00)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -565,10 +563,10 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
@@ -578,7 +576,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control                 4-42
@@ -586,20 +584,20 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control                                   9-8
  *-----------------------------------------------------------------------
  * Ensure DFBRG is Divide by 16
  */
-#define CFG_SCCR        SCCR_DFBRG01
+#define CONFIG_SYS_SCCR        SCCR_DFBRG01
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration                         13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR        0
+#define CONFIG_SYS_RCCR        0
 
 /*
  * Init Memory Controller:
@@ -615,16 +613,16 @@
 
 /* Initialize SDRAM
 	 */
-#undef CFG_INIT_LOCAL_SDRAM		/* No SDRAM on Local Bus */
+#undef CONFIG_SYS_INIT_LOCAL_SDRAM		/* No SDRAM on Local Bus */
 
 #define SDRAM_MAX_SIZE	0x20000000	/* max. 512 MB		*/
 
 /* Minimum mask to separate preliminary
  * address ranges for CS[0:2]
  */
-#define CFG_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
+#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
 
-#define CFG_MPTPR       0x4000
+#define CONFIG_SYS_MPTPR       0x4000
 
 /*-----------------------------------------------------------------------------
  * Address for Mode Register Set (MRS) command
@@ -641,16 +639,16 @@
  *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
  *-----------------------------------------------------------------------------
  */
-#define CFG_MRS_OFFS	0x00000110
+#define CONFIG_SYS_MRS_OFFS	0x00000110
 
 /* Bank 0 - FLASH
  */
-#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_32                      |\
 			 BRx_MS_GPCM_P                  |\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 			 ORxG_CSNT                      |\
 			 ORxG_ACS_DIV4                  |\
 			 ORxG_SCY_8_CLK                 |\
@@ -662,25 +660,25 @@
 
 /* Bank 1 - 60x bus SDRAM
  */
-#define CFG_PSRT        0x20	/* Low Value */
-/* #define CFG_PSRT        0x10	 Fast Value */
-#define CFG_LSRT        0x20	/* Local Bus */
-#ifndef CFG_RAMBOOT
-#define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+#define CONFIG_SYS_PSRT        0x20	/* Low Value */
+/* #define CONFIG_SYS_PSRT        0x10	 Fast Value */
+#define CONFIG_SYS_LSRT        0x20	/* Local Bus */
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_64                      |\
 			 BRx_MS_SDRAM_P                 |\
 			 BRx_V)
 
-#define CFG_OR1_PRELIM	CFG_OR1_8COL
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR1_8COL
 
 /* SDRAM initialization values for 8-column chips
  */
-#define CFG_OR1_8COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+#define CONFIG_SYS_OR1_8COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI1_A7             |\
 			 ORxS_NUMR_12)
 
-#define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
+#define CONFIG_SYS_PSDMR_8COL  (PSDMR_PBI                      |\
 			 PSDMR_SDAM_A15_IS_A5           |\
 			 PSDMR_BSMA_A12_A14             |\
 			 PSDMR_SDA10_PBI1_A8            |\
@@ -696,12 +694,12 @@
 
 /* SDRAM initialization values for 9-column chips
  */
-#define CFG_OR1_9COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+#define CONFIG_SYS_OR1_9COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI1_A5             |\
 			 ORxS_NUMR_13)
 
-#define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
+#define CONFIG_SYS_PSDMR_9COL  (PSDMR_PBI                      |\
 			 PSDMR_SDAM_A16_IS_A5           |\
 			 PSDMR_BSMA_A12_A14             |\
 			 PSDMR_SDA10_PBI1_A7            |\
@@ -714,12 +712,12 @@
 			 PSDMR_BUFCMD			|\
 			 PSDMR_CL_2)
 
-#define CFG_OR1_10COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+#define CONFIG_SYS_OR1_10COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI1_A4             |\
 			 ORxS_NUMR_13)
 
-#define CFG_PSDMR_10COL  (PSDMR_PBI                      |\
+#define CONFIG_SYS_PSDMR_10COL  (PSDMR_PBI                      |\
 			 PSDMR_SDAM_A17_IS_A5           |\
 			 PSDMR_BSMA_A12_A14             |\
 			 PSDMR_SDA10_PBI1_A4            |\
@@ -760,6 +758,6 @@
 #define PSDMR_BUFCMD_100MHZ_60X         0x00000000  /* PSDMR[BUFCMD] at 100 MHz 60x mode */
 #define PSDMR_BUFCMD_DEFAULT            PSDMR_BUFCMD_133MHZ_SINGLE  /* PSDMR[BUFCMD] default value */
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 3fd46a0..e126dc3 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -38,7 +38,7 @@
 #define CONFIG_TQM834X		1	/* TQM834X board specific */
 
 /* IMMR Base Addres Register, use Freescale default: 0xff400000 */
-#define CFG_IMMR		0xff400000
+#define CONFIG_SYS_IMMR		0xff400000
 
 /* System clock. Primary input clock when in PCI host mode */
 #define CONFIG_83XX_CLKIN	66666000	/* 66,666 MHz */
@@ -52,7 +52,7 @@
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)
+#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)
 
 /* board pre init: do not call, nothing to do */
 #undef CONFIG_BOARD_EARLY_INIT_F
@@ -63,141 +63,140 @@
 /*
  * DDR Setup
  */
-#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
 #define DDR_CASLAT_25				/* CASLAT set to 2.5 */
 #undef CONFIG_DDR_ECC				/* only for ECC DDR module */
 #undef CONFIG_SPD_EEPROM			/* do not use SPD EEPROM for DDR setup */
 
-#undef CFG_DRAM_TEST				/* memory test, takes time */
-#define CFG_MEMTEST_START	0x00000000	/* memtest region */
-#define CFG_MEMTEST_END		0x00100000
+#undef CONFIG_SYS_DRAM_TEST				/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
 
 /*
  * FLASH on the Local Bus
  */
-#define CFG_FLASH_CFI				/* use the Common Flash Interface */
+#define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
-#undef CFG_FLASH_CHECKSUM
-#define CFG_FLASH_BASE		0x80000000	/* start of FLASH   */
-#define CFG_FLASH_SIZE		8		/* FLASH size in MB */
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_BASE		0x80000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		8		/* FLASH size in MB */
 
 /* buffered writes in the AMD chip set is not supported yet */
-#undef CFG_FLASH_USE_BUFFER_WRITE
+#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 /*
  * FLASH bank number detection
  */
 
 /*
- * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
+ * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
  * banks has to be determined at runtime and stored in a gloabl variable
- * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only
- * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and
+ * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is only
+ * used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array flash_info, and
  * should be made sufficiently large to accomodate the number of banks that
  * might actually be detected.  Since most (all?) Flash related functions use
- * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is
+ * CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on the board, it is
  * defined as tqm834x_num_flash_banks.
  */
-#define CFG_MAX_FLASH_BANKS_DETECT	2
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	2
 #ifndef __ASSEMBLY__
 extern int tqm834x_num_flash_banks;
 #endif
-#define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
+#define CONFIG_SYS_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
 
-#define CFG_MAX_FLASH_SECT		512	/* max sectors per device */
+#define CONFIG_SYS_MAX_FLASH_SECT		512	/* max sectors per device */
 
 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
-#define CFG_BR0_PRELIM		((CFG_FLASH_BASE & BR_BA) | \
+#define CONFIG_SYS_BR0_PRELIM		((CONFIG_SYS_FLASH_BASE & BR_BA) | \
 					BR_MS_GPCM | BR_PS_32 | BR_V)
 
 /* FLASH timing (0x0000_0c54) */
-#define CFG_OR_TIMING_FLASH	(OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
 					OR_GPCM_SCY_5 | OR_GPCM_TRLX)
 
-#define CFG_PRELIM_OR_AM	0xc0000000	/* OR addr mask: 1 GiB */
+#define CONFIG_SYS_PRELIM_OR_AM	0xc0000000	/* OR addr mask: 1 GiB */
 
-#define CFG_OR0_PRELIM		(CFG_PRELIM_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM		(CONFIG_SYS_PRELIM_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 
-#define CFG_LBLAWAR0_PRELIM	0x8000001D	/* 1 GiB window size (2^(size + 1)) */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x8000001D	/* 1 GiB window size (2^(size + 1)) */
 
-#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE	/* Window base at flash base */
 
 /* disable remaining mappings */
-#define CFG_BR1_PRELIM		0x00000000
-#define CFG_OR1_PRELIM		0x00000000
-#define CFG_LBLAWBAR1_PRELIM	0x00000000
-#define CFG_LBLAWAR1_PRELIM	0x00000000
-
-#define CFG_BR2_PRELIM		0x00000000
-#define CFG_OR2_PRELIM		0x00000000
-#define CFG_LBLAWBAR2_PRELIM	0x00000000
-#define CFG_LBLAWAR2_PRELIM	0x00000000
-
-#define CFG_BR3_PRELIM		0x00000000
-#define CFG_OR3_PRELIM		0x00000000
-#define CFG_LBLAWBAR3_PRELIM	0x00000000
-#define CFG_LBLAWAR3_PRELIM	0x00000000
-
-#define CFG_BR4_PRELIM		0x00000000
-#define CFG_OR4_PRELIM		0x00000000
-#define CFG_LBLAWBAR4_PRELIM	0x00000000
-#define CFG_LBLAWAR4_PRELIM	0x00000000
-
-#define CFG_BR5_PRELIM		0x00000000
-#define CFG_OR5_PRELIM		0x00000000
-#define CFG_LBLAWBAR5_PRELIM	0x00000000
-#define CFG_LBLAWAR5_PRELIM	0x00000000
-
-#define CFG_BR6_PRELIM		0x00000000
-#define CFG_OR6_PRELIM		0x00000000
-#define CFG_LBLAWBAR6_PRELIM	0x00000000
-#define CFG_LBLAWAR6_PRELIM	0x00000000
-
-#define CFG_BR7_PRELIM		0x00000000
-#define CFG_OR7_PRELIM		0x00000000
-#define CFG_LBLAWBAR7_PRELIM	0x00000000
-#define CFG_LBLAWAR7_PRELIM	0x00000000
+#define CONFIG_SYS_BR1_PRELIM		0x00000000
+#define CONFIG_SYS_OR1_PRELIM		0x00000000
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	0x00000000
+#define CONFIG_SYS_LBLAWAR1_PRELIM	0x00000000
+
+#define CONFIG_SYS_BR2_PRELIM		0x00000000
+#define CONFIG_SYS_OR2_PRELIM		0x00000000
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	0x00000000
+#define CONFIG_SYS_LBLAWAR2_PRELIM	0x00000000
+
+#define CONFIG_SYS_BR3_PRELIM		0x00000000
+#define CONFIG_SYS_OR3_PRELIM		0x00000000
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	0x00000000
+#define CONFIG_SYS_LBLAWAR3_PRELIM	0x00000000
+
+#define CONFIG_SYS_BR4_PRELIM		0x00000000
+#define CONFIG_SYS_OR4_PRELIM		0x00000000
+#define CONFIG_SYS_LBLAWBAR4_PRELIM	0x00000000
+#define CONFIG_SYS_LBLAWAR4_PRELIM	0x00000000
+
+#define CONFIG_SYS_BR5_PRELIM		0x00000000
+#define CONFIG_SYS_OR5_PRELIM		0x00000000
+#define CONFIG_SYS_LBLAWBAR5_PRELIM	0x00000000
+#define CONFIG_SYS_LBLAWAR5_PRELIM	0x00000000
+
+#define CONFIG_SYS_BR6_PRELIM		0x00000000
+#define CONFIG_SYS_OR6_PRELIM		0x00000000
+#define CONFIG_SYS_LBLAWBAR6_PRELIM	0x00000000
+#define CONFIG_SYS_LBLAWAR6_PRELIM	0x00000000
+
+#define CONFIG_SYS_BR7_PRELIM		0x00000000
+#define CONFIG_SYS_OR7_PRELIM		0x00000000
+#define CONFIG_SYS_LBLAWBAR7_PRELIM	0x00000000
+#define CONFIG_SYS_LBLAWAR7_PRELIM	0x00000000
 
 /*
  * Monitor config
  */
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef  CFG_RAMBOOT
+#undef  CONFIG_SYS_RAMBOOT
 #endif
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0x20000000	/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/
 
-#define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(256 * 1024) /* Reserve 256 kB for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024) /* Reserve 256 kB for malloc */
 
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1	(CFG_IMMR + 0x4500)
-#define CFG_NS16550_COM2	(CFG_IMMR + 0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
 
 /*
  * I2C
@@ -205,28 +204,27 @@ extern int tqm834x_num_flash_banks;
 #define CONFIG_HARD_I2C				/* I2C with hardware support	*/
 #undef CONFIG_SOFT_I2C				/* I2C bit-banged		*/
 #define CONFIG_FSL_I2C
-#define CFG_I2C_SPEED			400000	/* I2C speed: 400KHz		*/
-#define CFG_I2C_SLAVE			0x7F	/* slave address		*/
-#define CFG_I2C_OFFSET			0x3000
+#define CONFIG_SYS_I2C_SPEED			400000	/* I2C speed: 400KHz		*/
+#define CONFIG_SYS_I2C_SLAVE			0x7F	/* slave address		*/
+#define CONFIG_SYS_I2C_OFFSET			0x3000
 
 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x			*/
-#define CFG_I2C_EEPROM_ADDR_LEN		2	/* 16 bit			*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 32 bytes per write		*/
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	12	/* 10ms +/- 20%			*/
-#define CFG_I2C_MULTI_EEPROMS		1       /* more than one eeprom		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x			*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* 16 bit			*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 32 bytes per write		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	12	/* 10ms +/- 20%			*/
+#define CONFIG_SYS_I2C_MULTI_EEPROMS		1       /* more than one eeprom		*/
 
 /* I2C RTC */
 #define CONFIG_RTC_DS1337			/* use ds1337 rtc via i2c	*/
-#define CFG_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
 
 /* I2C SYSMON (LM75) */
 #define CONFIG_DTT_LM75			1	/* ON Semi's LM75		*/
 #define CONFIG_DTT_SENSORS		{0}	/* Sensor addresses		*/
-#define CFG_DTT_MAX_TEMP		70
-#define CFG_DTT_LOW_TEMP		-30
-#define CFG_DTT_HYSTERESIS		3
+#define CONFIG_SYS_DTT_MAX_TEMP		70
+#define CONFIG_SYS_DTT_LOW_TEMP		-30
+#define CONFIG_SYS_DTT_HYSTERESIS		3
 
 /*
  * TSEC
@@ -234,10 +232,10 @@ extern int tqm834x_num_flash_banks;
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_MII
 
-#define CFG_TSEC1_OFFSET	0x24000
-#define CFG_TSEC1		(CFG_IMMR + CFG_TSEC1_OFFSET)
-#define CFG_TSEC2_OFFSET	0x25000
-#define CFG_TSEC2		(CFG_IMMR + CFG_TSEC2_OFFSET)
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
 
 #if defined(CONFIG_TSEC_ENET)
 
@@ -273,24 +271,24 @@ extern int tqm834x_num_flash_banks;
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 
 /* PCI1 host bridge */
-#define CFG_PCI1_MEM_BASE       0xc0000000
-#define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CFG_PCI1_IO_BASE        0xe2000000
-#define CFG_PCI1_IO_PHYS        CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE        0x1000000       /* 16M */
+#define CONFIG_SYS_PCI1_MEM_BASE       0xc0000000
+#define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
+#define CONFIG_SYS_PCI1_IO_BASE        0xe2000000
+#define CONFIG_SYS_PCI1_IO_PHYS        CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_SIZE        0x1000000       /* 16M */
 
 #undef CONFIG_EEPRO100
 #define CONFIG_EEPRO100
 #undef CONFIG_TULIP
 
 #if !defined(CONFIG_PCI_PNP)
-	#define PCI_ENET0_IOADDR	CFG_PCI1_IO_BASE
-	#define PCI_ENET0_MEMADDR	CFG_PCI1_MEM_BASE
+	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BASE
+	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_MEM_BASE
 	#define PCI_IDSEL_NUMBER	0x1c    /* slot0 (IDSEL) = 28 */
 #endif
 
-#define CFG_PCI_SUBSYS_VENDORID		0x1957  /* Freescale */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID		0x1957  /* Freescale */
 
 #endif	/* CONFIG_PCI */
 
@@ -299,20 +297,20 @@ extern int tqm834x_num_flash_banks;
  */
 #define CONFIG_ENV_OVERWRITE
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
 	#define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
 	#define CONFIG_ENV_SIZE		0x2000
 #else
-	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 	#define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE		1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE		1	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -341,34 +339,34 @@ extern int tqm834x_num_flash_banks;
     #define CONFIG_CMD_PCI
 #endif
 
-#if defined(CFG_RAMBOOT)
-    #undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory	*/
-#define CFG_LOAD_ADDR		0x2000000	/* default load address */
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory	*/
+#define CONFIG_SYS_LOAD_ADDR		0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-	#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ			1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1ms ticks */
 
 #undef CONFIG_WATCHDOG				/* watchdog disabled */
 
@@ -377,9 +375,9 @@ extern int tqm834x_num_flash_banks;
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN_4X1 |\
@@ -387,7 +385,7 @@ extern int tqm834x_num_flash_banks;
 	HRCWL_CORE_TO_CSB_2X1)
 
 #if defined(PCI_64BIT)
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_64_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
@@ -400,7 +398,7 @@ extern int tqm834x_num_flash_banks;
 	HRCWH_TSEC1M_IN_GMII |\
 	HRCWH_TSEC2M_IN_GMII )
 #else
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_32_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
@@ -415,67 +413,67 @@ extern int tqm834x_num_flash_banks;
 #endif
 
 /* System IO Config */
-#define CFG_SICRH	SICRH_TSOBI1
-#define CFG_SICRL	SICRL_LDP_A
+#define CONFIG_SYS_SICRH	SICRH_TSOBI1
+#define CONFIG_SYS_SICRL	SICRL_LDP_A
 
 /* i-cache and d-cache disabled */
-#define CFG_HID0_INIT	0x000000000
-#define CFG_HID0_FINAL	CFG_HID0_INIT
-#define CFG_HID2	HID2_HBE
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	CONFIG_SYS_HID0_INIT
+#define CONFIG_SYS_HID2	HID2_HBE
 
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR 0 - 512M */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT1L	(CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* stack in DCACHE @ 512M (no backing mem) */
-#define CFG_IBAT2L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT2U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 
 /* PCI */
 #ifdef CONFIG_PCI
-#define CFG_IBAT3L	(CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT3U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT4L	(CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT4U	(CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT5L	(CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT5U	(CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
 #else
-#define CFG_IBAT3L	(0)
-#define CFG_IBAT3U	(0)
-#define CFG_IBAT4L	(0)
-#define CFG_IBAT4U	(0)
-#define CFG_IBAT5L	(0)
-#define CFG_IBAT5U	(0)
+#define CONFIG_SYS_IBAT3L	(0)
+#define CONFIG_SYS_IBAT3U	(0)
+#define CONFIG_SYS_IBAT4L	(0)
+#define CONFIG_SYS_IBAT4U	(0)
+#define CONFIG_SYS_IBAT5L	(0)
+#define CONFIG_SYS_IBAT5U	(0)
 #endif
 
 /* IMMRBAR */
-#define CFG_IBAT6L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT6U	(CFG_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)
 
 /* FLASH */
-#define CFG_IBAT7L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT7U	(CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
-#define CFG_DBAT4L	CFG_IBAT4L
-#define CFG_DBAT4U	CFG_IBAT4U
-#define CFG_DBAT5L	CFG_IBAT5L
-#define CFG_DBAT5U	CFG_IBAT5U
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 
 /*
  * Internal Definitions
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index 473c390..77eb5a9 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -80,7 +80,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -112,6 +112,7 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_NFS
@@ -123,32 +124,32 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -158,47 +159,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
@@ -208,7 +209,7 @@
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 #define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
 
@@ -227,16 +228,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -246,10 +247,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -258,9 +259,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -268,20 +269,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -289,7 +290,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -298,7 +299,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 
@@ -307,14 +308,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -327,28 +328,28 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -363,22 +364,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -389,19 +390,19 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 #ifndef	CONFIG_CAN_DRIVER
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 #endif	/* CONFIG_CAN_DRIVER */
 
@@ -432,34 +433,34 @@
  * 80 Mhz => 80.000.000 / Divider = 156
  */
 
-#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
-#define CFG_MAMR_PTA	98
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index 4de5a33..bb8825b 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -78,7 +78,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -110,6 +110,7 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_NFS
@@ -122,32 +123,32 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -157,47 +158,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
@@ -208,7 +209,7 @@
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 #define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
 
@@ -227,16 +228,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -246,10 +247,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -258,9 +259,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -268,20 +269,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -289,7 +290,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -298,7 +299,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 
@@ -307,14 +308,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -327,28 +328,28 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -363,22 +364,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -389,19 +390,19 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 #ifndef	CONFIG_CAN_DRIVER
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 #endif	/* CONFIG_CAN_DRIVER */
 
@@ -432,34 +433,34 @@
  * 80 Mhz => 80.000.000 / Divider = 156
  */
 
-#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
-#define CFG_MAMR_PTA	98
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index 2ba94c8..2ccbaf8 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -83,7 +83,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -116,6 +116,7 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_NFS
@@ -128,32 +129,32 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -163,47 +164,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
@@ -213,7 +214,7 @@
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 #define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
 
@@ -232,16 +233,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -251,10 +252,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -263,9 +264,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -273,20 +274,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -294,7 +295,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -303,7 +304,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 
@@ -312,14 +313,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -332,28 +333,28 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -368,22 +369,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -394,19 +395,19 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 #ifndef	CONFIG_CAN_DRIVER
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 #endif	/* CONFIG_CAN_DRIVER */
 
@@ -437,34 +438,34 @@
  * 80 Mhz => 80.000.000 / Divider = 156
  */
 
-#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
-#define CFG_MAMR_PTA	98
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index 7699d51..8a65183 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -83,7 +83,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -95,8 +95,8 @@
 #undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/
 
-#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
-#define CFG_I2C_SLAVE		0xFE
+#define CONFIG_SYS_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CONFIG_SYS_I2C_SLAVE		0xFE
 
 #ifdef CONFIG_SOFT_I2C
 /*
@@ -116,12 +116,12 @@
 #define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
 #endif	/* CONFIG_SOFT_I2C */
 
-#define CFG_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C64	*/
-#define CFG_I2C_EEPROM_ADDR_LEN	2		/* two byte address	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C64	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2		/* two byte address	*/
 #if 0
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
-#define CFG_EEPROM_PAGE_WRITE_BITS	5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
 #endif
 
 /*
@@ -149,6 +149,7 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
@@ -162,32 +163,32 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -197,47 +198,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
@@ -248,7 +249,7 @@
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 #define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
 
@@ -267,16 +268,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -286,10 +287,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -298,9 +299,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -308,20 +309,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -329,7 +330,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -338,7 +339,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 
@@ -347,14 +348,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -367,28 +368,28 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -403,22 +404,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -429,19 +430,19 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 #ifndef	CONFIG_CAN_DRIVER
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 #endif	/* CONFIG_CAN_DRIVER */
 
@@ -472,34 +473,34 @@
  * 80 Mhz => 80.000.000 / Divider = 156
  */
 
-#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
-#define CFG_MAMR_PTA	98
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index fcf0f59..3b2272c 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -41,14 +41,21 @@
 #define CONFIG_E500		1	/* BOOKE e500 family		*/
 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41		*/
 
+#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
+#define CONFIG_TQM8548
+#endif
+
 #define CONFIG_PCI
+#ifndef CONFIG_TQM8548_AG
+#define CONFIG_PCI1			/* PCI/PCI-X controller		*/
+#endif
+#ifdef CONFIG_TQM8548
+#define CONFIG_PCIE1			/* PCI Express interface	*/
+#endif
+
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code	*/
 #define CONFIG_PCIX_CHECK		/* PCIX olny works at 66 MHz	*/
-#ifdef CONFIG_TQM8548
-#define CONFIG_PCI1
-#define CONFIG_PCIE1
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata	*/
-#endif
 
 #define CONFIG_TSEC_ENET		/* tsec ethernet support	*/
 
@@ -70,7 +77,9 @@
  * Warning: NAND support will likely increase the U-Boot image size
  * to more than 256 KB. Please adjust TEXT_BASE if necessary.
  */
-#undef CONFIG_NAND
+#ifdef CONFIG_TQM8548_BE
+#define CONFIG_NAND
+#endif
 
 /*
  * MPC8540 and MPC8548 don't have CPM module
@@ -81,7 +90,9 @@
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code	*/
 
-#undef	CONFIG_CAN_DRIVER		/* CAN Driver support		*/
+#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
+#define	CONFIG_CAN_DRIVER		/* CAN Driver support		*/
+#endif
 
 /*
  * sysclk for MPC85xx
@@ -106,36 +117,38 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache		*/
 #define CONFIG_BTB			/* toggle branch predition	*/
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming	*/
 
-#define CFG_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions	*/
+#define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions	*/
 
-#undef	CFG_DRAM_TEST			/* memory test, takes time	*/
-#define CFG_MEMTEST_START	0x00000000
-#define CFG_MEMTEST_END		0x10000000
+#undef	CONFIG_SYS_DRAM_TEST			/* memory test, takes time	*/
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END		0x10000000
 
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xFF700000	/* CCSRBAR Default	*/
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xFF700000	/* CCSRBAR Default	*/
 #ifdef CONFIG_TQM_BIGFLASH
-#define CFG_CCSRBAR	 	0xA0000000	/* relocated CCSRBAR	*/
+#define CONFIG_SYS_CCSRBAR	 	0xA0000000	/* relocated CCSRBAR	*/
 #else /* !CONFIG_TQM_BIGFLASH */
-#define CFG_CCSRBAR		0xE0000000	/* relocated CCSRBAR	*/
+#define CONFIG_SYS_CCSRBAR		0xE0000000	/* relocated CCSRBAR	*/
 #endif /* CONFIG_TQM_BIGFLASH */
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR	*/
 
-#define CFG_PCI1_ADDR		(CFG_CCSRBAR + 0x8000)
-#define CFG_PCI2_ADDR		(CFG_CCSRBAR + 0x9000)
-#define CFG_PCIE1_ADDR		(CFG_CCSRBAR + 0xa000)
+#define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR + 0x8000)
+#define CONFIG_SYS_PCI2_ADDR		(CONFIG_SYS_CCSRBAR + 0x9000)
+#define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR + 0xa000)
 
 /*
  * DDR Setup
  */
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	*/
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#ifdef CONFIG_TQM8548_AG
+#define CONFIG_VERY_BIG_RAM
+#endif
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
@@ -165,16 +178,16 @@
  * Flash on the Local Bus
  */
 #ifdef CONFIG_TQM_BIGFLASH
-#define CFG_FLASH0		0xE0000000
-#define CFG_FLASH1		0xC0000000
+#define CONFIG_SYS_FLASH0		0xE0000000
+#define CONFIG_SYS_FLASH1		0xC0000000
 #else /* !CONFIG_TQM_BIGFLASH */
-#define CFG_FLASH0		0xFC000000
-#define CFG_FLASH1		0xF8000000
+#define CONFIG_SYS_FLASH0		0xFC000000
+#define CONFIG_SYS_FLASH1		0xF8000000
 #endif /* CONFIG_TQM_BIGFLASH */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH1, CFG_FLASH0 }
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
 
-#define CFG_LBC_FLASH_BASE	CFG_FLASH1	/* Localbus flash start	*/
-#define CFG_FLASH_BASE		CFG_LBC_FLASH_BASE  /* start of FLASH	*/
+#define CONFIG_SYS_LBC_FLASH_BASE	CONFIG_SYS_FLASH1	/* Localbus flash start	*/
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_LBC_FLASH_BASE  /* start of FLASH	*/
 
 /* Default ORx timings are for <= 41.7 MHz Local Bus Clock.
  *
@@ -183,7 +196,7 @@
  *
  * For other Local Bus Clocks see following table:
  *
- * Clock/MHz   CFG_ORx_PRELIM
+ * Clock/MHz   CONFIG_SYS_ORx_PRELIM
  * 166         0x.....CA5
  * 133         0x.....C85
  * 100         0x.....C65
@@ -196,56 +209,55 @@
  *
  */
 #ifdef CONFIG_TQM_BIGFLASH
-#define CFG_BR0_PRELIM		0xE0001801	/* port size 32bit	*/
-#define CFG_OR0_PRELIM		0xE0000040	/* 512MB Flash		*/
-#define CFG_BR1_PRELIM		0xC0001801	/* port size 32bit	*/
-#define CFG_OR1_PRELIM		0xE0000040	/* 512MB Flash		*/
+#define CONFIG_SYS_BR0_PRELIM		0xE0001801	/* port size 32bit	*/
+#define CONFIG_SYS_OR0_PRELIM		0xE0000040	/* 512MB Flash		*/
+#define CONFIG_SYS_BR1_PRELIM		0xC0001801	/* port size 32bit	*/
+#define CONFIG_SYS_OR1_PRELIM		0xE0000040	/* 512MB Flash		*/
 #else /* !CONFIG_TQM_BIGFLASH */
-#define CFG_BR0_PRELIM		0xfc001801	/* port size 32bit	*/
-#define CFG_OR0_PRELIM		0xfc000040	/* 64MB Flash		*/
-#define CFG_BR1_PRELIM		0xf8001801	/* port size 32bit	*/
-#define CFG_OR1_PRELIM		0xfc000040	/* 64MB Flash		*/
+#define CONFIG_SYS_BR0_PRELIM		0xfc001801	/* port size 32bit	*/
+#define CONFIG_SYS_OR0_PRELIM		0xfc000040	/* 64MB Flash		*/
+#define CONFIG_SYS_BR1_PRELIM		0xf8001801	/* port size 32bit	*/
+#define CONFIG_SYS_OR1_PRELIM		0xfc000040	/* 64MB Flash		*/
 #endif /* CONFIG_TQM_BIGFLASH */
 
-#define CFG_FLASH_CFI			/* flash is CFI compat.		*/
+#define CONFIG_SYS_FLASH_CFI			/* flash is CFI compat.		*/
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
-#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
-#define CFG_FLASH_USE_BUFFER_WRITE	1 /* speed up output to Flash	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1 /* speed up output to Flash	*/
 
-#define CFG_MAX_FLASH_BANKS	2	/* number of banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* sectors per device		*/
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms)	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device		*/
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms)	*/
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
 
 /*
  * Note: when changing the Local Bus clock divider you have to
- * change the timing values in CFG_ORx_PRELIM.
+ * change the timing values in CONFIG_SYS_ORx_PRELIM.
  *
  * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8.
  * LCRR[16:17] EADC  : External address delay cycles. It should be set to 2
  *                     for Local Bus Clock > 83.3 MHz.
  */
-#define CFG_LBC_LCRR		0x00030008	/* LB clock ratio reg	*/
-#define CFG_LBC_LBCR		0x00000000	/* LB config reg	*/
-#define CFG_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
-#define CFG_LBC_MRTPR		0x20000000	/* LB refresh timer presc.*/
-
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	(CFG_CCSRBAR \
+#define CONFIG_SYS_LBC_LCRR		0x00030008	/* LB clock ratio reg	*/
+#define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg	*/
+#define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x20000000	/* LB refresh timer presc.*/
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_CCSRBAR \
 				 + 0x04010000)	/* Initial RAM address	*/
-#define CFG_INIT_RAM_END	0x4000		/* End used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End used area in RAM	*/
 
-#define CFG_GBL_DATA_SIZE	128	/* num bytes initial data	*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(~TEXT_BASE + 1)/* Reserved for Monitor	*/
-#define CFG_MALLOC_LEN		(384 * 1024)	/* Reserved for malloc	*/
+#define CONFIG_SYS_MONITOR_LEN		(~TEXT_BASE + 1)/* Reserved for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(384 * 1024)	/* Reserved for malloc	*/
 
 /* Serial Port */
 #if defined(CONFIG_TQM8560)
@@ -258,32 +270,32 @@
 
 #define CONFIG_CONS_INDEX     1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
 /* PS/2 Keyboard */
 #define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
 #define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
 #define CONFIG_PS2SERIAL	2	/* .. on DUART2			*/
-#define CONFIG_PS2MULT_DELAY	(CFG_HZ/2)	/* Initial delay	*/
+#define CONFIG_PS2MULT_DELAY	(CONFIG_SYS_HZ/2)	/* Initial delay	*/
 #define CONFIG_BOARD_EARLY_INIT_R	1
 
 #endif /* CONFIG_TQM8560 */
 
 #define CONFIG_BAUDRATE		115200
 
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 /* pass open firmware flat tree */
@@ -292,12 +304,12 @@
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
 /* CAN */
-#define CFG_CAN_BASE		(CFG_CCSRBAR \
+#define CONFIG_SYS_CAN_BASE		(CONFIG_SYS_CCSRBAR \
 				 + 0x03000000)	/* CAN base address     */
 #ifdef CONFIG_CAN_DRIVER
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 KiB address mask  */
-#define CFG_OR2_CAN		(CFG_CAN_OR_AM | OR_UPM_BI)
-#define CFG_BR2_CAN		((CFG_CAN_BASE & BR_BA) | \
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 KiB address mask  */
+#define CONFIG_SYS_OR2_CAN		(CONFIG_SYS_CAN_OR_AM | OR_UPM_BI)
+#define CONFIG_SYS_BR2_CAN		((CONFIG_SYS_CAN_BASE & BR_BA) | \
 				 BR_PS_8 | BR_MS_UPMC | BR_V)
 #endif /* CONFIG_CAN_DRIVER */
 
@@ -307,43 +319,42 @@
 #define CONFIG_FSL_I2C			/* Use FSL common I2C driver	*/
 #define CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x48}	/* Don't probe these addrs	*/
-#define CFG_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{0x48}	/* Don't probe these addrs	*/
+#define CONFIG_SYS_I2C_OFFSET		0x3000
 
 /* I2C RTC */
 #define CONFIG_RTC_DS1337		/* Use ds1337 rtc via i2c	*/
-#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68		*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68		*/
 
 /* I2C EEPROM */
 /*
  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
  */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x		*/
-#define CFG_I2C_EEPROM_ADDR_LEN		2
-#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write	*/
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
-#define CFG_I2C_MULTI_EEPROMS		1	/* more than one eeprom	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CONFIG_SYS_I2C_MULTI_EEPROMS		1	/* more than one eeprom	*/
 
 /* I2C SYSMON (LM75) */
 #define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
 #define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
-#define CFG_DTT_MAX_TEMP	70
-#define CFG_DTT_LOW_TEMP	-30
-#define CFG_DTT_HYSTERESIS	3
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
 
 #ifndef CONFIG_PCIE1
 /* RapidIO MMU */
 #ifdef CONFIG_TQM_BIGFLASH
-#define CFG_RIO_MEM_BASE	0xb0000000	/* base address		*/
-#define CFG_RIO_MEM_SIZE	0x10000000	/* 256M			*/
+#define CONFIG_SYS_RIO_MEM_BASE	0xb0000000	/* base address		*/
+#define CONFIG_SYS_RIO_MEM_SIZE	0x10000000	/* 256M			*/
 #else /* !CONFIG_TQM_BIGFLASH */
-#define CFG_RIO_MEM_BASE	0xc0000000	/* base address		*/
-#define CFG_RIO_MEM_SIZE	0x20000000	/* 512M			*/
+#define CONFIG_SYS_RIO_MEM_BASE	0xc0000000	/* base address		*/
+#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 512M			*/
 #endif /* CONFIG_TQM_BIGFLASH */
-#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
+#define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BASE
 #endif /* CONFIG_PCIE1 */
 
 /* NAND FLASH */
@@ -356,38 +367,37 @@
 #define	CONFIG_MTD_NAND_ECC_JFFS2	1	/* use JFFS2 ECC	*/
 
 /* address distance between chip selects */
-#define	CFG_NAND_SELECT_DEVICE	1
-#define	CFG_NAND_CS_DIST	0x200
-
-#define CFG_NAND_SIZE		0x8000
-#define CFG_NAND0_BASE		(CFG_CCSRBAR + 0x03010000)
-#define CFG_NAND1_BASE		(CFG_NAND0_BASE + CFG_NAND_CS_DIST)
-#define CFG_NAND2_BASE		(CFG_NAND1_BASE + CFG_NAND_CS_DIST)
-#define CFG_NAND3_BASE		(CFG_NAND2_BASE + CFG_NAND_CS_DIST)
-
-#define CFG_MAX_NAND_DEVICE     2	/* Max number of NAND devices	*/
-#define NAND_MAX_CHIPS		1
-
-#if (CFG_MAX_NAND_DEVICE == 1)
-#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
-#elif (CFG_MAX_NAND_DEVICE == 2)
-#define	CFG_NAND_QUIET_TEST	1
-#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \
-			     CFG_NAND1_BASE, \
+#define	CONFIG_SYS_NAND_SELECT_DEVICE	1
+#define	CONFIG_SYS_NAND_CS_DIST	0x200
+
+#define CONFIG_SYS_NAND_SIZE		0x8000
+#define CONFIG_SYS_NAND0_BASE		(CONFIG_SYS_CCSRBAR + 0x03010000)
+#define CONFIG_SYS_NAND1_BASE		(CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
+#define CONFIG_SYS_NAND2_BASE		(CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
+#define CONFIG_SYS_NAND3_BASE		(CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
+
+#define CONFIG_SYS_MAX_NAND_DEVICE     2	/* Max number of NAND devices	*/
+
+#if (CONFIG_SYS_MAX_NAND_DEVICE == 1)
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
+#elif (CONFIG_SYS_MAX_NAND_DEVICE == 2)
+#define	CONFIG_SYS_NAND_QUIET_TEST	1
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
+			     CONFIG_SYS_NAND1_BASE, \
 }
-#elif (CFG_MAX_NAND_DEVICE == 4)
-#define	CFG_NAND_QUIET_TEST	1
-#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \
-			     CFG_NAND1_BASE, \
-			     CFG_NAND2_BASE, \
-			     CFG_NAND3_BASE, \
+#elif (CONFIG_SYS_MAX_NAND_DEVICE == 4)
+#define	CONFIG_SYS_NAND_QUIET_TEST	1
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
+			     CONFIG_SYS_NAND1_BASE, \
+			     CONFIG_SYS_NAND2_BASE, \
+			     CONFIG_SYS_NAND3_BASE, \
 }
 #endif
 
 /* CS3 for NAND Flash */
-#define CFG_BR3_PRELIM		((CFG_NAND0_BASE & BR_BA) | BR_PS_8 | \
+#define CONFIG_SYS_BR3_PRELIM		((CONFIG_SYS_NAND0_BASE & BR_BA) | BR_PS_8 | \
 				 BR_MS_UPMB | BR_V)
-#define CFG_OR3_PRELIM		(P2SZ_TO_AM(CFG_NAND_SIZE) | OR_UPM_BI)
+#define CONFIG_SYS_OR3_PRELIM		(P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI)
 
 #define NAND_BIG_DELAY_US       25	/* max tR for Samsung devices	*/
 
@@ -397,17 +407,12 @@
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M			*/
-#define CFG_PCI1_IO_BASE	(CFG_CCSRBAR + 0x02000000)
-#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE	0x1000000	/*  16M			*/
-
-/* PCI view of System Memory */
-#define CFG_PCI_MEMORY_BUS	0x00000000
-#define CFG_PCI_MEMORY_PHYS	0x00000000
-#define CFG_PCI_MEMORY_SIZE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M			*/
+#define CONFIG_SYS_PCI1_IO_BASE	(CONFIG_SYS_CCSRBAR + 0x02000000)
+#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_SIZE	0x1000000	/*  16M			*/
 
 #ifdef CONFIG_PCIE1
 /*
@@ -415,17 +420,17 @@
  * Addresses are mapped 1-1.
  */
 #ifdef CONFIG_TQM_BIGFLASH
-#define CFG_PCIE1_MEM_BASE	0xb0000000
-#define CFG_PCIE1_MEM_SIZE	0x10000000      /* 512M                 */
-#define CFG_PCIE1_IO_BASE	0xaf000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xb0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000      /* 512M                 */
+#define CONFIG_SYS_PCIE1_IO_BASE	0xaf000000
 #else /* !CONFIG_TQM_BIGFLASH */
-#define CFG_PCIE1_MEM_BASE	0xc0000000
-#define CFG_PCIE1_MEM_SIZE	0x20000000      /* 512M                 */
-#define CFG_PCIE1_IO_BASE	0xef000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M                 */
+#define CONFIG_SYS_PCIE1_IO_BASE	0xef000000
 #endif /* CONFIG_TQM_BIGFLASH */
-#define CFG_PCIE1_MEM_PHYS	CFG_PCIE1_MEM_BASE
-#define CFG_PCIE1_IO_PHYS	CFG_PCIE1_IO_BASE
-#define CFG_PCIE1_IO_SIZE	0x1000000       /* 16M                  */
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_IO_PHYS	CONFIG_SYS_PCIE1_IO_BASE
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x1000000       /* 16M                  */
 #endif /* CONFIG_PCIE1 */
 
 #if defined(CONFIG_PCI)
@@ -436,7 +441,7 @@
 #undef CONFIG_TULIP
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
-#define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola			*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057	/* Motorola			*/
 
 #endif /* CONFIG_PCI */
 
@@ -530,29 +535,29 @@
 
 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
 #define CONFIG_ETHER_ON_FCC1
-#define CFG_CMXFCR_MASK1	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
+#define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
 				 CMXFCR_TF1CS_MSK)
-#define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
-#define CFG_CPMFCR_RAMTYPE	0
-#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+#define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 #endif
 
 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 #define CONFIG_ETHER_ON_FCC2
-#define CFG_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
+#define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
 				 CMXFCR_TF2CS_MSK)
-#define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
-#define CFG_CPMFCR_RAMTYPE	0
-#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+#define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 #endif
 
 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
 #define CONFIG_ETHER_ON_FCC3
-#define CFG_CMXFCR_MASK3	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
+#define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
 				 CMXFCR_TF3CS_MSK)
-#define CFG_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
-#define CFG_CPMFCR_RAMTYPE	0
-#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+#define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 #endif
 
 /*
@@ -565,13 +570,13 @@
 #else /* !CONFIG_TQM_FLASH_N_TYPE */
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) for env	*/
 #endif /* CONFIG_TQM_FLASH_N_TYPE */
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define	CONFIG_TIMESTAMP	/* Print image info with ts	*/
 
@@ -613,7 +618,9 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_SNTP
+#ifndef CONFIG_TQM8548_AG
 #define CONFIG_CMD_DATE
+#endif
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_MII
@@ -627,28 +634,28 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_LOAD_ADDR	0x2000000	/* default load address		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 
-#define CFG_PBSIZE	(CFG_CBSIZE + \
-			 sizeof(CFG_PROMPT) + 16)   /* Print Buf Size	*/
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks	*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+			 sizeof(CONFIG_SYS_PROMPT) + 16)   /* Print Buf Size	*/
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index 23d0dd6..8bd1fe0 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -83,7 +83,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -116,6 +116,7 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_NFS
@@ -127,32 +128,32 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -162,47 +163,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
@@ -212,7 +213,7 @@
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 #define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
 
@@ -231,16 +232,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -250,10 +251,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -262,9 +263,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -272,20 +273,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -293,7 +294,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -302,7 +303,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 
@@ -311,14 +312,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -331,28 +332,28 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -367,22 +368,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -393,19 +394,19 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 #ifndef	CONFIG_CAN_DRIVER
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 #endif	/* CONFIG_CAN_DRIVER */
 
@@ -436,34 +437,34 @@
  * 80 Mhz => 80.000.000 / Divider = 156
  */
 
-#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
-#define CFG_MAMR_PTA	98
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index e8d2ec4..ad2c71c 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -83,7 +83,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -116,6 +116,7 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_NFS
@@ -128,32 +129,32 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -163,46 +164,46 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
@@ -213,7 +214,7 @@
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 #define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
 
@@ -232,16 +233,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -251,10 +252,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -263,9 +264,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -273,20 +274,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -294,7 +295,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -303,7 +304,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 
@@ -312,14 +313,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -332,28 +333,28 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -368,22 +369,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -394,19 +395,19 @@
 #define	SDRAM_MAX_SIZE		0x08000000	/* max 128 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 #ifndef	CONFIG_CAN_DRIVER
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 #endif	/* CONFIG_CAN_DRIVER */
 
@@ -437,38 +438,38 @@
  * 80 Mhz => 80.000.000 / Divider = 156
  */
 
-#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
-#define CFG_MAMR_PTA	98
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 10 column SDRAM */
-#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_10COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index 74c815b..0a5180e 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -86,7 +86,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -119,6 +119,7 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_NFS
@@ -131,32 +132,32 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -166,47 +167,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
@@ -216,7 +217,7 @@
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 #define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
 
@@ -235,16 +236,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -254,10 +255,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -266,9 +267,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -276,20 +277,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -297,7 +298,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -306,7 +307,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 
@@ -315,14 +316,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -335,28 +336,28 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -371,22 +372,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -397,19 +398,19 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 #ifndef	CONFIG_CAN_DRIVER
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 #endif	/* CONFIG_CAN_DRIVER */
 
@@ -441,34 +442,34 @@
  * 100 Mhz => 100.000.000 / Divider = 195
  */
 
-#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
-#define CFG_MAMR_PTA	98
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index a5fc38d..ee6980c 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -86,7 +86,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -119,6 +119,7 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_NFS
@@ -131,32 +132,32 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -166,47 +167,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
@@ -217,7 +218,7 @@
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 #define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
 
@@ -236,16 +237,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -255,10 +256,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -267,9 +268,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -277,20 +278,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -298,7 +299,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -307,7 +308,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 
@@ -316,14 +317,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -336,28 +337,28 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -372,22 +373,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -398,19 +399,19 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 #ifndef	CONFIG_CAN_DRIVER
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 #endif	/* CONFIG_CAN_DRIVER */
 
@@ -442,34 +443,34 @@
  * 100 Mhz => 100.000.000 / Divider = 195
  */
 
-#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
-#define CFG_MAMR_PTA	98
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index 9e14d99..421a2d8 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -37,17 +37,17 @@
 #define CONFIG_TQM866M		1	/* ...on a TQM8xxM module	*/
 
 #define CONFIG_8xx_OSCLK		10000000	/*  10 MHz - PLL input clock	*/
-#define CFG_8xx_CPUCLK_MIN		15000000	/*  15 MHz - CPU minimum clock	*/
-#define CFG_8xx_CPUCLK_MAX		133000000	/* 133 MHz - CPU maximum clock	*/
+#define CONFIG_SYS_8xx_CPUCLK_MIN		15000000	/*  15 MHz - CPU minimum clock	*/
+#define CONFIG_SYS_8xx_CPUCLK_MAX		133000000	/* 133 MHz - CPU maximum clock	*/
 #define CONFIG_8xx_CPUCLK_DEFAULT	50000000	/*  50 MHz - CPU default clock	*/
 						/* (it will be used if there is no	*/
 						/* 'cpuclk' variable with valid value)	*/
 
-#undef CFG_MEASURE_CPUCLK			/* Measure real cpu clock	*/
+#undef CONFIG_SYS_MEASURE_CPUCLK			/* Measure real cpu clock	*/
 						/* (function measure_gclk()	*/
 						/* will be called)		*/
-#ifdef CFG_MEASURE_CPUCLK
-#define CFG_8XX_XIN		10000000	/* measure_gclk() needs this	*/
+#ifdef CONFIG_SYS_MEASURE_CPUCLK
+#define CONFIG_SYS_8XX_XIN		10000000	/* measure_gclk() needs this	*/
 #endif
 
 #define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
@@ -95,7 +95,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -107,8 +107,8 @@
 #undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
 
-#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
-#define CFG_I2C_SLAVE		0xFE
+#define CONFIG_SYS_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CONFIG_SYS_I2C_SLAVE		0xFE
 
 #ifdef CONFIG_SOFT_I2C
 /*
@@ -128,10 +128,10 @@
 #define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
 #endif	/* CONFIG_SOFT_I2C */
 
-#define CFG_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C256	*/
-#define CFG_I2C_EEPROM_ADDR_LEN 2		/* two byte address	*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C256	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2		/* two byte address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
 /*
  * BOOTP options
@@ -160,6 +160,7 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_NFS
@@ -172,32 +173,32 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -207,46 +208,46 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
@@ -257,7 +258,7 @@
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 #define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
 
@@ -276,16 +277,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -295,10 +296,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -307,9 +308,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -317,14 +318,14 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -333,7 +334,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 
@@ -342,14 +343,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -362,28 +363,28 @@
 #undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER 0
+#define CONFIG_SYS_DER 0
 
 /*
  * Init Memory Controller:
@@ -398,22 +399,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing: Default value of OR0 after reset
  */
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
 				 OR_SCY_15_CLK | OR_TRLX)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -424,19 +425,19 @@
 #define SDRAM_MAX_SIZE		(256 << 20)	/* max 256 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 #ifndef CONFIG_CAN_DRIVER
-#define CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 #endif	/* CONFIG_CAN_DRIVER */
 
@@ -447,48 +448,48 @@
  * 4	Number of refresh cycles per period
  * 64	Refresh cycle in ms per number of rows
  */
-#define CFG_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))
 
 /*
  * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
  *
  *                        CPUclock(MHz) * 31.2
- * CFG_MAMR_PTA = -----------------------------------     with DFBRG = 0
+ * CONFIG_SYS_MAMR_PTA = -----------------------------------     with DFBRG = 0
  *                2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
  *
- * CPU clock =  15 MHz:  CFG_MAMR_PTA =  29   ->  4 * 7.73 us
- * CPU clock =  50 MHz:  CFG_MAMR_PTA =  97   ->  4 * 7.76 us
- * CPU clock =  66 MHz:  CFG_MAMR_PTA = 128   ->  4 * 7.75 us
- * CPU clock = 133 MHz:  CFG_MAMR_PTA = 255   ->  4 * 7.67 us
+ * CPU clock =  15 MHz:  CONFIG_SYS_MAMR_PTA =  29   ->  4 * 7.73 us
+ * CPU clock =  50 MHz:  CONFIG_SYS_MAMR_PTA =  97   ->  4 * 7.76 us
+ * CPU clock =  66 MHz:  CONFIG_SYS_MAMR_PTA = 128   ->  4 * 7.75 us
+ * CPU clock = 133 MHz:  CONFIG_SYS_MAMR_PTA = 255   ->  4 * 7.67 us
  *
  * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
  * be met also in the default configuration, i.e. if environment variable
  * 'cpuclk' is not set.
  */
-#define CFG_MAMR_PTA		97
+#define CONFIG_SYS_MAMR_PTA		97
 
 /*
  * Memory Periodic Timer Prescaler Register (MPTPR) values.
  */
 /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16
 /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 10 column SDRAM */
-#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_10COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
index 66f4a98..4c80bad 100644
--- a/include/configs/TQM885D.h
+++ b/include/configs/TQM885D.h
@@ -40,8 +40,8 @@
 #define CONFIG_TQM885D		1	/* ...on a TQM88D module	*/
 
 #define CONFIG_8xx_OSCLK		10000000	/*  10 MHz - PLL input clock	*/
-#define CFG_8xx_CPUCLK_MIN		15000000	/*  15 MHz - CPU minimum clock	*/
-#define CFG_8xx_CPUCLK_MAX		133000000	/* 133 MHz - CPU maximum clock	*/
+#define CONFIG_SYS_8xx_CPUCLK_MIN		15000000	/*  15 MHz - CPU minimum clock	*/
+#define CONFIG_SYS_8xx_CPUCLK_MAX		133000000	/* 133 MHz - CPU maximum clock	*/
 #define CONFIG_8xx_CPUCLK_DEFAULT	66000000	/*  66 MHz - CPU default clock	*/
 						/* (it will be used if there is no	*/
 						/* 'cpuclk' variable with valid value)	*/
@@ -89,7 +89,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -101,8 +101,8 @@
 #undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
 
-#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
-#define CFG_I2C_SLAVE		0xFE
+#define CONFIG_SYS_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CONFIG_SYS_I2C_SLAVE		0xFE
 
 #ifdef CONFIG_SOFT_I2C
 /*
@@ -122,13 +122,13 @@
 #define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
 #endif	/* CONFIG_SOFT_I2C */
 
-#define CFG_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C??	*/
-#define CFG_I2C_EEPROM_ADDR_LEN 2		/* two byte address	*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C??	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2		/* two byte address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
 # define CONFIG_RTC_DS1337 1
-# define CFG_I2C_RTC_ADDR 0x68
+# define CONFIG_SYS_I2C_RTC_ADDR 0x68
 
 /*
  * BOOTP options
@@ -157,6 +157,7 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_MII
@@ -167,34 +168,34 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0300000	/* 1 ... 3 MB in DRAM	*/
-#define CFG_ALT_MEMTEST				/* alternate, more extensive
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0300000	/* 1 ... 3 MB in DRAM	*/
+#define CONFIG_SYS_ALT_MEMTEST				/* alternate, more extensive
 						   memory test.*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Enable loopw command.
@@ -209,47 +210,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
@@ -263,16 +264,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -282,10 +283,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -294,9 +295,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -304,14 +305,14 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -320,7 +321,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 
@@ -329,14 +330,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -349,28 +350,28 @@
 #undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER 0
+#define CONFIG_SYS_DER 0
 
 /*
  * Init Memory Controller:
@@ -385,22 +386,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing: Default value of OR0 after reset
  */
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
 				 OR_SCY_6_CLK | OR_TRLX)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -411,19 +412,19 @@
 #define SDRAM_MAX_SIZE		(256 << 20)	/* max 256 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 #ifndef CONFIG_CAN_DRIVER
-#define CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 #endif	/* CONFIG_CAN_DRIVER */
 
@@ -434,48 +435,48 @@
  * 4	Number of refresh cycles per period
  * 64	Refresh cycle in ms per number of rows
  */
-#define CFG_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))
 
 /*
  * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
  *
  *                        CPUclock(MHz) * 31.2
- * CFG_MAMR_PTA = -----------------------------------     with DFBRG = 0
+ * CONFIG_SYS_MAMR_PTA = -----------------------------------     with DFBRG = 0
  *                2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
  *
- * CPU clock =  15 MHz:  CFG_MAMR_PTA =  29   ->  4 * 7.73 us
- * CPU clock =  50 MHz:  CFG_MAMR_PTA =  97   ->  4 * 7.76 us
- * CPU clock =  66 MHz:  CFG_MAMR_PTA = 128   ->  4 * 7.75 us
- * CPU clock = 133 MHz:  CFG_MAMR_PTA = 255   ->  4 * 7.67 us
+ * CPU clock =  15 MHz:  CONFIG_SYS_MAMR_PTA =  29   ->  4 * 7.73 us
+ * CPU clock =  50 MHz:  CONFIG_SYS_MAMR_PTA =  97   ->  4 * 7.76 us
+ * CPU clock =  66 MHz:  CONFIG_SYS_MAMR_PTA = 128   ->  4 * 7.75 us
+ * CPU clock = 133 MHz:  CONFIG_SYS_MAMR_PTA = 255   ->  4 * 7.67 us
  *
  * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
  * be met also in the default configuration, i.e. if environment variable
  * 'cpuclk' is not set.
  */
-#define CFG_MAMR_PTA		128
+#define CONFIG_SYS_MAMR_PTA		128
 
 /*
  * Memory Periodic Timer Prescaler Register (MPTPR) values.
  */
 /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16
 /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 10 column SDRAM */
-#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_10COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
@@ -496,7 +497,7 @@
 #define CONFIG_ETHER_ON_FEC2		/* ... for FEC2 */
 
 #if defined(CONFIG_CMD_MII)
-#define CFG_DISCOVER_PHY
+#define CONFIG_SYS_DISCOVER_PHY
 #define CONFIG_MII_INIT	1
 #endif
 
diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h
index 19b3be7..9a75848 100644
--- a/include/configs/Total5200.h
+++ b/include/configs/Total5200.h
@@ -43,7 +43,7 @@
 #define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
 #define CONFIG_TOTAL5200	1	/* ... on Total5200 board */
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
@@ -55,7 +55,7 @@
  */
 #define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*
  * Video console
@@ -95,7 +95,7 @@
 #define CONFIG_NET_MULTI	1
 #define CONFIG_MII		1
 #define CONFIG_EEPRO100		1
-#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
 #define CONFIG_NS8382X		1
 
 #else	/* MGT5100 */
@@ -141,7 +141,7 @@
 
 
 #if (TEXT_BASE == 0xFE000000)		/* Boot low */
-#   define CFG_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT		1
 #endif
 
 /*
@@ -180,54 +180,54 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 #endif
 
 /*
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		1	/* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_MODULE		1	/* Select I2C module #1 or #2 */
 
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration
  */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
 
 /*
  * Flash configuration
  */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
 #if CONFIG_TOTAL5200_REV==2
-#   define CFG_MAX_FLASH_BANKS	3	/* max num of flash banks */
-#   define CFG_FLASH_BANKS_LIST { CFG_CS5_START, CFG_CS4_START, CFG_BOOTCS_START }
+#   define CONFIG_SYS_MAX_FLASH_BANKS	3	/* max num of flash banks */
+#   define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS5_START, CONFIG_SYS_CS4_START, CONFIG_SYS_BOOTCS_START }
 #else
-#   define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks  */
-#   define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
+#   define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks  */
+#   define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
 #endif
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
 
 #if CONFIG_TOTAL5200_REV==1
-#   define CFG_FLASH_BASE	0xFE000000
-#   define CFG_FLASH_SIZE	0x02000000
+#   define CONFIG_SYS_FLASH_BASE	0xFE000000
+#   define CONFIG_SYS_FLASH_SIZE	0x02000000
 #elif CONFIG_TOTAL5200_REV==2
-#   define CFG_FLASH_BASE	0xFA000000
-#   define CFG_FLASH_SIZE	0x06000000
+#   define CONFIG_SYS_FLASH_BASE	0xFA000000
+#   define CONFIG_SYS_FLASH_SIZE	0x06000000
 #endif /* CONFIG_TOTAL5200_REV */
 
-#if defined(CFG_LOWBOOT)
+#if defined(CONFIG_SYS_LOWBOOT)
 #   define CONFIG_ENV_ADDR		0xFE040000
-#else	/* CFG_LOWBOOT */
+#else	/* CONFIG_SYS_LOWBOOT */
 #   define CONFIG_ENV_ADDR		0xFFF40000
-#endif	/* CFG_LOWBOOT */
+#endif	/* CONFIG_SYS_LOWBOOT */
 
 /*
  * Environment settings
@@ -240,34 +240,35 @@
 /*
  * Memory map
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
-#define CFG_MBAR		0xF0000000	/*   64 kB */
-#define CFG_FPGA_BASE		0xF0010000	/*   64 kB */
-#define CFG_CPLD_BASE		0xF0020000	/*   64 kB */
-#define CFG_LCD_BASE		0xF1000000	/* 4096 kB */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xF0000000	/*   64 kB */
+#define CONFIG_SYS_FPGA_BASE		0xF0010000	/*   64 kB */
+#define CONFIG_SYS_CPLD_BASE		0xF0020000	/*   64 kB */
+#define CONFIG_SYS_LCD_BASE		0xF1000000	/* 4096 kB */
 
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_SEVENWIRE
 /* dummy, 7-wire FEC does not have phy address */
 #define CONFIG_PHY_ADDR		0x00
 
@@ -293,32 +294,32 @@
  * PSC1:  reset default, changed in AC'97 driver                 000
  *
  */
-#define CFG_GPS_PORT_CONFIG	0x00000C10
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x00000C10
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 
@@ -326,11 +327,11 @@
  * Various low-level settings
  */
 #if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 #else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
 #endif
 
 #if defined (CONFIG_MGT5100)
@@ -338,43 +339,43 @@
 #endif
 
 #if CONFIG_TOTAL5200_REV==1
-#   define CFG_BOOTCS_START	CFG_FLASH_BASE
-#   define CFG_BOOTCS_SIZE	0x02000000	/* 32 MB */
-#   define CFG_BOOTCS_CFG	0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
-#   define CFG_CS0_START	CFG_FLASH_BASE
-#   define CFG_CS0_SIZE		0x02000000	/* 32 MB */
+#   define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#   define CONFIG_SYS_BOOTCS_SIZE	0x02000000	/* 32 MB */
+#   define CONFIG_SYS_BOOTCS_CFG	0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
+#   define CONFIG_SYS_CS0_START	CONFIG_SYS_FLASH_BASE
+#   define CONFIG_SYS_CS0_SIZE		0x02000000	/* 32 MB */
 #else
-#   define CFG_BOOTCS_START	(CFG_CS4_START + CFG_CS4_SIZE)
-#   define CFG_BOOTCS_SIZE	0x02000000	/* 32 MB */
-#   define CFG_BOOTCS_CFG	0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
-#   define CFG_CS4_START	(CFG_CS5_START + CFG_CS5_SIZE)
-#   define CFG_CS4_SIZE		0x02000000	/* 32 MB */
-#   define CFG_CS4_CFG		0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
-#   define CFG_CS5_START	CFG_FLASH_BASE
-#   define CFG_CS5_SIZE		0x02000000	/* 32 MB */
-#   define CFG_CS5_CFG		0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
+#   define CONFIG_SYS_BOOTCS_START	(CONFIG_SYS_CS4_START + CONFIG_SYS_CS4_SIZE)
+#   define CONFIG_SYS_BOOTCS_SIZE	0x02000000	/* 32 MB */
+#   define CONFIG_SYS_BOOTCS_CFG	0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
+#   define CONFIG_SYS_CS4_START	(CONFIG_SYS_CS5_START + CONFIG_SYS_CS5_SIZE)
+#   define CONFIG_SYS_CS4_SIZE		0x02000000	/* 32 MB */
+#   define CONFIG_SYS_CS4_CFG		0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
+#   define CONFIG_SYS_CS5_START	CONFIG_SYS_FLASH_BASE
+#   define CONFIG_SYS_CS5_SIZE		0x02000000	/* 32 MB */
+#   define CONFIG_SYS_CS5_CFG		0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
 #endif
 
-#define CFG_CS1_START		CFG_FPGA_BASE
-#define CFG_CS1_SIZE		0x00010000	/* 64 kB */
-#define CFG_CS1_CFG		0x0019FF00	/* 25WS, MX, AL, AA, CE, AS_25, DS_32 */
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_FPGA_BASE
+#define CONFIG_SYS_CS1_SIZE		0x00010000	/* 64 kB */
+#define CONFIG_SYS_CS1_CFG		0x0019FF00	/* 25WS, MX, AL, AA, CE, AS_25, DS_32 */
 
-#define CFG_CS2_START		CFG_LCD_BASE
-#define CFG_CS2_SIZE		0x00400000	/* 4096 kB */
-#define CFG_CS2_CFG		0x0032FD0C	/* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */
+#define CONFIG_SYS_CS2_START		CONFIG_SYS_LCD_BASE
+#define CONFIG_SYS_CS2_SIZE		0x00400000	/* 4096 kB */
+#define CONFIG_SYS_CS2_CFG		0x0032FD0C	/* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */
 
 #if CONFIG_TOTAL5200_REV==1
-#   define CFG_CS3_START	CFG_CPLD_BASE
-#   define CFG_CS3_SIZE		0x00010000	/* 64 kB */
-#   define CFG_CS3_CFG		0x000ADF00	/* 10WS, MX, AL, CE, AS_25, DS_32 */
+#   define CONFIG_SYS_CS3_START	CONFIG_SYS_CPLD_BASE
+#   define CONFIG_SYS_CS3_SIZE		0x00010000	/* 64 kB */
+#   define CONFIG_SYS_CS3_CFG		0x000ADF00	/* 10WS, MX, AL, CE, AS_25, DS_32 */
 #else
-#   define CFG_CS3_START	CFG_CPLD_BASE
-#   define CFG_CS3_SIZE		0x00010000	/* 64 kB */
-#   define CFG_CS3_CFG		0x000AD800	/* 10WS, MX, AL, CE, AS_24, DS_8 */
+#   define CONFIG_SYS_CS3_START	CONFIG_SYS_CPLD_BASE
+#   define CONFIG_SYS_CS3_SIZE		0x00010000	/* 64 kB */
+#   define CONFIG_SYS_CS3_CFG		0x000AD800	/* 10WS, MX, AL, CE, AS_24, DS_8 */
 #endif
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
 
 /*-----------------------------------------------------------------------
  * USB stuff
@@ -396,23 +397,23 @@
 #define	CONFIG_IDE_RESET		/* reset for ide supported	*/
 #define CONFIG_IDE_PREINIT
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(0x0060)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005C)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
 
 /* Interval between registers                                                */
-#define CFG_ATA_STRIDE          4
+#define CONFIG_SYS_ATA_STRIDE          4
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index aeb649e..d9bcf6b 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -36,7 +36,6 @@
 #define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
 #define	CONFIG_S3C2410		1	/* in a SAMSUNG S3C2410 SoC     */
 #define CONFIG_VCMA9		1	/* on a MPL VCMA9 Board  */
-#define LITTLEENDIAN		1	/* used by usb_ohci.c		*/
 
 /* input clock of PLL */
 #define CONFIG_SYS_CLK_FREQ	12000000/* VCMA9 has 12MHz input clock	*/
@@ -76,35 +75,35 @@
 #define CONFIG_CMD_BSP
 
 
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 /***********************************************************
  * I2C stuff:
  * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
  * address 0x50 with 16bit addressing
  ***********************************************************/
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
-#define CFG_I2C_SPEED		100000	/* I2C speed */
-#define CFG_I2C_SLAVE		0x7F	/* I2C slave addr */
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed */
+#define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave addr */
 
-#define CFG_I2C_EEPROM_ADDR	0x50
-#define CFG_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
 #define CONFIG_ENV_OFFSET		0x000	/* environment starts at offset 0 */
 #define CONFIG_ENV_SIZE		0x800	/* 2KB should be more than enough */
 
-#undef CFG_I2C_EEPROM_ADDR_OVERFLOW
-#define CFG_EEPROM_PAGE_WRITE_BITS 6	/* 64 bytes page write mode on 24C256 */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6	/* 64 bytes page write mode on 24C256 */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 
 /*
  * Size of malloc() pool
  */
 /*#define CONFIG_MALLOC_SIZE	(CONFIG_ENV_SIZE + 128*1024)*/
-#define CFG_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
 
-#define CFG_MONITOR_LEN		(256 * 1024)
-#define CFG_MALLOC_LEN		(1024 * 1024)	/* BUNZIP2 needs a lot of RAM */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* BUNZIP2 needs a lot of RAM */
 
 /*
  * Hardware drivers
@@ -129,7 +128,7 @@
 #define CONFIG_DOS_PARTITION	1
 
 /* Enable needed helper functions */
-#define CFG_DEVICE_DEREGISTER		/* needs device_deregister */
+#define CONFIG_SYS_DEVICE_DEREGISTER		/* needs device_deregister */
 
 /************************************************************
  * RTC
@@ -160,28 +159,28 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"VCMA9 # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"VCMA9 # "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x30000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x30F80000	/* 15.5 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x30000000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x30F80000	/* 15.5 MB in DRAM	*/
 
-#define CFG_ALT_MEMTEST
-#define	CFG_LOAD_ADDR		0x30800000	/* default load address	*/
+#define CONFIG_SYS_ALT_MEMTEST
+#define	CONFIG_SYS_LOAD_ADDR		0x30800000	/* default load address	*/
 
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
 /* we configure PWM Timer 4 to 1us ~ 1MHz */
-/*#define	CFG_HZ			1000000 */
-#define	CFG_HZ			1562500
+/*#define	CONFIG_SYS_HZ			1000000 */
+#define	CONFIG_SYS_HZ			1562500
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /* support BZIP2 compression */
 #define CONFIG_BZIP2		1
@@ -211,7 +210,7 @@
 #define PHYS_SDRAM_1		0x30000000 /* SDRAM Bank #1 */
 #define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
@@ -222,21 +221,21 @@
 #define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */
 #endif
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
 #ifdef CONFIG_AMD_LV800
 #define PHYS_FLASH_SIZE		0x00100000 /* 1MB */
-#define CFG_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
+#define CONFIG_SYS_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
 #endif
 #ifdef CONFIG_AMD_LV400
 #define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
-#define CFG_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x070000) /* addr of environment */
+#define CONFIG_SYS_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
 #endif
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #if 0
 #define	CONFIG_ENV_IS_IN_FLASH	1
@@ -244,8 +243,8 @@
 #endif
 
 
-#define CFG_JFFS2_FIRST_BANK	0
-#define CFG_JFFS2_NUM_BANKS	1
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
 
 #define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
 
@@ -255,7 +254,7 @@
 #if defined(CONFIG_CMD_NAND)
 
 #define CONFIG_NAND_LEGACY
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
 #define SECTORSIZE 512
 
 #define ADDR_COLUMN 1
@@ -264,7 +263,6 @@
 
 #define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
 
 #define NAND_WAIT_READY(nand)	NF_WaitRB()
 
diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
index d5c0a5e..38a1d0d 100644
--- a/include/configs/VOH405.h
+++ b/include/configs/VOH405.h
@@ -50,11 +50,12 @@
 
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_NET_MULTI	1
 #undef  CONFIG_HAS_ETH1
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
@@ -99,76 +100,74 @@
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
+#define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
-#define CFG_BASE_BAUD       691200
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD       691200
 #define CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*-----------------------------------------------------------------------
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
-#define NAND_MAX_CHIPS          1
-#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
 #define NAND_BIG_DELAY_US	25
 
-#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
-#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
-#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
-#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
+#define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
-#define CFG_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
-#define CFG_NAND_QUIET          1
+#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
+#define CONFIG_SYS_NAND_QUIET          1
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -187,15 +186,15 @@
 
 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
@@ -205,62 +204,62 @@
 #undef	CONFIG_IDE_LED			/* no led for ide supported	*/
 #define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
 
-#define CFG_IDE_MAXBUS		2		/* max. 2 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		2		/* max. 2 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR	0xF0100000
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#define CFG_ATA_IDE1_OFFSET	0x0010
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0x0010
 
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFF80000
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(2 * 1024*1024)	/* Reserve 2 MB for malloc()	*/
-
-#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CFG_RAMBOOT		1
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFF80000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(2 * 1024*1024)	/* Reserve 2 MB for malloc()	*/
+
+#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CONFIG_SYS_RAMBOOT		1
 #else
-# undef CFG_RAMBOOT
+# undef CONFIG_SYS_RAMBOOT
 #endif
 
 /*-----------------------------------------------------------------------
@@ -271,28 +270,27 @@
 #define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */
 
-#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
-#define CFG_EEPROM_WREN         1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
+#define CONFIG_SYS_EEPROM_WREN         1
 
 /* CAT24WC32/64... */
-#define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
-#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x01
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
 					/* 32 byte page write mode using*/
 					/* last 5 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
@@ -303,79 +301,79 @@
 #define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
 #define RTC_BA		0xF0000500	    /* RTC Base Address			*/
 #define VGA_BA		0xF1000000	    /* Epson VGA Base Address		*/
-#define CFG_NAND_BASE	0xF4000000	    /* NAND FLASH Base Address		*/
+#define CONFIG_SYS_NAND_BASE	0xF4000000	    /* NAND FLASH Base Address		*/
 
 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x92015480
-/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+/*#define CONFIG_SYS_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
-#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 4 (Epson VGA) initialization					*/
-#define CFG_EBC_PB4AP	0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
-#define CFG_EBC_PB4CR	VGA_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB4AP	0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
+#define CONFIG_SYS_EBC_PB4CR	VGA_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
 
 /*-----------------------------------------------------------------------
  * LCD Setup
  */
 
-#define CFG_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
-#define CFG_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
-#define CFG_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
-#define CFG_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */
+#define CONFIG_SYS_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
+#define CONFIG_SYS_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
+#define CONFIG_SYS_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
+#define CONFIG_SYS_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */
 
-#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20)
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20)
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
 
-#define CFG_FPGA_BASE_ADDR 0xF0100100	    /* FPGA internal Base Address	*/
+#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100	    /* FPGA internal Base Address	*/
 
 /* FPGA internal regs */
-#define CFG_FPGA_CTRL		0x000
+#define CONFIG_SYS_FPGA_CTRL		0x000
 
 /* FPGA Control Reg */
-#define CFG_FPGA_CTRL_CF_RESET	0x0001
-#define CFG_FPGA_CTRL_WDI	0x0002
-#define CFG_FPGA_CTRL_PS2_RESET 0x0020
+#define CONFIG_SYS_FPGA_CTRL_CF_RESET	0x0001
+#define CONFIG_SYS_FPGA_CTRL_WDI	0x0002
+#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
 
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
 
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup (PPC405EP specific)
@@ -389,20 +387,20 @@
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
  */
-#define CFG_GPIO0_OSRH		0x00000550
-#define CFG_GPIO0_OSRL		0x00000110
-#define CFG_GPIO0_ISR1H		0x00000000
-#define CFG_GPIO0_ISR1L		0x15555440
-#define CFG_GPIO0_TSRH		0x00000000
-#define CFG_GPIO0_TSRL		0x00000000
-#define CFG_GPIO0_TCR		0x777E0017
-
-#define CFG_DUART_RST		(0x80000000 >> 14)
-#define CFG_LCD_ENDIAN		(0x80000000 >> 7)
-#define CFG_IIC_ON		(0x80000000 >> 8)
-#define CFG_LCD0_RST		(0x80000000 >> 30)
-#define CFG_LCD1_RST		(0x80000000 >> 31)
-#define CFG_EEPROM_WP		(0x80000000 >> 0)
+#define CONFIG_SYS_GPIO0_OSRH		0x00000550
+#define CONFIG_SYS_GPIO0_OSRL		0x00000110
+#define CONFIG_SYS_GPIO0_ISR1H		0x00000000
+#define CONFIG_SYS_GPIO0_ISR1L		0x15555440
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0x777E0017
+
+#define CONFIG_SYS_DUART_RST		(0x80000000 >> 14)
+#define CONFIG_SYS_LCD_ENDIAN		(0x80000000 >> 7)
+#define CONFIG_SYS_IIC_ON		(0x80000000 >> 8)
+#define CONFIG_SYS_LCD0_RST		(0x80000000 >> 30)
+#define CONFIG_SYS_LCD1_RST		(0x80000000 >> 31)
+#define CONFIG_SYS_EEPROM_WP		(0x80000000 >> 0)
 
 /*
  * Internal Definitions
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index b952e0c..db00c65 100644
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -48,11 +48,12 @@
 
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_NET_MULTI	1
 #undef  CONFIG_HAS_ETH1
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
@@ -95,97 +96,96 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
 #undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*
  * FLASH organization
  */
 #define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-
-#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CFG_RAMBOOT		1
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CONFIG_SYS_RAMBOOT		1
 #else
-# undef CFG_RAMBOOT
+# undef CONFIG_SYS_RAMBOOT
 #endif
 
 /*
@@ -196,25 +196,24 @@
 #define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */
 
-#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
 
 /*
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 /*
  * External Bus Controller (EBC) Setup
@@ -222,41 +221,41 @@
 #define CAN_BA		0xF0000000	    /* CAN Base Address			*/
 
 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
 /*
  * FPGA stuff
  */
-#define CFG_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
-#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
+#define CONFIG_SYS_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
+#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
-#define CFG_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
-#define CFG_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
-#define CFG_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
 
 /*
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
 
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Definitions for GPIO setup (PPC405EP specific)
@@ -274,13 +273,13 @@
 /* GPIO Output:		OSR=00, ISR=00, TSR=00, TCR=1 */
 /* Alt. Funtion Input:	OSR=00, ISR=01, TSR=00, TCR=0 */
 /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
-#define CFG_GPIO0_OSRH		0x40000500  /*	0 ... 15 */
-#define CFG_GPIO0_OSRL		0x00000110  /* 16 ... 31 */
-#define CFG_GPIO0_ISR1H		0x00000000  /*	0 ... 15 */
-#define CFG_GPIO0_ISR1L		0x14000045  /* 16 ... 31 */
-#define CFG_GPIO0_TSRH		0x00000000  /*	0 ... 15 */
-#define CFG_GPIO0_TSRL		0x00000000  /* 16 ... 31 */
-#define CFG_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */
+#define CONFIG_SYS_GPIO0_OSRH		0x40000500  /*	0 ... 15 */
+#define CONFIG_SYS_GPIO0_OSRL		0x00000110  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_ISR1H		0x00000000  /*	0 ... 15 */
+#define CONFIG_SYS_GPIO0_ISR1L		0x14000045  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000  /*	0 ... 15 */
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */
 
 /*
  * Internal Definitions
diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h
index f72da78..5f9a17f 100644
--- a/include/configs/VoVPN-GW.h
+++ b/include/configs/VoVPN-GW.h
@@ -82,10 +82,10 @@
 #define CONFIG_LOADS_ECHO		1
 
 /* don't allow baudrate change	*/
-#undef	CFG_LOADS_BAUD_CHANGE
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
 
 /* supported baudrates */
-#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * select ethernet configuration
@@ -107,32 +107,32 @@
 #define	CONFIG_ETHER_INDEX		1
 
 /* Marvell Switch SMI base addr */
-#define CFG_PHY_ADDR			0x10
+#define CONFIG_SYS_PHY_ADDR			0x10
 
 /* FCC1 RMII REFCLK is CLK10 */
-#define CFG_CMXFCR_VALUE		CMXFCR_TF1CS_CLK10
-#define CFG_CMXFCR_MASK			(CMXFCR_FC1|CMXFCR_TF1CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE		CMXFCR_TF1CS_CLK10
+#define CONFIG_SYS_CMXFCR_MASK			(CMXFCR_FC1|CMXFCR_TF1CS_MSK)
 
 /* BDs and buffers on 60x bus */
-#define CFG_CPMFCR_RAMTYPE		0
+#define CONFIG_SYS_CPMFCR_RAMTYPE		0
 
 /* Local Protect, Full duplex, Flowcontrol, RMII */
-#define CFG_FCC_PSMR			(FCC_PSMR_LPB|FCC_PSMR_FDE|\
+#define CONFIG_SYS_FCC_PSMR			(FCC_PSMR_LPB|FCC_PSMR_FDE|\
 					 FCC_PSMR_FCE|FCC_PSMR_RMII)
 
 /* bit-bang MII PHY management	*/
 #define CONFIG_BITBANGMII
 
 #define MDIO_PORT			1		/* Port B */
-#define CFG_MDIO_PIN			0x00002000	/* PB18 */
-#define CFG_MDC_PIN			0x00001000	/* PB19 */
-#define MDIO_ACTIVE			(iop->pdir |=  CFG_MDIO_PIN)
-#define MDIO_TRISTATE			(iop->pdir &= ~CFG_MDIO_PIN)
-#define MDIO_READ			((iop->pdat &  CFG_MDIO_PIN) != 0)
-#define MDIO(bit)			if(bit) iop->pdat |=  CFG_MDIO_PIN; \
-					else	iop->pdat &= ~CFG_MDIO_PIN
-#define MDC(bit)			if(bit) iop->pdat |=  CFG_MDC_PIN; \
-					else	iop->pdat &= ~CFG_MDC_PIN
+#define CONFIG_SYS_MDIO_PIN			0x00002000	/* PB18 */
+#define CONFIG_SYS_MDC_PIN			0x00001000	/* PB19 */
+#define MDIO_ACTIVE			(iop->pdir |=  CONFIG_SYS_MDIO_PIN)
+#define MDIO_TRISTATE			(iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
+#define MDIO_READ			((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
+#define MDIO(bit)			if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
+					else	iop->pdat &= ~CONFIG_SYS_MDIO_PIN
+#define MDC(bit)			if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
+					else	iop->pdat &= ~CONFIG_SYS_MDC_PIN
 #define MIIDELAY			udelay(1)
 
 #endif
@@ -154,7 +154,7 @@
 #define CONFIG_CMD_BDI
 #define CONFIG_CMD_CONSOLE
 #define CONFIG_CMD_ECHO
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_IMI
 #define CONFIG_CMD_IMLS
@@ -209,58 +209,58 @@
  */
 
 /* undef to save memory */
-#define	CFG_LONGHELP
+#define	CONFIG_SYS_LONGHELP
 
 /* monitor command prompt */
-#define	CFG_PROMPT			"=> "
+#define	CONFIG_SYS_PROMPT			"=> "
 
 /* console i/o buffer size */
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE			1024
+#define	CONFIG_SYS_CBSIZE			1024
 #else
-#define	CFG_CBSIZE			256
+#define	CONFIG_SYS_CBSIZE			256
 #endif
 
 /* print buffer size */
-#define	CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define	CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 
 /* max number of command args */
-#define	CFG_MAXARGS			16
+#define	CONFIG_SYS_MAXARGS			16
 
 /* boot argument buffer size */
-#define CFG_BARGSIZE			CFG_CBSIZE
+#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
 
 /* memtest works on */
-#define CFG_MEMTEST_START		0x00100000
+#define CONFIG_SYS_MEMTEST_START		0x00100000
 /* 1 ... 15 MB in DRAM */
-#define CFG_MEMTEST_END			0x00f00000
+#define CONFIG_SYS_MEMTEST_END			0x00f00000
 /* full featured memtest */
-#define CFG_ALT_MEMTEST
+#define CONFIG_SYS_ALT_MEMTEST
 
 /* default load address */
-#define	CFG_LOAD_ADDR			0x00100000
+#define	CONFIG_SYS_LOAD_ADDR			0x00100000
 
 /* decrementer freq: 1 ms ticks	*/
-#define	CFG_HZ				1000
+#define	CONFIG_SYS_HZ				1000
 
 /* configure flash */
-#define CFG_FLASH_BASE			0xff800000
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		64
-#define CFG_FLASH_SIZE			8
-#undef	CFG_FLASH_16BIT
-#define CFG_FLASH_ERASE_TOUT		240000
-#define CFG_FLASH_WRITE_TOUT		500
-#define CFG_FLASH_LOCK_TOUT		500
-#define CFG_FLASH_UNLOCK_TOUT		10000
-#define CFG_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_BASE			0xff800000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		64
+#define CONFIG_SYS_FLASH_SIZE			8
+#undef	CONFIG_SYS_FLASH_16BIT
+#define CONFIG_SYS_FLASH_ERASE_TOUT		240000
+#define CONFIG_SYS_FLASH_WRITE_TOUT		500
+#define CONFIG_SYS_FLASH_LOCK_TOUT		500
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT		10000
+#define CONFIG_SYS_FLASH_PROTECTION
 
 /* monitor in flash */
-#define CFG_MONITOR_OFFSET		0x00700000
+#define CONFIG_SYS_MONITOR_OFFSET		0x00700000
 
 /* environment in flash */
 #define CONFIG_ENV_IS_IN_FLASH		1
-#define CONFIG_ENV_ADDR			(CFG_FLASH_BASE + 0x00020000)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x00020000)
 #define CONFIG_ENV_SIZE			0x00020000
 #define CONFIG_ENV_SECT_SIZE		0x00020000
 
@@ -270,52 +270,52 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ			(8 << 20)
+#define CONFIG_SYS_BOOTMAPSZ			(8 << 20)
 
 /* hard reset configuration words */
 #ifdef	CONFIG_CLKIN_66MHz
-#define CFG_HRCW_MASTER			0x04643050
+#define CONFIG_SYS_HRCW_MASTER			0x04643050
 #else
 #error NO HRCW FOR 100MHZ SPECIFIED !!!
 #endif
-#define CFG_HRCW_SLAVE1			0x00000000
-#define CFG_HRCW_SLAVE2			0x00000000
-#define CFG_HRCW_SLAVE3			0x00000000
-#define CFG_HRCW_SLAVE4			0x00000000
-#define CFG_HRCW_SLAVE5			0x00000000
-#define CFG_HRCW_SLAVE6			0x00000000
-#define CFG_HRCW_SLAVE7			0x00000000
+#define CONFIG_SYS_HRCW_SLAVE1			0x00000000
+#define CONFIG_SYS_HRCW_SLAVE2			0x00000000
+#define CONFIG_SYS_HRCW_SLAVE3			0x00000000
+#define CONFIG_SYS_HRCW_SLAVE4			0x00000000
+#define CONFIG_SYS_HRCW_SLAVE5			0x00000000
+#define CONFIG_SYS_HRCW_SLAVE6			0x00000000
+#define CONFIG_SYS_HRCW_SLAVE7			0x00000000
 
 /* internal memory mapped register */
-#define CFG_IMMR			0xF0000000
+#define CONFIG_SYS_IMMR			0xF0000000
 
 /* definitions for initial stack pointer and data area (in DPRAM) */
-#define CFG_INIT_RAM_ADDR		CFG_IMMR
-#define CFG_INIT_RAM_END		0x2000
-#define CFG_GBL_DATA_SIZE		128
-#define CFG_GBL_DATA_OFFSET		(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET		CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR		CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END		0x2000
+#define CONFIG_SYS_GBL_DATA_SIZE		128
+#define CONFIG_SYS_GBL_DATA_OFFSET		(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET		CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE			0x00000000
-#define CFG_SDRAM_SIZE			(32*1024*1024)
-#define CFG_MONITOR_BASE		TEXT_BASE
-#define CFG_MONITOR_FLASH		(CFG_FLASH_BASE + CFG_MONITOR_OFFSET)
-#define CFG_MONITOR_LEN			0x00020000
-#define CFG_MALLOC_LEN			0x00020000
+#define CONFIG_SYS_SDRAM_BASE			0x00000000
+#define CONFIG_SYS_SDRAM_SIZE			(32*1024*1024)
+#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE
+#define CONFIG_SYS_MONITOR_FLASH		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_OFFSET)
+#define CONFIG_SYS_MONITOR_LEN			0x00020000
+#define CONFIG_SYS_MALLOC_LEN			0x00020000
 
 /* boot flags */
 #define BOOTFLAG_COLD			0x01	/* normal power-on */
 #define BOOTFLAG_WARM			0x02	/* software reboot */
 
 /* cache configuration */
-#define CFG_CACHELINE_SIZE		32      /* for MPC8260 */
+#define CONFIG_SYS_CACHELINE_SIZE		32      /* for MPC8260 */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT		5	/* log base 2 of above */
+#define CONFIG_SYS_CACHELINE_SHIFT		5	/* log base 2 of above */
 #endif
 
 /*
@@ -328,43 +328,43 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT			(HID0_ICE|HID0_DCE|\
+#define CONFIG_SYS_HID0_INIT			(HID0_ICE|HID0_DCE|\
 					 HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL			(HID0_IFEM|HID0_ABE)
-#define CFG_HID2			0
+#define CONFIG_SYS_HID0_FINAL			(HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2			0
 
 /* RMR - reset mode register - turn on checkstop reset enable */
-#define CFG_RMR				RMR_CSRE
+#define CONFIG_SYS_RMR				RMR_CSRE
 
 /* BCR - bus configuration */
-#define CFG_BCR				0x00000000
+#define CONFIG_SYS_BCR				0x00000000
 
 /* SIUMCR - siu module configuration */
-#define CFG_SIUMCR			0x4905c000
+#define CONFIG_SYS_SIUMCR			0x4905c000
 
 /* SYPCR - system protection control */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR			0xffffff87
+#define CONFIG_SYS_SYPCR			0xffffff87
 #else
-#define CFG_SYPCR			0xffffff83
+#define CONFIG_SYS_SYPCR			0xffffff83
 #endif
 
 /* TMCNTSC - time counter status and control */
 /* clear interrupts XXX jse */
-/*#define CFG_TMCNTSC			(TMCNTSC_SEC|TMCNTSC_ALR) */
-#define CFG_TMCNTSC			(TMCNTSC_SEC|TMCNTSC_ALR|\
+/*#define CONFIG_SYS_TMCNTSC			(TMCNTSC_SEC|TMCNTSC_ALR) */
+#define CONFIG_SYS_TMCNTSC			(TMCNTSC_SEC|TMCNTSC_ALR|\
 					 TMCNTSC_TCF|TMCNTSC_TCE)
 
 /* PISCR - periodic interrupt status and control */
 /* clear interrupts XXX jse */
-/*#define CFG_PISCR			(PISCR_PS) */
-#define CFG_PISCR			(PISCR_PS|PISCR_PTF|PISCR_PTE)
+/*#define CONFIG_SYS_PISCR			(PISCR_PS) */
+#define CONFIG_SYS_PISCR			(PISCR_PS|PISCR_PTF|PISCR_PTE)
 
 /* SCCR - system clock control */
-#define CFG_SCCR			0x000001a9
+#define CONFIG_SYS_SCCR			0x000001a9
 
 /* RCCR - risc controller configuration */
-#define CFG_RCCR			0
+#define CONFIG_SYS_RCCR			0
 
 /*
  * MEMORY MAP
@@ -379,37 +379,37 @@
  *  x  - IMMR     384KB		base=0xf0000000
  */
 /* XXX jse 100MHz TODO */
-#define CFG_BR0_PRELIM			0xff800801
-#define CFG_OR0_PRELIM			0xff801e44
-#define CFG_BR1_PRELIM			0x00000041
-#define CFG_OR1_PRELIM			0xfe002ec0
+#define CONFIG_SYS_BR0_PRELIM			0xff800801
+#define CONFIG_SYS_OR0_PRELIM			0xff801e44
+#define CONFIG_SYS_BR1_PRELIM			0x00000041
+#define CONFIG_SYS_OR1_PRELIM			0xfe002ec0
 #if 1
-#define CFG_BR2_PRELIM			0xf0101001
-#define CFG_OR2_PRELIM			0xfff00ef4
-#define CFG_BR3_PRELIM			0xf0201001
-#define CFG_OR3_PRELIM			0xfff00ef4
-#define CFG_BR4_PRELIM			0xf0301001
-#define CFG_OR4_PRELIM			0xfff00ef4
-#define CFG_BR5_PRELIM			0xf0401001
-#define CFG_OR5_PRELIM			0xfff00ef4
+#define CONFIG_SYS_BR2_PRELIM			0xf0101001
+#define CONFIG_SYS_OR2_PRELIM			0xfff00ef4
+#define CONFIG_SYS_BR3_PRELIM			0xf0201001
+#define CONFIG_SYS_OR3_PRELIM			0xfff00ef4
+#define CONFIG_SYS_BR4_PRELIM			0xf0301001
+#define CONFIG_SYS_OR4_PRELIM			0xfff00ef4
+#define CONFIG_SYS_BR5_PRELIM			0xf0401001
+#define CONFIG_SYS_OR5_PRELIM			0xfff00ef4
 #else
-#define CFG_BR2_PRELIM			0xf0101081
-#define CFG_OR2_PRELIM			0xfff00104
-#define CFG_BR3_PRELIM			0xf0201081
-#define CFG_OR3_PRELIM			0xfff00104
-#define CFG_BR4_PRELIM			0xf0301081
-#define CFG_OR4_PRELIM			0xfff00104
-#define CFG_BR5_PRELIM			0xf0401081
-#define CFG_OR5_PRELIM			0xfff00104
+#define CONFIG_SYS_BR2_PRELIM			0xf0101081
+#define CONFIG_SYS_OR2_PRELIM			0xfff00104
+#define CONFIG_SYS_BR3_PRELIM			0xf0201081
+#define CONFIG_SYS_OR3_PRELIM			0xfff00104
+#define CONFIG_SYS_BR4_PRELIM			0xf0301081
+#define CONFIG_SYS_OR4_PRELIM			0xfff00104
+#define CONFIG_SYS_BR5_PRELIM			0xf0401081
+#define CONFIG_SYS_OR5_PRELIM			0xfff00104
 #endif
-#define CFG_BR7_PRELIM			0xf0500881
-#define CFG_OR7_PRELIM			0xffff8104
-#define CFG_MPTPR			0x2700
-#define CFG_PSDMR			0x822a2452	/* optimal */
-/*#define CFG_PSDMR			0x822a48a3 */	/* relaxed */
-#define CFG_PSRT			0x1a
+#define CONFIG_SYS_BR7_PRELIM			0xf0500881
+#define CONFIG_SYS_OR7_PRELIM			0xffff8104
+#define CONFIG_SYS_MPTPR			0x2700
+#define CONFIG_SYS_PSDMR			0x822a2452	/* optimal */
+/*#define CONFIG_SYS_PSDMR			0x822a48a3 */	/* relaxed */
+#define CONFIG_SYS_PSRT			0x1a
 
 /* "bad" address */
-#define	CFG_RESET_ADDRESS		0x40000000
+#define	CONFIG_SYS_RESET_ADDRESS		0x40000000
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h
index 95e4556..51d0a0a 100644
--- a/include/configs/W7OLMC.h
+++ b/include/configs/W7OLMC.h
@@ -63,8 +63,9 @@
 #define CONFIG_SERVERIP		192.168.1.2
 
 #define CONFIG_LOADS_ECHO	1		/* echo on for serial download	*/
-#undef CFG_LOADS_BAUD_CHANGE			/* disallow baudrate change	*/
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE			/* disallow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1		/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0		/* PHY address			*/
 
@@ -104,38 +105,38 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"Wave7Optics> " /* Monitor Command Prompt	*/
-#undef  CFG_HUSH_PARSER				/* No hush parse for U-Boot       */
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"Wave7Optics> " /* Monitor Command Prompt	*/
+#undef  CONFIG_SYS_HUSH_PARSER				/* No hush parse for U-Boot       */
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
 #endif
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM		*/
 
-#undef  CFG_EXT_SERIAL_CLOCK			/* external serial clock */
-#define CFG_405_UART_ERRATA_59			/* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD		384000
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK			/* external serial clock */
+#define CONFIG_SYS_405_UART_ERRATA_59			/* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		384000
 
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	{9600}
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600}
 
-#define CFG_CLKS_IN_HZ		1		/* everything, incl board info, in Hz */
+#define CONFIG_SYS_CLKS_IN_HZ		1		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address		*/
-#define CFG_EXTBDINFO		1		/* use extended board_info (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address		*/
+#define CONFIG_SYS_EXTBDINFO		1		/* use extended board_info (bd_t) */
 
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -150,14 +151,14 @@
 #define CONFIG_PCI_HOST		PCI_HOST_AUTO	/* select pci host function	*/
 #define CONFIG_PCI_PNP				/* pci plug-and-play		*/
 /* resource configuration	*/
-#define CFG_PCI_SUBSYS_VENDORID 0x1014		/* PCI Vendor ID: IBM		*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0156		/* PCI Device ID: 405GP		*/
-#define CFG_PCI_PTM1LA		0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS		0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI		0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA		0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2MS		0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2PCI		0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014		/* PCI Vendor ID: IBM		*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156		/* PCI Device ID: 405GP		*/
+#define CONFIG_SYS_PCI_PTM1LA		0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS		0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CONFIG_SYS_PCI_PTM1PCI		0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA		0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2MS		0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2PCI		0x00000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * Set up values for external bus controller
@@ -168,94 +169,94 @@
 #undef CONFIG_USE_PERWE
 
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
+#define CONFIG_SYS_TEMP_STACK_OCM        1
 
 /* bank 0 is boot flash */
 /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CFG_W7O_EBC_PB0AP   0x03050440
+#define CONFIG_SYS_W7O_EBC_PB0AP   0x03050440
 /* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
-#define CFG_W7O_EBC_PB0CR   0xFFE38000
+#define CONFIG_SYS_W7O_EBC_PB0CR   0xFFE38000
 
 /* bank 1 is main flash */
 /* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CFG_EBC_PB1AP   0x05850240
+#define CONFIG_SYS_EBC_PB1AP   0x05850240
 /* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
-#define CFG_EBC_PB1CR   0xF00FC000
+#define CONFIG_SYS_EBC_PB1CR   0xF00FC000
 
 /* bank 2 is RTC/NVRAM */
 /* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CFG_EBC_PB2AP   0x03000440
+#define CONFIG_SYS_EBC_PB2AP   0x03000440
 /* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
-#define CFG_EBC_PB2CR   0xFC018000
+#define CONFIG_SYS_EBC_PB2CR   0xFC018000
 
 /* bank 3 is FPGA 0 */
 /* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
-#define CFG_EBC_PB3AP   0x02000400
+#define CONFIG_SYS_EBC_PB3AP   0x02000400
 /* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
-#define CFG_EBC_PB3CR   0xFD01A000
+#define CONFIG_SYS_EBC_PB3CR   0xFD01A000
 
 /* bank 4 is FPGA 1 */
 /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
-#define CFG_EBC_PB4AP   0x02000400
+#define CONFIG_SYS_EBC_PB4AP   0x02000400
 /* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
-#define CFG_EBC_PB4CR   0xFD11A000
+#define CONFIG_SYS_EBC_PB4CR   0xFD11A000
 
 /* bank 5 is FPGA 2 */
 /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
-#define CFG_EBC_PB5AP   0x02000400
+#define CONFIG_SYS_EBC_PB5AP   0x02000400
 /* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
-#define CFG_EBC_PB5CR   0xFD21A000
+#define CONFIG_SYS_EBC_PB5CR   0xFD21A000
 
 /* bank 6 is unused */
 /* pb6ap = 0 */
-#define CFG_EBC_PB6AP   0x00000000
+#define CONFIG_SYS_EBC_PB6AP   0x00000000
 /* pb6cr = 0 */
-#define CFG_EBC_PB6CR   0x00000000
+#define CONFIG_SYS_EBC_PB6CR   0x00000000
 
 /* bank 7 is LED register */
 /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CFG_W7O_EBC_PB7AP   0x03050440
+#define CONFIG_SYS_W7O_EBC_PB7AP   0x03050440
 /* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
-#define CFG_W7O_EBC_PB7CR   0xFE01C000
+#define CONFIG_SYS_W7O_EBC_PB7CR   0xFE01C000
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2		/* max number of memory banks	*/
-#define CFG_MAX_FLASH_SECT	256		/* max number of sec on 1 chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* max number of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max number of sec on 1 chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000		/* Timeout, Flash Erase, in ms	*/
-#define CFG_FLASH_WRITE_TOUT	500		/* Timeout, Flash Write, in ms	*/
-#define CFG_FLASH_PROTECTION	1		/* Use real Flash protection	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000		/* Timeout, Flash Erase, in ms	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout, Flash Write, in ms	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1		/* Use real Flash protection	*/
 
 #if 1 /* Use NVRAM for environment variables */
 /*-----------------------------------------------------------------------
  * NVRAM organization
  */
 #define CONFIG_ENV_IS_IN_NVRAM	1		/* use NVRAM for env vars	*/
-#define CFG_NVRAM_BASE_ADDR	0xfc000000	/* NVRAM base address		*/
-#define CFG_NVRAM_SIZE		(32*1024)	/* NVRAM size			*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xfc000000	/* NVRAM base address		*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)	/* NVRAM size			*/
 #define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
 /*define CONFIG_ENV_ADDR		 \
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE) Env  */
-#define CONFIG_ENV_ADDR		CFG_NVRAM_BASE_ADDR
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env  */
+#define CONFIG_ENV_ADDR		CONFIG_SYS_NVRAM_BASE_ADDR
 
 #else /* Use Boot Flash for environment variables */
 /*-----------------------------------------------------------------------
@@ -272,18 +273,17 @@
  * I2C EEPROM (CAT24WC08) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last	4 bits of the address	*/
-#define CFG_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
 /*-----------------------------------------------------------------------
  * Definitions for Serial Presence Detect EEPROM address
  * (to get SDRAM settings)
@@ -297,17 +297,17 @@
 #define FLASH_BASE1_PRELIM	0xF0000000	/* FLASH bank #1		*/
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in RAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 
 /*
@@ -326,7 +326,7 @@
 /*
  * FPGA(s) configuration
  */
-#define CFG_FPGA_IMAGE_LEN	0x80000		/* 512KB FPGA image		*/
+#define CONFIG_SYS_FPGA_IMAGE_LEN	0x80000		/* 512KB FPGA image		*/
 #define CONFIG_NUM_FPGAS	3		/* Number of FPGAs on board	*/
 #define CONFIG_MAX_FPGAS	6		/* Maximum number of FPGAs	*/
 #define CONFIG_FPGAS_BASE	0xFD000000L	/* Base address of FPGAs	*/
diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h
index 9c5bbff..ca1a9d4 100644
--- a/include/configs/W7OLMG.h
+++ b/include/configs/W7OLMG.h
@@ -63,17 +63,18 @@
 #define CONFIG_SERVERIP		192.168.1.2
 
 #define CONFIG_LOADS_ECHO	1		/* echo on for serial download	*/
-#undef CFG_LOADS_BAUD_CHANGE			/* disallow baudrate change	*/
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE			/* disallow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1		/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0		/* PHY address			*/
 
 #define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
 #define CONFIG_DTT_LM75     1                /* ON Semi's LM75 */
 #define CONFIG_DTT_SENSORS  {2, 4}           /* Sensor addresses */
-#define CFG_DTT_MAX_TEMP	70
-#define CFG_DTT_LOW_TEMP	-30
-#define CFG_DTT_HYSTERESIS	3
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
 
 
 /*
@@ -112,38 +113,38 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"Wave7Optics> " /* Monitor Command Prompt	*/
-#undef  CFG_HUSH_PARSER				/* No hush parse for U-Boot       */
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"Wave7Optics> " /* Monitor Command Prompt	*/
+#undef  CONFIG_SYS_HUSH_PARSER				/* No hush parse for U-Boot       */
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
 #endif
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM		*/
 
-#undef  CFG_EXT_SERIAL_CLOCK			/* external serial clock */
-#define CFG_405_UART_ERRATA_59			/* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD		384000
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK			/* external serial clock */
+#define CONFIG_SYS_405_UART_ERRATA_59			/* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		384000
 
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	{9600}
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600}
 
-#define CFG_CLKS_IN_HZ		1		/* everything, incl board info, in Hz */
+#define CONFIG_SYS_CLKS_IN_HZ		1		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address		*/
-#define CFG_EXTBDINFO		1		/* use extended board_info (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address		*/
+#define CONFIG_SYS_EXTBDINFO		1		/* use extended board_info (bd_t) */
 
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -157,14 +158,14 @@
 #define CONFIG_PCI_HOST		PCI_HOST_AUTO	/* select pci host function	*/
 #define CONFIG_PCI_PNP				/* pci plug-and-play		*/
 /* resource configuration	*/
-#define CFG_PCI_SUBSYS_VENDORID 0x1014		/* PCI Vendor ID: IBM		*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0156		/* PCI Device ID: 405GP		*/
-#define CFG_PCI_PTM1LA		0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS		0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI		0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA		0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2MS		0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2PCI		0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014		/* PCI Vendor ID: IBM		*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156		/* PCI Device ID: 405GP		*/
+#define CONFIG_SYS_PCI_PTM1LA		0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS		0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CONFIG_SYS_PCI_PTM1PCI		0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA		0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2MS		0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2PCI		0x00000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * Set up values for external bus controller
@@ -175,94 +176,94 @@
 #define CONFIG_USE_PERWE 1
 
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
+#define CONFIG_SYS_TEMP_STACK_OCM        1
 
 /* bank 0 is boot flash */
 /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CFG_W7O_EBC_PB0AP   0x03050440
+#define CONFIG_SYS_W7O_EBC_PB0AP   0x03050440
 /* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
-#define CFG_W7O_EBC_PB0CR   0xFFE38000
+#define CONFIG_SYS_W7O_EBC_PB0CR   0xFFE38000
 
 /* bank 1 is main flash */
 /* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CFG_EBC_PB1AP   0x04850240
+#define CONFIG_SYS_EBC_PB1AP   0x04850240
 /* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
-#define CFG_EBC_PB1CR   0xF00FC000
+#define CONFIG_SYS_EBC_PB1CR   0xF00FC000
 
 /* bank 2 is RTC/NVRAM */
 /* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CFG_EBC_PB2AP   0x03000440
+#define CONFIG_SYS_EBC_PB2AP   0x03000440
 /* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
-#define CFG_EBC_PB2CR   0xFC018000
+#define CONFIG_SYS_EBC_PB2CR   0xFC018000
 
 /* bank 3 is FPGA 0 */
 /* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
-#define CFG_EBC_PB3AP   0x02000400
+#define CONFIG_SYS_EBC_PB3AP   0x02000400
 /* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
-#define CFG_EBC_PB3CR   0xFD01A000
+#define CONFIG_SYS_EBC_PB3CR   0xFD01A000
 
 /* bank 4 is SAM 8 bit range */
 /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
-#define CFG_EBC_PB4AP   0x02840380
+#define CONFIG_SYS_EBC_PB4AP   0x02840380
 /* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
-#define CFG_EBC_PB4CR   0xFE878000
+#define CONFIG_SYS_EBC_PB4CR   0xFE878000
 
 /* bank 5 is SAM 16 bit range */
 /* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */
-#define CFG_EBC_PB5AP   0x05040d80
+#define CONFIG_SYS_EBC_PB5AP   0x05040d80
 /* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
-#define CFG_EBC_PB5CR   0xFD87A000
+#define CONFIG_SYS_EBC_PB5CR   0xFD87A000
 
 /* bank 6 is unused */
 /* pb6ap = 0 */
-#define CFG_EBC_PB6AP   0x00000000
+#define CONFIG_SYS_EBC_PB6AP   0x00000000
 /* pb6cr = 0 */
-#define CFG_EBC_PB6CR   0x00000000
+#define CONFIG_SYS_EBC_PB6CR   0x00000000
 
 /* bank 7 is LED register */
 /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CFG_W7O_EBC_PB7AP   0x03050440
+#define CONFIG_SYS_W7O_EBC_PB7AP   0x03050440
 /* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
-#define CFG_W7O_EBC_PB7CR   0xFE01C000
+#define CONFIG_SYS_W7O_EBC_PB7CR   0xFE01C000
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 196 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 196 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2		/* max number of memory banks	*/
-#define CFG_MAX_FLASH_SECT	256		/* max number of sec on 1 chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* max number of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max number of sec on 1 chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000		/* Timeout, Flash Erase, in ms	*/
-#define CFG_FLASH_WRITE_TOUT	500		/* Timeout, Flash Write, in ms	*/
-#define CFG_FLASH_PROTECTION	1		/* Use real Flash protection	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000		/* Timeout, Flash Erase, in ms	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout, Flash Write, in ms	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1		/* Use real Flash protection	*/
 
 #if 1 /* Use NVRAM for environment variables */
 /*-----------------------------------------------------------------------
  * NVRAM organization
  */
 #define CONFIG_ENV_IS_IN_NVRAM	1		/* use NVRAM for env vars	*/
-#define CFG_NVRAM_BASE_ADDR	0xfc000000	/* NVRAM base address		*/
-#define CFG_NVRAM_SIZE		(32*1024)	/* NVRAM size			*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xfc000000	/* NVRAM base address		*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)	/* NVRAM size			*/
 #define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
 /*define CONFIG_ENV_ADDR		 \
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE) Env  */
-#define CONFIG_ENV_ADDR		CFG_NVRAM_BASE_ADDR
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env  */
+#define CONFIG_ENV_ADDR		CONFIG_SYS_NVRAM_BASE_ADDR
 
 #else /* Use Boot Flash for environment variables */
 /*-----------------------------------------------------------------------
@@ -279,14 +280,13 @@
  * I2C EEPROM (ATMEL 24C04N)
  */
 #define CONFIG_HARD_I2C		1		/* Hardware assisted I2C	*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-
-#define CFG_I2C_EEPROM_ADDR	0x50		/* EEPROM ATMEL 24C04N		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* EEPROM ATMEL 24C04N		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
 /*-----------------------------------------------------------------------
  * Definitions for Serial Presence Detect EEPROM address
  * (to get SDRAM settings)
@@ -300,17 +300,17 @@
 #define FLASH_BASE1_PRELIM	0xF0000000	/* FLASH bank #1		*/
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in RAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 
 /*
@@ -329,7 +329,7 @@
 /*
  * FPGA(s) configuration
  */
-#define CFG_FPGA_IMAGE_LEN	0x80000		/* 512KB FPGA image		*/
+#define CONFIG_SYS_FPGA_IMAGE_LEN	0x80000		/* 512KB FPGA image		*/
 #define CONFIG_NUM_FPGAS	1		/* Number of FPGAs on board	*/
 #define CONFIG_MAX_FPGAS	6		/* Maximum number of FPGAs	*/
 #define CONFIG_FPGAS_BASE	0xFD000000L	/* Base address of FPGAs	*/
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
index c3fc3af..99188bc 100644
--- a/include/configs/WUH405.h
+++ b/include/configs/WUH405.h
@@ -52,8 +52,9 @@
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
@@ -89,73 +90,71 @@
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
+#define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
 #define	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*-----------------------------------------------------------------------
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
-#define NAND_MAX_CHIPS          1
-#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
 #define NAND_BIG_DELAY_US	25
 
-#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
-#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
-#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
-#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
+#define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
-#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -172,58 +171,58 @@
 
 #undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -234,25 +233,24 @@
 #define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */
 
-#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 /*
  * Init Memory Controller:
@@ -267,21 +265,21 @@
  */
 
 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x92015480
-/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+/*#define CONFIG_SYS_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
-#define CFG_EBC_PB1AP		0x92015480
-#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
-#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
-#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
 #define CAN_BA		0xF0000000	    /* CAN Base Address			*/
 #define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
@@ -289,36 +287,36 @@
 #define DUART2_BA	0xF0000410	    /* DUART Base Address		*/
 #define DUART3_BA	0xF0000418	    /* DUART Base Address		*/
 #define RTC_BA		0xF0000500	    /* RTC Base Address			*/
-#define CFG_NAND_BASE	0xF4000000
+#define CONFIG_SYS_NAND_BASE	0xF4000000
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
 
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup (PPC405EP specific)
@@ -332,15 +330,15 @@
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  */
-#define CFG_GPIO0_OSRH		0x40000550
-#define CFG_GPIO0_OSRL		0x00000110
-#define CFG_GPIO0_ISR1H		0x00000000
-#define CFG_GPIO0_ISR1L		0x15555445
-#define CFG_GPIO0_TSRH		0x00000000
-#define CFG_GPIO0_TSRL		0x00000000
-#define CFG_GPIO0_TCR		0xF7FE0014
-
-#define CFG_DUART_RST		(0x80000000 >> 14)
+#define CONFIG_SYS_GPIO0_OSRH		0x40000550
+#define CONFIG_SYS_GPIO0_OSRL		0x00000110
+#define CONFIG_SYS_GPIO0_ISR1H		0x00000000
+#define CONFIG_SYS_GPIO0_ISR1L		0x15555445
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0xF7FE0014
+
+#define CONFIG_SYS_DUART_RST		(0x80000000 >> 14)
 
 /*
  * Internal Definitions
diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h
index 77b29f4..8d44ec6 100644
--- a/include/configs/XPEDITE1K.h
+++ b/include/configs/XPEDITE1K.h
@@ -38,29 +38,29 @@
 #define CONFIG_440		1
 #define CONFIG_440GX		1		/* 440 GX */
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_pre_init	*/
-#undef	CFG_DRAM_TEST				/* Disable-takes long time! */
+#undef	CONFIG_SYS_DRAM_TEST				/* Disable-takes long time! */
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll */
 
 
 /* POST support */
-#define CONFIG_POST		(CFG_POST_RTC	   | \
-				 CFG_POST_I2C)
+#define CONFIG_POST		(CONFIG_SYS_POST_RTC	   | \
+				 CONFIG_SYS_POST_I2C)
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE	    0x00000000		/* _must_ be 0		*/
-#define CFG_FLASH_BASE	    0xfff80000		/* start of FLASH	*/
+#define CONFIG_SYS_SDRAM_BASE	    0x00000000		/* _must_ be 0		*/
+#define CONFIG_SYS_FLASH_BASE	    0xfff80000		/* start of FLASH	*/
 
-#define CFG_MONITOR_BASE    CFG_FLASH_BASE	/* start of monitor	*/
-#define CFG_PCI_MEMBASE	    0x80000000		/* mapped pci memory	*/
-#define CFG_PERIPHERAL_BASE 0xe0000000		/* internal peripherals */
-#define CFG_ISRAM_BASE	    0xc0000000		/* internal SRAM	*/
-#define CFG_PCI_BASE	    0xd0000000		/* internal PCI regs	*/
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_FLASH_BASE	/* start of monitor	*/
+#define CONFIG_SYS_PCI_MEMBASE	    0x80000000		/* mapped pci memory	*/
+#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000		/* internal peripherals */
+#define CONFIG_SYS_ISRAM_BASE	    0xc0000000		/* internal SRAM	*/
+#define CONFIG_SYS_PCI_BASE	    0xd0000000		/* internal PCI regs	*/
 
-#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
-#define CFG_GPIO_BASE	    (CFG_PERIPHERAL_BASE + 0x00000700)
+#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
+#define CONFIG_SYS_GPIO_BASE	    (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
 
 #define USR_LED0	    0x00000080
 #define USR_LED1	    0x00000100
@@ -71,33 +71,33 @@
 extern unsigned long in32(unsigned int);
 extern void out32(unsigned int, unsigned long);
 
-#define LED0_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED0))
-#define LED1_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED1))
-#define LED2_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED2))
-#define LED3_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED3))
+#define LED0_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED0))
+#define LED1_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED1))
+#define LED2_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED2))
+#define LED3_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED3))
 
-#define LED0_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED0))
-#define LED1_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED1))
-#define LED2_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED2))
-#define LED3_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED3))
+#define LED0_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED0))
+#define LED1_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED1))
+#define LED2_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED2))
+#define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3))
 #endif
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
-#define CFG_TEMP_STACK_OCM  1
-#define CFG_OCM_DATA_ADDR   CFG_ISRAM_BASE
-#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
-#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE   128		    /* num bytes initial data	*/
+#define CONFIG_SYS_TEMP_STACK_OCM  1
+#define CONFIG_SYS_OCM_DATA_ADDR   CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR   CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE   128		    /* num bytes initial data	*/
 
 
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR  (CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET  CFG_POST_WORD_ADDR
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_POST_WORD_ADDR  (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_POST_WORD_ADDR
 
-#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
-#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
+#define CONFIG_SYS_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
+#define CONFIG_SYS_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
 
 /*-----------------------------------------------------------------------
  * Serial Port
@@ -105,7 +105,7 @@ extern void out32(unsigned int, unsigned long);
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CONFIG_BAUDRATE		9600
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
 
 /*-----------------------------------------------------------------------
@@ -115,23 +115,23 @@ extern void out32(unsigned int, unsigned long);
  * The DS1743 code assumes this condition (i.e. -- it assumes the base
  * address for the RTC registers is:
  *
- *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *	CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
  *
  *----------------------------------------------------------------------*/
 /* TBS:	 Xpedite 1000 has STMicro M41T00 via IIC */
 #define CONFIG_RTC_M41T11 1
-#define CFG_I2C_RTC_ADDR 0x68
-#define CFG_M41T11_BASE_YEAR 2000
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 2000
 
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS	1		    /* number of banks	    */
-#define CFG_MAX_FLASH_SECT	8		    /* sectors per device   */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		    /* number of banks	    */
+#define CONFIG_SYS_MAX_FLASH_SECT	8		    /* sectors per device   */
 
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	    /* Timeout for Flash Write (in ms)	*/
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	    /* Timeout for Flash Write (in ms)	*/
 
 /*-----------------------------------------------------------------------
  * DDR SDRAM
@@ -144,9 +144,9 @@ extern void out32(unsigned int, unsigned long);
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7f
-#define CFG_I2C_NOPROBES	{0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7f
+#define CONFIG_SYS_I2C_NOPROBES	{0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69}	/* Don't probe these addrs */
 
 /*-----------------------------------------------------------------------
  * Environment
@@ -154,11 +154,10 @@ extern void out32(unsigned int, unsigned long);
 #define CONFIG_ENV_IS_IN_EEPROM 1
 #define CONFIG_ENV_SIZE		0x100	    /* Size of Environment vars */
 #define CONFIG_ENV_OFFSET		0x100
-#define CFG_I2C_EEPROM_ADDR	0x50		/* this is actually the second page of the eeprom */
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* this is actually the second page of the eeprom */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 
 #define CONFIG_BOOTARGS		"root=/dev/hda1 "
 #define CONFIG_BOOTCOMMAND	"bootm ffc00000"    /* autoboot command */
@@ -166,8 +165,9 @@ extern void out32(unsigned int, unsigned long);
 #define CONFIG_BAUDRATE		9600
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII			1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address phy0 not populated */
 #define CONFIG_PHY1_ADDR	1	/* PHY address phy1 not populated */
@@ -176,7 +176,7 @@ extern void out32(unsigned int, unsigned long);
 #define CONFIG_NET_MULTI	1
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 #define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
-#define CFG_RX_ETH_BUFFER   32	/* Number of ethernet rx buffers & descriptors */
+#define CONFIG_SYS_RX_ETH_BUFFER   32	/* Number of ethernet rx buffers & descriptors */
 
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
 #define CONFIG_HAS_ETH2		1	/* add support for "eth2addr"	*/
@@ -215,24 +215,24 @@ extern void out32(unsigned int, unsigned long);
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 
 /*-----------------------------------------------------------------------
@@ -243,20 +243,20 @@ extern void out32(unsigned int, unsigned long);
 #define CONFIG_PCI				    /* include pci support		*/
 #define CONFIG_PCI_PNP				/* do pci plug-and-play		*/
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
-#define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
+#define CONFIG_SYS_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT		    /* let board init pci target    */
+#define CONFIG_SYS_PCI_TARGET_INIT		    /* let board init pci target    */
 
-#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
-#define CFG_PCI_FORCE_PCI_CONV          /* Force PCI Conventional Mode */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+#define CONFIG_SYS_PCI_FORCE_PCI_CONV          /* Force PCI Conventional Mode */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Internal Definitions
diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h
new file mode 100644
index 0000000..370aae1
--- /dev/null
+++ b/include/configs/XPEDITE5200.h
@@ -0,0 +1,546 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * xpedite5200 board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548		1
+#define CONFIG_XPEDITE5200	1
+#define CONFIG_SYS_BOARD_NAME	"XPedite5200"
+#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
+#define CONFIG_RELOC_FIXUP_WORKS	/* Fully relocate to SDRAM */
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
+#define CONFIG_PCI1		1	/* PCI controller 1 */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+/*
+ * DDR config
+ */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS		0x54
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_SYS_CLK_FREQ	66666666
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xef000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
+#define CONFIG_SYS_PCI1_ADDR	(CONFIG_SYS_CCSRBAR + 0x8000)
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+
+/*
+ * Memory map
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCI1 Mem		1G non-cacheable
+ * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
+ * 0xe800_0000	0xe87f_ffff	PCI1 IO			8M non-cacheable
+ * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
+ * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
+ * 0xf800_0000	0xfbff_ffff	NOR Flash 2		64M non-cacheable
+ * 0xfc00_0000	0xffff_ffff	NOR Flash 1		64M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_4 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE		0xef800000
+#define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_NAND_ACTL
+#define CONFIG_SYS_NAND_ACTL_CLE	(1 << 3)	/* ADDR3 is CLE */
+#define CONFIG_SYS_NAND_ACTL_ALE	(1 << 4)	/* ADDR4 is ALE */
+#define CONFIG_SYS_NAND_ACTL_NCE	(0)		/* NCE not controlled by ADDR */
+#define CONFIG_SYS_NAND_ACTL_DELAY	25
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xfc000000
+#define CONFIG_SYS_FLASH_BASE2		0xf8000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
+						  {0xfbf40000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(OR_AM_64MB		| \
+				 OR_GPCM_ACS_DIV4	| \
+				 OR_GPCM_SCY_8)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
+				 BR_PS_8		| \
+				 BR_V)
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB		| \
+				 OR_GPCM_BCTLD		| \
+				 OR_GPCM_CSNT		| \
+				 OR_GPCM_ACS_DIV4	| \
+				 OR_GPCM_SCY_4		| \
+				 OR_GPCM_TRLX		| \
+				 OR_GPCM_EHTR)
+
+/* NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
+				 BR_PS_8		| \
+				 BR_V)
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
+#define CONFIG_SYS_INIT_RAM_END		0x4000
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C				/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C				/* I2C with hardware support */
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+
+/* I2C EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11			1
+#define CONFIG_SYS_I2C_RTC_ADDR			0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR		2000
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0		0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1		0x19
+#define CONFIG_SYS_I2C_PCA953X_ADDR		CONFIG_SYS_I2C_PCA953X_ADDR0
+
+/* PCA957 @ 0x18 */
+#define CONFIG_SYS_PCA953X_BRD_CFG0		0x01
+#define CONFIG_SYS_PCA953X_BRD_CFG1		0x02
+#define CONFIG_SYS_PCA953X_BRD_CFG2		0x04
+#define CONFIG_SYS_PCA953X_XMC_ROOT0		0x08
+#define CONFIG_SYS_PCA953X_FLASH_PASS_CS	0x10
+#define CONFIG_SYS_PCA953X_FLASH_WP		0x20
+#define CONFIG_SYS_PCA953X_MONARCH		0x40
+#define CONFIG_SYS_PCA953X_EREADY		0x80
+
+/* PCA957 @ 0x19 */
+#define CONFIG_SYS_PCA953X_P14_IO0		0x01
+#define CONFIG_SYS_PCA953X_P14_IO1		0x02
+#define CONFIG_SYS_PCA953X_P14_IO2		0x04
+#define CONFIG_SYS_PCA953X_P14_IO3		0x08
+#define CONFIG_SYS_PCA953X_P14_IO4		0x10
+#define CONFIG_SYS_PCA953X_P14_IO5		0x20
+#define CONFIG_SYS_PCA953X_P14_IO6		0x40
+#define CONFIG_SYS_PCA953X_P14_IO7		0x80
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x40000000	/* 1G */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xe8000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00800000	/* 1M */
+
+/*
+ * Networking options
+ */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_NET_MULTI	1
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC1_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define TSEC2_PHY_ADDR		2
+#define TSEC2_PHYIDX		0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+#define TSEC3_FLAGS		TSEC_GIGABIT
+#define TSEC3_PHY_ADDR		3
+#define TSEC3_PHYIDX		0
+#define CONFIG_HAS_ETH2
+
+#define CONFIG_TSEC4	1
+#define CONFIG_TSEC4_NAME	"eTSEC4"
+#define TSEC4_FLAGS		TSEC_GIGABIT
+#define TSEC4_PHY_ADDR		4
+#define TSEC4_PHYIDX		0
+#define CONFIG_HAS_ETH3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+
+/*
+ * Command configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
+#define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG			/* do not reset board on panic */
+#define CONFIG_PREBOOT				/* enable preboot variable */
+#define CONFIG_FIT		1
+#define CONFIG_FIT_VERBOSE	1
+#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
+#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
+
+/*
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02		/* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff     Pri U-Boot (512 KB)
+ * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff     Pri FDT (256KB)
+ * fef00000 - ffefffff     Pri OS image (16MB)
+ * fc000000 - feefffff     Pri OS Use/Filesystem (47MB)
+ *
+ * fbf80000 - fbffffff     Sec U-Boot (512 KB)
+ * fbf40000 - fbf7ffff     Sec U-Boot Environment (256 KB)
+ * fbf00000 - fbf3ffff     Sec FDT (256KB)
+ * faf00000 - fbefffff     Sec OS image (16MB)
+ * f8000000 - faefffff     Sec OS Use/Filesystem (47MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR	MK_STR(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR	MK_STR(0xfbf80000)
+#define CONFIG_FDT1_ENV_ADDR	MK_STR(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR	MK_STR(0xfbf00000)
+#define CONFIG_OS1_ENV_ADDR	MK_STR(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR	MK_STR(0xfaf00000)
+
+#define CONFIG_PROG_UBOOT1						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_UBOOT2						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_BOOT_OS_NET						\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"if test -n $fdtaddr; then "				\
+			"$download_cmd $fdtaddr $fdtfile; "		\
+			"if test $? -eq 0; then "			\
+				"bootm $osaddr - $fdtaddr; "		\
+			"else; "					\
+				"echo FDT DOWNLOAD FAILED; "		\
+			"fi; "						\
+		"else; "						\
+			"bootm $osaddr; "				\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS1							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS2							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT1						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT2						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"autoload=yes\0"						\
+	"download_cmd=tftp\0"						\
+	"console_args=console=ttyS0,115200\0"				\
+	"root_args=root=/dev/nfs rw\0"					\
+	"misc_args=ip=on\0"						\
+	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+	"bootfile=/home/user/file\0"					\
+	"osfile=/home/user/uImage-XPedite5200\0"			\
+	"fdtfile=/home/user/xpedite5200.dtb\0"				\
+	"ubootfile=/home/user/u-boot.bin\0"				\
+	"fdtaddr=c00000\0"						\
+	"osaddr=0x1000000\0"						\
+	"loadaddr=0x1000000\0"						\
+	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
+	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
+	"prog_os1="CONFIG_PROG_OS1"\0"					\
+	"prog_os2="CONFIG_PROG_OS2"\0"					\
+	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
+	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
+	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
+	"bootcmd_flash1=run set_bootargs; "				\
+		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+	"bootcmd_flash2=run set_bootargs; "				\
+		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+	"bootcmd=run bootcmd_flash1\0"
+#endif	/* __CONFIG_H */
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
new file mode 100644
index 0000000..a353a14
--- /dev/null
+++ b/include/configs/XPEDITE5370.h
@@ -0,0 +1,589 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * xpedite5370 board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8572		1
+#define CONFIG_XPEDITE5370	1
+#define CONFIG_SYS_BOARD_NAME	"XPedite5370"
+#define CONFIG_NUM_CPUS		2	/* 2 Cores */
+#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
+#define CONFIG_RELOC_FIXUP_WORKS	/* Fully relocate to SDRAM */
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 */
+#define CONFIG_PCIE2		1	/* PCIE controler 2 */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+/*
+ * DDR config
+ */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS1		0x54	/* Both channels use the */
+#define SPD_EEPROM_ADDRESS2		0x54	/* same SPD data         */
+#define SPD_EEPROM_OFFSET		0x200	/* OFFSET of SPD in EEPROM */
+#define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+extern unsigned long get_board_ddr_clk(unsigned long dummy);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xef000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
+#define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR + 0xa000)
+#define CONFIG_SYS_PCIE2_ADDR		(CONFIG_SYS_CCSRBAR + 0x9000)
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+
+/*
+ * Memory map
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCIe1 Mem		1G non-cacheable
+ * 0xc000_0000	0xcfff_ffff	PCIe2 Mem		256M non-cacheable
+ * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
+ * 0xe800_0000	0xe87f_ffff	PCIe1 IO		8M non-cacheable
+ * 0xe880_0000	0xe8ff_ffff	PCIe2 IO		8M non-cacheable
+ * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
+ * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
+ * 0xf000_0000	0xf7ff_ffff	NOR Flash 2		128M non-cacheable
+ * 0xf800_0000	0xffff_ffff	NOR Flash 1		128M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_4 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE		0xef800000
+#define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xf8000000
+#define CONFIG_SYS_FLASH_BASE2		0xf0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
+						  {0xf7f40000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(OR_AM_128MB		| \
+				 OR_GPCM_CSNT		| \
+				 OR_GPCM_XACS		| \
+				 OR_GPCM_ACS_DIV2	| \
+				 OR_GPCM_SCY_8		| \
+				 OR_GPCM_TRLX		| \
+				 OR_GPCM_EHTR		| \
+				 OR_GPCM_EAD)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
+				 (2<<BR_DECC_SHIFT)	| \
+				 BR_PS_8		| \
+				 BR_MS_FCM		| \
+				 BR_V)
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB	| \
+				 OR_FCM_PGS	| \
+				 OR_FCM_CSCT	| \
+				 OR_FCM_CST	| \
+				 OR_FCM_CHT	| \
+				 OR_FCM_SCY_1	| \
+				 OR_FCM_TRLX	| \
+				 OR_FCM_EHTR)
+
+/* NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
+				 (2<<BR_DECC_SHIFT)	| \
+				 BR_PS_8		| \
+				 BR_MS_FCM		| \
+				 BR_V)
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
+#define CONFIG_SYS_INIT_RAM_END		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C				/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C				/* I2C with hardware support */
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+
+/* PEX8518 slave I2C interface */
+#define CONFIG_SYS_I2C_PEX8518_ADDR	0x70
+
+/* I2C DS1631 temperature sensor */
+#define CONFIG_SYS_I2C_DS1621_ADDR	0x48
+#define CONFIG_DTT_DS1621
+#define CONFIG_DTT_SENSORS		{ 0 }
+
+/* I2C EEPROM - AT24C128B */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	2000
+
+/* GPIO/EEPROM/SRAM */
+#define CONFIG_DS4510
+#define CONFIG_SYS_I2C_DS4510_ADDR	0x51
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0	0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1	0x1c
+#define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
+#define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
+#define CONFIG_SYS_I2C_PCA953X_ADDR	CONFIG_SYS_I2C_PCA953X_ADDR0
+
+/*
+ * PU = pulled high, PD = pulled low
+ * I = input, O = output, IO = input/output
+ */
+/* PCA9557 @ 0x18*/
+#define CONFIG_SYS_PCA953X_C0_SER0_EN		0x01 /* PU; UART0 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER0_MODE		0x02 /* PU; UART0 serial mode select */
+#define CONFIG_SYS_PCA953X_C0_SER1_EN		0x04 /* PU; UART1 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER1_MODE		0x08 /* PU; UART1 serial mode select */
+#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS	0x10 /* PU; Boot flash CS select */
+#define CONFIG_SYS_PCA953X_NVM_WP		0x20 /* PU; Set to 0 to enable NVM writing */
+#define CONFIG_SYS_PCA953X_C0_VCORE_VID2	0x40 /* VID2 of ISL6262 */
+#define CONFIG_SYS_PCA953X_C0_VCORE_VID3	0x80 /* VID3 of ISL6262 */
+
+/* PCA9557 @ 0x1c*/
+#define CONFIG_SYS_PCA953X_XMC0_ROOT0		0x01 /* PU; Low if XMC is RC */
+#define CONFIG_SYS_PCA953X_XMC0_MVMR0		0x02 /* XMC EEPROM write protect */
+#define CONFIG_SYS_PCA953X_XMC0_WAKE		0x04 /* PU; XMC wake */
+#define CONFIG_SYS_PCA953X_XMC0_BIST		0x08 /* PU; XMC built in self test */
+#define CONFIG_SYS_PCA953X_XMC_PRESENT		0x10 /* PU; Low if XMC module installed */
+#define CONFIG_SYS_PCA953X_PMC_PRESENT		0x20 /* PU; Low if PMC module installed */
+#define CONFIG_SYS_PCA953X_PMC0_MONARCH		0x40 /* PMC monarch mode enable */
+#define CONFIG_SYS_PCA953X_PMC0_EREADY		0x80 /* PU; PMC PCI eready */
+
+/* PCA9557 @ 0x1e*/
+#define CONFIG_SYS_PCA953X_P0_GA0		0x01 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA1		0x02 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA2		0x04 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA3		0x08 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA4		0x10 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GAP		0x20 /* PU; tied to VPX P0.GAP */
+#define CONFIG_SYS_PCA953X_P1_SYSEN		0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
+
+/* PCA9557 @ 0x1f */
+#define CONFIG_SYS_PCA953X_GPIO_VPX0		0x01 /* PU */
+#define CONFIG_SYS_PCA953X_GPIO_VPX1		0x02 /* PU */
+#define CONFIG_SYS_PCA953X_GPIO_VPX2		0x04 /* PU */
+#define CONFIG_SYS_PCA953X_GPIO_VPX3		0x08 /* PU */
+#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL	0x10 /* PD; I2C master source for FRU SEEPROM */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* PCIE1 - VPX P1 */
+#define CONFIG_SYS_PCIE1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
+
+/* PCIE2 - PEX8518 */
+#define CONFIG_SYS_PCIE2_MEM_BASE	0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xe8800000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000	/* 8M */
+
+/*
+ * Networking options
+ */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_NET_MULTI	1
+#define CONFIG_TSEC_TBI
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_ETHPRIME		"eTSEC2"
+
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHY_ADDR		2
+#define TSEC2_PHYIDX		0
+#define CONFIG_HAS_ETH1
+
+/*
+ * Command configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DS4510
+#define CONFIG_CMD_DS4510_INFO
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
+#define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG			/* do not reset board on panic */
+#define CONFIG_PREBOOT				/* enable preboot variable */
+#define CONFIG_FIT		1
+#define CONFIG_FIT_VERBOSE	1
+#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
+
+/*
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02		/* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff     Pri U-Boot (512 KB)
+ * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff     Pri FDT (256KB)
+ * fef00000 - ffefffff     Pri OS image (16MB)
+ * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
+ *
+ * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
+ * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
+ * f7f00000 - f7f3ffff     Sec FDT (256KB)
+ * f6f00000 - f7efffff     Sec OS image (16MB)
+ * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR	MK_STR(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR	MK_STR(0xf7f80000)
+#define CONFIG_FDT1_ENV_ADDR	MK_STR(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR	MK_STR(0xf7f00000)
+#define CONFIG_OS1_ENV_ADDR	MK_STR(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR	MK_STR(0xf6f00000)
+
+#define CONFIG_PROG_UBOOT1						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_UBOOT2						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_BOOT_OS_NET						\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"if test -n $fdtaddr; then "				\
+			"$download_cmd $fdtaddr $fdtfile; "		\
+			"if test $? -eq 0; then "			\
+				"bootm $osaddr - $fdtaddr; "		\
+			"else; "					\
+				"echo FDT DOWNLOAD FAILED; "		\
+			"fi; "						\
+		"else; "						\
+			"bootm $osaddr; "				\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS1							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS2							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT1						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT2						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"autoload=yes\0"						\
+	"download_cmd=tftp\0"						\
+	"console_args=console=ttyS0,115200\0"				\
+	"root_args=root=/dev/nfs rw\0"					\
+	"misc_args=ip=on\0"						\
+	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+	"bootfile=/home/user/file\0"					\
+	"osfile=/home/user/uImage-XPedite5370\0"			\
+	"fdtfile=/home/user/xpedite5370.dtb\0"				\
+	"ubootfile=/home/user/u-boot.bin\0"				\
+	"fdtaddr=c00000\0"						\
+	"osaddr=0x1000000\0"						\
+	"loadaddr=0x1000000\0"						\
+	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
+	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
+	"prog_os1="CONFIG_PROG_OS1"\0"					\
+	"prog_os2="CONFIG_PROG_OS2"\0"					\
+	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
+	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
+	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
+	"bootcmd_flash1=run set_bootargs; "				\
+		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+	"bootcmd_flash2=run set_bootargs; "				\
+		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+	"bootcmd=run bootcmd_flash1\0"
+#endif	/* __CONFIG_H */
diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h
index cbc1ed6..c439068 100644
--- a/include/configs/Yukon8220.h
+++ b/include/configs/Yukon8220.h
@@ -35,8 +35,8 @@
 
 /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
    determine the CPU speed. */
-#define CFG_MPC8220_CLKIN	30000000/* ... running at 30MHz */
-#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
+#define CONFIG_SYS_MPC8220_CLKIN	30000000/* ... running at 30MHz */
+#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	*/
@@ -53,16 +53,16 @@
 
 #ifdef CONFIG_EXTUART_CONSOLE
 #   define CONFIG_CONS_INDEX	1
-#   define CFG_NS16550_SERIAL
-#   define CFG_NS16550
-#   define CFG_NS16550_REG_SIZE 1
-#   define CFG_NS16550_COM1	(CFG_CPLD_BASE + 0x1008)
-#   define CFG_NS16550_CLK	18432000
+#   define CONFIG_SYS_NS16550_SERIAL
+#   define CONFIG_SYS_NS16550
+#   define CONFIG_SYS_NS16550_REG_SIZE 1
+#   define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CPLD_BASE + 0x1008)
+#   define CONFIG_SYS_NS16550_CLK	18432000
 #endif
 
 #define CONFIG_BAUDRATE		115200	    /* ... at 115200 bps */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #define CONFIG_TIMESTAMP			/* Print image info with timestamp */
 
@@ -120,104 +120,104 @@
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1
-#define CFG_I2C_MODULE		1
+#define CONFIG_SYS_I2C_MODULE		1
 
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration
  */
-#define CFG_I2C_EEPROM_ADDR		0x52	/* 1011000xb */
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x52	/* 1011000xb */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
 /*
 #define CONFIG_ENV_IS_IN_EEPROM	1
 #define CONFIG_ENV_OFFSET		0
 #define CONFIG_ENV_SIZE		256
 */
 
-/* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
+/* If CONFIG_SYS_AMD_BOOT is defined, the the system will boot from AMD.
    else undefined it will boot from Intel Strata flash */
-#define CFG_AMD_BOOT		1
+#define CONFIG_SYS_AMD_BOOT		1
 
 /*
  * Flexbus Chipselect configuration
  */
-#if defined (CFG_AMD_BOOT)
-#define CFG_CS0_BASE		0xfff0
-#define CFG_CS0_MASK		0x00080000  /* 512 KB */
-#define CFG_CS0_CTRL		0x003f0d40
-
-#define CFG_CS1_BASE		0xfe00
-#define CFG_CS1_MASK		0x01000000  /* 16 MB */
-#define CFG_CS1_CTRL		0x003f1540
+#if defined (CONFIG_SYS_AMD_BOOT)
+#define CONFIG_SYS_CS0_BASE		0xfff0
+#define CONFIG_SYS_CS0_MASK		0x00080000  /* 512 KB */
+#define CONFIG_SYS_CS0_CTRL		0x003f0d40
+
+#define CONFIG_SYS_CS1_BASE		0xfe00
+#define CONFIG_SYS_CS1_MASK		0x01000000  /* 16 MB */
+#define CONFIG_SYS_CS1_CTRL		0x003f1540
 #else
-#define CFG_CS0_BASE		0xff00
-#define CFG_CS0_MASK		0x01000000  /* 16 MB */
-#define CFG_CS0_CTRL		0x003f1540
+#define CONFIG_SYS_CS0_BASE		0xff00
+#define CONFIG_SYS_CS0_MASK		0x01000000  /* 16 MB */
+#define CONFIG_SYS_CS0_CTRL		0x003f1540
 
-#define CFG_CS1_BASE		0xfe08
-#define CFG_CS1_MASK		0x00080000  /* 512 KB */
-#define CFG_CS1_CTRL		0x003f0d40
+#define CONFIG_SYS_CS1_BASE		0xfe08
+#define CONFIG_SYS_CS1_MASK		0x00080000  /* 512 KB */
+#define CONFIG_SYS_CS1_CTRL		0x003f0d40
 #endif
 
-#define CFG_CS2_BASE		0xf100
-#define CFG_CS2_MASK		0x00040000
-#define CFG_CS2_CTRL		0x003f1140
+#define CONFIG_SYS_CS2_BASE		0xf100
+#define CONFIG_SYS_CS2_MASK		0x00040000
+#define CONFIG_SYS_CS2_CTRL		0x003f1140
 
-#define CFG_CS3_BASE		0xf200
-#define CFG_CS3_MASK		0x00040000
-#define CFG_CS3_CTRL		0x003f1100
+#define CONFIG_SYS_CS3_BASE		0xf200
+#define CONFIG_SYS_CS3_MASK		0x00040000
+#define CONFIG_SYS_CS3_CTRL		0x003f1100
 
 
-#define CFG_FLASH0_BASE		(CFG_CS0_BASE << 16)
-#define CFG_FLASH1_BASE		(CFG_CS1_BASE << 16)
+#define CONFIG_SYS_FLASH0_BASE		(CONFIG_SYS_CS0_BASE << 16)
+#define CONFIG_SYS_FLASH1_BASE		(CONFIG_SYS_CS1_BASE << 16)
 
-#if defined (CFG_AMD_BOOT)
-#define CFG_AMD_BASE		CFG_FLASH0_BASE
-#define CFG_INTEL_BASE		CFG_FLASH1_BASE + 0xf00000
-#define CFG_FLASH_BASE		CFG_AMD_BASE
+#if defined (CONFIG_SYS_AMD_BOOT)
+#define CONFIG_SYS_AMD_BASE		CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_INTEL_BASE		CONFIG_SYS_FLASH1_BASE + 0xf00000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_AMD_BASE
 #else
-#define CFG_INTEL_BASE		CFG_FLASH0_BASE + 0xf00000
-#define CFG_AMD_BASE		CFG_FLASH1_BASE
-#define CFG_FLASH_BASE		CFG_INTEL_BASE
+#define CONFIG_SYS_INTEL_BASE		CONFIG_SYS_FLASH0_BASE + 0xf00000
+#define CONFIG_SYS_AMD_BASE		CONFIG_SYS_FLASH1_BASE
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_INTEL_BASE
 #endif
 
-#define CFG_CPLD_BASE		(CFG_CS2_BASE << 16)
-#define CFG_FPGA_BASE		(CFG_CS3_BASE << 16)
+#define CONFIG_SYS_CPLD_BASE		(CONFIG_SYS_CS2_BASE << 16)
+#define CONFIG_SYS_FPGA_BASE		(CONFIG_SYS_CS3_BASE << 16)
 
 
-#define CFG_MAX_FLASH_BANKS	4	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	4	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
-#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
 
 #define PHYS_AMD_SECT_SIZE	0x00010000 /*  64 KB sectors (x2) */
 #define PHYS_INTEL_SECT_SIZE	0x00020000 /* 128 KB sectors (x2) */
 
-#define CFG_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_CHECKSUM
 /*
  * Environment settings
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#if defined (CFG_AMD_BOOT)
-#define CONFIG_ENV_ADDR		(CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
+#if defined (CONFIG_SYS_AMD_BOOT)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_AMD_SECT_SIZE)
 #define CONFIG_ENV_SIZE		PHYS_AMD_SECT_SIZE
 #define CONFIG_ENV_SECT_SIZE	PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV1_ADDR		(CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
+#define CONFIG_ENV1_ADDR		(CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_INTEL_SECT_SIZE)
 #define CONFIG_ENV1_SIZE		PHYS_INTEL_SECT_SIZE
 #define CONFIG_ENV1_SECT_SIZE	PHYS_INTEL_SECT_SIZE
 #else
-#define CONFIG_ENV_ADDR		(CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_INTEL_SECT_SIZE)
 #define CONFIG_ENV_SIZE		PHYS_INTEL_SECT_SIZE
 #define CONFIG_ENV_SECT_SIZE	PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV1_ADDR		(CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
+#define CONFIG_ENV1_ADDR		(CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_AMD_SECT_SIZE)
 #define CONFIG_ENV1_SIZE		PHYS_AMD_SECT_SIZE
 #define CONFIG_ENV1_SECT_SIZE	PHYS_AMD_SECT_SIZE
 #endif
@@ -235,51 +235,51 @@
 #undef CONFIG_ENV_IS_IN_FLASH
 #endif
 
-#ifndef CFG_JFFS2_FIRST_SECTOR
-#define CFG_JFFS2_FIRST_SECTOR	0
+#ifndef CONFIG_SYS_JFFS2_FIRST_SECTOR
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR	0
 #endif
-#ifndef CFG_JFFS2_FIRST_BANK
-#define CFG_JFFS2_FIRST_BANK	0
+#ifndef CONFIG_SYS_JFFS2_FIRST_BANK
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
 #endif
-#ifndef CFG_JFFS2_NUM_BANKS
-#define CFG_JFFS2_NUM_BANKS	1
+#ifndef CONFIG_SYS_JFFS2_NUM_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
 #endif
-#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
+#define CONFIG_SYS_JFFS2_LAST_BANK (CONFIG_SYS_JFFS2_FIRST_BANK + CONFIG_SYS_JFFS2_NUM_BANKS - 1)
 
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
-#define CFG_SRAM_BASE		(CFG_MBAR + 0x20000)
-#define CFG_SRAM_SIZE		0x8000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_SRAM_BASE		(CONFIG_SYS_MBAR + 0x20000)
+#define CONFIG_SYS_SRAM_SIZE		0x8000
 
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	(CFG_MBAR + 0x20000)
-#define CFG_INIT_RAM_END	0x8000	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MBAR + 0x20000)
+#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in DPRAM */
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10) /* Reserve 256 kB for Monitor   */
-#define CFG_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
-#define CFG_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10) /* Reserve 256 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
 
 /* SDRAM configuration */
-#define CFG_SDRAM_TOTAL_BANKS		2
-#define CFG_SDRAM_SPD_I2C_ADDR		0x51		/* 7bit */
-#define CFG_SDRAM_SPD_SIZE		0x40
-#define CFG_SDRAM_CAS_LATENCY		4		/* (CL=2)x2 */
+#define CONFIG_SYS_SDRAM_TOTAL_BANKS		2
+#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR		0x51		/* 7bit */
+#define CONFIG_SYS_SDRAM_SPD_SIZE		0x40
+#define CONFIG_SYS_SDRAM_CAS_LATENCY		4		/* (CL=2)x2 */
 
 /* SDRAM drive strength register */
-#define CFG_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_LOW  << SDRAMDS_SBE_SHIFT) | \
+#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_LOW  << SDRAMDS_SBE_SHIFT) | \
 					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
 					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBA_SHIFT) | \
 					 (DRIVE_STRENGTH_OFF  << SDRAMDS_SBS_SHIFT) | \
@@ -296,33 +296,33 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			    /* undef to save memory	*/
-#define CFG_PROMPT		"=> "	    /* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			    /* undef to save memory	*/
+#define CONFIG_SYS_PROMPT		"=> "	    /* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	    /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		1024	    /* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE		256	    /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		256	    /* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	    /* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size    */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	    /* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START	0x00100000  /* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000  /* 1 ... 15 MB in DRAM  */
+#define CONFIG_SYS_MEMTEST_START	0x00100000  /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000  /* 1 ... 15 MB in DRAM  */
 
-#define CFG_LOAD_ADDR		0x100000    /* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000    /* default load address */
 
-#define CFG_HZ			1000	    /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	    /* decrementer freq: 1 ms ticks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5   /* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5   /* log base 2 of the above value */
 #endif
 
 /*
  * Various low-level settings
  */
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h
index 59cca0b..9cda3f9 100644
--- a/include/configs/ZPC1900.h
+++ b/include/configs/ZPC1900.h
@@ -73,10 +73,10 @@
  * - Select bus for bd/buffers (see 28-13)
  * - Full duplex
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 
 #endif /* CONFIG_ETHER_INDEX */
 
@@ -146,79 +146,79 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size  */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size  */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x03800000	/* 1 ... 56 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x03800000	/* 1 ... 56 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x400000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_SIZE		64
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		64
 
-#define CFG_IMMR		0xF0000000
-#define CFG_LSDRAM_BASE		0xFC000000
-#define CFG_FLASH_BASE		0xFE000000
-#define CFG_BCSR		0xFEA00000
-#define CFG_EEPROM		0xFEB00000
-#define CFG_FLSIMM_BASE		0xFF000000
+#define CONFIG_SYS_IMMR		0xF0000000
+#define CONFIG_SYS_LSDRAM_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_BCSR		0xFEA00000
+#define CONFIG_SYS_EEPROM		0xFEB00000
+#define CONFIG_SYS_FLSIMM_BASE		0xFF000000
 
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_MAX_FLASH_BANKS	2	/* max num of flash banks	*/
-#define CFG_MAX_FLASH_SECT	32	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of flash banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	32	/* max num of sects on one chip */
 
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLSIMM_BASE }
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLSIMM_BASE }
 
 #define BCSR_PCI_MODE		0x01
 
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* Hard reset configuration word */
-#define CFG_HRCW_MASTER		(HRCW_EBM | HRCW_BPS01| HRCW_CIP          |\
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_EBM | HRCW_BPS01| HRCW_CIP          |\
 				 HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\
 				 HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10     |\
 				 HRCW_MODCK_H0111                          \
 				) /* 0x16848207 */
 /* No slaves */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot                  */
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 #if !defined(CONFIG_ENV_IS_IN_FLASH) && !defined(CONFIG_ENV_IS_IN_NVRAM)
 #define CONFIG_ENV_IS_IN_NVRAM	1
@@ -226,53 +226,53 @@
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #  define CONFIG_ENV_SECT_SIZE	0x10000
-#  define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#  define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #else
-#  define CONFIG_ENV_ADDR		(CFG_EEPROM + 0x400)
+#  define CONFIG_ENV_ADDR		(CONFIG_SYS_EEPROM + 0x400)
 #  define CONFIG_ENV_SIZE		0x1000
-#  define CFG_NVRAM_ACCESS_ROUTINE
+#  define CONFIG_SYS_NVRAM_ACCESS_ROUTINE
 #endif
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
-#define CFG_HID0_INIT		(HID0_ICFI)
-#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
-
-#define CFG_HID2		0
-
-#define CFG_SIUMCR		0x42200000
-#define CFG_SYPCR		0xFFFFFFC3
-#define CFG_BCR			0x90000000
-#define CFG_SCCR		SCCR_DFBRG01
-
-#define CFG_RMR			RMR_CSRE
-#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CFG_RCCR		0
-
-#define CFG_PSDMR		/* 0x834DA43B */0x014DA43A
-#define CFG_PSRT		0x0F/* 0x0C */
-#define CFG_LSDMR		0x0085A562
-#define CFG_LSRT		0x0F
-#define CFG_MPTPR		0x4000
-
-#define CFG_PSDRAM_BR		(CFG_SDRAM_BASE | 0x00000041)
-#define CFG_PSDRAM_OR		0xFC0028C0
-#define CFG_LSDRAM_BR		(CFG_LSDRAM_BASE | 0x00001861)
-#define CFG_LSDRAM_OR		0xFF803480
-
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | 0x00000801)
-#define CFG_OR0_PRELIM		0xFFE00856
-#define CFG_BR5_PRELIM		(CFG_EEPROM | 0x00000801)
-#define CFG_OR5_PRELIM		0xFFFF03F6
-#define CFG_BR6_PRELIM		(CFG_FLSIMM_BASE | 0x00001801)
-#define CFG_OR6_PRELIM		0xFF000856
-#define CFG_BR7_PRELIM		(CFG_BCSR | 0x00000801)
-#define CFG_OR7_PRELIM		0xFFFF83F6
-
-#define CFG_RESET_ADDRESS	0xC0000000
+#define CONFIG_SYS_HID0_INIT		(HID0_ICFI)
+#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
+
+#define CONFIG_SYS_HID2		0
+
+#define CONFIG_SYS_SIUMCR		0x42200000
+#define CONFIG_SYS_SYPCR		0xFFFFFFC3
+#define CONFIG_SYS_BCR			0x90000000
+#define CONFIG_SYS_SCCR		SCCR_DFBRG01
+
+#define CONFIG_SYS_RMR			RMR_CSRE
+#define CONFIG_SYS_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_RCCR		0
+
+#define CONFIG_SYS_PSDMR		/* 0x834DA43B */0x014DA43A
+#define CONFIG_SYS_PSRT		0x0F/* 0x0C */
+#define CONFIG_SYS_LSDMR		0x0085A562
+#define CONFIG_SYS_LSRT		0x0F
+#define CONFIG_SYS_MPTPR		0x4000
+
+#define CONFIG_SYS_PSDRAM_BR		(CONFIG_SYS_SDRAM_BASE | 0x00000041)
+#define CONFIG_SYS_PSDRAM_OR		0xFC0028C0
+#define CONFIG_SYS_LSDRAM_BR		(CONFIG_SYS_LSDRAM_BASE | 0x00001861)
+#define CONFIG_SYS_LSDRAM_OR		0xFF803480
+
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | 0x00000801)
+#define CONFIG_SYS_OR0_PRELIM		0xFFE00856
+#define CONFIG_SYS_BR5_PRELIM		(CONFIG_SYS_EEPROM | 0x00000801)
+#define CONFIG_SYS_OR5_PRELIM		0xFFFF03F6
+#define CONFIG_SYS_BR6_PRELIM		(CONFIG_SYS_FLSIMM_BASE | 0x00001801)
+#define CONFIG_SYS_OR6_PRELIM		0xFF000856
+#define CONFIG_SYS_BR7_PRELIM		(CONFIG_SYS_BCSR | 0x00000801)
+#define CONFIG_SYS_OR7_PRELIM		0xFFFF83F6
+
+#define CONFIG_SYS_RESET_ADDRESS	0xC0000000
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h
index 170553c..08c4ced 100644
--- a/include/configs/ZUMA.h
+++ b/include/configs/ZUMA.h
@@ -28,7 +28,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CFG_GT_6426x        GT_64260 /* with a 64260 system controller */
+#define CONFIG_SYS_GT_6426x        GT_64260 /* with a 64260 system controller */
 #define CONFIG_ETHER_PORT_MII	/* use two MII ports */
 #define CONFIG_INTEL_LXT97X	/* Intel LXT97X phy */
 
@@ -52,12 +52,12 @@
 /* which initialization functions to call for this board */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_BOARD_EARLY_INIT_F
-#define CFG_BOARD_ASM_INIT
+#define CONFIG_SYS_BOARD_ASM_INIT
 
-#define CFG_BOARD_NAME		"Zuma APv2"
+#define CONFIG_SYS_BOARD_NAME		"Zuma APv2"
 
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 /*
  * The following defines let you select what serial you want to use
@@ -65,7 +65,7 @@
  *
  * what to do:
  * to use the DUART, undef CONFIG_MPSC.	 If you have hacked a serial
- * cable onto the second DUART channel, change the CFG_DUART port from 1
+ * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
  * to 0 below.
  *
  * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
@@ -96,7 +96,7 @@
 	"$netmask:$hostname:eth0:none panic=5 && bootm"
 
 #define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
-#define CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 #undef	CONFIG_ALTIVEC			/* undef to disable		*/
@@ -146,29 +146,29 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x00300000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x00300000	/* default load address */
 
-#define CFG_HZ			1000		/* decr freq: 1ms ticks */
+#define CONFIG_SYS_HZ			1000		/* decr freq: 1ms ticks */
 
-#define CFG_BUS_HZ		133000000	/* 133 MHz		*/
+#define CONFIG_SYS_BUS_HZ		133000000	/* 133 MHz		*/
 
-#define CFG_BUS_CLK		CFG_BUS_HZ
+#define CONFIG_SYS_BUS_CLK		CONFIG_SYS_BUS_HZ
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*
  * Low Level Configuration Settings
@@ -179,48 +179,48 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area
  */
-#define CFG_INIT_RAM_ADDR	0x40000000
-#define CFG_INIT_RAM_END	0x1000
-#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_LOCK
 
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xfff00000
-#define CFG_RESET_ADDRESS	0xfff00100
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xfff00000
+#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
 
 /* areas to map different things with the GT in physical space */
-#define CFG_DRAM_BANKS		4
-#define CFG_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */
+#define CONFIG_SYS_DRAM_BANKS		4
+#define CONFIG_SYS_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */
 
 /* What to put in the bats. */
-#define CFG_MISC_REGION_BASE	0xf0000000
+#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
 
 /* Peripheral Device section */
-#define CFG_GT_REGS		0xf8000000	/* later mapped GT_REGS */
-#define CFG_DEV_BASE		0xf0000000
-#define CFG_DEV0_SIZE		_64M /* zuma flash @ 0xf000.0000*/
-#define CFG_DEV1_SIZE		 _8M /* zuma IDE   @ 0xf400.0000 */
-#define CFG_DEV2_SIZE		 _8M /* unused */
-#define CFG_DEV3_SIZE		 _8M /* unused */
-
-#define CFG_DEV0_PAR		0xc498243c
+#define CONFIG_SYS_GT_REGS		0xf8000000	/* later mapped GT_REGS */
+#define CONFIG_SYS_DEV_BASE		0xf0000000
+#define CONFIG_SYS_DEV0_SIZE		_64M /* zuma flash @ 0xf000.0000*/
+#define CONFIG_SYS_DEV1_SIZE		 _8M /* zuma IDE   @ 0xf400.0000 */
+#define CONFIG_SYS_DEV2_SIZE		 _8M /* unused */
+#define CONFIG_SYS_DEV3_SIZE		 _8M /* unused */
+
+#define CONFIG_SYS_DEV0_PAR		0xc498243c
 	/*     c    4     9     8     2	    4     3     c */
 	/* 33 22|2222|22 22|111 1|11 11|1 1  |	   |      */
 	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
 	/* 11|00|0100|10 01|100|0 00|10 0|100 0|011 1|100 */
 	/*  3| 0|.... ..| 1| 4 |  0 |  4 |   8 |   7 | 4  */
 
-#define CFG_DEV1_PAR		0xc01b6ac5
+#define CONFIG_SYS_DEV1_PAR		0xc01b6ac5
 	/*     c    0     1     b     6	    a     c     5 */
 	/* 33 22|2222|22 22|111 1|11 11|1 1  |	   |      */
 	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
@@ -228,18 +228,18 @@
 	/*  3| 0|.... ..| 1| 5 |  5 |  5 |   5 |   8 | 5  */
 
 
-#define CFG_8BIT_BOOT_PAR	0xc00b5e7c
+#define CONFIG_SYS_8BIT_BOOT_PAR	0xc00b5e7c
 
-#define CFG_MPP_CONTROL_0	0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */
-#define CFG_MPP_CONTROL_1	0x00000000 /* GPP[15:12] : GPP[11:8] */
-#define CFG_MPP_CONTROL_2	0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */
-#define CFG_MPP_CONTROL_3	0x00000000 /* GPP[31:28] (int[3:0]) */
+#define CONFIG_SYS_MPP_CONTROL_0	0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */
+#define CONFIG_SYS_MPP_CONTROL_1	0x00000000 /* GPP[15:12] : GPP[11:8] */
+#define CONFIG_SYS_MPP_CONTROL_2	0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */
+#define CONFIG_SYS_MPP_CONTROL_3	0x00000000 /* GPP[31:28] (int[3:0]) */
 					   /* GPP[27:24] (27 is int4, rest are GPP) */
 
-#define CFG_SERIAL_PORT_MUX	0x00001101 /* 11=MPSC1/MPSC0 01=ETH,  0=only MII */
-#define CFG_GPP_LEVEL_CONTROL	0xf8000000 /* interrupt inputs: GPP[31:27] */
+#define CONFIG_SYS_SERIAL_PORT_MUX	0x00001101 /* 11=MPSC1/MPSC0 01=ETH,  0=only MII */
+#define CONFIG_SYS_GPP_LEVEL_CONTROL	0xf8000000 /* interrupt inputs: GPP[31:27] */
 
-#define CFG_SDRAM_CONFIG	0xe4e18200	/* 0x448 */
+#define CONFIG_SYS_SDRAM_CONFIG	0xe4e18200	/* 0x448 */
 				/* idmas use buffer 1,1
 				   comm use buffer 1
 				   pci use buffer 0,0 (pci1->0 pci0->0)
@@ -257,10 +257,10 @@
 				/* 15 14 13:0 */
 				/* 1  0	 0x200 */
 
-#define CFG_DEV0_SPACE		CFG_DEV_BASE
-#define CFG_DEV1_SPACE		(CFG_DEV0_SPACE + CFG_DEV0_SIZE)
-#define CFG_DEV2_SPACE		(CFG_DEV1_SPACE + CFG_DEV1_SIZE)
-#define CFG_DEV3_SPACE		(CFG_DEV2_SPACE + CFG_DEV2_SIZE)
+#define CONFIG_SYS_DEV0_SPACE		CONFIG_SYS_DEV_BASE
+#define CONFIG_SYS_DEV1_SPACE		(CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
+#define CONFIG_SYS_DEV2_SPACE		(CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
+#define CONFIG_SYS_DEV3_SPACE		(CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -275,24 +275,24 @@
 #define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
 
 /* PCI MEMORY MAP section */
-#define CFG_PCI0_MEM_BASE	0x80000000
-#define CFG_PCI0_MEM_SIZE	_128M
-#define CFG_PCI1_MEM_BASE	0x88000000
-#define CFG_PCI1_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
 
-#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
-#define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
+#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
+#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
 
 /* PCI I/O MAP section */
-#define CFG_PCI0_IO_BASE	0xfa000000
-#define CFG_PCI0_IO_SIZE	_16M
-#define CFG_PCI1_IO_BASE	0xfb000000
-#define CFG_PCI1_IO_SIZE	_16M
+#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
+#define CONFIG_SYS_PCI0_IO_SIZE	_16M
+#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
+#define CONFIG_SYS_PCI1_IO_SIZE	_16M
 
-#define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
-#define CFG_PCI0_IO_SPACE_PCI	0x00000000
-#define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
-#define CFG_PCI1_IO_SPACE_PCI	0x00000000
+#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
+#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000
+#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
+#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000
 
 
 /*----------------------------------------------------------------------
@@ -305,49 +305,49 @@
  */
 
 /* SDRAM */
-#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT0U CFG_IBAT0U
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
 
 /* init ram */
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 
 /* PCI0, PCI1 memory space (starting at PCI0 base, mapped in one BAT) */
-#define CFG_IBAT2L BATL_NO_ACCESS
-#define CFG_IBAT2U CFG_DBAT2U
-#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
+#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* GT regs, bootrom, all the devices, PCI I/O */
-#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
 
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	3	/* max number of memory banks	*/
-#define CFG_MAX_FLASH_SECT	130	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* max number of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	130	/* max number of sectors on one chip */
 
-#define CFG_EXTRA_FLASH_DEVICE	DEVICE0 /* extra flash at device 0 */
-#define CFG_EXTRA_FLASH_WIDTH	2	/* 16 bit */
+#define CONFIG_SYS_EXTRA_FLASH_DEVICE	DEVICE0 /* extra flash at device 0 */
+#define CONFIG_SYS_EXTRA_FLASH_WIDTH	2	/* 16 bit */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_CFI		1
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_CFI		1
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
@@ -357,9 +357,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -367,7 +367,7 @@
  * look in include/74xx_7xx.h for the defines used here
  */
 
-#define CFG_L2
+#define CONFIG_SYS_L2
 
 #ifdef CONFIG_750CX
 #define L2_INIT		0
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index 1b1fd29..9ffd86b 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -42,7 +42,7 @@
 #include "amcc-common.h"
 
 /* Detect Acadia PLL input clock automatically via CPLD bit		*/
-#define CONFIG_SYS_CLK_FREQ    ((in8(CFG_CPLD_BASE + 0) == 0x0c) ? \
+#define CONFIG_SYS_CLK_FREQ    ((in8(CONFIG_SYS_CPLD_BASE + 0) == 0x0c) ? \
 				66666666 : 33333000)
 
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
@@ -66,31 +66,31 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE		0xfe000000
-#define CFG_CPLD_BASE		0x80000000
-#define CFG_NAND_ADDR		0xd0000000
-#define CFG_USB_HOST		0xef603000	/* USB OHCI 1.1 controller	*/
+#define CONFIG_SYS_FLASH_BASE		0xfe000000
+#define CONFIG_SYS_CPLD_BASE		0x80000000
+#define CONFIG_SYS_NAND_ADDR		0xd0000000
+#define CONFIG_SYS_USB_HOST		0xef603000	/* USB OHCI 1.1 controller	*/
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer
  *----------------------------------------------------------------------*/
-#define CFG_TEMP_STACK_OCM	1		/* OCM as init ram	*/
+#define CONFIG_SYS_TEMP_STACK_OCM	1		/* OCM as init ram	*/
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xf8000000
-#define CFG_OCM_DATA_SIZE	0x4000			/* 16K of onchip SRAM		*/
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR	/* inside of SRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE	/* End of used area in RAM	*/
+#define CONFIG_SYS_OCM_DATA_ADDR	0xf8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x4000			/* 16K of onchip SRAM		*/
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of SRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE	/* End of used area in RAM	*/
 
-#define CFG_GBL_DATA_SIZE	128			/* size for initial data	*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128			/* size for initial data	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#undef	CFG_EXT_SERIAL_CLOCK			/* external serial clock */
-#define CFG_BASE_BAUD		691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK			/* external serial clock */
+#define CONFIG_SYS_BASE_BAUD		691200
 
 /*-----------------------------------------------------------------------
  * Environment
@@ -106,26 +106,26 @@
  * FLASH related
  *----------------------------------------------------------------------*/
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-#define CFG_FLASH_CFI			/* The flash is CFI compatible	*/
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
 
-#define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #else
-#define	CFG_NO_FLASH		1	/* No NOR on Acadia when NAND-booting	*/
+#define	CONFIG_SYS_NO_FLASH		1	/* No NOR on Acadia when NAND-booting	*/
 #endif
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x40000 /* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -151,69 +151,68 @@
  * set up. While still running from cache, I experienced problems accessing
  * the NAND controller.	sr - 2006-08-25
  */
-#define CFG_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
-#define CFG_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
-#define CFG_NAND_BOOT_SPL_DST	(CFG_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
-#define CFG_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
-#define CFG_NAND_U_BOOT_START	CFG_NAND_U_BOOT_DST /* Start NUB from this addr	*/
-#define CFG_NAND_BOOT_SPL_DELTA	(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
+#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
+#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
+#define CONFIG_SYS_NAND_BOOT_SPL_DST	(CONFIG_SYS_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr	*/
+#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 
 /*
  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
  */
-#define CFG_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
-#define CFG_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/
 
 /*
  * Now the NAND chip has to be defined (no autodetection used!)
  */
-#define CFG_NAND_PAGE_SIZE	512		/* NAND chip page size		*/
-#define CFG_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
-#define CFG_NAND_PAGE_COUNT	32		/* NAND chip page count		*/
-#define CFG_NAND_BAD_BLOCK_POS	5		/* Location of bad block marker	*/
-#undef CFG_NAND_4_ADDR_CYCLE			/* No fourth addr used (<=32MB)	*/
-
-#define CFG_NAND_ECCSIZE	256
-#define CFG_NAND_ECCBYTES	3
-#define CFG_NAND_ECCSTEPS	(CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
-#define CFG_NAND_OOBSIZE	16
-#define CFG_NAND_ECCTOTAL	(CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
-#define CFG_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
+#define CONFIG_SYS_NAND_PAGE_SIZE	512		/* NAND chip page size		*/
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
+#define CONFIG_SYS_NAND_PAGE_COUNT	32		/* NAND chip page count		*/
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	5		/* Location of bad block marker	*/
+#undef CONFIG_SYS_NAND_4_ADDR_CYCLE			/* No fourth addr used (<=32MB)	*/
+
+#define CONFIG_SYS_NAND_ECCSIZE	256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_OOBSIZE	16
+#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
+#define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
 
 #ifdef CONFIG_ENV_IS_IN_NAND
 /*
  * For NAND booting the environment is embedded in the U-Boot image. Please take
  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
  */
-#define CONFIG_ENV_SIZE		CFG_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(CFG_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 #endif
 
 /*-----------------------------------------------------------------------
  * RAM (CRAM)
  *----------------------------------------------------------------------*/
-#define CFG_MBYTES_RAM		64		/* 64MB			*/
+#define CONFIG_SYS_MBYTES_RAM		64		/* 64MB			*/
 
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
 
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 
 /* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
 #define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
 #define CONFIG_DTT_AD7414	1		/* use AD7414		*/
 #define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
-#define CFG_DTT_MAX_TEMP	70
-#define CFG_DTT_LOW_TEMP	-30
-#define CFG_DTT_HYSTERESIS	3
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
 
 /*-----------------------------------------------------------------------
  * Ethernet
@@ -262,64 +261,63 @@
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/
-#define CFG_MAX_NAND_DEVICE	1
-#define NAND_MAX_CHIPS		1
-#define CFG_NAND_BASE		(CFG_NAND_ADDR + CFG_NAND_CS)
-#define CFG_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
+#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-#define CFG_NAND_CS		3
+#define CONFIG_SYS_NAND_CS		3
 /* Memory Bank 0 (Flash) initialization						*/
-#define CFG_EBC_PB0AP		0x03337200
-#define CFG_EBC_PB0CR		0xfe0bc000
+#define CONFIG_SYS_EBC_PB0AP		0x03337200
+#define CONFIG_SYS_EBC_PB0CR		0xfe0bc000
 
 /* Memory Bank 3 (NAND-FLASH) initialization					*/
-#define CFG_EBC_PB3AP		0x018003c0
-#define CFG_EBC_PB3CR		(CFG_NAND_ADDR | 0x1c000)
+#define CONFIG_SYS_EBC_PB3AP		0x018003c0
+#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
 
 /* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
 /* Memory Bank 1 (CRAM) initialization						*/
-#define CFG_EBC_PB1AP		0x030400c0
-#define CFG_EBC_PB1CR		0x000bc000
+#define CONFIG_SYS_EBC_PB1AP		0x030400c0
+#define CONFIG_SYS_EBC_PB1CR		0x000bc000
 
 /* Memory Bank 2 (CRAM) initialization						*/
-#define CFG_EBC_PB2AP		0x030400c0
-#define CFG_EBC_PB2CR		0x020bc000
+#define CONFIG_SYS_EBC_PB2AP		0x030400c0
+#define CONFIG_SYS_EBC_PB2CR		0x020bc000
 #else
-#define CFG_NAND_CS		0		/* NAND chip connected to CSx	*/
+#define CONFIG_SYS_NAND_CS		0		/* NAND chip connected to CSx	*/
 /* Memory Bank 0 (NAND-FLASH) initialization					*/
-#define CFG_EBC_PB0AP		0x018003c0
-#define CFG_EBC_PB0CR		(CFG_NAND_ADDR | 0x1c000)
+#define CONFIG_SYS_EBC_PB0AP		0x018003c0
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
 
 /*
  * When NAND-booting the CRAM EBC setup must be done in sync mode, since the
  * NAND-SPL already initialized the CRAM and EBC to sync mode.
  */
 /* Memory Bank 1 (CRAM) initialization						*/
-#define CFG_EBC_PB1AP		0x9C0201C0
-#define CFG_EBC_PB1CR		0x000bc000
+#define CONFIG_SYS_EBC_PB1AP		0x9C0201C0
+#define CONFIG_SYS_EBC_PB1CR		0x000bc000
 
 /* Memory Bank 2 (CRAM) initialization						*/
-#define CFG_EBC_PB2AP		0x9C0201C0
-#define CFG_EBC_PB2CR		0x020bc000
+#define CONFIG_SYS_EBC_PB2AP		0x9C0201C0
+#define CONFIG_SYS_EBC_PB2CR		0x020bc000
 #endif
 
 /* Memory Bank 4 (CPLD) initialization						*/
-#define CFG_EBC_PB4AP		0x04006000
-#define CFG_EBC_PB4CR		(CFG_CPLD_BASE | 0x18000)
+#define CONFIG_SYS_EBC_PB4AP		0x04006000
+#define CONFIG_SYS_EBC_PB4CR		(CONFIG_SYS_CPLD_BASE | 0x18000)
 
-#define CFG_EBC_CFG		0xf8400000
+#define CONFIG_SYS_EBC_CFG		0xf8400000
 
 /*-----------------------------------------------------------------------
  * GPIO Setup
  *----------------------------------------------------------------------*/
-#define CFG_GPIO_CRAM_CLK	8
-#define CFG_GPIO_CRAM_WAIT	9		/* GPIO-In		*/
-#define CFG_GPIO_CRAM_ADV	10
-#define CFG_GPIO_CRAM_CRE	(32 + 21)	/* GPIO-Out		*/
+#define CONFIG_SYS_GPIO_CRAM_CLK	8
+#define CONFIG_SYS_GPIO_CRAM_WAIT	9		/* GPIO-In		*/
+#define CONFIG_SYS_GPIO_CRAM_ADV	10
+#define CONFIG_SYS_GPIO_CRAM_CRE	(32 + 21)	/* GPIO-Out		*/
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO_0 setup (PPC405EZ specific)
@@ -341,13 +339,13 @@
  * GPIO0[28-30]	- Trace Outputs / PWM Inputs
  * GPIO0[31]	- PWM_8 I/O
  */
-#define CFG_GPIO0_TCR		0xC0A00000
-#define CFG_GPIO0_OSRL		0x50004400
-#define CFG_GPIO0_OSRH		0x02000055
-#define CFG_GPIO0_ISR1L		0x00001000
-#define CFG_GPIO0_ISR1H		0x00000055
-#define CFG_GPIO0_TSRL		0x02000000
-#define CFG_GPIO0_TSRH		0x00000055
+#define CONFIG_SYS_GPIO0_TCR		0xC0A00000
+#define CONFIG_SYS_GPIO0_OSRL		0x50004400
+#define CONFIG_SYS_GPIO0_OSRH		0x02000055
+#define CONFIG_SYS_GPIO0_ISR1L		0x00001000
+#define CONFIG_SYS_GPIO0_ISR1H		0x00000055
+#define CONFIG_SYS_GPIO0_TSRL		0x02000000
+#define CONFIG_SYS_GPIO0_TSRH		0x00000055
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO_1 setup (PPC405EZ specific)
@@ -363,12 +361,12 @@
  * GPIO1[16]	- SPI_SS_1_N Output
  * GPIO1[17-20]	- Trace Output/External Interrupts IRQ0 - IRQ3 inputs
  */
-#define CFG_GPIO1_TCR		0xFFFF8414
-#define CFG_GPIO1_OSRL		0x40000110
-#define CFG_GPIO1_OSRH		0x55455555
-#define CFG_GPIO1_ISR1L		0x15555445
-#define CFG_GPIO1_ISR1H		0x00000000
-#define CFG_GPIO1_TSRL		0x00000000
-#define CFG_GPIO1_TSRH		0x00000000
+#define CONFIG_SYS_GPIO1_TCR		0xFFFF8414
+#define CONFIG_SYS_GPIO1_OSRL		0x40000110
+#define CONFIG_SYS_GPIO1_OSRH		0x55455555
+#define CONFIG_SYS_GPIO1_ISR1L		0x15555445
+#define CONFIG_SYS_GPIO1_ISR1H		0x00000000
+#define CONFIG_SYS_GPIO1_TSRL		0x00000000
+#define CONFIG_SYS_GPIO1_TSRH		0x00000000
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/actux1.h b/include/configs/actux1.h
index ec1d469..adbc399 100644
--- a/include/configs/actux1.h
+++ b/include/configs/actux1.h
@@ -39,7 +39,8 @@
 #define CONFIG_DISPLAY_CPUINFO		1
 #define CONFIG_DISPLAY_BOARDINFO	1
 
-#define CFG_IXP425_CONSOLE		IXP425_UART2
+#define CONFIG_IXP_SERIAL
+#define CONFIG_SYS_IXP425_CONSOLE		IXP425_UART2
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
@@ -52,9 +53,9 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_SIZE		128
+#define CONFIG_SYS_GBL_DATA_SIZE		128
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -80,30 +81,30 @@
 #endif
 
 /* Miscellaneous configurable options */
-#define CFG_LONGHELP
-#define CFG_PROMPT			"=> "
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT			"=> "
 /* Console I/O Buffer Size */
-#define CFG_CBSIZE			256
+#define CONFIG_SYS_CBSIZE			256
 /* Print Buffer Size */
-#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 /* max number of command args */
-#define CFG_MAXARGS			16
+#define CONFIG_SYS_MAXARGS			16
 /* Boot Argument Buffer Size */
-#define CFG_BARGSIZE			CFG_CBSIZE
+#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
 
-#define CFG_MEMTEST_START		0x00400000
-#define CFG_MEMTEST_END			0x00800000
+#define CONFIG_SYS_MEMTEST_START		0x00400000
+#define CONFIG_SYS_MEMTEST_END			0x00800000
 
 /* everything, incl board info, in Hz */
-#undef  CFG_CLKS_IN_HZ
+#undef  CONFIG_SYS_CLKS_IN_HZ
 /* spec says 66.666 MHz, but it appears to be 33 */
-#define CFG_HZ				3333333
+#define CONFIG_SYS_HZ				3333333
 
 /* default load address */
-#define CFG_LOAD_ADDR			0x00010000
+#define CONFIG_SYS_LOAD_ADDR			0x00010000
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600,	\
+#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600,	\
 					  115200, 230400 }
 #define CONFIG_SERIAL_RTS_ACTIVE	1
 
@@ -118,69 +119,67 @@
 #endif
 
 /* Expansion bus settings */
-#define CFG_EXP_CS0			0xbd113842
+#define CONFIG_SYS_EXP_CS0			0xbd113842
 
 /* SDRAM settings */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM_1			0x00000000
-#define CFG_DRAM_BASE			0x00000000
+#define CONFIG_SYS_DRAM_BASE			0x00000000
 
 #if CONFIG_ACTUX1_32MB
-# define CFG_SDR_CONFIG			0x18
+# define CONFIG_SYS_SDR_CONFIG			0x18
 # define PHYS_SDRAM_1_SIZE		0x02000000
-# define CFG_SDRAM_REFRESH_CNT		0x81a
-# define CFG_SDR_MODE_CONFIG		0x1
-# define CFG_DRAM_SIZE			0x02000000
+# define CONFIG_SYS_SDRAM_REFRESH_CNT		0x81a
+# define CONFIG_SYS_SDR_MODE_CONFIG		0x1
+# define CONFIG_SYS_DRAM_SIZE			0x02000000
 #else /* 16MB SDRAM */
-# define CFG_SDR_CONFIG			0x3A
+# define CONFIG_SYS_SDR_CONFIG			0x3A
 # define PHYS_SDRAM_1_SIZE		0x01000000
-# define CFG_SDRAM_REFRESH_CNT		0x81a
-# define CFG_SDR_MODE_CONFIG		0x1
-# define CFG_DRAM_SIZE			0x01000000
+# define CONFIG_SYS_SDRAM_REFRESH_CNT		0x81a
+# define CONFIG_SYS_SDR_MODE_CONFIG		0x1
+# define CONFIG_SYS_DRAM_SIZE			0x01000000
 #endif
 
 /* FLASH organization */
 #if CONFIG_ACTUX1_FLASH2X2
-# define CFG_MAX_FLASH_BANKS		2
+# define CONFIG_SYS_MAX_FLASH_BANKS		2
 /* max number of sectors on one chip */
-# define CFG_MAX_FLASH_SECT		40
+# define CONFIG_SYS_MAX_FLASH_SECT		40
 # define PHYS_FLASH_1			0x50000000
 # define PHYS_FLASH_2			0x50200000
-# define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH_1, PHYS_FLASH_2 }
+# define CONFIG_SYS_FLASH_BANKS_LIST		{ PHYS_FLASH_1, PHYS_FLASH_2 }
 #endif
 #if CONFIG_ACTUX1_FLASH1X8
-# define CFG_MAX_FLASH_BANKS		1
+# define CONFIG_SYS_MAX_FLASH_BANKS		1
 /* max number of sectors on one chip */
-# define CFG_MAX_FLASH_SECT		140
+# define CONFIG_SYS_MAX_FLASH_SECT		140
 # define PHYS_FLASH_1			0x50000000
-# define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH_1 }
+# define CONFIG_SYS_FLASH_BANKS_LIST		{ PHYS_FLASH_1 }
 #endif
 
-#define CFG_FLASH_BASE			PHYS_FLASH_1
-#define CFG_MONITOR_BASE		PHYS_FLASH_1
-#define CFG_MONITOR_LEN			(256 << 10)
+#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_LEN			(256 << 10)
 
 /* Use common CFI driver */
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
 /* no byte writes on IXP4xx */
-#define CFG_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
 /* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 /* Ethernet */
 
 /* include IXP4xx NPE support */
 #define CONFIG_IXP4XX_NPE		1
-/* use separate flash sector with ucode images */
-#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE	0x50040000
 #define CONFIG_NET_MULTI		1
 /* NPE0 PHY address */
 #define	CONFIG_PHY_ADDR			0
 /* MII PHY management */
 #define CONFIG_MII			1
 /* Number of ethernet rx buffers & descriptors */
-#define CFG_RX_ETH_BUFFER		16
+#define CONFIG_SYS_RX_ETH_BUFFER		16
 #define CONFIG_RESET_PHY_R		1
 
 #define CONFIG_CMD_DHCP
@@ -196,7 +195,7 @@
 #define CONFIG_BOOTP_HOSTNAME
 
 /* Cache Configuration */
-#define CFG_CACHELINE_SIZE		32
+#define CONFIG_SYS_CACHELINE_SIZE		32
 
 /*
  * environment organization:
@@ -205,9 +204,10 @@
 #define	CONFIG_ENV_IS_IN_FLASH		1
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x4000)
-#define CFG_USE_PPCENV			1
+#define CONFIG_SYS_USE_PPCENV			1
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	"npe_ucode=50040000\0"						\
 	"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
 	"kerneladdr=50050000\0"						\
 	"rootaddr=50170000\0"						\
diff --git a/include/configs/actux2.h b/include/configs/actux2.h
index a3f5a4a..4c579eb 100644
--- a/include/configs/actux2.h
+++ b/include/configs/actux2.h
@@ -32,7 +32,8 @@
 #define CONFIG_DISPLAY_CPUINFO		1
 #define CONFIG_DISPLAY_BOARDINFO	1
 
-#define CFG_IXP425_CONSOLE		IXP425_UART2
+#define CONFIG_IXP_SERIAL
+#define CONFIG_SYS_IXP425_CONSOLE		IXP425_UART2
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_BOOTDELAY		5
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
@@ -43,9 +44,9 @@
 #undef CONFIG_USE_IRQ
 
 /* Size of malloc() pool */
-#define CFG_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_SIZE		128
+#define CONFIG_SYS_GBL_DATA_SIZE		128
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -71,30 +72,30 @@
 #endif
 
 /* Miscellaneous configurable options */
-#define CFG_LONGHELP
-#define CFG_PROMPT			"=> "
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT			"=> "
 /* Console I/O Buffer Size */
-#define CFG_CBSIZE			256
+#define CONFIG_SYS_CBSIZE			256
 /* Print Buffer Size */
-#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 /* max number of command args */
-#define CFG_MAXARGS			16
+#define CONFIG_SYS_MAXARGS			16
 /* Boot Argument Buffer Size */
-#define CFG_BARGSIZE			CFG_CBSIZE
+#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
 
-#define CFG_MEMTEST_START		0x00400000
-#define CFG_MEMTEST_END			0x00800000
+#define CONFIG_SYS_MEMTEST_START		0x00400000
+#define CONFIG_SYS_MEMTEST_END			0x00800000
 
 /* everything, incl board info, in Hz */
-#undef  CFG_CLKS_IN_HZ
+#undef  CONFIG_SYS_CLKS_IN_HZ
 /* spec says 66.666 MHz, but it appears to be 33 */
-#define CFG_HZ				3333333
+#define CONFIG_SYS_HZ				3333333
 
 /* default load address */
-#define CFG_LOAD_ADDR			0x00010000
+#define CONFIG_SYS_LOAD_ADDR			0x00010000
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, \
+#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, \
 					  115200, 230400 }
 #define CONFIG_SERIAL_RTS_ACTIVE	1
 
@@ -109,53 +110,51 @@
 #endif
 
 /* Expansion bus settings */
-#define CFG_EXP_CS0			0xbd113042
+#define CONFIG_SYS_EXP_CS0			0xbd113042
 
 /* SDRAM settings */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM_1			0x00000000
-#define CFG_DRAM_BASE			0x00000000
+#define CONFIG_SYS_DRAM_BASE			0x00000000
 
 /* 16MB SDRAM */
-#define CFG_SDR_CONFIG			0x3A
+#define CONFIG_SYS_SDR_CONFIG			0x3A
 #define PHYS_SDRAM_1_SIZE		0x01000000
-#define CFG_SDRAM_REFRESH_CNT		0x81a
-#define CFG_SDR_MODE_CONFIG		0x1
-#define CFG_DRAM_SIZE			0x01000000
+#define CONFIG_SYS_SDRAM_REFRESH_CNT		0x81a
+#define CONFIG_SYS_SDR_MODE_CONFIG		0x1
+#define CONFIG_SYS_DRAM_SIZE			0x01000000
 
 /* FLASH organization */
-#define CFG_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
 /* max number of sectors on one chip */
-#define CFG_MAX_FLASH_SECT		140
+#define CONFIG_SYS_MAX_FLASH_SECT		140
 #define PHYS_FLASH_1			0x50000000
-#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH_1 }
+#define CONFIG_SYS_FLASH_BANKS_LIST		{ PHYS_FLASH_1 }
 
-#define CFG_FLASH_BASE			PHYS_FLASH_1
-#define CFG_MONITOR_BASE		PHYS_FLASH_1
-#define CFG_MONITOR_LEN			(256 << 10)
+#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_LEN			(256 << 10)
 
 /* Use common CFI driver */
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
 /* no byte writes on IXP4xx */
-#define CFG_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
 
 /* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 /* Ethernet */
 
 /* include IXP4xx NPE support */
 #define CONFIG_IXP4XX_NPE		1
-/* use separate flash sector with ucode images */
-#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE	0x50040000
 #define CONFIG_NET_MULTI		1
 /* NPE0 PHY address */
 #define	CONFIG_PHY_ADDR			0x00
 /* MII PHY management */
 #define CONFIG_MII			1
 /* Number of ethernet rx buffers & descriptors */
-#define CFG_RX_ETH_BUFFER		16
+#define CONFIG_SYS_RX_ETH_BUFFER		16
 #define CONFIG_RESET_PHY_R		1
 /* ethernet switch connected to MII port */
 #define CONFIG_MII_ETHSWITCH		1
@@ -173,7 +172,7 @@
 #define CONFIG_BOOTP_HOSTNAME
 
 /* Cache Configuration */
-#define CFG_CACHELINE_SIZE		32
+#define CONFIG_SYS_CACHELINE_SIZE		32
 
 /*
  * environment organization:
@@ -182,9 +181,10 @@
 #define	CONFIG_ENV_IS_IN_FLASH		1
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x4000)
-#define CFG_USE_PPCENV			1
+#define CONFIG_SYS_USE_PPCENV			1
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
+	"npe_ucode=50040000\0"						\
 	"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
 	"kerneladdr=50050000\0"						\
 	"rootaddr=50170000\0"						\
diff --git a/include/configs/actux3.h b/include/configs/actux3.h
index fc2d02f..694f522 100644
--- a/include/configs/actux3.h
+++ b/include/configs/actux3.h
@@ -32,7 +32,8 @@
 #define CONFIG_DISPLAY_CPUINFO		1
 #define CONFIG_DISPLAY_BOARDINFO	1
 
-#define CFG_IXP425_CONSOLE		IXP425_UART2
+#define CONFIG_IXP_SERIAL
+#define CONFIG_SYS_IXP425_CONSOLE		IXP425_UART2
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
@@ -43,9 +44,9 @@
 #undef CONFIG_USE_IRQ
 
 /* Size of malloc() pool */
-#define CFG_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_SIZE		128
+#define CONFIG_SYS_GBL_DATA_SIZE		128
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -69,30 +70,30 @@
 #endif
 
 /* Miscellaneous configurable options */
-#define CFG_LONGHELP
-#define CFG_PROMPT			"=> "
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT			"=> "
 /* Console I/O Buffer Size */
-#define CFG_CBSIZE			256
+#define CONFIG_SYS_CBSIZE			256
 /* Print Buffer Size */
-#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 /* max number of command args */
-#define CFG_MAXARGS			16
+#define CONFIG_SYS_MAXARGS			16
 /* Boot Argument Buffer Size */
-#define CFG_BARGSIZE			CFG_CBSIZE
+#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
 
-#define CFG_MEMTEST_START		0x00400000
-#define CFG_MEMTEST_END			0x00800000
+#define CONFIG_SYS_MEMTEST_START		0x00400000
+#define CONFIG_SYS_MEMTEST_END			0x00800000
 
 /* everything, incl board info, in Hz */
-#undef  CFG_CLKS_IN_HZ
+#undef  CONFIG_SYS_CLKS_IN_HZ
 /* spec says 66.666 MHz, but it appears to be 33 */
-#define CFG_HZ				3333333
+#define CONFIG_SYS_HZ				3333333
 
 /* default load address */
-#define CFG_LOAD_ADDR			0x00010000
+#define CONFIG_SYS_LOAD_ADDR			0x00010000
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, \
+#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, \
 					  115200, 230400 }
 #define CONFIG_SERIAL_RTS_ACTIVE	1
 
@@ -108,46 +109,44 @@
 #endif
 
 /* Expansion bus settings */
-#define CFG_EXP_CS0			0xbd113442
+#define CONFIG_SYS_EXP_CS0			0xbd113442
 
 /* SDRAM settings */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM_1			0x00000000
-#define CFG_DRAM_BASE			0x00000000
+#define CONFIG_SYS_DRAM_BASE			0x00000000
 
 /* 16MB SDRAM */
-#define CFG_SDR_CONFIG			0x3A
+#define CONFIG_SYS_SDR_CONFIG			0x3A
 #define PHYS_SDRAM_1_SIZE		0x01000000
-#define CFG_SDRAM_REFRESH_CNT		0x81a
-#define CFG_SDR_MODE_CONFIG		0x1
-#define CFG_DRAM_SIZE			0x01000000
+#define CONFIG_SYS_SDRAM_REFRESH_CNT		0x81a
+#define CONFIG_SYS_SDR_MODE_CONFIG		0x1
+#define CONFIG_SYS_DRAM_SIZE			0x01000000
 
 /* FLASH organization */
-#define CFG_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
 /* max number of sectors on one chip */
-#define CFG_MAX_FLASH_SECT		140
+#define CONFIG_SYS_MAX_FLASH_SECT		140
 #define PHYS_FLASH_1			0x50000000
-#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH_1 }
+#define CONFIG_SYS_FLASH_BANKS_LIST		{ PHYS_FLASH_1 }
 
-#define CFG_FLASH_BASE			PHYS_FLASH_1
-#define CFG_MONITOR_BASE		PHYS_FLASH_1
-#define CFG_MONITOR_LEN			(256 << 10)
+#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_LEN			(256 << 10)
 
 /* Use common CFI driver */
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
 /* no byte writes on IXP4xx */
-#define CFG_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
 
 /* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 /* Ethernet */
 
 /* include IXP4xx NPE support */
 #define CONFIG_IXP4XX_NPE		1
-/* use separate flash sector with ucode images */
-#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE	0x50040000
 
 #define CONFIG_NET_MULTI		1
 /* NPE0 PHY address */
@@ -155,7 +154,7 @@
 /* MII PHY management */
 #define CONFIG_MII			1
 /* Number of ethernet rx buffers & descriptors */
-#define CFG_RX_ETH_BUFFER		16
+#define CONFIG_SYS_RX_ETH_BUFFER		16
 #define CONFIG_RESET_PHY_R		1
 /* ethernet switch connected to MII port */
 #define CONFIG_MII_ETHSWITCH		1
@@ -173,7 +172,7 @@
 #define CONFIG_BOOTP_HOSTNAME
 
 /* Cache Configuration */
-#define CFG_CACHELINE_SIZE		32
+#define CONFIG_SYS_CACHELINE_SIZE		32
 
 /*
  * environment organization:
@@ -182,9 +181,10 @@
 #define	CONFIG_ENV_IS_IN_FLASH		1
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x4000)
-#define CFG_USE_PPCENV			1
+#define CONFIG_SYS_USE_PPCENV			1
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
+	"npe_ucode=50040000\0"						\
 	"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
 	"kerneladdr=50050000\0"						\
 	"rootaddr=50170000\0"						\
diff --git a/include/configs/actux4.h b/include/configs/actux4.h
index 83bd7f5..cdc9956 100644
--- a/include/configs/actux4.h
+++ b/include/configs/actux4.h
@@ -32,7 +32,8 @@
 #define CONFIG_DISPLAY_CPUINFO		1
 #define CONFIG_DISPLAY_BOARDINFO	1
 
-#define CFG_IXP425_CONSOLE		IXP425_UART1
+#define CONFIG_IXP_SERIAL
+#define CONFIG_SYS_IXP425_CONSOLE		IXP425_UART1
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
@@ -43,9 +44,9 @@
 #undef CONFIG_USE_IRQ
 
 /* Size of malloc() pool */
-#define CFG_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_SIZE		128
+#define CONFIG_SYS_GBL_DATA_SIZE		128
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -68,30 +69,30 @@
 #endif
 
 /* Miscellaneous configurable options */
-#define CFG_LONGHELP
-#define CFG_PROMPT			"=> "
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT			"=> "
 /* Console I/O Buffer Size */
-#define CFG_CBSIZE			256
+#define CONFIG_SYS_CBSIZE			256
 /* Print Buffer Size */
-#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 /* max number of command args */
-#define CFG_MAXARGS			16
+#define CONFIG_SYS_MAXARGS			16
 /* Boot Argument Buffer Size */
-#define CFG_BARGSIZE			CFG_CBSIZE
+#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
 
-#define CFG_MEMTEST_START		0x00400000
-#define CFG_MEMTEST_END			0x00800000
+#define CONFIG_SYS_MEMTEST_START		0x00400000
+#define CONFIG_SYS_MEMTEST_END			0x00800000
 
 /* everything, incl board info, in Hz */
-#undef  CFG_CLKS_IN_HZ
+#undef  CONFIG_SYS_CLKS_IN_HZ
 /* spec says 66.666 MHz, but it appears to be 33 */
-#define CFG_HZ				3333333
+#define CONFIG_SYS_HZ				3333333
 
 /* default load address */
-#define CFG_LOAD_ADDR			0x00010000
+#define CONFIG_SYS_LOAD_ADDR			0x00010000
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, \
+#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, \
 					  115200, 230400 }
 #define CONFIG_SERIAL_RTS_ACTIVE	1
 
@@ -106,51 +107,49 @@
 #endif
 
 /* Expansion bus settings */
-#define CFG_EXP_CS0			0xbd113003
+#define CONFIG_SYS_EXP_CS0			0xbd113003
 
 /* SDRAM settings */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM_1			0x00000000
-#define CFG_DRAM_BASE			0x00000000
+#define CONFIG_SYS_DRAM_BASE			0x00000000
 
 /* 32MB SDRAM */
-#define CFG_SDR_CONFIG			0x18
+#define CONFIG_SYS_SDR_CONFIG			0x18
 #define PHYS_SDRAM_1_SIZE		0x02000000
-#define CFG_SDRAM_REFRESH_CNT		0x81a
-#define CFG_SDR_MODE_CONFIG		0x1
-#define CFG_DRAM_SIZE			0x02000000
+#define CONFIG_SYS_SDRAM_REFRESH_CNT		0x81a
+#define CONFIG_SYS_SDR_MODE_CONFIG		0x1
+#define CONFIG_SYS_DRAM_SIZE			0x02000000
 
 /* FLASH organization */
-#define CFG_MAX_FLASH_BANKS		2
+#define CONFIG_SYS_MAX_FLASH_BANKS		2
 /* max # of sectors per chip */
-#define CFG_MAX_FLASH_SECT		70
+#define CONFIG_SYS_MAX_FLASH_SECT		70
 #define PHYS_FLASH_1			0x50000000
 #define PHYS_FLASH_2			0x51000000
-#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH_1, PHYS_FLASH_2 }
+#define CONFIG_SYS_FLASH_BANKS_LIST		{ PHYS_FLASH_1, PHYS_FLASH_2 }
 
-#define CFG_FLASH_BASE			PHYS_FLASH_1
-#define CFG_MONITOR_BASE		PHYS_FLASH_1
-#define CFG_MONITOR_LEN			(252 << 10)
+#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_LEN			(252 << 10)
 
 /* Use common CFI driver */
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
 /* board provides its own flash_init code */
 #define CONFIG_FLASH_CFI_LEGACY		1
 /* no byte writes on IXP4xx */
-#define CFG_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
 /* SST 39VF020 etc. support */
-#define CFG_FLASH_LEGACY_256Kx8	1
+#define CONFIG_SYS_FLASH_LEGACY_256Kx8	1
 
 /* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 /* Ethernet */
 
 /* include IXP4xx NPE support */
 #define CONFIG_IXP4XX_NPE		1
-/* use separate flash sector with ucode images */
-#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE	0x51000000
 
 #define CONFIG_NET_MULTI		1
 /* NPE0 PHY address */
@@ -158,7 +157,7 @@
 /* MII PHY management */
 #define CONFIG_MII			1
 /* Number of ethernet rx buffers & descriptors */
-#define CFG_RX_ETH_BUFFER		16
+#define CONFIG_SYS_RX_ETH_BUFFER		16
 
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_NET
@@ -173,7 +172,7 @@
 #define CONFIG_BOOTP_HOSTNAME
 
 /* Cache Configuration */
-#define CFG_CACHELINE_SIZE		32
+#define CONFIG_SYS_CACHELINE_SIZE		32
 
 /* environment organization: one complete 4k flash sector */
 #define	CONFIG_ENV_IS_IN_FLASH		1
@@ -181,6 +180,7 @@
 #define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x3f000)
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
+	"npe_ucode=51000000\0"						\
 	"mtd=IXP4XX-Flash.0:252k(uboot),4k(uboot_env);"			\
 	"IXP4XX-Flash.1:128k(ucode),1280k(linux),-(root)\0"		\
 	"kerneladdr=51020000\0"						\
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index d6f7e02..8fda3f2 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -47,6 +47,7 @@
 #define CONFIG_E300		1	/* E300 Family */
 #define CONFIG_MPC512X		1	/* MPC512X family */
 #define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
+#undef CONFIG_FSL_DIU_LOGO_BMP		/* Don't include FSL DIU binary bmp */
 
 /* video */
 #undef CONFIG_VIDEO
@@ -59,31 +60,31 @@
 /* CONFIG_PCI is defined at config time */
 
 #ifdef CONFIG_ADS5121_REV2
-#define CFG_MPC512X_CLKIN	66000000	/* in Hz */
+#define CONFIG_SYS_MPC512X_CLKIN	66000000	/* in Hz */
 #else
-#define CFG_MPC512X_CLKIN	33333333	/* in Hz */
+#define CONFIG_SYS_MPC512X_CLKIN	33333333	/* in Hz */
 #define CONFIG_PCI
 #endif
 
 #define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */
 #define CONFIG_MISC_INIT_R
 
-#define CFG_IMMR		0x80000000
-#define CFG_DIU_ADDR		(CFG_IMMR+0x2100)
+#define CONFIG_SYS_IMMR		0x80000000
+#define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_IMMR+0x2100)
 
-#define CFG_MEMTEST_START	0x00200000      /* memtest region */
-#define CFG_MEMTEST_END		0x00400000
+#define CONFIG_SYS_MEMTEST_START	0x00200000      /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
 
 /*
  * DDR Setup - manually set all parameters as there's no SPD etc.
  */
 #ifdef CONFIG_ADS5121_REV2
-#define CFG_DDR_SIZE		256		/* MB */
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
 #else
-#define CFG_DDR_SIZE		512		/* MB */
+#define CONFIG_SYS_DDR_SIZE		512		/* MB */
 #endif
-#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_BASE
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
 
 /* DDR Controller Configuration
  *
@@ -130,102 +131,102 @@
  *	[04:00] DRAM tRPA
  */
 #ifdef CONFIG_ADS5121_REV2
-#define CFG_MDDRC_SYS_CFG	0xF8604A00
-#define CFG_MDDRC_SYS_CFG_RUN	0xE8604A00
-#define CFG_MDDRC_TIME_CFG1	0x54EC1168
-#define CFG_MDDRC_TIME_CFG2	0x35210864
+#define CONFIG_SYS_MDDRC_SYS_CFG	0xF8604A00
+#define CONFIG_SYS_MDDRC_SYS_CFG_RUN	0xE8604A00
+#define CONFIG_SYS_MDDRC_TIME_CFG1	0x54EC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2	0x35210864
 #else
-#define CFG_MDDRC_SYS_CFG	 0xFA804A00
-#define CFG_MDDRC_SYS_CFG_RUN	 0xEA804A00
-#define CFG_MDDRC_TIME_CFG1	 0x68EC1168
-#define CFG_MDDRC_TIME_CFG2	 0x34310864
+#define CONFIG_SYS_MDDRC_SYS_CFG	 0xFA804A00
+#define CONFIG_SYS_MDDRC_SYS_CFG_RUN	 0xEA804A00
+#define CONFIG_SYS_MDDRC_TIME_CFG1	 0x68EC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2	 0x34310864
 #endif
-#define CFG_MDDRC_SYS_CFG_EN	0xF0000000
-#define CFG_MDDRC_TIME_CFG0	0x00003D2E
-#define CFG_MDDRC_TIME_CFG0_RUN	0x06183D2E
-
-#define CFG_MICRON_NOP		0x01380000
-#define CFG_MICRON_PCHG_ALL	0x01100400
-#define CFG_MICRON_EM2		0x01020000
-#define CFG_MICRON_EM3		0x01030000
-#define CFG_MICRON_EN_DLL	0x01010000
-#define CFG_MICRON_RFSH		0x01080000
-#define CFG_MICRON_INIT_DEV_OP	0x01000432
-#define CFG_MICRON_OCD_DEFAULT	0x01010780
+#define CONFIG_SYS_MDDRC_SYS_CFG_EN	0xF0000000
+#define CONFIG_SYS_MDDRC_TIME_CFG0	0x00003D2E
+#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN	0x06183D2E
+
+#define CONFIG_SYS_MICRON_NOP		0x01380000
+#define CONFIG_SYS_MICRON_PCHG_ALL	0x01100400
+#define CONFIG_SYS_MICRON_EM2		0x01020000
+#define CONFIG_SYS_MICRON_EM3		0x01030000
+#define CONFIG_SYS_MICRON_EN_DLL	0x01010000
+#define CONFIG_SYS_MICRON_RFSH		0x01080000
+#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
+#define CONFIG_SYS_MICRON_OCD_DEFAULT	0x01010780
 
 /* DDR Priority Manager Configuration */
-#define CFG_MDDRCGRP_PM_CFG1	0x00077777
-#define CFG_MDDRCGRP_PM_CFG2	0x00000000
-#define CFG_MDDRCGRP_HIPRIO_CFG	0x00000001
-#define CFG_MDDRCGRP_LUT0_MU	0xFFEEDDCC
-#define CFG_MDDRCGRP_LUT0_ML	0xBBAAAAAA
-#define CFG_MDDRCGRP_LUT1_MU	0x66666666
-#define CFG_MDDRCGRP_LUT1_ML	0x55555555
-#define CFG_MDDRCGRP_LUT2_MU	0x44444444
-#define CFG_MDDRCGRP_LUT2_ML	0x44444444
-#define CFG_MDDRCGRP_LUT3_MU	0x55555555
-#define CFG_MDDRCGRP_LUT3_ML	0x55555558
-#define CFG_MDDRCGRP_LUT4_MU	0x11111111
-#define CFG_MDDRCGRP_LUT4_ML	0x11111122
-#define CFG_MDDRCGRP_LUT0_AU	0xaaaaaaaa
-#define CFG_MDDRCGRP_LUT0_AL	0xaaaaaaaa
-#define CFG_MDDRCGRP_LUT1_AU	0x66666666
-#define CFG_MDDRCGRP_LUT1_AL	0x66666666
-#define CFG_MDDRCGRP_LUT2_AU	0x11111111
-#define CFG_MDDRCGRP_LUT2_AL	0x11111111
-#define CFG_MDDRCGRP_LUT3_AU	0x11111111
-#define CFG_MDDRCGRP_LUT3_AL	0x11111111
-#define CFG_MDDRCGRP_LUT4_AU	0x11111111
-#define CFG_MDDRCGRP_LUT4_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
+#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
+#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
+#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
+#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
+#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
+#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
+#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
 
 /*
  * NOR FLASH on the Local Bus
  */
 #undef CONFIG_BKUP_FLASH
-#define CFG_FLASH_CFI				/* use the Common Flash Interface */
+#define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
 #ifdef CONFIG_BKUP_FLASH
-#define CFG_FLASH_BASE		0xFF800000	/* start of FLASH   */
-#define CFG_FLASH_SIZE		0x00800000	/* max flash size in bytes */
+#define CONFIG_SYS_FLASH_BASE		0xFF800000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		0x00800000	/* max flash size in bytes */
 #else
-#define CFG_FLASH_BASE		0xFC000000	/* start of FLASH   */
-#define CFG_FLASH_SIZE		0x04000000	/* max flash size in bytes */
+#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		0x04000000	/* max flash size in bytes */
 #endif
-#define CFG_FLASH_USE_BUFFER_WRITE
-#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_FLASH_BANKS_LIST	{CFG_FLASH_BASE}
-#define CFG_MAX_FLASH_SECT	256		/* max sectors per device */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max sectors per device */
 
-#undef CFG_FLASH_CHECKSUM
+#undef CONFIG_SYS_FLASH_CHECKSUM
 
 /*
  * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
  * window is 64KB
  */
-#define CFG_CPLD_BASE		0x82000000
-#define CFG_CPLD_SIZE		0x00010000	/* 64 KB */
+#define CONFIG_SYS_CPLD_BASE		0x82000000
+#define CONFIG_SYS_CPLD_SIZE		0x00010000	/* 64 KB */
 
-#define CFG_SRAM_BASE		0x30000000
-#define CFG_SRAM_SIZE		0x00020000	/* 128 KB */
+#define CONFIG_SYS_SRAM_BASE		0x30000000
+#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
 
-#define CFG_CS0_CFG		0x05059310	/* ALE active low, data size 4bytes */
-#define CFG_CS2_CFG		0x05059010	/* ALE active low, data size 1byte */
-#define CFG_CS_ALETIMING	0x00000005	/* Use alternative CS timing for CS0 and CS2 */
+#define CONFIG_SYS_CS0_CFG		0x05059310	/* ALE active low, data size 4bytes */
+#define CONFIG_SYS_CS2_CFG		0x05059010	/* ALE active low, data size 1byte */
+#define CONFIG_SYS_CS_ALETIMING	0x00000005	/* Use alternative CS timing for CS0 and CS2 */
 
 /* Use SRAM for initial stack */
-#define CFG_INIT_RAM_ADDR	CFG_SRAM_BASE		/* Initial RAM address */
-#define CFG_INIT_RAM_END	CFG_SRAM_SIZE		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE		/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_SRAM_SIZE		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE	0x100			/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100			/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE	TEXT_BASE		/* Start of monitor */
-#define CFG_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE		/* Start of monitor */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
 #ifdef	CONFIG_FSL_DIU_FB
-#define CFG_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
+#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
 #else
-#define CFG_MALLOC_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
 #endif
 
 /*
@@ -242,7 +243,7 @@
 #error CONFIG_PSC_CONSOLE must be 3
 #endif
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
 #define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC3_TX_SIZE
@@ -252,9 +253,9 @@
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /*
@@ -265,15 +266,15 @@
 /*
  * General PCI
  */
-#define CFG_PCI_MEM_BASE	0xA0000000
-#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BASE
-#define CFG_PCI_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCI_MMIO_BASE	(CFG_PCI_MEM_BASE + CFG_PCI_MEM_SIZE)
-#define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
-#define CFG_PCI_MMIO_SIZE	0x10000000	/* 256M */
-#define CFG_PCI_IO_BASE		0x00000000
-#define CFG_PCI_IO_PHYS		0x84000000
-#define CFG_PCI_IO_SIZE		0x01000000	/* 16M */
+#define CONFIG_SYS_PCI_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI_MMIO_BASE	(CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
+#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0x84000000
+#define CONFIG_SYS_PCI_IO_SIZE		0x01000000	/* 16M */
 
 
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
@@ -287,19 +288,24 @@
 #undef CONFIG_SOFT_I2C			/* so disable bit-banged I2C */
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 #if 0
-#define CFG_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
 #endif
 
 /*
+ * IIM - IC Identification Module
+ */
+#undef CONFIG_IIM
+
+/*
  * EEPROM configuration
  */
-#define CFG_I2C_EEPROM_ADDR_LEN		2	/* 16-bit EEPROM address */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* Atmel: AT24C32A-10TQ-2.7 */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10ms of delay */
-#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 32-Byte Page Write Mode */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* 16-bit EEPROM address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* Atmel: AT24C32A-10TQ-2.7 */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10ms of delay */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 32-Byte Page Write Mode */
 
 /*
  * Ethernet configuration
@@ -315,14 +321,14 @@
  * Configure on-board RTC
  */
 #define CONFIG_RTC_M41T62			/* use M41T62 rtc via i2 */
-#define CFG_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
 
 /*
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
 /* This has to be a multiple of the Flash sector size */
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_ENV_SIZE		0x2000
 #ifdef CONFIG_BKUP_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* one sector (256K) for env */
@@ -335,7 +341,7 @@
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 #include <config_cmd_default.h>
 
@@ -348,56 +354,65 @@
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_DATE
+#undef CONFIG_CMD_FUSE
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
 #endif
 
+#if defined(CONFIG_CMD_IDE)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+#endif /* defined(CONFIG_CMD_IDE) */
+
 /*
- * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock.
- * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set
+ * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
+ * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
  * to 0xFFFF, watchdog timeouts after about 64s. For details refer
  * to chapter 36 of the MPC5121e Reference Manual.
  */
 /* #define CONFIG_WATCHDOG */		/* enable watchdog */
-#define CFG_WATCHDOG_VALUE 0xFFFF
+#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
 
  /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory */
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #ifdef CONFIG_CMD_KGDB
-	#define CFG_CBSIZE	1024	/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
 #else
-	#define CFG_CBSIZE	256	/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
 #endif
 
 
-#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /* Cache Configuration */
-#define CFG_DCACHE_SIZE		32768
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_DCACHE_SIZE		32768
+#define CONFIG_SYS_CACHELINE_SIZE	32
 #ifdef CONFIG_CMD_KGDB
-#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
 #endif
 
-#define CFG_HID0_INIT	0x000000000
-#define CFG_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
-#define CFG_HID2	HID2_HBE
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID2	HID2_HBE
 
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
@@ -489,4 +504,48 @@
 #define OF_TBCLK		(bd->bi_busfreq / 4)
 #define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
 
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for IDE not supported	*/
+
+#define CONFIG_IDE_RESET		/* reset for IDE supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC512X_PATA
+
+/* Offset for data I/O			RefMan MPC5121EE Table 28-10	*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x00A0)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	RefMan MPC5121EE Table 28-23	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x00D8)
+
+/* Interval between registers	*/
+#define CONFIG_SYS_ATA_STRIDE		4
+
+#define ATA_BASE_ADDR		MPC512X_PATA
+
+/*
+ * Control register bit definitions
+ */
+#define FSL_ATA_CTRL_FIFO_RST_B		0x80000000
+#define FSL_ATA_CTRL_ATA_RST_B		0x40000000
+#define FSL_ATA_CTRL_FIFO_TX_EN		0x20000000
+#define FSL_ATA_CTRL_FIFO_RCV_EN	0x10000000
+#define FSL_ATA_CTRL_DMA_PENDING	0x08000000
+#define FSL_ATA_CTRL_DMA_ULTRA		0x04000000
+#define FSL_ATA_CTRL_DMA_WRITE		0x02000000
+#define FSL_ATA_CTRL_IORDY_EN		0x01000000
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/aev.h b/include/configs/aev.h
index 2dcaa58..2b4826d 100644
--- a/include/configs/aev.h
+++ b/include/configs/aev.h
@@ -39,7 +39,7 @@
 #define CONFIG_STK52XX		1	/* ... on a STK52XX base board */
 #define CONFIG_STK52XX_REV100	1	/*  define for revision 100 baseboards */
 #define CONFIG_AEVFIFO		1
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
 
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
@@ -51,7 +51,7 @@
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*
  * PCI Mapping:
@@ -74,7 +74,7 @@
 
 #define CONFIG_NET_MULTI	1
 #define CONFIG_EEPRO100		1
-#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
 #define CONFIG_NS8382X		1
 #endif	/* CONFIG_AEVFIFO */
 
@@ -84,9 +84,9 @@
 #define CONFIG_ISO_PARTITION
 
 /* POST support */
-#define CONFIG_POST		(CFG_POST_MEMORY   | \
-				 CFG_POST_CPU	   | \
-				 CFG_POST_I2C)
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_I2C)
 
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
@@ -129,7 +129,7 @@
 #define	CONFIG_TIMESTAMP		/* display image timestamps */
 
 #if (TEXT_BASE == 0xFC000000)		/* Boot low */
-#   define CFG_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT		1
 #endif
 
 /*
@@ -172,17 +172,17 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
-#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
+#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
  * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
+#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
 
 /*
@@ -190,9 +190,9 @@
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
 #ifdef CONFIG_TQM5200_REV100
-#define CFG_I2C_MODULE		1	/* Select I2C module #1 for rev. 100 board */
+#define CONFIG_SYS_I2C_MODULE		1	/* Select I2C module #1 for rev. 100 board */
 #else
-#define CFG_I2C_MODULE		2	/* Select I2C module #2 for all other revs */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #2 for all other revs */
 #endif
 
 /*
@@ -201,11 +201,11 @@
  * Please notice, that the resulting clock frequency could differ from the
  * configured value. This is because the I2C clock is derived from system
  * clock over a frequency divider with only a few divider values. U-boot
- * calculates the best approximation for CFG_I2C_SPEED. However the calculated
+ * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
  * approximation allways lies below the configured value, never above.
  */
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
@@ -213,34 +213,34 @@
  * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
  * same configuration could be used.
  */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CFG_I2C_EEPROM_ADDR_LEN		2
-#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
 
 /*
  * Flash configuration
  */
-#define CFG_FLASH_BASE		TEXT_BASE /* 0xFC000000 */
+#define CONFIG_SYS_FLASH_BASE		TEXT_BASE /* 0xFC000000 */
 
 /* use CFI flash driver if no module variant is spezified */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
-#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
-#undef CFG_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
-
-#if !defined(CFG_LOWBOOT)
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00760000 + 0x00800000)
-#else	/* CFG_LOWBOOT */
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
-#endif	/* CFG_LOWBOOT */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_BOOTCS_START }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MByte */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
+
+#if !defined(CONFIG_SYS_LOWBOOT)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
+#else	/* CONFIG_SYS_LOWBOOT */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
+#endif	/* CONFIG_SYS_LOWBOOT */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
 					   (= chip selects) */
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
 
 
 /*
@@ -255,32 +255,32 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /* Use ON-Chip SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
 #else
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
 #endif
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
@@ -318,7 +318,7 @@
  *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
  *   tests.
  */
-#define CFG_GPS_PORT_CONFIG	0x81500014
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x81500014
 
 /*
  * RTC configuration
@@ -328,30 +328,30 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
 /* Enable an alternate, more extensive memory test */
-#define CFG_ALT_MEMTEST
+#define CONFIG_SYS_ALT_MEMTEST
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*
@@ -363,22 +363,22 @@
  * Various low-level settings
  */
 #if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 #else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
 #endif
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
-#define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
+#define CONFIG_SYS_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
 #else
-#define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
+#define CONFIG_SYS_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
 #endif
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
 #define CONFIG_LAST_STAGE_INIT
 
@@ -386,23 +386,23 @@
  * SRAM - Do not map below 2 GB in address space, because this area is used
  * for SDRAM autosizing.
  */
-#define CFG_CS2_START		0xE5000000
-#define CFG_CS2_SIZE		0x80000		/* 512 kByte */
-#define CFG_CS2_CFG		0x0004D930
+#define CONFIG_SYS_CS2_START		0xE5000000
+#define CONFIG_SYS_CS2_SIZE		0x80000		/* 512 kByte */
+#define CONFIG_SYS_CS2_CFG		0x0004D930
 
 /*
  * Grafic controller - Do not map below 2 GB in address space, because this
  * area is used for SDRAM autosizing.
  */
 #define SM501_FB_BASE           0xE0000000
-#define CFG_CS1_START           (SM501_FB_BASE)
-#define CFG_CS1_SIZE            0x4000000       /* 64 MByte */
-#define CFG_CS1_CFG             0x8F48FF70
-#define SM501_MMIO_BASE         CFG_CS1_START + 0x03E00000
+#define CONFIG_SYS_CS1_START           (SM501_FB_BASE)
+#define CONFIG_SYS_CS1_SIZE            0x4000000       /* 64 MByte */
+#define CONFIG_SYS_CS1_CFG             0x8F48FF70
+#define SM501_MMIO_BASE         CONFIG_SYS_CS1_START + 0x03E00000
 
-#define CFG_CS_BURST            0x00000000
-#define CFG_CS_DEADCYCLE        0x33333311      /* 1 dead cycle for flash and SM501 */
+#define CONFIG_SYS_CS_BURST            0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE        0x33333311      /* 1 dead cycle for flash and SM501 */
 
-#define CFG_RESET_ADDRESS	0xff000000
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h
new file mode 100644
index 0000000..9eed342
--- /dev/null
+++ b/include/configs/afeb9260.h
@@ -0,0 +1,167 @@
+/*
+ * (C) Copyright 2008 Sergey Lapin <slapin@ossfans.org>
+ *
+ * Configuation settings for the AFEB9260 board.
+ * Based on configuration for AT91SAM9260-EK
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91_MAIN_CLOCK		18429952	/* from 18.432 MHz crystal */
+#define AT91_MASTER_CLOCK	89999598	/* peripheral = main / 2 */
+#define CONFIG_SYS_AT91_PLLB	0x107c3e18	/* PLLB settings for USB */
+#define CONFIG_SYS_HZ		1000000		/* 1us resolution */
+
+#define AT91_SLOW_CLOCK		32768	/* slow clock */
+
+#define CONFIG_AT91SAM9260	1	/* It's an Atmel AT91SAM9260 SoC*/
+#define CONFIG_AFEB9260		1	/* on an AFEB9260 Board	*/
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_USART	1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3		1	/* USART 3 is DBGU */
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+#define CONFIG_BOOTP_BOOTPATH		1
+#define CONFIG_BOOTP_GATEWAY		1
+#define CONFIG_BOOTP_HOSTNAME		1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_PING		1
+#define CONFIG_CMD_DHCP		1
+
+#define CONFIG_CMD_NAND		1
+#define CONFIG_CMD_USB		1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x20000000
+#define PHYS_SDRAM_SIZE			0x04000000	/* 64 megs */
+
+/* DataFlash */
+#define CONFIG_HAS_DATAFLASH		1
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1	0xD0000000	/* CS1 */
+#define AT91_SPI_CLK			15000000
+#define DATAFLASH_TCSS			(0x1a << 16)
+#define DATAFLASH_TCHS			(0x1 << 24)
+
+/* NAND flash */
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			0x40000000
+#define CONFIG_SYS_NAND_DBW_8			1
+
+/* NOR flash - no real flash on this board */
+#define CONFIG_SYS_NO_FLASH		1
+
+/* Ethernet */
+#define CONFIG_MACB			1
+#undef CONFIG_RMII			/* We have full MII there */
+#define CONFIG_RESET_PHY_R		1
+
+#define CONFIG_NET_MULTI		1
+#define CONFIG_NET_RETRY_COUNT		20
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW		1
+#define CONFIG_DOS_PARTITION		1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9260_UHP_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	1
+#define CONFIG_USB_STORAGE		1
+
+#define CONFIG_SYS_LOAD_ADDR			0x21000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END			0x21e00000
+
+#undef CONFIG_SYS_USE_DATAFLASH_CS0
+#define CONFIG_SYS_USE_DATAFLASH_CS1		1
+#undef CONFIG_SYS_USE_NANDFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS1 */
+#define CONFIG_ENV_IS_IN_DATAFLASH	1
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400)
+#define CONFIG_ENV_OFFSET		0x4200
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_BOOTCOMMAND	"nand read 0x21000000 0xa0000 0x200000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
+				"root=/dev/mtdblock2 "			\
+				"rw rootfstype=jffs2 panic=20"
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING	1
+
+#define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index c80c76a..e6248e9 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -40,63 +40,63 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0			*/
-#define CFG_FLASH_BASE		0xffe00000	/* start of FLASH		*/
-#define CFG_MONITOR_BASE	0xfffc0000	/* start of monitor		*/
-#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory		*/
-#define	CFG_PCI_MEMSIZE		0x40000000	/* size of mapped pci memory	*/
-#define CFG_PERIPHERAL_BASE	0xe0000000	/* internal peripherals		*/
-#define CFG_ISRAM_BASE		0xc0000000	/* internal SRAM		*/
-#define CFG_PCI_BASE		0xd0000000	/* internal PCI regs		*/
-#define CFG_PCI_MEMBASE1	CFG_PCI_MEMBASE  + 0x10000000
-#define CFG_PCI_MEMBASE2	CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3	CFG_PCI_MEMBASE2 + 0x10000000
-
-
-#define CFG_FPGA_BASE	    (CFG_PERIPHERAL_BASE + 0x08300000)
-#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0			*/
+#define CONFIG_SYS_FLASH_BASE		0xffe00000	/* start of FLASH		*/
+#define CONFIG_SYS_MONITOR_BASE	0xfffc0000	/* start of monitor		*/
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory		*/
+#define	CONFIG_SYS_PCI_MEMSIZE		0x40000000	/* size of mapped pci memory	*/
+#define CONFIG_SYS_PERIPHERAL_BASE	0xe0000000	/* internal peripherals		*/
+#define CONFIG_SYS_ISRAM_BASE		0xc0000000	/* internal SRAM		*/
+#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs		*/
+#define CONFIG_SYS_PCI_MEMBASE1	CONFIG_SYS_PCI_MEMBASE  + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2	CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3	CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
+
+
+#define CONFIG_SYS_FPGA_BASE	    (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
+#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
-#define CFG_TEMP_STACK_OCM  1
-#define CFG_OCM_DATA_ADDR   CFG_ISRAM_BASE
-#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
-#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE   128		    /* num bytes initial data	*/
+#define CONFIG_SYS_TEMP_STACK_OCM  1
+#define CONFIG_SYS_OCM_DATA_ADDR   CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR   CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE   128		    /* num bytes initial data	*/
 
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_POST_WORD_ADDR
 
-#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
-#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
+#define CONFIG_SYS_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
+#define CONFIG_SYS_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#undef	CFG_EXT_SERIAL_CLOCK
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK
 #define CONFIG_BAUDRATE		115200
 #define	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI		1	/* The flash is CFI compatible		*/
+#define CONFIG_SYS_FLASH_CFI		1	/* The flash is CFI compatible		*/
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use common CFI driver		*/
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
 
 #define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
 
 #define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector		*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -109,7 +109,7 @@
 #undef CONFIG_SPD_EEPROM		/* Don't use SPD EEPROM for setup	*/
 #define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0	*/
 #undef CONFIG_SDRAM_ECC			/* enable ECC support			*/
-#define CFG_SDRAM_TABLE	{ \
+#define CONFIG_SYS_SDRAM_TABLE	{ \
 		{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
 		{(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)	*/
 
@@ -118,22 +118,21 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs	*/
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs	*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (PCF8594C)
  *----------------------------------------------------------------------*/
-#define CFG_I2C_EEPROM_ADDR	0x54	/* EEPROM PCF8594C		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x54	/* EEPROM PCF8594C		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 3	/* The Philips PCF8594C has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3	/* The Philips PCF8594C has	*/
 					/* 8 byte page write mode using */
 					/* last 3 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	40   /* and takes up to 40 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	40   /* and takes up to 40 msec */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \"run kernelx\" to boot the system;"			\
@@ -197,8 +196,9 @@
 #define CONFIG_BAUDRATE		115200
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_NET_MULTI	1
 #define CONFIG_PHY_ADDR		0x02	/* dummy setting, no EMAC0 used	*/
@@ -212,7 +212,7 @@
 #define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
 #define CONFIG_M88E1111_PHY	1	/* needed for PHY specific setup*/
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+#define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
 
 #define CONFIG_NETCONSOLE		/* include NetConsole support	*/
 
@@ -235,43 +235,40 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
 #define CONFIG_CMD_FPGA
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-
+#undef CONFIG_CMD_NFS
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_ALT_MEMTEST		1	/* Enable more extensive memtest*/
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_ALT_MEMTEST		1	/* Enable more extensive memtest*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
@@ -279,7 +276,7 @@
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE	1	/* include version env variable */
 
-#define CFG_4xx_RESET_TYPE	0x2	/* use chip reset on this board	*/
+#define CONFIG_SYS_4xx_RESET_TYPE	0x2	/* use chip reset on this board	*/
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -289,15 +286,15 @@
 #define CONFIG_PCI			/* include pci support		*/
 #define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
-#define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
+#define CONFIG_SYS_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 #define CONFIG_PCI_BOOTDELAY	1       /* enable pci bootdelay variable*/
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT		/* let board init pci target    */
-#define CFG_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */
+#define CONFIG_SYS_PCI_MASTER_INIT
 
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
@@ -305,8 +302,8 @@
 #define CONFIG_FPGA
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
-#define CFG_FPGA_CHECK_CTRLC
-#define CFG_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_CHECK_CTRLC
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
 #define CONFIG_FPGA_COUNT       1		/* Ich habe 2 ... aber in
 					Reihe geschaltet -> sollte gehen,
 					aufpassen mit Datasize ist jetzt
@@ -315,54 +312,53 @@
 					Mode erklaert ...*/
 
 /* FPGA program pin configuration */
-#define CFG_GPIO_CLK		18	/* FPGA clk pin (cpu output)		*/
-#define CFG_GPIO_DATA		19	/* FPGA data pin (cpu output)		*/
-#define CFG_GPIO_STATUS		20	/* FPGA status pin (cpu input)		*/
-#define CFG_GPIO_CONFIG		21	/* FPGA CONFIG pin (cpu output)		*/
-#define CFG_GPIO_CON_DON	22	/* FPGA CONFIG_DONE pin (cpu input)	*/
+#define CONFIG_SYS_GPIO_CLK		18	/* FPGA clk pin (cpu output)		*/
+#define CONFIG_SYS_GPIO_DATA		19	/* FPGA data pin (cpu output)		*/
+#define CONFIG_SYS_GPIO_STATUS		20	/* FPGA status pin (cpu input)		*/
+#define CONFIG_SYS_GPIO_CONFIG		21	/* FPGA CONFIG pin (cpu output)		*/
+#define CONFIG_SYS_GPIO_CON_DON	22	/* FPGA CONFIG_DONE pin (cpu input)	*/
 
-#define CFG_GPIO_SEL_DPR	14	/* cpu output */
-#define CFG_GPIO_SEL_AVR	15	/* cpu output */
-#define CFG_GPIO_PROG_EN	23	/* cpu output */
+#define CONFIG_SYS_GPIO_SEL_DPR	14	/* cpu output */
+#define CONFIG_SYS_GPIO_SEL_AVR	15	/* cpu output */
+#define CONFIG_SYS_GPIO_PROG_EN	23	/* cpu output */
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup
  *-----------------------------------------------------------------------*/
-#define CFG_GPIO_SHUTDOWN	(0x80000000 >> 6)
-#define CFG_GPIO_SSD_EMPTY	(0x80000000 >> 9)
-#define CFG_GPIO_EREADY		(0x80000000 >> 26)
-#define CFG_GPIO_REV0		(0x80000000 >> 14)
-#define CFG_GPIO_REV1		(0x80000000 >> 15)
+#define CONFIG_SYS_GPIO_SHUTDOWN	(0x80000000 >> 6)
+#define CONFIG_SYS_GPIO_SSD_EMPTY	(0x80000000 >> 9)
+#define CONFIG_SYS_GPIO_EREADY		(0x80000000 >> 26)
+#define CONFIG_SYS_GPIO_REV0		(0x80000000 >> 14)
+#define CONFIG_SYS_GPIO_REV1		(0x80000000 >> 15)
 
 /*-----------------------------------------------------------------------
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------*/
-#define CFG_MAX_NAND_DEVICE	4
-#define NAND_MAX_CHIPS		CFG_MAX_NAND_DEVICE
-#define CFG_NAND_BASE		0xF0000000	/* NAND FLASH Base Address	*/
-#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE + 0, CFG_NAND_BASE + 2,	\
-				  CFG_NAND_BASE + 4, CFG_NAND_BASE + 6 }
-#define CFG_NAND_QUIET_TEST	1	/* don't warn upon unknown NAND flash	*/
+#define CONFIG_SYS_MAX_NAND_DEVICE	4
+#define CONFIG_SYS_NAND_BASE		0xF0000000	/* NAND FLASH Base Address	*/
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2,	\
+				  CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 }
+#define CONFIG_SYS_NAND_QUIET_TEST	1	/* don't warn upon unknown NAND flash	*/
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
-#define CFG_FLASH		CFG_FLASH_BASE
+#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE
 
 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x92015480
-#define CFG_EBC_PB0CR		(CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (NAND-FLASH) initialization					*/
-#define CFG_EBC_PB1AP		0x01840380	/* TWT=3			*/
-#define CFG_EBC_PB1CR		(CFG_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB1AP		0x01840380	/* TWT=3			*/
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Internal Definitions
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index 1f27d78..d3dc3e5 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -23,35 +23,36 @@
 #ifndef __AMCC_COMMON_H
 #define __AMCC_COMMON_H
 
-#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
-#define CFG_MONITOR_BASE	TEXT_BASE	/* Start of U-Boot	*/
-#define CFG_MONITOR_LEN		(0xFFFFFFFF - CFG_MONITOR_BASE + 1)
-#define CFG_MALLOC_LEN		(1 << 20)	/* Reserved for malloc	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* Start of U-Boot	*/
+#define CONFIG_SYS_MONITOR_LEN		(0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* Reserved for malloc	*/
 
 /*
  * UART
  */
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SERIAL_MULTI
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
 /*
  * I2C
  */
 #define CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * Ethernet/EMAC/PHY
  */
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII			/* MII PHY management		*/
 #define CONFIG_NET_MULTI
 #define CONFIG_NETCONSOLE		/* include NetConsole support	*/
 #if defined(CONFIG_440)
-#define CFG_RX_ETH_BUFFER	32	/* number of eth rx buffers	*/
+#define CONFIG_SYS_RX_ETH_BUFFER	32	/* number of eth rx buffers	*/
 #else
-#define CFG_RX_ETH_BUFFER	16	/* number of eth rx buffers	*/
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* number of eth rx buffers	*/
 #endif
 
 /*
@@ -79,24 +80,24 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE /* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
-#define CFG_EXTBDINFO			/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
+#define CONFIG_SYS_EXTBDINFO			/* To use extended board_into (bd_t) */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
 #define CONFIG_CMDLINE_EDITING		/* add command line history	*/
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support	*/
@@ -104,15 +105,15 @@
 #define CONFIG_MX_CYCLIC		/* enable mdc/mwc commands      */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 	/* include version env variable */
-#define CFG_CONSOLE_INFO_QUIET		/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET		/* don't print console @ startup*/
 
-#define CFG_HUSH_PARSER			/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER			/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #define CONFIG_LOADS_ECHO		/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE		/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate change	*/
 
 /*
  * BOOTP options
@@ -128,7 +129,7 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*
  * Internal Definitions
@@ -160,6 +161,13 @@
 #endif
 
 /*
+ * Only very few boards have default netdev not set to eth0 (like Arches)
+ */
+#if !defined(CONFIG_USE_NETDEV)
+#define CONFIG_USE_NETDEV	eth0
+#endif
+
+/*
  * Only some 4xx PPC's are equipped with an FPU
  */
 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
@@ -184,7 +192,7 @@
  * General common environment variables shared on all AMCC eval boards
  */
 #define CONFIG_AMCC_DEF_ENV						\
-	"netdev=eth0\0"							\
+	"netdev=" xstr(CONFIG_USE_NETDEV) "\0"				\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
@@ -197,8 +205,10 @@
 	"initrd_high=30000000\0"					\
 	"kernel_addr_r=400000\0"					\
 	"fdt_addr_r=800000\0"						\
+	"ramdisk_addr_r=C00000\0"					\
 	"hostname=" xstr(CONFIG_HOSTNAME) "\0"				\
 	"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0"			\
+	"ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0"		\
 	CONFIG_AMCC_DEF_ENV_ROOTPATH
 
 /*
@@ -214,6 +224,12 @@
 		"tftp ${fdt_addr_r} ${fdt_file}; "			\
 		"run nfsargs addip addtty addmisc;"			\
 		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"net_self_load=tftp ${kernel_addr_r} ${bootfile};"		\
+		"tftp ${fdt_addr_r} ${fdt_file};"			\
+		"tftp ${ramdisk_addr_r} ${ramdisk_file};\0"		\
+	"net_self=run net_self_load;"					\
+		"run ramargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
 	"fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0"
 
 /*
@@ -244,9 +260,9 @@
 
 #define CONFIG_AMCC_DEF_ENV_NOR_UPD					\
 	"load=tftp 200000 " xstr(CONFIG_HOSTNAME) "/u-boot.bin\0"	\
-	"update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;"	\
-		"era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;"		\
-		"cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \
+	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;"	\
+		"era " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;"		\
+		"cp.b ${fileaddr} " xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize};" \
 		"setenv filesize;saveenv\0"				\
 	"upd=run load update\0"						\
 
diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h
index a6312b5..c6d77e3 100644
--- a/include/configs/ap325rxa.h
+++ b/include/configs/ap325rxa.h
@@ -40,7 +40,7 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_EXT2
 #define CONFIG_DOS_PARTITION
@@ -63,19 +63,19 @@
 #define AP325RXA_FLASH_BANK_SIZE	(128 * 1024 * 1024)
 
 /* undef to save memory	*/
-#define CFG_LONGHELP
+#define CONFIG_SYS_LONGHELP
 /* Monitor Command Prompt */
-#define CFG_PROMPT		"=> "
+#define CONFIG_SYS_PROMPT		"=> "
 /* Buffer size for input from the Console */
-#define CFG_CBSIZE		256
+#define CONFIG_SYS_CBSIZE		256
 /* Buffer size for Console output */
-#define CFG_PBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
 /* max args accepted for monitor commands */
-#define CFG_MAXARGS		16
+#define CONFIG_SYS_MAXARGS		16
 /* Buffer size for Boot Arguments passed to kernel */
-#define CFG_BARGSIZE	512
+#define CONFIG_SYS_BARGSIZE	512
 /* List of legal baudrate settings for this board */
-#define CFG_BAUDRATE_TABLE	{ 38400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 38400 }
 
 /* SCIF */
 #define CONFIG_SCIF_CONSOLE 1
@@ -83,94 +83,94 @@
 #define CONFIG_CONS_SCIF5	1
 
 /* Suppress display of console information at boot */
-#undef  CFG_CONSOLE_INFO_QUIET
-#undef  CFG_CONSOLE_OVERWRITE_ROUTINE
-#undef  CFG_CONSOLE_ENV_OVERWRITE
+#undef  CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 
-#define CFG_MEMTEST_START	(AP325RXA_SDRAM_BASE)
-#define CFG_MEMTEST_END		(CFG_MEMTEST_START + (60 * 1024 * 1024))
+#define CONFIG_SYS_MEMTEST_START	(AP325RXA_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
 
 /* Enable alternate, more extensive, memory test */
-#undef  CFG_ALT_MEMTEST
+#undef  CONFIG_SYS_ALT_MEMTEST
 /* Scratch address used by the alternate memory test */
-#undef  CFG_MEMTEST_SCRATCH
+#undef  CONFIG_SYS_MEMTEST_SCRATCH
 
 /* Enable temporary baudrate change while serial download */
-#undef  CFG_LOADS_BAUD_CHANGE
+#undef  CONFIG_SYS_LOADS_BAUD_CHANGE
 
-#define CFG_SDRAM_BASE	(AP325RXA_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_BASE	(AP325RXA_SDRAM_BASE)
 /* maybe more, but if so u-boot doesn't know about it... */
-#define CFG_SDRAM_SIZE	(128 * 1024 * 1024)
+#define CONFIG_SYS_SDRAM_SIZE	(128 * 1024 * 1024)
 /* default load address for scripts ?!? */
-#define CFG_LOAD_ADDR	(CFG_SDRAM_BASE + 16 * 1024 * 1024)
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
 
 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
-#define CFG_MONITOR_BASE	(AP325RXA_FLASH_BASE_1)
+#define CONFIG_SYS_MONITOR_BASE	(AP325RXA_FLASH_BASE_1)
 /* Monitor size */
-#define CFG_MONITOR_LEN	(128 * 1024)
+#define CONFIG_SYS_MONITOR_LEN	(128 * 1024)
 /* Size of DRAM reserved for malloc() use */
-#define CFG_MALLOC_LEN	(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_SIZE	(256)
-#define CFG_BOOTMAPSZ	(8 * 1024 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	(256)
+#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
 
 /* FLASH */
 #define CONFIG_FLASH_CFI_DRIVER 1
-#define CFG_FLASH_CFI
-#undef  CFG_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_CFI
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
 /* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 /* Physical start address of Flash memory */
-#define CFG_FLASH_BASE	(AP325RXA_FLASH_BASE_1)
+#define CONFIG_SYS_FLASH_BASE	(AP325RXA_FLASH_BASE_1)
 /* Max number of sectors on each Flash chip */
-#define CFG_MAX_FLASH_SECT	512
+#define CONFIG_SYS_MAX_FLASH_SECT	512
 
 /*
  * IDE support
  */
 #define CONFIG_IDE_RESET	1
-#define CFG_PIO_MODE		1
-#define CFG_IDE_MAXBUS		1	/* IDE bus */
-#define CFG_IDE_MAXDEVICE	1
-#define CFG_ATA_BASE_ADDR	0xB4180000
-#define CFG_ATA_STRIDE		2	/* 1bit shift */
-#define CFG_ATA_DATA_OFFSET	0x200	/* data reg offset */
-#define CFG_ATA_REG_OFFSET	0x200	/* reg offset */
-#define CFG_ATA_ALT_OFFSET	0x210	/* alternate register offset */
+#define CONFIG_SYS_PIO_MODE		1
+#define CONFIG_SYS_IDE_MAXBUS		1	/* IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_BASE_ADDR	0xB4180000
+#define CONFIG_SYS_ATA_STRIDE		2	/* 1bit shift */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x200	/* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x200	/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x210	/* alternate register offset */
 
 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */
-#define CFG_MAX_FLASH_BANKS	1
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}
 
 /* Timeout for Flash erase operations (in ms) */
-#define CFG_FLASH_ERASE_TOUT	(3 * 1000)
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
 /* Timeout for Flash write operations (in ms) */
-#define CFG_FLASH_WRITE_TOUT	(3 * 1000)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
 /* Timeout for Flash set sector lock bit operations (in ms) */
-#define CFG_FLASH_LOCK_TOUT	(3 * 1000)
+#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
 /* Timeout for Flash clear lock bit operations (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	(3 * 1000)
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
 
 /*
  * Use hardware flash sectors protection instead
  * of U-Boot software protection
  */
-#undef  CFG_FLASH_PROTECTION
-#undef  CFG_DIRECT_FLASH_TFTP
+#undef  CONFIG_SYS_FLASH_PROTECTION
+#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
 
 /* ENV setting */
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_OVERWRITE	1
 #define CONFIG_ENV_SECT_SIZE	(128 * 1024)
 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN)
-/* Offset of env Flash sector relative to CFG_FLASH_BASE */
-#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CFG_FLASH_BASE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
+#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
 #define TMU_CLK_DIVIDER		(4)	/* 4 (default), 16, 64, 256 or 1024 */
-#define CFG_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
 
 #endif	/* __AP325RXA_H */
diff --git a/include/configs/apollon.h b/include/configs/apollon.h
index edfae27..dff47fc 100644
--- a/include/configs/apollon.h
+++ b/include/configs/apollon.h
@@ -43,16 +43,19 @@
 
 /* Boot method */
 /* uncomment if you use NOR boot */
-/* #define CFG_NOR_BOOT		1 */
+/* #define CONFIG_SYS_NOR_BOOT		1 */
 
 /* uncomment if you use NOR on CS3 */
-/* #define CFG_USE_NOR		1 */
+/* #define CONFIG_SYS_USE_NOR		1 */
 
-#ifdef CFG_NOR_BOOT
-#undef CFG_USE_NOR
-#define CFG_USE_NOR		1
+#ifdef CONFIG_SYS_NOR_BOOT
+#undef CONFIG_SYS_USE_NOR
+#define CONFIG_SYS_USE_NOR		1
 #endif
 
+/* uncommnet if you want to use UBI */
+#define CONFIG_SYS_USE_UBI
+
 #include <asm/arch/omap2420.h>	/* get chip and board defs */
 
 #define	V_SCLK	12000000
@@ -73,8 +76,9 @@
  * Size of malloc() pool
  */
 #define	CONFIG_ENV_SIZE SZ_128K	/* Total Size of Environment Sector */
-#define	CFG_MALLOC_LEN	(CONFIG_ENV_SIZE + SZ_128K)
-#define	CFG_GBL_DATA_SIZE	128	/* bytes reserved for initial data */
+#define	CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + SZ_1M)
+/* bytes reserved for initial data */
+#define	CONFIG_SYS_GBL_DATA_SIZE	128
 
 /*
  * Hardware drivers
@@ -92,11 +96,11 @@
  */
 #define	V_NS16550_CLK	(48000000)	/* 48MHz (APLL96/2) */
 
-#define	CFG_NS16550
-#define	CFG_NS16550_SERIAL
-#define	CFG_NS16550_REG_SIZE	(-4)
-#define	CFG_NS16550_CLK	V_NS16550_CLK	/* 3MHz (1.5MHz*2) */
-#define	CFG_NS16550_COM1	OMAP2420_UART1
+#define	CONFIG_SYS_NS16550
+#define	CONFIG_SYS_NS16550_SERIAL
+#define	CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define	CONFIG_SYS_NS16550_CLK	V_NS16550_CLK	/* 3MHz (1.5MHz*2) */
+#define	CONFIG_SYS_NS16550_COM1	OMAP2420_UART1
 
 /*
  * select serial console configuration
@@ -107,7 +111,7 @@
 #define	CONFIG_ENV_OVERWRITE
 #define	CONFIG_CONS_INDEX	1
 #define	CONFIG_BAUDRATE		115200
-#define	CFG_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+#define	CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include	<config_cmd_default.h>
@@ -116,9 +120,16 @@
 #define	CONFIG_CMD_DIAG
 #define	CONFIG_CMD_ONENAND
 
+#ifdef CONFIG_SYS_USE_UBI
+#define	CONFIG_CMD_JFFS2
+#define	CONFIG_CMD_UBI
+#define	CONFIG_RBTREE
+#define CONFIG_MTD_PARTITIONS
+#endif
+
 #undef	CONFIG_CMD_AUTOSCRIPT
 
-#ifndef	CFG_USE_NOR
+#ifndef	CONFIG_SYS_USE_NOR
 # undef	CONFIG_CMD_FLASH
 # undef	CONFIG_CMD_IMLS
 #endif
@@ -133,24 +144,39 @@
 #define	CONFIG_BOOTFILE	"uImage"
 #define	CONFIG_ETHADDR	00:0E:99:00:24:20
 
-#ifdef	CONFIG_APOLLON_PLUS
-# define	CONFIG_BOOTARGS "root=/dev/nfs rw mem=64M console=ttyS0,115200n8 ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2"
+#ifdef CONFIG_APOLLON_PLUS
+#define CONFIG_SYS_MEM	"mem=64M"
 #else
-# define	CONFIG_BOOTARGS "root=/dev/nfs rw mem=128M console=ttyS0,115200n8 ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2"
+#define CONFIG_SYS_MEM	"mem=128"
 #endif
 
+#ifdef CONFIG_SYS_USE_UBI
+#define CONFIG_SYS_UBI "ubi.mtd=4"
+#else
+#define CONFIG_SYS_UBI ""
+#endif
+
+#define CONFIG_BOOTARGS "root=/dev/nfs rw " CONFIG_SYS_MEM \
+	" console=ttyS0,115200n8" \
+	" ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:" \
+	"apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2 " \
+	CONFIG_SYS_UBI
+
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"Image=tftp 0x80008000 Image; go 0x80008000\0"			\
 	"zImage=tftp 0x80180000 zImage; go 0x80180000\0"		\
 	"uImage=tftp 0x80180000 uImage; bootm 0x80180000\0"		\
 	"uboot=tftp 0x80008000 u-boot.bin; go 0x80008000\0"		\
-	"xloader=tftp 0x80180000 x-load.bin; cp.w 0x80180000 0x00000400 0x1000; go 0x00000400\0"	\
+	"xloader=tftp 0x80180000 x-load.bin; "				\
+	" cp.w 0x80180000 0x00000400 0x1000; go 0x00000400\0"		\
 	"syncmode50=mw.w 0x1e442 0xc0c4; mw 0x6800a060 0xe30d1201\0"	\
 	"syncmode=mw.w 0x1e442 0xe0f4; mw 0x6800a060 0xe30d1201\0"	\
 	"norboot=cp32 0x18040000 0x80008000 0x200000; go 0x80008000\0"	\
-	"oneboot=onenand read 0x80008000 0x40000 0x200000; go 0x80008000\0"\
+	"oneboot=onenand read 0x80008000 0x40000 0x200000; go 0x80008000\0" \
 	"onesyncboot=run syncmode oneboot\0"				\
-	"updateb=tftp 0x80180000 u-boot-onenand.bin; onenand erase 0x0 0x20000; onenand write 0x80180000 0x0 0x20000\0"					\
+	"updateb=tftp 0x80180000 u-boot-onenand.bin; "			\
+	" onenand erase 0x0 0x20000; onenand write 0x80180000 0x0 0x20000\0" \
+	"ubi=setenv bootargs ${bootargs} ubi.mtd=4 ${mtdparts}; run uImage\0" \
 	"bootcmd=run uboot\0"
 
 /*
@@ -158,20 +184,21 @@
  */
 #define	V_PROMPT	"Apollon # "
 
-#define	CFG_LONGHELP	/* undef to save memory */
-#define	CFG_PROMPT	V_PROMPT
-#define	CFG_CBSIZE	256	/* Console I/O Buffer Size */
+#define	CONFIG_SYS_LONGHELP	/* undef to save memory */
+#define	CONFIG_SYS_PROMPT	V_PROMPT
+#define	CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
 /* Print Buffer Size */
-#define	CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define	CFG_MAXARGS	16	/* max number of command args */
-#define	CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-
-#define	CFG_MEMTEST_START	(OMAP2420_SDRC_CS0)	/* memtest works on */
-#define	CFG_MEMTEST_END		(OMAP2420_SDRC_CS0+SZ_31M)
-
-#undef	CFG_CLKS_IN_HZ	/* everything, incl board info, in Hz */
-
-#define	CFG_LOAD_ADDR	(OMAP2420_SDRC_CS0)	/* default load address */
+#define	CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define	CONFIG_SYS_MAXARGS	16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define	CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define	CONFIG_SYS_MEMTEST_START	(OMAP2420_SDRC_CS0)
+#define	CONFIG_SYS_MEMTEST_END		(OMAP2420_SDRC_CS0+SZ_31M)
+
+#undef	CONFIG_SYS_CLKS_IN_HZ	/* everything, incl board info, in Hz */
+/* default load address */
+#define	CONFIG_SYS_LOAD_ADDR	(OMAP2420_SDRC_CS0)
 
 /* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2)
  * or by 32KHz clk, or from external sig. This rate is divided by a local
@@ -179,9 +206,9 @@
  */
 #define	V_PVT	7	/* use with 12MHz/128 */
 
-#define	CFG_TIMERBASE	OMAP2420_GPT2
-#define	CFG_PVT	V_PVT	/* 2^(pvt+1) */
-#define	CFG_HZ		((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+#define	CONFIG_SYS_TIMERBASE	OMAP2420_GPT2
+#define	CONFIG_SYS_PVT	V_PVT	/* 2^(pvt+1) */
+#define	CONFIG_SYS_HZ		((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -205,27 +232,40 @@
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#ifdef	CFG_USE_NOR
+#ifdef	CONFIG_SYS_USE_NOR
 /* OneNAND boot, NOR has CS3, But NOR has CS0 when NOR boot */
-# define	CFG_FLASH_BASE		0x18000000
-# define	CFG_MAX_FLASH_BANKS	1
-# define	CFG_MAX_FLASH_SECT	1024
+# define	CONFIG_SYS_FLASH_BASE		0x18000000
+# define	CONFIG_SYS_MAX_FLASH_BANKS	1
+# define	CONFIG_SYS_MAX_FLASH_SECT	1024
 /*-----------------------------------------------------------------------
-
  * CFI FLASH driver setup
  */
-# define	CFG_FLASH_CFI	1	/* Flash memory is CFI compliant */
+/* Flash memory is CFI compliant */
+# define	CONFIG_SYS_FLASH_CFI	1
 # define	CONFIG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
-/* #define CFG_FLASH_USE_BUFFER_WRITE 1 */ /* Use buffered writes (~10x faster) */
-# define	CFG_FLASH_PROTECTION	1	/* Use h/w sector protection*/
+/* Use buffered writes (~10x faster) */
+/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 */
+/* Use h/w sector protection*/
+# define	CONFIG_SYS_FLASH_PROTECTION	1
 
-#else	/* !CFG_USE_NOR */
-# define	CFG_NO_FLASH	1
-#endif	/* CFG_USE_NOR */
+#else	/* !CONFIG_SYS_USE_NOR */
+# define	CONFIG_SYS_NO_FLASH	1
+#endif	/* CONFIG_SYS_USE_NOR */
 
 /* OneNAND boot, OneNAND has CS0, NOR boot ONeNAND has CS2 */
-#define	CFG_ONENAND_BASE	0x00000000
+#define	CONFIG_SYS_ONENAND_BASE	0x00000000
 #define	CONFIG_ENV_IS_IN_ONENAND	1
 #define CONFIG_ENV_ADDR		0x00020000
 
+#ifdef CONFIG_SYS_USE_UBI
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"onenand0=onenand"
+#define MTDPARTS_DEFAULT	"mtdparts=onenand:128k(bootloader),"	\
+					"128k(params),"			\
+					"2m(kernel),"			\
+					"16m(rootfs),"			\
+					"32m(fs),"			\
+					"-(ubifs)"
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h
index 668c2c1..5a4ceaf 100644
--- a/include/configs/armadillo.h
+++ b/include/configs/armadillo.h
@@ -50,8 +50,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -95,24 +95,24 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"ARMADILLO # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"ARMADILLO # "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0xc0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0x00040000	/* default load address	for armadillo: kernel img is here*/
+#define	CONFIG_SYS_LOAD_ADDR		0x00040000	/* default load address	for armadillo: kernel img is here*/
 
-#define	CFG_HZ			2000		/* decrementer freq: 2 kHz */
+#define	CONFIG_SYS_HZ			2000		/* decrementer freq: 2 kHz */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -135,17 +135,17 @@
 #define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
 #define PHYS_FLASH_SIZE		0x00400000 /* 4 MB */
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x20000)	/* Addr of Environment Sector	*/
diff --git a/include/configs/assabet.h b/include/configs/assabet.h
index 28864ea..024fa20 100644
--- a/include/configs/assabet.h
+++ b/include/configs/assabet.h
@@ -45,8 +45,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN          (CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE       128	/* size rsrvd for initial data */
+#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE       128	/* size rsrvd for initial data */
 
 /*
  * Hardware drivers
@@ -85,7 +85,7 @@
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySA0,115200n8 root=/dev/nfs ip=bootp"
 #define CONFIG_BOOTCOMMAND	"bootp;tftp;bootm"
-#define CFG_AUTOLOAD            "n"	/* No autoload */
+#define CONFIG_SYS_AUTOLOAD            "n"	/* No autoload */
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
@@ -95,25 +95,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory         */
-#define CFG_PROMPT		"Intel Assabet # "	/* Monitor Command Prompt       */
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size      */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory         */
+#define CONFIG_SYS_PROMPT		"Intel Assabet # "	/* Monitor Command Prompt       */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START	0xc0400000	/* memtest works on     */
-#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM   */
+#define CONFIG_SYS_MEMTEST_START	0xc0400000	/* memtest works on     */
+#define CONFIG_SYS_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM   */
 
-#undef  CFG_CLKS_IN_HZ
+#undef  CONFIG_SYS_CLKS_IN_HZ
 
-#define CFG_LOAD_ADDR		0xc0000000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0xc0000000	/* default load address */
 
-#define CFG_HZ			3686400	/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x0a	/* set core clock to 206MHz */
+#define CONFIG_SYS_HZ			3686400	/* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_CPUSPEED		0x0a	/* set core clock to 206MHz */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -138,27 +138,27 @@
 #define PHYS_FLASH_BANK_SIZE    0x01000000	/* 16 MB Banks */
 #define PHYS_FLASH_SECT_SIZE    0x00040000	/* 256 KB sectors (x2) */
 
-#define CFG_MONITOR_BASE        TEXT_BASE
-#define CFG_MONITOR_LEN         (256 * 1024)	/* Reserve 256 KB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE        TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN         (256 * 1024)	/* Reserve 256 KB for Monitor */
 
-#if CFG_MONITOR_BASE < CFG_FLASH_BASE
-#define CFG_RAMSTART
+#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_RAMSTART
 #endif
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-#define CFG_FLASH_SIZE          PHYS_FLASH_SIZE
-#define CFG_FLASH_CFI           1	/* flash is CFI conformant      */
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_SIZE          PHYS_FLASH_SIZE
+#define CONFIG_SYS_FLASH_CFI           1	/* flash is CFI conformant      */
 #define CONFIG_FLASH_CFI_DRIVER    1	/* use common cfi driver        */
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
-#define CFG_MAX_FLASH_BANKS     1	/* max # of memory banks        */
-#define CFG_FLASH_INCREMENT     0	/* there is only one bank       */
-#define CFG_MAX_FLASH_SECT      128	/* max # of sectors on one chip */
-#undef CFG_FLASH_PROTECTION
-#define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
+#define CONFIG_SYS_MAX_FLASH_BANKS     1	/* max # of memory banks        */
+#define CONFIG_SYS_FLASH_INCREMENT     0	/* there is only one bank       */
+#define CONFIG_SYS_MAX_FLASH_SECT      128	/* max # of sectors on one chip */
+#undef CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE }
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 
diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h
index fd06245..01da99b 100644
--- a/include/configs/at91cap9adk.h
+++ b/include/configs/at91cap9adk.h
@@ -29,9 +29,11 @@
 
 /* ARM asynchronous clock */
 #define AT91_CPU_NAME		"AT91CAP9"
-#define AT91_MAIN_CLOCK		200000000	/* from 12 MHz crystal */
-#define AT91_MASTER_CLOCK	100000000	/* peripheral = main / 2 */
-#define CFG_HZ			1000000		/* 1us resolution */
+#define AT91_MAIN_CLOCK		12000000	/* 12 MHz crystal */
+#define AT91_MASTER_CLOCK	100000000	/* peripheral */
+#define AT91_CPU_CLOCK		200000000	/* cpu */
+#define CONFIG_SYS_AT91_PLLB	0x10073e01	/* PLLB settings for USB */
+#define CONFIG_SYS_HZ		1000000		/* 1us resolution */
 
 #define AT91_SLOW_CLOCK		32768	/* slow clock */
 
@@ -63,10 +65,10 @@
 #undef LCD_TEST_PATTERN
 #define CONFIG_LCD_INFO			1
 #define CONFIG_LCD_INFO_BELOW_LOGO	1
-#define CFG_WHITE_ON_BLACK		1
+#define CONFIG_SYS_WHITE_ON_BLACK		1
 #define CONFIG_ATMEL_LCD		1
 #define CONFIG_ATMEL_LCD_BGR555		1
-#define CFG_CONSOLE_IS_IN_ENV		1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
 
 #define CONFIG_BOOTDELAY	3
 
@@ -100,26 +102,25 @@
 
 /* DataFlash */
 #define CONFIG_HAS_DATAFLASH		1
-#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
-#define CFG_MAX_DATAFLASH_BANKS		1
-#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
 #define AT91_SPI_CLK			15000000
 #define DATAFLASH_TCSS			(0x1a << 16)
 #define DATAFLASH_TCHS			(0x1 << 24)
 
 /* NOR flash */
-#define CFG_FLASH_CFI			1
+#define CONFIG_SYS_FLASH_CFI			1
 #define CONFIG_FLASH_CFI_DRIVER		1
 #define PHYS_FLASH_1			0x10000000
-#define CFG_FLASH_BASE			PHYS_FLASH_1
-#define CFG_MAX_FLASH_SECT		256
-#define CFG_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT		256
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
 
 /* NAND flash */
-#define NAND_MAX_CHIPS			1
-#define CFG_MAX_NAND_DEVICE		1
-#define CFG_NAND_BASE			0x40000000
-#define CFG_NAND_DBW_8			1
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			0x40000000
+#define CONFIG_SYS_NAND_DBW_8			1
 
 /* Ethernet */
 #define CONFIG_MACB			1
@@ -130,28 +131,29 @@
 
 /* USB */
 #define CONFIG_USB_OHCI_NEW		1
-#define LITTLEENDIAN			1
 #define CONFIG_DOS_PARTITION		1
-#define CFG_USB_OHCI_CPU_INIT		1
-#define CFG_USB_OHCI_REGS_BASE		0x00700000	/* AT91_BASE_UHP */
-#define CFG_USB_OHCI_SLOT_NAME		"at91cap9"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00700000	/* AT91_BASE_UHP */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91cap9"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE		1
+#define CONFIG_CMD_FAT			1
 
-#define CFG_LOAD_ADDR			0x72000000	/* load address */
+#define CONFIG_SYS_LOAD_ADDR			0x72000000	/* load address */
 
-#define CFG_MEMTEST_START		PHYS_SDRAM
-#define CFG_MEMTEST_END			0x73e00000
+#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END			0x73e00000
 
-#define CFG_USE_DATAFLASH		1
-#undef CFG_USE_NORFLASH
+#define CONFIG_SYS_USE_DATAFLASH		1
+#undef CONFIG_SYS_USE_NORFLASH
 
-#ifdef CFG_USE_DATAFLASH
+#ifdef CONFIG_SYS_USE_DATAFLASH
 
 /* bootstrap + u-boot + env + linux in dataflash */
 #define CONFIG_ENV_IS_IN_DATAFLASH	1
-#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
 #define CONFIG_ENV_OFFSET		0x4200
-#define CONFIG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_SIZE		0x4200
 #define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x72000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
@@ -164,7 +166,7 @@
 
 /* bootstrap + u-boot + env + linux in norflash */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CFG_MONITOR_BASE	(PHYS_FLASH_1 + 0x8000)
+#define CONFIG_SYS_MONITOR_BASE	(PHYS_FLASH_1 + 0x8000)
 #define CONFIG_ENV_OFFSET		0x4000
 #define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_SIZE		0x4000
@@ -179,21 +181,21 @@
 #endif
 
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
 
-#define CFG_PROMPT		"U-Boot> "
-#define CFG_CBSIZE		256
-#define CFG_MAXARGS		16
-#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_LONGHELP		1
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP		1
 #define CONFIG_CMDLINE_EDITING	1
 
 #define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		ROUND(CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CFG_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(CONFIG_ENV_SIZE + 128*1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
 
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
 
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index 000eb0e..5a980d3 100644
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -1,7 +1,7 @@
 /*
  * Rick Bronson <rick@efn.org>
  *
- * Configuation settings for the AT91RM9200DK board.
+ * Configuration settings for the AT91RM9200DK board.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -43,41 +43,43 @@
 #define CONFIG_INITRD_TAG	1
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#define CFG_USE_MAIN_OSCILLATOR		1
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR		1
 /* flash */
-#define MC_PUIA_VAL	0x00000000
-#define MC_PUP_VAL	0x00000000
-#define MC_PUER_VAL	0x00000000
-#define MC_ASR_VAL	0x00000000
-#define MC_AASR_VAL	0x00000000
-#define EBI_CFGR_VAL	0x00000000
-#define SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define CONFIG_SYS_MC_PUIA_VAL	0x00000000
+#define CONFIG_SYS_MC_PUP_VAL	0x00000000
+#define CONFIG_SYS_MC_PUER_VAL	0x00000000
+#define CONFIG_SYS_MC_ASR_VAL	0x00000000
+#define CONFIG_SYS_MC_AASR_VAL	0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
-#define PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
-#define PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
-#define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
+#define CONFIG_SYS_PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+#define CONFIG_SYS_MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
 
 /* sdram */
-#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR_VAL	0x00000000
-#define PIOC_PDR_VAL	0xFFFF0000
-#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
-#define SDRC_CR_VAL	0x2188c155 /* set up the SDRAM */
-#define SDRAM		0x20000000 /* address of the SDRAM */
-#define SDRAM1		0x20000080 /* address of the SDRAM */
-#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
-#define SDRC_MR_VAL	0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1	0x00000004 /* refresh */
-#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
-#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL	0x2188c155 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM	0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1	0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#else
+#define CONFIG_SKIP_RELOCATE_UBOOT
 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 #define CONFIG_BAUDRATE 115200
 
@@ -118,7 +120,7 @@
 
 #define CONFIG_NAND_LEGACY
 
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
 #define SECTORSIZE 512
 
 #define ADDR_COLUMN 1
@@ -127,7 +129,6 @@
 
 #define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
 
 #define AT91_SMART_MEDIA_ALE (1 << 22)	/* our ALE is AD22 */
 #define AT91_SMART_MEDIA_CLE (1 << 21)	/* our CLE is AD21 */
@@ -152,8 +153,8 @@
 #define PHYS_SDRAM 0x20000000
 #define PHYS_SDRAM_SIZE 0x2000000  /* 32 megs */
 
-#define CFG_MEMTEST_START		PHYS_SDRAM
-#define CFG_MEMTEST_END			CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
+#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END			CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
 
 #define CONFIG_DRIVER_ETHER
 #define CONFIG_NET_RETRY_COUNT		20
@@ -165,25 +166,25 @@
 #define DATAFLASH_TCHS	(0x1 << 24)
 
 #define CONFIG_HAS_DATAFLASH		1
-#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
-#define CFG_MAX_DATAFLASH_BANKS		2
-#define CFG_MAX_DATAFLASH_PAGES		16384
-#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* Logical adress for CS0 */
-#define CFG_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* Logical adress for CS3 */
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
+#define CONFIG_SYS_MAX_DATAFLASH_PAGES		16384
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* Logical adress for CS0 */
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* Logical adress for CS3 */
 
 #define PHYS_FLASH_1			0x10000000
 #define PHYS_FLASH_SIZE			0x200000  /* 2 megs main flash */
-#define CFG_FLASH_BASE			PHYS_FLASH_1
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		256
-#define CFG_FLASH_ERASE_TOUT		(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT		(2*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		256
+#define CONFIG_SYS_FLASH_ERASE_TOUT		(2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT		(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #undef	CONFIG_ENV_IS_IN_DATAFLASH
 
 #ifdef CONFIG_ENV_IS_IN_DATAFLASH
 #define CONFIG_ENV_OFFSET			0x20000
-#define CONFIG_ENV_ADDR			(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_SIZE			0x2000  /* 0x8000 */
 #else
 #define CONFIG_ENV_IS_IN_FLASH		1
@@ -197,27 +198,27 @@
 #endif	/* CONFIG_ENV_IS_IN_DATAFLASH */
 
 
-#define CFG_LOAD_ADDR		0x21000000  /* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
 
 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
-#define CFG_BOOT_SIZE		0x6000 /* 24 KBytes */
-#define CFG_U_BOOT_BASE		(PHYS_FLASH_1 + 0x10000)
-#define CFG_U_BOOT_SIZE		0x10000 /* 64 KBytes */
+#define CONFIG_SYS_BOOT_SIZE		0x6000 /* 24 KBytes */
+#define CONFIG_SYS_U_BOOT_BASE		(PHYS_FLASH_1 + 0x10000)
+#define CONFIG_SYS_U_BOOT_SIZE		0x10000 /* 64 KBytes */
 #else
-#define CFG_BOOT_SIZE		0x00 /* 0 KBytes */
-#define CFG_U_BOOT_BASE		PHYS_FLASH_1
-#define CFG_U_BOOT_SIZE		0x60000 /* 384 KBytes */
+#define CONFIG_SYS_BOOT_SIZE		0x00 /* 0 KBytes */
+#define CONFIG_SYS_U_BOOT_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_U_BOOT_SIZE		0x60000 /* 384 KBytes */
 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
 
-#define CFG_BAUDRATE_TABLE	{ 115200, 19200, 38400, 57600, 9600 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 19200, 38400, 57600, 9600 }
 
-#define CFG_PROMPT		"U-Boot> "	/* Monitor Command Prompt */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_PROMPT		"U-Boot> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 
-#define CFG_HZ 1000
-#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2	/* AT91C_TC0_CMR is implicitly set to */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2	/* AT91C_TC0_CMR is implicitly set to */
 						/* AT91C_TC_TIMER_DIV1_CLOCK */
 
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 41d1da3..2f1a41f 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -28,9 +28,12 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		198656000	/* from 18.432 MHz crystal */
-#define AT91_MASTER_CLOCK	99328000	/* peripheral = main / 2 */
-#define CFG_HZ			1000000		/* 1us resolution */
+#define AT91_CPU_NAME		"AT91SAM9260"
+#define AT91_MAIN_CLOCK		18432000	/* 18.432 MHz crystal */
+#define AT91_MASTER_CLOCK	100000000	/* peripheral */
+#define AT91_CPU_CLOCK		200000000	/* cpu */
+#define CONFIG_SYS_AT91_PLLB	0x107c3e18	/* PLLB settings for USB */
+#define CONFIG_SYS_HZ		1000000		/* 1us resolution */
 
 #define AT91_SLOW_CLOCK		32768	/* slow clock */
 
@@ -88,22 +91,21 @@
 
 /* DataFlash */
 #define CONFIG_HAS_DATAFLASH		1
-#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
-#define CFG_MAX_DATAFLASH_BANKS		2
-#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
-#define CFG_DATAFLASH_LOGIC_ADDR_CS1	0xD0000000	/* CS1 */
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1	0xD0000000	/* CS1 */
 #define AT91_SPI_CLK			15000000
 #define DATAFLASH_TCSS			(0x1a << 16)
 #define DATAFLASH_TCHS			(0x1 << 24)
 
 /* NAND flash */
-#define NAND_MAX_CHIPS			1
-#define CFG_MAX_NAND_DEVICE		1
-#define CFG_NAND_BASE			0x40000000
-#define CFG_NAND_DBW_8			1
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			0x40000000
+#define CONFIG_SYS_NAND_DBW_8			1
 
 /* NOR flash - no real flash on this board */
-#define CFG_NO_FLASH			1
+#define CONFIG_SYS_NO_FLASH			1
 
 /* Ethernet */
 #define CONFIG_MACB			1
@@ -114,30 +116,26 @@
 
 /* USB */
 #define CONFIG_USB_OHCI_NEW		1
-#define LITTLEENDIAN			1
 #define CONFIG_DOS_PARTITION		1
-#define CFG_USB_OHCI_CPU_INIT		1
-#define CFG_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9260_UHP_BASE */
-#define CFG_USB_OHCI_SLOT_NAME		"at91sam9260"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9260_UHP_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE		1
+#define CONFIG_CMD_FAT			1
 
-#define CFG_LOAD_ADDR			0x22000000	/* load address */
+#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
 
-#define CFG_MEMTEST_START		PHYS_SDRAM
-#define CFG_MEMTEST_END			0x23e00000
+#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
 
-#undef CFG_USE_DATAFLASH_CS0
-#define CFG_USE_DATAFLASH_CS1		1
-#undef CFG_USE_NANDFLASH
-
-#ifdef CFG_USE_DATAFLASH_CS0
+#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
 
 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 #define CONFIG_ENV_IS_IN_DATAFLASH	1
-#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
 #define CONFIG_ENV_OFFSET		0x4200
-#define CONFIG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_SIZE		0x4200
 #define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
@@ -145,13 +143,13 @@
 				"mtdparts=at91_nand:-(root) "		\
 				"rw rootfstype=jffs2"
 
-#elif CFG_USE_DATAFLASH_CS1
+#elif CONFIG_SYS_USE_DATAFLASH_CS1
 
 /* bootstrap + u-boot + env + linux in dataflash on CS1 */
 #define CONFIG_ENV_IS_IN_DATAFLASH	1
-#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400)
 #define CONFIG_ENV_OFFSET		0x4200
-#define CONFIG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_SIZE		0x4200
 #define CONFIG_BOOTCOMMAND	"cp.b 0xD0042000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
@@ -159,7 +157,7 @@
 				"mtdparts=at91_nand:-(root) "		\
 				"rw rootfstype=jffs2"
 
-#else /* CFG_USE_NANDFLASH */
+#else /* CONFIG_SYS_USE_NANDFLASH */
 
 /* bootstrap + u-boot + env + linux in nandflash */
 #define CONFIG_ENV_IS_IN_NAND	1
@@ -177,21 +175,21 @@
 #endif
 
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
 
-#define CFG_PROMPT		"U-Boot> "
-#define CFG_CBSIZE		256
-#define CFG_MAXARGS		16
-#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_LONGHELP		1
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP		1
 #define CONFIG_CMDLINE_EDITING	1
 
 #define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CFG_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
 
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
 
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index 80c3b03..ebecfa4 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -29,9 +29,10 @@
 
 /* ARM asynchronous clock */
 #define AT91_CPU_NAME		"AT91SAM9261"
-#define AT91_MAIN_CLOCK		198656000	/* from 18.432 MHz crystal */
-#define AT91_MASTER_CLOCK	99328000	/* peripheral = main / 2 */
-#define CFG_HZ			1000000		/* 1us resolution */
+#define AT91_MAIN_CLOCK		18432000	/* 18.432 MHz crystal */
+#define AT91_MASTER_CLOCK	100000000	/* peripheral */
+#define AT91_CPU_CLOCK		200000000	/* cpu */
+#define CONFIG_SYS_HZ		1000000		/* 1us resolution */
 
 #define AT91_SLOW_CLOCK		32768	/* slow clock */
 
@@ -63,10 +64,10 @@
 #undef LCD_TEST_PATTERN
 #define CONFIG_LCD_INFO			1
 #define CONFIG_LCD_INFO_BELOW_LOGO	1
-#define CFG_WHITE_ON_BLACK		1
+#define CONFIG_SYS_WHITE_ON_BLACK		1
 #define CONFIG_ATMEL_LCD		1
 #define CONFIG_ATMEL_LCD_BGR555		1
-#define CFG_CONSOLE_IS_IN_ENV		1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
 
 #define CONFIG_BOOTDELAY	3
 
@@ -101,22 +102,21 @@
 
 /* DataFlash */
 #define CONFIG_HAS_DATAFLASH		1
-#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
-#define CFG_MAX_DATAFLASH_BANKS		2
-#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
-#define CFG_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* CS3 */
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* CS3 */
 #define AT91_SPI_CLK			15000000
 #define DATAFLASH_TCSS			(0x1a << 16)
 #define DATAFLASH_TCHS			(0x1 << 24)
 
 /* NAND flash */
-#define NAND_MAX_CHIPS			1
-#define CFG_MAX_NAND_DEVICE		1
-#define CFG_NAND_BASE			0x40000000
-#define CFG_NAND_DBW_8			1
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			0x40000000
+#define CONFIG_SYS_NAND_DBW_8			1
 
 /* NOR flash - no real flash on this board */
-#define CFG_NO_FLASH			1
+#define CONFIG_SYS_NO_FLASH			1
 
 /* Ethernet */
 #define CONFIG_DRIVER_DM9000		1
@@ -129,29 +129,26 @@
 
 /* USB */
 #define CONFIG_USB_OHCI_NEW		1
-#define LITTLEENDIAN			1
 #define CONFIG_DOS_PARTITION		1
-#define CFG_USB_OHCI_CPU_INIT		1
-#define CFG_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9261_UHP_BASE */
-#define CFG_USB_OHCI_SLOT_NAME		"at91sam9261"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9261_UHP_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9261"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE		1
+#define CONFIG_CMD_FAT			1
 
-#define CFG_LOAD_ADDR			0x22000000	/* load address */
+#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
 
-#define CFG_MEMTEST_START		PHYS_SDRAM
-#define CFG_MEMTEST_END			0x23e00000
+#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
 
-#define CFG_USE_DATAFLASH_CS0		1
-#undef CFG_USE_NANDFLASH
-
-#ifdef CFG_USE_DATAFLASH_CS0
+#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
 
 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 #define CONFIG_ENV_IS_IN_DATAFLASH	1
-#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
-#define CONFIG_ENV_OFFSET		0x4200
-#define CONFIG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CONFIG_ENV_OFFSET	0x4200
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_SIZE		0x4200
 #define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
@@ -159,7 +156,21 @@
 				"mtdparts=at91_nand:-(root) "		\
 				"rw rootfstype=jffs2"
 
-#else /* CFG_USE_NANDFLASH */
+#elif CONFIG_SYS_USE_DATAFLASH_CS3
+
+/* bootstrap + u-boot + env + linux in dataflash on CS3 */
+#define CONFIG_ENV_IS_IN_DATAFLASH	1
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + 0x8400)
+#define CONFIG_ENV_OFFSET	0x4200
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_BOOTCOMMAND	"cp.b 0xD0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
+				"root=/dev/mtdblock0 "			\
+				"mtdparts=at91_nand:-(root) "		\
+				"rw rootfstype=jffs2"
+
+#else /* CONFIG_SYS_USE_NANDFLASH */
 
 /* bootstrap + u-boot + env + linux in nandflash */
 #define CONFIG_ENV_IS_IN_NAND	1
@@ -177,21 +188,21 @@
 #endif
 
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
 
-#define CFG_PROMPT		"U-Boot> "
-#define CFG_CBSIZE		256
-#define CFG_MAXARGS		16
-#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_LONGHELP		1
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP		1
 #define CONFIG_CMDLINE_EDITING	1
 
 #define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CFG_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
 
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
 
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index b4368ef..09b871a 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -29,9 +29,11 @@
 
 /* ARM asynchronous clock */
 #define AT91_CPU_NAME		"AT91SAM9263"
-#define AT91_MAIN_CLOCK		199919000	/* from 16.367 MHz crystal */
-#define AT91_MASTER_CLOCK	99959500	/* peripheral = main / 2 */
-#define CFG_HZ			1000000		/* 1us resolution */
+#define AT91_MAIN_CLOCK		16367660	/* 16.367 MHz crystal */
+#define AT91_MASTER_CLOCK	100000000	/* peripheral */
+#define AT91_CPU_CLOCK		200000000	/* cpu */
+#define CONFIG_SYS_AT91_PLLB	0x133a3e8d	/* PLLB settings for USB */
+#define CONFIG_SYS_HZ		1000000		/* 1us resolution */
 
 #define AT91_SLOW_CLOCK		32768	/* slow clock */
 
@@ -63,10 +65,10 @@
 #undef LCD_TEST_PATTERN
 #define CONFIG_LCD_INFO			1
 #define CONFIG_LCD_INFO_BELOW_LOGO	1
-#define CFG_WHITE_ON_BLACK		1
+#define CONFIG_SYS_WHITE_ON_BLACK		1
 #define CONFIG_ATMEL_LCD		1
 #define CONFIG_ATMEL_LCD_BGR555		1
-#define CFG_CONSOLE_IS_IN_ENV		1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
 
 #define CONFIG_BOOTDELAY	3
 
@@ -101,30 +103,29 @@
 
 /* DataFlash */
 #define CONFIG_HAS_DATAFLASH		1
-#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
-#define CFG_MAX_DATAFLASH_BANKS		1
-#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
 #define AT91_SPI_CLK			15000000
 #define DATAFLASH_TCSS			(0x1a << 16)
 #define DATAFLASH_TCHS			(0x1 << 24)
 
 /* NOR flash, if populated */
 #if 1
-#define CFG_NO_FLASH			1
+#define CONFIG_SYS_NO_FLASH			1
 #else
-#define CFG_FLASH_CFI			1
+#define CONFIG_SYS_FLASH_CFI			1
 #define CONFIG_FLASH_CFI_DRIVER		1
 #define PHYS_FLASH_1			0x10000000
-#define CFG_FLASH_BASE			PHYS_FLASH_1
-#define CFG_MAX_FLASH_SECT		256
-#define CFG_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT		256
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
 #endif
 
 /* NAND flash */
-#define NAND_MAX_CHIPS			1
-#define CFG_MAX_NAND_DEVICE		1
-#define CFG_NAND_BASE			0x40000000
-#define CFG_NAND_DBW_8			1
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			0x40000000
+#define CONFIG_SYS_NAND_DBW_8			1
 
 /* Ethernet */
 #define CONFIG_MACB			1
@@ -135,29 +136,26 @@
 
 /* USB */
 #define CONFIG_USB_OHCI_NEW		1
-#define LITTLEENDIAN			1
 #define CONFIG_DOS_PARTITION		1
-#define CFG_USB_OHCI_CPU_INIT		1
-#define CFG_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
-#define CFG_USB_OHCI_SLOT_NAME		"at91sam9263"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE		1
+#define CONFIG_CMD_FAT			1
 
-#define CFG_LOAD_ADDR			0x22000000	/* load address */
+#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
 
-#define CFG_MEMTEST_START		PHYS_SDRAM
-#define CFG_MEMTEST_END			0x23e00000
+#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
 
-#define CFG_USE_DATAFLASH		1
-#undef CFG_USE_NANDFLASH
-
-#ifdef CFG_USE_DATAFLASH
+#ifdef CONFIG_SYS_USE_DATAFLASH
 
 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 #define CONFIG_ENV_IS_IN_DATAFLASH	1
-#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
 #define CONFIG_ENV_OFFSET		0x4200
-#define CONFIG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_SIZE		0x4200
 #define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
@@ -165,7 +163,7 @@
 				"mtdparts=at91_nand:-(root) "\
 				"rw rootfstype=jffs2"
 
-#else /* CFG_USE_NANDFLASH */
+#else /* CONFIG_SYS_USE_NANDFLASH */
 
 /* bootstrap + u-boot + env + linux in nandflash */
 #define CONFIG_ENV_IS_IN_NAND	1
@@ -181,21 +179,21 @@
 #endif
 
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
 
-#define CFG_PROMPT		"U-Boot> "
-#define CFG_CBSIZE		256
-#define CFG_MAXARGS		16
-#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_LONGHELP		1
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP		1
 #define CONFIG_CMDLINE_EDITING	1
 
 #define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CFG_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
 
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
 
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index 32168dc..5bef1fe 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -29,9 +29,10 @@
 
 /* ARM asynchronous clock */
 #define AT91_CPU_NAME		"AT91SAM9RL"
-#define AT91_MAIN_CLOCK		200000000	/* from 12.000 MHz crystal */
-#define AT91_MASTER_CLOCK	100000000	/* peripheral = main / 2 */
-#define CFG_HZ			1000000		/* 1us resolution */
+#define AT91_MAIN_CLOCK		12000000	/* 12 MHz crystal */
+#define AT91_MASTER_CLOCK	100000000	/* peripheral */
+#define AT91_CPU_CLOCK		200000000	/* cpu */
+#define CONFIG_SYS_HZ		1000000		/* 1us resolution */
 
 #define AT91_SLOW_CLOCK		32768	/* slow clock */
 
@@ -63,10 +64,10 @@
 #undef LCD_TEST_PATTERN
 #define CONFIG_LCD_INFO			1
 #define CONFIG_LCD_INFO_BELOW_LOGO	1
-#define CFG_WHITE_ON_BLACK		1
+#define CONFIG_SYS_WHITE_ON_BLACK		1
 #define CONFIG_ATMEL_LCD		1
 #define CONFIG_ATMEL_LCD_RGB565		1
-#define CFG_CONSOLE_IS_IN_ENV		1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
 
 #define CONFIG_BOOTDELAY	3
 
@@ -92,41 +93,37 @@
 
 /* DataFlash */
 #define CONFIG_HAS_DATAFLASH		1
-#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
-#define CFG_MAX_DATAFLASH_BANKS		1
-#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
 #define AT91_SPI_CLK			15000000
 #define DATAFLASH_TCSS			(0x1a << 16)
 #define DATAFLASH_TCHS			(0x1 << 24)
 
 /* NOR flash - not present */
-#define CFG_NO_FLASH			1
+#define CONFIG_SYS_NO_FLASH			1
 
 /* NAND flash */
-#define NAND_MAX_CHIPS			1
-#define CFG_MAX_NAND_DEVICE		1
-#define CFG_NAND_BASE			0x40000000
-#define CFG_NAND_DBW_8			1
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			0x40000000
+#define CONFIG_SYS_NAND_DBW_8			1
 
 /* Ethernet - not present */
 
 /* USB - not supported */
 
-#define CFG_LOAD_ADDR			0x22000000	/* load address */
+#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
 
-#define CFG_MEMTEST_START		PHYS_SDRAM
-#define CFG_MEMTEST_END			0x23e00000
+#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
 
-#define CFG_USE_DATAFLASH		1
-#undef CFG_USE_NANDFLASH
-
-#ifdef CFG_USE_DATAFLASH
+#ifdef CONFIG_SYS_USE_DATAFLASH
 
 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 #define CONFIG_ENV_IS_IN_DATAFLASH	1
-#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
 #define CONFIG_ENV_OFFSET		0x4200
-#define CONFIG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_SIZE		0x4200
 #define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
@@ -134,7 +131,7 @@
 				"mtdparts=at91_nand:-(root) "\
 				"rw rootfstype=jffs2"
 
-#else /* CFG_USE_NANDFLASH */
+#else /* CONFIG_SYS_USE_NANDFLASH */
 
 /* bootstrap + u-boot + env + linux in nandflash */
 #define CONFIG_ENV_IS_IN_NAND	1
@@ -150,21 +147,21 @@
 #endif
 
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
 
-#define CFG_PROMPT		"U-Boot> "
-#define CFG_CBSIZE		256
-#define CFG_MAXARGS		16
-#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_LONGHELP		1
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP		1
 #define CONFIG_CMDLINE_EDITING	1
 
 #define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CFG_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
 
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
 
diff --git a/include/configs/atc.h b/include/configs/atc.h
index 02ec239..24015b7 100644
--- a/include/configs/atc.h
+++ b/include/configs/atc.h
@@ -79,10 +79,10 @@
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 #define CONFIG_ETHER_ON_FCC3
 
@@ -92,8 +92,8 @@
  * - RAM for BD/Buffers is on the local Bus (see 28-13)
  * - Enable Half Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK3	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CFG_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+# define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 
 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 #define CONFIG_8260_CLKIN	64000000	/* in Hz */
@@ -120,7 +120,7 @@
  */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 
 /*
@@ -150,31 +150,31 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/
 
-#define CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+#define CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define	CFG_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
+#define	CONFIG_SYS_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
 
-#define CFG_ALLOC_DPRAM
+#define CONFIG_SYS_ALLOC_DPRAM
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -193,92 +193,92 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * Flash configuration
  */
 
-#define CFG_FLASH_BASE		0xFF000000
-#define CFG_FLASH_SIZE		0x00800000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
 
 #define CONFIG_FLASH_16BIT
 
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  *
- * if you change bits in the HRCW, you must also change the CFG_*
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
  * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
  */
-#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
 				 HRCW_BPS10 |\
 				 HRCW_APPC10)
 
 /* no slaves so just fill with zeros */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR		0xF0000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00  /* End of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  *
- * 60x SDRAM is mapped at CFG_SDRAM_BASE.
+ * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-# define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT
 #endif
 
 #define	CONFIG_PCI
 #define	CONFIG_PCI_PNP
-#define	CFG_PCI_MSTR_IO_BUS	0x00000000	/* PCI base   */
+#define	CONFIG_SYS_PCI_MSTR_IO_BUS	0x00000000	/* PCI base   */
 
 #if 1
 /* environment is in Flash */
 #define CONFIG_ENV_IS_IN_FLASH	1
-# define CONFIG_ENV_ADDR		(CFG_FLASH_BASE+0x30000)
+# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x30000)
 # define CONFIG_ENV_SIZE		0x10000
 # define CONFIG_ENV_SECT_SIZE	0x10000
 #else
 #define CONFIG_ENV_IS_IN_EEPROM	1
 #define CONFIG_ENV_OFFSET		0
 #define CONFIG_ENV_SIZE		2048
-#define CFG_EEPROM_PAGE_WRITE_BITS	4	/* 16-byte page size	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4	/* 16-byte page size	*/
 #endif
 /*
  * Internal Definitions
@@ -292,9 +292,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 #if defined(CONFIG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -307,30 +307,30 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
+#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
 			 HID0_DCI|HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
-#define CFG_HID2        0
+#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2        0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register                                     5-5
  *-----------------------------------------------------------------------
  * turn on Checkstop Reset Enable
  */
-#define CFG_RMR         RMR_CSRE
+#define CONFIG_SYS_RMR         RMR_CSRE
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration                                       4-25
  *-----------------------------------------------------------------------
  */
 #define BCR_APD01	0x10000000
-#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration                             4-31
  *-----------------------------------------------------------------------
  */
-#define CFG_SIUMCR      (SIUMCR_BBD|SIUMCR_APPC10|\
+#define CONFIG_SYS_SIUMCR      (SIUMCR_BBD|SIUMCR_APPC10|\
 			 SIUMCR_CS10PC00|SIUMCR_BCTLC10)
 
 /*-----------------------------------------------------------------------
@@ -340,10 +340,10 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
@@ -353,7 +353,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control                 4-42
@@ -361,33 +361,33 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control                                   9-8
  *-----------------------------------------------------------------------
  * Ensure DFBRG is Divide by 16
  */
-#define CFG_SCCR        SCCR_DFBRG01
+#define CONFIG_SYS_SCCR        SCCR_DFBRG01
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration                         13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR        0
+#define CONFIG_SYS_RCCR        0
 
-#define CFG_MIN_AM_MASK	0xC0000000
+#define CONFIG_SYS_MIN_AM_MASK	0xC0000000
 /*-----------------------------------------------------------------------
  * MPTPR - Memory Refresh Timer Prescaler Register              10-18
  *-----------------------------------------------------------------------
  */
-#define CFG_MPTPR       0x1F00
+#define CONFIG_SYS_MPTPR       0x1F00
 
 /*-----------------------------------------------------------------------
  * PSRT - Refresh Timer Register                                10-16
  *-----------------------------------------------------------------------
  */
-#define CFG_PSRT        0x0f
+#define CONFIG_SYS_PSRT        0x0f
 
 /*-----------------------------------------------------------------------
  * PSRT - SDRAM Mode Register                                   10-10
@@ -396,12 +396,12 @@
 
 	/* SDRAM initialization values for 8-column chips
 	 */
-#define CFG_OR2_8COL	(CFG_MIN_AM_MASK		|\
+#define CONFIG_SYS_OR2_8COL	(CONFIG_SYS_MIN_AM_MASK		|\
 			 ORxS_BPD_4			|\
 			 ORxS_ROWST_PBI1_A7		|\
 			 ORxS_NUMR_12)
 
-#define CFG_PSDMR_8COL	(PSDMR_PBI			|\
+#define CONFIG_SYS_PSDMR_8COL	(PSDMR_PBI			|\
 			 PSDMR_SDAM_A15_IS_A5		|\
 			 PSDMR_BSMA_A15_A17		|\
 			 PSDMR_SDA10_PBI1_A7		|\
@@ -414,12 +414,12 @@
 
 	/* SDRAM initialization values for 9-column chips
 	 */
-#define CFG_OR2_9COL	(CFG_MIN_AM_MASK		|\
+#define CONFIG_SYS_OR2_9COL	(CONFIG_SYS_MIN_AM_MASK		|\
 			 ORxS_BPD_4			|\
 			 ORxS_ROWST_PBI1_A6		|\
 			 ORxS_NUMR_12)
 
-#define CFG_PSDMR_9COL	(PSDMR_PBI			|\
+#define CONFIG_SYS_PSDMR_9COL	(PSDMR_PBI			|\
 			 PSDMR_SDAM_A16_IS_A5		|\
 			 PSDMR_BSMA_A15_A17		|\
 			 PSDMR_SDA10_PBI1_A6		|\
@@ -441,16 +441,16 @@
  *
  */
 
-#define CFG_MRS_OFFS	0x00000000
+#define CONFIG_SYS_MRS_OFFS	0x00000000
 
 /* Bank 0 - FLASH
  */
-#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_16                      |\
 			 BRx_MS_GPCM_P                  |\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)     |\
+#define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
 			 ORxG_CSNT                      |\
 			 ORxG_ACS_DIV1                  |\
 			 ORxG_SCY_3_CLK                 |\
@@ -459,23 +459,23 @@
 
 /* Bank 2 - 60x bus SDRAM
  */
-#ifndef CFG_RAMBOOT
-#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_64                      |\
 			 BRx_MS_SDRAM_P                 |\
 			 BRx_V)
 
-#define CFG_OR2_PRELIM	 CFG_OR2_8COL
+#define CONFIG_SYS_OR2_PRELIM	 CONFIG_SYS_OR2_8COL
 
-#define CFG_PSDMR	 CFG_PSDMR_8COL
-#endif /* CFG_RAMBOOT */
+#define CONFIG_SYS_PSDMR	 CONFIG_SYS_PSDMR_8COL
+#endif /* CONFIG_SYS_RAMBOOT */
 
-#define CFG_BR4_PRELIM  ((RTC_BASE_ADDR & BRx_BA_MSK)   |\
+#define CONFIG_SYS_BR4_PRELIM  ((RTC_BASE_ADDR & BRx_BA_MSK)   |\
 			 BRx_PS_8                       |\
 			 BRx_MS_UPMA                    |\
 			 BRx_V)
 
-#define CFG_OR4_PRELIM  (ORxU_AM_MSK | ORxU_BI)
+#define CONFIG_SYS_OR4_PRELIM  (ORxU_AM_MSK | ORxU_BI)
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
@@ -484,8 +484,8 @@
  */
 #define CONFIG_I82365
 
-#define CFG_PCMCIA_MEM_ADDR	0x81000000
-#define CFG_PCMCIA_MEM_SIZE	0x1000
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	0x81000000
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	0x1000
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -498,20 +498,20 @@
 #undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	0xa0000000
+#define CONFIG_SYS_ATA_BASE_ADDR	0xa0000000
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	0x100
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x100
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	0x100
+#define CONFIG_SYS_ATA_REG_OFFSET	0x100
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x108
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x108
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 5c28638..c998952 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -31,7 +31,7 @@
 #define CONFIG_AT32AP7000		1
 #define CONFIG_ATNGW100			1
 
-#define CFG_HZ				1000
+#define CONFIG_SYS_HZ				1000
 
 /*
  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
@@ -39,15 +39,15 @@
  * and the PBA bus to run at 1/4 the PLL frequency.
  */
 #define CONFIG_PLL			1
-#define CFG_POWER_MANAGER		1
-#define CFG_OSC0_HZ			20000000
-#define CFG_PLL0_DIV			1
-#define CFG_PLL0_MUL			7
-#define CFG_PLL0_SUPPRESS_CYCLES	16
-#define CFG_CLKDIV_CPU			0
-#define CFG_CLKDIV_HSB			1
-#define CFG_CLKDIV_PBA			2
-#define CFG_CLKDIV_PBB			1
+#define CONFIG_SYS_POWER_MANAGER		1
+#define CONFIG_SYS_OSC0_HZ			20000000
+#define CONFIG_SYS_PLL0_DIV			1
+#define CONFIG_SYS_PLL0_MUL			7
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
+#define CONFIG_SYS_CLKDIV_CPU			0
+#define CONFIG_SYS_CLKDIV_HSB			1
+#define CONFIG_SYS_CLKDIV_PBA			2
+#define CONFIG_SYS_CLKDIV_PBB			1
 
 /*
  * The PLLOPT register controls the PLL like this:
@@ -56,7 +56,7 @@
  *
  * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
  */
-#define CFG_PLL0_OPT			0x04
+#define CONFIG_SYS_PLL0_OPT			0x04
 
 #define CONFIG_USART1			1
 
@@ -124,9 +124,9 @@
 
 #define CONFIG_ATMEL_USART		1
 #define CONFIG_MACB			1
-#define CONFIG_PIO2			1
-#define CFG_NR_PIOS			5
-#define CFG_HSDRAMC			1
+#define CONFIG_PORTMUX_PIO		1
+#define CONFIG_SYS_NR_PIOS			5
+#define CONFIG_SYS_HSDRAMC			1
 #define CONFIG_MMC			1
 #define CONFIG_ATMEL_MCI		1
 #define CONFIG_ATMEL_SPI		1
@@ -134,48 +134,48 @@
 #define CONFIG_SPI_FLASH		1
 #define CONFIG_SPI_FLASH_ATMEL		1
 
-#define CFG_DCACHE_LINESZ		32
-#define CFG_ICACHE_LINESZ		32
+#define CONFIG_SYS_DCACHE_LINESZ		32
+#define CONFIG_SYS_ICACHE_LINESZ		32
 
 #define CONFIG_NR_DRAM_BANKS		1
 
-#define CFG_FLASH_CFI			1
+#define CONFIG_SYS_FLASH_CFI			1
 #define CONFIG_FLASH_CFI_DRIVER		1
 
-#define CFG_FLASH_BASE			0x00000000
-#define CFG_FLASH_SIZE			0x800000
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		135
+#define CONFIG_SYS_FLASH_BASE			0x00000000
+#define CONFIG_SYS_FLASH_SIZE			0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		135
 
-#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 
-#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
-#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
-#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
+#define CONFIG_SYS_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE			EBI_SDRAM_BASE
 
 #define CONFIG_ENV_IS_IN_FLASH		1
 #define CONFIG_ENV_SIZE			65536
-#define CONFIG_ENV_ADDR			(CFG_FLASH_BASE + CFG_FLASH_SIZE - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
 
-#define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
 
-#define CFG_MALLOC_LEN			(256*1024)
-#define CFG_DMA_ALLOC_LEN		(16384)
+#define CONFIG_SYS_MALLOC_LEN			(256*1024)
+#define CONFIG_SYS_DMA_ALLOC_LEN		(16384)
 
 /* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
-#define CFG_BOOTPARAMS_LEN		(16 * 1024)
+#define CONFIG_SYS_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT			"U-Boot> "
-#define CFG_CBSIZE			256
-#define CFG_MAXARGS			16
-#define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_LONGHELP			1
+#define CONFIG_SYS_PROMPT			"U-Boot> "
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP			1
 
-#define CFG_MEMTEST_START		EBI_SDRAM_BASE
-#define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x1f00000)
+#define CONFIG_SYS_MEMTEST_START		EBI_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + 0x1f00000)
 
-#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index faa7a01..2284277 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -38,40 +38,40 @@
  * Timer clock frequency. We're using the CPU-internal COUNT register
  * for this, so this is equivalent to the CPU core clock frequency
  */
-#define CFG_HZ				1000
+#define CONFIG_SYS_HZ				1000
 
 /*
  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
  * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
  * PLL frequency.
- * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
+ * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
  */
 #define CONFIG_PLL			1
-#define CFG_POWER_MANAGER		1
-#define CFG_OSC0_HZ			20000000
-#define CFG_PLL0_DIV			1
-#define CFG_PLL0_MUL			7
-#define CFG_PLL0_SUPPRESS_CYCLES	16
+#define CONFIG_SYS_POWER_MANAGER		1
+#define CONFIG_SYS_OSC0_HZ			20000000
+#define CONFIG_SYS_PLL0_DIV			1
+#define CONFIG_SYS_PLL0_MUL			7
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
 /*
  * Set the CPU running at:
- * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
  */
-#define CFG_CLKDIV_CPU			0
+#define CONFIG_SYS_CLKDIV_CPU			0
 /*
  * Set the HSB running at:
- * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
  */
-#define CFG_CLKDIV_HSB			1
+#define CONFIG_SYS_CLKDIV_HSB			1
 /*
  * Set the PBA running at:
- * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
  */
-#define CFG_CLKDIV_PBA			2
+#define CONFIG_SYS_CLKDIV_PBA			2
 /*
  * Set the PBB running at:
- * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
  */
-#define CFG_CLKDIV_PBB			1
+#define CONFIG_SYS_CLKDIV_PBB			1
 
 /*
  * The PLLOPT register controls the PLL like this:
@@ -80,7 +80,7 @@
  *
  * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
  */
-#define CFG_PLL0_OPT			0x04
+#define CONFIG_SYS_PLL0_OPT			0x04
 
 #undef CONFIG_USART0
 #define CONFIG_USART1			1
@@ -149,56 +149,56 @@
 
 #define CONFIG_ATMEL_USART		1
 #define CONFIG_MACB			1
-#define CONFIG_PIO2			1
-#define CFG_NR_PIOS			5
-#define CFG_HSDRAMC			1
+#define CONFIG_PORTMUX_PIO		1
+#define CONFIG_SYS_NR_PIOS			5
+#define CONFIG_SYS_HSDRAMC			1
 #define CONFIG_MMC			1
 #define CONFIG_ATMEL_MCI		1
 
-#define CFG_DCACHE_LINESZ		32
-#define CFG_ICACHE_LINESZ		32
+#define CONFIG_SYS_DCACHE_LINESZ		32
+#define CONFIG_SYS_ICACHE_LINESZ		32
 
 #define CONFIG_NR_DRAM_BANKS		1
 
 /* External flash on STK1000 */
 #if 0
-#define CFG_FLASH_CFI			1
+#define CONFIG_SYS_FLASH_CFI			1
 #define CONFIG_FLASH_CFI_DRIVER		1
 #endif
 
-#define CFG_FLASH_BASE			0x00000000
-#define CFG_FLASH_SIZE			0x800000
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		135
+#define CONFIG_SYS_FLASH_BASE			0x00000000
+#define CONFIG_SYS_FLASH_SIZE			0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		135
 
-#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 
-#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
-#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
-#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
+#define CONFIG_SYS_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE			EBI_SDRAM_BASE
 
 #define CONFIG_ENV_IS_IN_FLASH		1
 #define CONFIG_ENV_SIZE			65536
-#define CONFIG_ENV_ADDR			(CFG_FLASH_BASE + CFG_FLASH_SIZE - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
 
-#define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
 
-#define CFG_MALLOC_LEN			(256*1024)
-#define CFG_DMA_ALLOC_LEN		(16384)
+#define CONFIG_SYS_MALLOC_LEN			(256*1024)
+#define CONFIG_SYS_DMA_ALLOC_LEN		(16384)
 
 /* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
-#define CFG_BOOTPARAMS_LEN		(16 * 1024)
+#define CONFIG_SYS_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT			"U-Boot> "
-#define CFG_CBSIZE			256
-#define CFG_MAXARGS			16
-#define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_LONGHELP			1
-
-#define CFG_MEMTEST_START		EBI_SDRAM_BASE
-#define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x700000)
-#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+#define CONFIG_SYS_PROMPT			"U-Boot> "
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP			1
+
+#define CONFIG_SYS_MEMTEST_START		EBI_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + 0x700000)
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h
index e3084d4..2ef2552 100644
--- a/include/configs/atstk1003.h
+++ b/include/configs/atstk1003.h
@@ -38,40 +38,40 @@
  * Timer clock frequency. We're using the CPU-internal COUNT register
  * for this, so this is equivalent to the CPU core clock frequency
  */
-#define CFG_HZ				1000
+#define CONFIG_SYS_HZ				1000
 
 /*
  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
  * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
  * PLL frequency.
- * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
+ * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
  */
 #define CONFIG_PLL			1
-#define CFG_POWER_MANAGER		1
-#define CFG_OSC0_HZ			20000000
-#define CFG_PLL0_DIV			1
-#define CFG_PLL0_MUL			7
-#define CFG_PLL0_SUPPRESS_CYCLES	16
+#define CONFIG_SYS_POWER_MANAGER		1
+#define CONFIG_SYS_OSC0_HZ			20000000
+#define CONFIG_SYS_PLL0_DIV			1
+#define CONFIG_SYS_PLL0_MUL			7
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
 /*
  * Set the CPU running at:
- * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
  */
-#define CFG_CLKDIV_CPU			0
+#define CONFIG_SYS_CLKDIV_CPU			0
 /*
  * Set the HSB running at:
- * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
  */
-#define CFG_CLKDIV_HSB			1
+#define CONFIG_SYS_CLKDIV_HSB			1
 /*
  * Set the PBA running at:
- * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
  */
-#define CFG_CLKDIV_PBA			2
+#define CONFIG_SYS_CLKDIV_PBA			2
 /*
  * Set the PBB running at:
- * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
  */
-#define CFG_CLKDIV_PBB			1
+#define CONFIG_SYS_CLKDIV_PBB			1
 
 /*
  * The PLLOPT register controls the PLL like this:
@@ -80,7 +80,7 @@
  *
  * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
  */
-#define CFG_PLL0_OPT			0x04
+#define CONFIG_SYS_PLL0_OPT			0x04
 
 #undef CONFIG_USART0
 #define CONFIG_USART1			1
@@ -133,54 +133,54 @@
 #undef CONFIG_CMD_XIMG
 
 #define CONFIG_ATMEL_USART		1
-#define CONFIG_PIO2			1
-#define CFG_HSDRAMC			1
+#define CONFIG_PORTMUX_PIO		1
+#define CONFIG_SYS_HSDRAMC			1
 #define CONFIG_MMC			1
 #define CONFIG_ATMEL_MCI		1
 
-#define CFG_DCACHE_LINESZ		32
-#define CFG_ICACHE_LINESZ		32
+#define CONFIG_SYS_DCACHE_LINESZ		32
+#define CONFIG_SYS_ICACHE_LINESZ		32
 
 #define CONFIG_NR_DRAM_BANKS		1
 
 /* External flash on STK1000 */
 #if 0
-#define CFG_FLASH_CFI			1
+#define CONFIG_SYS_FLASH_CFI			1
 #define CONFIG_FLASH_CFI_DRIVER		1
 #endif
 
-#define CFG_FLASH_BASE			0x00000000
-#define CFG_FLASH_SIZE			0x800000
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		135
+#define CONFIG_SYS_FLASH_BASE			0x00000000
+#define CONFIG_SYS_FLASH_SIZE			0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		135
 
-#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 
-#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
-#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
-#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
+#define CONFIG_SYS_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE			EBI_SDRAM_BASE
 
 #define CONFIG_ENV_IS_IN_FLASH		1
 #define CONFIG_ENV_SIZE			65536
-#define CONFIG_ENV_ADDR			(CFG_FLASH_BASE + CFG_FLASH_SIZE - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
 
-#define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
 
-#define CFG_MALLOC_LEN			(256*1024)
+#define CONFIG_SYS_MALLOC_LEN			(256*1024)
 
 /* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
-#define CFG_BOOTPARAMS_LEN		(16 * 1024)
+#define CONFIG_SYS_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT			"U-Boot> "
-#define CFG_CBSIZE			256
-#define CFG_MAXARGS			16
-#define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_LONGHELP			1
-
-#define CFG_MEMTEST_START		EBI_SDRAM_BASE
-#define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x700000)
-#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+#define CONFIG_SYS_PROMPT			"U-Boot> "
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP			1
+
+#define CONFIG_SYS_MEMTEST_START		EBI_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + 0x700000)
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h
index c87c5b7..195be82 100644
--- a/include/configs/atstk1004.h
+++ b/include/configs/atstk1004.h
@@ -38,40 +38,40 @@
  * Timer clock frequency. We're using the CPU-internal COUNT register
  * for this, so this is equivalent to the CPU core clock frequency
  */
-#define CFG_HZ				1000
+#define CONFIG_SYS_HZ				1000
 
 /*
  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
  * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
  * PLL frequency.
- * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
+ * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
  */
 #define CONFIG_PLL			1
-#define CFG_POWER_MANAGER		1
-#define CFG_OSC0_HZ			20000000
-#define CFG_PLL0_DIV			1
-#define CFG_PLL0_MUL			7
-#define CFG_PLL0_SUPPRESS_CYCLES	16
+#define CONFIG_SYS_POWER_MANAGER		1
+#define CONFIG_SYS_OSC0_HZ			20000000
+#define CONFIG_SYS_PLL0_DIV			1
+#define CONFIG_SYS_PLL0_MUL			7
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
 /*
  * Set the CPU running at:
- * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
  */
-#define CFG_CLKDIV_CPU			0
+#define CONFIG_SYS_CLKDIV_CPU			0
 /*
  * Set the HSB running at:
- * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
  */
-#define CFG_CLKDIV_HSB			1
+#define CONFIG_SYS_CLKDIV_HSB			1
 /*
  * Set the PBA running at:
- * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
  */
-#define CFG_CLKDIV_PBA			2
+#define CONFIG_SYS_CLKDIV_PBA			2
 /*
  * Set the PBB running at:
- * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
  */
-#define CFG_CLKDIV_PBB			1
+#define CONFIG_SYS_CLKDIV_PBB			1
 
 /*
  * The PLLOPT register controls the PLL like this:
@@ -80,7 +80,7 @@
  *
  * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
  */
-#define CFG_PLL0_OPT			0x04
+#define CONFIG_SYS_PLL0_OPT			0x04
 
 #undef CONFIG_USART0
 #define CONFIG_USART1			1
@@ -133,54 +133,54 @@
 #undef CONFIG_CMD_XIMG
 
 #define CONFIG_ATMEL_USART		1
-#define CONFIG_PIO2			1
-#define CFG_HSDRAMC			1
+#define CONFIG_PORTMUX_PIO		1
+#define CONFIG_SYS_HSDRAMC			1
 #define CONFIG_MMC			1
 #define CONFIG_ATMEL_MCI		1
 
-#define CFG_DCACHE_LINESZ		32
-#define CFG_ICACHE_LINESZ		32
+#define CONFIG_SYS_DCACHE_LINESZ		32
+#define CONFIG_SYS_ICACHE_LINESZ		32
 
 #define CONFIG_NR_DRAM_BANKS		1
 
 /* External flash on STK1000 */
 #if 0
-#define CFG_FLASH_CFI			1
+#define CONFIG_SYS_FLASH_CFI			1
 #define CONFIG_FLASH_CFI_DRIVER		1
 #endif
 
-#define CFG_FLASH_BASE			0x00000000
-#define CFG_FLASH_SIZE			0x800000
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		135
+#define CONFIG_SYS_FLASH_BASE			0x00000000
+#define CONFIG_SYS_FLASH_SIZE			0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		135
 
-#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 
-#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
-#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
-#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
+#define CONFIG_SYS_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE			EBI_SDRAM_BASE
 
 #define CONFIG_ENV_IS_IN_FLASH		1
 #define CONFIG_ENV_SIZE			65536
-#define CONFIG_ENV_ADDR			(CFG_FLASH_BASE + CFG_FLASH_SIZE - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
 
-#define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
 
-#define CFG_MALLOC_LEN			(256*1024)
+#define CONFIG_SYS_MALLOC_LEN			(256*1024)
 
 /* Allow 2MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00200000)
-#define CFG_BOOTPARAMS_LEN		(16 * 1024)
+#define CONFIG_SYS_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00200000)
+#define CONFIG_SYS_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT			"U-Boot> "
-#define CFG_CBSIZE			256
-#define CFG_MAXARGS			16
-#define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_LONGHELP			1
-
-#define CFG_MEMTEST_START		EBI_SDRAM_BASE
-#define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x700000)
-#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+#define CONFIG_SYS_PROMPT			"U-Boot> "
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP			1
+
+#define CONFIG_SYS_MEMTEST_START		EBI_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + 0x700000)
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h
index fe7a99b..8cfa312 100644
--- a/include/configs/atstk1006.h
+++ b/include/configs/atstk1006.h
@@ -38,40 +38,40 @@
  * Timer clock frequency. We're using the CPU-internal COUNT register
  * for this, so this is equivalent to the CPU core clock frequency
  */
-#define CFG_HZ				1000
+#define CONFIG_SYS_HZ				1000
 
 /*
  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
  * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
  * PLL frequency.
- * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
+ * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
  */
 #define CONFIG_PLL			1
-#define CFG_POWER_MANAGER		1
-#define CFG_OSC0_HZ			20000000
-#define CFG_PLL0_DIV			1
-#define CFG_PLL0_MUL			7
-#define CFG_PLL0_SUPPRESS_CYCLES	16
+#define CONFIG_SYS_POWER_MANAGER		1
+#define CONFIG_SYS_OSC0_HZ			20000000
+#define CONFIG_SYS_PLL0_DIV			1
+#define CONFIG_SYS_PLL0_MUL			7
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
 /*
  * Set the CPU running at:
- * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
  */
-#define CFG_CLKDIV_CPU			0
+#define CONFIG_SYS_CLKDIV_CPU			0
 /*
  * Set the HSB running at:
- * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
  */
-#define CFG_CLKDIV_HSB			1
+#define CONFIG_SYS_CLKDIV_HSB			1
 /*
  * Set the PBA running at:
- * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
  */
-#define CFG_CLKDIV_PBA			2
+#define CONFIG_SYS_CLKDIV_PBA			2
 /*
  * Set the PBB running at:
- * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
  */
-#define CFG_CLKDIV_PBB			1
+#define CONFIG_SYS_CLKDIV_PBB			1
 
 /*
  * The PLLOPT register controls the PLL like this:
@@ -80,7 +80,7 @@
  *
  * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
  */
-#define CFG_PLL0_OPT			0x04
+#define CONFIG_SYS_PLL0_OPT			0x04
 
 #undef CONFIG_USART0
 #define CONFIG_USART1			1
@@ -149,56 +149,56 @@
 
 #define CONFIG_ATMEL_USART		1
 #define CONFIG_MACB			1
-#define CONFIG_PIO2			1
-#define CFG_NR_PIOS			5
-#define CFG_HSDRAMC			1
+#define CONFIG_PORTMUX_PIO		1
+#define CONFIG_SYS_NR_PIOS			5
+#define CONFIG_SYS_HSDRAMC			1
 #define CONFIG_MMC			1
 #define CONFIG_ATMEL_MCI		1
 
-#define CFG_DCACHE_LINESZ		32
-#define CFG_ICACHE_LINESZ		32
+#define CONFIG_SYS_DCACHE_LINESZ		32
+#define CONFIG_SYS_ICACHE_LINESZ		32
 
 #define CONFIG_NR_DRAM_BANKS		1
 
 /* External flash on STK1000 */
 #if 0
-#define CFG_FLASH_CFI			1
+#define CONFIG_SYS_FLASH_CFI			1
 #define CONFIG_FLASH_CFI_DRIVER		1
 #endif
 
-#define CFG_FLASH_BASE			0x00000000
-#define CFG_FLASH_SIZE			0x800000
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		135
+#define CONFIG_SYS_FLASH_BASE			0x00000000
+#define CONFIG_SYS_FLASH_SIZE			0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		135
 
-#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 
-#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
-#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
-#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
+#define CONFIG_SYS_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE			EBI_SDRAM_BASE
 
 #define CONFIG_ENV_IS_IN_FLASH		1
 #define CONFIG_ENV_SIZE			65536
-#define CONFIG_ENV_ADDR			(CFG_FLASH_BASE + CFG_FLASH_SIZE - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
 
-#define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
 
-#define CFG_MALLOC_LEN			(256*1024)
-#define CFG_DMA_ALLOC_LEN		(16384)
+#define CONFIG_SYS_MALLOC_LEN			(256*1024)
+#define CONFIG_SYS_DMA_ALLOC_LEN		(16384)
 
 /* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
-#define CFG_BOOTPARAMS_LEN		(16 * 1024)
+#define CONFIG_SYS_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT			"U-Boot> "
-#define CFG_CBSIZE			256
-#define CFG_MAXARGS			16
-#define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_LONGHELP			1
-
-#define CFG_MEMTEST_START		EBI_SDRAM_BASE
-#define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x3f00000)
-#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+#define CONFIG_SYS_PROMPT			"U-Boot> "
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP			1
+
+#define CONFIG_SYS_MEMTEST_START		EBI_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + 0x3f00000)
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index 31c725f..8c4127d 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -55,37 +55,37 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE	        0xfff00000	    /* start of FLASH	*/
-#define CFG_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
-#define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
-#define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
+#define CONFIG_SYS_FLASH_BASE	        0xfff00000	    /* start of FLASH	*/
+#define CONFIG_SYS_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
+#define CONFIG_SYS_PCI_MEMBASE1        CONFIG_SYS_PCI_MEMBASE  + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2        CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3        CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
 
 /*Don't change either of these*/
-#define CFG_PERIPHERAL_BASE     0xef600000	    /* internal peripherals*/
-#define CFG_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
+#define CONFIG_SYS_PERIPHERAL_BASE     0xef600000	    /* internal peripherals*/
+#define CONFIG_SYS_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
 /*Don't change either of these*/
 
-#define CFG_USB_DEVICE          0x50000000
-#define CFG_NVRAM_BASE_ADDR     0x80000000
-#define CFG_BOOT_BASE_ADDR      0xf0000000
-#define CFG_NAND_ADDR           0x90000000
-#define CFG_NAND2_ADDR          0x94000000
+#define CONFIG_SYS_USB_DEVICE          0x50000000
+#define CONFIG_SYS_NVRAM_BASE_ADDR     0x80000000
+#define CONFIG_SYS_BOOT_BASE_ADDR      0xf0000000
+#define CONFIG_SYS_NAND_ADDR           0x90000000
+#define CONFIG_SYS_NAND2_ADDR          0x94000000
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
-#define CFG_INIT_RAM_ADDR	0x70000000	/* DCache       */
-#define CFG_INIT_RAM_END	(4 << 10)
-#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data	*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
+#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000	/* DCache       */
+#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#define CFG_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
 /* define this if you want console on UART1 */
 #undef CONFIG_UART1_CONSOLE
 
@@ -96,7 +96,7 @@
  * The DS1558 code assumes this condition
  *
  *----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE	        (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs     */
+#define CONFIG_SYS_NVRAM_SIZE	        (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs     */
 #define CONFIG_RTC_DS1556	1		         /* DS1556 RTC		*/
 
 /*-----------------------------------------------------------------------
@@ -112,23 +112,23 @@
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS	3	/* number of banks			*/
-#define CFG_MAX_FLASH_SECT	256	/* sectors per device			*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* number of banks			*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* sectors per device			*/
 
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_ADDR0         0x555
-#define CFG_FLASH_ADDR1         0x2aa
-#define CFG_FLASH_WORD_SIZE     unsigned char
+#define CONFIG_SYS_FLASH_ADDR0         0x555
+#define CONFIG_SYS_FLASH_ADDR1         0x2aa
+#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char
 
-#define CFG_FLASH_2ND_16BIT_DEV 1	/* bamboo has 8 and 16bit device	*/
-#define CFG_FLASH_2ND_ADDR      0x87800000  /* bamboo has 8 and 16bit device	*/
+#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1	/* bamboo has 8 and 16bit device	*/
+#define CONFIG_SYS_FLASH_2ND_ADDR      0x87800000  /* bamboo has 8 and 16bit device	*/
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector		*/
-#define CONFIG_ENV_ADDR		((-CFG_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -154,61 +154,60 @@
  * set up. While still running from cache, I experienced problems accessing
  * the NAND controller.	sr - 2006-08-25
  */
-#define CFG_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
-#define CFG_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
-#define CFG_NAND_BOOT_SPL_DST	0x00800000	/* Copy SPL here		*/
-#define CFG_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
-#define CFG_NAND_U_BOOT_START	CFG_NAND_U_BOOT_DST /* Start NUB from this addr	*/
-#define CFG_NAND_BOOT_SPL_DELTA	(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
+#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
+#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
+#define CONFIG_SYS_NAND_BOOT_SPL_DST	0x00800000	/* Copy SPL here		*/
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr	*/
+#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 
 /*
  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
  */
-#define CFG_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
-#define CFG_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/
 
 /*
  * Now the NAND chip has to be defined (no autodetection used!)
  */
-#define CFG_NAND_PAGE_SIZE	512		/* NAND chip page size		*/
-#define CFG_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
-#define CFG_NAND_PAGE_COUNT	32		/* NAND chip page count		*/
-#define CFG_NAND_BAD_BLOCK_POS	5		/* Location of bad block marker	*/
-#define CFG_NAND_4_ADDR_CYCLE	1		/* Fourth addr used (>32MB)	*/
-
-#define CFG_NAND_ECCSIZE	256
-#define CFG_NAND_ECCBYTES	3
-#define CFG_NAND_ECCSTEPS	(CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
-#define CFG_NAND_OOBSIZE	16
-#define CFG_NAND_ECCTOTAL	(CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
-#define CFG_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
+#define CONFIG_SYS_NAND_PAGE_SIZE	512		/* NAND chip page size		*/
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
+#define CONFIG_SYS_NAND_PAGE_COUNT	32		/* NAND chip page count		*/
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	5		/* Location of bad block marker	*/
+#define CONFIG_SYS_NAND_4_ADDR_CYCLE	1		/* Fourth addr used (>32MB)	*/
+
+#define CONFIG_SYS_NAND_ECCSIZE	256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_OOBSIZE	16
+#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
+#define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
 
 #ifdef CONFIG_ENV_IS_IN_NAND
 /*
  * For NAND booting the environment is embedded in the U-Boot image. Please take
  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
  */
-#define CONFIG_ENV_SIZE		CFG_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(CFG_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 #endif
 
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/
-#define CFG_MAX_NAND_DEVICE	2
-#define NAND_MAX_CHIPS		CFG_MAX_NAND_DEVICE
-#define CFG_NAND_BASE		(CFG_NAND_ADDR + CFG_NAND_CS)
-#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE, CFG_NAND_ADDR + 2 }
-#define CFG_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
+#define CONFIG_SYS_MAX_NAND_DEVICE	2
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
+#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
 
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-#define CFG_NAND_CS		1
+#define CONFIG_SYS_NAND_CS		1
 #else
-#define CFG_NAND_CS		0		/* NAND chip connected to CSx	*/
+#define CONFIG_SYS_NAND_CS		0		/* NAND chip connected to CSx	*/
 /* Memory Bank 0 (NAND-FLASH) initialization					*/
-#define CFG_EBC_PB0AP		0x018003c0
-#define CFG_EBC_PB0CR		(CFG_NAND_ADDR | 0x1c000)
+#define CONFIG_SYS_EBC_PB0AP		0x018003c0
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -216,22 +215,21 @@
  *----------------------------------------------------------------------------- */
 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
 #undef CONFIG_DDR_ECC			/* don't use ECC			*/
-#define CFG_SIMULATE_SPD_EEPROM	0xff	/* simulate spd eeprom on this address	*/
-#define SPD_EEPROM_ADDRESS	{CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
-#define CFG_MBYTES_SDRAM	(64)	/* 64MB fixed size for early-sdram-init */
+#define CONFIG_SYS_SIMULATE_SPD_EEPROM	0xff	/* simulate spd eeprom on this address	*/
+#define SPD_EEPROM_ADDRESS	{CONFIG_SYS_SIMULATE_SPD_EEPROM, 0x50, 0x51}
+#define CONFIG_SYS_MBYTES_SDRAM	(64)	/* 64MB fixed size for early-sdram-init */
 #define CONFIG_PROG_SDRAM_TLB
 
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 
 #ifdef CONFIG_ENV_IS_IN_EEPROM
 #define CONFIG_ENV_SIZE		0x200	    /* Size of Environment vars */
@@ -298,13 +296,13 @@
 #define CONFIG_PCI			/* include pci support	        */
 #undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
-#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+#define CONFIG_SYS_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT
-#define CFG_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
 
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever */
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/barco.h b/include/configs/barco.h
index 9afb10e..e00f84a 100644
--- a/include/configs/barco.h
+++ b/include/configs/barco.h
@@ -102,14 +102,14 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		1		/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 
 /*-----------------------------------------------------------------------
@@ -128,58 +128,58 @@
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	0x02000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE	0x02000000
 
 #define CONFIG_LOGBUFFER
 #ifdef	CONFIG_LOGBUFFER
-#define CFG_STDOUT_ADDR		0x1FFC000
+#define CONFIG_SYS_STDOUT_ADDR		0x1FFC000
 #else
-#define CFG_STDOUT_ADDR		0x2B9000
+#define CONFIG_SYS_STDOUT_ADDR		0x2B9000
 #endif
 
-#define CFG_RESET_ADDRESS	0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
 
 #if defined (USE_DINK32)
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	0x00090000
-#define CFG_RAMBOOT		1
-#define CFG_INIT_RAM_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_INIT_RAM_END	0x10000
-#define CFG_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_LEN		0x00030000
+#define CONFIG_SYS_MONITOR_BASE	0x00090000
+#define CONFIG_SYS_RAMBOOT		1
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_INIT_RAM_END	0x10000
+#define CONFIG_SYS_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #else
-#undef	CFG_RAMBOOT
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	TEXT_BASE
+#undef	CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_MONITOR_LEN		0x00030000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 
-#define CFG_GBL_DATA_SIZE	128
+#define CONFIG_SYS_GBL_DATA_SIZE	128
 
-#define CFG_INIT_RAM_ADDR	0x40000000
-#define CFG_INIT_RAM_END	0x1000
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 #endif
 
-#define CFG_FLASH_BASE		0xFFF00000
-#define CFG_FLASH_SIZE		(8 * 1024 * 1024)	/* Unity has onboard 1MByte flash */
+#define CONFIG_SYS_FLASH_BASE		0xFFF00000
+#define CONFIG_SYS_FLASH_SIZE		(8 * 1024 * 1024)	/* Unity has onboard 1MByte flash */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x000047A4	/* Offset of Environment Sector */
 #define CONFIG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
 /* #define ENV_CRC		0x8BF6F24B	XXX - FIXME: gets defined automatically */
 
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
 
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
 
-#define CFG_EUMB_ADDR		0xFDF00000
+#define CONFIG_SYS_EUMB_ADDR		0xFDF00000
 
-#define CFG_FLASH_RANGE_BASE	0xFFC00000	/* flash memory address range	*/
-#define CFG_FLASH_RANGE_SIZE	0x00400000
+#define CONFIG_SYS_FLASH_RANGE_BASE	0xFFC00000	/* flash memory address range	*/
+#define CONFIG_SYS_FLASH_RANGE_SIZE	0x00400000
 #define FLASH_BASE0_PRELIM	0xFFF00000	/* sandpoint flash		*/
 #define FLASH_BASE1_PRELIM	0xFF000000	/* PMC onboard flash		*/
 
@@ -192,8 +192,8 @@
  */
 #define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
 #undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 #ifdef CONFIG_SOFT_I2C
 #error "Soft I2C is not configured properly.  Please review!"
@@ -208,14 +208,14 @@
 #define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
 #endif /* CONFIG_SOFT_I2C */
 
-#define CFG_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
-#define CFG_DBUS_SIZE2		1
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
+#define CONFIG_SYS_DBUS_SIZE2		1
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
@@ -233,24 +233,24 @@
 
 #define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
 
-#define CFG_ROMNAL		0x0F	/*rom/flash next access time		*/
-#define CFG_ROMFAL		0x1E	/*rom/flash access time			*/
+#define CONFIG_SYS_ROMNAL		0x0F	/*rom/flash next access time		*/
+#define CONFIG_SYS_ROMFAL		0x1E	/*rom/flash access time			*/
 
-#define CFG_REFINT	0x8F	/* no of clock cycles between CBR refresh cycles */
+#define CONFIG_SYS_REFINT	0x8F	/* no of clock cycles between CBR refresh cycles */
 
 /* the following are for SDRAM only*/
-#define CFG_BSTOPRE	0x25C	/* Burst To Precharge, sets open page interval */
-#define CFG_REFREC		8	/* Refresh to activate interval		*/
-#define CFG_RDLAT		4	/* data latency from read command	*/
-#define CFG_PRETOACT		3	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
-#define CFG_ACTORW		2	/* Activate to R/W			*/
-#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
-#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#define CONFIG_SYS_BSTOPRE	0x25C	/* Burst To Precharge, sets open page interval */
+#define CONFIG_SYS_REFREC		8	/* Refresh to activate interval		*/
+#define CONFIG_SYS_RDLAT		4	/* data latency from read command	*/
+#define CONFIG_SYS_PRETOACT		3	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		2	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
 
-#define CFG_REGISTERD_TYPE_BUFFER   1
-#define CFG_EXTROM 0
-#define CFG_REGDIMM 0
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
+#define CONFIG_SYS_EXTROM 0
+#define CONFIG_SYS_REGDIMM 0
 
 
 /* memory bank settings*/
@@ -260,95 +260,95 @@
  * bits will be set to 0x00000 for a start address, or 0xfffff for an
  * end address
  */
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		0x01FFFFFF
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x02000000
-#define CFG_BANK1_END		0x02ffffff
-#define CFG_BANK1_ENABLE	0
-#define CFG_BANK2_START		0x03f00000
-#define CFG_BANK2_END		0x03ffffff
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x04000000
-#define CFG_BANK3_END		0x04ffffff
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x05000000
-#define CFG_BANK4_END		0x05FFFFFF
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x06000000
-#define CFG_BANK5_END		0x06FFFFFF
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x07000000
-#define CFG_BANK6_END		0x07FFFFFF
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x08000000
-#define CFG_BANK7_END		0x08FFFFFF
-#define CFG_BANK7_ENABLE	0
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		0x01FFFFFF
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x02000000
+#define CONFIG_SYS_BANK1_END		0x02ffffff
+#define CONFIG_SYS_BANK1_ENABLE	0
+#define CONFIG_SYS_BANK2_START		0x03f00000
+#define CONFIG_SYS_BANK2_END		0x03ffffff
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x04000000
+#define CONFIG_SYS_BANK3_END		0x04ffffff
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x05000000
+#define CONFIG_SYS_BANK4_END		0x05FFFFFF
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x06000000
+#define CONFIG_SYS_BANK5_END		0x06FFFFFF
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x07000000
+#define CONFIG_SYS_BANK6_END		0x07FFFFFF
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x08000000
+#define CONFIG_SYS_BANK7_END		0x08FFFFFF
+#define CONFIG_SYS_BANK7_ENABLE	0
 /*
  * Memory bank enable bitmask, specifying which of the banks defined above
  are actually present. MSB is for bank #7, LSB is for bank #0.
  */
-#define CFG_BANK_ENABLE		0x01
+#define CONFIG_SYS_BANK_ENABLE		0x01
 
-#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
+#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
 					/* see 8240 book for bit definitions	*/
-#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
 					/* currently accessed page in memory	*/
 					/* see 8240 book for details		*/
 
 /* SDRAM 0 - 256MB */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* stack in DCACHE @ 1GB (no backing mem) */
 #if defined(USE_DINK32)
-#define CFG_IBAT1L	(0x40000000 | BATL_PP_00 )
-#define CFG_IBAT1U	(0x40000000 | BATU_BL_128K )
+#define CONFIG_SYS_IBAT1L	(0x40000000 | BATL_PP_00 )
+#define CONFIG_SYS_IBAT1U	(0x40000000 | BATU_BL_128K )
 #else
-#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 #endif
 
 /* PCI memory */
-#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* Flash, config addrs, etc */
-#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_CHECKSUM
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
index b35e362..48c0252 100644
--- a/include/configs/bf533-ezkit.h
+++ b/include/configs/bf533-ezkit.h
@@ -10,9 +10,9 @@
 #define CONFIG_BAUDRATE		57600
 
 #define CONFIG_BOOTDELAY	5
-#define CFG_AUTOLOAD		"no"	/*rarpb, bootp or dhcp commands will perform only a */
+#define CONFIG_SYS_AUTOLOAD		"no"	/*rarpb, bootp or dhcp commands will perform only a */
 
-#define CFG_LONGHELP		1
+#define CONFIG_SYS_LONGHELP		1
 #define CONFIG_CMDLINE_EDITING	1
 #define CONFIG_LOADADDR		0x01000000	/* default load address */
 #define CONFIG_BOOTCOMMAND	"tftp $(loadaddr) linux"
@@ -23,7 +23,7 @@
 
 #if 0
 #define	CONFIG_MII
-#define CFG_DISCOVER_PHY
+#define CONFIG_SYS_DISCOVER_PHY
 #endif
 
 #define CONFIG_RTC_BFIN		1
@@ -105,48 +105,48 @@
 
 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600"
 
-#define	CFG_PROMPT		"bfin> "	/* Monitor Command Prompt */
+#define	CONFIG_SYS_PROMPT		"bfin> "	/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #endif
-#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on */
-#define CFG_MEMTEST_END		( (CONFIG_MEM_SIZE - 1) * 1024 * 1024)	/* 1 ... 31 MB in DRAM */
-#define	CFG_LOAD_ADDR		0x01000000	/* default load address */
-#define	CFG_HZ			1000	/* decrementer freq: 10 ms ticks */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024 * 1024)
-#define CFG_FLASH_BASE		0x20000000
-
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	(CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_SIZE	0x4000
-#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)
-
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-#define CFG_FLASH0_BASE		0x20000000
-#define CFG_FLASH1_BASE		0x20200000
-#define CFG_FLASH2_BASE		0x20280000
-#define CFG_MAX_FLASH_BANKS	3	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	40	/* max number of sectors on one chip */
+#define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		( (CONFIG_MEM_SIZE - 1) * 1024 * 1024)	/* 1 ... 31 MB in DRAM */
+#define	CONFIG_SYS_LOAD_ADDR		0x01000000	/* default load address */
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 10 ms ticks */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024 * 1024)
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_SIZE	0x4000
+#define CONFIG_SYS_GBL_DATA_ADDR	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE	(CONFIG_SYS_GBL_DATA_ADDR  - 4)
+
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_FLASH0_BASE		0x20000000
+#define CONFIG_SYS_FLASH1_BASE		0x20200000
+#define CONFIG_SYS_FLASH2_BASE		0x20280000
+#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	40	/* max number of sectors on one chip */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		0x20020000
 #define	CONFIG_ENV_SECT_SIZE	0x10000	/* Total Size of Environment Sector */
 
 /* JFFS Partition offset set  */
-#define CFG_JFFS2_FIRST_BANK	0
-#define CFG_JFFS2_NUM_BANKS	1
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
 /* 512k reserved for u-boot */
-#define CFG_JFFS2_FIRST_SECTOR	11
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR	11
 
 
 /*
@@ -157,7 +157,7 @@
 #define POLL_MODE		1
 #define FLASH_TOT_SECT		40
 #define FLASH_SIZE		0x220000
-#define CFG_FLASH_SIZE		0x220000
+#define CONFIG_SYS_FLASH_SIZE		0x220000
 
 /*
  * Initialize PSD4256 registers for using I2C
@@ -197,10 +197,10 @@
 				}
 #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
 
-#define CFG_I2C_SPEED		50000
-#define CFG_I2C_SLAVE		0xFE
+#define CONFIG_SYS_I2C_SPEED		50000
+#define CONFIG_SYS_I2C_SLAVE		0
 
-#define CFG_BOOTM_LEN		0x4000000	/* Large Image Length, set to 64 Meg */
+#define CONFIG_SYS_BOOTM_LEN		0x4000000	/* Large Image Length, set to 64 Meg */
 
 #define CONFIG_EBIU_SDRRC_VAL  0x398
 #define CONFIG_EBIU_SDGCTL_VAL 0x91118d
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index 6e138b8..ee41c7e 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -93,13 +93,13 @@
  * Flash settings
  */
 
-#define CFG_FLASH_CFI		/* The flash is CFI compatible  */
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible  */
 #define CONFIG_FLASH_CFI_DRIVER	/* Use common CFI driver	*/
-#define	CFG_FLASH_CFI_AMD_RESET
+#define	CONFIG_SYS_FLASH_CFI_AMD_RESET
 
-#define CFG_FLASH_BASE		0x20000000
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
 
 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
 #define CONFIG_ENV_IS_IN_EEPROM	1
@@ -108,29 +108,29 @@
 #else
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		0x20004000
-#define	CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CFG_FLASH_BASE)
+#define	CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
 #endif
 
 #define	CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x2000	/* Total Size of Environment Sector */
 #define	ENV_IS_EMBEDDED
 
-#define CFG_FLASH_ERASE_TOUT	30000	/* Timeout for Chip Erase (in ms) */
-#define CFG_FLASH_ERASEBLOCK_TOUT	5000	/* Timeout for Block Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	1	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	30000	/* Timeout for Chip Erase (in ms) */
+#define CONFIG_SYS_FLASH_ERASEBLOCK_TOUT	5000	/* Timeout for Block Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1	/* Timeout for Flash Write (in ms) */
 
 /* JFFS Partition offset set  */
-#define CFG_JFFS2_FIRST_BANK 0
-#define CFG_JFFS2_NUM_BANKS  1
+#define CONFIG_SYS_JFFS2_FIRST_BANK 0
+#define CONFIG_SYS_JFFS2_NUM_BANKS  1
 /* 512k reserved for u-boot */
-#define CFG_JFFS2_FIRST_SECTOR	11
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR	11
 
 /*
  * following timeouts shall be used once the
  * Flash real protection is enabled
  */
-#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
 
 /*
  * SDRAM settings & memory map
@@ -140,27 +140,27 @@
 #define CONFIG_MEM_ADD_WDTH     11	/* 8, 9, 10, 11    */
 #define CONFIG_MEM_MT48LC64M4A2FB_7E	1
 
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
 
-#define	CFG_SDRAM_BASE		0x00000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
 
-#define CFG_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024 *1024)
-#define CFG_MEMTEST_END		(CFG_MAX_RAM_SIZE - 0x80000 - 1)
+#define CONFIG_SYS_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024 *1024)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MAX_RAM_SIZE - 0x80000 - 1)
 #define CONFIG_LOADADDR		0x01000000
 
-#define CFG_LOAD_ADDR		CONFIG_LOADADDR
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)     /* Reserve 128 kB for malloc()	*/
-#define CFG_GBL_DATA_SIZE	0x4000		/* Reserve 16k for Global Data  */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)     /* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	0x4000		/* Reserve 16k for Global Data  */
 #define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
 
-#define CFG_MONITOR_BASE		(CFG_MAX_RAM_SIZE - 0x40000)
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_MAX_RAM_SIZE - 0x40000)
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_ADDR	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE	(CONFIG_SYS_GBL_DATA_ADDR  - 4)
 
 /* Check to make sure everything fits in SDRAM */
-#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE)
+#if ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE)
 	#error Memory Map does not fit into configuration
 #endif
 
@@ -182,10 +182,10 @@
  * Command settings
  */
 
-#define CFG_LONGHELP		1
+#define CONFIG_SYS_LONGHELP		1
 #define CONFIG_CMDLINE_EDITING	1
 
-#define CFG_AUTOLOAD		"no"	/*rarpb, bootp or dhcp commands will perform only a */
+#define CONFIG_SYS_AUTOLOAD		"no"	/*rarpb, bootp or dhcp commands will perform only a */
 
 /* configuration lookup from the BOOTP/DHCP server, */
 /* but not try to load any image using TFTP	    */
@@ -256,18 +256,18 @@
  */
 
 #define CONFIG_BAUDRATE		57600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define	CFG_PROMPT		"bfin> "	/* Monitor Command Prompt */
+#define	CONFIG_SYS_PROMPT		"bfin> "	/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
 #define CONFIG_LOADS_ECHO	1
 
@@ -299,8 +299,8 @@
 				}
 #define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
 
-#define CFG_I2C_SPEED		50000
-#define CFG_I2C_SLAVE		0xFE
+#define CONFIG_SYS_I2C_SPEED		50000
+#define CONFIG_SYS_I2C_SLAVE		0
 #endif /* CONFIG_SOFT_I2C */
 
 /*
@@ -321,26 +321,26 @@
 #undef  CONFIG_IDE_LED			/* no led for ide supported */
 #undef  CONFIG_IDE_RESET		/* no reset for ide supported */
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE busses */
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE busses */
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR	0x20200000
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	0x20200000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_DATA_OFFSET	0x0020	/* Offset for data I/O */
-#define CFG_ATA_REG_OFFSET	0x0020	/* Offset for normal register accesses */
-#define CFG_ATA_ALT_OFFSET	0x0007	/* Offset for alternate registers */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* Offset for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0007	/* Offset for alternate registers */
 
-#define CFG_ATA_STRIDE		2
+#define CONFIG_SYS_ATA_STRIDE		2
 #endif
 
 /*
  * Miscellaneous configurable options
  */
 
-#define	CFG_HZ			1000	/* 1ms time tick */
+#define	CONFIG_SYS_HZ			1000	/* 1ms time tick */
 
-#define CFG_BOOTM_LEN		0x4000000/* Large Image Length, set to 64 Meg */
+#define CONFIG_SYS_BOOTM_LEN		0x4000000/* Large Image Length, set to 64 Meg */
 
 #define CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs */
 
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 01e185a..f6399a9 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -7,7 +7,7 @@
 
 #include <asm/blackfin-config-pre.h>
 
-#define CFG_LONGHELP		1
+#define CONFIG_SYS_LONGHELP		1
 #define CONFIG_CMDLINE_EDITING	1
 #define CONFIG_BAUDRATE		57600
 /* Set default serial console for bf537 */
@@ -81,7 +81,7 @@
  * configuration lookup from the BOOTP/DHCP server
  * but not try to load any image using TFTP
  */
-#define CFG_AUTOLOAD			"no"
+#define CONFIG_SYS_AUTOLOAD			"no"
 
 /*
  * Network Settings
@@ -100,19 +100,19 @@
 /* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
 /* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */
 
-#define CFG_LONGHELP		1
+#define CONFIG_SYS_LONGHELP		1
 #define CONFIG_BOOTDELAY	5
 #define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
 #define CONFIG_BOOTCOMMAND	"run ramboot"
 
 #if defined(CONFIG_POST_TEST)
 /* POST support */
-#define CONFIG_POST		( CFG_POST_MEMORY | \
-				  CFG_POST_UART	  | \
-				  CFG_POST_FLASH  | \
-				  CFG_POST_ETHER  | \
-				  CFG_POST_LED	  | \
-				  CFG_POST_BUTTON)
+#define CONFIG_POST		( CONFIG_SYS_POST_MEMORY | \
+				  CONFIG_SYS_POST_UART	  | \
+				  CONFIG_SYS_POST_FLASH  | \
+				  CONFIG_SYS_POST_ETHER  | \
+				  CONFIG_SYS_POST_LED	  | \
+				  CONFIG_SYS_POST_BUTTON)
 #else
 #undef CONFIG_POST
 #endif
@@ -201,38 +201,38 @@
 	"erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0"	\
 	""
 
-#define	CFG_PROMPT		"bfin> "	/* Monitor Command Prompt */
+#define	CONFIG_SYS_PROMPT		"bfin> "	/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #endif
-#define CFG_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024*1024)
-#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START	0x0	/* memtest works on */
-#define CFG_MEMTEST_END		( (CONFIG_MEM_SIZE - 1) * 1024*1024)	/* 1 ... 63 MB in DRAM */
-#define	CFG_LOAD_ADDR		CONFIG_LOADADDR	/* default load address */
-#define	CFG_HZ			1000	/* decrementer freq: 10 ms ticks */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define	CFG_SDRAM_BASE		0x00000000
-
-#define CFG_FLASH_BASE		0x20000000
-#define CFG_FLASH_CFI		/* The flash is CFI compatible */
+#define CONFIG_SYS_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024*1024)
+#define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_MEMTEST_START	0x0	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		( (CONFIG_MEM_SIZE - 1) * 1024*1024)	/* 1 ... 63 MB in DRAM */
+#define	CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR	/* default load address */
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 10 ms ticks */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible */
 #define CONFIG_FLASH_CFI_DRIVER	/* Use common CFI driver */
-#define CFG_FLASH_PROTECTION
-#define CFG_MAX_FLASH_BANKS	1
-#define CFG_MAX_FLASH_SECT	71	/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
-
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	(CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_SIZE	0x4000
-#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
+
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_SIZE	0x4000
+#define CONFIG_SYS_GBL_DATA_ADDR	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE	(CONFIG_SYS_GBL_DATA_ADDR  - 4)
 
 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
 #define CONFIG_ENV_IS_IN_EEPROM	1
@@ -241,17 +241,17 @@
 #else
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		0x20004000
-#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CFG_FLASH_BASE)
+#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
 #endif
 #define CONFIG_ENV_SIZE		0x2000
 #define	CONFIG_ENV_SECT_SIZE	0x2000	/* Total Size of Environment Sector */
 #define ENV_IS_EMBEDDED
 
 /* JFFS Partition offset set  */
-#define CFG_JFFS2_FIRST_BANK	0
-#define CFG_JFFS2_NUM_BANKS	1
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
 /* 512k reserved for u-boot */
-#define CFG_JFFS2_FIRST_SECTOR	15
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR	15
 
 #define CONFIG_SPI
 
@@ -263,22 +263,21 @@
 #define POLL_MODE		1
 #define FLASH_TOT_SECT		71
 #define FLASH_SIZE		0x400000
-#define CFG_FLASH_SIZE		0x400000
+#define CONFIG_SYS_FLASH_SIZE		0x400000
 
 /*
  * Board NAND Infomation
  */
 
-#define CFG_NAND_ADDR		0x20212000
-#define CFG_NAND_BASE		CFG_NAND_ADDR
-#define CFG_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_ADDR		0x20212000
+#define CONFIG_SYS_NAND_BASE		CONFIG_SYS_NAND_ADDR
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define SECTORSIZE		512
 #define ADDR_COLUMN		1
 #define ADDR_PAGE		2
 #define ADDR_COLUMN_PAGE	3
 #define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS		1
-#define NAND_MAX_CHIPS		1
 #define BFIN_NAND_READY		PF3
 
 #define NAND_WAIT_READY(nand)			\
@@ -302,17 +301,15 @@
  */
 #define CONFIG_MISC_INIT_R
 
-#define CFG_BOOTM_LEN		0x4000000	/* Large Image Length, set to 64 Meg */
+#define CONFIG_SYS_BOOTM_LEN		0x4000000	/* Large Image Length, set to 64 Meg */
 
 /*
  * I2C settings
- * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
  */
-/* #define CONFIG_SOFT_I2C	1*/	/* I2C bit-banged */
-#define CONFIG_HARD_I2C		1	/* I2C TWI */
-#if defined CONFIG_HARD_I2C
-#define CONFIG_TWICLK_KHZ	50
-#endif
+#define CONFIG_HARD_I2C		1
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_SYS_I2C_SPEED	50000
+#define CONFIG_SYS_I2C_SLAVE	0
 
 #define CONFIG_EBIU_SDRRC_VAL  0x306
 #define CONFIG_EBIU_SDGCTL_VAL 0x91114d
@@ -322,39 +319,6 @@
 #define CONFIG_EBIU_AMBCTL0_VAL		0x7BB07BB0
 #define CONFIG_EBIU_AMBCTL1_VAL		0xFFC27BB0
 
-#if defined CONFIG_SOFT_I2C
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PF_SCL			PF0
-#define PF_SDA			PF1
-
-#define I2C_INIT		(*pFIO_DIR |=  PF_SCL); asm("ssync;")
-#define I2C_ACTIVE		(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
-#define I2C_TRISTATE		(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
-#define I2C_READ		((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
-#define I2C_SDA(bit)		if(bit) { \
-					*pFIO_FLAG_S = PF_SDA; \
-					asm("ssync;"); \
-					} \
-				else    { \
-					*pFIO_FLAG_C = PF_SDA; \
-					asm("ssync;"); \
-					}
-#define I2C_SCL(bit)		if(bit) { \
-					*pFIO_FLAG_S = PF_SCL; \
-					asm("ssync;"); \
-					} \
-				else    { \
-					*pFIO_FLAG_C = PF_SCL; \
-					asm("ssync;"); \
-					}
-#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
-#endif
-
-#define CFG_I2C_SPEED		50000
-#define CFG_I2C_SLAVE		0xFE
-
 /* 0xFF, 0x7BB07BB0, 0x22547BB0 */
 /* #define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
 #define AMBCTL0VAL		(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
@@ -377,8 +341,8 @@
 #undef  CONFIG_IDE_LED		/* no led for ide supported */
 #undef  CONFIG_IDE_RESET	/* no reset for ide supported */
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE busses */
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1)	/* max. 1 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE busses */
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1)	/* max. 1 drives per IDE bus */
 
 #undef  AMBCTL1VAL
 #define AMBCTL1VAL		0xFFC3FFC3
@@ -391,30 +355,30 @@
  * Note that these settings aren't for the most part used in include/ata.h
  * when all of the ATA registers are setup
  */
-#define CFG_ATA_BASE_ADDR	0x2031C000
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#define CFG_ATA_DATA_OFFSET	0x0020	/* Offset for data I/O */
-#define CFG_ATA_REG_OFFSET	0x0020	/* Offset for normal register accesses */
-#define CFG_ATA_ALT_OFFSET	0x001C	/* Offset for alternate registers */
-#define CFG_ATA_STRIDE		2	/* CF.A0 --> Blackfin.Ax */
+#define CONFIG_SYS_ATA_BASE_ADDR	0x2031C000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* Offset for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x001C	/* Offset for alternate registers */
+#define CONFIG_SYS_ATA_STRIDE		2	/* CF.A0 --> Blackfin.Ax */
 #endif				/* CONFIG_BFIN_TRUE_IDE */
 
 #if defined(CONFIG_BFIN_CF_IDE)	/* USE CompactFlash Storage Card in the common memory space */
-#define CFG_ATA_BASE_ADDR	0x20211800
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
-#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses */
-#define CFG_ATA_ALT_OFFSET	0x000E	/* Offset for alternate registers */
-#define CFG_ATA_STRIDE		1	/* CF.A0 --> Blackfin.Ax */
+#define CONFIG_SYS_ATA_BASE_ADDR	0x20211800
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x000E	/* Offset for alternate registers */
+#define CONFIG_SYS_ATA_STRIDE		1	/* CF.A0 --> Blackfin.Ax */
 #endif				/* CONFIG_BFIN_CF_IDE */
 
 #if defined(CONFIG_BFIN_HDD_IDE)	/* USE TRUE IDE */
-#define CFG_ATA_BASE_ADDR	0x20314000
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#define CFG_ATA_DATA_OFFSET	0x0020	/* Offset for data I/O */
-#define CFG_ATA_REG_OFFSET	0x0020	/* Offset for normal register accesses */
-#define CFG_ATA_ALT_OFFSET	0x001C	/* Offset for alternate registers */
-#define CFG_ATA_STRIDE		2	/* CF.A0 --> Blackfin.A1 */
+#define CONFIG_SYS_ATA_BASE_ADDR	0x20314000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* Offset for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x001C	/* Offset for alternate registers */
+#define CONFIG_SYS_ATA_STRIDE		2	/* CF.A0 --> Blackfin.A1 */
 
 #undef  CONFIG_SCLK_DIV
 #define CONFIG_SCLK_DIV		8
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 59a0f3f..320a8c6 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -7,7 +7,7 @@
 
 #include <asm/blackfin-config-pre.h>
 
-#define CFG_LONGHELP		1
+#define CONFIG_SYS_LONGHELP		1
 #define CONFIG_CMDLINE_EDITING	1
 #define CONFIG_BAUDRATE		57600
 /* Set default serial console for bf537 */
@@ -76,20 +76,20 @@
  * Flash settings
  */
 
-#define CFG_FLASH_CFI		/* The flash is CFI compatible */
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible */
 #define CONFIG_FLASH_CFI_DRIVER	/* Use common CFI driver */
-#define CFG_FLASH_CFI_AMD_RESET
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
 #define	CONFIG_ENV_IS_IN_FLASH	1
-#define CFG_FLASH_BASE		0x20000000
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	135	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	135	/* max number of sectors on one chip */
 #define CONFIG_ENV_ADDR		0x20020000
 #define	CONFIG_ENV_SECT_SIZE	0x10000	/* Total Size of Environment Sector */
 /* JFFS Partition offset set  */
-#define CFG_JFFS2_FIRST_BANK	0
-#define CFG_JFFS2_NUM_BANKS	1
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
 /* 512k reserved for u-boot */
-#define CFG_JFFS2_FIRST_SECTOR	8
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR	8
 
 /*
  * SDRAM settings & memory map
@@ -99,23 +99,23 @@
 #define CONFIG_MEM_ADD_WDTH		9	/* 8, 9, 10, 11    */
 #define CONFIG_MEM_MT48LC16M16A2TG_75	1
 
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024 * 1024)
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024 * 1024)
 
-#define CFG_MEMTEST_START	0x0	/* memtest works on */
-#define CFG_MEMTEST_END		( (CONFIG_MEM_SIZE - 1) * 1024*1024)	/* 1 ... 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	0x0	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		( (CONFIG_MEM_SIZE - 1) * 1024*1024)	/* 1 ... 63 MB in DRAM */
 
 #define	CONFIG_LOADADDR		0x01000000	/* default load address */
-#define CFG_LOAD_ADDR		CONFIG_LOADADDR
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
-#define CFG_MONITOR_BASE	(CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
 
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
 
-#define CFG_GBL_DATA_SIZE	0x4000
-#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)
+#define CONFIG_SYS_GBL_DATA_SIZE	0x4000
+#define CONFIG_SYS_GBL_DATA_ADDR	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE	(CONFIG_SYS_GBL_DATA_ADDR  - 4)
 #define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
 
 #if ( CONFIG_CLKIN_HALF == 0 )
@@ -136,7 +136,7 @@
  * Command settings
  */
 
-#define CFG_AUTOLOAD	"no"	/* rarpb, bootp, dhcp commands will	*/
+#define CONFIG_SYS_AUTOLOAD	"no"	/* rarpb, bootp, dhcp commands will	*/
 				/* only perform a configuration		*/
 				/* lookup from the BOOTP/DHCP server	*/
 				/* but not try to load any image	*/
@@ -194,26 +194,26 @@
 /*
  * Console settings
  */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define	CFG_PROMPT		"bfin> "	/* Monitor Command Prompt */
+#define	CONFIG_SYS_PROMPT		"bfin> "	/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size */
+#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size */
 #else
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
 #endif
-#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
 #define CONFIG_LOADS_ECHO	1
 
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_HZ			1000		/* decrementer freq: 10 ms ticks */
-#define CFG_BOOTM_LEN		0x4000000	/* Large Image Length, set to 64 Meg */
+#define	CONFIG_SYS_HZ			1000		/* decrementer freq: 10 ms ticks */
+#define CONFIG_SYS_BOOTM_LEN		0x4000000	/* Large Image Length, set to 64 Meg */
 
 /*
  * FLASH organization and environment definitions
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
index 49abcc6..dcf5b6d 100644
--- a/include/configs/bubinga.h
+++ b/include/configs/bubinga.h
@@ -115,31 +115,31 @@
 #define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
 
 /*
- * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
  * The Linux BASE_BAUD define should match this configuration.
  *    baseBaud = cpuClock/(uartDivisor*16)
- * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  * set Linux BASE_BAUD to 403200.
  */
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#undef  CFG_EXT_SERIAL_CLOCK           /* external serial clock */
-#undef  CFG_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD       691200
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
+#undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD       691200
 
 /*-----------------------------------------------------------------------
  * I2C stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 
-#define CFG_I2C_NOPROBES	{ 0x69 }	/* avoid iprobe hangup (why?) */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */
+#define CONFIG_SYS_I2C_NOPROBES	{ 0x69 }	/* avoid iprobe hangup (why?) */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */
 
 #if defined(CONFIG_CMD_EEPROM)
-#define CFG_I2C_EEPROM_ADDR	0x50	/* I2C boot EEPROM (24C02W)	*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* I2C boot EEPROM (24C02W)	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -156,47 +156,47 @@
 					/* resource configuration       */
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
-#define CFG_PCI_CLASSCODE       0x0600  /* PCI Class Code: bridge/host  */
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
-#define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0600  /* PCI Class Code: bridge/host  */
+#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0x00000000      /* disabled                     */
+#define CONFIG_SYS_PCI_PTM2MS  0x00000000      /* disabled                     */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * External peripheral base address
  *-----------------------------------------------------------------------
  */
-#define	CFG_KEY_REG_BASE_ADDR	0xF0100000
-#define	CFG_IR_REG_BASE_ADDR	0xF0200000
-#define	CFG_FPGA_REG_BASE_ADDR	0xF0300000
+#define	CONFIG_SYS_KEY_REG_BASE_ADDR	0xF0100000
+#define	CONFIG_SYS_IR_REG_BASE_ADDR	0xF0200000
+#define	CONFIG_SYS_FPGA_REG_BASE_ADDR	0xF0300000
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  */
-#define CFG_SRAM_BASE		0xFFF00000
-#define CFG_FLASH_BASE		0xFFF80000
+#define CONFIG_SYS_SRAM_BASE		0xFFF00000
+#define CONFIG_SYS_FLASH_BASE		0xFFF80000
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_ADDR0         0x5555
-#define CFG_FLASH_ADDR1         0x2aaa
-#define CFG_FLASH_WORD_SIZE     unsigned char
+#define CONFIG_SYS_FLASH_ADDR0         0x5555
+#define CONFIG_SYS_FLASH_ADDR1         0x2aaa
+#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -207,13 +207,13 @@
 /*-----------------------------------------------------------------------
  * NVRAM organization
  */
-#define CFG_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
 
 #ifdef CONFIG_ENV_IS_IN_NVRAM
 #define CONFIG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
 #define CONFIG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
 #endif
 
 /*
@@ -222,48 +222,48 @@
  * BR0/1 and OR0/1 (FLASH)
  */
 
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	*/
 #define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
+#define CONFIG_SYS_TEMP_STACK_OCM        1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
 
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  */
 
 /* Memory Bank 0 (Flash/SRAM) initialization                                    */
-#define CFG_EBC_PB0AP           0x04006000
-#define CFG_EBC_PB0CR           0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit  */
+#define CONFIG_SYS_EBC_PB0AP           0x04006000
+#define CONFIG_SYS_EBC_PB0CR           0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit  */
 
 /* Memory Bank 1 (NVRAM/RTC) initialization                                     */
-#define CFG_EBC_PB1AP           0x04041000
-#define CFG_EBC_PB1CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+#define CONFIG_SYS_EBC_PB1AP           0x04041000
+#define CONFIG_SYS_EBC_PB1CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 
 /* Memory Bank 2 (not used) initialization                                      */
-#define CFG_EBC_PB2AP           0x00000000
-#define CFG_EBC_PB2CR           0x00000000
+#define CONFIG_SYS_EBC_PB2AP           0x00000000
+#define CONFIG_SYS_EBC_PB2CR           0x00000000
 
 /* Memory Bank 2 (not used) initialization                                      */
-#define CFG_EBC_PB3AP           0x00000000
-#define CFG_EBC_PB3CR           0x00000000
+#define CONFIG_SYS_EBC_PB3AP           0x00000000
+#define CONFIG_SYS_EBC_PB3CR           0x00000000
 
 /* Memory Bank 4 (FPGA regs) initialization                                     */
-#define CFG_EBC_PB4AP           0x01815000
-#define CFG_EBC_PB4CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
+#define CONFIG_SYS_EBC_PB4AP           0x01815000
+#define CONFIG_SYS_EBC_PB4CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
 
 /*-----------------------------------------------------------------------
  * Definitions for Serial Presence Detect EEPROM address
@@ -283,13 +283,13 @@
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  */
-#define CFG_GPIO0_OSRH          0x55555555
-#define CFG_GPIO0_OSRL          0x40000110
-#define CFG_GPIO0_ISR1H         0x00000000
-#define CFG_GPIO0_ISR1L         0x15555445
-#define CFG_GPIO0_TSRH          0x00000000
-#define CFG_GPIO0_TSRL          0x00000000
-#define CFG_GPIO0_TCR           0xFFFF8014
+#define CONFIG_SYS_GPIO0_OSRH          0x55555555
+#define CONFIG_SYS_GPIO0_OSRL          0x40000110
+#define CONFIG_SYS_GPIO0_ISR1H         0x00000000
+#define CONFIG_SYS_GPIO0_ISR1L         0x15555445
+#define CONFIG_SYS_GPIO0_TSRH          0x00000000
+#define CONFIG_SYS_GPIO0_TSRL          0x00000000
+#define CONFIG_SYS_GPIO0_TCR           0xFFFF8014
 
 /*-----------------------------------------------------------------------
  * Some BUBINGA stuff...
diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h
index dca7b47..4508d75 100644
--- a/include/configs/c2mon.h
+++ b/include/configs/c2mon.h
@@ -60,7 +60,7 @@
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -101,31 +101,31 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -135,47 +135,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
 #if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
@@ -184,9 +184,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -196,10 +196,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -208,9 +208,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -218,20 +218,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -242,10 +242,10 @@
  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  */
 #ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_PLPRCR							\
+#define CONFIG_SYS_PLPRCR							\
 		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
 #else			/* up to 50 MHz we use a 1:1 clock */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 #endif	/* CONFIG_80MHz */
 
 /*-----------------------------------------------------------------------
@@ -256,12 +256,12 @@
  */
 #define SCCR_MASK	SCCR_EBDF11
 #ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_SCCR	(/* SCCR_TBS  | */ \
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS  | */ \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 #else			/* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -272,14 +272,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * PCMCIA Power Switch
@@ -312,21 +312,21 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 
 /*-----------------------------------------------------------------------
@@ -334,7 +334,7 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -349,20 +349,20 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
 				 OR_SCY_5_CLK | OR_EHTR)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -373,19 +373,19 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 #ifndef	CONFIG_CAN_DRIVER
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 #endif	/* CONFIG_CAN_DRIVER */
 
@@ -394,26 +394,26 @@
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
index 59e4cb3..1f275e5 100644
--- a/include/configs/canmb.h
+++ b/include/configs/canmb.h
@@ -33,7 +33,7 @@
 #define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
 #define CONFIG_CANMB		1	/* ... on canmb board - we need this for FEC.C */
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
@@ -47,7 +47,7 @@
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 
 /*
@@ -78,8 +78,8 @@
  * MUST be low boot - HIGHBOOT is not supported anymore
  */
 #if (TEXT_BASE == 0xFE000000)		/* Boot low with 32 MB Flash */
-#   define CFG_LOWBOOT		1
-#   define CFG_LOWBOOT16	1
+#   define CONFIG_SYS_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT16	1
 #else
 #   error "TEXT_BASE must be 0xFE000000"
 #endif
@@ -117,22 +117,22 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * Flash configuration, expect one 16 Megabyte Bank at most
  */
-#define CFG_FLASH_BASE		0xFE000000
-#define CFG_FLASH_SIZE		0x02000000
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_SIZE		0x02000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 /*
  * Environment settings
@@ -147,32 +147,33 @@
  *
  * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
  */
-#define CFG_MBAR			0xf0000000	/* DO NOT CHANGE this */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR			0xf0000000	/* DO NOT CHANGE this */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
 #define	CONFIG_PHY_ADDR		0x0
 /*
  * GPIO configuration:
@@ -180,51 +181,51 @@
  * PCI disabled
  * Ethernet 100 with MD
  */
-#define CFG_GPS_PORT_CONFIG	0x00058444
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x00058444
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#  define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#  define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x200000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*
  * Various low-level settings
  */
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x00047D01
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047D01
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
 
-#define CFG_RESET_ADDRESS	0x7f000000
+#define CONFIG_SYS_RESET_ADDRESS	0x7f000000
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index 2f162e1..d814012 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -27,14 +27,24 @@
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
-/* This config file is used for Canyonlands (460EX) and Glacier (460GT)	*/
-#ifndef CONFIG_CANYONLANDS
+/*
+ * This config file is used for Canyonlands (460EX) Glacier (460GT)
+ * and Arches dual (460GT)
+ */
+#ifdef CONFIG_CANYONLANDS
+#define CONFIG_460EX		1	/* Specific PPC460EX		*/
+#define CONFIG_HOSTNAME		canyonlands
+#else
 #define CONFIG_460GT		1	/* Specific PPC460GT		*/
+#ifdef CONFIG_GLACIER
 #define CONFIG_HOSTNAME		glacier
 #else
-#define CONFIG_460EX		1	/* Specific PPC460EX		*/
-#define CONFIG_HOSTNAME		canyonlands
+#define CONFIG_HOSTNAME		arches
+#define CONFIG_USE_NETDEV	eth1
+#define CONFIG_BD_NUM_CPUS	2
 #endif
+#endif
+
 #define CONFIG_440		1
 #define CONFIG_4xx		1	/* ... PPC4xx family */
 
@@ -54,51 +64,60 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
-#define CFG_PCI_BASE		0xd0000000	/* internal PCI regs	*/
-#define CFG_PCI_TARGBASE	CFG_PCI_MEMBASE
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
+#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs	*/
+#define CONFIG_SYS_PCI_TARGBASE	CONFIG_SYS_PCI_MEMBASE
 
-#define CFG_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
-#define CFG_PCIE_MEMSIZE	0x08000000	/* smallest incr for PCIe port */
-#define CFG_PCIE_BASE		0xc4000000	/* PCIe UTL regs */
+#define CONFIG_SYS_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
+#define CONFIG_SYS_PCIE_MEMSIZE	0x08000000	/* smallest incr for PCIe port */
+#define CONFIG_SYS_PCIE_BASE		0xc4000000	/* PCIe UTL regs */
 
-#define CFG_PCIE0_CFGBASE	0xc0000000
-#define CFG_PCIE1_CFGBASE	0xc1000000
-#define CFG_PCIE0_XCFGBASE	0xc3000000
-#define CFG_PCIE1_XCFGBASE	0xc3001000
+#define CONFIG_SYS_PCIE0_CFGBASE	0xc0000000
+#define CONFIG_SYS_PCIE1_CFGBASE	0xc1000000
+#define CONFIG_SYS_PCIE0_XCFGBASE	0xc3000000
+#define CONFIG_SYS_PCIE1_XCFGBASE	0xc3001000
 
-#define	CFG_PCIE0_UTLBASE	0xc08010000ULL	/* 36bit physical addr	*/
+#define	CONFIG_SYS_PCIE0_UTLBASE	0xc08010000ULL	/* 36bit physical addr	*/
 
 /* base address of inbound PCIe window */
-#define CFG_PCIE_INBOUND_BASE	0x000000000ULL	/* 36bit physical addr	*/
+#define CONFIG_SYS_PCIE_INBOUND_BASE	0x000000000ULL	/* 36bit physical addr	*/
 
 /* EBC stuff */
-#define CFG_NAND_ADDR		0xE0000000
-#define CFG_BCSR_BASE		0xE1000000
-#define CFG_BOOT_BASE_ADDR	0xFF000000	/* EBC Boot Space: 0xFF000000	*/
-#define CFG_FLASH_BASE		0xFC000000	/* later mapped to this addr	*/
-#define CFG_FLASH_BASE_PHYS_H	0x4
-#define CFG_FLASH_BASE_PHYS_L	0xCC000000
-#define CFG_FLASH_BASE_PHYS	(((u64)CFG_FLASH_BASE_PHYS_H << 32) | \
-				 (u64)CFG_FLASH_BASE_PHYS_L)
-#define CFG_FLASH_SIZE		(64 << 20)
+#if !defined(CONFIG_ARCHES)
+#define CONFIG_SYS_BCSR_BASE		0xE1000000
+#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* later mapped to this addr */
+#define CONFIG_SYS_FLASH_SIZE		(64 << 20)
+#else
+#define CONFIG_SYS_FPGA_BASE		0xE1000000
+#define CONFIG_SYS_CPLD_ADDR		(CONFIG_SYS_FPGA_BASE + 0x00080000)
+#define CONFIG_SYS_CPLD_DATA		(CONFIG_SYS_FPGA_BASE + 0x00080002)
+#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* later mapped to this addr  */
+#define CONFIG_SYS_FLASH_SIZE		(32 << 20)
+#endif
 
-#define CFG_OCM_BASE		0xE3000000	/* OCM: 16k		*/
-#define CFG_SRAM_BASE		0xE8000000	/* SRAM: 256k		*/
-#define CFG_LOCAL_CONF_REGS	0xEF000000
+#define CONFIG_SYS_NAND_ADDR		0xE0000000
+#define CONFIG_SYS_BOOT_BASE_ADDR	0xFF000000	/* EBC Boot Space: 0xFF000000 */
+#define CONFIG_SYS_FLASH_BASE_PHYS_H	0x4
+#define CONFIG_SYS_FLASH_BASE_PHYS_L	0xCC000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) |	\
+					 (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
 
-#define CFG_PERIPHERAL_BASE	0xEF600000	/* internal peripherals */
+#define CONFIG_SYS_OCM_BASE		0xE3000000	/* OCM: 64k		*/
+#define CONFIG_SYS_SRAM_BASE		0xE8000000	/* SRAM: 256k		*/
+#define CONFIG_SYS_LOCAL_CONF_REGS	0xEF000000
 
-#define CFG_AHB_BASE		0xE2000000	/* internal AHB peripherals	*/
+#define CONFIG_SYS_PERIPHERAL_BASE	0xEF600000	/* internal peripherals */
+
+#define CONFIG_SYS_AHB_BASE		0xE2000000	/* internal AHB peripherals	*/
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in OCM)
  *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM			*/
-#define CFG_INIT_RAM_END	(4 << 10)
-#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
+#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Serial Port
@@ -113,10 +132,10 @@
  */
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define	CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
-#define CFG_NAND_CS		3	/* NAND chip connected to CSx */
+#define CONFIG_SYS_NAND_CS		3	/* NAND chip connected to CSx */
 #else
 #define	CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars  */
-#define CFG_NAND_CS		0	/* NAND chip connected to CSx */
+#define CONFIG_SYS_NAND_CS		0	/* NAND chip connected to CSx */
 #define CONFIG_ENV_IS_EMBEDDED	1	/* use embedded environment */
 #endif
 
@@ -141,36 +160,36 @@
  * This is the first official implementation of booting from 2k page sized
  * NAND devices (e.g. Micron 29F2G08AA 256Mbit * 8)
  */
-#define CFG_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location		      */
-#define CFG_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size		      */
-#define CFG_NAND_BOOT_SPL_DST	(CFG_OCM_BASE + (12 << 10)) /* Copy SPL here  */
-#define CFG_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr      */
-#define CFG_NAND_U_BOOT_START	CFG_NAND_U_BOOT_DST	/* Start NUB from     */
+#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location		      */
+#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size		      */
+#define CONFIG_SYS_NAND_BOOT_SPL_DST	(CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here  */
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr      */
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST	/* Start NUB from     */
 							/*   this addr	      */
-#define CFG_NAND_BOOT_SPL_DELTA	(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
+#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 
 /*
  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
  */
-#define CFG_NAND_U_BOOT_OFFS	(128 << 10)	/* Offset to RAM U-Boot image */
-#define CFG_NAND_U_BOOT_SIZE	(1 << 20)	/* Size of RAM U-Boot image   */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)	/* Offset to RAM U-Boot image */
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(1 << 20)	/* Size of RAM U-Boot image   */
 
 /*
  * Now the NAND chip has to be defined (no autodetection used!)
  */
-#define CFG_NAND_PAGE_SIZE	(2 << 10)	/* NAND chip page size	      */
-#define CFG_NAND_BLOCK_SIZE	(128 << 10)	/* NAND chip block size	      */
-#define CFG_NAND_PAGE_COUNT	(CFG_NAND_BLOCK_SIZE / CFG_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)	/* NAND chip page size	      */
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)	/* NAND chip block size	      */
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)
 						/* NAND chip page count	      */
-#define CFG_NAND_BAD_BLOCK_POS	0		/* Location of bad block marker*/
-#define CFG_NAND_5_ADDR_CYCLE			/* Fifth addr used (<=128MB)  */
-
-#define CFG_NAND_ECCSIZE	256
-#define CFG_NAND_ECCBYTES	3
-#define CFG_NAND_ECCSTEPS	(CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
-#define CFG_NAND_OOBSIZE	64
-#define CFG_NAND_ECCTOTAL	(CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
-#define CFG_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47, \
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0		/* Location of bad block marker*/
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE			/* Fifth addr used (<=128MB)  */
+
+#define CONFIG_SYS_NAND_ECCSIZE	256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_OOBSIZE	64
+#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
+#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47, \
 				 48, 49, 50, 51, 52, 53, 54, 55, \
 				 56, 57, 58, 59, 60, 61, 62, 63}
 
@@ -179,31 +198,31 @@
  * For NAND booting the environment is embedded in the U-Boot image. Please take
  * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
  */
-#define CONFIG_ENV_SIZE		CFG_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(CFG_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 #endif
 
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI			/* The flash is CFI compatible	*/
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
-#define CFG_FLASH_CFI_AMD_RESET	1	/* Use AMD (Spansion) reset cmd */
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1	/* Use AMD (Spansion) reset cmd */
 
-#define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000		/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -214,15 +233,15 @@
 /*-----------------------------------------------------------------------
  * NAND-FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_MAX_NAND_DEVICE	1
-#define NAND_MAX_CHIPS		1
-#define CFG_NAND_BASE		(CFG_NAND_ADDR + CFG_NAND_CS)
-#define CFG_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
+#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
 
 /*------------------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------------*/
 #if !defined(CONFIG_NAND_U_BOOT)
+#if !defined(CONFIG_ARCHES)
 /*
  * NAND booting U-Boot version uses a fixed initialization, since the whole
  * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
@@ -232,41 +251,112 @@
 #define SPD_EEPROM_ADDRESS	{0x50, 0x51}	/* SPD i2c spd addresses*/
 #define CONFIG_DDR_ECC		1	/* with ECC support		*/
 #define CONFIG_DDR_RQDC_FIXED	0x80000038 /* fixed value for RQDC	*/
-#endif
-#define CFG_MBYTES_SDRAM	512	/* 512MB			*/
+
+#else /* defined(CONFIG_ARCHES) */
+
+#define CONFIG_AUTOCALIB	"silent\0"	/* default is non-verbose    */
+
+#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION	/* IBM DDR autocalibration   */
+#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION	/* dynamic DDR autocal debug */
+#undef CONFIG_PPC4xx_DDR_METHOD_A
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+/* Memory Queue */
+#define CONFIG_SYS_SDRAM_R0BAS		0x0000f000
+#define CONFIG_SYS_SDRAM_R1BAS		0x00000000
+#define CONFIG_SYS_SDRAM_R2BAS		0x00000000
+#define CONFIG_SYS_SDRAM_R3BAS		0x00000000
+#define CONFIG_SYS_SDRAM_PLBADDULL	0x00000000
+#define CONFIG_SYS_SDRAM_PLBADDUHB	0x00000008
+#define CONFIG_SYS_SDRAM_CONF1LL	0x00001080
+#define CONFIG_SYS_SDRAM_CONF1HB	0x00001080
+#define CONFIG_SYS_SDRAM_CONFPATHB	0x10a68000
+
+/* SDRAM Controller */
+#define CONFIG_SYS_SDRAM0_MB0CF		0x00000701
+#define CONFIG_SYS_SDRAM0_MB1CF		0x00000000
+#define CONFIG_SYS_SDRAM0_MB2CF		0x00000000
+#define CONFIG_SYS_SDRAM0_MB3CF		0x00000000
+#define CONFIG_SYS_SDRAM0_MCOPT1	0x05322000
+#define CONFIG_SYS_SDRAM0_MCOPT2	0x00000000
+#define CONFIG_SYS_SDRAM0_MODT0		0x01000000
+#define CONFIG_SYS_SDRAM0_MODT1		0x00000000
+#define CONFIG_SYS_SDRAM0_MODT2		0x00000000
+#define CONFIG_SYS_SDRAM0_MODT3		0x00000000
+#define CONFIG_SYS_SDRAM0_CODT		0x00800021
+#define CONFIG_SYS_SDRAM0_RTR		0x06180000
+#define CONFIG_SYS_SDRAM0_INITPLR0	0xb5380000
+#define CONFIG_SYS_SDRAM0_INITPLR1	0x82100400
+#define CONFIG_SYS_SDRAM0_INITPLR2	0x80820000
+#define CONFIG_SYS_SDRAM0_INITPLR3	0x80830000
+#define CONFIG_SYS_SDRAM0_INITPLR4	0x80810040
+#define CONFIG_SYS_SDRAM0_INITPLR5	0x80800532
+#define CONFIG_SYS_SDRAM0_INITPLR6	0x82100400
+#define CONFIG_SYS_SDRAM0_INITPLR7	0x8a080000
+#define CONFIG_SYS_SDRAM0_INITPLR8	0x8a080000
+#define CONFIG_SYS_SDRAM0_INITPLR9	0x8a080000
+#define CONFIG_SYS_SDRAM0_INITPLR10	0x8a080000
+#define CONFIG_SYS_SDRAM0_INITPLR11	0x80000432
+#define CONFIG_SYS_SDRAM0_INITPLR12	0x808103c0
+#define CONFIG_SYS_SDRAM0_INITPLR13	0x80810040
+#define CONFIG_SYS_SDRAM0_INITPLR14	0x00000000
+#define CONFIG_SYS_SDRAM0_INITPLR15	0x00000000
+#define CONFIG_SYS_SDRAM0_RQDC		0x80000038
+#define CONFIG_SYS_SDRAM0_RFDC		0x00000257
+#define CONFIG_SYS_SDRAM0_RDCC		0x40000000
+#define CONFIG_SYS_SDRAM0_DLCR		0x03000091
+#define CONFIG_SYS_SDRAM0_CLKTR		0x40000000
+#define CONFIG_SYS_SDRAM0_WRDTR		0x82000823
+#define CONFIG_SYS_SDRAM0_SDTR1		0x80201000
+#define CONFIG_SYS_SDRAM0_SDTR2		0x42204243
+#define CONFIG_SYS_SDRAM0_SDTR3		0x090c0d1a
+#define CONFIG_SYS_SDRAM0_MMODE		0x00000432
+#define CONFIG_SYS_SDRAM0_MEMODE	0x00000004
+#endif	/* !defined(CONFIG_ARCHES) */
+#endif	/* !defined(CONFIG_NAND_U_BOOT) */
+
+#define CONFIG_SYS_MBYTES_SDRAM	512	/* 512MB			*/
 
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CFG_I2C_SPEED		400000	/* I2C speed			*/
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed			*/
 
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR		(0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR		(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 
 /* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
 #define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
 #define CONFIG_DTT_AD7414	1		/* use AD7414		*/
 #define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
-#define CFG_DTT_MAX_TEMP	70
-#define CFG_DTT_LOW_TEMP	-30
-#define CFG_DTT_HYSTERESIS	3
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
+
+#if defined(CONFIG_ARCHES)
+#define CONFIG_SYS_I2C_DTT_ADDR	0x4a		/* AD7414 I2C address	*/
+#endif
 
+#if !defined(CONFIG_ARCHES)
 /* RTC configuration */
 #define CONFIG_RTC_M41T62	1
-#define CFG_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#endif
 
 /*-----------------------------------------------------------------------
  * Ethernet
  *----------------------------------------------------------------------*/
 #define CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
-#define CONFIG_PHY1_ADDR	1
+
 #define CONFIG_HAS_ETH0
 #define CONFIG_HAS_ETH1
+
+#if !defined(CONFIG_ARCHES)
+#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
+#define CONFIG_PHY1_ADDR	1
 /* Only Glacier (460GT) has 4 EMAC interfaces */
 #ifdef CONFIG_460GT
 #define CONFIG_PHY2_ADDR	2
@@ -275,6 +365,30 @@
 #define CONFIG_HAS_ETH3
 #endif
 
+#else /* defined(CONFIG_ARCHES) */
+
+#define CONFIG_FIXED_PHY	0xFFFFFFFF
+#define CONFIG_PHY_ADDR		CONFIG_FIXED_PHY
+#define CONFIG_PHY1_ADDR	0
+#define CONFIG_PHY2_ADDR	1
+#define CONFIG_HAS_ETH2
+
+#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
+		{devnum, speed, duplex}
+#define CONFIG_SYS_FIXED_PHY_PORTS \
+		CONFIG_SYS_FIXED_PHY_PORT(0, 1000, FULL)
+
+#define CONFIG_M88E1112_PHY
+
+/*
+ * For the GPCS_PHYx_ADDR PHY address, choose some PHY address not
+ * used by CONFIG_PHYx_ADDR
+ */
+#define CONFIG_GPCS_PHY_ADDR    0xA
+#define CONFIG_GPCS_PHY1_ADDR   0xB
+#define CONFIG_GPCS_PHY2_ADDR   0xC
+#endif	/* !defined(CONFIG_ARCHES) */
+
 #define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 #define CONFIG_PHY_DYNAMIC_ANEG	1
@@ -286,18 +400,19 @@
 #ifdef CONFIG_460EX
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_STORAGE
-#undef CFG_OHCI_BE_CONTROLLER		/* 460EX has little endian descriptors	*/
-#define CFG_OHCI_SWAP_REG_ACCESS	/* 460EX has little endian register	*/
-#define CFG_OHCI_USE_NPS		/* force NoPowerSwitching mode		*/
-#define CFG_USB_OHCI_REGS_BASE	(CFG_AHB_BASE | 0xd0000)
-#define CFG_USB_OHCI_SLOT_NAME	"ppc440"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+#undef CONFIG_SYS_OHCI_BE_CONTROLLER		/* 460EX has little endian descriptors	*/
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	/* 460EX has little endian register	*/
+#define CONFIG_SYS_OHCI_USE_NPS		/* force NoPowerSwitching mode		*/
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	(CONFIG_SYS_AHB_BASE | 0xd0000)
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ppc440"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 #endif
 
 /*
  * Default environment variables
  */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
+#if !defined(CONFIG_ARCHES)
+#define CONFIG_EXTRA_ENV_SETTINGS					\
 	CONFIG_AMCC_DEF_ENV						\
 	CONFIG_AMCC_DEF_ENV_POWERPC					\
 	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
@@ -308,20 +423,46 @@
 	"pciconfighost=1\0"						\
 	"pcie_mode=RP:RP\0"						\
 	""
+#else /* defined(CONFIG_ARCHES) */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fe000000\0"					\
+	"fdt_addr=fe1e0000\0"						\
+	"ramdisk_addr=fe200000\0"					\
+	"pciconfighost=1\0"						\
+	"pcie_mode=RP:RP\0"						\
+	"ethprime=ppc_4xx_eth1\0"					\
+	""
+#endif	/* !defined(CONFIG_ARCHES) */
 
 /*
  * Commands additional to the ones defined in amcc-common.h
  */
+#if defined(CONFIG_ARCHES)
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+#elif defined(CONFIG_CANYONLANDS)
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DTT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SNTP
-#ifdef CONFIG_460EX
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_USB
+#elif defined(CONFIG_GLACIER)
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+#else
+#error "board type not defined"
 #endif
 
 /* Partitions */
@@ -339,11 +480,41 @@
 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT		/* let board init pci target    */
-#undef	CFG_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */
+#undef	CONFIG_SYS_PCI_MASTER_INIT
 
-#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
+
+#ifdef CONFIG_460GT
+#if defined(CONFIG_ARCHES)
+/*-----------------------------------------------------------------------
+ * RapidIO I/O and Registers
+ *----------------------------------------------------------------------*/
+#define CONFIG_RAPIDIO
+#define CONFIG_SYS_460GT_SRIO_ERRATA_1
+
+#define SRGPL0_REG_BAR		0x0000000DAA000000ull	/*  16MB */
+#define SRGPL0_CFG_BAR		0x0000000DAB000000ull	/*  16MB */
+#define SRGPL0_MNT_BAR		0x0000000DAC000000ull	/*  16MB */
+#define SRGPL0_MSG_BAR		0x0000000DAD000000ull	/*  16MB */
+#define SRGPL0_OUT_BAR		0x0000000DB0000000ull	/* 256MB */
+
+#define CONFIG_SYS_SRGPL0_REG_BAR	0xAA000000		/*  16MB */
+#define CONFIG_SYS_SRGPL0_CFG_BAR	0xAB000000		/*  16MB */
+#define CONFIG_SYS_SRGPL0_MNT_BAR	0xAC000000		/*  16MB */
+#define CONFIG_SYS_SRGPL0_MSG_BAR	0xAD000000		/*  16MB */
+
+#define CONFIG_SYS_I2ODMA_BASE		0xCF000000
+#define CONFIG_SYS_I2ODMA_PHYS_ADDR	0x0000000400100000ull
+
+#define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
+#undef CONFIG_PPC4XX_RAPIDIO_DEBUG
+#undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
+#define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
+#undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
+#endif /* CONFIG_ARCHES */
+#endif /* CONFIG_460GT */
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
@@ -357,38 +528,63 @@
  * EBC address which accepts bigger regions:
  *
  * 0xfc00.0000 -> 4.cc00.0000
+ *
+ * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), it will be
+ * remapped to:
+ *
+ * 0xfe00.0000 -> 4.ce00.0000
  */
 
 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 /* Memory Bank 3 (NOR-FLASH) initialization					*/
-#define CFG_EBC_PB3AP		0x10055e00
-#define CFG_EBC_PB3CR		(CFG_BOOT_BASE_ADDR | 0x9a000)
+#define CONFIG_SYS_EBC_PB3AP		0x10055e00
+#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
 
 /* Memory Bank 0 (NAND-FLASH) initialization						*/
-#define CFG_EBC_PB0AP		0x018003c0
-#define CFG_EBC_PB0CR		(CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
+#define CONFIG_SYS_EBC_PB0AP		0x018003c0
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
 #else
 /* Memory Bank 0 (NOR-FLASH) initialization					*/
-#define CFG_EBC_PB0AP		0x10055e00
-#define CFG_EBC_PB0CR		(CFG_BOOT_BASE_ADDR | 0x9a000)
+#define CONFIG_SYS_EBC_PB0AP		0x10055e00
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
 
+#if !defined(CONFIG_ARCHES)
 /* Memory Bank 3 (NAND-FLASH) initialization						*/
-#define CFG_EBC_PB3AP		0x018003c0
-#define CFG_EBC_PB3CR		(CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
+#define CONFIG_SYS_EBC_PB3AP		0x018003c0
+#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
 #endif
+#endif	/*defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
 
+#if !defined(CONFIG_ARCHES)
 /* Memory Bank 2 (CPLD) initialization						*/
-#define CFG_EBC_PB2AP		0x00804240
-#define CFG_EBC_PB2CR		(CFG_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
+#define CONFIG_SYS_EBC_PB2AP		0x00804240
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
 
-#define CFG_EBC_CFG		0xB8400000		/*  EBC0_CFG */
+#else /* defined(CONFIG_ARCHES) */
+
+/* Memory Bank 1 (FPGA) initialization  */
+#define CONFIG_SYS_EBC_PB1AP		0x7f8ffe80
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
+#endif	/* !defined(CONFIG_ARCHES) */
+
+#define CONFIG_SYS_EBC_CFG		0xB8400000		/*  EBC0_CFG */
+
+/*
+ * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
+ * pin multiplexing correctly
+ */
+#if defined(CONFIG_ARCHES)
+#define GPIO43_USE		GPIO_SEL	/* On Arches this pin is used as GPIO */
+#else
+#define GPIO43_USE		GPIO_ALT1	/* On Glacier this pin is used as ALT1 -> PerCS3 */
+#endif
 
 /*
  * PPC4xx GPIO Configuration
  */
 #ifdef CONFIG_460EX
 /* 460EX: Use USB configuration */
-#define CFG_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
 {											\
 /* GPIO Core 0 */									\
 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	GMC1TxD(0)	USB2HostD(0)	*/	\
@@ -462,7 +658,7 @@
 }
 #else
 /* 460GT: Use EMAC2+3 configuration */
-#define CFG_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
 {											\
 /* GPIO Core 0 */									\
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	GMC1TxD(0)	USB2HostD(0)	*/	\
@@ -511,7 +707,7 @@
 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)				*/	\
 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)				*/	\
 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)				*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)		DMAReq1		IRQ(10)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO43_USE, GPIO_OUT_0},/* GPIO43 CS(3)		DMAReq1		IRQ(10)*/ \
 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)		DMAAck1		IRQ(11)*/ \
 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)		EOT/TC1		IRQ(12)*/ \
 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)	DMAReq0		IRQ(13)*/ \
diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h
index 9618425..f19374e 100644
--- a/include/configs/cerf250.h
+++ b/include/configs/cerf250.h
@@ -44,8 +44,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -94,33 +94,33 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_HUSH_PARSER		1
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
-#define CFG_LONGHELP					/* undef to save memory		*/
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT			"uboot$ "	/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP					/* undef to save memory		*/
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT			"uboot$ "	/* Monitor Command Prompt */
 #else
-#define CFG_PROMPT			"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT			"=> "		/* Monitor Command Prompt */
 #endif
-#define CFG_CBSIZE			256			/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CONFIG_SYS_CBSIZE			256			/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 										/* Print Buffer Size */
-#define CFG_MAXARGS			16			/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_DEVICE_NULLDEV	1
+#define CONFIG_SYS_MAXARGS			16			/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1
 
-#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
 
-#undef	CFG_CLKS_IN_HZ
+#undef	CONFIG_SYS_CLKS_IN_HZ
 
-#define CFG_LOAD_ADDR		0xa2000000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0xa2000000	/* default load address */
 
-#define CFG_HZ				3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x141		/* set core clock to 400/200/100 MHz */
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CPUSPEED		0x141		/* set core clock to 400/200/100 MHz */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 
 /*
@@ -153,54 +153,54 @@
 #define PHYS_FLASH_BANK_SIZE		0x02000000	/* 32 MB Banks */
 #define PHYS_FLASH_SECT_SIZE		0x00040000	/* 256 KB sectors (x2) */
 
-#define CFG_DRAM_BASE			0xa0000000
-#define CFG_DRAM_SIZE			0x04000000
+#define CONFIG_SYS_DRAM_BASE			0xa0000000
+#define CONFIG_SYS_DRAM_SIZE			0x04000000
 
-#define CFG_FLASH_BASE			PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
 
 /*
  * GPIO settings
  */
 
 
-#define CFG_GPSR0_VAL		0x00408030
-#define CFG_GPSR1_VAL		0x00BFA882
-#define CFG_GPSR2_VAL		0x0001C000
-#define CFG_GPCR0_VAL		0xC0031100
-#define CFG_GPCR1_VAL		0xFC400300
-#define CFG_GPCR2_VAL		0x00003FFF
-#define CFG_GPDR0_VAL		0xC0439330
-#define CFG_GPDR1_VAL		0xFCFFAB82
-#define CFG_GPDR2_VAL		0x0001FFFF
-#define CFG_GAFR0_L_VAL		0x80000000
-#define CFG_GAFR0_U_VAL		0xA5000010
-#define CFG_GAFR1_L_VAL		0x60008018
-#define CFG_GAFR1_U_VAL		0xAAA5AAAA
-#define CFG_GAFR2_L_VAL		0xAAA0000A
-#define CFG_GAFR2_U_VAL		0x00000002
-
-#define CFG_PSSR_VAL		0x20
+#define CONFIG_SYS_GPSR0_VAL		0x00408030
+#define CONFIG_SYS_GPSR1_VAL		0x00BFA882
+#define CONFIG_SYS_GPSR2_VAL		0x0001C000
+#define CONFIG_SYS_GPCR0_VAL		0xC0031100
+#define CONFIG_SYS_GPCR1_VAL		0xFC400300
+#define CONFIG_SYS_GPCR2_VAL		0x00003FFF
+#define CONFIG_SYS_GPDR0_VAL		0xC0439330
+#define CONFIG_SYS_GPDR1_VAL		0xFCFFAB82
+#define CONFIG_SYS_GPDR2_VAL		0x0001FFFF
+#define CONFIG_SYS_GAFR0_L_VAL		0x80000000
+#define CONFIG_SYS_GAFR0_U_VAL		0xA5000010
+#define CONFIG_SYS_GAFR1_L_VAL		0x60008018
+#define CONFIG_SYS_GAFR1_U_VAL		0xAAA5AAAA
+#define CONFIG_SYS_GAFR2_L_VAL		0xAAA0000A
+#define CONFIG_SYS_GAFR2_U_VAL		0x00000002
+
+#define CONFIG_SYS_PSSR_VAL		0x20
 
 /*
  * Memory settings
  */
-#define CFG_MSC0_VAL		0x12447FF0
-#define CFG_MSC1_VAL		0x12BC5554
-#define CFG_MSC2_VAL		0x7FF97FF1
-#define CFG_MDCNFG_VAL		0x00001AC9
-#define CFG_MDREFR_VAL		0x03CDC017
-#define CFG_MDMRS_VAL		0x00000000
+#define CONFIG_SYS_MSC0_VAL		0x12447FF0
+#define CONFIG_SYS_MSC1_VAL		0x12BC5554
+#define CONFIG_SYS_MSC2_VAL		0x7FF97FF1
+#define CONFIG_SYS_MDCNFG_VAL		0x00001AC9
+#define CONFIG_SYS_MDREFR_VAL		0x03CDC017
+#define CONFIG_SYS_MDMRS_VAL		0x00000000
 
 /*
  * PCMCIA and CF Interfaces
  */
-#define CFG_MECR_VAL		0x00000000
-#define CFG_MCMEM0_VAL		0x00010504
-#define CFG_MCMEM1_VAL		0x00010504
-#define CFG_MCATT0_VAL		0x00010504
-#define CFG_MCATT1_VAL		0x00010504
-#define CFG_MCIO0_VAL		0x00004715
-#define CFG_MCIO1_VAL		0x00004715
+#define CONFIG_SYS_MECR_VAL		0x00000000
+#define CONFIG_SYS_MCMEM0_VAL		0x00010504
+#define CONFIG_SYS_MCMEM1_VAL		0x00010504
+#define CONFIG_SYS_MCATT0_VAL		0x00010504
+#define CONFIG_SYS_MCATT1_VAL		0x00010504
+#define CONFIG_SYS_MCIO0_VAL		0x00004715
+#define CONFIG_SYS_MCIO1_VAL		0x00004715
 
 #define _LED			0x08000010	/*check this */
 #define LED_BLANK		0x08000040
@@ -209,16 +209,16 @@
 /*
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip    */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip    */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
-#define CFG_MONITOR_LEN		0x40000		/* 256 KiB */
+#define CONFIG_SYS_MONITOR_LEN		0x40000		/* 256 KiB */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/
 
 
diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h
index c9c057c..ce36a24 100644
--- a/include/configs/cm4008.h
+++ b/include/configs/cm4008.h
@@ -42,8 +42,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -56,7 +56,7 @@
 #define	CONFIG_SERIAL1
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 
 /*
@@ -73,7 +73,7 @@
  */
 #include <config_cmd_default.h>
 
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
 
 
 #define CONFIG_BOOTDELAY	0
@@ -83,21 +83,21 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"boot > "	/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"boot > "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00800000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x01000000	/* 16 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00800000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x01000000	/* 16 MB in DRAM	*/
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR		0x00008000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x00008000	/* default load address */
 
-#define CFG_HZ			(1000)		/* 1ms resolution ticks */
+#define CONFIG_SYS_HZ			(1000)		/* 1ms resolution ticks */
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -119,17 +119,17 @@
 
 #define PHYS_FLASH_1		0x02000000 /* Flash Bank #1 */
 #define PHYS_FLASH_SECT_SIZE    0x00020000 /* 128 KB sectors (x1) */
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of flash banks */
-#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define CONFIG_ENV_SIZE		0x20000     /* Total Size of Environment */
 
diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h
index 940e3e1..02cb1ef 100644
--- a/include/configs/cm41xx.h
+++ b/include/configs/cm41xx.h
@@ -42,8 +42,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -56,7 +56,7 @@
 #define	CONFIG_SERIAL1
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 
 /*
@@ -73,7 +73,7 @@
  */
 #include <config_cmd_default.h>
 
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
 
 
 #define CONFIG_BOOTDELAY	0
@@ -83,21 +83,21 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"boot > "	/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"boot > "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00800000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x01000000	/* 16 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00800000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x01000000	/* 16 MB in DRAM	*/
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR		0x00008000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x00008000	/* default load address */
 
-#define CFG_HZ			(1000)		/* 1ms resolution ticks */
+#define CONFIG_SYS_HZ			(1000)		/* 1ms resolution ticks */
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -119,17 +119,17 @@
 
 #define PHYS_FLASH_1		0x02000000 /* Flash Bank #1 */
 #define PHYS_FLASH_SECT_SIZE    0x00020000 /* 128 KB sectors (x1) */
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of flash banks */
-#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define CONFIG_ENV_SIZE		0x20000     /* Total Size of Environment */
 
diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h
index 5257db3..ddcc6aa 100644
--- a/include/configs/cm5200.h
+++ b/include/configs/cm5200.h
@@ -58,26 +58,27 @@
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
 #define CONFIG_BAUDRATE		57600	/* ... at 57600 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 #define CONFIG_SILENT_CONSOLE	1	/* needed to silence i2c_init() */
 
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
 #define CONFIG_PHY_ADDR		0x00
 #define CONFIG_ENV_OVERWRITE	1	/* allow overwriting of ethaddr */
-/* use misc_init_r() to read ethaddr from I2C EEPROM (see CFG_I2C_EEPROM) */
+/* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
 #define CONFIG_MISC_INIT_R	1
 #define CONFIG_MAC_OFFSET	0x35	/* MAC address offset in I2C EEPROM */
 
 /*
  * POST support
  */
-#define CONFIG_POST		(CFG_POST_MEMORY | CFG_POST_CPU | CFG_POST_I2C)
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C)
 #define MPC5XXX_SRAM_POST_SIZE	(MPC5XXX_SRAM_SIZE - 4)
 /* List of I2C addresses to be verified by POST */
-#define I2C_ADDR_LIST		{ CFG_I2C_SLAVE, CFG_I2C_IO, CFG_I2C_EEPROM }
+#define I2C_ADDR_LIST		{ CONFIG_SYS_I2C_SLAVE, CONFIG_SYS_I2C_IO, CONFIG_SYS_I2C_EEPROM }
 
 /* display image timestamps */
 #define CONFIG_TIMESTAMP	1
@@ -141,53 +142,53 @@
 /*
  * Clock configuration
  */
-#define CFG_MPC5XXX_CLKIN	33000000	/* SYS_XTAL_IN = 33MHz */
-#define CFG_IPBCLK_EQUALS_XLBCLK	1	/* IPB = 133MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* SYS_XTAL_IN = 33MHz */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK	1	/* IPB = 133MHz */
 
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
-#define CFG_LOWBOOT		1
+#define CONFIG_SYS_LOWBOOT		1
 
 /* Use ON-Chip SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
 #else
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
 #endif
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_BOARD_TYPES	1	/* we use board_type */
 
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(384 << 10)	/* 384 kB for Monitor */
-#define CFG_MALLOC_LEN		(256 << 10)	/* 256 kB for malloc() */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* initial mem map for Linux */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* 384 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* 256 kB for malloc() */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* initial mem map for Linux */
 
 /*
  * Flash configuration
  */
-#define CFG_FLASH_CFI		1
+#define CONFIG_SYS_FLASH_CFI		1
 #define CONFIG_FLASH_CFI_DRIVER	1
-#define CFG_FLASH_BASE		0xfc000000
+#define CONFIG_SYS_FLASH_BASE		0xfc000000
 /* we need these despite using CFI */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks */
-#define CFG_MAX_FLASH_SECT	256	/* max num of sectors on one chip */
-#define CFG_FLASH_SIZE		0x02000000 /* 32 MiB */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sectors on one chip */
+#define CONFIG_SYS_FLASH_SIZE		0x02000000 /* 32 MiB */
 
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT		1
-#undef CFG_LOWBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT		1
+#undef CONFIG_SYS_LOWBOOT
 #endif
 
 
@@ -195,19 +196,19 @@
  * Chip selects configuration
  */
 /* Boot Chipselect */
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x00087D31	/* for pci_clk = 33 MHz */
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00087D31	/* for pci_clk = 33 MHz */
 /* use board_early_init_r to enable flash write in CS_BOOT */
 #define CONFIG_BOARD_EARLY_INIT_R
 
 /* Flash memory addressing */
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
 /* No burst, dead cycle = 1 for CS0 (Flash) */
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x00000001
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x00000001
 
 /*
  * SDRAM configuration
@@ -233,11 +234,11 @@
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		2	/* Select I2C module #2 */
-#define CFG_I2C_SPEED		40000	/* 40 kHz */
-#define CFG_I2C_SLAVE		0x0
-#define CFG_I2C_IO		0x38	/* PCA9554AD I2C I/O port address */
-#define CFG_I2C_EEPROM		0x53	/* I2C EEPROM device address */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #2 */
+#define CONFIG_SYS_I2C_SPEED		40000	/* 40 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_IO		0x38	/* PCA9554AD I2C I/O port address */
+#define CONFIG_SYS_I2C_EEPROM		0x53	/* I2C EEPROM device address */
 
 /*
  * RTC configuration
@@ -267,7 +268,7 @@
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SIZE		0x10000
 #define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 /* Configuration of redundant environment */
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
@@ -287,44 +288,44 @@
  * PSC2: UART
  * PSC1: UART
  */
-#define CFG_GPS_PORT_CONFIG	0x10559C44
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x10559C44
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		1	/* undef to save memory */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_LONGHELP		1	/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
-#define CFG_ALT_MEMTEST		1
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x03f00000	/* 1 .. 63 MiB in SDRAM */
+#define CONFIG_SYS_ALT_MEMTEST		1
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x03f00000	/* 1 .. 63 MiB in SDRAM */
 
 #define CONFIG_LOOPW		1
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 /*
  * Various low-level settings
  */
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot */
 
-#define CFG_XLB_PIPELINING	1	/* enable transaction pipeling */
+#define CONFIG_SYS_XLB_PIPELINING	1	/* enable transaction pipeling */
 
 /*
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #ifdef CONFIG_CMD_KGDB
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*
diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index 9b74438..d9acb47 100644
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -42,42 +42,44 @@
 #define CONFIG_INITRD_TAG	1
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#define CFG_USE_MAIN_OSCILLATOR		1
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR		1
 /* flash */
-#define MC_PUIA_VAL	0x00000000
-#define MC_PUP_VAL	0x00000000
-#define MC_PUER_VAL	0x00000000
-#define MC_ASR_VAL	0x00000000
-#define MC_AASR_VAL	0x00000000
-#define EBI_CFGR_VAL	0x00000000
-#define SMC_CSR0_VAL	0x100032ad /* 16bit, 2 TDF, 4 WS */
+#define CONFIG_SYS_MC_PUIA_VAL	0x00000000
+#define CONFIG_SYS_MC_PUP_VAL	0x00000000
+#define CONFIG_SYS_MC_PUER_VAL	0x00000000
+#define CONFIG_SYS_MC_ASR_VAL	0x00000000
+#define CONFIG_SYS_MC_AASR_VAL	0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL	0x100032ad /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
-#define PLLAR_VAL	0x2026BE04 /* 179,712 MHz for PCK */
-#define PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
-#define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
+#define CONFIG_SYS_PLLAR_VAL	0x2026BE04 /* 179,712 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+#define CONFIG_SYS_MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
 
 /* sdram */
-#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR_VAL	0x00000000
-#define PIOC_PDR_VAL	0xFFFF0000
-#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
-#define SDRC_CR_VAL	0x3399c1d4 /* set up the SDRAM */
-#define SDRAM		0x20000000 /* address of the SDRAM */
-#define SDRAM1		0x20000080 /* address of the SDRAM */
-#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
-#define SDRC_MR_VAL	0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1	0x00000004 /* refresh */
-#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
-#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL	0x3399c1d4 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM	0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1	0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#else
+#define CONFIG_SKIP_RELOCATE_UBOOT
 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
 
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 #define CONFIG_BAUDRATE		9600
 
@@ -97,18 +99,18 @@
 #define CONFIG_HARD_I2C
 
 #ifdef CONFIG_HARD_I2C
-#define CFG_I2C_SPEED		0	/* not used */
-#define CFG_I2C_SLAVE		0	/* not used */
+#define CONFIG_SYS_I2C_SPEED		0	/* not used */
+#define CONFIG_SYS_I2C_SLAVE		0	/* not used */
 #define CONFIG_RTC_RS5C372A		/* RICOH I2C RTC */
-#define CFG_I2C_RTC_ADDR	0x32
-#define CFG_I2C_EEPROM_ADDR	0x50
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW
+#define CONFIG_SYS_I2C_RTC_ADDR	0x32
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 #else
 #define CONFIG_TIMESTAMP
 #endif
 /* still about 20 kB free with this defined */
-#define CFG_LONGHELP
+#define CONFIG_SYS_LONGHELP
 
 #define CONFIG_BOOTDELAY      1
 
@@ -141,7 +143,7 @@
 #endif
 
 
-#define CFG_LONGHELP
+#define CONFIG_SYS_LONGHELP
 
 #define AT91_SMART_MEDIA_ALE	(1 << 22)	/* our ALE is AD22 */
 #define AT91_SMART_MEDIA_CLE	(1 << 21)	/* our CLE is AD21 */
@@ -150,44 +152,44 @@
 #define PHYS_SDRAM		0x20000000
 #define PHYS_SDRAM_SIZE		0x1000000	/* 16 megs */
 
-#define CFG_MEMTEST_START	PHYS_SDRAM
-#define CFG_MEMTEST_END		CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
 
 #define CONFIG_DRIVER_ETHER
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_AT91C_USE_RMII
 
-#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
-#define CFG_MAX_DATAFLASH_BANKS		2
-#define CFG_MAX_DATAFLASH_PAGES		16384
-#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* Logical adress for CS0 */
-#define CFG_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* Logical adress for CS3 */
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
+#define CONFIG_SYS_MAX_DATAFLASH_PAGES		16384
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* Logical adress for CS0 */
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* Logical adress for CS3 */
 
 #define PHYS_FLASH_1			0x10000000
 #define PHYS_FLASH_SIZE			0x800000  /* 8 megs main flash */
-#define CFG_FLASH_BASE			PHYS_FLASH_1
-#define CFG_MONITOR_BASE		CFG_FLASH_BASE
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		256
-#define CFG_FLASH_ERASE_TOUT		(11 * CFG_HZ)	/* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT		( 2 * CFG_HZ)	/* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		256
+#define CONFIG_SYS_FLASH_ERASE_TOUT		(11 * CONFIG_SYS_HZ)	/* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT		( 2 * CONFIG_SYS_HZ)	/* Timeout for Flash Write */
 
 #define CONFIG_ENV_IS_IN_FLASH		1
 #define CONFIG_ENV_OFFSET			0x20000		/* after u-boot.bin */
 #define CONFIG_ENV_SECT_SIZE		(64 << 10)	/* sectors are 64 kB */
 #define CONFIG_ENV_SIZE			(16 << 10)	/* Use only 16 kB */
 
-#define CFG_LOAD_ADDR		0x21000000  /* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
 
-#define CFG_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
 
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
-#define CFG_MAXARGS		32		/* max number of command args */
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS		32		/* max number of command args */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 
-#define CFG_HZ 1000
-#define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2)	/* AT91C_TC0_CMR is implicitly set to */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK/2)	/* AT91C_TC0_CMR is implicitly set to */
 						/* AT91C_TC_TIMER_DIV1_CLOCK */
 
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h
index 19c2836..c3c603b 100644
--- a/include/configs/cmi_mpc5xx.h
+++ b/include/configs/cmi_mpc5xx.h
@@ -69,7 +69,7 @@
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BDI
 #define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_RUN
 #define CONFIG_CMD_IMI
 
@@ -93,25 +93,25 @@
  * Miscellaneous configurable options
  */
 
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	       /* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	       /* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x000fa000	/* 1 MB in SRAM			*/
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x000fa000	/* 1 MB in SRAM			*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address		*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address		*/
 
-#define	CFG_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 1250000 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 1250000 }
 
 
 /*
@@ -121,39 +121,39 @@
 /*
  * Internal Memory Mapped (This is not the IMMR content)
  */
-#define CFG_IMMR		0x01000000		/* Physical start adress of internal memory map */
+#define CONFIG_SYS_IMMR		0x01000000		/* Physical start adress of internal memory map */
 
 /*
  * Definitions for initial stack pointer and data area
  */
-#define CFG_INIT_RAM_ADDR	(CFG_IMMR + 0x003f9800)	/* Physical start adress of internal MPC555 writable RAM */
-#define	CFG_INIT_RAM_END	(CFG_IMMR + 0x003fffff)	/* Physical end adress of internal MPC555 used RAM area	*/
-#define	CFG_GBL_DATA_SIZE	64			/* Size in bytes reserved for initial global data */
-#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
-#define	CFG_INIT_SP_ADDR	0x013fa000		/* Physical start adress of inital stack */
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_IMMR + 0x003f9800)	/* Physical start adress of internal MPC555 writable RAM */
+#define	CONFIG_SYS_INIT_RAM_END	(CONFIG_SYS_IMMR + 0x003fffff)	/* Physical end adress of internal MPC555 used RAM area	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64			/* Size in bytes reserved for initial global data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_RAM_ADDR) - CONFIG_SYS_GBL_DATA_SIZE) /* Offset from the beginning of ram */
+#define	CONFIG_SYS_INIT_SP_ADDR	0x013fa000		/* Physical start adress of inital stack */
 
 /*
  * Start addresses for the final memory configuration
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000	/* Monitor won't change memory map			*/
-#define CFG_FLASH_BASE		0x02000000	/* External flash */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000	/* Monitor won't change memory map			*/
+#define CONFIG_SYS_FLASH_BASE		0x02000000	/* External flash */
 #define PLD_BASE		0x03000000	/* PLD  */
 #define ANYBUS_BASE		0x03010000	/* Anybus Module */
 
-#define CFG_RESET_ADRESS	0x01000000	/* Adress which causes reset */
-#define	CFG_MONITOR_BASE	CFG_FLASH_BASE	/* TEXT_BASE is defined in the board config.mk file.	*/
+#define CONFIG_SYS_RESET_ADRESS	0x01000000	/* Adress which causes reset */
+#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE	/* TEXT_BASE is defined in the board config.mk file.	*/
 						/* This adress is given to the linker with -Ttext to	*/
 						/* locate the text section at this adress.		*/
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor				*/
-#define	CFG_MALLOC_LEN		(64 << 10)	/* Reserve 128 kB for malloc()				*/
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor				*/
+#define	CONFIG_SYS_MALLOC_LEN		(64 << 10)	/* Reserve 128 kB for malloc()				*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux		*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux		*/
 
 
 /*-----------------------------------------------------------------------
@@ -162,18 +162,18 @@
  *
  */
 
-#define CFG_MAX_FLASH_BANKS	1		/* Max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	64		/* Max number of sectors on one chip	*/
-#define CFG_FLASH_ERASE_TOUT	180000		/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	600		/* Timeout for Flash Write (in ms)	*/
-#define CFG_FLASH_PROTECTION    1		/* Physically section protection on	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64		/* Max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	180000		/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	600		/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_PROTECTION    1		/* Physically section protection on	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 
 #ifdef	CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_OFFSET		0x00020000	/* Environment starts at this adress	*/
 #define	CONFIG_ENV_SIZE		0x00010000	/* Set whole sector as env		*/
-#define	CFG_USE_PPCENV				/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV				/* Environment embedded in sect .ppcenv */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -183,10 +183,10 @@
  * SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWP)
 #endif	/* CONFIG_WATCHDOG */
 
@@ -195,14 +195,14 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register
@@ -211,7 +211,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF00
-#define CFG_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
 			 SCCR_COM00   | SCCR_DFNL000 | SCCR_DFNH000)
 
 /*-----------------------------------------------------------------------
@@ -219,7 +219,7 @@
  *-----------------------------------------------------------------------
  * Data show cycle
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00)		/* Disable data show cycle	*/
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00)		/* Disable data show cycle	*/
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register
@@ -227,8 +227,8 @@
  * Set all bits to 40 Mhz
  *
  */
-#define CFG_OSC_CLK	((uint)4000000)		/* Oscillator clock is 4MHz	*/
-#define CFG_PLPRCR	(PLPRCR_MF_9 | PLPRCR_DIVF_0)
+#define CONFIG_SYS_OSC_CLK	((uint)4000000)		/* Oscillator clock is 4MHz	*/
+#define CONFIG_SYS_PLPRCR	(PLPRCR_MF_9 | PLPRCR_DIVF_0)
 
 
 /*-----------------------------------------------------------------------
@@ -236,36 +236,36 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_UMCR	(UMCR_FSPEED)		/* IMB clock same as U-bus	*/
+#define CONFIG_SYS_UMCR	(UMCR_FSPEED)		/* IMB clock same as U-bus	*/
 
 /*-----------------------------------------------------------------------
  * ICTRL - I-Bus Support Control Register
  */
-#define CFG_ICTRL	(ICTRL_ISCT_SER_7)	/* Take out of serialized mode	*/
+#define CONFIG_SYS_ICTRL	(ICTRL_ISCT_SER_7)	/* Take out of serialized mode	*/
 
 /*-----------------------------------------------------------------------
  * USIU - Memory Controller Register
  *-----------------------------------------------------------------------
  */
 
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16)
-#define CFG_OR0_PRELIM		(OR_ADDR_MK_FF | OR_SCY_3)
-#define CFG_BR1_PRELIM		(ANYBUS_BASE)
-#define CFG_OR1_PRELIM		(OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR)
-#define CFG_BR2_PRELIM		(CFG_SDRAM_BASE | BR_V | BR_PS_32)
-#define CFG_OR2_PRELIM		(OR_ADDR_MK_FF)
-#define CFG_BR3_PRELIM		(PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8)
-#define CFG_OR3_PRELIM		(OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16)
+#define CONFIG_SYS_OR0_PRELIM		(OR_ADDR_MK_FF | OR_SCY_3)
+#define CONFIG_SYS_BR1_PRELIM		(ANYBUS_BASE)
+#define CONFIG_SYS_OR1_PRELIM		(OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR)
+#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_SDRAM_BASE | BR_V | BR_PS_32)
+#define CONFIG_SYS_OR2_PRELIM		(OR_ADDR_MK_FF)
+#define CONFIG_SYS_BR3_PRELIM		(PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8)
+#define CONFIG_SYS_OR3_PRELIM		(OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \
 				 OR_ACS_10 | OR_ETHR | OR_CSNT)
 
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* We don't realign the flash	*/
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* We don't realign the flash	*/
 
 /*-----------------------------------------------------------------------
  * DER - Timer Decrementer
  *-----------------------------------------------------------------------
  * Initialise to zero
  */
-#define CFG_DER			0x00000000
+#define CONFIG_SYS_DER			0x00000000
 
 
 /*
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 9b729ac..fb32f3f 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -53,13 +53,13 @@
 /* ---
  * Defines processor clock - important for correct timings concerning serial
  * interface etc.
- * CFG_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms
+ * CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms
  * ---
  */
 
-#define CFG_HZ			1000
-#define CFG_CLK			66000000
-#define CFG_SDRAM_SIZE		16		/* SDRAM size in MB */
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CLK			66000000
+#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
 
 /* ---
  * Enable use of Ethernet
@@ -73,15 +73,15 @@
 /* ---
  * Define baudrate for UART1 (console output, tftp, ...)
  * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
- * CFG_BAUDRATE_TABLE defines values that can be selected in u-boot command
+ * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
  * interface
  * ---
  */
 
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		19200
-#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
 
 /* ---
  * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
@@ -159,22 +159,22 @@
 #	define CONFIG_NET_MULTI		1
 #	define CONFIG_MII		1
 #	define CONFIG_MII_INIT		1
-#	define CFG_DISCOVER_PHY
-#	define CFG_RX_ETH_BUFFER	8
-#	define CFG_FAULT_ECHO_LINK_DOWN
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 
-#	define CFG_FEC0_PINMUX		0
-#	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
 #	define MCFFEC_TOUT_LOOP		50000
-/* If CFG_DISCOVER_PHY is not defined - hardcoded */
-#	ifndef CFG_DISCOVER_PHY
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
 #		define FECDUPLEX	FULL
 #		define FECSPEED		_100BASET
 #	else
-#		ifndef CFG_FAULT_ECHO_LINK_DOWN
-#			define CFG_FAULT_ECHO_LINK_DOWN
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #		endif
-#	endif			/* CFG_DISCOVER_PHY */
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
 #endif
 
 /*
@@ -211,23 +211,23 @@ considered during boot */
 
 #endif
 
-#define CFG_PROMPT		"COBRA > "	/* Layout of u-boot prompt*/
+#define CONFIG_SYS_PROMPT		"COBRA > "	/* Layout of u-boot prompt*/
 
-#define CFG_LOAD_ADDR		0x20000		/*Defines default RAM address
+#define CONFIG_SYS_LOAD_ADDR		0x20000		/*Defines default RAM address
 from which user programs will be started */
 
 /*---*/
 
-#define CFG_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
 /*
  *-----------------------------------------------------------------------------
@@ -240,8 +240,8 @@ from which user programs will be started */
  * ---
  */
 
-#define CFG_MEMTEST_START	0x400
-#define CFG_MEMTEST_END		0x380000
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
 
 /* ---
  * Low Level Configuration Settings
@@ -255,39 +255,39 @@ from which user programs will be started */
  * ---
  */
 
-#define CFG_MBAR		0x10000000	/* Register Base Addrs */
+#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
 
 /* ---
  * System Conf. Reg. & System Protection Reg.
  * ---
  */
 
-#define CFG_SCR			0x0003;
-#define CFG_SPR			0xffff;
+#define CONFIG_SYS_SCR			0x0003
+#define CONFIG_SYS_SPR			0xffff
 
 /* ---
  * Ethernet settings
  * ---
  */
 
-#define CFG_DISCOVER_PHY
-#define CFG_ENET_BD_BASE	0x780000
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_SYS_ENET_BD_BASE	0x780000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in internal SRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x20000000
-#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
-#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
 
 /*
  *-------------------------------------------------------------------------
@@ -295,42 +295,42 @@ from which user programs will be started */
  *-----------------------------------------------------------------------
  */
 
-/* #define CFG_SDRAM_SIZE		16 */
+/* #define CONFIG_SYS_SDRAM_SIZE		16 */
 
 /*
  *-----------------------------------------------------------------------
  */
 
-#define CFG_FLASH_BASE		0xffe00000
+#define CONFIG_SYS_FLASH_BASE		0xffe00000
 
 #ifdef	CONFIG_MONITOR_IS_IN_RAM
-#define CFG_MONITOR_BASE	0x20000
+#define CONFIG_SYS_MONITOR_BASE	0x20000
 #else
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
 #endif
 
-#define CFG_MONITOR_LEN		0x20000
-#define CFG_MALLOC_LEN		(256 << 10)
-#define CFG_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	11	/* max number of sectors on one chip	*/
-#define CFG_FLASH_ERASE_TOUT	1000	/* flash timeout */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	11	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000	/* flash timeout */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /*-----------------------------------------------------------------------
  * Memory bank definitions
@@ -338,29 +338,29 @@ from which user programs will be started */
  * Please refer also to Motorola Coldfire user manual - Chapter XXX
  * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
  */
-#define CFG_BR0_PRELIM		0xFFE00201
-#define CFG_OR0_PRELIM		0xFFE00014
+#define CONFIG_SYS_BR0_PRELIM		0xFFE00201
+#define CONFIG_SYS_OR0_PRELIM		0xFFE00014
 
-#define CFG_BR1_PRELIM		0
-#define CFG_OR1_PRELIM		0
+#define CONFIG_SYS_BR1_PRELIM		0
+#define CONFIG_SYS_OR1_PRELIM		0
 
-#define CFG_BR2_PRELIM		0
-#define CFG_OR2_PRELIM		0
+#define CONFIG_SYS_BR2_PRELIM		0
+#define CONFIG_SYS_OR2_PRELIM		0
 
-#define CFG_BR3_PRELIM		0
-#define CFG_OR3_PRELIM		0
+#define CONFIG_SYS_BR3_PRELIM		0
+#define CONFIG_SYS_OR3_PRELIM		0
 
-#define CFG_BR4_PRELIM		0
-#define CFG_OR4_PRELIM		0
+#define CONFIG_SYS_BR4_PRELIM		0
+#define CONFIG_SYS_OR4_PRELIM		0
 
-#define CFG_BR5_PRELIM		0
-#define CFG_OR5_PRELIM		0
+#define CONFIG_SYS_BR5_PRELIM		0
+#define CONFIG_SYS_OR5_PRELIM		0
 
-#define CFG_BR6_PRELIM		0
-#define CFG_OR6_PRELIM		0
+#define CONFIG_SYS_BR6_PRELIM		0
+#define CONFIG_SYS_OR6_PRELIM		0
 
-#define CFG_BR7_PRELIM		0x00000701
-#define CFG_OR7_PRELIM		0xFF00007C
+#define CONFIG_SYS_BR7_PRELIM		0x00000701
+#define CONFIG_SYS_OR7_PRELIM		0xFF00007C
 
 /*-----------------------------------------------------------------------
  * LED config
@@ -377,15 +377,15 @@ from which user programs will be started */
 /*-----------------------------------------------------------------------
  * Port configuration (GPIO)
  */
-#define CFG_PACNT		0x00000000		/* PortA control reg.: All pins are external
+#define CONFIG_SYS_PACNT		0x00000000		/* PortA control reg.: All pins are external
 GPIO*/
-#define CFG_PADDR		0x00FF			/* PortA direction reg.: PA7 to PA0 are outputs
+#define CONFIG_SYS_PADDR		0x00FF			/* PortA direction reg.: PA7 to PA0 are outputs
 (1^=output, 0^=input) */
-#define CFG_PADAT		LED_STAT_0		/* PortA value reg.: Turn all LED off */
-#define CFG_PBCNT		0x55554155		/* PortB control reg.: Ethernet/UART
+#define CONFIG_SYS_PADAT		LED_STAT_0		/* PortA value reg.: Turn all LED off */
+#define CONFIG_SYS_PBCNT		0x55554155		/* PortB control reg.: Ethernet/UART
 configuration */
-#define CFG_PBDDR		0x0000			/* PortB direction: All pins configured as inputs */
-#define CFG_PBDAT		0x0000			/* PortB value reg. */
-#define CFG_PDCNT		0x00000000		/* PortD control reg. */
+#define CONFIG_SYS_PBDDR		0x0000			/* PortB direction: All pins configured as inputs */
+#define CONFIG_SYS_PBDAT		0x0000			/* PortB value reg. */
+#define CONFIG_SYS_PDCNT		0x00000000		/* PortD control reg. */
 
 #endif	/* _CONFIG_COBRA5272_H */
diff --git a/include/configs/cogent_mpc8260.h b/include/configs/cogent_mpc8260.h
index b39f4cb..c580230 100644
--- a/include/configs/cogent_mpc8260.h
+++ b/include/configs/cogent_mpc8260.h
@@ -136,25 +136,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*
  * Low Level Configuration Settings
@@ -164,19 +164,19 @@
 
 /*-----------------------------------------------------------------------
  * Low Level Cogent settings
- * if CFG_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
+ * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
  * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
  * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
  * (second 2 for CMA120 only)
  */
-#define CFG_CMA_MB_BASE		0x00000000	/* base of m/b address space */
+#define CONFIG_SYS_CMA_MB_BASE		0x00000000	/* base of m/b address space */
 
 #include <configs/cogent_common.h>
 
 #ifdef CONFIG_CONS_NONE
-#define CFG_CMA_CONS_SERIAL	/* use Cogent motherboard serial for console */
+#define CONFIG_SYS_CMA_CONS_SERIAL	/* use Cogent motherboard serial for console */
 #endif
-#define CFG_CMA_LCD_HEARTBEAT	/* define for sec rotator in lcd corner */
+#define CONFIG_SYS_CMA_LCD_HEARTBEAT	/* define for sec rotator in lcd corner */
 #define CONFIG_SHOW_ACTIVITY
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
@@ -197,68 +197,68 @@
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  *
- * if you change bits in the HRCW, you must also change the CFG_*
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
  * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
  */
-#define CFG_HRCW_MASTER	(HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\
+#define CONFIG_SYS_HRCW_MASTER	(HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\
 			 HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101)
 /* no slaves so just duplicate the master hrcw */
-#define CFG_HRCW_SLAVE1	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE2	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE3	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE4	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE5	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE6	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE7	CFG_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE1	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE2	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE3	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE4	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE5	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE6	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE7	CONFIG_SYS_HRCW_MASTER
 
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR		0xF0000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		CMA_MB_RAM_BASE
+#define	CONFIG_SYS_SDRAM_BASE		CMA_MB_RAM_BASE
 #ifdef CONFIG_CMA302
-#define CFG_FLASH_BASE		CMA_MB_SLOT2_BASE	/* cma302 in slot 2 */
+#define CONFIG_SYS_FLASH_BASE		CMA_MB_SLOT2_BASE	/* cma302 in slot 2 */
 #else
-#define CFG_FLASH_BASE		CMA_MB_FLASH_BASE	/* flash on m/b */
+#define CONFIG_SYS_FLASH_BASE		CMA_MB_FLASH_BASE	/* flash on m/b */
 #endif
-#define	CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+#define	CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	67	/* max num of sects on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max num of sects on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		CFG_FLASH_BASE /* Addr of Environment Sector */
+#define CONFIG_ENV_ADDR		CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
 #ifdef CONFIG_CMA302
 #define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
 #define CONFIG_ENV_SECT_SIZE	(512*1024) /* see README - env sect real size */
@@ -269,9 +269,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
 #if defined(CONFIG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -284,29 +284,29 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 				HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
-#define CFG_HID2	0
+#define CONFIG_SYS_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2	0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register					 5-5
  *-----------------------------------------------------------------------
  * turn on Checkstop Reset Enable
  */
-#define CFG_RMR		RMR_CSRE
+#define CONFIG_SYS_RMR		RMR_CSRE
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration					 4-25
  *-----------------------------------------------------------------------
  */
-#define CFG_BCR		BCR_EBM
+#define CONFIG_SYS_BCR		BCR_EBM
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration				 4-31
  *-----------------------------------------------------------------------
  */
-#define CFG_SIUMCR	(SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)
 
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control				 4-35
@@ -315,10 +315,10 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
@@ -328,7 +328,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		 4-42
@@ -336,20 +336,20 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control					 9-8
  *-----------------------------------------------------------------------
  * Ensure DFBRG is Divide by 16
  */
-#define CFG_SCCR	(SCCR_DFBRG01)
+#define CONFIG_SYS_SCCR	(SCCR_DFBRG01)
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration				13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR	0
+#define CONFIG_SYS_RCCR	0
 
 #if defined(CONFIG_CMA282)
 
@@ -367,26 +367,26 @@
  * (the *_SIZE vars must be a power of 2)
  */
 
-#define CFG_CMA_CS0_BASE	TEXT_BASE	/* EPROM */
-#define CFG_CMA_CS0_SIZE	(1 << 20)
+#define CONFIG_SYS_CMA_CS0_BASE	TEXT_BASE	/* EPROM */
+#define CONFIG_SYS_CMA_CS0_SIZE	(1 << 20)
 #if 0
-#define CFG_CMA_CS2_BASE	0x10000000	/* Local Bus SDRAM */
-#define CFG_CMA_CS2_SIZE	(16 << 20)
+#define CONFIG_SYS_CMA_CS2_BASE	0x10000000	/* Local Bus SDRAM */
+#define CONFIG_SYS_CMA_CS2_SIZE	(16 << 20)
 #endif
 
 /*
  * CS0 maps the EPROM on the cpu module
- * Set it for 10 wait states, address CFG_MONITOR_BASE and size 1M
+ * Set it for 10 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
  *
  * Note: We must have already transferred control to the final location
  * of the EPROM before these are used, because when BR0/OR0 are set, the
  * mirror of the eprom at any other addresses will disappear.
  */
 
-/* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
-#define CFG_BR0_PRELIM	((CFG_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
-/* mask size CFG_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
-#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_CMA_CS0_SIZE)|\
+/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
+/* mask size CONFIG_SYS_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
+#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_CMA_CS0_SIZE)|\
 				ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
 
 /*
@@ -399,10 +399,10 @@
  */
 
 #if 0
-/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, ??? */
-#define CFG_BR0_PRELIM	((CFG_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
-/* mask size CFG_CMA_CS2_SIZE, CS time normal, ??? */
-#define CFG_OR2_PRELIM	((~(CFG_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
+/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, ??? */
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
+/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, ??? */
+#define CONFIG_SYS_OR2_PRELIM	((~(CONFIG_SYS_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
 #endif
 
 #endif
diff --git a/include/configs/cogent_mpc8xx.h b/include/configs/cogent_mpc8xx.h
index c77f9a2..17bd9a0 100644
--- a/include/configs/cogent_mpc8xx.h
+++ b/include/configs/cogent_mpc8xx.h
@@ -55,8 +55,8 @@
 #define CONFIG_BAUDRATE		230400
 
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
-#define CFG_I2C_SPEED		400000  /* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000  /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 
 /*
@@ -101,27 +101,27 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#define CFG_ALLOC_DPRAM
+#define CONFIG_SYS_ALLOC_DPRAM
 
 /*
  * Low Level Configuration Settings
@@ -131,18 +131,18 @@
 
 /*-----------------------------------------------------------------------
  * Low Level Cogent settings
- * if CFG_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not.
+ * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not.
  * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
  * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
  * (second 2 for CMA120 only)
  */
-#define CFG_CMA_MB_BASE		0x00000000	/* base of m/b address space */
+#define CONFIG_SYS_CMA_MB_BASE		0x00000000	/* base of m/b address space */
 
 #include <configs/cogent_common.h>
 
-#define CFG_CMA_CONS_SERIAL	/* use Cogent motherboard serial for console */
+#define CONFIG_SYS_CMA_CONS_SERIAL	/* use Cogent motherboard serial for console */
 #define CONFIG_CONS_INDEX	1
-#define CFG_CMA_LCD_HEARTBEAT	/* define for sec rotator in lcd corner */
+#define CONFIG_SYS_CMA_LCD_HEARTBEAT	/* define for sec rotator in lcd corner */
 #define CONFIG_SHOW_ACTIVITY
 #if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
 /*
@@ -162,49 +162,49 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFF000000
+#define CONFIG_SYS_IMMR		0xFF000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		CMA_MB_RAM_BASE
+#define	CONFIG_SYS_SDRAM_BASE		CMA_MB_RAM_BASE
 #ifdef CONFIG_CMA302
-#define CFG_FLASH_BASE		CMA_MB_SLOT2_BASE	/* cma302 in slot 2 */
+#define CONFIG_SYS_FLASH_BASE		CMA_MB_SLOT2_BASE	/* cma302 in slot 2 */
 #else
-#define CFG_FLASH_BASE		CMA_MB_FLASH_BASE	/* flash on m/b */
+#define CONFIG_SYS_FLASH_BASE		CMA_MB_FLASH_BASE	/* flash on m/b */
 #endif
-#define	CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		CFG_FLASH_BASE /* Addr of Environment Sector */
+#define CONFIG_ENV_ADDR		CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
 #ifdef CONFIG_CMA302
 #define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
 #define CONFIG_ENV_SECT_SIZE	(512*1024) /* see README - env sect real size */
@@ -214,9 +214,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 
@@ -227,10 +227,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif	/* CONFIG_WATCHDOG */
 
 /*-----------------------------------------------------------------------
@@ -238,21 +238,21 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -260,7 +260,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit - leave PLL multiplication factor unchanged !
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -269,7 +269,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -279,29 +279,29 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
 
 #if defined(CONFIG_CMA286_60_OLD)
 
 /*
  * Init Memory Controller:
  *
- * NOTE: although the names (CFG_xRn_PRELIM) suggest preliminary settings,
+ * NOTE: although the names (CONFIG_SYS_xRn_PRELIM) suggest preliminary settings,
  * they are actually the final settings for this cpu/board, because the
  * flash and RAM are on the motherboard, accessed via the CMAbus, and the
  * mappings are pretty much fixed.
@@ -309,58 +309,58 @@
  * (the *_SIZE vars must be a power of 2)
  */
 
-#define CFG_CMA_CS0_BASE	TEXT_BASE		/* EPROM */
-#define CFG_CMA_CS0_SIZE	(1 << 20)
-#define CFG_CMA_CS1_BASE	CMA_MB_RAM_BASE		/* RAM + I/O SLOT 1 */
-#define CFG_CMA_CS1_SIZE	(64 << 20)
-#define CFG_CMA_CS2_BASE	CMA_MB_SLOT2_BASE	/* I/O SLOTS 2 + 3 */
-#define CFG_CMA_CS2_SIZE	(64 << 20)
-#define CFG_CMA_CS3_BASE	CMA_MB_ROMLOW_BASE	/* M/B I/O */
-#define CFG_CMA_CS3_SIZE	(32 << 20)
+#define CONFIG_SYS_CMA_CS0_BASE	TEXT_BASE		/* EPROM */
+#define CONFIG_SYS_CMA_CS0_SIZE	(1 << 20)
+#define CONFIG_SYS_CMA_CS1_BASE	CMA_MB_RAM_BASE		/* RAM + I/O SLOT 1 */
+#define CONFIG_SYS_CMA_CS1_SIZE	(64 << 20)
+#define CONFIG_SYS_CMA_CS2_BASE	CMA_MB_SLOT2_BASE	/* I/O SLOTS 2 + 3 */
+#define CONFIG_SYS_CMA_CS2_SIZE	(64 << 20)
+#define CONFIG_SYS_CMA_CS3_BASE	CMA_MB_ROMLOW_BASE	/* M/B I/O */
+#define CONFIG_SYS_CMA_CS3_SIZE	(32 << 20)
 
 /*
  * CS0 maps the EPROM on the cpu module
- * Set it for 4 wait states, address CFG_MONITOR_BASE and size 1M
+ * Set it for 4 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
  *
  * Note: We must have already transferred control to the final location
  * of the EPROM before these are used, because when BR0/OR0 are set, the
  * mirror of the eprom at any other addresses will disappear.
  */
 
-/* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */
-#define CFG_BR0_PRELIM	((CFG_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V)
-/* mask size CFG_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */
-#define CFG_OR0_PRELIM	((~(CFG_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK)
+/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V)
+/* mask size CONFIG_SYS_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */
+#define CONFIG_SYS_OR0_PRELIM	((~(CONFIG_SYS_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK)
 
 /*
  * CS1 maps motherboard DRAM and motherboard I/O slot 1
  * (each 32Mbyte in size)
  */
 
-/* base address = CFG_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */
-#define CFG_BR1_PRELIM	((CFG_CMA_CS1_BASE&BR_BA_MSK)|BR_V)
-/* mask size CFG_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */
-#define CFG_OR1_PRELIM	((~(CFG_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA)
+/* base address = CONFIG_SYS_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_CMA_CS1_BASE&BR_BA_MSK)|BR_V)
+/* mask size CONFIG_SYS_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */
+#define CONFIG_SYS_OR1_PRELIM	((~(CONFIG_SYS_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA)
 
 /*
  * CS2 maps motherboard I/O slots 2 and 3
  * (each 32Mbyte in size)
  */
 
-/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */
-#define CFG_BR2_PRELIM	((CFG_CMA_CS2_BASE&BR_BA_MSK)|BR_V)
-/* mask size CFG_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */
-#define CFG_OR2_PRELIM	((~(CFG_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA)
+/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */
+#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_CMA_CS2_BASE&BR_BA_MSK)|BR_V)
+/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */
+#define CONFIG_SYS_OR2_PRELIM	((~(CONFIG_SYS_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA)
 
 /*
  * CS3 maps motherboard I/O
  * (32Mbyte in size)
  */
 
-/* base address = CFG_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */
-#define CFG_BR3_PRELIM	((CFG_CMA_CS3_BASE&BR_BA_MSK)|BR_V)
-/* mask size CFG_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */
-#define CFG_OR3_PRELIM	((~(CFG_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA)
+/* base address = CONFIG_SYS_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */
+#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_CMA_CS3_BASE&BR_BA_MSK)|BR_V)
+/* mask size CONFIG_SYS_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */
+#define CONFIG_SYS_OR3_PRELIM	((~(CONFIG_SYS_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA)
 
 #endif
 
diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h
index 1f53ddc..52df16a 100644
--- a/include/configs/cpci5200.h
+++ b/include/configs/cpci5200.h
@@ -45,7 +45,7 @@
 #define CONFIG_CPCI5200		1	/* ... on CPCI5200  board */
 #define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM	  */
 
-#define CFG_MPC5XXX_CLKIN	33000000	/* ... running at 33.000000MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* ... running at 33.000000MHz */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
@@ -57,7 +57,7 @@
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
 #define CONFIG_BAUDRATE		9600	/* ... at 115200 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #ifdef CONFIG_MPC5200		/* MPC5100 PCI is not supported yet. */
 /*
@@ -86,7 +86,7 @@
 #if 0				/* test-only !!! */
 #define CONFIG_NET_MULTI	1
 #define CONFIG_EEPRO100		1
-#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
+#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
 #define CONFIG_NS8382X		1
 #endif
 
@@ -130,12 +130,12 @@
 #define CONFIG_CMD_DATE
 
 #if (TEXT_BASE == 0xFF000000)	/* Boot low with 16 MB Flash */
-#   define CFG_LOWBOOT		1
-#   define CFG_LOWBOOT16	1
+#   define CONFIG_SYS_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT16	1
 #endif
 #if (TEXT_BASE == 0xFF800000)	/* Boot low with  8 MB Flash */
-#   define CFG_LOWBOOT		1
-#   define CFG_LOWBOOT08	1
+#   define CONFIG_SYS_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT08	1
 #endif
 
 /*
@@ -172,48 +172,48 @@
 #if defined(CONFIG_MPC5200)
 
 #define CONFIG_RTC_M48T35A	1	/* ST Electronics M48 timekeeper */
-#define CFG_NVRAM_BASE_ADDR	0xfd010000
-#define CFG_NVRAM_SIZE		32*1024
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xfd010000
+#define CONFIG_SYS_NVRAM_SIZE		32*1024
 
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 #endif
 /*
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		1	/* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_MODULE		1	/* Select I2C module #1 or #2 */
 
-#define CFG_I2C_SPEED		86000	/* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		86000	/* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration
  */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CFG_I2C_EEPROM_ADDR_LEN		2
-#define CFG_EEPROM_PAGE_WRITE_BITS	5
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
-#define CFG_I2C_MULTI_EEPROMS		1
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CONFIG_SYS_I2C_MULTI_EEPROMS		1
 /*
  * Flash configuration
  */
 
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant	     */
-#define CFG_FLASH_BASE		0xFE000000
-#define CFG_FLASH_SIZE		0x02000000
-#define CFG_FLASH_INCREMENT	0x01000000
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00000000)
-#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	128
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant	     */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_SIZE		0x02000000
+#define CONFIG_SYS_FLASH_INCREMENT	0x01000000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00000000)
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128
 
-#define CFG_FLASH_PROTECTION	1	/* use hardware protection	     */
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)  */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware protection	     */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)  */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
 
 /*
  * Environment settings
@@ -234,31 +234,32 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
 /*
  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
  */
@@ -269,66 +270,66 @@
 /*
  * GPIO configuration
  */
-#define CFG_GPS_PORT_CONFIG	0x01052444
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x01052444
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*
  * Various low-level settings
  */
 #if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 #else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
 #endif
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x0004DD00
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x0004DD00
 
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
-#define CFG_CS1_START		0xfd000000
-#define CFG_CS1_SIZE		0x00010000
-#define CFG_CS1_CFG		0x10101410
+#define CONFIG_SYS_CS1_START		0xfd000000
+#define CONFIG_SYS_CS1_SIZE		0x00010000
+#define CONFIG_SYS_CS1_CFG		0x10101410
 
-#define CFG_CS3_START		0xfd010000
-#define CFG_CS3_SIZE		0x00010000
-#define CFG_CS3_CFG		0x10109410
+#define CONFIG_SYS_CS3_START		0xfd010000
+#define CONFIG_SYS_CS3_SIZE		0x00010000
+#define CONFIG_SYS_CS3_CFG		0x10109410
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
 
-#define CFG_RESET_ADDRESS	0xff000000
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
 
 /*-----------------------------------------------------------------------
  * USB stuff
@@ -350,71 +351,71 @@
 #define	CONFIG_IDE_RESET	/* reset for ide supported	*/
 #define CONFIG_IDE_PREINIT
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(0x0060)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005C)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
 
 /* Interval between registers						     */
-#define CFG_ATA_STRIDE		4
+#define CONFIG_SYS_ATA_STRIDE		4
 
 /*-----------------------------------------------------------------------
  * CPLD stuff
  */
-#define CFG_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD	 */
-#define CFG_FPGA_MAX_SIZE	32*1024	/* 32kByte is enough for CPLD	 */
+#define CONFIG_SYS_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD	 */
+#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	/* 32kByte is enough for CPLD	 */
 
 /* CPLD program pin configuration */
-#define CFG_FPGA_PRG		0x20000000	/* JTAG TMS pin (ppc output)	       */
-#define CFG_FPGA_CLK		0x10000000	/* JTAG TCK pin (ppc output)	       */
-#define CFG_FPGA_DATA		0x20000000	/* JTAG TDO->TDI data pin (ppc output) */
-#define CFG_FPGA_DONE		0x10000000	/* JTAG TDI->TDO pin (ppc input)       */
+#define CONFIG_SYS_FPGA_PRG		0x20000000	/* JTAG TMS pin (ppc output)	       */
+#define CONFIG_SYS_FPGA_CLK		0x10000000	/* JTAG TCK pin (ppc output)	       */
+#define CONFIG_SYS_FPGA_DATA		0x20000000	/* JTAG TDO->TDI data pin (ppc output) */
+#define CONFIG_SYS_FPGA_DONE		0x10000000	/* JTAG TDI->TDO pin (ppc input)       */
 
-#define JTAG_GPIO_ADDR_TMS	(CFG_MBAR + 0xB10)	/* JTAG TMS pin (GPS data out value reg.)      */
-#define JTAG_GPIO_ADDR_TCK	(CFG_MBAR + 0xC0C)	/* JTAG TCK pin (GPW data out value reg.)      */
-#define JTAG_GPIO_ADDR_TDI	(CFG_MBAR + 0xC0C)	/* JTAG TDO->TDI pin (GPW data out value reg.) */
-#define JTAG_GPIO_ADDR_TDO	(CFG_MBAR + 0xB14)	/* JTAG TDI->TDO pin (GPS data in value reg.)  */
+#define JTAG_GPIO_ADDR_TMS	(CONFIG_SYS_MBAR + 0xB10)	/* JTAG TMS pin (GPS data out value reg.)      */
+#define JTAG_GPIO_ADDR_TCK	(CONFIG_SYS_MBAR + 0xC0C)	/* JTAG TCK pin (GPW data out value reg.)      */
+#define JTAG_GPIO_ADDR_TDI	(CONFIG_SYS_MBAR + 0xC0C)	/* JTAG TDO->TDI pin (GPW data out value reg.) */
+#define JTAG_GPIO_ADDR_TDO	(CONFIG_SYS_MBAR + 0xB14)	/* JTAG TDI->TDO pin (GPS data in value reg.)  */
 
-#define JTAG_GPIO_ADDR_CFG	(CFG_MBAR + 0xB00)
+#define JTAG_GPIO_ADDR_CFG	(CONFIG_SYS_MBAR + 0xB00)
 #define JTAG_GPIO_CFG_SET	0x00000000
 #define JTAG_GPIO_CFG_RESET	0x00F00000
 
-#define JTAG_GPIO_ADDR_EN_TMS	(CFG_MBAR + 0xB04)
+#define JTAG_GPIO_ADDR_EN_TMS	(CONFIG_SYS_MBAR + 0xB04)
 #define JTAG_GPIO_TMS_EN_SET	0x20000000	/* Enable for GPIO */
 #define JTAG_GPIO_TMS_EN_RESET	0x00000000
-#define JTAG_GPIO_ADDR_DDR_TMS	(CFG_MBAR + 0xB0C)
+#define JTAG_GPIO_ADDR_DDR_TMS	(CONFIG_SYS_MBAR + 0xB0C)
 #define JTAG_GPIO_TMS_DDR_SET	0x20000000	/* Set as output   */
 #define JTAG_GPIO_TMS_DDR_RESET 0x00000000
 
-#define JTAG_GPIO_ADDR_EN_TCK	(CFG_MBAR + 0xC00)
+#define JTAG_GPIO_ADDR_EN_TCK	(CONFIG_SYS_MBAR + 0xC00)
 #define JTAG_GPIO_TCK_EN_SET	0x20000000	/* Enable for GPIO */
 #define JTAG_GPIO_TCK_EN_RESET	0x00000000
-#define JTAG_GPIO_ADDR_DDR_TCK	(CFG_MBAR + 0xC08)
+#define JTAG_GPIO_ADDR_DDR_TCK	(CONFIG_SYS_MBAR + 0xC08)
 #define JTAG_GPIO_TCK_DDR_SET	0x20000000	/* Set as output   */
 #define JTAG_GPIO_TCK_DDR_RESET 0x00000000
 
-#define JTAG_GPIO_ADDR_EN_TDI	(CFG_MBAR + 0xC00)
+#define JTAG_GPIO_ADDR_EN_TDI	(CONFIG_SYS_MBAR + 0xC00)
 #define JTAG_GPIO_TDI_EN_SET	0x10000000	/* Enable as GPIO  */
 #define JTAG_GPIO_TDI_EN_RESET	0x00000000
-#define JTAG_GPIO_ADDR_DDR_TDI	(CFG_MBAR + 0xC08)
+#define JTAG_GPIO_ADDR_DDR_TDI	(CONFIG_SYS_MBAR + 0xC08)
 #define JTAG_GPIO_TDI_DDR_SET	0x10000000	/* Set as output   */
 #define JTAG_GPIO_TDI_DDR_RESET 0x00000000
 
-#define JTAG_GPIO_ADDR_EN_TDO	(CFG_MBAR + 0xB04)
+#define JTAG_GPIO_ADDR_EN_TDO	(CONFIG_SYS_MBAR + 0xB04)
 #define JTAG_GPIO_TDO_EN_SET	0x10000000	/* Enable as GPIO  */
 #define JTAG_GPIO_TDO_EN_RESET	0x00000000
-#define JTAG_GPIO_ADDR_DDR_TDO	(CFG_MBAR + 0xB0C)
+#define JTAG_GPIO_ADDR_DDR_TDO	(CONFIG_SYS_MBAR + 0xB0C)
 #define JTAG_GPIO_TDO_DDR_SET	0x00000000
 #define JTAG_GPIO_TDO_DDR_RESET 0x10000000	/* Set as input	   */
 
diff --git a/include/configs/cradle.h b/include/configs/cradle.h
index 34a265d..5131175 100644
--- a/include/configs/cradle.h
+++ b/include/configs/cradle.h
@@ -40,8 +40,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -89,25 +89,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP                            /* undef to save memory         */
-#define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
-#define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS             16              /* max number of command args   */
-#define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LONGHELP                            /* undef to save memory         */
+#define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt       */
+#define CONFIG_SYS_CBSIZE              256             /* Console I/O Buffer Size      */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS             16              /* max number of command args   */
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE      /* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START       0xa0400000      /* memtest works on     */
-#define CFG_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
+#define CONFIG_SYS_MEMTEST_START       0xa0400000      /* memtest works on     */
+#define CONFIG_SYS_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
 
-#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR           0xa2000000      /* default load address */
+#define CONFIG_SYS_LOAD_ADDR           0xa2000000      /* default load address */
 
-#define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Stack sizes
@@ -137,20 +137,20 @@
 #define PHYS_FLASH_2            0x04000000 /* Flash Bank #1 */
 #define PHYS_FLASH_SIZE         0x02000000 /* 32 MB */
 
-#define CFG_DRAM_BASE           0xa0000000
-#define CFG_DRAM_SIZE           0x04000000
+#define CONFIG_SYS_DRAM_BASE           0xa0000000
+#define CONFIG_SYS_DRAM_SIZE           0x04000000
 
-#define CFG_FLASH_BASE          PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
 /*
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS     1     /* max number of memory banks           */
-#define CFG_MAX_FLASH_SECT      32    /* max number of sectors on one chip    */
+#define CONFIG_SYS_MAX_FLASH_BANKS     1     /* max number of memory banks           */
+#define CONFIG_SYS_MAX_FLASH_SECT      32    /* max number of sectors on one chip    */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR				0x00020000	/* absolute address for now   */
@@ -254,38 +254,38 @@
  */
 /* Pin direction control */
 /* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */
-#define CFG_GPDR0_VAL       0xfff3bf02
-#define CFG_GPDR1_VAL       0xfbffbf83
-#define CFG_GPDR2_VAL       0x0001ffff
+#define CONFIG_SYS_GPDR0_VAL       0xfff3bf02
+#define CONFIG_SYS_GPDR1_VAL       0xfbffbf83
+#define CONFIG_SYS_GPDR2_VAL       0x0001ffff
 /* Set and Clear registers */
-#define CFG_GPSR0_VAL       0x00400800
-#define CFG_GPSR1_VAL       0x00000480
-#define CFG_GPSR2_VAL       0x00014000
-#define CFG_GPCR0_VAL       0x00000000
-#define CFG_GPCR1_VAL       0x00000000
-#define CFG_GPCR2_VAL       0x00000000
+#define CONFIG_SYS_GPSR0_VAL       0x00400800
+#define CONFIG_SYS_GPSR1_VAL       0x00000480
+#define CONFIG_SYS_GPSR2_VAL       0x00014000
+#define CONFIG_SYS_GPCR0_VAL       0x00000000
+#define CONFIG_SYS_GPCR1_VAL       0x00000000
+#define CONFIG_SYS_GPCR2_VAL       0x00000000
 /* Edge detect registers (these are set by the kernel) */
-#define CFG_GRER0_VAL       0x00000000
-#define CFG_GRER1_VAL       0x00000000
-#define CFG_GRER2_VAL       0x00000000
-#define CFG_GFER0_VAL       0x00000000
-#define CFG_GFER1_VAL       0x00000000
-#define CFG_GFER2_VAL       0x00000000
+#define CONFIG_SYS_GRER0_VAL       0x00000000
+#define CONFIG_SYS_GRER1_VAL       0x00000000
+#define CONFIG_SYS_GRER2_VAL       0x00000000
+#define CONFIG_SYS_GFER0_VAL       0x00000000
+#define CONFIG_SYS_GFER1_VAL       0x00000000
+#define CONFIG_SYS_GFER2_VAL       0x00000000
 /* Alternate function registers */
-#define CFG_GAFR0_L_VAL     0x00000000
-#define CFG_GAFR0_U_VAL     0x00000010
-#define CFG_GAFR1_L_VAL     0x900a9550
-#define CFG_GAFR1_U_VAL     0x00000008
-#define CFG_GAFR2_L_VAL     0x20000000
-#define CFG_GAFR2_U_VAL     0x00000002
+#define CONFIG_SYS_GAFR0_L_VAL     0x00000000
+#define CONFIG_SYS_GAFR0_U_VAL     0x00000010
+#define CONFIG_SYS_GAFR1_L_VAL     0x900a9550
+#define CONFIG_SYS_GAFR1_U_VAL     0x00000008
+#define CONFIG_SYS_GAFR2_L_VAL     0x20000000
+#define CONFIG_SYS_GAFR2_U_VAL     0x00000002
 
 /*
  * Clocks, power control and interrupts
  */
-#define CFG_PSSR_VAL        0x00000020
-#define CFG_CCCR_VAL        0x00000141  /* 100 MHz memory, 200 MHz CPU  */
-#define CFG_CKEN_VAL        0x00000060  /* FFUART and STUART enabled    */
-#define CFG_ICMR_VAL        0x00000000  /* No interrupts enabled        */
+#define CONFIG_SYS_PSSR_VAL        0x00000020
+#define CONFIG_SYS_CCCR_VAL        0x00000141  /* 100 MHz memory, 200 MHz CPU  */
+#define CONFIG_SYS_CKEN_VAL        0x00000060  /* FFUART and STUART enabled    */
+#define CONFIG_SYS_ICMR_VAL        0x00000000  /* No interrupts enabled        */
 
 /* FIXME
  *
@@ -300,30 +300,30 @@
  * FIXME Can ethernet be burst read and/or write?? This is set for lubbock
  *       Verify timings on all
  */
-#define CFG_MSC0_VAL        0x000023FA  /* flash bank    (cs0)   */
-/*#define CFG_MSC1_VAL        0x00003549  / * SuperIO bank  (cs2)   */
-#define CFG_MSC1_VAL        0x0000354c  /* SuperIO bank  (cs2)   */
-#define CFG_MSC2_VAL        0x00001224  /* Ethernet bank (cs4)   */
+#define CONFIG_SYS_MSC0_VAL        0x000023FA  /* flash bank    (cs0)   */
+/*#define CONFIG_SYS_MSC1_VAL        0x00003549  / * SuperIO bank  (cs2)   */
+#define CONFIG_SYS_MSC1_VAL        0x0000354c  /* SuperIO bank  (cs2)   */
+#define CONFIG_SYS_MSC2_VAL        0x00001224  /* Ethernet bank (cs4)   */
 #ifdef REDBOOT_WAY
-#define CFG_MDCNFG_VAL      0x00001aa1  /* FIXME can DTC be 01?     */
-#define CFG_MDMRS_VAL       0x00000000
-#define CFG_MDREFR_VAL      0x00018018
+#define CONFIG_SYS_MDCNFG_VAL      0x00001aa1  /* FIXME can DTC be 01?     */
+#define CONFIG_SYS_MDMRS_VAL       0x00000000
+#define CONFIG_SYS_MDREFR_VAL      0x00018018
 #else
-#define CFG_MDCNFG_VAL      0x00001aa1  /* FIXME can DTC be 01?     */
-#define CFG_MDMRS_VAL       0x00000000
-#define CFG_MDREFR_VAL      0x00403018  /* Initial setting, individual bits set in lowlevel_init.S */
+#define CONFIG_SYS_MDCNFG_VAL      0x00001aa1  /* FIXME can DTC be 01?     */
+#define CONFIG_SYS_MDMRS_VAL       0x00000000
+#define CONFIG_SYS_MDREFR_VAL      0x00403018  /* Initial setting, individual bits set in lowlevel_init.S */
 #endif
 
 /*
  * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
  */
-#define CFG_MECR_VAL          0x00000000
-#define CFG_MCMEM0_VAL        0x00010504
-#define CFG_MCMEM1_VAL        0x00010504
-#define CFG_MCATT0_VAL        0x00010504
-#define CFG_MCATT1_VAL        0x00010504
-#define CFG_MCIO0_VAL         0x00004715
-#define CFG_MCIO1_VAL         0x00004715
+#define CONFIG_SYS_MECR_VAL          0x00000000
+#define CONFIG_SYS_MCMEM0_VAL        0x00010504
+#define CONFIG_SYS_MCMEM1_VAL        0x00010504
+#define CONFIG_SYS_MCATT0_VAL        0x00010504
+#define CONFIG_SYS_MCATT1_VAL        0x00010504
+#define CONFIG_SYS_MCIO0_VAL         0x00004715
+#define CONFIG_SYS_MCIO1_VAL         0x00004715
 
 /* Board specific defines */
 
diff --git a/include/configs/csb226.h b/include/configs/csb226.h
index 266e0e6..d65c14a 100644
--- a/include/configs/csb226.h
+++ b/include/configs/csb226.h
@@ -78,7 +78,7 @@
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_NET
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_RUN
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_ECHO
@@ -111,38 +111,38 @@
  * used for the RAM copy of the uboot code
  *
  */
-#define CFG_MALLOC_LEN		(128*1024)
-#define CFG_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
 
-#define CFG_LONGHELP				/* undef to save memory         */
-#define CFG_PROMPT		"uboot> "	/* Monitor Command Prompt       */
-#define CFG_CBSIZE		128		/* Console I/O Buffer Size      */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory         */
+#define CONFIG_SYS_PROMPT		"uboot> "	/* Monitor Command Prompt       */
+#define CONFIG_SYS_CBSIZE		128		/* Console I/O Buffer Size      */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START	0xa0400000      /* memtest works on     */
-#define CFG_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
+#define CONFIG_SYS_MEMTEST_START	0xa0400000      /* memtest works on     */
+#define CONFIG_SYS_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
 
-#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR           0xa3000000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR           0xa3000000	/* default load address */
 						/* RS: where is this documented? */
 						/* RS: is this where U-Boot is  */
 						/* RS: relocated to in RAM?      */
 
-#define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ			1000
 						/* RS: the oscillator is actually 3680130?? */
-#define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
+#define CONFIG_SYS_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
 						/* 0101000001 */
 						/*      ^^^^^ Memory Speed 99.53 MHz         */
 						/*    ^^      Run Mode Speed = 2x Mem Speed  */
 						/* ^^         Turbo Mode Sp. = 1x Run M. Sp. */
 
-#define CFG_MONITOR_LEN		0x20000		/* 128 KiB */
+#define CONFIG_SYS_MONITOR_LEN		0x20000		/* 128 KiB */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Network chip
@@ -172,10 +172,10 @@
 #define PHYS_FLASH_1		0x00000000	/* Flash Bank #1            */
 #define PHYS_FLASH_SIZE		0x02000000	/* 32 MB                    */
 
-#define CFG_DRAM_BASE		0xa0000000	/* RAM starts here          */
-#define CFG_DRAM_SIZE		0x02000000
+#define CONFIG_SYS_DRAM_BASE		0xa0000000	/* RAM starts here          */
+#define CONFIG_SYS_DRAM_SIZE		0x02000000
 
-#define CFG_FLASH_BASE          PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
 # if 0
 /* FIXME: switch to _documented_ registers */
@@ -196,9 +196,9 @@
  * GP79 == nCS3      is 1
  * GP80 == nCS4      is 1
  */
-#define CFG_GPSR0_VAL       0x03008000
-#define CFG_GPSR1_VAL       0xC0028282
-#define CFG_GPSR2_VAL       0x0001C000
+#define CONFIG_SYS_GPSR0_VAL       0x03008000
+#define CONFIG_SYS_GPSR1_VAL       0xC0028282
+#define CONFIG_SYS_GPSR2_VAL       0x0001C000
 
 /* GP02 == DON_RST   is 0
  * GP23 == SCLK      is 0
@@ -207,9 +207,9 @@
  * GP61 == LED_A     is 0
  * GP73 == SWUPD_LED is 0
  */
-#define CFG_GPCR0_VAL       0x00800004
-#define CFG_GPCR1_VAL       0x30002000
-#define CFG_GPCR2_VAL       0x00000100
+#define CONFIG_SYS_GPCR0_VAL       0x00800004
+#define CONFIG_SYS_GPCR1_VAL       0x30002000
+#define CONFIG_SYS_GPCR2_VAL       0x00000100
 
 /* GP00 == DON_READY is input
  * GP01 == DON_OK    is input
@@ -254,9 +254,9 @@
  * GP79 == nCS3      is output
  * GP80 == nCS4      is output
  */
-#define CFG_GPDR0_VAL       0x03808004
-#define CFG_GPDR1_VAL       0xF002A282
-#define CFG_GPDR2_VAL       0x0001C200
+#define CONFIG_SYS_GPDR0_VAL       0x03808004
+#define CONFIG_SYS_GPDR1_VAL       0xF002A282
+#define CONFIG_SYS_GPDR2_VAL       0x0001C200
 
 /* GP15 == nCS1  is AF10
  * GP18 == RDY   is AF01
@@ -276,12 +276,12 @@
  * GP79 == nCS3  is AF10
  * GP80 == nCS4  is AF10
  */
-#define CFG_GAFR0_L_VAL     0x80000000
-#define CFG_GAFR0_U_VAL     0x001A8010
-#define CFG_GAFR1_L_VAL     0x60088058
-#define CFG_GAFR1_U_VAL     0x00000008
-#define CFG_GAFR2_L_VAL     0xA0000000
-#define CFG_GAFR2_U_VAL     0x00000002
+#define CONFIG_SYS_GAFR0_L_VAL     0x80000000
+#define CONFIG_SYS_GAFR0_U_VAL     0x001A8010
+#define CONFIG_SYS_GAFR1_L_VAL     0x60088058
+#define CONFIG_SYS_GAFR1_U_VAL     0x00000008
+#define CONFIG_SYS_GAFR2_L_VAL     0xA0000000
+#define CONFIG_SYS_GAFR2_U_VAL     0x00000002
 
 
 /* FIXME: set GPIO_RER/FER */
@@ -292,7 +292,7 @@
  * BFS = 1
  * SSS = 1
  */
-#define CFG_PSSR_VAL		0x37
+#define CONFIG_SYS_PSSR_VAL		0x37
 
 /*
  * Memory settings
@@ -313,7 +313,7 @@
  * [03]    1    - 16 Bit bus width
  * [02:00] 000  - nonburst RAM or FLASH
  */
-#define CFG_MSC0_VAL		0x25b825b8 /* flash banks                   */
+#define CONFIG_SYS_MSC0_VAL		0x25b825b8 /* flash banks                   */
 
 /* This is the configuration for nCS2/3 -> TDM-Switch, DSP
  * configuration for nCS3: DSP
@@ -331,7 +331,7 @@
  * [03]    1    - 16 Bit bus width
  * [02:00] 100  - variable latency I/O
  */
-#define CFG_MSC1_VAL		0x123C593C /* TDM switch, DSP               */
+#define CONFIG_SYS_MSC1_VAL		0x123C593C /* TDM switch, DSP               */
 
 /* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
  *
@@ -350,7 +350,7 @@
  * [03]    1    - 16 Bit bus width
  * [02:00] 100  - variable latency I/O
  */
-#define CFG_MSC2_VAL		0x123C6CDC /* extra bus, LAN controller     */
+#define CONFIG_SYS_MSC2_VAL		0x123C6CDC /* extra bus, LAN controller     */
 
 /* MDCNFG: SDRAM Configuration Register
  *
@@ -378,7 +378,7 @@
  * [00]      1   - enable  SDRAM partition 0
  */
 /* use the configuration above but disable partition 0 */
-#define CFG_MDCNFG_VAL		0x000019c8
+#define CONFIG_SYS_MDCNFG_VAL		0x000019c8
 
 /* MDREFR: SDRAM Refresh Control Register
  *
@@ -399,7 +399,7 @@
  * [12]    1     - E0PIN: disable SDCKE0
  * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
  */
-#define CFG_MDREFR_VAL		0x0081D018
+#define CONFIG_SYS_MDREFR_VAL		0x0081D018
 
 /* MDMRS: Mode Register Set Configuration Register
  *
@@ -414,64 +414,64 @@
  * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
  * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
  */
-#define CFG_MDMRS_VAL		0x00020022
+#define CONFIG_SYS_MDMRS_VAL		0x00020022
 
 /*
  * PCMCIA and CF Interfaces
  */
-#define CFG_MECR_VAL		0x00000000
-#define CFG_MCMEM0_VAL		0x00000000
-#define CFG_MCMEM1_VAL		0x00000000
-#define CFG_MCATT0_VAL		0x00000000
-#define CFG_MCATT1_VAL		0x00000000
-#define CFG_MCIO0_VAL		0x00000000
-#define CFG_MCIO1_VAL		0x00000000
+#define CONFIG_SYS_MECR_VAL		0x00000000
+#define CONFIG_SYS_MCMEM0_VAL		0x00000000
+#define CONFIG_SYS_MCMEM1_VAL		0x00000000
+#define CONFIG_SYS_MCATT0_VAL		0x00000000
+#define CONFIG_SYS_MCATT1_VAL		0x00000000
+#define CONFIG_SYS_MCIO0_VAL		0x00000000
+#define CONFIG_SYS_MCIO1_VAL		0x00000000
 #endif
 
 /*
  * GPIO settings
  */
-#define CFG_GPSR0_VAL		0xFFFFFFFF
-#define CFG_GPSR1_VAL		0xFFFFFFFF
-#define CFG_GPSR2_VAL		0xFFFFFFFF
-#define CFG_GPCR0_VAL		0x08022080
-#define CFG_GPCR1_VAL		0x00000000
-#define CFG_GPCR2_VAL		0x00000000
-#define CFG_GPDR0_VAL		0xCD82A878
-#define CFG_GPDR1_VAL		0xFCFFAB80
-#define CFG_GPDR2_VAL		0x0001FFFF
-#define CFG_GAFR0_L_VAL		0x80000000
-#define CFG_GAFR0_U_VAL		0xA5254010
-#define CFG_GAFR1_L_VAL		0x599A9550
-#define CFG_GAFR1_U_VAL		0xAAA5AAAA
-#define CFG_GAFR2_L_VAL		0xAAAAAAAA
-#define CFG_GAFR2_U_VAL		0x00000002
+#define CONFIG_SYS_GPSR0_VAL		0xFFFFFFFF
+#define CONFIG_SYS_GPSR1_VAL		0xFFFFFFFF
+#define CONFIG_SYS_GPSR2_VAL		0xFFFFFFFF
+#define CONFIG_SYS_GPCR0_VAL		0x08022080
+#define CONFIG_SYS_GPCR1_VAL		0x00000000
+#define CONFIG_SYS_GPCR2_VAL		0x00000000
+#define CONFIG_SYS_GPDR0_VAL		0xCD82A878
+#define CONFIG_SYS_GPDR1_VAL		0xFCFFAB80
+#define CONFIG_SYS_GPDR2_VAL		0x0001FFFF
+#define CONFIG_SYS_GAFR0_L_VAL		0x80000000
+#define CONFIG_SYS_GAFR0_U_VAL		0xA5254010
+#define CONFIG_SYS_GAFR1_L_VAL		0x599A9550
+#define CONFIG_SYS_GAFR1_U_VAL		0xAAA5AAAA
+#define CONFIG_SYS_GAFR2_L_VAL		0xAAAAAAAA
+#define CONFIG_SYS_GAFR2_U_VAL		0x00000002
 
 /* FIXME: set GPIO_RER/FER */
 
-#define CFG_PSSR_VAL        0x20
+#define CONFIG_SYS_PSSR_VAL        0x20
 
 /*
  * Memory settings
  */
 
-#define CFG_MSC0_VAL            0x2ef15af0
-#define CFG_MSC1_VAL            0x00003ff4
-#define CFG_MSC2_VAL            0x7ff07ff0
-#define CFG_MDCNFG_VAL          0x09a909a9
-#define CFG_MDREFR_VAL          0x038ff030
-#define CFG_MDMRS_VAL           0x00220022
+#define CONFIG_SYS_MSC0_VAL            0x2ef15af0
+#define CONFIG_SYS_MSC1_VAL            0x00003ff4
+#define CONFIG_SYS_MSC2_VAL            0x7ff07ff0
+#define CONFIG_SYS_MDCNFG_VAL          0x09a909a9
+#define CONFIG_SYS_MDREFR_VAL          0x038ff030
+#define CONFIG_SYS_MDMRS_VAL           0x00220022
 
 /*
  * PCMCIA and CF Interfaces
  */
-#define CFG_MECR_VAL        0x00000000
-#define CFG_MCMEM0_VAL      0x00000000
-#define CFG_MCMEM1_VAL      0x00000000
-#define CFG_MCATT0_VAL      0x00000000
-#define CFG_MCATT1_VAL      0x00000000
-#define CFG_MCIO0_VAL       0x00000000
-#define CFG_MCIO1_VAL       0x00000000
+#define CONFIG_SYS_MECR_VAL        0x00000000
+#define CONFIG_SYS_MCMEM0_VAL      0x00000000
+#define CONFIG_SYS_MCMEM1_VAL      0x00000000
+#define CONFIG_SYS_MCATT0_VAL      0x00000000
+#define CONFIG_SYS_MCATT1_VAL      0x00000000
+#define CONFIG_SYS_MCIO0_VAL       0x00000000
+#define CONFIG_SYS_MCIO1_VAL       0x00000000
 
 #define CSB226_USER_LED0	0x00000008
 #define CSB226_USER_LED1	0x00000010
@@ -481,12 +481,12 @@
 /*
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS     1	/* max number of memory banks       */
-#define CFG_MAX_FLASH_SECT	128	/* max number of sect. on one chip  */
+#define CONFIG_SYS_MAX_FLASH_BANKS     1	/* max number of memory banks       */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sect. on one chip  */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase       */
-#define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write       */
+#define CONFIG_SYS_FLASH_ERASE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase       */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Write       */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR            (PHYS_FLASH_1 + 0x1C000)
diff --git a/include/configs/csb272.h b/include/configs/csb272.h
index 13892e6..5d3b09a 100644
--- a/include/configs/csb272.h
+++ b/include/configs/csb272.h
@@ -105,7 +105,7 @@
  *
  */
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 /*
  * KGDB Configuration
@@ -120,36 +120,36 @@
  * Miscellaneous configurable options
  *
  */
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser */
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "	/* hush shell secondary prompt */
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser */
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "	/* hush shell secondary prompt */
 #endif
 
-#define CFG_LONGHELP			/* undef to save memory	*/
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-#define CFG_CLKS_IN_HZ		1	/* everything, incl board info, in Hz */
-#define CFG_EXTBDINFO		1	/* To use extended board_info (bd_t) */
-#define CFG_LOAD_ADDR		0x100000 /* default load address */
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define CONFIG_SYS_CLKS_IN_HZ		1	/* everything, incl board info, in Hz */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_info (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000 /* default load address */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*
  * watchdog configuration
@@ -161,11 +161,10 @@
  * UART configuration
  *
  */
-#define CFG_EXT_SERIAL_CLOCK	3868400	/* use external serial clock */
-#undef  CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59 */
-#undef  CFG_BASE_BAUD
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	3868400	/* use external serial clock */
+#undef  CONFIG_SYS_BASE_BAUD
 #define CONFIG_BAUDRATE		38400	/* Default baud rate */
-#define CFG_BAUDRATE_TABLE      \
+#define CONFIG_SYS_BAUDRATE_TABLE      \
     { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*
@@ -173,13 +172,14 @@
  *
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#define CFG_I2C_SPEED		100000	/* I2C speed			*/
-#define CFG_I2C_SLAVE		0x7F	/* I2C slave address		*/
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed			*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave address		*/
 
 /*
  * MII PHY configuration
  *
  */
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_PHY_CMD_DELAY	40	/* PHY COMMAND delay		*/
@@ -209,14 +209,14 @@
 #undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
-#define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
+#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0x00000000      /* disabled                     */
+#define CONFIG_SYS_PCI_PTM2MS  0x00000000      /* disabled                     */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 
 /*
  * IDE stuff
@@ -239,17 +239,17 @@
  *
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFE000000
-#define CFG_FLASH_SIZE		0x02000000
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 KB for Monitor */
-#define CFG_MALLOC_LEN		(128 * 1024) /* Reserve 128 KB for malloc() */
-
-#if CFG_MONITOR_BASE < CFG_FLASH_BASE
-#define CFG_RAMSTART
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_SIZE		0x02000000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 KB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* Reserve 128 KB for malloc() */
+
+#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_RAMSTART
 #endif
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
@@ -263,37 +263,37 @@
  * FLASH Device configuration
  *
  */
-#define CFG_FLASH_CFI		1	/* flash is CFI conformant	*/
+#define CONFIG_SYS_FLASH_CFI		1	/* flash is CFI conformant	*/
 #define CONFIG_FLASH_CFI_DRIVER	1	/* use common cfi driver	*/
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
-#define CFG_MAX_FLASH_BANKS	1	/* max # of memory banks	*/
-#define CFG_FLASH_INCREMENT	0	/* there is only one bank	*/
-#define CFG_MAX_FLASH_SECT	128	/* max # of sectors on one chip	*/
-#define CFG_FLASH_PROTECTION	1	/* hardware flash protection	*/
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max # of memory banks	*/
+#define CONFIG_SYS_FLASH_INCREMENT	0	/* there is only one bank	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max # of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware flash protection	*/
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 
 /*
  * On Chip Memory location/size
  *
  */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 
 /*
  * Global info and initial stack
  *
  */
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE	128 /* byte size reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	128 /* byte size reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Miscellaneous board specific definitions
  *
  */
-#define CFG_I2C_PLL_ADDR	0x58	/* I2C address of AMIS FS6377-01 PLL */
+#define CONFIG_SYS_I2C_PLL_ADDR	0x58	/* I2C address of AMIS FS6377-01 PLL */
 #define CONFIG_I2CFAST		1	/* enable "i2cfast" env. setting     */
 
 /*
diff --git a/include/configs/csb472.h b/include/configs/csb472.h
index 0644982..a33efde 100644
--- a/include/configs/csb472.h
+++ b/include/configs/csb472.h
@@ -104,7 +104,7 @@
  *
  */
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 /*
  * KGDB Configuration
@@ -119,36 +119,36 @@
  * Miscellaneous configurable options
  *
  */
-#undef	CFG_HUSH_PARSER			/* use "hush" command parser */
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "	/* hush shell secondary prompt */
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser */
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "	/* hush shell secondary prompt */
 #endif
 
-#define CFG_LONGHELP			/* undef to save memory	*/
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-#define CFG_CLKS_IN_HZ		1	/* everything, incl board info, in Hz */
-#define CFG_EXTBDINFO		1	/* To use extended board_info (bd_t) */
-#define CFG_LOAD_ADDR		0x100000 /* default load address */
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define CONFIG_SYS_CLKS_IN_HZ		1	/* everything, incl board info, in Hz */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_info (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000 /* default load address */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*
  * watchdog configuration
@@ -160,11 +160,10 @@
  * UART configuration
  *
  */
-#undef CFG_EXT_SERIAL_CLOCK		/* use internal serial clock */
-#undef  CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59 */
-#define CFG_BASE_BAUD		691200
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK		/* use internal serial clock */
+#define CONFIG_SYS_BASE_BAUD		691200
 #define CONFIG_BAUDRATE		38400	/* Default baud rate */
-#define CFG_BAUDRATE_TABLE      \
+#define CONFIG_SYS_BAUDRATE_TABLE      \
     { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*
@@ -172,13 +171,14 @@
  *
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#define CFG_I2C_SPEED		100000	/* I2C speed			*/
-#define CFG_I2C_SLAVE		0x7F	/* I2C slave address		*/
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed			*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave address		*/
 
 /*
  * MII PHY configuration
  *
  */
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_PHY_CMD_DELAY	40	/* PHY COMMAND delay		*/
@@ -208,14 +208,14 @@
 #undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
-#define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
+#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0x00000000      /* disabled                     */
+#define CONFIG_SYS_PCI_PTM2MS  0x00000000      /* disabled                     */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 
 /*
  * IDE stuff
@@ -238,17 +238,17 @@
  *
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFF800000
-#define CFG_FLASH_SIZE		0x00800000
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 KB for Monitor */
-#define CFG_MALLOC_LEN		(128 * 1024) /* Reserve 128 KB for malloc() */
-
-#if CFG_MONITOR_BASE < CFG_FLASH_BASE
-#define CFG_RAMSTART
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF800000
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 KB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* Reserve 128 KB for malloc() */
+
+#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_RAMSTART
 #endif
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
@@ -262,31 +262,31 @@
  * FLASH Device configuration
  *
  */
-#define CFG_FLASH_CFI		1	/* flash is CFI conformant	*/
+#define CONFIG_SYS_FLASH_CFI		1	/* flash is CFI conformant	*/
 #define CONFIG_FLASH_CFI_DRIVER	1	/* use common cfi driver	*/
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
-#define CFG_MAX_FLASH_BANKS	1	/* max # of memory banks	*/
-#define CFG_FLASH_INCREMENT	0	/* there is only one bank	*/
-#define CFG_MAX_FLASH_SECT	64	/* max # of sectors on one chip	*/
-#define CFG_FLASH_PROTECTION	1	/* hardware flash protection	*/
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max # of memory banks	*/
+#define CONFIG_SYS_FLASH_INCREMENT	0	/* there is only one bank	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max # of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware flash protection	*/
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 
 /*
  * On Chip Memory location/size
  *
  */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 
 /*
  * Global info and initial stack
  *
  */
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE	128 /* byte size reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	128 /* byte size reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Miscellaneous board specific definitions
diff --git a/include/configs/csb637.h b/include/configs/csb637.h
index 0760084..761c0dc 100644
--- a/include/configs/csb637.h
+++ b/include/configs/csb637.h
@@ -43,45 +43,47 @@
 #define CONFIG_INITRD_TAG	1
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#define CFG_USE_MAIN_OSCILLATOR		1
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR		1
 /* flash */
-#define MC_PUIA_VAL	0x00000000
-#define MC_PUP_VAL	0x00000000
-#define MC_PUER_VAL	0x00000000
-#define MC_ASR_VAL	0x00000000
-#define MC_AASR_VAL	0x00000000
-#define EBI_CFGR_VAL	0x00000000
-#define SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define CONFIG_SYS_MC_PUIA_VAL	0x00000000
+#define CONFIG_SYS_MC_PUP_VAL	0x00000000
+#define CONFIG_SYS_MC_PUER_VAL	0x00000000
+#define CONFIG_SYS_MC_ASR_VAL	0x00000000
+#define CONFIG_SYS_MC_AASR_VAL	0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
-#define PLLAR_VAL	0x2031BE01 /* 184.320000 MHz for PCK */
-#define PLLBR_VAL	0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */
-#define MCKR_VAL	0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */
+#define CONFIG_SYS_PLLAR_VAL	0x2031BE01 /* 184.320000 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL	0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */
+#define CONFIG_SYS_MCKR_VAL	0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */
 
 /* sdram */
-#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR_VAL	0x00000000
-#define PIOC_PDR_VAL	0xFFFF0000
-#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
-#define SDRC_CR_VAL	0x21914159 /* set up the SDRAM */
-#define SDRAM		0x20000000 /* address of the SDRAM */
-#define SDRAM1		0x20000080 /* address of the SDRAM */
-#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
-#define SDRC_MR_VAL	0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1	0x00000004 /* refresh */
-#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
-#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL	0x21914159 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM	0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1	0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#else
+#define CONFIG_SKIP_RELOCATE_UBOOT
 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 #define CONFIG_BAUDRATE 115200
 
-#define CFG_AT91C_BRGR_DIVISOR	75	/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
+#define CONFIG_SYS_AT91C_BRGR_DIVISOR	75	/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
 
 /*
  * Hardware drivers
@@ -120,7 +122,7 @@
 
 #ifdef	NAND_SUPPORT_HAS_BEEN_FIXED	/* NAND support is broken / unimplemented */
 
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
 #define SECTORSIZE 512
 
 #define ADDR_COLUMN 1
@@ -129,7 +131,6 @@
 
 #define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
 
 #define AT91_SMART_MEDIA_ALE (1 << 22)	/* our ALE is AD22 */
 #define AT91_SMART_MEDIA_CLE (1 << 21)	/* our CLE is AD21 */
@@ -156,46 +157,46 @@
 #define PHYS_SDRAM			0x20000000
 #define PHYS_SDRAM_SIZE			0x4000000  /* 64 megs */
 
-#define CFG_MEMTEST_START		PHYS_SDRAM
-#define CFG_MEMTEST_END			CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 512*1024 - 4
-#define CFG_ALT_MEMTEST			1
-#define CFG_MEMTEST_SCRATCH		CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 4
+#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END			CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512*1024 - 4
+#define CONFIG_SYS_ALT_MEMTEST			1
+#define CONFIG_SYS_MEMTEST_SCRATCH		CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 4
 
 #define CONFIG_DRIVER_ETHER
 #define CONFIG_NET_RETRY_COUNT		20
 #undef CONFIG_AT91C_USE_RMII
 
 #undef CONFIG_HAS_DATAFLASH
-#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
-#define CFG_MAX_DATAFLASH_BANKS		0
-#define CFG_MAX_DATAFLASH_PAGES		16384
-#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* Logical adress for CS0 */
-#define CFG_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* Logical adress for CS3 */
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		0
+#define CONFIG_SYS_MAX_DATAFLASH_PAGES		16384
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* Logical adress for CS0 */
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* Logical adress for CS3 */
 
 /*
  * FLASH Device configuration
  */
 #define PHYS_FLASH_1			0x10000000
 #define PHYS_FLASH_SIZE			0x800000  /* 8 megs main flash */
-#define CFG_FLASH_BASE			PHYS_FLASH_1
-#define CFG_FLASH_CFI		1	/* flash is CFI conformant	*/
+#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_CFI		1	/* flash is CFI conformant	*/
 #define CONFIG_FLASH_CFI_DRIVER	1	/* use common cfi driver	*/
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
-#define CFG_MAX_FLASH_BANKS	1	/* max # of memory banks	*/
-#define CFG_FLASH_INCREMENT	0	/* there is only one bank	*/
-#define CFG_FLASH_PROTECTION	1	/* hardware flash protection	*/
-#define CFG_MAX_FLASH_SECT		64
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max # of memory banks	*/
+#define CONFIG_SYS_FLASH_INCREMENT	0	/* there is only one bank	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware flash protection	*/
+#define CONFIG_SYS_MAX_FLASH_SECT		64
 
-#define CFG_JFFS2_FIRST_BANK	0
-#define CFG_JFFS2_FIRST_SECTOR	3
-#define CFG_JFFS2_NUM_BANKS	1
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR	3
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
 
 #undef	CONFIG_ENV_IS_IN_DATAFLASH
 
 #ifdef CONFIG_ENV_IS_IN_DATAFLASH
 #define CONFIG_ENV_OFFSET			0x20000
-#define CONFIG_ENV_ADDR			(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_SIZE			0x2000  /* 0x8000 */
 #else
 #define CONFIG_ENV_IS_IN_FLASH		1
@@ -204,17 +205,17 @@
 #endif	/* CONFIG_ENV_IS_IN_DATAFLASH */
 
 
-#define CFG_LOAD_ADDR		0x21000000  /* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
 
-#define CFG_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
 
-#define CFG_PROMPT		"U-Boot> "	/* Monitor Command Prompt */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_PROMPT		"U-Boot> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 
-#define CFG_HZ 1000
-#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2	/* AT91C_TC0_CMR is implicitly set to */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2	/* AT91C_TC0_CMR is implicitly set to */
 						/* AT91C_TC_TIMER_DIV1_CLOCK */
 
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index ae2f6a5..667c0d8 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -50,31 +50,31 @@
 /* Board */
 /*=======*/
 #define DV_EVM
-#define CFG_NAND_SMALLPAGE
-#define CFG_USE_NOR
+#define CONFIG_SYS_NAND_SMALLPAGE
+#define CONFIG_SYS_USE_NOR
 /*===================*/
 /* SoC Configuration */
 /*===================*/
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
 #define CONFIG_SYS_CLK_FREQ	297000000	/* Arm Clock frequency */
-#define CFG_TIMERBASE		0x01c21400	/* use timer 0 */
-#define CFG_HZ_CLOCK		27000000	/* Timer Input clock freq */
-#define CFG_HZ			1000
+#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
+#define CONFIG_SYS_HZ			1000
 /*====================================================*/
 /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
 /* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */
 /*====================================================*/
-#define CFG_I2C_EEPROM_ADDR_LEN		2
-#define CFG_I2C_EEPROM_ADDR		0x50
-#define CFG_EEPROM_PAGE_WRITE_BITS	6
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
 /*=============*/
 /* Memory Info */
 /*=============*/
-#define CFG_MALLOC_LEN		(0x10000 + 128*1024)	/* malloc() len */
-#define CFG_GBL_DATA_SIZE	128		/* reserved for initial data */
-#define CFG_MEMTEST_START	0x80000000	/* memtest start address */
-#define CFG_MEMTEST_END		0x81000000	/* 16MB RAM test */
+#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 128*1024)	/* malloc() len */
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* reserved for initial data */
+#define CONFIG_SYS_MEMTEST_START	0x80000000	/* memtest start address */
+#define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
 #define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
 #define CONFIG_STACKSIZE	(256*1024)	/* regular stack */
 #define PHYS_SDRAM_1		0x80000000	/* DDR Start */
@@ -83,21 +83,21 @@
 /*====================*/
 /* Serial Driver info */
 /*====================*/
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	4		/* NS16550 register size */
-#define CFG_NS16550_COM1	0x01c20000	/* Base address of UART0 */
-#define CFG_NS16550_CLK		27000000	/* Input clock to NS16550 */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	4		/* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1	0x01c20000	/* Base address of UART0 */
+#define CONFIG_SYS_NS16550_CLK		27000000	/* Input clock to NS16550 */
 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
 #define CONFIG_BAUDRATE		115200		/* Default baud rate */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 /*===================*/
 /* I2C Configuration */
 /*===================*/
 #define CONFIG_HARD_I2C
 #define CONFIG_DRIVER_DAVINCI_I2C
-#define CFG_I2C_SPEED		80000	/* 100Kbps won't work, silicon bug */
-#define CFG_I2C_SLAVE		10	/* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C_SPEED		80000	/* 100Kbps won't work, silicon bug */
+#define CONFIG_SYS_I2C_SLAVE		10	/* Bogus, master-only in U-Boot */
 /*==================================*/
 /* Network & Ethernet Configuration */
 /*==================================*/
@@ -111,11 +111,11 @@
 /*=====================*/
 /* Flash & Environment */
 /*=====================*/
-#ifdef CFG_USE_NAND
+#ifdef CONFIG_SYS_USE_NAND
 #undef CONFIG_ENV_IS_IN_FLASH
-#define CFG_NO_FLASH
+#define CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
-#ifdef CFG_NAND_SMALLPAGE
+#ifdef CONFIG_SYS_NAND_SMALLPAGE
 #define CONFIG_ENV_SECT_SIZE	512	/* Env sector Size */
 #define CONFIG_ENV_SIZE		SZ_16K
 #else
@@ -124,13 +124,12 @@
 #endif
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
 #define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
-#define CFG_NAND_BASE		0x02000000
-#define CFG_NAND_HW_ECC
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
-#define NAND_MAX_CHIPS		1
+#define CONFIG_SYS_NAND_BASE		0x02000000
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
 #define CONFIG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
 #define DEF_BOOTM		""
-#elif defined(CFG_USE_NOR)
+#elif defined(CONFIG_SYS_USE_NOR)
 #ifdef CONFIG_NOR_UART_BOOT
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
 #define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
@@ -139,17 +138,17 @@
 #undef CONFIG_SKIP_RELOCATE_UBOOT
 #endif
 #define CONFIG_ENV_IS_IN_FLASH
-#undef CFG_NO_FLASH
+#undef CONFIG_SYS_NO_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_MAX_FLASH_BANKS	1		/* max number of flash banks */
-#define CFG_FLASH_SECT_SZ	0x10000		/* 64KB sect size AMD Flash */
-#define CONFIG_ENV_OFFSET		(CFG_FLASH_SECT_SZ*3)
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ	0x10000		/* 64KB sect size AMD Flash */
+#define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ*3)
 #define PHYS_FLASH_1		0x02000000	/* CS2 Base address	 */
-#define CFG_FLASH_BASE		PHYS_FLASH_1	/* Flash Base for U-Boot */
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1	/* Flash Base for U-Boot */
 #define PHYS_FLASH_SIZE		0x2000000	/* Flash size 32MB	 */
-#define CFG_MAX_FLASH_SECT	(PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
-#define CONFIG_ENV_SECT_SIZE	CFG_FLASH_SECT_SZ	/* Env sector Size */
+#define CONFIG_SYS_MAX_FLASH_SECT	(PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_FLASH_SECT_SZ	/* Env sector Size */
 #endif
 /*==============================*/
 /* U-Boot general configuration */
@@ -158,20 +157,22 @@
 #define CONFIG_MISC_INIT_R
 #undef CONFIG_BOOTDELAY
 #define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
-#define CFG_PROMPT		"U-Boot > "	/* Monitor Command Prompt */
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size  */
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print buffer sz */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_LOAD_ADDR		0x80700000	/* default Linux kernel load address */
+#define CONFIG_SYS_PROMPT		"U-Boot > "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print buffer sz */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR		0x80700000	/* default Linux kernel load address */
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_AUTO_COMPLETE		/* Won't work with hush so far, may be later */
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_CMDLINE_EDITING
-#define CFG_LONGHELP
+#define CONFIG_SYS_LONGHELP
 #define CONFIG_CRC32_VERIFY
 #define CONFIG_MX_CYCLIC
+#define CONFIG_MUSB_HCD
+#define CONFIG_USB_DAVINCI
 /*===================*/
 /* Linux Information */
 /*===================*/
@@ -195,14 +196,30 @@
 #undef CONFIG_CMD_BDI
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_SETGETDCR
-#ifdef CFG_USE_NAND
+#ifdef CONFIG_SYS_USE_NAND
 #undef CONFIG_CMD_FLASH
 #undef CONFIG_CMD_IMLS
 #define CONFIG_CMD_NAND
-#elif defined(CFG_USE_NOR)
+#elif defined(CONFIG_SYS_USE_NOR)
 #define CONFIG_CMD_JFFS2
 #else
-#error "Either CFG_USE_NAND or CFG_USE_NOR _MUST_ be defined !!!"
+#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
+#endif
+/*==========================*/
+/* USB MSC support (if any) */
+/*==========================*/
+#ifdef CONFIG_USB_DAVINCI
+#define CONFIG_CMD_USB
+#ifdef CONFIG_MUSB_HCD
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_STORAGE
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+#ifdef CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_PREBOOT "usb start"
+#endif
 #endif
 /*=======================*/
 /* KGDB support (if any) */
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index 016a897..22d3808 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -25,23 +25,23 @@
 /* Board */
 /*=======*/
 #define SCHMOOGIE
-#define CFG_NAND_LARGEPAGE
-#define CFG_USE_NAND
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_USE_NAND
 /*===================*/
 /* SoC Configuration */
 /*===================*/
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
 #define CONFIG_SYS_CLK_FREQ	297000000	/* Arm Clock frequency */
-#define CFG_TIMERBASE		0x01c21400	/* use timer 0 */
-#define CFG_HZ_CLOCK		27000000	/* Timer Input clock freq */
-#define CFG_HZ			1000
+#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
+#define CONFIG_SYS_HZ			1000
 /*=============*/
 /* Memory Info */
 /*=============*/
-#define CFG_MALLOC_LEN		(0x10000 + 256*1024)	/* malloc() len */
-#define CFG_GBL_DATA_SIZE	128		/* reserved for initial data */
-#define CFG_MEMTEST_START	0x80000000	/* memtest start address */
-#define CFG_MEMTEST_END		0x81000000	/* 16MB RAM test */
+#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 256*1024)	/* malloc() len */
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* reserved for initial data */
+#define CONFIG_SYS_MEMTEST_START	0x80000000	/* memtest start address */
+#define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
 #define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
 #define CONFIG_STACKSIZE	(256*1024)	/* regular stack */
 #define PHYS_SDRAM_1		0x80000000	/* DDR Start */
@@ -50,21 +50,21 @@
 /*====================*/
 /* Serial Driver info */
 /*====================*/
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	4		/* NS16550 register size */
-#define CFG_NS16550_COM1	0x01c20000	/* Base address of UART0 */
-#define CFG_NS16550_CLK		27000000	/* Input clock to NS16550 */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	4		/* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1	0x01c20000	/* Base address of UART0 */
+#define CONFIG_SYS_NS16550_CLK		27000000	/* Input clock to NS16550 */
 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
 #define CONFIG_BAUDRATE		115200		/* Default baud rate */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 /*===================*/
 /* I2C Configuration */
 /*===================*/
 #define CONFIG_HARD_I2C
 #define CONFIG_DRIVER_DAVINCI_I2C
-#define CFG_I2C_SPEED		80000	/* 100Kbps won't work, silicon bug */
-#define CFG_I2C_SLAVE		10	/* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C_SPEED		80000	/* 100Kbps won't work, silicon bug */
+#define CONFIG_SYS_I2C_SLAVE		10	/* Bogus, master-only in U-Boot */
 /*==================================*/
 /* Network & Ethernet Configuration */
 /*==================================*/
@@ -80,25 +80,24 @@
 /* Flash & Environment */
 /*=====================*/
 #undef CONFIG_ENV_IS_IN_FLASH
-#define CFG_NO_FLASH
+#define CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
 #define CONFIG_ENV_SECT_SIZE	2048	/* Env sector Size */
 #define CONFIG_ENV_SIZE		SZ_128K
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
 #define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
-#define CFG_NAND_BASE		0x02000000
-#define CFG_NAND_HW_ECC
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
-#define NAND_MAX_CHIPS		1
+#define CONFIG_SYS_NAND_BASE		0x02000000
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
 #define CONFIG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
 /*=====================*/
 /* Board related stuff */
 /*=====================*/
 #define CONFIG_RTC_DS1307		/* RTC chip on SCHMOOGIE */
-#define CFG_I2C_RTC_ADDR	0x6f	/* RTC chip I2C address */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x6f	/* RTC chip I2C address */
 #define CONFIG_HAS_UID
 #define CONFIG_UID_DS28CM00		/* Unique ID on SCHMOOGIE */
-#define CFG_UID_ADDR		0x50	/* UID chip I2C address */
+#define CONFIG_SYS_UID_ADDR		0x50	/* UID chip I2C address */
 /*==============================*/
 /* U-Boot general configuration */
 /*==============================*/
@@ -106,18 +105,18 @@
 #define CONFIG_MISC_INIT_R
 #undef CONFIG_BOOTDELAY
 #define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
-#define CFG_PROMPT		"U-Boot > "	/* Monitor Command Prompt */
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size  */
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print buffer sz */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_LOAD_ADDR		0x80700000	/* default Linux kernel load address */
+#define CONFIG_SYS_PROMPT		"U-Boot > "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print buffer sz */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR		0x80700000	/* default Linux kernel load address */
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_AUTO_COMPLETE		/* Won't work with hush so far, may be later */
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_CMDLINE_EDITING
-#define CFG_LONGHELP
+#define CONFIG_SYS_LONGHELP
 #define CONFIG_CRC32_VERIFY
 #define CONFIG_MX_CYCLIC
 /*===================*/
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index 39fb2a5..875bab6 100644
--- a/include/configs/davinci_sffsdr.h
+++ b/include/configs/davinci_sffsdr.h
@@ -26,45 +26,45 @@
 
 /* Board */
 #define SFFSDR
-#define CFG_NAND_LARGEPAGE
-#define CFG_USE_NAND
-#define CFG_USE_DSPLINK		/* This is to prevent U-Boot from
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_USE_NAND
+#define CONFIG_SYS_USE_DSPLINK		/* This is to prevent U-Boot from
 				 * powering ON the DSP. */
 /* SoC Configuration */
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
 #define CONFIG_SYS_CLK_FREQ	297000000	/* Arm Clock frequency */
-#define CFG_TIMERBASE		0x01c21400	/* use timer 0 */
-#define CFG_HZ_CLOCK		27000000	/* Timer Input clock freq */
-#define CFG_HZ			1000
+#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
+#define CONFIG_SYS_HZ			1000
 /* EEPROM definitions for Atmel 24LC64 EEPROM chip */
-#define CFG_I2C_EEPROM_ADDR_LEN		2
-#define CFG_I2C_EEPROM_ADDR		0x50
-#define CFG_EEPROM_PAGE_WRITE_BITS	5
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
 /* Memory Info */
-#define CFG_MALLOC_LEN		(0x10000 + 256*1024)	/* malloc() len */
-#define CFG_GBL_DATA_SIZE	128		/* reserved for initial data */
-#define CFG_MEMTEST_START	0x80000000	/* memtest start address */
-#define CFG_MEMTEST_END		0x81000000	/* 16MB RAM test */
+#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 256*1024)	/* malloc() len */
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* reserved for initial data */
+#define CONFIG_SYS_MEMTEST_START	0x80000000	/* memtest start address */
+#define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
 #define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
 #define CONFIG_STACKSIZE	(256*1024)	/* regular stack */
 #define PHYS_SDRAM_1		0x80000000	/* DDR Start */
 #define PHYS_SDRAM_1_SIZE	0x08000000	/* DDR size 128MB */
 #define DDR_4BANKS				/* 4-bank DDR2 (128MB) */
 /* Serial Driver info */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	4		/* NS16550 register size */
-#define CFG_NS16550_COM1	0x01c20000	/* Base address of UART0 */
-#define CFG_NS16550_CLK		27000000	/* Input clock to NS16550 */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	4		/* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1	0x01c20000	/* Base address of UART0 */
+#define CONFIG_SYS_NS16550_CLK		27000000	/* Input clock to NS16550 */
 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
 #define CONFIG_BAUDRATE		115200		/* Default baud rate */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 /* I2C Configuration */
 #define CONFIG_HARD_I2C
 #define CONFIG_DRIVER_DAVINCI_I2C
-#define CFG_I2C_SPEED		80000	/* 100Kbps won't work, silicon bug */
-#define CFG_I2C_SLAVE		10	/* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C_SPEED		80000	/* 100Kbps won't work, silicon bug */
+#define CONFIG_SYS_I2C_SLAVE		10	/* Bogus, master-only in U-Boot */
 /* Network & Ethernet Configuration */
 #define CONFIG_DRIVER_TI_EMAC
 #define CONFIG_MII
@@ -76,41 +76,40 @@
 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 /* Flash & Environment */
 #undef CONFIG_ENV_IS_IN_FLASH
-#define CFG_NO_FLASH
+#define CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
 #define CONFIG_ENV_SECT_SIZE	2048	/* Env sector Size */
 #define CONFIG_ENV_SIZE		SZ_128K
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
 #define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
-#define CFG_NAND_BASE		0x02000000
-#define CFG_NAND_HW_ECC
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
-#define NAND_MAX_CHIPS		1
+#define CONFIG_SYS_NAND_BASE		0x02000000
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
 #define CONFIG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
 /* I2C switch definitions for PCA9543 chip */
-#define CFG_I2C_PCA9543_ADDR		0x70
-#define CFG_I2C_PCA9543_ADDR_LEN	0	/* Single register. */
-#define CFG_I2C_PCA9543_ENABLE_CH0	0x01	/* Enable channel 0. */
+#define CONFIG_SYS_I2C_PCA9543_ADDR		0x70
+#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN	0	/* Single register. */
+#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0	0x01	/* Enable channel 0. */
 /* U-Boot general configuration */
 #undef CONFIG_USE_IRQ				/* No IRQ/FIQ in U-Boot */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_BOOTDELAY	5		/* Autoboot after 5 seconds. */
 #define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
-#define CFG_PROMPT		"U-Boot > "	/* Monitor Command Prompt */
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size  */
-#define CFG_PBSIZE							\
-		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print buffer size */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_LOAD_ADDR		0x80700000	/* Default Linux kernel
+#define CONFIG_SYS_PROMPT		"U-Boot > "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE							\
+		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)	/* Print buffer size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR		0x80700000	/* Default Linux kernel
 						 * load address. */
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_AUTO_COMPLETE		/* Won't work with hush so far,
 					 * may be later */
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_CMDLINE_EDITING
-#define CFG_LONGHELP
+#define CONFIG_SYS_LONGHELP
 #define CONFIG_CRC32_VERIFY
 #define CONFIG_MX_CYCLIC
 /* Linux Information */
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index bb42a54..47ab27a 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -50,31 +50,31 @@
 /* Board */
 /*=======*/
 #define SONATA_BOARD
-#define CFG_NAND_SMALLPAGE
-#define CFG_USE_NOR
+#define CONFIG_SYS_NAND_SMALLPAGE
+#define CONFIG_SYS_USE_NOR
 /*===================*/
 /* SoC Configuration */
 /*===================*/
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
 #define CONFIG_SYS_CLK_FREQ	297000000	/* Arm Clock frequency */
-#define CFG_TIMERBASE		0x01c21400	/* use timer 0 */
-#define CFG_HZ_CLOCK		27000000	/* Timer Input clock freq */
-#define CFG_HZ			1000
+#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
+#define CONFIG_SYS_HZ			1000
 /*====================================================*/
 /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
 /* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */
 /*====================================================*/
-#define CFG_I2C_EEPROM_ADDR_LEN		2
-#define CFG_I2C_EEPROM_ADDR		0x50
-#define CFG_EEPROM_PAGE_WRITE_BITS	6
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
 /*=============*/
 /* Memory Info */
 /*=============*/
-#define CFG_MALLOC_LEN		(0x10000 + 128*1024)	/* malloc() len */
-#define CFG_GBL_DATA_SIZE	128		/* reserved for initial data */
-#define CFG_MEMTEST_START	0x80000000	/* memtest start address */
-#define CFG_MEMTEST_END		0x81000000	/* 16MB RAM test */
+#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 128*1024)	/* malloc() len */
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* reserved for initial data */
+#define CONFIG_SYS_MEMTEST_START	0x80000000	/* memtest start address */
+#define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
 #define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
 #define CONFIG_STACKSIZE	(256*1024)	/* regular stack */
 #define PHYS_SDRAM_1		0x80000000	/* DDR Start */
@@ -83,21 +83,21 @@
 /*====================*/
 /* Serial Driver info */
 /*====================*/
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	4		/* NS16550 register size */
-#define CFG_NS16550_COM1	0x01c20000	/* Base address of UART0 */
-#define CFG_NS16550_CLK		27000000	/* Input clock to NS16550 */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	4		/* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1	0x01c20000	/* Base address of UART0 */
+#define CONFIG_SYS_NS16550_CLK		27000000	/* Input clock to NS16550 */
 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
 #define CONFIG_BAUDRATE		115200		/* Default baud rate */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 /*===================*/
 /* I2C Configuration */
 /*===================*/
 #define CONFIG_HARD_I2C
 #define CONFIG_DRIVER_DAVINCI_I2C
-#define CFG_I2C_SPEED		80000	/* 100Kbps won't work, silicon bug */
-#define CFG_I2C_SLAVE		10	/* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C_SPEED		80000	/* 100Kbps won't work, silicon bug */
+#define CONFIG_SYS_I2C_SLAVE		10	/* Bogus, master-only in U-Boot */
 /*==================================*/
 /* Network & Ethernet Configuration */
 /*==================================*/
@@ -111,21 +111,20 @@
 /*=====================*/
 /* Flash & Environment */
 /*=====================*/
-#ifdef CFG_USE_NAND
+#ifdef CONFIG_SYS_USE_NAND
 #undef CONFIG_ENV_IS_IN_FLASH
-#define CFG_NO_FLASH
+#define CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
 #define CONFIG_ENV_SECT_SIZE	512	/* Env sector Size */
 #define CONFIG_ENV_SIZE		SZ_16K
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
 #define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
-#define CFG_NAND_BASE		0x02000000
-#define CFG_NAND_HW_ECC
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
-#define NAND_MAX_CHIPS		1
+#define CONFIG_SYS_NAND_BASE		0x02000000
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
 #define CONFIG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
 #define DEF_BOOTM		""
-#elif defined(CFG_USE_NOR)
+#elif defined(CONFIG_SYS_USE_NOR)
 #ifdef CONFIG_NOR_UART_BOOT
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
 #define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
@@ -134,17 +133,17 @@
 #undef CONFIG_SKIP_RELOCATE_UBOOT
 #endif
 #define CONFIG_ENV_IS_IN_FLASH
-#undef CFG_NO_FLASH
+#undef CONFIG_SYS_NO_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_MAX_FLASH_BANKS	1		/* max number of flash banks */
-#define CFG_FLASH_SECT_SZ	0x20000		/* 128KB sect size AMD Flash */
-#define CONFIG_ENV_OFFSET		(CFG_FLASH_SECT_SZ*2)
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ	0x20000		/* 128KB sect size AMD Flash */
+#define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ*2)
 #define PHYS_FLASH_1		0x02000000	/* CS2 Base address	 */
-#define CFG_FLASH_BASE		PHYS_FLASH_1	/* Flash Base for U-Boot */
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1	/* Flash Base for U-Boot */
 #define PHYS_FLASH_SIZE		0x2000000	/* Flash size 32MB	 */
-#define CFG_MAX_FLASH_SECT	(PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
-#define CONFIG_ENV_SECT_SIZE	CFG_FLASH_SECT_SZ	/* Env sector Size */
+#define CONFIG_SYS_MAX_FLASH_SECT	(PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_FLASH_SECT_SZ	/* Env sector Size */
 #endif
 /*==============================*/
 /* U-Boot general configuration */
@@ -153,18 +152,18 @@
 #define CONFIG_MISC_INIT_R
 #undef CONFIG_BOOTDELAY
 #define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
-#define CFG_PROMPT		"U-Boot > "	/* Monitor Command Prompt */
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size  */
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print buffer sz */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_LOAD_ADDR		0x80700000	/* default Linux kernel load address */
+#define CONFIG_SYS_PROMPT		"U-Boot > "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print buffer sz */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR		0x80700000	/* default Linux kernel load address */
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_AUTO_COMPLETE		/* Won't work with hush so far, may be later */
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_CMDLINE_EDITING
-#define CFG_LONGHELP
+#define CONFIG_SYS_LONGHELP
 #define CONFIG_CRC32_VERIFY
 #define CONFIG_MX_CYCLIC
 /*===================*/
@@ -190,14 +189,14 @@
 #undef CONFIG_CMD_BDI
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_SETGETDCR
-#ifdef CFG_USE_NAND
+#ifdef CONFIG_SYS_USE_NAND
 #undef CONFIG_CMD_FLASH
 #undef CONFIG_CMD_IMLS
 #define CONFIG_CMD_NAND
-#elif defined(CFG_USE_NOR)
+#elif defined(CONFIG_SYS_USE_NOR)
 #define CONFIG_CMD_JFFS2
 #else
-#error "Either CFG_USE_NAND or CFG_USE_NOR _MUST_ be defined !!!"
+#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
 #endif
 /*=======================*/
 /* KGDB support (if any) */
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index d7e48d0..b439c80 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -59,7 +59,7 @@
 #define CONFIG_BAUDRATE		115200
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
 #undef	CONFIG_BOOTARGS
@@ -97,7 +97,7 @@
 #undef CONFIG_CMD_BDI
 #undef CONFIG_CMD_BEDBUG
 #undef CONFIG_CMD_ELF
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
 #undef CONFIG_CMD_FAT
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_MII
@@ -130,73 +130,73 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory      */
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory      */
 
-#define	CFG_PROMPT		"DbAu1xx0 # "	/* Monitor Command Prompt    */
+#define	CONFIG_SYS_PROMPT		"DbAu1xx0 # "	/* Monitor Command Prompt    */
 
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size   */
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args*/
 
-#define CFG_MALLOC_LEN		128*1024
+#define CONFIG_SYS_MALLOC_LEN		128*1024
 
-#define CFG_BOOTPARAMS_LEN	128*1024
+#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024
 
-#define CFG_MHZ			396
+#define CONFIG_SYS_MHZ			396
 
-#if (CFG_MHZ % 12) != 0
+#if (CONFIG_SYS_MHZ % 12) != 0
 #error "Invalid CPU frequency - must be multiple of 12!"
 #endif
 
-#define CFG_MIPS_TIMER_FREQ	(CFG_MHZ * 1000000)
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
 
-#define CFG_HZ			1000
+#define CONFIG_SYS_HZ			1000
 
-#define CFG_SDRAM_BASE		0x80000000     /* Cached addr */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000     /* Cached addr */
 
-#define	CFG_LOAD_ADDR		0x81000000     /* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x81000000     /* default load address	*/
 
-#define CFG_MEMTEST_START	0x80100000
-#define CFG_MEMTEST_END		0x80800000
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x80800000
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
 #ifdef CONFIG_DBAU1550
 
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	(512)	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	(512)	/* max number of sectors on one chip */
 
 #define PHYS_FLASH_1		0xb8000000 /* Flash Bank #1 */
 #define PHYS_FLASH_2		0xbc000000 /* Flash Bank #2 */
 
 #else /* CONFIG_DBAU1550 */
 
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
 
 #define PHYS_FLASH_1		0xbec00000 /* Flash Bank #1 */
 #define PHYS_FLASH_2		0xbfc00000 /* Flash Bank #2 */
 
 #endif /* CONFIG_DBAU1550 */
 
-#define CFG_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
+#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
 
-#define CFG_FLASH_CFI           1
+#define CONFIG_SYS_FLASH_CFI           1
 #define CONFIG_FLASH_CFI_DRIVER    1
 
 /* The following #defines are needed to get flash environment right */
-#define	CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MONITOR_LEN		(192 << 10)
+#define	CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)
 
-#define CFG_INIT_SP_OFFSET	0x400000
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
 
 /* We boot from this flash, selected with dip switch */
-#define CFG_FLASH_BASE		PHYS_FLASH_2
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_2
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define	CONFIG_ENV_IS_NOWHERE	1
 
@@ -220,8 +220,8 @@
 
 #ifndef CONFIG_DBAU1550
 /*---ATA PCMCIA ------------------------------------*/
-#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
-#define CFG_PCMCIA_MEM_ADDR 0x20000000
+#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
 #define CONFIG_PCMCIA_SLOT_A
 
 #define CONFIG_ATAPI 1
@@ -231,31 +231,31 @@
 #define CONFIG_IDE_PCMCIA 1
 
 /* We only support one slot for now */
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR       CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET     8
+#define CONFIG_SYS_ATA_DATA_OFFSET     8
 
 /* Offset for normal register accesses  */
-#define CFG_ATA_REG_OFFSET      0
+#define CONFIG_SYS_ATA_REG_OFFSET      0
 
 /* Offset for alternate registers       */
-#define CFG_ATA_ALT_OFFSET      0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET      0x0100
 #endif /* CONFIG_DBAU1550 */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		16384
-#define CFG_ICACHE_SIZE		16384
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_DCACHE_SIZE		16384
+#define CONFIG_SYS_ICACHE_SIZE		16384
+#define CONFIG_SYS_CACHELINE_SIZE	32
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/debris.h b/include/configs/debris.h
index 3ea4fa6..4d65f6a 100644
--- a/include/configs/debris.h
+++ b/include/configs/debris.h
@@ -76,7 +76,7 @@
 #define CONFIG_SERVERIP	192.168.0.1
 
 /* autoload */
-#undef CFG_AUTOLOAD
+#undef CONFIG_SYS_AUTOLOAD
 
 /* rootpath */
 #define CONFIG_ROOTPATH /tftpboot/target
@@ -156,14 +156,14 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		1		/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -174,7 +174,7 @@
 
 #define CONFIG_NET_MULTI		/* Multi ethernet cards support */
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100  */
 #define CONFIG_EEPRO100_SROM_WRITE
 
 #define PCI_ENET0_IOADDR	0x80000000
@@ -184,49 +184,49 @@
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	0x20000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE	0x20000000
 #define CONFIG_VERY_BIG_RAM
 
-#define CFG_RESET_ADDRESS	0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
 
 #if defined (USE_DINK32)
-#define CFG_MONITOR_LEN		0x00040000
-#define CFG_MONITOR_BASE	0x00090000
-#define CFG_RAMBOOT		1
-#define CFG_INIT_RAM_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_INIT_RAM_END	0x10000
-#define CFG_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_LEN		0x00040000
+#define CONFIG_SYS_MONITOR_BASE	0x00090000
+#define CONFIG_SYS_RAMBOOT		1
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_INIT_RAM_END	0x10000
+#define CONFIG_SYS_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #else
-#undef	CFG_RAMBOOT
-#define CFG_MONITOR_LEN		0x00040000
-#define CFG_MONITOR_BASE	TEXT_BASE
+#undef	CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_MONITOR_LEN		0x00040000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 
-/*#define CFG_GBL_DATA_SIZE    256*/
-#define CFG_GBL_DATA_SIZE	128
+/*#define CONFIG_SYS_GBL_DATA_SIZE    256*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128
 
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_END      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 #endif
 
-#define CFG_FLASH_BASE		0x7C000000
-#define CFG_FLASH_SIZE		(16*1024*1024)	/* debris has tiny eeprom	*/
+#define CONFIG_SYS_FLASH_BASE		0x7C000000
+#define CONFIG_SYS_FLASH_SIZE		(16*1024*1024)	/* debris has tiny eeprom	*/
 
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
 
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
 
-#define CFG_EUMB_ADDR		0xFC000000
+#define CONFIG_SYS_EUMB_ADDR		0xFC000000
 
-#define CFG_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
-#define CFG_FLASH_RANGE_SIZE	0x01000000
+#define CONFIG_SYS_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
+#define CONFIG_SYS_FLASH_RANGE_SIZE	0x01000000
 #define FLASH_BASE0_PRELIM	0x7C000000	/* debris flash		*/
 
 /*
@@ -253,18 +253,18 @@
 
 #define CONFIG_ENV_IS_IN_NVRAM      1
 #define CONFIG_ENV_OVERWRITE     1
-#define CFG_NVRAM_ACCESS_ROUTINE 1
+#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
 #define CONFIG_ENV_ADDR		0xFF000000 /* right at the start of NVRAM  */
 #define CONFIG_ENV_SIZE		0x400	/* Size of the Environment - 8K	   */
 #define CONFIG_ENV_OFFSET		0	/* starting right at the beginning */
 
-#define CFG_NVRAM_BASE_ADDR	0xff000000
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xff000000
 
 /*
- * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS =
+ * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS =
  * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
  */
-#define CFG_NVRAM_VXWORKS_OFFS	0x6900
+#define CONFIG_SYS_NVRAM_VXWORKS_OFFS	0x6900
 
 /*
  * select i2c support configuration
@@ -275,8 +275,8 @@
  */
 #define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
 #undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 #ifdef CONFIG_SOFT_I2C
 #error "Soft I2C is not configured properly.  Please review!"
@@ -291,13 +291,13 @@
 #define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
 #endif /* CONFIG_SOFT_I2C */
 
-#define CFG_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_FLASH_BANKS		{ FLASH_BASE0_PRELIM }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_FLASH_BANKS		{ FLASH_BASE0_PRELIM }
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
@@ -306,17 +306,17 @@
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
 
-#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_REG_SIZE	1
 
-#define CFG_NS16550_CLK		7372800
+#define CONFIG_SYS_NS16550_CLK		7372800
 
-#define CFG_NS16550_COM1	0xFF080000
-#define CFG_NS16550_COM2	(CFG_NS16550_COM1 + 8)
-#define CFG_NS16550_COM3	(CFG_NS16550_COM1 + 16)
-#define CFG_NS16550_COM4	(CFG_NS16550_COM1 + 24)
+#define CONFIG_SYS_NS16550_COM1	0xFF080000
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_NS16550_COM1 + 8)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_NS16550_COM1 + 16)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_NS16550_COM1 + 24)
 
 /*
  * Low Level Configuration Settings
@@ -327,32 +327,32 @@
 #define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
 
-#define CFG_DLL_EXTEND		0x00
-#define CFG_PCI_HOLD_DEL	0x20
+#define CONFIG_SYS_DLL_EXTEND		0x00
+#define CONFIG_SYS_PCI_HOLD_DEL	0x20
 
-#define CFG_ROMNAL	15	/* rom/flash next access time */
-#define CFG_ROMFAL	31	/* rom/flash access time */
+#define CONFIG_SYS_ROMNAL	15	/* rom/flash next access time */
+#define CONFIG_SYS_ROMFAL	31	/* rom/flash access time */
 
-#define CFG_REFINT	430	/* # of clocks between CBR refresh cycles */
+#define CONFIG_SYS_REFINT	430	/* # of clocks between CBR refresh cycles */
 
-#define CFG_DBUS_SIZE2	1	/* set for 8-bit RCS1, clear for 32,64 */
+#define CONFIG_SYS_DBUS_SIZE2	1	/* set for 8-bit RCS1, clear for 32,64 */
 
 /* the following are for SDRAM only*/
-#define CFG_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
-#define CFG_REFREC	8	/* Refresh to activate interval		*/
-#define CFG_RDLAT	4	/* data latency from read command	*/
-#define CFG_PRETOACT	3	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE	5	/* Activate to Precharge interval	*/
-#define CFG_ACTORW		3	/* Activate to R/W			*/
-#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
-#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#define CONFIG_SYS_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
+#define CONFIG_SYS_REFREC	8	/* Refresh to activate interval		*/
+#define CONFIG_SYS_RDLAT	4	/* data latency from read command	*/
+#define CONFIG_SYS_PRETOACT	3	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE	5	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
 #if 0
-#define CFG_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
+#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
 #endif
 
-#define CFG_REGISTERD_TYPE_BUFFER   1
-#define CFG_EXTROM 1
-#define CFG_REGDIMM 0
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
+#define CONFIG_SYS_EXTROM 1
+#define CONFIG_SYS_REGDIMM 0
 
 
 /* memory bank settings*/
@@ -362,93 +362,93 @@
  * bits will be set to 0x00000 for a start address, or 0xfffff for an
  * end address
  */
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		(0x4000000 - 1)
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x04000000
-#define CFG_BANK1_END		(0x8000000 - 1)
-#define CFG_BANK1_ENABLE	1
-#define CFG_BANK2_START		0x3ff00000
-#define CFG_BANK2_END		0x3fffffff
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x3ff00000
-#define CFG_BANK3_END		0x3fffffff
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x00000000
-#define CFG_BANK4_END		0x00000000
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x00000000
-#define CFG_BANK5_END		0x00000000
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x00000000
-#define CFG_BANK6_END		0x00000000
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x00000000
-#define CFG_BANK7_END		0x00000000
-#define CFG_BANK7_ENABLE	0
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		(0x4000000 - 1)
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x04000000
+#define CONFIG_SYS_BANK1_END		(0x8000000 - 1)
+#define CONFIG_SYS_BANK1_ENABLE	1
+#define CONFIG_SYS_BANK2_START		0x3ff00000
+#define CONFIG_SYS_BANK2_END		0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x3ff00000
+#define CONFIG_SYS_BANK3_END		0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x00000000
+#define CONFIG_SYS_BANK4_END		0x00000000
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x00000000
+#define CONFIG_SYS_BANK5_END		0x00000000
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x00000000
+#define CONFIG_SYS_BANK6_END		0x00000000
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x00000000
+#define CONFIG_SYS_BANK7_END		0x00000000
+#define CONFIG_SYS_BANK7_ENABLE	0
 /*
  * Memory bank enable bitmask, specifying which of the banks defined above
  are actually present. MSB is for bank #7, LSB is for bank #0.
  */
-#define CFG_BANK_ENABLE		0x01
+#define CONFIG_SYS_BANK_ENABLE		0x01
 
-#define CFG_ODCR		0x75	/* configures line driver impedances,	*/
+#define CONFIG_SYS_ODCR		0x75	/* configures line driver impedances,	*/
 					/* see 8240 book for bit definitions	*/
-#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
 					/* currently accessed page in memory	*/
 					/* see 8240 book for details		*/
 
 /* SDRAM 0 - 256MB */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* stack in DCACHE @ 1GB (no backing mem) */
 #if defined(USE_DINK32)
-#define CFG_IBAT1L	(0x40000000 | BATL_PP_00 )
-#define CFG_IBAT1U	(0x40000000 | BATU_BL_128K )
+#define CONFIG_SYS_IBAT1L	(0x40000000 | BATL_PP_00 )
+#define CONFIG_SYS_IBAT1U	(0x40000000 | BATU_BL_128K )
 #else
-#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 #endif
 
 /* PCI memory */
-#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* Flash, config addrs, etc */
-#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 
diff --git a/include/configs/delta.h b/include/configs/delta.h
index 4b75e15..001b48a 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -34,7 +34,6 @@
 #ifdef CONFIG_LCD
 #define CONFIG_SHARP_LM8V31
 #endif
-/* #define CONFIG_MMC		1 */
 #define BOARD_LATE_INIT		1
 
 #undef CONFIG_SKIP_RELOCATE_UBOOT
@@ -43,8 +42,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN	    (CONFIG_ENV_SIZE + 256*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 256*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -59,11 +58,11 @@
 #endif
 
 #define CONFIG_HARD_I2C		1	/* required for DA9030 access */
-#define CFG_I2C_SPEED		400000	/* I2C speed */
-#define CFG_I2C_SLAVE		1	/* I2C controllers address */
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed */
+#define CONFIG_SYS_I2C_SLAVE		1	/* I2C controllers address */
 #define DA9030_I2C_ADDR		0x49	/* I2C address of DA9030 */
-#define CFG_DA9030_EXTON_DELAY	100000	/* wait x us after DA9030 reset via EXTON */
-#define CFG_I2C_INIT_BOARD	1
+#define CONFIG_SYS_DA9030_EXTON_DELAY	100000	/* wait x us after DA9030 reset via EXTON */
+#define CONFIG_SYS_I2C_INIT_BOARD	1
 /* #define CONFIG_HW_WATCHDOG	1	/\* Required for hitting the DA9030 WD *\/ */
 
 #define DELTA_CHECK_KEYBD	1	/* check for keys pressed during boot */
@@ -108,7 +107,7 @@
 
 #else
 
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_I2C
 
@@ -125,13 +124,11 @@
 
 #include <asm/arch/pxa-regs.h> /* for OHCI_REGS_BASE */
 
-#undef CFG_USB_OHCI_BOARD_INIT
-#define CFG_USB_OHCI_CPU_INIT	1
-#define CFG_USB_OHCI_REGS_BASE	OHCI_REGS_BASE
-#define CFG_USB_OHCI_SLOT_NAME	"delta"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS	3
-
-#define LITTLEENDIAN            1       /* used by usb_ohci.c  */
+#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	OHCI_REGS_BASE
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"delta"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
 
 #define CONFIG_BOOTDELAY	-1
 #define CONFIG_ETHADDR		08:00:3e:26:0a:5b
@@ -151,39 +148,43 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_HUSH_PARSER		1
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
-#define CFG_LONGHELP				/* undef to save memory		*/
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT		"$ "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
 #else
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 #endif
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_DEVICE_NULLDEV	1
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1
 
-#define CFG_MEMTEST_START	0x80400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x80800000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x80400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x80800000	/* 4 ... 8 MB in DRAM	*/
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR	(CFG_DRAM_BASE + 0x8000) /* default load address */
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
 
-#define CFG_HZ			3250000		/* incrementer freq: 3.25 MHz */
+#define CONFIG_SYS_HZ			1000
 
 /* Monahans Core Frequency */
-#define CFG_MONAHANS_RUN_MODE_OSC_RATIO		16 /* valid values: 8, 16, 24, 31 */
-#define CFG_MONAHANS_TURBO_RUN_MODE_RATIO	1  /* valid values: 1, 2 */
+#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO		16 /* valid values: 8, 16, 24, 31 */
+#define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO	1  /* valid values: 1, 2 */
 
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-/* #define CFG_MMC_BASE		0xF0000000 */
+#ifdef CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_SYS_MMC_BASE		0xF0000000
+#endif
 
 /*
  * Stack sizes
@@ -209,26 +210,26 @@
 #define PHYS_SDRAM_4		0x83000000 /* SDRAM Bank #4 */
 #define PHYS_SDRAM_4_SIZE	0x1000000  /* 64 MB */
 
-#define CFG_DRAM_BASE		0x80000000 /* at CS0 */
-#define CFG_DRAM_SIZE		0x04000000 /* 64 MB Ram */
+#define CONFIG_SYS_DRAM_BASE		0x80000000 /* at CS0 */
+#define CONFIG_SYS_DRAM_SIZE		0x04000000 /* 64 MB Ram */
 
-#undef CFG_SKIP_DRAM_SCRUB
+#undef CONFIG_SYS_SKIP_DRAM_SCRUB
 
 /*
  * NAND Flash
  */
 #undef CONFIG_NAND_LEGACY
 
-#define CFG_NAND0_BASE		0x0 /* 0x43100040 */ /* 0x10000000 */
-#undef CFG_NAND1_BASE
+#define CONFIG_SYS_NAND0_BASE		0x0 /* 0x43100040 */ /* 0x10000000 */
+#undef CONFIG_SYS_NAND1_BASE
 
-#define CFG_NAND_BASE_LIST	{ CFG_NAND0_BASE }
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND0_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
 
 /* nand timeout values */
-#define CFG_NAND_PROG_ERASE_TO	3000
-#define CFG_NAND_OTHER_TO	100
-#define CFG_NAND_SENDCMD_RETRY	3
+#define CONFIG_SYS_NAND_PROG_ERASE_TO	3000
+#define CONFIG_SYS_NAND_OTHER_TO	100
+#define CONFIG_SYS_NAND_SENDCMD_RETRY	3
 #undef NAND_ALLOW_ERASE_ALL	/* Allow erasing bad blocks - don't use */
 
 /* NAND Timing Parameters (in ns) */
@@ -245,9 +246,9 @@
 #define NAND_TIMING_tAR		10
 
 /* NAND debugging */
-#define CFG_DFC_DEBUG1 /* usefull */
-#undef CFG_DFC_DEBUG2  /* noisy */
-#undef CFG_DFC_DEBUG3  /* extremly noisy  */
+#define CONFIG_SYS_DFC_DEBUG1 /* usefull */
+#undef CONFIG_SYS_DFC_DEBUG2  /* noisy */
+#undef CONFIG_SYS_DFC_DEBUG3  /* extremly noisy  */
 
 #define CONFIG_MTD_DEBUG
 #define CONFIG_MTD_DEBUG_VERBOSE 1
@@ -258,9 +259,8 @@
 
 #define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS		1
-#define NAND_MAX_CHIPS		1
 
-#define CFG_NO_FLASH		1
+#define CONFIG_SYS_NO_FLASH		1
 
 #define CONFIG_ENV_IS_IN_NAND	1
 #define CONFIG_ENV_OFFSET		0x40000
diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h
index 2249fc8..e329fd3 100644
--- a/include/configs/dnp1110.h
+++ b/include/configs/dnp1110.h
@@ -46,8 +46,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -99,25 +99,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"DNP1110 # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"DNP1110 # "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0xc0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0xc0200000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0xc0200000	/* default load address	*/
 
-#define	CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x0b		/* set core clock to 220 MHz */
+#define	CONFIG_SYS_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_CPUSPEED		0x0b		/* set core clock to 220 MHz */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -143,17 +143,17 @@
 #define PHYS_FLASH_BANK_SIZE    0x01000000 /* 32 MB Banks */
 #define PHYS_FLASH_SECT_SIZE    0x00020000 /* 256 KB sectors (x2) */
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128		/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* max number of sectors on one chip	*/
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0xF80000)	/* Addr of Environment Sector	*/
diff --git a/include/configs/eNET.h b/include/configs/eNET.h
new file mode 100644
index 0000000..447c7bc
--- /dev/null
+++ b/include/configs/eNET.h
@@ -0,0 +1,248 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Stuff still to be dealt with -
+ */
+#define CONFIG_RTC_MC146818
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define DEBUG_PARSER
+
+#define CONFIG_X86			1	/* Intel X86 CPU */
+#define CONFIG_SC520			1	/* AMD SC520 */
+#define CONFIG_SC520_SSI
+#define CONFIG_SHOW_BOOT_PROGRESS	1
+#define CONFIG_LAST_STAGE_INIT		1
+
+/*
+ * If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the
+ * bottom (processor) board MUST be removed!
+ */
+#undef CONFIG_WATCHDOG
+#undef CONFIG_HW_WATCHDOG
+
+ /*-----------------------------------------------------------------------
+  * Video Configuration
+  */
+#undef CONFIG_VIDEO			/* No Video Hardware */
+#undef CONFIG_CFB_CONSOLE
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_MALLOC_SIZE	(CONFIG_SYS_ENV_SIZE + 128*1024)
+
+#define CONFIG_BAUDRATE		9600
+
+/*-----------------------------------------------------------------------
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_AUTOSCRIPT	/* Autoscript Support		*/
+#define CONFIG_CMD_BDI		/* bdinfo			*/
+#define CONFIG_CMD_BOOTD	/* bootd			*/
+#define CONFIG_CMD_CONSOLE	/* coninfo			*/
+#define CONFIG_CMD_ECHO		/* echo arguments		*/
+#define CONFIG_CMD_SAVEENV	/* saveenv			*/
+#define CONFIG_CMD_FLASH	/* flinfo, erase, protect	*/
+#define CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#define CONFIG_CMD_IMI		/* iminfo			*/
+#define CONFIG_CMD_IMLS		/* List all found images	*/
+#define CONFIG_CMD_ITEST	/* Integer (and string) test	*/
+#define CONFIG_CMD_LOADB	/* loadb			*/
+#define CONFIG_CMD_LOADS	/* loads			*/
+#define CONFIG_CMD_MEMORY	/* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MISC		/* Misc functions like sleep etc*/
+#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#undef CONFIG_CMD_NFS		/* NFS support			*/
+#define CONFIG_CMD_RUN		/* run command in env variable	*/
+#define CONFIG_CMD_SETGETDCR	/* DCR support on 4xx		*/
+#define CONFIG_CMD_XIMG		/* Load part of Multi Image	*/
+#undef CONFIG_CMD_IRQ		/* IRQ Information		*/
+
+#define CONFIG_BOOTDELAY		15
+#define CONFIG_BOOTARGS			"root=/dev/mtdblock0 console=ttyS0,9600"
+/* #define CONFIG_BOOTCOMMAND		"bootm 38000000" */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE		115200		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX		2		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"boot > "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + \
+					 16)		/* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x01000000	/* 1 ... 16 MB in DRAM	*/
+
+#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CONFIG_SYS_HZ			1024		/* incrementer freq: 1kHz */
+
+						/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * SDRAM Configuration
+ */
+#define CONFIG_SYS_SDRAM_DRCTMCTL	0x18
+#define CONFIG_NR_DRAM_BANKS		4
+
+/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
+#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
+#undef CONFIG_SYS_SDRAM_REFRESH_RATE
+#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
+#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
+#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
+
+/*-----------------------------------------------------------------------
+ * CPU Features
+ */
+#define CONFIG_SYS_SC520_HIGH_SPEED	0	/* 100 or 133MHz */
+#undef  CONFIG_SYS_RESET_SC520			/* use SC520 MMCR's to reset cpu */
+#define CONFIG_SYS_TIMER_SC520			/* use SC520 swtimers */
+#undef  CONFIG_SYS_TIMER_GENERIC		/* use the i8254 PIT timers */
+#undef  CONFIG_SYS_TIMER_TSC			/* use the Pentium TSC timers */
+#define CONFIG_SYS_USE_SIO_UART		0       /* prefer the uarts on the SIO to those
+					 * in the SC520 on the CDP */
+
+/*-----------------------------------------------------------------------
+ * Memory organization
+ */
+#define CONFIG_SYS_STACK_SIZE		0x8000  	/* Size of bootloader stack */
+#define CONFIG_SYS_BL_START_FLASH	0x38040000	/* Address of relocated code */
+#define CONFIG_SYS_BL_START_RAM		0x03fd0000	/* Address of relocated code */
+#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon	*/
+#define CONFIG_SYS_FLASH_BASE		0x38000000	/* Boot Flash */
+#define CONFIG_SYS_FLASH_BASE_1		0x10000000	/* StrataFlash 1 */
+#define CONFIG_SYS_FLASH_BASE_2		0x11000000	/* StrataFlash 2 */
+
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+ /*-----------------------------------------------------------------------
+  * FLASH configuration
+  */
+#define CONFIG_FLASH_CFI_DRIVER				/* Use the common driver */
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_FLASH_CFI				/* Flash is CFI conformant */
+#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* max number of memory banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE,   \
+					 CONFIG_SYS_FLASH_BASE_1, \
+					 CONFIG_SYS_FLASH_BASE_2}
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#define CONFIG_SYS_FLASH_LEGACY_512Kx8
+
+ /*-----------------------------------------------------------------------
+  * Environment configuration
+  */
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_OFFSET		0x20000 /*   Offset   of Environment Sector */
+#define CONFIG_ENV_SIZE			0x08000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_SECT_SIZE		0x20000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE_1 + \
+					 CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+					 CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+
+
+ /*-----------------------------------------------------------------------
+  * PCI configuration
+  */
+#undef CONFIG_PCI                                /* include pci support */
+#undef CONFIG_PCI_PNP                            /* pci plug-and-play */
+#undef CONFIG_PCI_SCAN_SHOW
+#undef CONFIG_SYS_FIRST_PCI_IRQ
+#undef CONFIG_SYS_SECOND_PCI_IRQ
+#undef CONFIG_SYS_THIRD_PCI_IRQ
+#undef CONFIG_SYS_FORTH_PCI_IRQ
+
+/*-----------------------------------------------------------------------
+ * Hardware watchdog configuration
+ */
+#define CONFIG_SYS_WATCHDOG_PIO_BIT  		0x8000
+#define CONFIG_SYS_WATCHDIG_PIO_DATA 		SC520_PIODATA15_0
+#define CONFIG_SYS_WATCHDIG_PIO_CLR  		SC520_PIOCLR15_0
+#define CONFIG_SYS_WATCHDIG_PIO_SET  		SC520_PIOSET15_0
+
+/*-----------------------------------------------------------------------
+ * FPGA configuration
+ */
+#define CONFIG_SYS_FPGA_PROGRAM_PIO_BIT		0x2000
+#define CONFIG_SYS_FPGA_INIT_PIO_BIT		0x4000
+#define CONFIG_SYS_FPGA_DONE_PIO_BIT		0x8000
+#define CONFIG_SYS_FPGA_PIO_DATA 		SC520_PIODATA31_16
+#define CONFIG_SYS_FPGA_PIO_DIRECTION 		SC520_PIODIR31_16
+#define CONFIG_SYS_FPGA_PIO_CLR  		SC520_PIOCLR31_16
+#define CONFIG_SYS_FPGA_PIO_SET  		SC520_PIOSET31_16
+#define CONFIG_SYS_FPGA_PROGRAM_BIT_DROP_TIME	1	/* milliseconds */
+#define CONFIG_SYS_FPGA_MAX_INIT_TIME		10	/* milliseconds */
+#define CONFIG_SYS_FPGA_MAX_FINALISE_TIME	10	/* milliseconds */
+#define CONFIG_SYS_FPGA_SSI_DATA_RATE		8333	/* kHz (33.3333MHz xtal) */
+
+#ifndef __ASSEMBLER__
+extern unsigned long ip;
+
+#define PRINTIP				asm ("call next_line\n" \
+					    "next_line:\n" \
+					    "pop %%eax\n" \
+					    "movl %%eax, %0\n" \
+					    :"=r"(ip) \
+					    : /* No Input Registers */ \
+					    :"%eax"); \
+					    printf("IP: 0x%08lx (File: %s, Line: %d)\n", ip, __FILE__, __LINE__);
+
+#endif
+#endif	/* __CONFIG_H */
diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h
index ecf4c5e..85bf236 100644
--- a/include/configs/eXalion.h
+++ b/include/configs/eXalion.h
@@ -77,60 +77,60 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_PCI
 
 
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		1	/* undef to save memory		*/
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
-#define CFG_MAXARGS		8	/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
+#define CONFIG_SYS_LONGHELP		1	/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		8	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_MISC_INIT_R	1
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	0x10000000	/* 1 GBytes - initdram() will	   */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000	/* 1 GBytes - initdram() will	   */
 					     /* return real value.		*/
 
-#define CFG_RESET_ADDRESS	0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
 
-#undef	CFG_RAMBOOT
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	    */
-#define CFG_MONITOR_BASE	TEXT_BASE
+#undef	CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	    */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area
  */
-#define CFG_INIT_DATA_SIZE	128
+#define CONFIG_SYS_INIT_DATA_SIZE	128
 
-#define CFG_INIT_RAM_ADDR	0x40000000
-#define CFG_INIT_RAM_END	0x1000
-#define CFG_INIT_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000
+#define CONFIG_SYS_INIT_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_DATA_SIZE)
 
-#define CFG_GBL_DATA_SIZE	 256	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	 256	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 
 #if defined (CONFIG_MPC8240)
-#define CFG_FLASH_BASE	    0xFFE00000
-#define CFG_FLASH_SIZE	    (2 * 1024 * 1024)	/* onboard 2MByte flash	    */
+#define CONFIG_SYS_FLASH_BASE	    0xFFE00000
+#define CONFIG_SYS_FLASH_SIZE	    (2 * 1024 * 1024)	/* onboard 2MByte flash	    */
 #elif defined (CONFIG_MPC8245)
-#define CFG_FLASH_BASE	    0xFFC00000
-#define CFG_FLASH_SIZE	    (4 * 1024 * 1024)	/* onboard 4MByte flash	    */
+#define CONFIG_SYS_FLASH_BASE	    0xFFC00000
+#define CONFIG_SYS_FLASH_SIZE	    (4 * 1024 * 1024)	/* onboard 4MByte flash	    */
 #else
 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 #endif
@@ -141,27 +141,27 @@
 #define CONFIG_ENV_ADDR		0xFFFC0000
 #define CONFIG_ENV_OFFSET		0	/* starting right at the beginning  */
 
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
-#define CFG_ALT_MEMTEST		1	/* use real memory test	    */
-#define CFG_MEMTEST_START	0x00004000	/* memtest works on	    */
-#define CFG_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM	    */
+#define CONFIG_SYS_ALT_MEMTEST		1	/* use real memory test	    */
+#define CONFIG_SYS_MEMTEST_START	0x00004000	/* memtest works on	    */
+#define CONFIG_SYS_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM	    */
 
-#define CFG_EUMB_ADDR		0xFC000000
+#define CONFIG_SYS_EUMB_ADDR		0xFC000000
 
-/* #define CFG_ISA_MEM		   0xFD000000 */
-#define CFG_ISA_IO		0xFE000000
+/* #define CONFIG_SYS_ISA_MEM		   0xFD000000 */
+#define CONFIG_SYS_ISA_IO		0xFE000000
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks	    */
-#define CFG_MAX_FLASH_SECT	64	/* Max number of sectors per flash  */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks	    */
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* Max number of sectors per flash  */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
 
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE
 #define FLASH_BASE1_PRELIM	0
 
 
@@ -169,13 +169,13 @@
  * FLASH and environment organization
  */
 
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver		*/
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_FLASH_INCREMENT	0	/* there is only one bank		*/
-#define CFG_FLASH_PROTECTION	1	/* use hardware protection		*/
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_FLASH_INCREMENT	0	/* there is only one bank		*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware protection		*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
 
 
 /*-----------------------------------------------------------------------
@@ -200,23 +200,23 @@
 /*-----------------------------------------------------------------------
  * NS16550 Configuration
  */
-#define CFG_NS16550		1
-#define CFG_NS16550_SERIAL	1
+#define CONFIG_SYS_NS16550		1
+#define CONFIG_SYS_NS16550_SERIAL	1
 
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		38400
 
-#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_REG_SIZE	1
 
 #if (CONFIG_CONS_INDEX == 1)
-#define CFG_NS16550_CLK		1843200 /* COM1 only !	*/
+#define CONFIG_SYS_NS16550_CLK		1843200 /* COM1 only !	*/
 #else
-#define CFG_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); })
+#define CONFIG_SYS_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); })
 #endif
 
-#define CFG_NS16550_COM1	(CFG_ISA_IO + 0x3F8)
-#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4500)
-#define CFG_NS16550_COM3	(CFG_EUMB_ADDR + 0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_ISA_IO + 0x3F8)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4500)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_EUMB_ADDR + 0x4600)
 
 /*-----------------------------------------------------------------------
  * select i2c support configuration
@@ -227,15 +227,15 @@
  */
 #define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*-----------------------------------------------------------------------
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
  * You should know what you are doing if you make changes here.
  */
-#define CFG_HZ			1000
+#define CONFIG_SYS_HZ			1000
 
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external frequency to pll	*/
 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2	/* for MPC8240 only		*/
@@ -245,76 +245,76 @@
 #if defined (CONFIG_MPC8245)
 /* Bit-field values for PMCR2.							*/
 #if defined (CONFIG_133MHZ_DRAM)
-#define CFG_DLL_EXTEND		0x80	/* use DLL extended range - 133MHz only */
-#define CFG_PCI_HOLD_DEL	0x20	/* delay and hold timing - 133MHz only	*/
+#define CONFIG_SYS_DLL_EXTEND		0x80	/* use DLL extended range - 133MHz only */
+#define CONFIG_SYS_PCI_HOLD_DEL	0x20	/* delay and hold timing - 133MHz only	*/
 #endif
 
 /* Bit-field values for MIOCR1.							*/
 #if !defined (CONFIG_133MHZ_DRAM)
-#define CFG_DLL_MAX_DELAY	0x04	/*  longer DLL delay line - 66MHz only	*/
+#define CONFIG_SYS_DLL_MAX_DELAY	0x04	/*  longer DLL delay line - 66MHz only	*/
 #endif
 /* Bit-field values for MIOCR2.							*/
-#define CFG_SDRAM_DSCD		0x20	/* SDRAM data in sample clock delay	*/
+#define CONFIG_SYS_SDRAM_DSCD		0x20	/* SDRAM data in sample clock delay	*/
 					/*	- note bottom 3 bits MUST be 0	*/
 #endif
 
 /* Bit-field values for MCCR1.							*/
-#define CFG_ROMNAL		7	/*rom/flash next access time		*/
-#define CFG_ROMFAL	       11	/*rom/flash access time			*/
+#define CONFIG_SYS_ROMNAL		7	/*rom/flash next access time		*/
+#define CONFIG_SYS_ROMFAL	       11	/*rom/flash access time			*/
 
 /* Bit-field values for MCCR2.							*/
-#define CFG_TSWAIT		0x5	/* Transaction Start Wait States timer	*/
+#define CONFIG_SYS_TSWAIT		0x5	/* Transaction Start Wait States timer	*/
 #if defined (CONFIG_133MHZ_DRAM)
-#define CFG_REFINT		1300	/* no of clock cycles between CBR	*/
+#define CONFIG_SYS_REFINT		1300	/* no of clock cycles between CBR	*/
 #else  /* refresh cycles */
-#define CFG_REFINT		750
+#define CONFIG_SYS_REFINT		750
 #endif
 
 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.		*/
 #if defined (CONFIG_133MHZ_DRAM)
-#define CFG_BSTOPRE		1023
+#define CONFIG_SYS_BSTOPRE		1023
 #else
-#define CFG_BSTOPRE		250
+#define CONFIG_SYS_BSTOPRE		250
 #endif
 
 /* Bit-field values for MCCR3.							*/
 /* the following are for SDRAM only						*/
 
 #if defined (CONFIG_133MHZ_DRAM)
-#define CFG_REFREC		9	/* Refresh to activate interval		*/
+#define CONFIG_SYS_REFREC		9	/* Refresh to activate interval		*/
 #else
-#define CFG_REFREC		5	/* Refresh to activate interval		*/
+#define CONFIG_SYS_REFREC		5	/* Refresh to activate interval		*/
 #endif
 #if defined (CONFIG_MPC8240)
-#define CFG_RDLAT		2	/* data latency from read command	*/
+#define CONFIG_SYS_RDLAT		2	/* data latency from read command	*/
 #endif
 
 /* Bit-field values for MCCR4.	*/
 #if defined (CONFIG_133MHZ_DRAM)
-#define CFG_PRETOACT		3	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE		7	/* Activate to Precharge interval	*/
-#define CFG_ACTORW		5	/* Activate to R/W			*/
-#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CONFIG_SYS_PRETOACT		3	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE		7	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		5	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
 #else
 #if 0
-#define CFG_PRETOACT		2	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE		3	/* Activate to Precharge interval	*/
-#define CFG_ACTORW		3	/* Activate to R/W			*/
-#define CFG_SDMODE_CAS_LAT	2	/* SDMODE CAS latency			*/
+#define CONFIG_SYS_PRETOACT		2	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE		3	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	2	/* SDMODE CAS latency			*/
 #endif
-#define CFG_PRETOACT		2	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
-#define CFG_ACTORW		3	/* Activate to R/W			*/
-#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CONFIG_SYS_PRETOACT		2	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
 #endif
-#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
-#define CFG_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
-#define CFG_REGDIMM		0
+#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
+#define CONFIG_SYS_REGDIMM		0
 #if defined (CONFIG_MPC8240)
-#define CFG_REGISTERD_TYPE_BUFFER   0
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   0
 #elif defined (CONFIG_MPC8245)
-#define CFG_REGISTERD_TYPE_BUFFER   1
-#define CFG_EXTROM		    0
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
+#define CONFIG_SYS_EXTROM		    0
 #else
 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 #endif
@@ -327,51 +327,51 @@
  * bits will be set to 0x00000 for a start address, or 0xfffff for an
  * end address
  */
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x3ff00000
-#define CFG_BANK1_END		0x3fffffff
-#define CFG_BANK1_ENABLE	0
-#define CFG_BANK2_START		0x3ff00000
-#define CFG_BANK2_END		0x3fffffff
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x3ff00000
-#define CFG_BANK3_END		0x3fffffff
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x00000000
-#define CFG_BANK4_END		0x00000000
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x00000000
-#define CFG_BANK5_END		0x00000000
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x00000000
-#define CFG_BANK6_END		0x00000000
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x00000000
-#define CFG_BANK7_END		0x00000000
-#define CFG_BANK7_ENABLE	0
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x3ff00000
+#define CONFIG_SYS_BANK1_END		0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE	0
+#define CONFIG_SYS_BANK2_START		0x3ff00000
+#define CONFIG_SYS_BANK2_END		0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x3ff00000
+#define CONFIG_SYS_BANK3_END		0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x00000000
+#define CONFIG_SYS_BANK4_END		0x00000000
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x00000000
+#define CONFIG_SYS_BANK5_END		0x00000000
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x00000000
+#define CONFIG_SYS_BANK6_END		0x00000000
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x00000000
+#define CONFIG_SYS_BANK7_END		0x00000000
+#define CONFIG_SYS_BANK7_ENABLE	0
 
 /*-----------------------------------------------------------------------
  * Memory bank enable bitmask, specifying which of the banks defined above
  are actually present. MSB is for bank #7, LSB is for bank #0.
  */
-#define CFG_BANK_ENABLE		0x01
+#define CONFIG_SYS_BANK_ENABLE		0x01
 
 #if defined (CONFIG_MPC8240)
-#define CFG_ODCR		0xDF	/* configures line driver impedances,	*/
+#define CONFIG_SYS_ODCR		0xDF	/* configures line driver impedances,	*/
 					/* see 8240 book for bit definitions	*/
 #elif defined (CONFIG_MPC8245)
 #if defined (CONFIG_133MHZ_DRAM)
-#define CFG_ODCR		0xFE	/* configures line driver impedances - 133MHz	*/
+#define CONFIG_SYS_ODCR		0xFE	/* configures line driver impedances - 133MHz	*/
 #else
-#define CFG_ODCR		0xDE	/* configures line driver impedances - 66MHz	*/
+#define CONFIG_SYS_ODCR		0xDE	/* configures line driver impedances - 66MHz	*/
 #endif
 #else
 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 #endif
 
-#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
 					/* currently accessed page in memory	*/
 					/* see 8240 book for details		*/
 
@@ -379,37 +379,37 @@
  * Block Address Translation (BAT) register settings.
  */
 /* SDRAM 0 - 256MB */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* stack in DCACHE @ 1GB (no backing mem) */
-#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 
 /* PCI memory */
-#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* Flash, config addrs, etc */
-#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SIZE	32
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 
@@ -432,15 +432,15 @@
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
  */
-#define CFG_IDE_MAXBUS	    1	/* max. 2 IDE busses	*/
-#define CFG_IDE_MAXDEVICE   (CFG_IDE_MAXBUS*1)	/* max. 2 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS	    1	/* max. 2 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE   (CONFIG_SYS_IDE_MAXBUS*1)	/* max. 2 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR   CFG_ISA_IO	/* base address */
-#define CFG_ATA_IDE0_OFFSET 0x01F0	/* ide0 offste */
-#define CFG_ATA_IDE1_OFFSET 0x0170	/* ide1 offset */
-#define CFG_ATA_DATA_OFFSET 0	/* data reg offset  */
-#define CFG_ATA_REG_OFFSET  0	/* reg offset */
-#define CFG_ATA_ALT_OFFSET  0x200	/* alternate register offset */
+#define CONFIG_SYS_ATA_BASE_ADDR   CONFIG_SYS_ISA_IO	/* base address */
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0	/* ide0 offste */
+#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170	/* ide1 offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET 0	/* data reg offset  */
+#define CONFIG_SYS_ATA_REG_OFFSET  0	/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET  0x200	/* alternate register offset */
 
 #define CONFIG_ATAPI
 
@@ -459,6 +459,6 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/ebony.h b/include/configs/ebony.h
index 3affdd2..10f425d 100644
--- a/include/configs/ebony.h
+++ b/include/configs/ebony.h
@@ -58,31 +58,31 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
-#define CFG_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
-#define CFG_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
-#define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
-#define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
-#define CFG_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/
+#define CONFIG_SYS_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
+#define CONFIG_SYS_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
+#define CONFIG_SYS_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
+#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
+#define CONFIG_SYS_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
+#define CONFIG_SYS_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/
 
-#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
-#define CFG_FPGA_BASE	    (CFG_PERIPHERAL_BASE + 0x08300000)
+#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
+#define CONFIG_SYS_FPGA_BASE	    (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
-#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE  128		    /* num bytes initial data	*/
+#define CONFIG_SYS_INIT_RAM_ADDR   CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE  128		    /* num bytes initial data	*/
 
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
 
 /*-----------------------------------------------------------------------
  * NVRAM/RTC
@@ -91,36 +91,36 @@
  * The DS1743 code assumes this condition (i.e. -- it assumes the base
  * address for the RTC registers is:
  *
- *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *	CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
  *
  *----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
+#define CONFIG_SYS_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
 #define CONFIG_RTC_DS174x	1		    /* DS1743 RTC		*/
 
 #ifdef CONFIG_ENV_IS_IN_NVRAM
 #define CONFIG_ENV_SIZE		0x1000	    /* Size of Environment vars */
 #define CONFIG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE)
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)
 #endif /* CONFIG_ENV_IS_IN_NVRAM */
 
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS	3		    /* number of banks	    */
-#define CFG_MAX_FLASH_SECT	32		    /* sectors per device   */
+#define CONFIG_SYS_MAX_FLASH_BANKS	3		    /* number of banks	    */
+#define CONFIG_SYS_MAX_FLASH_SECT	32		    /* sectors per device   */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-#define CFG_FLASH_ADDR0         0x5555
-#define CFG_FLASH_ADDR1         0x2aaa
-#define CFG_FLASH_WORD_SIZE     unsigned char
+#define CONFIG_SYS_FLASH_ADDR0         0x5555
+#define CONFIG_SYS_FLASH_ADDR1         0x2aaa
+#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector		*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -138,14 +138,13 @@
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 
 /*
  * Default environment variables
@@ -180,12 +179,12 @@
 #define CONFIG_PCI			            /* include pci support	        */
 #define CONFIG_PCI_PNP			        /* do pci plug-and-play         */
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
-#define CFG_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CFG_PCI_MEMBASE */
+#define CONFIG_SYS_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT	            /* let board init pci target    */
+#define CONFIG_SYS_PCI_TARGET_INIT	            /* let board init pci target    */
 
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/ep7312.h b/include/configs/ep7312.h
index 60c87bd..0581842 100644
--- a/include/configs/ep7312.h
+++ b/include/configs/ep7312.h
@@ -41,8 +41,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -97,24 +97,24 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"EP7312 # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"EP7312 # "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0xc0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0xc0500000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0xc0500000	/* default load address	*/
 
-#define	CFG_HZ			2000		/* decrementer freq: 2 kHz */
+#define	CONFIG_SYS_HZ			2000		/* decrementer freq: 2 kHz */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -137,17 +137,17 @@
 #define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
 #define PHYS_FLASH_SIZE		0x01000000 /* 16 MB */
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x20000)	/* Addr of Environment Sector	*/
diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h
index d8f1aaf..f7b3fde 100644
--- a/include/configs/ep8248.h
+++ b/include/configs/ep8248.h
@@ -48,7 +48,7 @@
 #undef	CONFIG_CONS_NONE		/* It's not on external UART */
 #define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */
 
-#define CFG_BCSR		0xFA000000
+#define CONFIG_SYS_BCSR		0xFA000000
 
 /*
  * Select ethernet configuration
@@ -76,10 +76,10 @@
  * - BDs/buffers on 60x bus
  * - Full duplex
  */
-#define CFG_CMXFCR_MASK	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
-#define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
-#define CFG_CPMFCR_RAMTYPE	0
-#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+#define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 
 #elif (CONFIG_ETHER_INDEX == 2)
 
@@ -88,10 +88,10 @@
  * - BDs/buffers on 60x bus
  * - Full duplex
  */
-#define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-#define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-#define CFG_CPMFCR_RAMTYPE	0
-#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+#define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 
 #endif /* CONFIG_ETHER_INDEX */
 
@@ -101,15 +101,15 @@
  * GPIO pins used for bit-banged MII communications
  */
 #define MDIO_PORT		0	/* Not used - implemented in BCSR */
-#define MDIO_ACTIVE		(*(vu_char *)(CFG_BCSR + 8) &= 0xFB)
-#define MDIO_TRISTATE		(*(vu_char *)(CFG_BCSR + 8) |= 0x04)
-#define MDIO_READ		(*(vu_char *)(CFG_BCSR + 8) & 1)
+#define MDIO_ACTIVE		(*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
+#define MDIO_TRISTATE		(*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
+#define MDIO_READ		(*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
 
-#define MDIO(bit)		if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \
-				else	*(vu_char *)(CFG_BCSR + 8) &= 0xFE
+#define MDIO(bit)		if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
+				else	*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
 
-#define MDC(bit)		if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \
-				else	*(vu_char *)(CFG_BCSR + 8) &= 0xFD
+#define MDC(bit)		if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
+				else	*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
 
 #define MIIDELAY		udelay(1)
 
@@ -162,125 +162,125 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size  */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size  */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#define CFG_FLASH_BASE		0xFF800000
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_BASE		0xFF800000
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
-#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
 
-#define	CFG_DIRECT_FLASH_TFTP
+#define	CONFIG_SYS_DIRECT_FLASH_TFTP
 
 #if defined(CONFIG_CMD_JFFS2)
-#define CFG_JFFS2_FIRST_BANK	0
-#define CFG_JFFS2_NUM_BANKS	CFG_MAX_FLASH_BANKS
-#define CFG_JFFS2_FIRST_SECTOR  0
-#define CFG_JFFS2_LAST_SECTOR   62
-#define CFG_JFFS2_SORT_FRAGMENTS
-#define CFG_JFFS_CUSTOM_PART
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#define CONFIG_SYS_JFFS2_NUM_BANKS	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR  0
+#define CONFIG_SYS_JFFS2_LAST_SECTOR   62
+#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
+#define CONFIG_SYS_JFFS_CUSTOM_PART
 #endif
 
 #if defined(CONFIG_CMD_I2C)
 #define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
-#define CFG_I2C_SPEED		100000	/* I2C speed			*/
-#define CFG_I2C_SLAVE		0x7F	/* I2C slave address		*/
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed			*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave address		*/
 #endif
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256KB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256KB for Monitor */
 
 #define CONFIG_ENV_IS_IN_FLASH
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #endif /* CONFIG_ENV_IS_IN_FLASH */
 
-#define CFG_DEFAULT_IMMR	0x00010000
+#define CONFIG_SYS_DEFAULT_IMMR	0x00010000
 
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR		0xF0000000
 
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* Hard reset configuration word */
-#define CFG_HRCW_MASTER		0x0C40025A /* Not used - provided by FPGA */
+#define CONFIG_SYS_HRCW_MASTER		0x0C40025A /* Not used - provided by FPGA */
 /* No slaves */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot                  */
 
-#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
 
-#define CFG_HID2		0
+#define CONFIG_SYS_HID2		0
 
-#define CFG_SIUMCR		0x01240200
-#define CFG_SYPCR		0xFFFF0683
-#define CFG_BCR			0x00000000
-#define CFG_SCCR		SCCR_DFBRG01
+#define CONFIG_SYS_SIUMCR		0x01240200
+#define CONFIG_SYS_SYPCR		0xFFFF0683
+#define CONFIG_SYS_BCR			0x00000000
+#define CONFIG_SYS_SCCR		SCCR_DFBRG01
 
-#define CFG_RMR			RMR_CSRE
-#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CFG_RCCR		0
+#define CONFIG_SYS_RMR			RMR_CSRE
+#define CONFIG_SYS_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_RCCR		0
 
-#define CFG_MPTPR		0x1300
-#define CFG_PSDMR		0x82672522
-#define CFG_PSRT		0x4B
+#define CONFIG_SYS_MPTPR		0x1300
+#define CONFIG_SYS_PSDMR		0x82672522
+#define CONFIG_SYS_PSRT		0x4B
 
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_BR		(CFG_SDRAM_BASE | 0x00001841)
-#define CFG_SDRAM_OR		0xFF0030C0
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BR		(CONFIG_SYS_SDRAM_BASE | 0x00001841)
+#define CONFIG_SYS_SDRAM_OR		0xFF0030C0
 
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | 0x00001801)
-#define CFG_OR0_PRELIM		0xFF8008C2
-#define CFG_BR2_PRELIM		(CFG_BCSR | 0x00000801)
-#define CFG_OR2_PRELIM		0xFFF00864
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | 0x00001801)
+#define CONFIG_SYS_OR0_PRELIM		0xFF8008C2
+#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_BCSR | 0x00000801)
+#define CONFIG_SYS_OR2_PRELIM		0xFFF00864
 
-#define CFG_RESET_ADDRESS	0xC0000000
+#define CONFIG_SYS_RESET_ADDRESS	0xC0000000
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h
index 9a602c3..d49d02f 100644
--- a/include/configs/ep8260.h
+++ b/include/configs/ep8260.h
@@ -33,7 +33,7 @@
  *	- 16M Flash (4 x AM29DL323DB90WDI)
  *	- 128k NVRAM with RTC
  *
- * "EP8260 H2, V.1.3" (CFG_EP8260_H2)
+ * "EP8260 H2, V.1.3" (CONFIG_SYS_EP8260_H2)
  *	- 300MHz/133MHz/66MHz
  *	- 64M 60x Bus SDRAM
  *	- 32M Local Bus SDRAM
@@ -45,8 +45,8 @@
 #define __CONFIG_H
 
 /* Define this to enable support the EP8260 H2 version */
-#define CFG_EP8260_H2	1
-/* #undef CFG_EP8260_H2  */
+#define CONFIG_SYS_EP8260_H2	1
+/* #undef CONFIG_SYS_EP8260_H2  */
 
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
@@ -75,10 +75,10 @@
  * 0x6	     0x1	 66	133    266
  * 0x6	     0x2	 66	133    300
  */
-#ifdef CFG_EP8260_H2
-#define CFG_SBC_MODCK_H  (HRCW_MODCK_H0110)
+#ifdef CONFIG_SYS_EP8260_H2
+#define CONFIG_SYS_SBC_MODCK_H  (HRCW_MODCK_H0110)
 #else
-#define CFG_SBC_MODCK_H  (HRCW_MODCK_H0110)
+#define CONFIG_SYS_SBC_MODCK_H  (HRCW_MODCK_H0110)
 #endif
 
 /* Define this if you want to boot from 0x00000100. If you don't define
@@ -87,26 +87,26 @@
  * way to do that is to program the bootloader at both addresses.
  * It is suggested that you just let U-Boot live at 0x00000000.
  */
-/* #define CFG_SBC_BOOT_LOW 1 */	/* only for HRCW */
-/* #undef CFG_SBC_BOOT_LOW */
+/* #define CONFIG_SYS_SBC_BOOT_LOW 1 */	/* only for HRCW */
+/* #undef CONFIG_SYS_SBC_BOOT_LOW */
 
 /* The reset command will not work as expected if the reset address does
  * not point to the correct address.
  */
 
-#define CFG_RESET_ADDRESS	0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
 
 /* What should the base address of the main FLASH be and how big is
  * it (in MBytes)? This must contain TEXT_BASE from board/ep8260/config.mk
  * The main FLASH is whichever is connected to *CS0. U-Boot expects
  * this to be the SIMM.
  */
-#ifdef CFG_EP8260_H2
-#define CFG_FLASH0_BASE 0xFE000000
-#define CFG_FLASH0_SIZE 32
+#ifdef CONFIG_SYS_EP8260_H2
+#define CONFIG_SYS_FLASH0_BASE 0xFE000000
+#define CONFIG_SYS_FLASH0_SIZE 32
 #else
-#define CFG_FLASH0_BASE 0xFF000000
-#define CFG_FLASH0_SIZE 16
+#define CONFIG_SYS_FLASH0_BASE 0xFF000000
+#define CONFIG_SYS_FLASH0_SIZE 16
 #endif
 
 /* What should the base address of the secondary FLASH be and how big
@@ -114,41 +114,41 @@
  * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
  * want it enabled, don't define these constants.
  */
-#define CFG_FLASH1_BASE 0
-#define CFG_FLASH1_SIZE 0
-#undef CFG_FLASH1_BASE
-#undef CFG_FLASH1_SIZE
+#define CONFIG_SYS_FLASH1_BASE 0
+#define CONFIG_SYS_FLASH1_SIZE 0
+#undef CONFIG_SYS_FLASH1_BASE
+#undef CONFIG_SYS_FLASH1_SIZE
 
 /* What should be the base address of SDRAM DIMM (60x bus) and how big is
  * it (in Mbytes)?
 */
-#define CFG_SDRAM0_BASE 0x00000000
-#define CFG_SDRAM0_SIZE 64
+#define CONFIG_SYS_SDRAM0_BASE 0x00000000
+#define CONFIG_SYS_SDRAM0_SIZE 64
 
-/* define CFG_LSDRAM if you want to enable the 32M SDRAM on the
+/* define CONFIG_SYS_LSDRAM if you want to enable the 32M SDRAM on the
  * local bus (8260 local bus is NOT cacheable!)
 */
-/* #define CFG_LSDRAM */
-#undef CFG_LSDRAM
+/* #define CONFIG_SYS_LSDRAM */
+#undef CONFIG_SYS_LSDRAM
 
-#ifdef CFG_LSDRAM
+#ifdef CONFIG_SYS_LSDRAM
 /* What should be the base address of SDRAM DIMM (local bus) and how big is
  * it (in Mbytes)?
 */
-  #define CFG_SDRAM1_BASE 0x04000000
-  #define CFG_SDRAM1_SIZE 32
+  #define CONFIG_SYS_SDRAM1_BASE 0x04000000
+  #define CONFIG_SYS_SDRAM1_SIZE 32
 #else
-  #define CFG_SDRAM1_BASE 0
-  #define CFG_SDRAM1_SIZE 0
-  #undef CFG_SDRAM1_BASE
-  #undef CFG_SDRAM1_SIZE
-#endif /* CFG_LSDRAM */
+  #define CONFIG_SYS_SDRAM1_BASE 0
+  #define CONFIG_SYS_SDRAM1_SIZE 0
+  #undef CONFIG_SYS_SDRAM1_BASE
+  #undef CONFIG_SYS_SDRAM1_SIZE
+#endif /* CONFIG_SYS_LSDRAM */
 
 /* What should be the base address of NVRAM and how big is
  * it (in Bytes)
  */
-#define CFG_NVRAM_BASE_ADDR  0xFA080000
-#define CFG_NVRAM_SIZE       (128*1024)-16
+#define CONFIG_SYS_NVRAM_BASE_ADDR  0xFA080000
+#define CONFIG_SYS_NVRAM_SIZE       (128*1024)-16
 
 /* The RTC is a Dallas DS1556
  */
@@ -157,8 +157,8 @@
 /* What should be the base address of the LEDs and switch S0?
  * If you don't want them enabled, don't define this.
  */
-#define CFG_LED_BASE 0x00000000
-#undef CFG_LED_BASE
+#define CONFIG_SYS_LED_BASE 0x00000000
+#undef CONFIG_SYS_LED_BASE
 
 /*
  * select serial console configuration
@@ -198,21 +198,21 @@
  * - RAM for BD/Buffers is on the local Bus (see 28-13)
  * - Enable Half Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 
 /*
  * - RAM for BD/Buffers is on the local Bus (see 28-13)
  */
-#ifdef CFG_LSDRAM
-  #define CFG_CPMFCR_RAMTYPE	3
-#else /* CFG_LSDRAM */
-  #define CFG_CPMFCR_RAMTYPE	0
-#endif /* CFG_LSDRAM */
+#ifdef CONFIG_SYS_LSDRAM
+  #define CONFIG_SYS_CPMFCR_RAMTYPE	3
+#else /* CONFIG_SYS_LSDRAM */
+  #define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#endif /* CONFIG_SYS_LSDRAM */
 
 /* - Enable Half Duplex in FSMR */
-/* # define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB) */
-# define CFG_FCC_PSMR		0
+/* # define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB) */
+# define CONFIG_SYS_FCC_PSMR		0
 
 #else /* CONFIG_ETHER_INDEX */
 # error "on EP8260 ethernet must be FCC3"
@@ -227,8 +227,8 @@
  */
 #undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * Software (bit-bang) I2C driver configuration
@@ -258,7 +258,7 @@
 #define CONFIG_ENV_OVERWRITE
 
 /* What should the console's baud rate be? */
-#ifdef CFG_EP8260_H2
+#ifdef CONFIG_SYS_EP8260_H2
 #define CONFIG_BAUDRATE         9600
 #else
 #define CONFIG_BAUDRATE         115200
@@ -274,10 +274,10 @@
 #define CONFIG_BOOTDELAY        -1
 
 /* undef this to save memory */
-#define CFG_LONGHELP
+#define CONFIG_SYS_LONGHELP
 
 /* Monitor Command Prompt       */
-#define CFG_PROMPT              "=> "
+#define CONFIG_SYS_PROMPT              "=> "
 
 /* Define this variable to enable the "hush" shell (from
    Busybox) as command line interpreter, thus enabling
@@ -287,8 +287,8 @@
    If undefined, you get the old, much simpler behaviour
    with a somewhat smapper memory footprint.
 */
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 
 /*
@@ -327,11 +327,11 @@
 #undef CONFIG_CMD_XIMG
 
 /* Where do the internal registers live? */
-#define CFG_IMMR               0xF0000000
-#define CFG_DEFAULT_IMMR       0x00010000
+#define CONFIG_SYS_IMMR               0xF0000000
+#define CONFIG_SYS_DEFAULT_IMMR       0x00010000
 
 /* Where do the on board registers (CS4) live? */
-#define CFG_REGS_BASE          0xFA000000
+#define CONFIG_SYS_REGS_BASE          0xFA000000
 
 /*****************************************************************************
  *
@@ -348,35 +348,35 @@
  * Miscellaneous configurable options
  */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CBSIZE              1024       /* Console I/O Buffer Size      */
+#  define CONFIG_SYS_CBSIZE              1024       /* Console I/O Buffer Size      */
 #else
-#  define CFG_CBSIZE              256        /* Console I/O Buffer Size      */
+#  define CONFIG_SYS_CBSIZE              256        /* Console I/O Buffer Size      */
 #endif
 
 /* Print Buffer Size */
-#define CFG_PBSIZE        (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
+#define CONFIG_SYS_PBSIZE        (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 
-#define CFG_MAXARGS       8            /* max number of command args   */
+#define CONFIG_SYS_MAXARGS       8            /* max number of command args   */
 
-#define CFG_BARGSIZE      CFG_CBSIZE   /* Boot Argument Buffer Size    */
+#define CONFIG_SYS_BARGSIZE      CONFIG_SYS_CBSIZE   /* Boot Argument Buffer Size    */
 
-#ifdef CFG_LSDRAM
-  #define CFG_MEMTEST_START 0x04000000   /* memtest works on  */
-  #define CFG_MEMTEST_END   0x06000000   /* 64-96 MB in SDRAM */
+#ifdef CONFIG_SYS_LSDRAM
+  #define CONFIG_SYS_MEMTEST_START 0x04000000   /* memtest works on  */
+  #define CONFIG_SYS_MEMTEST_END   0x06000000   /* 64-96 MB in SDRAM */
 #else
-  #define CFG_MEMTEST_START 0x00000000   /* memtest works on  */
-  #define CFG_MEMTEST_END   0x02000000   /* 0-32 MB in SDRAM */
-#endif /* CFG_LSDRAM */
+  #define CONFIG_SYS_MEMTEST_START 0x00000000   /* memtest works on  */
+  #define CONFIG_SYS_MEMTEST_END   0x02000000   /* 0-32 MB in SDRAM */
+#endif /* CONFIG_SYS_LSDRAM */
 
 #define	CONFIG_CLOCKS_IN_MHZ	1      /* clocks passsed to Linux in MHz */
 
-#define CFG_LOAD_ADDR     0x00100000   /* default load address */
-#define CFG_TFTP_LOADADDR 0x00100000   /* default load address for network file downloads */
+#define CONFIG_SYS_LOAD_ADDR     0x00100000   /* default load address */
+#define CONFIG_SYS_TFTP_LOADADDR 0x00100000   /* default load address for network file downloads */
 
-#define CFG_HZ            1000         /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ            1000         /* decrementer freq: 1 ms ticks */
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -384,119 +384,119 @@
  * You should know what you are doing if you make changes here.
  */
 
-#define CFG_FLASH_BASE    CFG_FLASH0_BASE
-#define CFG_SDRAM_BASE    CFG_SDRAM0_BASE
+#define CONFIG_SYS_FLASH_BASE    CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_SDRAM_BASE    CONFIG_SYS_SDRAM0_BASE
 
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  */
 
-#if defined(CFG_SBC_BOOT_LOW)
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#if defined(CONFIG_SYS_SBC_BOOT_LOW)
+#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 #else
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (0x00000000)
-#endif /* defined(CFG_SBC_BOOT_LOW) */
+#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (0x00000000)
+#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
 
-#ifdef CFG_EP8260_H2
-/* get the HRCW ISB field from CFG_DEFAULT_IMMR */
-#define CFG_SBC_HRCW_IMMR ( ((CFG_DEFAULT_IMMR & 0x10000000) >> 10) |\
-			    ((CFG_DEFAULT_IMMR & 0x01000000) >> 7)  |\
-			    ((CFG_DEFAULT_IMMR & 0x00100000) >> 4) )
+#ifdef CONFIG_SYS_EP8260_H2
+/* get the HRCW ISB field from CONFIG_SYS_DEFAULT_IMMR */
+#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_DEFAULT_IMMR & 0x10000000) >> 10) |\
+			    ((CONFIG_SYS_DEFAULT_IMMR & 0x01000000) >> 7)  |\
+			    ((CONFIG_SYS_DEFAULT_IMMR & 0x00100000) >> 4) )
 
-#define CFG_HRCW_MASTER (HRCW_EBM                |\
+#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM                |\
 			 HRCW_L2CPC01            |\
-			 CFG_SBC_HRCW_IMMR       |\
+			 CONFIG_SYS_SBC_HRCW_IMMR       |\
 			 HRCW_APPC10             |\
 			 HRCW_CS10PC01           |\
-			 CFG_SBC_MODCK_H	 |\
-			 CFG_SBC_HRCW_BOOT_FLAGS)
+			 CONFIG_SYS_SBC_MODCK_H	 |\
+			 CONFIG_SYS_SBC_HRCW_BOOT_FLAGS)
 #else
-#define CFG_HRCW_MASTER 0x10400245
+#define CONFIG_SYS_HRCW_MASTER 0x10400245
 #endif
 
 /* no slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
+#define CONFIG_SYS_HRCW_SLAVE1 0
+#define CONFIG_SYS_HRCW_SLAVE2 0
+#define CONFIG_SYS_HRCW_SLAVE3 0
+#define CONFIG_SYS_HRCW_SLAVE4 0
+#define CONFIG_SYS_HRCW_SLAVE5 0
+#define CONFIG_SYS_HRCW_SLAVE6 0
+#define CONFIG_SYS_HRCW_SLAVE7 0
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR       CFG_IMMR
-#define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE      128     /* bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_SIZE      128     /* bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
  */
-#define CFG_MONITOR_BASE          TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE          TEXT_BASE
 
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#  define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#  define CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */
-#define CFG_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS   1       /* max number of memory banks         */
-#ifdef CFG_EP8260_H2
-#define CFG_MAX_FLASH_SECT    128      /* max number of sectors on one chip  */
+#define CONFIG_SYS_MAX_FLASH_BANKS   1       /* max number of memory banks         */
+#ifdef CONFIG_SYS_EP8260_H2
+#define CONFIG_SYS_MAX_FLASH_SECT    128      /* max number of sectors on one chip  */
 #else
-#define CFG_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */
+#define CONFIG_SYS_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */
 #endif
 
-#ifdef CFG_EP8260_H2
-#define CFG_FLASH_ERASE_TOUT  240000  /* Timeout for Flash Erase (in ms)    */
-#define CFG_FLASH_WRITE_TOUT  500     /* Timeout for Flash Write (in ms)    */
+#ifdef CONFIG_SYS_EP8260_H2
+#define CONFIG_SYS_FLASH_ERASE_TOUT  240000  /* Timeout for Flash Erase (in ms)    */
+#define CONFIG_SYS_FLASH_WRITE_TOUT  500     /* Timeout for Flash Write (in ms)    */
 #else
-#define CFG_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
-#define CFG_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */
+#define CONFIG_SYS_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
+#define CONFIG_SYS_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */
 #endif
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 #  define CONFIG_ENV_IS_IN_FLASH  1
 
 #  ifdef CONFIG_ENV_IN_OWN_SECT
-#    define CONFIG_ENV_ADDR       (CFG_MONITOR_BASE + 0x40000)
+#    define CONFIG_ENV_ADDR       (CONFIG_SYS_MONITOR_BASE + 0x40000)
 #    define CONFIG_ENV_SECT_SIZE  0x40000
 #  else
-#    define CONFIG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
+#    define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
 #    define CONFIG_ENV_SIZE       0x1000  /* Total Size of Environment Sector */
 #    define CONFIG_ENV_SECT_SIZE  0x10000 /* see README - env sect real size */
 #  endif /* CONFIG_ENV_IN_OWN_SECT */
 #else
 #  define CONFIG_ENV_IS_IN_NVRAM  1
-#  define CONFIG_ENV_ADDR         (CFG_MONITOR_BASE - 0x1000)
+#  define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 #  define CONFIG_ENV_SIZE         0x200
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
+#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT     5     /* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT     5     /* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -509,38 +509,38 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT   (HID0_ICE  |\
+#define CONFIG_SYS_HID0_INIT   (HID0_ICE  |\
 			 HID0_DCE  |\
 			 HID0_ICFI |\
 			 HID0_DCI  |\
 			 HID0_IFEM |\
 			 HID0_ABE)
-#ifdef CFG_LSDRAM
+#ifdef CONFIG_SYS_LSDRAM
 /* 8260 local bus is NOT cacheable */
-#define CFG_HID0_FINAL  (/*HID0_ICE  |*/\
+#define CONFIG_SYS_HID0_FINAL  (/*HID0_ICE  |*/\
 			 HID0_IFEM |\
 			 HID0_ABE  |\
 			 HID0_EMCP)
-#else /* !CFG_LSDRAM */
-#define CFG_HID0_FINAL  (HID0_ICE  |\
+#else /* !CONFIG_SYS_LSDRAM */
+#define CONFIG_SYS_HID0_FINAL  (HID0_ICE  |\
 			 HID0_IFEM |\
 			 HID0_ABE  |\
 			 HID0_EMCP)
-#endif /* CFG_LSDRAM */
+#endif /* CONFIG_SYS_LSDRAM */
 
-#define CFG_HID2        0
+#define CONFIG_SYS_HID2        0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register
  *-----------------------------------------------------------------------
  */
-#define CFG_RMR         0
+#define CONFIG_SYS_RMR         0
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration                                       4-25
  *-----------------------------------------------------------------------
  */
-#define CFG_BCR         (BCR_EBM   |\
+#define CONFIG_SYS_BCR         (BCR_EBM   |\
 			 BCR_PLDP  |\
 			 BCR_EAV   |\
 			 BCR_NPQM0)
@@ -549,7 +549,7 @@
  * SIUMCR - SIU Module Configuration                             4-31
  *-----------------------------------------------------------------------
  */
-#define CFG_SIUMCR      (SIUMCR_L2CPC01 |\
+#define CONFIG_SYS_SIUMCR      (SIUMCR_L2CPC01 |\
 			 SIUMCR_APPC10  |\
 			 SIUMCR_CS10PC01)
 
@@ -559,25 +559,25 @@
  *-----------------------------------------------------------------------
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
-#ifdef CFG_EP8260_H2
+#ifdef CONFIG_SYS_EP8260_H2
 /* TBD: Find out why setting the BMT to 0xff causes the FCC to
  * generate TX buffer underrun errors for large packets under
  * Linux
  */
-#define CFG_SYPCR_BMT	0x00000600
+#define CONFIG_SYS_SYPCR_BMT	0x00000600
 #else
-#define CFG_SYPCR_BMT	SYPCR_BMT
+#define CONFIG_SYS_SYPCR_BMT	SYPCR_BMT
 #endif
 
-#ifdef CFG_LSDRAM
-#define CFG_SYPCR       (SYPCR_SWTC |\
-			 CFG_SYPCR_BMT  |\
+#ifdef CONFIG_SYS_LSDRAM
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC |\
+			 CONFIG_SYS_SYPCR_BMT  |\
 			 SYPCR_PBME |\
 			 SYPCR_LBME |\
 			 SYPCR_SWP)
 #else
-#define CFG_SYPCR       (SYPCR_SWTC |\
-			 CFG_SYPCR_BMT  |\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC |\
+			 CONFIG_SYS_SYPCR_BMT  |\
 			 SYPCR_PBME |\
 			 SYPCR_SWP)
 #endif
@@ -588,7 +588,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC     (TMCNTSC_SEC |\
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC |\
 			 TMCNTSC_ALR |\
 			 TMCNTSC_TCF |\
 			 TMCNTSC_TCE)
@@ -599,35 +599,35 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#ifdef CFG_EP8260_H2
-#define CFG_PISCR       (PISCR_PS  |\
+#ifdef CONFIG_SYS_EP8260_H2
+#define CONFIG_SYS_PISCR       (PISCR_PS  |\
 			 PISCR_PTF |\
 			 PISCR_PTE)
 #else
-#define CFG_PISCR	0
+#define CONFIG_SYS_PISCR	0
 #endif
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control                                   9-8
  *-----------------------------------------------------------------------
  */
-#ifdef CFG_EP8260_H2
-#define CFG_SCCR        (SCCR_DFBRG00)
+#ifdef CONFIG_SYS_EP8260_H2
+#define CONFIG_SYS_SCCR        (SCCR_DFBRG00)
 #else
-#define CFG_SCCR        (SCCR_DFBRG01)
+#define CONFIG_SYS_SCCR        (SCCR_DFBRG01)
 #endif
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration                         13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR        0
+#define CONFIG_SYS_RCCR        0
 
 /*-----------------------------------------------------------------------
  * MPTPR - Memory Refresh Timer Prescale Register               10-32
  *-----------------------------------------------------------------------
  */
-#define CFG_MPTPR	(0x0A00 & MPTPR_PTP_MSK)
+#define CONFIG_SYS_MPTPR	(0x0A00 & MPTPR_PTP_MSK)
 
 /*
  * Init Memory Controller:
@@ -659,13 +659,13 @@
 /* Bank 0 - FLASH
  *
  */
-#define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
 			 BRx_PS_64                      |\
 			 BRx_DECC_NONE                  |\
 			 BRx_MS_GPCM_P                  |\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE)     |\
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE)     |\
 			 ORxG_CSNT                      |\
 			 ORxG_ACS_DIV1                  |\
 			 ORxG_SCY_8_CLK                 |\
@@ -674,71 +674,71 @@
 /* Bank 1 - SDRAM
  * PSDRAM
  */
-#define CFG_BR1_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
 			 BRx_PS_64                      |\
 			 BRx_MS_SDRAM_P                 |\
 			 BRx_V)
 
-#define CFG_OR1_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE)     |\
+#define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE)     |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI1_A6             |\
 			 ORxS_NUMR_12)
 
-#ifdef CFG_EP8260_H2
-#define CFG_PSDMR       0xC34E246E
+#ifdef CONFIG_SYS_EP8260_H2
+#define CONFIG_SYS_PSDMR       0xC34E246E
 #else
-#define CFG_PSDMR       0xC34E2462
+#define CONFIG_SYS_PSDMR       0xC34E2462
 #endif
 
-#define CFG_PSRT	0x64
+#define CONFIG_SYS_PSRT	0x64
 
-#ifdef CFG_LSDRAM
+#ifdef CONFIG_SYS_LSDRAM
 /* Bank 2 - SDRAM
  * LSDRAM
  */
 
-  #define CFG_BR2_PRELIM  ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
+  #define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
 			   BRx_PS_32                      |\
 			   BRx_MS_SDRAM_L                 |\
 			   BRx_V)
 
-  #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM1_SIZE)     |\
+  #define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE)     |\
 			   ORxS_BPD_4                     |\
 			   ORxS_ROWST_PBI0_A9             |\
 			   ORxS_NUMR_12)
 
-  #define CFG_LSDMR      0x416A2562
-  #define CFG_LSRT	0x64
+  #define CONFIG_SYS_LSDMR      0x416A2562
+  #define CONFIG_SYS_LSRT	0x64
 #else
-  #define CFG_LSRT	0x0
-#endif /* CFG_LSDRAM */
+  #define CONFIG_SYS_LSRT	0x0
+#endif /* CONFIG_SYS_LSDRAM */
 
 /* Bank 4 - On board registers
  * NVRTC and BCSR
  */
-#define CFG_BR4_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
+#define CONFIG_SYS_BR4_PRELIM   ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK)  |\
 			   BRx_PS_8                     |\
 			   BRx_MS_GPCM_P                |\
 			   BRx_V)
 /*
-#define CFG_OR4_PRELIM    (ORxG_AM_MSK                 |\
+#define CONFIG_SYS_OR4_PRELIM    (ORxG_AM_MSK                 |\
 			   ORxG_CSNT                   |\
 			   ORxG_ACS_DIV1               |\
 			   ORxG_SCY_10_CLK              |\
 			   ORxG_TRLX)
 */
-#define CFG_OR4_PRELIM 0xfff00854
+#define CONFIG_SYS_OR4_PRELIM 0xfff00854
 
 #ifdef _NOT_USED_SINCE_NOT_WORKING_
 /* Bank 8 - On board registers
  * PCMCIA (currently not working!)
  */
-#define CFG_BR8_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
+#define CONFIG_SYS_BR8_PRELIM   ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK)  |\
 			   BRx_PS_16                     |\
 			   BRx_MS_GPCM_P                |\
 			   BRx_V)
 
-#define CFG_OR8_PRELIM    (ORxG_AM_MSK                 |\
+#define CONFIG_SYS_OR8_PRELIM    (ORxG_AM_MSK                 |\
 			   ORxG_CSNT                   |\
 			   ORxG_ACS_DIV1               |\
 			   ORxG_SETA                   |\
diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h
index a501900..239ff67 100644
--- a/include/configs/ep82xxm.h
+++ b/include/configs/ep82xxm.h
@@ -48,7 +48,7 @@
 #undef	CONFIG_CONS_NONE		/* It's not on external UART */
 #define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */
 
-#define CFG_BCSR		0xFA000000
+#define CONFIG_SYS_BCSR		0xFA000000
 
 /*
  * Select ethernet configuration
@@ -70,13 +70,13 @@
 #define CONFIG_ETHER_ON_FCC2
 #define CONFIG_ETHER_ON_FCC3
 
-#define CFG_CMXFCR_MASK3	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
-#define CFG_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16)
-#define CFG_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-#define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+#define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16)
+#define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 
-#define CFG_CPMFCR_RAMTYPE	0
-#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 
 #define CONFIG_MII			/* MII PHY management        */
 #define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */
@@ -85,15 +85,15 @@
  * GPIO pins used for bit-banged MII communications
  */
 #define MDIO_PORT		0	/* Not used - implemented in BCSR */
-#define MDIO_ACTIVE		(*(vu_char *)(CFG_BCSR + 8) &= 0xFB)
-#define MDIO_TRISTATE		(*(vu_char *)(CFG_BCSR + 8) |= 0x04)
-#define MDIO_READ		(*(vu_char *)(CFG_BCSR + 8) & 1)
+#define MDIO_ACTIVE		(*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
+#define MDIO_TRISTATE		(*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
+#define MDIO_READ		(*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
 
-#define MDIO(bit)		if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \
-				else	*(vu_char *)(CFG_BCSR + 8) &= 0xFE
+#define MDIO(bit)		if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
+				else	*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
 
-#define MDC(bit)		if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \
-				else	*(vu_char *)(CFG_BCSR + 8) &= 0xFD
+#define MDC(bit)		if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
+				else	*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
 
 #define MIIDELAY		udelay(1)
 
@@ -104,7 +104,7 @@
 
 #define CONFIG_BAUDRATE		115200
 
-#define CFG_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
+#define CONFIG_SYS_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
 
 
 /*
@@ -162,27 +162,27 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"ep82xxm=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"ep82xxm=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size  */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size  */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*-----------------------------------------------------------------------
  * Environment
@@ -200,28 +200,27 @@
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE		0xFC000000
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
-#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector in flinfo */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector in flinfo */
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #endif /* CONFIG_ENV_IS_IN_FLASH */
 
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
 /* EEPROM Configuration */
-#define CFG_EEPROM_SIZE	0x1000
-#define CFG_I2C_EEPROM_ADDR	0x54
-#define CFG_I2C_EEPROM_ADDR_LEN	1
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_EEPROM_SIZE	0x1000
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 
 #ifdef CONFIG_ENV_IS_IN_EEPROM
 #define CONFIG_ENV_SIZE		0x200	    /* Size of Environment vars */
@@ -230,22 +229,22 @@
 
 /* RTC Configuration */
 #define CONFIG_RTC_M41T11	1	/* uses a M41T81 */
-#define CFG_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
 #define CONFIG_M41T11_BASE_YEAR	1900
 
 /* I2C SYSMON (LM75) */
 #define CONFIG_DTT_LM75		1
 #define CONFIG_DTT_SENSORS	{0}
-#define CFG_DTT_MAX_TEMP	70
-#define CFG_DTT_LOW_TEMP	-30
-#define	CFG_DTT_HYSTERESIS	3
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define	CONFIG_SYS_DTT_HYSTERESIS	3
 
 /*-----------------------------------------------------------------------
  * NVRAM Configuration
  *-----------------------------------------------------------------------
  */
-#define CFG_NVRAM_BASE_ADDR	0xFA080000
-#define CFG_NVRAM_SIZE		(128*1024)-16
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xFA080000
+#define CONFIG_SYS_NVRAM_SIZE		(128*1024)-16
 
 
 /*-----------------------------------------------------------------------
@@ -259,9 +258,9 @@
 #define CONFIG_PCI_BOOTDELAY	0
 
 /* PCI Memory map (if different from default map */
-#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */
-#define CFG_PCI_SLV_MEM_BUS		0x00000000	/* PCI base */
-#define CFG_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE		/* Local base */
+#define CONFIG_SYS_PCI_SLV_MEM_BUS		0x00000000	/* PCI base */
+#define CONFIG_SYS_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
 				 PICMR_PREFETCH_EN)
 
 /*
@@ -277,11 +276,11 @@
  * in the bridge.
  */
 
-#define CFG_PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
-#define CFG_PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
-#define	CFG_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
-#define CFG_PCI_MSTR_MEM_SIZE	0x20000000          /* 512MB */
-#define CFG_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
+#define CONFIG_SYS_PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
+#define	CONFIG_SYS_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
+#define CONFIG_SYS_PCI_MSTR_MEM_SIZE	0x20000000          /* 512MB */
+#define CONFIG_SYS_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 
 /*
  * Master window that allows the CPU to access PCI Memory (non-prefetch).
@@ -289,11 +288,11 @@
  * in the bridge.
  */
 
-#define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
-#define CFG_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
-#define CFG_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
-#define CFG_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
-#define CFG_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
+#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
+#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
+#define CONFIG_SYS_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
+#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
+#define CONFIG_SYS_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
 
 /*
  * Master window that allows the CPU to access PCI IO space.
@@ -301,105 +300,105 @@
  * in the bridge.
  */
 
-#define CFG_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
-#define CFG_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
-#define CFG_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
-#define CFG_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
-#define CFG_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
+#define CONFIG_SYS_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
+#define CONFIG_SYS_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
+#define CONFIG_SYS_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
+#define CONFIG_SYS_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
+#define CONFIG_SYS_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
 
 
 /* PCIBR0 - for PCI IO*/
-#define CFG_PCI_MSTR0_LOCAL		CFG_PCI_MSTR_IO_LOCAL		/* Local base */
-#define CFG_PCIMSK0_MASK		~(CFG_PCI_MSTR_IO_SIZE - 1U)	/* Size of window */
+#define CONFIG_SYS_PCI_MSTR0_LOCAL		CONFIG_SYS_PCI_MSTR_IO_LOCAL		/* Local base */
+#define CONFIG_SYS_PCIMSK0_MASK		~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U)	/* Size of window */
 /* PCIBR1 - prefetch and non-prefetch regions joined together */
-#define CFG_PCI_MSTR1_LOCAL		CFG_PCI_MSTR_MEM_LOCAL
-#define CFG_PCIMSK1_MASK		~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U)
+#define CONFIG_SYS_PCI_MSTR1_LOCAL		CONFIG_SYS_PCI_MSTR_MEM_LOCAL
+#define CONFIG_SYS_PCIMSK1_MASK		~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
 
 
-#define	CFG_DIRECT_FLASH_TFTP
+#define	CONFIG_SYS_DIRECT_FLASH_TFTP
 
 #if defined(CONFIG_CMD_JFFS2)
-#define CFG_JFFS2_FIRST_BANK	0
-#define CFG_JFFS2_NUM_BANKS	CFG_MAX_FLASH_BANKS
-#define CFG_JFFS2_FIRST_SECTOR  0
-#define CFG_JFFS2_LAST_SECTOR   62
-#define CFG_JFFS2_SORT_FRAGMENTS
-#define CFG_JFFS_CUSTOM_PART
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#define CONFIG_SYS_JFFS2_NUM_BANKS	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR  0
+#define CONFIG_SYS_JFFS2_LAST_SECTOR   62
+#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
+#define CONFIG_SYS_JFFS_CUSTOM_PART
 #endif
 
 #if defined(CONFIG_CMD_I2C)
 #define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
-#define CFG_I2C_SPEED		100000	/* I2C speed			*/
-#define CFG_I2C_SLAVE		0x7F	/* I2C slave address		*/
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed			*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave address		*/
 #endif
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN		(512 << 10)	/* Reserve 256KB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 256KB for Monitor */
 
-#define CFG_DEFAULT_IMMR	0x00010000
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_DEFAULT_IMMR	0x00010000
+#define CONFIG_SYS_IMMR		0xF0000000
 
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 
 /* Hard reset configuration word */
-#define CFG_HRCW_MASTER		0 /*0x1C800641*/  /* Not used - provided by CPLD */
+#define CONFIG_SYS_HRCW_MASTER		0 /*0x1C800641*/  /* Not used - provided by CPLD */
 /* No slaves */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot                  */
 
-#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
 
-#define CFG_HID2		0
+#define CONFIG_SYS_HID2		0
 
-#define CFG_SIUMCR		0x02610000
-#define CFG_SYPCR		0xFFFF0689
-#define CFG_BCR			0x8080E000
-#define CFG_SCCR		0x00000001
+#define CONFIG_SYS_SIUMCR		0x02610000
+#define CONFIG_SYS_SYPCR		0xFFFF0689
+#define CONFIG_SYS_BCR			0x8080E000
+#define CONFIG_SYS_SCCR		0x00000001
 
-#define CFG_RMR			0
-#define CFG_TMCNTSC		0x000000C3
-#define CFG_PISCR		0x00000083
-#define CFG_RCCR		0
+#define CONFIG_SYS_RMR			0
+#define CONFIG_SYS_TMCNTSC		0x000000C3
+#define CONFIG_SYS_PISCR		0x00000083
+#define CONFIG_SYS_RCCR		0
 
-#define CFG_MPTPR		0x0A00
-#define CFG_PSDMR		0xC432246E
-#define CFG_PSRT		0x32
+#define CONFIG_SYS_MPTPR		0x0A00
+#define CONFIG_SYS_PSDMR		0xC432246E
+#define CONFIG_SYS_PSRT		0x32
 
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_BR		(CFG_SDRAM_BASE | 0x00000041)
-#define CFG_SDRAM_OR		0xF0002900
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BR		(CONFIG_SYS_SDRAM_BASE | 0x00000041)
+#define CONFIG_SYS_SDRAM_OR		0xF0002900
 
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | 0x00001801)
-#define CFG_OR0_PRELIM		0xFC000882
-#define CFG_BR4_PRELIM		(CFG_BCSR | 0x00001001)
-#define CFG_OR4_PRELIM		0xFFF00050
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | 0x00001801)
+#define CONFIG_SYS_OR0_PRELIM		0xFC000882
+#define CONFIG_SYS_BR4_PRELIM		(CONFIG_SYS_BCSR | 0x00001001)
+#define CONFIG_SYS_OR4_PRELIM		0xFFF00050
 
-#define CFG_RESET_ADDRESS	0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h
index 63ca2a5..cbaae62 100644
--- a/include/configs/evb4510.h
+++ b/include/configs/evb4510.h
@@ -51,8 +51,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 /*
  * Hardware drivers
@@ -108,29 +108,29 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory */
-#define CFG_PROMPT		"evb4510 # "	/* Monitor Command Prompt */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"evb4510 # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
 #define CONFIG_CMDLINE_TAG                      /* allow passing of command line args to linux */
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00780000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00780000	/* 4 ... 8 MB in DRAM	*/
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR		0x00000000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x00000000	/* default load address */
 
-#define CFG_SYS_CLK_FREQ	50000000	/* CPU freq: 50 MHz */
-#define CFG_HZ			1000		/* decrementer freq: 1 KHz */
+#define CONFIG_SYS_SYS_CLK_FREQ	50000000	/* CPU freq: 50 MHz */
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 KHz */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -156,25 +156,25 @@
 #define PHYS_FLASH_2		0x02000000 /* Flash Bank #2 */
 #define PHYS_FLASH_2_SIZE	0x00080000 /* 512KB (one chip, 8bit access) */
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-#define CFG_FLASH_SIZE		PHYS_FLASH_1_SIZE
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_SIZE		PHYS_FLASH_1_SIZE
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	35	/* max number of sectors on one chip */
-#define CFG_MAIN_SECT_SIZE	0x00010000  /* main size of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	35	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAIN_SECT_SIZE	0x00010000  /* main size of sectors on one chip */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(4*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(4*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 /* environment settings */
 #define CONFIG_ENV_IS_IN_FLASH
 #undef CONFIG_ENV_IS_NOWHERE
 
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x20000) /* environment start address */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x20000) /* environment start address */
 #define CONFIG_ENV_SECT_SIZE	0x10000	   /* Total Size of Environment Sector */
 #define CONFIG_ENV_SIZE		0x1000	   /* max size for environment */
 
diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h
index e445a13..21802df 100644
--- a/include/configs/favr-32-ezkit.h
+++ b/include/configs/favr-32-ezkit.h
@@ -35,40 +35,40 @@
  * Timer clock frequency. We're using the CPU-internal COUNT register
  * for this, so this is equivalent to the CPU core clock frequency
  */
-#define CFG_HZ				1000
+#define CONFIG_SYS_HZ				1000
 
 /*
  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
  * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
  * PLL frequency.
- * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
+ * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
  */
 #define CONFIG_PLL			1
-#define CFG_POWER_MANAGER		1
-#define CFG_OSC0_HZ			20000000
-#define CFG_PLL0_DIV			1
-#define CFG_PLL0_MUL			7
-#define CFG_PLL0_SUPPRESS_CYCLES	16
+#define CONFIG_SYS_POWER_MANAGER		1
+#define CONFIG_SYS_OSC0_HZ			20000000
+#define CONFIG_SYS_PLL0_DIV			1
+#define CONFIG_SYS_PLL0_MUL			7
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
 /*
  * Set the CPU running at:
- * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
  */
-#define CFG_CLKDIV_CPU			0
+#define CONFIG_SYS_CLKDIV_CPU			0
 /*
  * Set the HSB running at:
- * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
  */
-#define CFG_CLKDIV_HSB			1
+#define CONFIG_SYS_CLKDIV_HSB			1
 /*
  * Set the PBA running at:
- * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
  */
-#define CFG_CLKDIV_PBA			2
+#define CONFIG_SYS_CLKDIV_PBA			2
 /*
  * Set the PBB running at:
- * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
  */
-#define CFG_CLKDIV_PBB			1
+#define CONFIG_SYS_CLKDIV_PBB			1
 
 /*
  * The PLLOPT register controls the PLL like this:
@@ -77,7 +77,7 @@
  *
  * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
  */
-#define CFG_PLL0_OPT			0x04
+#define CONFIG_SYS_PLL0_OPT			0x04
 
 #undef CONFIG_USART0
 #undef CONFIG_USART1
@@ -146,56 +146,56 @@
 
 #define CONFIG_ATMEL_USART		1
 #define CONFIG_MACB			1
-#define CONFIG_PIO2			1
-#define CFG_NR_PIOS			5
-#define CFG_HSDRAMC			1
+#define CONFIG_PORTMUX_PIO		1
+#define CONFIG_SYS_NR_PIOS			5
+#define CONFIG_SYS_HSDRAMC			1
 #define CONFIG_MMC			1
 #define CONFIG_ATMEL_MCI		1
 
-#define CFG_DCACHE_LINESZ		32
-#define CFG_ICACHE_LINESZ		32
+#define CONFIG_SYS_DCACHE_LINESZ		32
+#define CONFIG_SYS_ICACHE_LINESZ		32
 
 #define CONFIG_NR_DRAM_BANKS		1
 
 /* External flash on Favr-32 */
 #if 0
-#define CFG_FLASH_CFI			1
+#define CONFIG_SYS_FLASH_CFI			1
 #define CONFIG_FLASH_CFI_DRIVER		1
 #endif
 
-#define CFG_FLASH_BASE			0x00000000
-#define CFG_FLASH_SIZE			0x800000
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		135
+#define CONFIG_SYS_FLASH_BASE			0x00000000
+#define CONFIG_SYS_FLASH_SIZE			0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		135
 
-#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 
-#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
-#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
-#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
+#define CONFIG_SYS_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE			EBI_SDRAM_BASE
 
 #define CONFIG_ENV_IS_IN_FLASH		1
 #define CONFIG_ENV_SIZE			65536
-#define CONFIG_ENV_ADDR			(CFG_FLASH_BASE + CFG_FLASH_SIZE - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
 
-#define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
 
-#define CFG_MALLOC_LEN			(256*1024)
-#define CFG_DMA_ALLOC_LEN		(16384)
+#define CONFIG_SYS_MALLOC_LEN			(256*1024)
+#define CONFIG_SYS_DMA_ALLOC_LEN		(16384)
 
 /* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
-#define CFG_BOOTPARAMS_LEN		(16 * 1024)
+#define CONFIG_SYS_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT			"U-Boot> "
-#define CFG_CBSIZE			256
-#define CFG_MAXARGS			16
-#define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_LONGHELP			1
-
-#define CFG_MEMTEST_START		EBI_SDRAM_BASE
-#define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x700000)
-#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+#define CONFIG_SYS_PROMPT			"U-Boot> "
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP			1
+
+#define CONFIG_SYS_MEMTEST_START		EBI_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + 0x700000)
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/fx12mm.h b/include/configs/fx12mm.h
new file mode 100644
index 0000000..5844567
--- /dev/null
+++ b/include/configs/fx12mm.h
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2008
+ *
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology  http://qtec.com
+ *
+ * Georg Schardt <schardt@team-ctech.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Configuration file for the Virtex4FX12 Minimodul by Avnet/Memec,
+ * see http://www.em.avnet.com
+ */
+
+#ifndef __CONFIG_FX12_H
+#define __CONFIG_FX12_H
+
+#include "../board/avnet/fx12mm/xparameters.h"
+
+/* cmd config */
+#define CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_CMDLINE
+#undef CONFIG_CMD_NET
+
+/* sdram */
+#define CONFIG_SYS_SDRAM_SIZE_MB       64
+
+/* environment */
+#define CONFIG_ENV_IS_IN_FLASH  1
+#define CONFIG_ENV_SIZE         0x10000
+#define CONFIG_ENV_SECT_SIZE    0x10000
+#define CONFIG_SYS_ENV_OFFSET   0xA0000
+#define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET)
+#define CONFIG_ENV_OVERWRITE 	1
+
+/*Misc*/
+#define CONFIG_SYS_PROMPT	"FX12MM:/# " /* Monitor Command Prompt */
+#define CONFIG_PREBOOT      	"echo U-Boot is up and running;"
+
+/*Flash*/
+#define CONFIG_SYS_FLASH_SIZE          (4*1024*1024)
+#define CONFIG_SYS_MAX_FLASH_SECT      71
+#define MTDIDS_DEFAULT		"nor0=fx12mm-flash"
+#define MTDPARTS_DEFAULT	"mtdparts=fx12mm-flash:-(user)"
+
+#include "configs/xilinx-ppc405.h"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h
index 5863f83..c0b3ab9 100644
--- a/include/configs/gcplus.h
+++ b/include/configs/gcplus.h
@@ -57,8 +57,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN          (CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE       128     /* size rsrvd for initial data */
+#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE       128     /* size rsrvd for initial data */
 
 
 /*
@@ -98,7 +98,7 @@
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySA0,38400n8 mtdparts=sa1100-flash:1m@0(zImage),3m@1m(ramdisk.gz),12m@4m(userfs) root=/dev/nfs ip=bootp"
 #define CONFIG_BOOTCOMMAND	"bootp;tftp;bootm"
-#define CFG_AUTOLOAD            "n"             /* No autoload */
+#define CONFIG_SYS_AUTOLOAD            "n"             /* No autoload */
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	38400		/* speed to run kgdb serial port */
@@ -108,25 +108,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"ADS GCPlus # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"ADS GCPlus # "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0xc0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0xc0000000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0xc0000000	/* default load address	*/
 
-#define	CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x0a		/* set core clock to 206MHz */
+#define	CONFIG_SYS_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_CPUSPEED		0x0a		/* set core clock to 206MHz */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -154,28 +154,28 @@
 #define PHYS_FLASH_BANK_SIZE    0x01000000 /* 16 MB Banks */
 #define PHYS_FLASH_SECT_SIZE    0x00040000 /* 256 KB sectors (x2) */
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
 #if	1
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 #else
 /* REVISIT: This doesn't work on ADS GCPlus just yet: */
-#define CFG_FLASH_CFI           1       /* flash is CFI conformant      */
+#define CONFIG_SYS_FLASH_CFI           1       /* flash is CFI conformant      */
 #define CONFIG_FLASH_CFI_DRIVER    1       /* use common cfi driver        */
-#define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster) */
-#define CFG_MAX_FLASH_BANKS     1       /* max # of memory banks        */
-#define CFG_FLASH_INCREMENT     0       /* there is only one bank       */
-#define CFG_MAX_FLASH_SECT      128     /* max # of sectors on one chip */
-/*#define CFG_FLASH_PROTECTION    1       /--* hardware flash protection    */
-#define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster) */
+#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* max # of memory banks        */
+#define CONFIG_SYS_FLASH_INCREMENT     0       /* there is only one bank       */
+#define CONFIG_SYS_MAX_FLASH_SECT      128     /* max # of sectors on one chip */
+/*#define CONFIG_SYS_FLASH_PROTECTION    1       /--* hardware flash protection    */
+#define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE }
 #endif
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h
new file mode 100644
index 0000000..d193919
--- /dev/null
+++ b/include/configs/gdppc440etx.h
@@ -0,0 +1,194 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * Based on include/configs/yosemite.h
+ * (C) Copyright 2005-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_440GR		1		/* Specific PPC440GR support */
+#define CONFIG_HOSTNAME		gdppc440etx
+#define CONFIG_440		1		/* ... PPC440 family         */
+#define CONFIG_4xx		1		/* ... PPC4xx family         */
+#define CONFIG_SYS_CLK_FREQ	66666666	/* external freq to pll      */
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* call board_early_init_f*/
+#define CONFIG_MISC_INIT_R		1	/* call misc_init_r()     */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_FLASH_BASE		0xfc000000	/* start of FLASH    */
+#define CONFIG_SYS_PCI_MEMBASE		0xa0000000	/* mapped pci memory */
+#define CONFIG_SYS_PCI_MEMBASE1		CONFIG_SYS_PCI_MEMBASE  + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2		CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3		CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
+
+/*Don't change either of these*/
+#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000	/* internal peripheral*/
+#define CONFIG_SYS_PCI_BASE		0xe0000000	/* internal PCI regs */
+/*Don't change either of these*/
+
+#define CONFIG_SYS_USB_DEVICE		0x50000000
+#define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
+
+/*
+ * Initial RAM & stack pointer (placed in SDRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram*/
+#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000	/* DCache             */
+#define CONFIG_SYS_INIT_RAM_END		(4 << 10)
+#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes init data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END \
+					 - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk */
+#define CONFIG_UART1_CONSOLE
+
+/*
+ * Environment
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#define CONFIG_ENV_IS_IN_FLASH		1		/* FLASH for env. vars*/
+
+/*
+ * FLASH related
+ */
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible*/
+#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver      */
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1	/* AMD RESET for STM 29W320DB!*/
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors/chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 	120000	/* Timeout/Flash Erase (in ms)*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout/Flash Write (in ms)*/
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE		0x20000 /* size of one complete sector*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE			0x2000 /* Total Size of Env. Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/*
+ * DDR SDRAM
+ */
+#undef CONFIG_SPD_EEPROM		/* Don't use SPD EEPROM for setup*/
+#define CONFIG_SYS_KBYTES_SDRAM		(128 * 1024)    /* 128MB         */
+#define CONFIG_SYS_SDRAM_BANKS		(2)
+
+#define CONFIG_SDRAM_BANK0
+#define CONFIG_SDRAM_BANK1
+
+#define CONFIG_SYS_SDRAM0_TR0		0x410a4012
+#define CONFIG_SYS_SDRAM0_WDDCTR	0x40000000
+#define CONFIG_SYS_SDRAM0_RTR		0x04080000
+#define CONFIG_SYS_SDRAM0_CFG0		0x80000000
+
+#undef CONFIG_SDRAM_ECC
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed+slave address*/
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"ramdisk_addr=fc180000\0"					\
+	""
+
+#define CONFIG_HAS_ETH1			1	/* add support for "eth1addr" */
+#define CONFIG_PHY_ADDR			1
+#define CONFIG_PHY1_ADDR		3
+
+#ifdef DEBUG
+#define CONFIG_PANIC_HANG
+#endif
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_PCI
+#undef CONFIG_CMD_EEPROM
+
+/*
+ * PCI stuff
+ */
+
+/* General PCI */
+#define CONFIG_PCI				/* include pci support        */
+#undef  CONFIG_PCI_PNP				/* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW			/* show pci devices on startup*/
+#define CONFIG_SYS_PCI_TARGBASE		0x80000000	/* PCIaddr mapped to \
+							CONFIG_SYS_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_ID	0xcafe	/* tbd */
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB0AP		0x03017200
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH | 0xda000)
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h
index 5a7a580..bbe635b 100644
--- a/include/configs/gr_cpci_ax2000.h
+++ b/include/configs/gr_cpci_ax2000.h
@@ -61,13 +61,13 @@
 #define CONFIG_SYS_CLK_FREQ	20000000	/* 20MHz */
 
 /* Number of SPARC register windows */
-#define CFG_SPARC_NWINDOWS 8
+#define CONFIG_SYS_SPARC_NWINDOWS 8
 
 /*
  * Serial console configuration
  */
 #define CONFIG_BAUDRATE		38400	/* ... at 38400 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /* Partitions */
 #define CONFIG_DOS_PARTITION
@@ -192,28 +192,28 @@
  *               0xFF000000 for 16 MB
  *               0xFF800000 for  8 MB
  */
-/*#define CFG_NO_FLASH		1*/
-#define CFG_FLASH_BASE		0x00000000
-#define CFG_FLASH_SIZE		0x00800000
+/*#define CONFIG_SYS_NO_FLASH		1*/
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
 
 #define PHYS_FLASH_SECT_SIZE	0x00020000	/* 128 KB sectors */
-#define CFG_MAX_FLASH_SECT	64	/* max num of sects on one chip */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
 
 /*** CFI CONFIG ***/
-#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 /* Bypass cache when reading regs from flash memory */
-#define CFG_FLASH_CFI_BYPASS_READ
+#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
 /* Buffered writes (32byte/go) instead of single accesses */
-#define CFG_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 /*
  * Environment settings
@@ -223,7 +223,7 @@
 /* CONFIG_ENV_ADDR need to be at sector boundary */
 #define CONFIG_ENV_SIZE		0x8000
 #define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE+CFG_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_OVERWRITE	1
 
 /*
@@ -235,59 +235,59 @@
  */
 
 #if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM
-#define CFG_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
 #else
-#define CFG_SDRAM_BASE		0x60000000
+#define CONFIG_SYS_SDRAM_BASE		0x60000000
 #endif
 
-#define CFG_SDRAM_SIZE		0x08000000
-#define CFG_SDRAM_END		(CFG_SDRAM_BASE+CFG_SDRAM_SIZE)
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+#define CONFIG_SYS_SDRAM_END		(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
 
 /* 4Mb SRAM available */
 #if CONFIG_LEON_RAM_SELECT != CONFIG_LEON_RAM_SDRAM_NOSRAM
-#define CFG_SRAM_BASE 0x40000000
-#define CFG_SRAM_SIZE 0x400000
-#define CFG_SRAM_END  (CFG_SRAM_BASE+CFG_SRAM_SIZE)
+#define CONFIG_SYS_SRAM_BASE 0x40000000
+#define CONFIG_SYS_SRAM_SIZE 0x400000
+#define CONFIG_SYS_SRAM_END  (CONFIG_SYS_SRAM_BASE+CONFIG_SYS_SRAM_SIZE)
 #endif
 
 /* Select RAM used to run U-BOOT from... */
 #if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SRAM
-#define CFG_RAM_BASE CFG_SRAM_BASE
-#define CFG_RAM_SIZE CFG_SRAM_SIZE
-#define CFG_RAM_END CFG_SRAM_END
+#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SRAM_BASE
+#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SRAM_SIZE
+#define CONFIG_SYS_RAM_END CONFIG_SYS_SRAM_END
 #else
-#define CFG_RAM_BASE CFG_SDRAM_BASE
-#define CFG_RAM_SIZE CFG_SDRAM_SIZE
-#define CFG_RAM_END CFG_SDRAM_END
+#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
 #endif
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
-#define CFG_PROM_SIZE		(8192-CFG_GBL_DATA_SIZE)
-#define CFG_PROM_OFFSET		(CFG_GBL_DATA_OFFSET-CFG_PROM_SIZE)
+#define CONFIG_SYS_PROM_SIZE		(8192-CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
 
-#define CFG_INIT_SP_OFFSET	(CFG_PROM_OFFSET-32)
-#define CFG_STACK_SIZE		(0x10000-32)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
+#define CONFIG_SYS_STACK_SIZE		(0x10000-32)
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-#define CFG_MALLOC_END		(CFG_INIT_SP_OFFSET-CFG_STACK_SIZE)
-#define CFG_MALLOC_BASE		(CFG_MALLOC_END-CFG_MALLOC_LEN)
+#define CONFIG_SYS_MALLOC_END		(CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
 
 /* relocated monitor area */
-#define CFG_RELOC_MONITOR_MAX_END   CFG_MALLOC_BASE
-#define CFG_RELOC_MONITOR_BASE     (CFG_RELOC_MONITOR_MAX_END-CFG_MONITOR_LEN)
+#define CONFIG_SYS_RELOC_MONITOR_MAX_END   CONFIG_SYS_MALLOC_BASE
+#define CONFIG_SYS_RELOC_MONITOR_BASE     (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
 
 /* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CFG_RELOC_MONITOR_BASE-TEXT_BASE))
+#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE))
 
 /*
  * Ethernet configuration uses on board SMC91C111
@@ -305,23 +305,23 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory     */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory     */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 /*
  * Various low-level settings
@@ -337,38 +337,38 @@
 /***** Gaisler GRLIB IP-Cores Config ********/
 
 /* AMBA Plug & Play info display on startup */
-/*#define CFG_AMBAPP_PRINT_ON_STARTUP*/
+/*#define CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP*/
 
-#define CFG_GRLIB_SDRAM    0
+#define CONFIG_SYS_GRLIB_SDRAM    0
 
 /* See, GRLIB Docs (grip.pdf) on how to set up
  * These the memory controller registers.
  */
-#define CFG_GRLIB_MEMCFG1   (0x10f800ff | (1<<11))
+#define CONFIG_SYS_GRLIB_MEMCFG1   (0x10f800ff | (1<<11))
 #if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM
-#define CFG_GRLIB_MEMCFG2   0x82206000
+#define CONFIG_SYS_GRLIB_MEMCFG2   0x82206000
 #else
-#define CFG_GRLIB_MEMCFG2   0x82205260
+#define CONFIG_SYS_GRLIB_MEMCFG2   0x82205260
 #endif
-#define CFG_GRLIB_MEMCFG3   0x0809a000
+#define CONFIG_SYS_GRLIB_MEMCFG3   0x0809a000
 
-#define CFG_GRLIB_FT_MEMCFG1   (0x10f800ff | (1<<11))
+#define CONFIG_SYS_GRLIB_FT_MEMCFG1   (0x10f800ff | (1<<11))
 #if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM
-#define CFG_GRLIB_FT_MEMCFG2   0x82206000
+#define CONFIG_SYS_GRLIB_FT_MEMCFG2   0x82206000
 #else
-#define CFG_GRLIB_FT_MEMCFG2   0x82205260
+#define CONFIG_SYS_GRLIB_FT_MEMCFG2   0x82205260
 #endif
-#define CFG_GRLIB_FT_MEMCFG3   0x0809a000
+#define CONFIG_SYS_GRLIB_FT_MEMCFG3   0x0809a000
 
 /* no DDR controller */
-#define CFG_GRLIB_DDR_CFG   0x00000000
+#define CONFIG_SYS_GRLIB_DDR_CFG   0x00000000
 
 /* no DDR2 Controller */
-#define CFG_GRLIB_DDR2_CFG1 0x00000000
-#define CFG_GRLIB_DDR2_CFG3 0x00000000
+#define CONFIG_SYS_GRLIB_DDR2_CFG1 0x00000000
+#define CONFIG_SYS_GRLIB_DDR2_CFG3 0x00000000
 
 /* Calculate scaler register value from default baudrate */
-#define CFG_GRLIB_APBUART_SCALER \
+#define CONFIG_SYS_GRLIB_APBUART_SCALER \
  ((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
 
 /* Identification string */
diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h
index 3133c0d..6f58bac 100644
--- a/include/configs/gr_ep2s60.h
+++ b/include/configs/gr_ep2s60.h
@@ -45,7 +45,7 @@
 #define CONFIG_SYS_CLK_FREQ	96000000	/* 96MHz */
 
 /* Number of SPARC register windows */
-#define CFG_SPARC_NWINDOWS 8
+#define CONFIG_SYS_SPARC_NWINDOWS 8
 
 /* Define this is the GR-2S60-MEZZ mezzanine is available and you
  * want to use the USB and GRETH functionality of the board
@@ -61,7 +61,7 @@
  * Serial console configuration
  */
 #define CONFIG_BAUDRATE		38400	/* ... at 38400 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /* Partitions */
 #define CONFIG_DOS_PARTITION
@@ -87,7 +87,7 @@
 #define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 /* Enable needed helper functions */
-#define CFG_DEVICE_DEREGISTER	/* needs device_deregister */
+#define CONFIG_SYS_DEVICE_DEREGISTER	/* needs device_deregister */
 #endif
 
 /*
@@ -180,28 +180,28 @@
  *               0xFF000000 for 16 MB
  *               0xFF800000 for  8 MB
  */
-/*#define CFG_NO_FLASH		1*/
-#define CFG_FLASH_BASE		0x00000000
-#define CFG_FLASH_SIZE		0x00400000	/* FPGA Bit file is in top of FLASH, we only ues the bottom 4Mb */
+/*#define CONFIG_SYS_NO_FLASH		1*/
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_FLASH_SIZE		0x00400000	/* FPGA Bit file is in top of FLASH, we only ues the bottom 4Mb */
 
 #define PHYS_FLASH_SECT_SIZE	0x00010000	/* 64 KB sectors */
-#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
 
 /*** CFI CONFIG ***/
-#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 /* Bypass cache when reading regs from flash memory */
-#define CFG_FLASH_CFI_BYPASS_READ
+#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
 /* Buffered writes (32byte/go) instead of single accesses */
-#define CFG_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 /*
  * Environment settings
@@ -211,51 +211,51 @@
 /* CONFIG_ENV_ADDR need to be at sector boundary */
 #define CONFIG_ENV_SIZE		0x8000
 #define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE+CFG_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_OVERWRITE	1
 
 /*
  * Memory map
  */
-#define CFG_SDRAM_BASE		0x40000000
-#define CFG_SDRAM_SIZE		0x02000000
-#define CFG_SDRAM_END		(CFG_SDRAM_BASE+CFG_SDRAM_SIZE)
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		0x02000000
+#define CONFIG_SYS_SDRAM_END		(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
 
 /* no SRAM available */
-#undef CFG_SRAM_BASE
-#undef CFG_SRAM_SIZE
+#undef CONFIG_SYS_SRAM_BASE
+#undef CONFIG_SYS_SRAM_SIZE
 
-#define CFG_RAM_BASE CFG_SDRAM_BASE
-#define CFG_RAM_SIZE CFG_SDRAM_SIZE
-#define CFG_RAM_END CFG_SDRAM_END
+#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_SDRAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_SDRAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
-#define CFG_PROM_SIZE		(8192-CFG_GBL_DATA_SIZE)
-#define CFG_PROM_OFFSET		(CFG_GBL_DATA_OFFSET-CFG_PROM_SIZE)
+#define CONFIG_SYS_PROM_SIZE		(8192-CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
 
-#define CFG_INIT_SP_OFFSET	(CFG_PROM_OFFSET-32)
-#define CFG_STACK_SIZE		(0x10000-32)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
+#define CONFIG_SYS_STACK_SIZE		(0x10000-32)
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor   */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-#define CFG_MALLOC_END		(CFG_INIT_SP_OFFSET-CFG_STACK_SIZE)
-#define CFG_MALLOC_BASE		(CFG_MALLOC_END-CFG_MALLOC_LEN)
+#define CONFIG_SYS_MALLOC_END		(CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
 
 /* relocated monitor area */
-#define CFG_RELOC_MONITOR_MAX_END   CFG_MALLOC_BASE
-#define CFG_RELOC_MONITOR_BASE     (CFG_RELOC_MONITOR_MAX_END-CFG_MONITOR_LEN)
+#define CONFIG_SYS_RELOC_MONITOR_MAX_END   CONFIG_SYS_MALLOC_BASE
+#define CONFIG_SYS_RELOC_MONITOR_BASE     (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
 
 /* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CFG_RELOC_MONITOR_BASE-TEXT_BASE))
+#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE))
 
 /*
  * Ethernet configuration uses on board SMC91C111, however if a mezzanine
@@ -295,23 +295,23 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory     */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory     */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * USB stuff
@@ -323,28 +323,28 @@
 /***** Gaisler GRLIB IP-Cores Config ********/
 
 /* AMBA Plug & Play info display on startup */
-/*#define CFG_AMBAPP_PRINT_ON_STARTUP*/
+/*#define CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP*/
 
-#define CFG_GRLIB_SDRAM    0
+#define CONFIG_SYS_GRLIB_SDRAM    0
 
 /* See, GRLIB Docs (grip.pdf) on how to set up
  * These the memory controller registers.
  */
-#define CFG_GRLIB_MEMCFG1  (0x10f800ff | (1<<11))
-#define CFG_GRLIB_MEMCFG2  0x00000000
-#define CFG_GRLIB_MEMCFG3  0x00000000
+#define CONFIG_SYS_GRLIB_MEMCFG1  (0x10f800ff | (1<<11))
+#define CONFIG_SYS_GRLIB_MEMCFG2  0x00000000
+#define CONFIG_SYS_GRLIB_MEMCFG3  0x00000000
 
-#define CFG_GRLIB_FT_MEMCFG1  (0x10f800ff | (1<<11))
-#define CFG_GRLIB_FT_MEMCFG2  0x00000000
-#define CFG_GRLIB_FT_MEMCFG3  0x00000000
+#define CONFIG_SYS_GRLIB_FT_MEMCFG1  (0x10f800ff | (1<<11))
+#define CONFIG_SYS_GRLIB_FT_MEMCFG2  0x00000000
+#define CONFIG_SYS_GRLIB_FT_MEMCFG3  0x00000000
 
-#define CFG_GRLIB_DDR_CFG  0xa900830a
+#define CONFIG_SYS_GRLIB_DDR_CFG  0xa900830a
 
-#define CFG_GRLIB_DDR2_CFG1 0x00000000
-#define CFG_GRLIB_DDR2_CFG3 0x00000000
+#define CONFIG_SYS_GRLIB_DDR2_CFG1 0x00000000
+#define CONFIG_SYS_GRLIB_DDR2_CFG3 0x00000000
 
 /* Calculate scaler register value from default baudrate */
-#define CFG_GRLIB_APBUART_SCALER \
+#define CONFIG_SYS_GRLIB_APBUART_SCALER \
  ((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
 
 /* Identification string */
diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h
index 316b003..4dd9a0f 100644
--- a/include/configs/gr_xc3s_1500.h
+++ b/include/configs/gr_xc3s_1500.h
@@ -42,13 +42,13 @@
 #define CONFIG_SYS_CLK_FREQ	40000000	/* 40MHz */
 
 /* Number of SPARC register windows */
-#define CFG_SPARC_NWINDOWS 8
+#define CONFIG_SYS_SPARC_NWINDOWS 8
 
 /*
  * Serial console configuration
  */
 #define CONFIG_BAUDRATE		38400	/* ... at 38400 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /* Partitions */
 #define CONFIG_DOS_PARTITION
@@ -156,28 +156,28 @@
  *               0xFF000000 for 16 MB
  *               0xFF800000 for  8 MB
  */
-/*#define CFG_NO_FLASH		1*/
-#define CFG_FLASH_BASE		0x00000000
-#define CFG_FLASH_SIZE		0x00800000
+/*#define CONFIG_SYS_NO_FLASH		1*/
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
 
 #define PHYS_FLASH_SECT_SIZE	0x00020000	/* 128 KB sectors */
-#define CFG_MAX_FLASH_SECT	64	/* max num of sects on one chip */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
 
 /*** CFI CONFIG ***/
-#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 /* Bypass cache when reading regs from flash memory */
-#define CFG_FLASH_CFI_BYPASS_READ
+#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
 /* Buffered writes (32byte/go) instead of single accesses */
-#define CFG_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 /*
  * Environment settings
@@ -187,52 +187,52 @@
 /* CONFIG_ENV_ADDR need to be at sector boundary */
 #define CONFIG_ENV_SIZE		0x8000
 #define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE+CFG_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_OVERWRITE	1
 
 /*
  * Memory map
  */
-#define CFG_SDRAM_BASE		0x40000000
-#define CFG_SDRAM_SIZE		0x4000000
-#define CFG_SDRAM_END		(CFG_SDRAM_BASE+CFG_SDRAM_SIZE)
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		0x4000000
+#define CONFIG_SYS_SDRAM_END		(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
 
 /* no SRAM available */
-#undef CFG_SRAM_BASE
-#undef CFG_SRAM_SIZE
+#undef CONFIG_SYS_SRAM_BASE
+#undef CONFIG_SYS_SRAM_SIZE
 
 /* Always Run U-Boot from SDRAM */
-#define CFG_RAM_BASE CFG_SDRAM_BASE
-#define CFG_RAM_SIZE CFG_SDRAM_SIZE
-#define CFG_RAM_END CFG_SDRAM_END
+#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
-#define CFG_PROM_SIZE		(8192-CFG_GBL_DATA_SIZE)
-#define CFG_PROM_OFFSET		(CFG_GBL_DATA_OFFSET-CFG_PROM_SIZE)
+#define CONFIG_SYS_PROM_SIZE		(8192-CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
 
-#define CFG_INIT_SP_OFFSET	(CFG_PROM_OFFSET-32)
-#define CFG_STACK_SIZE		(0x10000-32)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
+#define CONFIG_SYS_STACK_SIZE		(0x10000-32)
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-#define CFG_MALLOC_END		(CFG_INIT_SP_OFFSET-CFG_STACK_SIZE)
-#define CFG_MALLOC_BASE		(CFG_MALLOC_END-CFG_MALLOC_LEN)
+#define CONFIG_SYS_MALLOC_END		(CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
 
 /* relocated monitor area */
-#define CFG_RELOC_MONITOR_MAX_END   CFG_MALLOC_BASE
-#define CFG_RELOC_MONITOR_BASE     (CFG_RELOC_MONITOR_MAX_END-CFG_MONITOR_LEN)
+#define CONFIG_SYS_RELOC_MONITOR_MAX_END   CONFIG_SYS_MALLOC_BASE
+#define CONFIG_SYS_RELOC_MONITOR_BASE     (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
 
 /* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CFG_RELOC_MONITOR_BASE-TEXT_BASE))
+#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE))
 
 /*
  * Ethernet configuration
@@ -254,23 +254,23 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory     */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory     */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 /*
  * Various low-level settings
@@ -286,30 +286,30 @@
 /***** Gaisler GRLIB IP-Cores Config ********/
 
 /* AMBA Plug & Play info display on startup */
-/*#define CFG_AMBAPP_PRINT_ON_STARTUP*/
+/*#define CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP*/
 
-#define CFG_GRLIB_SDRAM    0
+#define CONFIG_SYS_GRLIB_SDRAM    0
 
 /* See, GRLIB Docs (grip.pdf) on how to set up
  * These the memory controller registers.
  */
-#define CFG_GRLIB_MEMCFG1   (0x000000ff | (1<<11))
-#define CFG_GRLIB_MEMCFG2   0x82206000
-#define CFG_GRLIB_MEMCFG3   0x00136000
+#define CONFIG_SYS_GRLIB_MEMCFG1   (0x000000ff | (1<<11))
+#define CONFIG_SYS_GRLIB_MEMCFG2   0x82206000
+#define CONFIG_SYS_GRLIB_MEMCFG3   0x00136000
 
-#define CFG_GRLIB_FT_MEMCFG1   (0x000000ff | (1<<11))
-#define CFG_GRLIB_FT_MEMCFG2   0x82206000
-#define CFG_GRLIB_FT_MEMCFG3   0x00136000
+#define CONFIG_SYS_GRLIB_FT_MEMCFG1   (0x000000ff | (1<<11))
+#define CONFIG_SYS_GRLIB_FT_MEMCFG2   0x82206000
+#define CONFIG_SYS_GRLIB_FT_MEMCFG3   0x00136000
 
 /* no DDR controller */
-#define CFG_GRLIB_DDR_CFG   0x00000000
+#define CONFIG_SYS_GRLIB_DDR_CFG   0x00000000
 
 /* no DDR2 Controller */
-#define CFG_GRLIB_DDR2_CFG1 0x00000000
-#define CFG_GRLIB_DDR2_CFG3 0x00000000
+#define CONFIG_SYS_GRLIB_DDR2_CFG1 0x00000000
+#define CONFIG_SYS_GRLIB_DDR2_CFG3 0x00000000
 
 /* Calculate scaler register value from default baudrate */
-#define CFG_GRLIB_APBUART_SCALER \
+#define CONFIG_SYS_GRLIB_APBUART_SCALER \
  ((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
 
 /* Identification string */
diff --git a/include/configs/grsim.h b/include/configs/grsim.h
index a5ef6e1..a9eaa4a 100644
--- a/include/configs/grsim.h
+++ b/include/configs/grsim.h
@@ -49,13 +49,13 @@
 #define CONFIG_SYS_CLK_FREQ	40000000	/* 40MHz */
 
 /* Number of SPARC register windows */
-#define CFG_SPARC_NWINDOWS 8
+#define CONFIG_SYS_SPARC_NWINDOWS 8
 
 /*
  * Serial console configuration
  */
 #define CONFIG_BAUDRATE		38400	/* ... at 38400 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /* Partitions */
 #define CONFIG_DOS_PARTITION
@@ -93,9 +93,9 @@
 	"echo"
 
 #undef	CONFIG_BOOTARGS
-/*#define CFG_HUSH_PARSER 0*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+/*#define CONFIG_SYS_HUSH_PARSER 0*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
@@ -178,32 +178,32 @@
  *               0xFF000000 for 16 MB
  *               0xFF800000 for  8 MB
  */
-#define CFG_NO_FLASH		1
-#define CFG_FLASH_BASE		0x00000000
-#define CFG_FLASH_SIZE		0x00800000
+#define CONFIG_SYS_NO_FLASH		1
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
 #define CONFIG_ENV_SIZE		0x8000
 
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE+CFG_FLASH_SIZE-CONFIG_ENV_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SIZE)
 
 #define PHYS_FLASH_SECT_SIZE	0x00020000	/* 128 KB sectors */
-#define CFG_MAX_FLASH_SECT	64	/* max num of sects on one chip */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
 
 #ifdef ENABLE_FLASH_SUPPORT
 /* For use with grsim FLASH emulation extension */
-#define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
 
 #undef CONFIG_FLASH_8BIT	/* Flash is 32-bit */
 
 /*** CFI CONFIG ***/
-#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #endif
 
 /*
@@ -218,46 +218,46 @@
 /*
  * Memory map
  */
-#define CFG_SDRAM_BASE		0x40000000
-#define CFG_SDRAM_SIZE		0x02000000
-#define CFG_SDRAM_END		(CFG_SDRAM_BASE+CFG_SDRAM_SIZE)
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		0x02000000
+#define CONFIG_SYS_SDRAM_END		(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
 
 /* no SRAM available */
-#undef CFG_SRAM_BASE
-#undef CFG_SRAM_SIZE
+#undef CONFIG_SYS_SRAM_BASE
+#undef CONFIG_SYS_SRAM_SIZE
 
 /* Always Run U-Boot from SDRAM */
-#define CFG_RAM_BASE CFG_SDRAM_BASE
-#define CFG_RAM_SIZE CFG_SDRAM_SIZE
-#define CFG_RAM_END CFG_SDRAM_END
+#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
-#define CFG_PROM_SIZE		(8192-CFG_GBL_DATA_SIZE)
-#define CFG_PROM_OFFSET		(CFG_GBL_DATA_OFFSET-CFG_PROM_SIZE)
+#define CONFIG_SYS_PROM_SIZE		(8192-CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
 
-#define CFG_INIT_SP_OFFSET	(CFG_PROM_OFFSET-32)
-#define CFG_STACK_SIZE		(0x10000-32)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
+#define CONFIG_SYS_STACK_SIZE		(0x10000-32)
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-#define CFG_MALLOC_END		(CFG_INIT_SP_OFFSET-CFG_STACK_SIZE)
-#define CFG_MALLOC_BASE		(CFG_MALLOC_END-CFG_MALLOC_LEN)
+#define CONFIG_SYS_MALLOC_END		(CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
 
 /* relocated monitor area */
-#define CFG_RELOC_MONITOR_MAX_END   CFG_MALLOC_BASE
-#define CFG_RELOC_MONITOR_BASE     (CFG_RELOC_MONITOR_MAX_END-CFG_MONITOR_LEN)
+#define CONFIG_SYS_RELOC_MONITOR_MAX_END   CONFIG_SYS_MALLOC_BASE
+#define CONFIG_SYS_RELOC_MONITOR_BASE     (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
 
 /* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CFG_RELOC_MONITOR_BASE-TEXT_BASE))
+#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE))
 
 /*
  * Ethernet configuration
@@ -284,52 +284,52 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory     */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory     */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 /***** Gaisler GRLIB IP-Cores Config ********/
 
 /* AMBA Plug & Play info display on startup */
-/*#define CFG_AMBAPP_PRINT_ON_STARTUP*/
+/*#define CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP*/
 
-#define CFG_GRLIB_SDRAM     0
-#define CFG_GRLIB_MEMCFG1   (0x000000ff | (1<<11))
+#define CONFIG_SYS_GRLIB_SDRAM     0
+#define CONFIG_SYS_GRLIB_MEMCFG1   (0x000000ff | (1<<11))
 #if CONFIG_GRSIM
 /* GRSIM configuration */
-#define CFG_GRLIB_MEMCFG2   0x82206000
+#define CONFIG_SYS_GRLIB_MEMCFG2   0x82206000
 #else
 /* TSIM configuration */
-#define CFG_GRLIB_MEMCFG2   0x00001820
+#define CONFIG_SYS_GRLIB_MEMCFG2   0x00001820
 #endif
-#define CFG_GRLIB_MEMCFG3   0x00136000
+#define CONFIG_SYS_GRLIB_MEMCFG3   0x00136000
 
-#define CFG_GRLIB_FT_MEMCFG1   (0x000000ff | (1<<11))
-#define CFG_GRLIB_FT_MEMCFG2   0x82206000
-#define CFG_GRLIB_FT_MEMCFG3   0x00136000
+#define CONFIG_SYS_GRLIB_FT_MEMCFG1   (0x000000ff | (1<<11))
+#define CONFIG_SYS_GRLIB_FT_MEMCFG2   0x82206000
+#define CONFIG_SYS_GRLIB_FT_MEMCFG3   0x00136000
 
 /* no DDR controller */
-#define CFG_GRLIB_DDR_CFG   0x00000000
+#define CONFIG_SYS_GRLIB_DDR_CFG   0x00000000
 
 /* no DDR2 Controller */
-#define CFG_GRLIB_DDR2_CFG1 0x00000000
-#define CFG_GRLIB_DDR2_CFG3 0x00000000
+#define CONFIG_SYS_GRLIB_DDR2_CFG1 0x00000000
+#define CONFIG_SYS_GRLIB_DDR2_CFG3 0x00000000
 
-#define CFG_GRLIB_APBUART_SCALER \
+#define CONFIG_SYS_GRLIB_APBUART_SCALER \
  ((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
 
 /* default kernel command line */
diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h
index a88ddb3..58f26fd 100644
--- a/include/configs/grsim_leon2.h
+++ b/include/configs/grsim_leon2.h
@@ -48,13 +48,13 @@
 #define CONFIG_SYS_CLK_FREQ	40000000	/* 40MHz */
 
 /* Number of SPARC register windows */
-#define CFG_SPARC_NWINDOWS 8
+#define CONFIG_SYS_SPARC_NWINDOWS 8
 
 /*
  * Serial console configuration
  */
 #define CONFIG_BAUDRATE		38400	/* ... at 38400 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /* Partitions */
 #define CONFIG_DOS_PARTITION
@@ -90,9 +90,9 @@
 	"echo"
 
 #undef	CONFIG_BOOTARGS
-/*#define CFG_HUSH_PARSER 0*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+/*#define CONFIG_SYS_HUSH_PARSER 0*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
@@ -175,32 +175,32 @@
  *               0xFF000000 for 16 MB
  *               0xFF800000 for  8 MB
  */
-#define CFG_NO_FLASH		1
-#define CFG_FLASH_BASE		0x00000000
-#define CFG_FLASH_SIZE		0x00800000
+#define CONFIG_SYS_NO_FLASH		1
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
 #define CONFIG_ENV_SIZE		0x8000
 
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE+CFG_FLASH_SIZE-CONFIG_ENV_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SIZE)
 
 #define PHYS_FLASH_SECT_SIZE	0x00020000	/* 128 KB sectors */
-#define CFG_MAX_FLASH_SECT	64	/* max num of sects on one chip */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
 
 #ifdef ENABLE_FLASH_SUPPORT
 /* For use with grsim FLASH emulation extension */
-#define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
 
 #undef CONFIG_FLASH_8BIT	/* Flash is 32-bit */
 
 /*** CFI CONFIG ***/
-#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #endif
 
 /*
@@ -215,47 +215,47 @@
 /*
  * Memory map
  */
-#define CFG_SDRAM_BASE		0x40000000
-#define CFG_SDRAM_SIZE		0x00800000
-#define CFG_SDRAM_END		(CFG_SDRAM_BASE+CFG_SDRAM_SIZE)
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		0x00800000
+#define CONFIG_SYS_SDRAM_END		(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
 
 /* no SRAM available */
-#undef CFG_SRAM_BASE
-#undef CFG_SRAM_SIZE
+#undef CONFIG_SYS_SRAM_BASE
+#undef CONFIG_SYS_SRAM_SIZE
 
 
 /* Always Run U-Boot from SDRAM */
-#define CFG_RAM_BASE CFG_SDRAM_BASE
-#define CFG_RAM_SIZE CFG_SDRAM_SIZE
-#define CFG_RAM_END CFG_SDRAM_END
+#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
-#define CFG_PROM_SIZE		(8192-CFG_GBL_DATA_SIZE)
-#define CFG_PROM_OFFSET		(CFG_GBL_DATA_OFFSET-CFG_PROM_SIZE)
+#define CONFIG_SYS_PROM_SIZE		(8192-CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
 
-#define CFG_INIT_SP_OFFSET	(CFG_PROM_OFFSET-32)
-#define CFG_STACK_SIZE		(0x10000-32)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
+#define CONFIG_SYS_STACK_SIZE		(0x10000-32)
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-#define CFG_MALLOC_END		(CFG_INIT_SP_OFFSET-CFG_STACK_SIZE)
-#define CFG_MALLOC_BASE		(CFG_MALLOC_END-CFG_MALLOC_LEN)
+#define CONFIG_SYS_MALLOC_END		(CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
 
 /* relocated monitor area */
-#define CFG_RELOC_MONITOR_MAX_END   CFG_MALLOC_BASE
-#define CFG_RELOC_MONITOR_BASE     (CFG_RELOC_MONITOR_MAX_END-CFG_MONITOR_LEN)
+#define CONFIG_SYS_RELOC_MONITOR_MAX_END   CONFIG_SYS_MALLOC_BASE
+#define CONFIG_SYS_RELOC_MONITOR_BASE     (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
 
 /* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CFG_RELOC_MONITOR_BASE-TEXT_BASE))
+#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE))
 
 /*
  * Ethernet configuration
@@ -282,37 +282,37 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory     */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory     */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 /***** Gaisler GRLIB IP-Cores Config ********/
 
-#define CFG_GRLIB_SDRAM    0
-#define CFG_GRLIB_MEMCFG1  (0x000000ff | (1<<11))
+#define CONFIG_SYS_GRLIB_SDRAM    0
+#define CONFIG_SYS_GRLIB_MEMCFG1  (0x000000ff | (1<<11))
 #if CONFIG_GRSIM
-#define CFG_GRLIB_MEMCFG2  0x82206000
+#define CONFIG_SYS_GRLIB_MEMCFG2  0x82206000
 #else
-#define CFG_GRLIB_MEMCFG2  0x00001820
+#define CONFIG_SYS_GRLIB_MEMCFG2  0x00001820
 #endif
-#define CFG_GRLIB_MEMCFG3  0x00136000
+#define CONFIG_SYS_GRLIB_MEMCFG3  0x00136000
 
 /*** LEON2 UART 1 ***/
-#define CFG_LEON2_UART1_SCALER \
+#define CONFIG_SYS_LEON2_UART1_SCALER \
 	((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
 
 /* UART1 Define to 1 or 0 */
@@ -323,7 +323,7 @@
 
 /*** LEON2 UART 2 ***/
 
-#define CFG_LEON2_UART2_SCALER \
+#define CONFIG_SYS_LEON2_UART2_SCALER \
 	((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
 
 /* UART2 Define to 1 or 0 */
diff --git a/include/configs/gth2.h b/include/configs/gth2.h
index aaf1e4a..b1b4842 100644
--- a/include/configs/gth2.h
+++ b/include/configs/gth2.h
@@ -49,7 +49,7 @@
 #define CONFIG_BAUDRATE		115200
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
 
 /* Only interrupt boot if space is pressed */
 /* If a long serial cable is connected but */
@@ -90,7 +90,7 @@
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_DHCP
 
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
 #undef CONFIG_CMD_FAT
 #undef CONFIG_CMD_FLASH
 #undef CONFIG_CMD_FPGA
@@ -107,51 +107,51 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory	     */
-#define CFG_PROMPT		"GTH2 # "	/* Monitor Command Prompt    */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size   */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args*/
+#define CONFIG_SYS_LONGHELP				/* undef to save memory	     */
+#define CONFIG_SYS_PROMPT		"GTH2 # "	/* Monitor Command Prompt    */
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size   */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args*/
 
-#define CFG_MALLOC_LEN		128*1024
+#define CONFIG_SYS_MALLOC_LEN		128*1024
 
-#define CFG_BOOTPARAMS_LEN	128*1024
+#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024
 
-#define CFG_MHZ			500
+#define CONFIG_SYS_MHZ			500
 
-#define CFG_MIPS_TIMER_FREQ	(CFG_MHZ * 1000000)
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
 
-#define CFG_HZ			1000
+#define CONFIG_SYS_HZ			1000
 
-#define CFG_SDRAM_BASE		0x80000000     /* Cached addr */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000     /* Cached addr */
 
-#define CFG_LOAD_ADDR		0x81000000     /* default load address	*/
+#define CONFIG_SYS_LOAD_ADDR		0x81000000     /* default load address	*/
 
-#define CFG_MEMTEST_START	0x80100000
-#define CFG_MEMTEST_END		0x83000000
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x83000000
 
 #define CONFIG_HW_WATCHDOG	1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
 
 #define PHYS_FLASH		0xbfc00000 /* Flash Bank #1 */
 
 /* The following #defines are needed to get flash environment right */
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(192 << 10)
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)
 
-#define CFG_INIT_SP_OFFSET	0x400000
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
 
 /* We boot from this flash, selected with dip switch */
-#define CFG_FLASH_BASE		PHYS_FLASH
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define CONFIG_ENV_IS_NOWHERE	1
 
@@ -168,11 +168,11 @@
 #define CONFIG_MEMSIZE_IN_BYTES
 
 /*---ATA PCMCIA ------------------------------------*/
-#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
+#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
 
-#define CFG_PCMCIA_MEM_ADDR  0x20000000
-#define CFG_PCMCIA_IO_BASE   0x28000000
-#define CFG_PCMCIA_ATTR_BASE 0x30000000
+#define CONFIG_SYS_PCMCIA_MEM_ADDR  0x20000000
+#define CONFIG_SYS_PCMCIA_IO_BASE   0x28000000
+#define CONFIG_SYS_PCMCIA_ATTR_BASE 0x30000000
 
 #define CONFIG_PCMCIA_SLOT_A
 
@@ -183,31 +183,31 @@
 #define CONFIG_IDE_PCMCIA 1
 
 /* We only support one slot for now */
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
 #undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_ATA_IDE0_OFFSET	0
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_IO_BASE
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_IO_BASE
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	0
+#define CONFIG_SYS_ATA_DATA_OFFSET	0
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	0
+#define CONFIG_SYS_ATA_REG_OFFSET	0
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0200
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0200
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		16384
-#define CFG_ICACHE_SIZE		16384
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_DCACHE_SIZE		16384
+#define CONFIG_SYS_ICACHE_SIZE		16384
+#define CONFIG_SYS_CACHELINE_SIZE	32
 
 #define GPIO_CACONFIG  (1<<0)
 #define GPIO_DPACONFIG (1<<6)
diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h
index e187764..53a001d 100644
--- a/include/configs/gw8260.h
+++ b/include/configs/gw8260.h
@@ -72,7 +72,7 @@
  * 0x6       0x1     66 133     266    Close Close  Open
  * 0x6       0x2     66 133     300    Close Open   Close
  */
-#define CFG_SBC_MODCK_H 0x05
+#define CONFIG_SYS_SBC_MODCK_H 0x05
 
 /* Define this if you want to boot from 0x00000100. If you don't define
  * this, you will need to program the bootloader to 0xfff00000, and
@@ -80,48 +80,48 @@
  * way to do that is to program the bootloader at both addresses.
  * It is suggested that you just let U-Boot live at 0x00000000.
  */
-#define CFG_SBC_BOOT_LOW 1
+#define CONFIG_SYS_SBC_BOOT_LOW 1
 
 /* What should the base address of the main FLASH be and how big is
  * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
  * The main FLASH is whichever is connected to *CS0. U-Boot expects
  * this to be the SIMM.
  */
-#define CFG_FLASH0_BASE 0x40000000
-#define CFG_FLASH0_SIZE 8
+#define CONFIG_SYS_FLASH0_BASE 0x40000000
+#define CONFIG_SYS_FLASH0_SIZE 8
 
-/* Define CFG_FLASH_CHECKSUM to enable flash checksum during boot.
+/* Define CONFIG_SYS_FLASH_CHECKSUM to enable flash checksum during boot.
  * Note: the 'flashchecksum' environment variable must also be set to 'y'.
  */
-#define CFG_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_CHECKSUM
 
 /* What should be the base address of SDRAM DIMM and how big is
  * it (in Mbytes)?
  */
-#define CFG_SDRAM0_BASE 0x00000000
-#define CFG_SDRAM0_SIZE 64
+#define CONFIG_SYS_SDRAM0_BASE 0x00000000
+#define CONFIG_SYS_SDRAM0_SIZE 64
 
 /*
  * DRAM tests
- *   CFG_DRAM_TEST - enables the following tests.
+ *   CONFIG_SYS_DRAM_TEST - enables the following tests.
  *
- *   CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
+ *   CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
  *                        Environment variable 'test_dram_data' must be
  *                        set to 'y'.
- *   CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
+ *   CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
  *                        addressable. Environment variable
  *                        'test_dram_address' must be set to 'y'.
- *   CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
+ *   CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
  *                        This test takes about 6 minutes to test 64 MB.
  *                        Environment variable 'test_dram_walk' must be
  *                        set to 'y'.
  */
-#define CFG_DRAM_TEST
-#if defined(CFG_DRAM_TEST)
-#define CFG_DRAM_TEST_DATA
-#define CFG_DRAM_TEST_ADDRESS
-#define CFG_DRAM_TEST_WALK
-#endif /* CFG_DRAM_TEST */
+#define CONFIG_SYS_DRAM_TEST
+#if defined(CONFIG_SYS_DRAM_TEST)
+#define CONFIG_SYS_DRAM_TEST_DATA
+#define CONFIG_SYS_DRAM_TEST_ADDRESS
+#define CONFIG_SYS_DRAM_TEST_WALK
+#endif /* CONFIG_SYS_DRAM_TEST */
 
 /*
  * GW8260 with 16 MB DIMM:
@@ -140,10 +140,10 @@
  *     0x00F5 FFB0     Board Info Data
  *     0x00F6 0000     Malloc Arena
  *           :          CONFIG_ENV_SECT_SIZE, 256k
- *           :          CFG_MALLOC_LEN,    128k
+ *           :          CONFIG_SYS_MALLOC_LEN,    128k
  *     0x00FC 0000     RAM Copy of Monitor Code
- *           :              CFG_MONITOR_LEN,   256k
- *     0x00FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
+ *           :              CONFIG_SYS_MONITOR_LEN,   256k
+ *     0x00FF FFFF     [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
  */
 
 /*
@@ -163,10 +163,10 @@
  *     0x03F5 FFB0     Board Info Data
  *     0x03F6 0000     Malloc Arena
  *           :          CONFIG_ENV_SECT_SIZE, 256k
- *           :          CFG_MALLOC_LEN,    128k
+ *           :          CONFIG_SYS_MALLOC_LEN,    128k
  *     0x03FC 0000     RAM Copy of Monitor Code
- *           :              CFG_MONITOR_LEN,   256k
- *     0x03FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
+ *           :              CONFIG_SYS_MONITOR_LEN,   256k
+ *     0x03FF FFFF     [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
  */
 
 
@@ -233,10 +233,10 @@
  * - Select bus for bd/buffers (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 
 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
 
@@ -246,10 +246,10 @@
  * - Select bus for bd/buffers (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 
 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 
@@ -297,10 +297,10 @@
 #define CONFIG_BOOTP_DNS
 
 /* undef this to save memory */
-#define CFG_LONGHELP
+#define CONFIG_SYS_LONGHELP
 
 /* Monitor Command Prompt */
-#define CFG_PROMPT      "=> "
+#define CONFIG_SYS_PROMPT      "=> "
 
 
 /*
@@ -319,16 +319,16 @@
 
 
 /* Where do the internal registers live? */
-#define CFG_IMMR        0xf0000000
+#define CONFIG_SYS_IMMR        0xf0000000
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* What is the address of IO controller */
-#define CFG_IO_BASE 0xe0000000
+#define CONFIG_SYS_IO_BASE 0xe0000000
 
 /*****************************************************************************
  *
@@ -344,44 +344,44 @@
  * Miscellaneous configurable options
  */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CBSIZE        1024    /* Console I/O Buffer Size       */
+#  define CONFIG_SYS_CBSIZE        1024    /* Console I/O Buffer Size       */
 #else
-#  define CFG_CBSIZE        256     /* Console I/O Buffer Size       */
+#  define CONFIG_SYS_CBSIZE        256     /* Console I/O Buffer Size       */
 #endif
 
 /* Print Buffer Size */
-#define CFG_PBSIZE    (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
+#define CONFIG_SYS_PBSIZE    (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 
-#define CFG_MAXARGS     8          /* max number of command args   */
+#define CONFIG_SYS_MAXARGS     8          /* max number of command args   */
 
-#define CFG_BARGSIZE    CFG_CBSIZE /* Boot Argument Buffer Size    */
+#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size    */
 
 /* Convert clocks to MHZ when passing board info to kernel.
  * This must be defined for eariler 2.4 kernels (~2.4.4).
  */
 #define CONFIG_CLOCKS_IN_MHZ
 
-#define CFG_LOAD_ADDR   0x100000 /* default load address */
-#define CFG_HZ          1000     /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_LOAD_ADDR   0x100000 /* default load address */
+#define CONFIG_SYS_HZ          1000     /* decrementer freq: 1 ms ticks */
 
 
 /* memtest works from the end of the exception vector table
  * to the end of the DRAM less monitor and malloc area
  */
-#define CFG_MEMTEST_START   0x2000
+#define CONFIG_SYS_MEMTEST_START   0x2000
 
-#define CFG_STACK_USAGE     0x10000 /* Reserve 64k for the stack usage */
+#define CONFIG_SYS_STACK_USAGE     0x10000 /* Reserve 64k for the stack usage */
 
-#define CFG_MEM_END_USAGE   ( CFG_MONITOR_LEN \
-			    + CFG_MALLOC_LEN \
+#define CONFIG_SYS_MEM_END_USAGE   ( CONFIG_SYS_MONITOR_LEN \
+			    + CONFIG_SYS_MALLOC_LEN \
 			    + CONFIG_ENV_SECT_SIZE \
-			    + CFG_STACK_USAGE )
+			    + CONFIG_SYS_STACK_USAGE )
 
-#define CFG_MEMTEST_END     ( CFG_SDRAM_SIZE * 1024 * 1024 \
-			    - CFG_MEM_END_USAGE )
+#define CONFIG_SYS_MEMTEST_END     ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
+			    - CONFIG_SYS_MEM_END_USAGE )
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -389,98 +389,98 @@
  * You should know what you are doing if you make changes here.
  */
 
-#define CFG_FLASH_BASE  CFG_FLASH0_BASE
-#define CFG_FLASH_SIZE  CFG_FLASH0_SIZE
-#define CFG_SDRAM_BASE  CFG_SDRAM0_BASE
-#define CFG_SDRAM_SIZE  CFG_SDRAM0_SIZE
+#define CONFIG_SYS_FLASH_BASE  CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_FLASH_SIZE  CONFIG_SYS_FLASH0_SIZE
+#define CONFIG_SYS_SDRAM_BASE  CONFIG_SYS_SDRAM0_BASE
+#define CONFIG_SYS_SDRAM_SIZE  CONFIG_SYS_SDRAM0_SIZE
 
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  */
-#if defined(CFG_SBC_BOOT_LOW)
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#if defined(CONFIG_SYS_SBC_BOOT_LOW)
+#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 #else
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (0)
-#endif /* defined(CFG_SBC_BOOT_LOW) */
+#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (0)
+#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
 
-/* get the HRCW ISB field from CFG_IMMR */
-#define CFG_SBC_HRCW_IMMR   ( ((CFG_IMMR & 0x10000000) >> 10) | \
-		  ((CFG_IMMR & 0x01000000) >>  7) | \
-		  ((CFG_IMMR & 0x00100000) >>  4) )
+/* get the HRCW ISB field from CONFIG_SYS_IMMR */
+#define CONFIG_SYS_SBC_HRCW_IMMR   ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
+		  ((CONFIG_SYS_IMMR & 0x01000000) >>  7) | \
+		  ((CONFIG_SYS_IMMR & 0x00100000) >>  4) )
 
-#define CFG_HRCW_MASTER     ( HRCW_BPS11                | \
+#define CONFIG_SYS_HRCW_MASTER     ( HRCW_BPS11                | \
 		  HRCW_DPPC11               | \
-		  CFG_SBC_HRCW_IMMR         | \
+		  CONFIG_SYS_SBC_HRCW_IMMR         | \
 		  HRCW_MMR00                | \
 		  HRCW_LBPC11               | \
 		  HRCW_APPC10               | \
 		  HRCW_CS10PC00             | \
-		  (CFG_SBC_MODCK_H & HRCW_MODCK_H1111)  | \
-		  CFG_SBC_HRCW_BOOT_FLAGS )
+		  (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111)  | \
+		  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
 
 /* no slaves */
-#define CFG_HRCW_SLAVE1     0
-#define CFG_HRCW_SLAVE2     0
-#define CFG_HRCW_SLAVE3     0
-#define CFG_HRCW_SLAVE4     0
-#define CFG_HRCW_SLAVE5     0
-#define CFG_HRCW_SLAVE6     0
-#define CFG_HRCW_SLAVE7     0
+#define CONFIG_SYS_HRCW_SLAVE1     0
+#define CONFIG_SYS_HRCW_SLAVE2     0
+#define CONFIG_SYS_HRCW_SLAVE3     0
+#define CONFIG_SYS_HRCW_SLAVE4     0
+#define CONFIG_SYS_HRCW_SLAVE5     0
+#define CONFIG_SYS_HRCW_SLAVE6     0
+#define CONFIG_SYS_HRCW_SLAVE7     0
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR    CFG_IMMR
-#define CFG_INIT_RAM_END     0x4000  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE   128 /* bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET   CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR    CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END     0x4000  /* End of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_SIZE   128 /* bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET   CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
  */
-#define CFG_MONITOR_BASE    CFG_FLASH0_BASE
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_FLASH0_BASE
 
-#define CFG_MONITOR_LEN     (256 * 1024) /* Reserve 256 kB for Monitor   */
-#define CFG_MALLOC_LEN      (128 * 1024) /* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_MONITOR_LEN     (256 * 1024) /* Reserve 256 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN      (128 * 1024) /* Reserve 128 kB for malloc()  */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ       (8 * 1024 * 1024) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ       (8 * 1024 * 1024) /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS   1    /* max number of memory banks        */
-#define CFG_MAX_FLASH_SECT    32   /* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS   1    /* max number of memory banks        */
+#define CONFIG_SYS_MAX_FLASH_SECT    32   /* max number of sectors on one chip */
 
-#define CFG_FLASH_ERASE_TOUT  8000 /* Timeout for Flash Erase (in ms)   */
-#define CFG_FLASH_WRITE_TOUT  1    /* Timeout for Flash Write (in ms)   */
+#define CONFIG_SYS_FLASH_ERASE_TOUT  8000 /* Timeout for Flash Erase (in ms)   */
+#define CONFIG_SYS_FLASH_WRITE_TOUT  1    /* Timeout for Flash Write (in ms)   */
 
 #define CONFIG_ENV_IS_IN_FLASH   1
 
 #ifdef CONFIG_ENV_IN_OWN_SECT
-#  define CONFIG_ENV_ADDR        (CFG_MONITOR_BASE +  (256 * 1024))
+#  define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE +  (256 * 1024))
 #  define CONFIG_ENV_SECT_SIZE   (256 * 1024)
 #else
 #  define CONFIG_ENV_SIZE        (16 * 1024)/* Size of Environment Sector  */
-#  define CONFIG_ENV_ADD  ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) - CONFIG_ENV_SIZE)
+#  define CONFIG_ENV_ADD  ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SIZE)
 #  define CONFIG_ENV_SECT_SIZE (256 * 1024)/* see README - env sect real size  */
 #endif /* CONFIG_ENV_IN_OWN_SECT */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE  32      /* For MPC8260 CPU */
+#define CONFIG_SYS_CACHELINE_SIZE  32      /* For MPC8260 CPU */
 
 #if defined(CONFIG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT    5   /* log base 2 of the above value */
+# define CONFIG_SYS_CACHELINE_SHIFT    5   /* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -493,36 +493,36 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT   (HID0_ICE  |\
+#define CONFIG_SYS_HID0_INIT   (HID0_ICE  |\
 			 HID0_DCE  |\
 			 HID0_ICFI |\
 			 HID0_DCI  |\
 			 HID0_IFEM |\
 			 HID0_ABE)
 
-#define CFG_HID0_FINAL  (HID0_ICE  |\
+#define CONFIG_SYS_HID0_FINAL  (HID0_ICE  |\
 			 HID0_IFEM |\
 			 HID0_ABE  |\
 			 HID0_EMCP)
-#define CFG_HID2    0
+#define CONFIG_SYS_HID2    0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register
  *-----------------------------------------------------------------------
  */
-#define CFG_RMR     0
+#define CONFIG_SYS_RMR     0
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration                           4-25
  *-----------------------------------------------------------------------
  */
-#define CFG_BCR     (BCR_ETM)
+#define CONFIG_SYS_BCR     (BCR_ETM)
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration                 4-31
  *-----------------------------------------------------------------------
  */
-#define CFG_SIUMCR  (SIUMCR_DPPC11  |\
+#define CONFIG_SYS_SIUMCR  (SIUMCR_DPPC11  |\
 		     SIUMCR_L2CPC00 |\
 		     SIUMCR_APPC10  |\
 		     SIUMCR_MMR00)
@@ -534,7 +534,7 @@
  *-----------------------------------------------------------------------
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
-#define CFG_SYPCR   (SYPCR_SWTC |\
+#define CONFIG_SYS_SYPCR   (SYPCR_SWTC |\
 		     SYPCR_BMT  |\
 		     SYPCR_PBME |\
 		     SYPCR_LBME |\
@@ -547,7 +547,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC (TMCNTSC_SEC |\
+#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
 		     TMCNTSC_ALR |\
 		     TMCNTSC_TCF |\
 		     TMCNTSC_TCE)
@@ -558,7 +558,7 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR   (PISCR_PS  |\
+#define CONFIG_SYS_PISCR   (PISCR_PS  |\
 		     PISCR_PTF |\
 		     PISCR_PTE)
 
@@ -566,13 +566,13 @@
  * SCCR - System Clock Control                           9-8
  *-----------------------------------------------------------------------
  */
-#define CFG_SCCR    0
+#define CONFIG_SYS_SCCR    0
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration                 13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR    0
+#define CONFIG_SYS_RCCR    0
 
 /*
  * Initialize Memory Controller:
@@ -618,7 +618,7 @@
  *     - No data pipelining is done
  *     - Valid
  */
-#define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
 			  BRx_PS_32                     |\
 			  BRx_MS_GPCM_P                 |\
 			  BRx_V)
@@ -637,7 +637,7 @@
  *     - One idle clock is inserted between a read access from the
  *       current bank and the next access.
  */
-#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE) |\
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
 			 ORxG_CSNT          |\
 			 ORxG_ACS_DIV1      |\
 			 ORxG_SCY_5_CLK     |\
@@ -673,7 +673,7 @@
  *     - No data pipelining is done
  *     - Valid
  */
-#define CFG_BR2_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
 			  BRx_PS_64          |\
 			  BRx_MS_SDRAM_P     |\
 			  BRx_V)
@@ -687,8 +687,8 @@
  *     - Back-to-back page mode
  *     - Internal bank interleaving within save device enabled
  */
-#if (CFG_SDRAM0_SIZE == 16)
-#define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
+#if (CONFIG_SYS_SDRAM0_SIZE == 16)
+#define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
 			 ORxS_BPD_2         |\
 			 ORxS_ROWST_PBI0_A9 |\
 			 ORxS_NUMR_11)
@@ -716,7 +716,7 @@
  *     Ref: Section 10.3.3 on page 10-21
  *-----------------------------------------------------------------------
  */
-#define CFG_PSDMR   (PSDMR_RFEN       |\
+#define CONFIG_SYS_PSDMR   (PSDMR_RFEN       |\
 		     PSDMR_SDAM_A14_IS_A5 |\
 		     PSDMR_BSMA_A16_A18   |\
 		     PSDMR_SDA10_PBI0_A9  |\
@@ -726,7 +726,7 @@
 		     PSDMR_LDOTOPRE_1C    |\
 		     PSDMR_WRC_1C         |\
 		     PSDMR_CL_2)
-#endif /* (CFG_SDRAM0_SIZE == 16) */
+#endif /* (CONFIG_SYS_SDRAM0_SIZE == 16) */
 
 /* With a 64 MB DIMM, the OR2 is configured as follows:
  *
@@ -737,8 +737,8 @@
  *     - Back-to-back page mode
  *     - Internal bank interleaving within save device enabled
  */
-#if (CFG_SDRAM0_SIZE == 64)
-#define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
+#if (CONFIG_SYS_SDRAM0_SIZE == 64)
+#define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
 	     ORxS_BPD_4         |\
 	     ORxS_ROWST_PBI0_A8     |\
 	     ORxS_NUMR_12)
@@ -766,7 +766,7 @@
  *     Ref: Section 10.3.3 on page 10-21
  *-----------------------------------------------------------------------
  */
-#define CFG_PSDMR   (PSDMR_RFEN       |\
+#define CONFIG_SYS_PSDMR   (PSDMR_RFEN       |\
 		     PSDMR_SDAM_A14_IS_A5 |\
 		     PSDMR_BSMA_A14_A16   |\
 		     PSDMR_SDA10_PBI0_A9  |\
@@ -776,10 +776,10 @@
 		     PSDMR_LDOTOPRE_1C    |\
 		     PSDMR_WRC_1C         |\
 		     PSDMR_CL_2)
-#endif  /* (CFG_SDRAM0_SIZE == 64) */
+#endif  /* (CONFIG_SYS_SDRAM0_SIZE == 64) */
 
-#define CFG_PSRT    0x0e
-#define CFG_MPTPR   MPTPR_PTP_DIV32
+#define CONFIG_SYS_PSRT    0x0e
+#define CONFIG_SYS_MPTPR   MPTPR_PTP_DIV32
 
 
 /*-----------------------------------------------------------------------
@@ -804,16 +804,16 @@
  *     - 11 wait states
  */
 
-#ifdef CFG_IO_BASE
-#  define CFG_BR4_PRELIM  ((CFG_IO_BASE & BRx_BA_MSK)  |\
+#ifdef CONFIG_SYS_IO_BASE
+#  define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_IO_BASE & BRx_BA_MSK)  |\
 			    BRx_PS_8                   |\
 			    BRx_MS_GPCM_L              |\
 			    BRx_V)
 
-#  define CFG_OR4_PRELIM   (ORxG_AM_MSK                |\
+#  define CONFIG_SYS_OR4_PRELIM   (ORxG_AM_MSK                |\
 			    ORxG_SCY_11_CLK            |\
 			    ORxG_EHTR)
-#endif /* CFG_IO_BASE */
+#endif /* CONFIG_SYS_IO_BASE */
 
 /*
  * Internal Definitions
diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h
index 5426c7a..0c70af5 100644
--- a/include/configs/hammerhead.h
+++ b/include/configs/hammerhead.h
@@ -29,7 +29,7 @@
 #define CONFIG_AT32AP7000		1
 #define CONFIG_HAMMERHEAD		1
 
-#define CFG_HZ				1000
+#define CONFIG_SYS_HZ				1000
 
 /*
  * Set up the PLL to run at 125 MHz, the CPU to run at the PLL
@@ -37,15 +37,15 @@
  * and the PBA bus to run at 1/4 the PLL frequency.
  */
 #define CONFIG_PLL			1
-#define CFG_POWER_MANAGER		1
-#define CFG_OSC0_HZ			25000000
-#define CFG_PLL0_DIV			1
-#define CFG_PLL0_MUL			5
-#define CFG_PLL0_SUPPRESS_CYCLES	16
-#define CFG_CLKDIV_CPU			0
-#define CFG_CLKDIV_HSB			1
-#define CFG_CLKDIV_PBA			2
-#define CFG_CLKDIV_PBB			1
+#define CONFIG_SYS_POWER_MANAGER		1
+#define CONFIG_SYS_OSC0_HZ			25000000
+#define CONFIG_SYS_PLL0_DIV			1
+#define CONFIG_SYS_PLL0_MUL			5
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
+#define CONFIG_SYS_CLKDIV_CPU			0
+#define CONFIG_SYS_CLKDIV_HSB			1
+#define CONFIG_SYS_CLKDIV_PBA			2
+#define CONFIG_SYS_CLKDIV_PBB			1
 
 /*
  * The PLLOPT register controls the PLL like this:
@@ -54,7 +54,7 @@
  *
  * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
  */
-#define CFG_PLL0_OPT			0x04
+#define CONFIG_SYS_PLL0_OPT			0x04
 
 #define CONFIG_USART1			1
 
@@ -117,56 +117,56 @@
 
 #define CONFIG_ATMEL_USART		1
 #define CONFIG_MACB			1
-#define CONFIG_PIO2			1
-#define CFG_NR_PIOS			5
-#define CFG_HSDRAMC			1
+#define CONFIG_PORTMUX_PIO		1
+#define CONFIG_SYS_NR_PIOS			5
+#define CONFIG_SYS_HSDRAMC			1
 #define CONFIG_MMC			1
 #define CONFIG_ATMEL_MCI		1
 
-#define CFG_DCACHE_LINESZ		32
-#define CFG_ICACHE_LINESZ		32
+#define CONFIG_SYS_DCACHE_LINESZ		32
+#define CONFIG_SYS_ICACHE_LINESZ		32
 
 #define CONFIG_NR_DRAM_BANKS		1
 
-#define CFG_FLASH_CFI			1
+#define CONFIG_SYS_FLASH_CFI			1
 #define CONFIG_FLASH_CFI_DRIVER		1
 
-#define CFG_FLASH_BASE			0x00000000
-#define CFG_FLASH_SIZE			0x800000
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		135
+#define CONFIG_SYS_FLASH_BASE			0x00000000
+#define CONFIG_SYS_FLASH_SIZE			0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		135
 
-#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 
-#define CFG_INTRAM_BASE			0x24000000
-#define CFG_INTRAM_SIZE			0x8000
+#define CONFIG_SYS_INTRAM_BASE			0x24000000
+#define CONFIG_SYS_INTRAM_SIZE			0x8000
 
-#define CFG_SDRAM_BASE			0x10000000
+#define CONFIG_SYS_SDRAM_BASE			0x10000000
 
 #define CONFIG_ENV_IS_IN_FLASH		1
 #define CONFIG_ENV_SIZE			65536
-#define CONFIG_ENV_ADDR			(CFG_FLASH_BASE + CFG_FLASH_SIZE - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
 
-#define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
 
-#define CFG_MALLOC_LEN			(256*1024)
+#define CONFIG_SYS_MALLOC_LEN			(256*1024)
 
-#define CFG_DMA_ALLOC_LEN		(16384)
+#define CONFIG_SYS_DMA_ALLOC_LEN		(16384)
 
 /* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00400000)
-#define CFG_BOOTPARAMS_LEN		(16 * 1024)
+#define CONFIG_SYS_LOAD_ADDR			(CONFIG_SYS_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT			"Hammerhead> "
-#define CFG_CBSIZE			256
-#define CFG_MAXARGS			16
-#define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_LONGHELP			1
+#define CONFIG_SYS_PROMPT			"Hammerhead> "
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP			1
 
-#define CFG_MEMTEST_START		CFG_SDRAM_BASE
-#define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x1f00000)
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + 0x1f00000)
 
-#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h
index b51ea4e..369b368 100644
--- a/include/configs/hcu4.h
+++ b/include/configs/hcu4.h
@@ -35,6 +35,12 @@
 #define CONFIG_4xx		1		/* ... PPC4xx family	*/
 #define CONFIG_405GP 1
 #define CONFIG_4xx   1
+#define CONFIG_HOSTNAME		hcu4
+
+/*
+ * Include common defines/options for all boards produced by Netstal Maschinen
+ */
+#include "netstal-common.h"
 
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
 
@@ -45,77 +51,64 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN	(320 * 1024)	/* Reserve 320 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024) /* Reserve 256 kB for malloc() */
+#define CONFIG_SYS_MONITOR_LEN	(320 * 1024)	/* Reserve 320 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024) /* Reserve 256 kB for malloc() */
 
 
-#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
-#define CFG_FLASH_BASE		0xfff80000	/* start of FLASH	*/
-#define CFG_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CONFIG_SYS_FLASH_BASE		0xfff80000	/* start of FLASH	*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 
 /* ... with on-chip memory here (4KBytes) */
-#define CFG_OCM_DATA_ADDR 0xF4000000
-#define CFG_OCM_DATA_SIZE 0x00001000
+#define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000
+#define CONFIG_SYS_OCM_DATA_SIZE 0x00001000
 /* Do not set up locked dcache as init ram. */
-#undef CFG_INIT_DCACHE_CS
+#undef CONFIG_SYS_INIT_DCACHE_CS
 
 /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
-#define CFG_TEMP_STACK_OCM 1
+#define CONFIG_SYS_TEMP_STACK_OCM 1
 
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR	/* OCM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE
-#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* OCM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE
+#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_POST_WORD_ADDR
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
 /*
- * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
  * The Linux BASE_BAUD define should match this configuration.
  *    baseBaud = cpuClock/(uartDivisor*16)
- * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  * set Linux BASE_BAUD to 403200.
  */
-#undef CFG_EXT_SERIAL_CLOCK	       /* external serial clock */
-#define CONFIG_SERIAL_MULTI  1
-/* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO */
-#undef	CFG_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD	    691200
-
-/* Size (bytes) of interrupt driven serial port buffer.
- * Set to 0 to use polling instead of interrupts.
- * Setting to 0 will also disable RTS/CTS handshaking.
- */
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#undef	CONFIG_SYS_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD	    691200
 
 /* Set console baudrate to 9600 */
 #define CONFIG_BAUDRATE		9600
 
-
-#define CFG_BAUDRATE_TABLE						\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
 /*-----------------------------------------------------------------------
  * Flash
  *----------------------------------------------------------------------*/
 
 /* Use common CFI driver */
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
 /* board provides its own flash_init code */
 #define CONFIG_FLASH_CFI_LEGACY		1
-#define CFG_FLASH_CFI_WIDTH		FLASH_CFI_8BIT
-#define CFG_FLASH_LEGACY_512Kx8 1
+#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_8BIT
+#define CONFIG_SYS_FLASH_LEGACY_512Kx8 1
 
 /* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip */
 
 /*-----------------------------------------------------------------------
  * Environment
@@ -135,7 +128,7 @@
 #ifdef CONFIG_ENV_IS_IN_FLASH
 /* Put the environment in Flash */
 #define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		((-CFG_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		8*1024	/* 8 KB Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -147,77 +140,14 @@
  * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
  * the first internal I2C controller of the PPC440EPx
  *----------------------------------------------------------------------*/
-#define CFG_SPD_BUS_NUM		0
-
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-/* This is the 7bit address of the device, not including P. */
-#define CFG_I2C_EEPROM_ADDR 0x50
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-
-/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#undef CFG_I2C_MULTI_EEPROMS
-
+#define CONFIG_SYS_SPD_BUS_NUM		0
 
-#define CONFIG_PREBOOT	"echo;"						\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
+#define CONFIG_IPADDR		172.25.1.14
 
-#undef	CONFIG_BOOTARGS
-
-/* Setup some board specific values for the default environment variables */
-#define CONFIG_HOSTNAME		hcu4
-#define CONFIG_IPADDR		172.25.1.99
-#define CONFIG_ETHADDR      00:60:13:00:00:00   /* Netstal Machines AG MAC */
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-#define CONFIG_SERVERIP		172.25.1.3
-
-#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
-
-#define	CONFIG_EXTRA_ENV_SETTINGS				\
-	"netdev=eth0\0"							\
-	"loadaddr=0x01000000\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"		\
-	        "bootm\0"						\
-	"rootpath=/home/diagnose/eldk/ppc_4xx\0"			\
-	"bootfile=/tftpboot/hcu4/uImage\0"				\
-	"load=tftp 100000 hcu4/u-boot.bin\0"				\
-	"update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;"	\
-		"cp.b 100000 FFFB0000 50000\0"			        \
-	"upd=run load update\0"						\
-	"vx_rom=hcu4/hcu4_vx_rom\0"					\
-	"vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0"		\
-	"vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}"	\
-	" h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0"	\
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_NETSTAL_DEF_ENV						\
+	CONFIG_NETSTAL_DEF_ENV_POWERPC					\
 	""
-#define CONFIG_BOOTCOMMAND	"run vx"
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR	1	/* PHY address			*/
-
-#define CONFIG_PHY_RESET        1	/* reset phy upon startup */
-
-#define CONFIG_HAS_ETH0
-#define CFG_RX_ETH_BUFFER	16 /* Number of ethernet rx buffers & desC */
 
 /*
  * BOOTP options
@@ -253,95 +183,88 @@
 #define SPD_EEPROM_ADDRESS      0x50
 
 /* POST support */
-#define CONFIG_POST		(CFG_POST_MEMORY   | \
-				 CFG_POST_CPU	   | \
-				 CFG_POST_UART	   | \
-				 CFG_POST_I2C	   | \
-				 CFG_POST_CACHE	   | \
-				 CFG_POST_ETHER	   | \
-				 CFG_POST_SPR)
-
-#define CFG_POST_UART_TABLE	{UART0_BASE}
-#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_UART	   | \
+				 CONFIG_SYS_POST_I2C	   | \
+				 CONFIG_SYS_POST_CACHE	   | \
+				 CONFIG_SYS_POST_ETHER	   | \
+				 CONFIG_SYS_POST_SPR)
+
+#define CONFIG_SYS_POST_UART_TABLE	{UART0_BASE}
+#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 #undef  CONFIG_LOGBUFFER
-#define CFG_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/
-#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+#define CONFIG_SYS_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  *----------------------------------------------------------------------*/
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-	#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  */
 
-#define CFG_EBC_CFG	0x98400000
+#define CONFIG_SYS_EBC_CFG	0x98400000
 
 /* Memory Bank 0 (Flash Bank 0) initialization	*/
-#define CFG_EBC_PB0AP	0x02005400
-#define CFG_EBC_PB0CR	0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB0AP	0x02005400
+#define CONFIG_SYS_EBC_PB0CR	0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
 
-#define CFG_EBC_PB1AP	0x03041200
-#define CFG_EBC_PB1CR	0x7009A000  /* BAS=,BS=MB,BU=R/W,BW=bit	*/
+#define CONFIG_SYS_EBC_PB1AP	0x03041200
+#define CONFIG_SYS_EBC_PB1CR	0x7009A000  /* BAS=,BS=MB,BU=R/W,BW=bit	*/
 
-#define CFG_EBC_PB2AP	0x02054500
-#define CFG_EBC_PB2CR	0x78018000  /* BAS=,BS=MB,BU=R/W,BW=bit	*/
+#define CONFIG_SYS_EBC_PB2AP	0x02054500
+#define CONFIG_SYS_EBC_PB2CR	0x78018000  /* BAS=,BS=MB,BU=R/W,BW=bit	*/
 
-#define CFG_EBC_PB3AP	0x01840300
-#define CFG_EBC_PB3CR	0x7c0ba000  /* BAS=,BS=MB,BU=R/W,BW=bit	*/
+#define CONFIG_SYS_EBC_PB3AP	0x01840300
+#define CONFIG_SYS_EBC_PB3CR	0x7c0ba000  /* BAS=,BS=MB,BU=R/W,BW=bit	*/
 
-#define CFG_EBC_PB4AP	0x01800300
-#define CFG_EBC_PB4CR	0x7e0ba000  /* BAS=,BS=MB,BU=R/W,BW=bit	*/
+#define CONFIG_SYS_EBC_PB4AP	0x01800300
+#define CONFIG_SYS_EBC_PB4CR	0x7e0ba000  /* BAS=,BS=MB,BU=R/W,BW=bit	*/
 
-#define CFG_GPIO0_OR	0xF27FFFFF  /* GPIO value */
-#define CFG_GPIO0_TCR	0x7FFE0000  /* GPIO value */
-#define CFG_GPIO0_ODR	0x00E897FC  /* GPIO value */
+#define CONFIG_SYS_GPIO0_OR	0xF27FFFFF  /* GPIO value */
+#define CONFIG_SYS_GPIO0_TCR	0x7FFE0000  /* GPIO value */
+#define CONFIG_SYS_GPIO0_ODR	0x00E897FC  /* GPIO value */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)/* Initial Memory map for Linux */
 
 /* Init Memory Controller:
  *
  * BR0/1 and OR0/1 (FLASH)
  */
 
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	*/
 #define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
 
 
 /* Configuration Port location */
 #define CONFIG_PORT_ADDR	0xF0000500
 
-#define CFG_HUSH_PARSER                 /* use "hush" command parser    */
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER                 /* use "hush" command parser    */
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
@@ -349,8 +272,4 @@
 #define CONFIG_KGDB_SER_INDEX	2	    /* which serial port to use */
 #endif
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h
index 1874ff2..26d2d0c 100644
--- a/include/configs/hcu5.h
+++ b/include/configs/hcu5.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007 Netstal Maschinen AG
+ * (C) Copyright 2007-2008 Netstal Maschinen AG
  * Niklaus Giger (Niklaus.Giger@netstal.com)
  *
  * (C) Copyright 2006-2007
@@ -39,8 +39,14 @@
 #define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
 #define CONFIG_440		1		/* ... PPC440 family	*/
 #define CONFIG_4xx		1		/* ... PPC4xx family	*/
-#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
+#define CONFIG_HOSTNAME		hcu5
+
+/*
+ * Include common defines/options for all boards produced by Netstal Maschinen
+ */
+#include "netstal-common.h"
 
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
 #define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
 
@@ -48,60 +54,48 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN	(320 * 1024)	/* Reserve 320 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024) /* Reserve 256 kB for malloc() */
-
-#define CFG_TLB_FOR_BOOT_FLASH  3
-#define CFG_BOOT_BASE_ADDR	0xfff00000
-#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
-#define CFG_FLASH_BASE		0xfff80000	/* start of FLASH	*/
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_OCM_BASE		0xe0010000      /* ocm			*/
-#define CFG_OCM_DATA_ADDR	CFG_OCM_BASE
-#define CFG_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
-#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
-#define CFG_PCI_MEMBASE1	CFG_PCI_MEMBASE  + 0x10000000
-#define CFG_PCI_MEMBASE2	CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3	CFG_PCI_MEMBASE2 + 0x10000000
+#define CONFIG_SYS_MONITOR_LEN	(320 * 1024)	/* Reserve 320 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024) /* Reserve 256 kB for malloc() */
+
+#define CONFIG_SYS_TLB_FOR_BOOT_FLASH  3
+#define CONFIG_SYS_BOOT_BASE_ADDR	0xfff00000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CONFIG_SYS_FLASH_BASE		0xfff80000	/* start of FLASH	*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_OCM_BASE		0xe0010000      /* ocm			*/
+#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_OCM_BASE
+#define CONFIG_SYS_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CONFIG_SYS_PCI_MEMBASE1	CONFIG_SYS_PCI_MEMBASE  + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2	CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3	CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
 
 /* Don't change either of these */
-#define CFG_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
+#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
 
-#define CFG_USB2D0_BASE		0xe0000100
-#define CFG_USB_DEVICE		0xe0000000
-#define CFG_USB_HOST		0xe0000400
+#define CONFIG_SYS_USB2D0_BASE		0xe0000100
+#define CONFIG_SYS_USB_DEVICE		0xe0000000
+#define CONFIG_SYS_USB_HOST		0xe0000400
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer
  *----------------------------------------------------------------------*/
 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
-#define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM			*/
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
 
-#define CFG_INIT_RAM_END	(4 << 10)
-#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_POST_WORD_ADDR
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#undef CFG_EXT_SERIAL_CLOCK	       /* external serial clock */
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_SERIAL_MULTI     1
-/* needed to be able to define
-	CONFIG_SERIAL_SOFTWARE_FIFO, but
-	CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */
-/* Size (bytes) of interrupt driven serial port buffer.
- * Set to 0 to use polling instead of interrupts.
- * Setting to 0 will also disable RTS/CTS handshaking.
- */
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK	       /* external serial clock */
+#define CONFIG_BAUDRATE		115200
 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 #undef CONFIG_UART1_CONSOLE
 
-#undef CONFIG_CMD_HWFLOW
-#define CFG_BAUDRATE_TABLE						\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
@@ -114,15 +108,15 @@
 #ifdef  CONFIG_ENV_IS_IN_EEPROM
 /* Put the environment after the SDRAM and bootstrap configuration */
 #define PROM_SIZE	2048
-#define CFG_BOOSTRAP_OPTION_OFFSET	 512
-#define CONFIG_ENV_OFFSET	 (CFG_BOOSTRAP_OPTION_OFFSET + 0x10)
+#define CONFIG_SYS_BOOSTRAP_OPTION_OFFSET	 512
+#define CONFIG_ENV_OFFSET	 (CONFIG_SYS_BOOSTRAP_OPTION_OFFSET + 0x10)
 #define CONFIG_ENV_SIZE	(PROM_SIZE-CONFIG_ENV_OFFSET)
 #endif
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 /* Put the environment in Flash */
 #define CONFIG_ENV_SECT_SIZE	0x10000 /* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		((-CFG_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		8*1024	/* 8 KB Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -134,8 +128,8 @@
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
-#define CFG_MBYTES_SDRAM        (128)		/* 128 MB or 256 MB	*/
-#define CFG_DDR_CACHED_ADDR	0x50000000	/* setup 2nd TLB cached here */
+#define CONFIG_SYS_MBYTES_SDRAM        (128)		/* 128 MB or 256 MB	*/
+#define CONFIG_SYS_DDR_CACHED_ADDR	0x50000000	/* setup 2nd TLB cached here */
 #undef  CONFIG_DDR_DATA_EYE		/* Do not use DDR2 optimization	*/
 #define CONFIG_DDR_ECC		1	/* enable ECC			*/
 
@@ -144,94 +138,26 @@
 #define PM_RESERVED_MEM       (  64)  /* in kB: pmLib reserved area size */
 #define CONFIG_PRAM           ( USER_RESERVED_MEM + PM_RESERVED_MEM )
 
+#define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
+					/* 440EPx errata CHIP 11	*/
+
 /*-----------------------------------------------------------------------
  * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
  * the second internal I2C controller of the PPC440EPx
  *----------------------------------------------------------------------*/
-#define CFG_SPD_BUS_NUM	1
-
-#define CONFIG_HARD_I2C	1	/* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-/* This is the 7bit address of the device, not including P. */
-#define CFG_I2C_EEPROM_ADDR 0x50
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-
-/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#undef CFG_I2C_MULTI_EEPROMS
-
-
-#define CONFIG_PREBOOT	"echo;"						\
-	"echo Type \"run nfs\" to mount Linux root filesystem over NFS;"\
-	"echo"
-
-#undef	CONFIG_BOOTARGS
+#define CONFIG_SYS_SPD_BUS_NUM	1
 
 /* Setup some board specific values for the default environment variables */
-#define CONFIG_HOSTNAME		hcu5
-#define CONFIG_IPADDR		172.25.1.99
-#define CONFIG_ETHADDR	00:60:13:00:00:00 /* Netstal Machines AG MAC */
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-#define CONFIG_SERVERIP		172.25.1.3
-
-#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
+#define CONFIG_IPADDR		172.25.1.15
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"loadaddr=0x01000000\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"		\
-		"bootm\0"						\
-		"bootfile=hcu5/uImage\0"				\
-		"rootpath=/home/hcu/eldk/ppc_4xxFP\0"			\
-		"load=tftp 100000 hcu5/u-boot.bin\0"			\
-	"update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;"	\
-		"cp.b 100000 FFFB0000 50000\0"			        \
-	"upd=run load update\0"						\
-	"vx_rom=hcu5/hcu5_vx_rom\0"					\
-	"vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0"		\
-	"vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}"	\
-	" h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0"	\
-	"usbargs=setenv bootargs root=/dev/sda1 ro\0"			\
-	"linux=usb start; ext2load usb 0 ${loadaddr} /boot/uImage;"     \
-	"run usbargs addip addtty; bootm\0"				\
-	"net_nfs_fdt=tftp 200000 ${bootfile};"				\
-		"tftp ${fdt_addr} ${fdt_file};"				\
-		"run nfsargs addip addtty;"				\
-		"bootm 200000 - ${fdt_addr}\0"				\
-		"fdt_file=hcu5/hcu5.dtb\0"				\
-	"fdt_addr=400000\0"						\
+	CONFIG_NETSTAL_DEF_ENV						\
+	CONFIG_NETSTAL_DEF_ENV_POWERPC					\
 	""
-#define CONFIG_BOOTCOMMAND	"run vx"
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_M88E1111_PHY	1
 #define	CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR	1	/* PHY address, like on HCU4	*/
-
-#define CONFIG_PHY_RESET       1	/* reset phy upon startup         */
-
-#define CONFIG_HAS_ETH0
-#define CFG_RX_ETH_BUFFER	32 /* Number of ethernet rx buffers & desc. */
 
-#define CONFIG_NET_MULTI	1
 #define CONFIG_HAS_ETH1	1	/* add support for "eth1addr" */
 #define CONFIG_PHY1_ADDR	2
 
@@ -279,48 +205,39 @@
 #define CONFIG_CMD_USB
 
 /* POST support */
-#define CONFIG_POST		(CFG_POST_MEMORY   | \
-				 CFG_POST_CPU	   | \
-				 CFG_POST_UART	   | \
-				 CFG_POST_I2C	   | \
-				 CFG_POST_CACHE	   | \
-				 CFG_POST_FPU	   | \
-				 CFG_POST_ETHER	   | \
-				 CFG_POST_SPR)
-#define CFG_POST_UART_TABLE	{UART0_BASE}
-
-#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_POST_CACHE_ADDR	0x7fff0000 /* free virtual address	*/
-#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_UART	   | \
+				 CONFIG_SYS_POST_I2C	   | \
+				 CONFIG_SYS_POST_CACHE	   | \
+				 CONFIG_SYS_POST_FPU	   | \
+				 CONFIG_SYS_POST_ETHER	   | \
+				 CONFIG_SYS_POST_SPR)
+#define CONFIG_SYS_POST_UART_TABLE	{UART0_BASE}
+
+#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_SYS_POST_CACHE_ADDR	0x7fff0000 /* free virtual address	*/
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 
 #define CONFIG_SUPPORT_VFAT
 
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  *----------------------------------------------------------------------*/
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
-#define CFG_MEMTEST_END	0x0C00000 /* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -329,80 +246,80 @@
 #define CONFIG_PCI		1	/* include pci support	        */
 #undef CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
-#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr map to CFG_PCI_MEMBASE*/
+#define CONFIG_SYS_PCI_TARGBASE        0x80000000 /* PCIaddr map to CONFIG_SYS_PCI_MEMBASE*/
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT
-#define CFG_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
 
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
-#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
+#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * Flash
  *----------------------------------------------------------------------*/
 
 /* Use common CFI driver */
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
 /* board provides its own flash_init code */
 #define CONFIG_FLASH_CFI_LEGACY		1
-#define CFG_FLASH_CFI_WIDTH		FLASH_CFI_8BIT
-#define CFG_FLASH_LEGACY_512Kx8 1
+#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_8BIT
+#define CONFIG_SYS_FLASH_LEGACY_512Kx8 1
 
 /* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip */
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
-#define CFG_FLASH		CFG_FLASH_BASE
-#define CFG_CS_1		0xC8000000 /* CAN */
-#define CFG_CS_2		0xCC000000 /* CPLD and IMC-Bus Standard */
-#define CFG_CPLD		CFG_CS_2
-#define CFG_CS_3		0xCE000000 /* CPLD and IMC-Bus Fast  */
+#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS_1		0xC8000000 /* CAN */
+#define CONFIG_SYS_CS_2		0xCC000000 /* CPLD and IMC-Bus Standard */
+#define CONFIG_SYS_CPLD		CONFIG_SYS_CS_2
+#define CONFIG_SYS_CS_3		0xCE000000 /* CPLD and IMC-Bus Fast  */
 
-#define CFG_BOOTFLASH_CS	0	/* Boot Flash chip connected to CSx */
-#define CFG_EBC_PB0AP		0x02005400
-#define CFG_EBC_PB0CR		0xFFF18000 /* (CFG_FLASH | 0xda000)  */
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
+#define CONFIG_SYS_BOOTFLASH_CS	0	/* Boot Flash chip connected to CSx */
+#define CONFIG_SYS_EBC_PB0AP		0x02005400
+#define CONFIG_SYS_EBC_PB0CR		0xFFF18000 /* (CONFIG_SYS_FLASH | 0xda000)  */
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	*/
 
 /* Memory Bank 1 CAN-Chips initialization				*/
-#define CFG_EBC_PB1AP		0x02054500
-#define CFG_EBC_PB1CR		0xC8018000
+#define CONFIG_SYS_EBC_PB1AP		0x02054500
+#define CONFIG_SYS_EBC_PB1CR		0xC8018000
 
 /* Memory Bank 2 CPLD/IMC-Bus standard initialization			*/
-#define CFG_EBC_PB2AP		0x01840300
-#define CFG_EBC_PB2CR		0xCC0BA000
+#define CONFIG_SYS_EBC_PB2AP		0x01840300
+#define CONFIG_SYS_EBC_PB2CR		0xCC0BA000
 
 /* Memory Bank 3 IMC-Bus fast mode initialization			*/
-#define CFG_EBC_PB3AP		0x01800300
-#define CFG_EBC_PB3CR		0xCE0BA000
+#define CONFIG_SYS_EBC_PB3AP		0x01800300
+#define CONFIG_SYS_EBC_PB3CR		0xCE0BA000
 
 /* Memory Bank 4 (not used) initialization				*/
-#undef CFG_EBC_PB4AP
-#undef CFG_EBC_PB4CR
+#undef CONFIG_SYS_EBC_PB4AP
+#undef CONFIG_SYS_EBC_PB4CR
 
 /* Memory Bank 5 (not used) initialization				*/
-#undef CFG_EBC_PB5AP
-#undef CFG_EBC_PB5CR
+#undef CONFIG_SYS_EBC_PB5AP
+#undef CONFIG_SYS_EBC_PB5CR
 
-#define HCU_CPLD_VERSION_REGISTER ( CFG_CPLD + 0x0F00000 )
-#define HCU_HW_VERSION_REGISTER   ( CFG_CPLD + 0x1400000 )
+#define HCU_CPLD_VERSION_REGISTER ( CONFIG_SYS_CPLD + 0x0F00000 )
+#define HCU_HW_VERSION_REGISTER   ( CONFIG_SYS_CPLD + 0x1400000 )
 
-#define CFG_HUSH_PARSER                 /* use "hush" command parser    */
-#ifdef  CFG_HUSH_PARSER
-	#define CFG_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_HUSH_PARSER                 /* use "hush" command parser    */
+#ifdef  CONFIG_SYS_HUSH_PARSER
+	#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
@@ -410,8 +327,4 @@
 #define CONFIG_KGDB_SER_INDEX	2	    /* which serial port to use */
 #endif
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/hermes.h b/include/configs/hermes.h
index e1a0846..0df46fa 100644
--- a/include/configs/hermes.h
+++ b/include/configs/hermes.h
@@ -60,7 +60,7 @@
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -83,29 +83,29 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address	*/
 
-#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+#define	CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define	CFG_ALLOC_DPRAM		1	/* use allocation routines	*/
+#define	CONFIG_SYS_ALLOC_DPRAM		1	/* use allocation routines	*/
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
@@ -114,46 +114,46 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFF000000	/* Non-Standard value!	*/
+#define CONFIG_SYS_IMMR		0xFF000000	/* Non-Standard value!	*/
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFE000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
 #ifdef	DEBUG
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	124	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	124	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x4000	/*   Offset   of Environment Sector	*/
@@ -161,9 +161,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -174,10 +174,10 @@
  * +0x0004
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -185,7 +185,7 @@
  *-----------------------------------------------------------------------
  * +0x0000 => 0x000000C0
  */
-#define CFG_SIUMCR	0
+#define CONFIG_SYS_SIUMCR	0
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
@@ -193,7 +193,7 @@
  * Clear Reference Interrupt Status, Timebase freezing enabled
  * +0x0200 => 0x00C2
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
@@ -201,7 +201,7 @@
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  * +0x0240 => 0x0082
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -210,7 +210,7 @@
  * interrupt status bit, set PLL multiplication factor !
  */
 /* +0x0286 => 0x00B0D0C0 */
-#define CFG_PLPRCR							\
+#define CONFIG_SYS_PLPRCR							\
 		(	(11 << PLPRCR_MF_SHIFT) |			\
 			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
 			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
@@ -225,7 +225,7 @@
  */
 #define SCCR_MASK	SCCR_EBDF11
 /* +0x0282 => 0x03800000 */
-#define CFG_SCCR	(SCCR_COM00	|   SCCR_TBS	  |	\
+#define CONFIG_SYS_SCCR	(SCCR_COM00	|   SCCR_TBS	  |	\
 			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
 			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
 			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
@@ -237,7 +237,7 @@
  *-----------------------------------------------------------------------
  */
 /* +0x0220 => 0x00C3 */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 
 /*-----------------------------------------------------------------------
@@ -245,20 +245,20 @@
  *-----------------------------------------------------------------------
  */
 /* +0x09C4 => TIMEP=1 */
-#define CFG_RCCR 0x0100
+#define CONFIG_SYS_RCCR 0x0100
 
 /*-----------------------------------------------------------------------
  * RMDS - RISC Microcode Development Support Control Register
  *-----------------------------------------------------------------------
  */
-#define CFG_RMDS 0
+#define CONFIG_SYS_RMDS 0
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -273,17 +273,17 @@
  * but not too much to meddle with FLASH accesses
  */
 /* allow for max 4 MB of Flash */
-#define CFG_REMAP_OR_AM		0xFFC00000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFFC00000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0xFFC00000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFFC00000	/* OR addr mask */
 
 /* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0	*/
-#define CFG_OR_TIMING_FLASH	( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH	( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \
 				 OR_SCY_5_CLK | OR_TRLX)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 /* 8 bit, bank valid */
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 
 /*
  * BR1/OR1 - SDRAM
@@ -296,8 +296,8 @@
 
 #define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
 
-#define CFG_OR1_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR1_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
+#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /*
  * BR2/OR2 - HPRO2: PEB2256   @ 0xE0000000, 8 Bit wide
@@ -306,8 +306,8 @@
 #define HPRO2_OR_AM		0xFFFF8000
 #define HPRO2_TIMING		0x00000934
 
-#define CFG_OR2 (HPRO2_OR_AM | HPRO2_TIMING)
-#define CFG_BR2	((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR2 (HPRO2_OR_AM | HPRO2_TIMING)
+#define CONFIG_SYS_BR2	((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 
 /*
  * BR3/OR3: not used
@@ -322,14 +322,14 @@
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h
index e816b6d..a81527e 100644
--- a/include/configs/hmi1001.h
+++ b/include/configs/hmi1001.h
@@ -33,7 +33,7 @@
 #define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
 #define CONFIG_HMI1001		1	/* HMI1001 board			*/
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM		0x02	/* Software reboot			*/
@@ -47,7 +47,7 @@
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /* Partitions */
 #define CONFIG_DOS_PARTITION
@@ -81,7 +81,7 @@
 #define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
 
 #if (TEXT_BASE == 0xFFF00000) /* Boot low */
-#   define CFG_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT		1
 #endif
 
 /*
@@ -116,49 +116,49 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
 
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration
  */
-#define CFG_I2C_EEPROM_ADDR		0x58
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 
 /*
  * RTC configuration
  */
 #define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR		0x51
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
 
 /*
  * Flash configuration
  */
-#define CFG_FLASH_BASE		0xFF800000
+#define CONFIG_SYS_FLASH_BASE		0xFF800000
 
-#define CFG_FLASH_SIZE		0x00800000 /* 8 MByte */
-#define CFG_MAX_FLASH_SECT	67	/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_SIZE		0x00800000 /* 8 MByte */
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max num of sects on one chip */
 
 #define CONFIG_ENV_ADDR		(TEXT_BASE+0x40000) /* second sector */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
 					   (= chip selects) */
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_CFI_AMD_RESET
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
 
 /*
  * Environment settings
@@ -172,12 +172,12 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
-#define CFG_DISPLAY_BASE	0x80600000
-#define CFG_STATUS1_BASE	0x80600200
-#define CFG_STATUS2_BASE	0x80600300
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_DISPLAY_BASE	0x80600000
+#define CONFIG_SYS_STATUS1_BASE	0x80600200
+#define CONFIG_SYS_STATUS2_BASE	0x80600300
 
 /* Settings for XLB = 132 MHz */
 #define SDRAM_DDR	 1
@@ -189,68 +189,69 @@
 #define SDRAM_TAPDELAY  0x10000000
 
 /* Use ON-Chip SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
 #else
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
 #endif
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
 #define CONFIG_PHY_ADDR		0x00
 #define CONFIG_MII		1		/* MII PHY management		*/
 
 /*
  * GPIO configuration
  */
-#define CFG_GPS_PORT_CONFIG	0x01051004
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x01051004
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /* Enable an alternate, more extensive memory test */
-#define CFG_ALT_MEMTEST
+#define CONFIG_SYS_ALT_MEMTEST
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 /*
  * Enable loopw command.
@@ -261,36 +262,36 @@
  * Various low-level settings
  */
 #if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 #else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
 #endif
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x0004FB00
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x0004FB00
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
 /* 8Mbit SRAM @0x80100000 */
-#define CFG_CS1_START		0x80100000
-#define CFG_CS1_SIZE		0x00100000
-#define CFG_CS1_CFG		0x19B00
+#define CONFIG_SYS_CS1_START		0x80100000
+#define CONFIG_SYS_CS1_SIZE		0x00100000
+#define CONFIG_SYS_CS1_CFG		0x19B00
 
 /* FRAM 32Kbyte @0x80700000 */
-#define CFG_CS2_START		0x80700000
-#define CFG_CS2_SIZE		0x00008000
-#define CFG_CS2_CFG		0x19800
+#define CONFIG_SYS_CS2_START		0x80700000
+#define CONFIG_SYS_CS2_SIZE		0x00008000
+#define CONFIG_SYS_CS2_CFG		0x19800
 
 /* Display H1, Status Inputs, EPLD @0x80600000 */
-#define CFG_CS3_START		0x80600000
-#define CFG_CS3_SIZE		0x00100000
-#define CFG_CS3_CFG		0x00019800
+#define CONFIG_SYS_CS3_START		0x80600000
+#define CONFIG_SYS_CS3_SIZE		0x00100000
+#define CONFIG_SYS_CS3_CFG		0x00019800
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff Supports IDE harddisk
@@ -302,26 +303,26 @@
 #undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
 
 #define CONFIG_IDE_PREINIT	1
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(0x0060)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005C)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
 
 /* Interval between registers                                                */
-#define CFG_ATA_STRIDE          4
+#define CONFIG_SYS_ATA_STRIDE          4
 
 #define CONFIG_ATAPI            1
 
@@ -348,13 +349,13 @@
 #define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
 #define CONFIG_PCI_IO_SIZE	0x01000000
 
-#define CFG_ISA_IO		CONFIG_PCI_IO_BUS
+#define CONFIG_SYS_ISA_IO		CONFIG_PCI_IO_BUS
 
 /*---------------------------------------------------------------------*/
 /* Display addresses						       */
 /*---------------------------------------------------------------------*/
 
-#define CFG_DISP_CHR_RAM	(CFG_DISPLAY_BASE + 0x38)
-#define CFG_DISP_CWORD		(CFG_DISPLAY_BASE + 0x30)
+#define CONFIG_SYS_DISP_CHR_RAM	(CONFIG_SYS_DISPLAY_BASE + 0x38)
+#define CONFIG_SYS_DISP_CWORD		(CONFIG_SYS_DISPLAY_BASE + 0x30)
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/hymod.h b/include/configs/hymod.h
index 9c704c6..0fdcda2 100644
--- a/include/configs/hymod.h
+++ b/include/configs/hymod.h
@@ -87,10 +87,10 @@
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 # define MDIO_PORT		0		/* Port A */
 # define MDIO_DATA_PINMASK	0x00040000	/* Pin 13 */
@@ -104,10 +104,10 @@
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 # define MDIO_PORT		0		/* Port A */
 # define MDIO_DATA_PINMASK	0x00000040	/* Pin 25 */
@@ -121,10 +121,10 @@
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 # define MDIO_PORT		0		/* Port A */
 # define MDIO_DATA_PINMASK	0x00000100	/* Pin 23 */
@@ -252,54 +252,53 @@
 /*
  * Hymod specific configurable options
  */
-#undef	CFG_HYMOD_DBLEDS			/* walk mezz board LEDs */
+#undef	CONFIG_SYS_HYMOD_DBLEDS			/* walk mezz board LEDs */
 
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x03c00000	/* 4 ... 60 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x03c00000	/* 4 ... 60 MB in DRAM	*/
 
-#define CFG_CLKS_IN_HZ		1	/* everything, incl board info, in Hz */
+#define CONFIG_SYS_CLKS_IN_HZ		1	/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#define	CFG_I2C_SPEED		50000
-#define	CFG_I2C_SLAVE		0x7e
+#define	CONFIG_SYS_I2C_SPEED		50000
+#define	CONFIG_SYS_I2C_SLAVE		0x7e
 
 /* these are for the ST M24C02 2kbit serial i2c eeprom */
-#define CFG_I2C_EEPROM_ADDR	0x50		/* base address */
-#define CFG_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
 /* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
 
-#define CFG_EEPROM_PAGE_WRITE_ENABLE	1	/* write eeprom in pages */
-#define CFG_EEPROM_PAGE_WRITE_BITS	4	/* 16 byte write page size */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4	/* 16 byte write page size */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
-#define CFG_I2C_MULTI_EEPROMS	1		/* hymod has two eeproms */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS	1		/* hymod has two eeproms */
 
-#define CFG_I2C_RTC_ADDR	0x51	/* philips PCF8563 RTC address */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* philips PCF8563 RTC address */
 
 /*
  * standard dtt sensor configuration - bottom bit will determine local or
  * remote sensor of the ADM1021, the rest determines index into
- * CFG_DTT_ADM1021 array below.
+ * CONFIG_SYS_DTT_ADM1021 array below.
  *
  * On HYMOD board, the remote sensor should be connected to the MPC8260
  * temperature diode thingy, but an errata said this didn't work and
@@ -324,7 +323,7 @@
  * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
  * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above)
  */
-#define CFG_DTT_ADM1021		{ { 0x2a, 0x02, 0, 1, 0, 85, 0, } }
+#define CONFIG_SYS_DTT_ADM1021		{ { 0x2a, 0x02, 0, 1, 0, 85, 0, } }
 
 /*
  * Low Level Configuration Settings
@@ -335,86 +334,86 @@
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  *
- * if you change bits in the HRCW, you must also change the CFG_*
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
  * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
  */
 #ifdef DEBUG
-#define CFG_HRCW_MASTER	(HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
+#define CONFIG_SYS_HRCW_MASTER	(HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
 			 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
 			 HRCW_MODCK_H0010)
 #else
-#define CFG_HRCW_MASTER	(HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
+#define CONFIG_SYS_HRCW_MASTER	(HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
 			 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
 			 HRCW_MODCK_H0101)
 #endif
 /* no slaves so just duplicate the master hrcw */
-#define CFG_HRCW_SLAVE1	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE2	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE3	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE4	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE5	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE6	CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE7	CFG_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE1	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE2	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE3	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE4	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE5	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE6	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE7	CONFIG_SYS_HRCW_MASTER
 
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR		0xF0000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		TEXT_BASE
-#define	CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_FPGA_BASE		0x80000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		TEXT_BASE
+#define	CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_FPGA_BASE		0x80000000
 /*
- * unfortunately, CFG_MONITOR_LEN must include the
+ * unfortunately, CONFIG_SYS_MONITOR_LEN must include the
  * (very large i.e. 256kB) environment flash sector
  */
-#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor*/
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+#define	CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor*/
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	67	/* max num of sects on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max num of sects on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_SIZE		0x40000	/* Total Size of Environment Sector */
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* see README - env sect real size */
-#define	CONFIG_ENV_ADDR	(CFG_FLASH_BASE+CFG_MONITOR_LEN-CONFIG_ENV_SECT_SIZE)
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -427,14 +426,14 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 				HID0_IFEM|HID0_ABE)
 #ifdef DEBUG
-#define CFG_HID0_FINAL	0
+#define CONFIG_SYS_HID0_FINAL	0
 #else
-#define CFG_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
 #endif
-#define CFG_HID2	0
+#define CONFIG_SYS_HID2	0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register					 5-5
@@ -442,22 +441,22 @@
  * turn on Checkstop Reset Enable
  */
 #ifdef DEBUG
-#define CFG_RMR		0
+#define CONFIG_SYS_RMR		0
 #else
-#define CFG_RMR		RMR_CSRE
+#define CONFIG_SYS_RMR		RMR_CSRE
 #endif
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration					 4-25
  *-----------------------------------------------------------------------
  */
-#define CFG_BCR		(BCR_ETM)
+#define CONFIG_SYS_BCR		(BCR_ETM)
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration				 4-31
  *-----------------------------------------------------------------------
  */
-#define CFG_SIUMCR	(SIUMCR_DPPC10|SIUMCR_L2CPC01|\
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC10|SIUMCR_L2CPC01|\
 			 SIUMCR_APPC10|SIUMCR_MMR11)
 
 /*-----------------------------------------------------------------------
@@ -467,10 +466,10 @@
  * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
@@ -480,7 +479,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		 4-42
@@ -488,20 +487,20 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control					 9-8
  *-----------------------------------------------------------------------
  * Ensure DFBRG is Divide by 16
  */
-#define CFG_SCCR	(SCCR_DFBRG01)
+#define CONFIG_SYS_SCCR	(SCCR_DFBRG01)
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration				13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR	0
+#define CONFIG_SYS_RCCR	0
 
 /*
  * Init Memory Controller:
@@ -534,10 +533,10 @@
  */
 
 /* 32 bit, read-write, GPCM on 60x bus */
-#define	CFG_BR0_PRELIM	((CFG_FLASH_BASE&BRx_BA_MSK)|\
+#define	CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE&BRx_BA_MSK)|\
 				BRx_PS_32|BRx_MS_GPCM_P|BRx_V)
 /* up to 32 Mb */
-#define	CFG_OR0_PRELIM	(MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
+#define	CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
 
 /*
  * Bank 2 - SDRAM
@@ -557,13 +556,13 @@
  *  address lines to be configured to the required multiplexing scheme."
  */
 
-#define CFG_SDRAM_SIZE	64
+#define CONFIG_SYS_SDRAM_SIZE	64
 
 /* 64 bit, read-write, SDRAM on 60x bus */
-#define	CFG_BR2_PRELIM	((CFG_SDRAM_BASE&BRx_BA_MSK)|\
+#define	CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_SDRAM_BASE&BRx_BA_MSK)|\
 				BRx_PS_64|BRx_MS_SDRAM_P|BRx_V)
 /* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */
-#define	CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM_SIZE)|\
+#define	CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE)|\
 				ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12)
 
 /*
@@ -580,7 +579,7 @@
  * was written is 1 clock, CAS Latency is 2.
  */
 
-#define CFG_PSDMR	(PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\
+#define CONFIG_SYS_PSDMR	(PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\
 				PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\
 				PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\
 				PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\
@@ -612,11 +611,11 @@
  */
 
 #ifdef DEBUG
-#define CFG_PSRT	39
-#define CFG_MPTPR	MPTPR_PTP_DIV8
+#define CONFIG_SYS_PSRT	39
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV8
 #else
-#define CFG_PSRT	31
-#define CFG_MPTPR	MPTPR_PTP_DIV32
+#define CONFIG_SYS_PSRT	31
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV32
 #endif
 
 /*
@@ -652,7 +651,7 @@
  */
 
 /* all the bank sizes must be a power of two, greater or equal to 32768 */
-#define FPGA_MAIN_CFG_BASE	(CFG_FPGA_BASE)
+#define FPGA_MAIN_CFG_BASE	(CONFIG_SYS_FPGA_BASE)
 #define FPGA_MAIN_CFG_SIZE	32768
 #define FPGA_MAIN_REG_BASE	(FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
 #define FPGA_MAIN_REG_SIZE	32768
@@ -662,36 +661,36 @@
 #define FPGA_MEZZ_CFG_SIZE	32768
 
 /* 8 bit, read-write, UPMC */
-#define	CFG_BR3_PRELIM	(FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
+#define	CONFIG_SYS_BR3_PRELIM	(FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
 /* up to 32Kbyte, burst inhibit */
-#define	CFG_OR3_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
+#define	CONFIG_SYS_OR3_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
 
 /* 32 bit, read-write, GPCM */
-#define	CFG_BR4_PRELIM	(FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
+#define	CONFIG_SYS_BR4_PRELIM	(FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
 /* up to 32Kbyte */
-#define	CFG_OR4_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
+#define	CONFIG_SYS_OR4_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
 
 /* 32 bit, read-write, UPMB */
-#define	CFG_BR5_PRELIM	(FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
+#define	CONFIG_SYS_BR5_PRELIM	(FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
 /* up to 32Kbyte */
-#define	CFG_OR5_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
+#define	CONFIG_SYS_OR5_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
 
 /* 8 bit, write-only, UPMC */
-#define	CFG_BR6_PRELIM	(FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
+#define	CONFIG_SYS_BR6_PRELIM	(FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
 /* up to 32Kbyte, burst inhibit */
-#define	CFG_OR6_PRELIM	(P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
+#define	CONFIG_SYS_OR6_PRELIM	(P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
 
 /*-----------------------------------------------------------------------
  * MBMR - Machine B Mode					10-27
  *-----------------------------------------------------------------------
  */
-#define CFG_MBMR	(MxMR_BSEL|MxMR_OP_NORM)	/* XXX - needs more */
+#define CONFIG_SYS_MBMR	(MxMR_BSEL|MxMR_OP_NORM)	/* XXX - needs more */
 
 /*-----------------------------------------------------------------------
  * MCMR - Machine C Mode					10-27
  *-----------------------------------------------------------------------
  */
-#define CFG_MCMR	(MxMR_BSEL|MxMR_DSx_2_CYCL)	/* XXX - needs more */
+#define CONFIG_SYS_MCMR	(MxMR_BSEL|MxMR_DSx_2_CYCL)	/* XXX - needs more */
 
 /*
  * FPGA I/O Port/Bit information
diff --git a/include/configs/idmr.h b/include/configs/idmr.h
index a1f1517..1dd89f9 100644
--- a/include/configs/idmr.h
+++ b/include/configs/idmr.h
@@ -45,9 +45,9 @@
 #define CONFIG_BOOTCOMMAND	"run net_nfs"
 #define CONFIG_BOOTDELAY	5
 #define CONFIG_MCFUART
-#define CFG_UART_PORT		(0)
+#define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		19200
-#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
 #define CONFIG_ETHADDR		00:06:3b:01:41:55
 #define CONFIG_ETHPRIME
 #define CONFIG_IPADDR		192.168.30.1
@@ -125,30 +125,30 @@
 #define CONFIG_ENV_IS_IN_FLASH
 #endif /* !CONFIG_MONITOR_IS_IN_RAM */
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
-#define CFG_PROMPT		"=> "
-#define CFG_LONGHELP				/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_LONGHELP				/* undef to save memory */
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
-#define CFG_LOAD_ADDR		0x00100000
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
 
-#define CFG_MEMTEST_START	0x400
-#define CFG_MEMTEST_END		0x380000
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
 
-#define CFG_HZ			(50000000 / 64)
-#define CFG_CLK			100000000
+#define CONFIG_SYS_HZ			(50000000 / 64)
+#define CONFIG_SYS_CLK			100000000
 
-#define CFG_MBAR		0x40000000	/* Register Base Addrs */
+#define CONFIG_SYS_MBAR		0x40000000	/* Register Base Addrs */
 
 /*
  * Ethernet
@@ -158,74 +158,74 @@
 #	define CONFIG_NET_MULTI		1
 #	define CONFIG_MII		1
 #	define CONFIG_MII_INIT		1
-#	define CFG_DISCOVER_PHY
-#	define CFG_RX_ETH_BUFFER	8
-#	define CFG_FAULT_ECHO_LINK_DOWN
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 
-#	define CFG_FEC0_PINMUX		0
-#	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
 #	define MCFFEC_TOUT_LOOP		50000
-/* If CFG_DISCOVER_PHY is not defined - hardcoded */
-#	ifndef CFG_DISCOVER_PHY
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
 #		define FECDUPLEX	FULL
 #		define FECSPEED		_100BASET
 #	else
-#		ifndef CFG_FAULT_ECHO_LINK_DOWN
-#			define CFG_FAULT_ECHO_LINK_DOWN
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #		endif
-#	endif			/* CFG_DISCOVER_PHY */
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
 #endif
 
 /*
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x20000000
-#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM */
-#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_SIZE		16		/* SDRAM size in MB */
-#define CFG_FLASH_BASE		0xff800000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
+#define CONFIG_SYS_FLASH_BASE		0xff800000
 
 #ifdef CONFIG_MONITOR_IS_IN_RAM
-#define CFG_MONITOR_BASE	0x20000
+#define CONFIG_SYS_MONITOR_BASE	0x20000
 #else /* !CONFIG_MONITOR_IS_IN_RAM */
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
 #endif /* CONFIG_MONITOR_IS_IN_RAM */
 
-#define CFG_MONITOR_LEN		0x20000
-#define CFG_MALLOC_LEN		(256 << 10)
-#define CFG_BOOTPARAMS_LEN	(64*1024)
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 
 /* FLASH organization */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT	1000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
 
-#define CFG_FLASH_SIZE		0x800000
+#define CONFIG_SYS_FLASH_SIZE		0x800000
 /*
- * #define CFG_FLASH_USE_BUFFER_WRITE	1
+ * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
  */
 
 /* Cache Configuration */
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /* Port configuration */
-#define CFG_FECI2C		0xF0
+#define CONFIG_SYS_FECI2C		0xF0
 
 
 /* Dynamic MTD partition support */
diff --git a/include/configs/impa7.h b/include/configs/impa7.h
index 52eb888..bb3c02e 100644
--- a/include/configs/impa7.h
+++ b/include/configs/impa7.h
@@ -41,8 +41,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -96,24 +96,24 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"impA7 # "		/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"impA7 # "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0xc0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0xc1000000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0xc1000000	/* default load address	*/
 
-#define	CFG_HZ			2000		/* decrementer freq: 2 kHz */
+#define	CONFIG_SYS_HZ			2000		/* decrementer freq: 2 kHz */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -139,17 +139,17 @@
 #define PHYS_FLASH_2		0x10000000 /* Flash Bank #2 */
 #define PHYS_FLASH_SIZE		0x00800000 /* 16 MB */
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x1C000)	/* Addr of Environment Sector	*/
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 60916b9..6c150ae 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -53,15 +53,15 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
-#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
  */
 
 #define CONFIG_MX31_UART	1
-#define CFG_MX31_UART1		1
+#define CONFIG_SYS_MX31_UART1		1
 
 #define CONFIG_HARD_SPI		1
 #define CONFIG_MXC_SPI		1
@@ -77,7 +77,7 @@
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
 
 /***********************************************************
  * Command definition
@@ -111,22 +111,20 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory */
-#define CFG_PROMPT		"uboot> "
-#define CFG_CBSIZE		256  /* Console I/O Buffer Size */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"uboot> "
+#define CONFIG_SYS_CBSIZE		256  /* Console I/O Buffer Size */
 /* Print Buffer Size */
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS		16          /* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16          /* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
 
-#define CFG_MEMTEST_START	0  /* memtest works on */
-#define CFG_MEMTEST_END		0x10000
+#define CONFIG_SYS_MEMTEST_START	0  /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x10000
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#define CONFIG_SYS_LOAD_ADDR		0 /* default load address */
 
-#define CFG_LOAD_ADDR		0 /* default load address */
-
-#define CFG_HZ			32000
+#define CONFIG_SYS_HZ			1000
 
 #define CONFIG_CMDLINE_EDITING	1
 
@@ -147,12 +145,12 @@
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_FLASH_BASE		CS0_BASE
-#define CFG_MAX_FLASH_BANKS	1           /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	128	     /* max number of sectors on one chip */
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE /* Monitor at beginning of flash */
+#define CONFIG_SYS_FLASH_BASE		CS0_BASE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1           /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	     /* max number of sectors on one chip */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
 
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x001f0000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x001f0000)
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SECT_SIZE	(64 * 1024)
 #define CONFIG_ENV_SIZE		(64 * 1024)
@@ -160,14 +158,14 @@
 /*-----------------------------------------------------------------------
  * CFI FLASH driver setup
  */
-#define CFG_FLASH_CFI		1	/* Flash memory is CFI compliant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash memory is CFI compliant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
-#define CFG_FLASH_PROTECTION	1	/* Use hardware sector protection */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use hardware sector protection */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(100*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(100*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 /*
  * JFFS2 partitions
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index bf2a8dd..f0d28ee 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -51,8 +51,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
-#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -60,18 +60,18 @@
 
 #define CONFIG_HARD_I2C		1
 #define CONFIG_I2C_MXC		1
-#define CFG_I2C_MX31_PORT2	1
-#define CFG_I2C_SPEED		100000
-#define CFG_I2C_SLAVE		0xfe
+#define CONFIG_SYS_I2C_MX31_PORT2	1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		0xfe
 
 #define CONFIG_MX31_UART	1
-#define CFG_MX31_UART1		1
+#define CONFIG_SYS_MX31_UART1		1
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
 
 /***********************************************************
  * Command definition
@@ -113,20 +113,20 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory */
-#define CFG_PROMPT		"uboot> "
-#define CFG_CBSIZE		256  /* Console I/O Buffer Size */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"uboot> "
+#define CONFIG_SYS_CBSIZE		256  /* Console I/O Buffer Size */
 /* Print Buffer Size */
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS		16          /* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16          /* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
 
-#define CFG_MEMTEST_START	0  /* memtest works on */
-#define CFG_MEMTEST_END		0x10000
+#define CONFIG_SYS_MEMTEST_START	0  /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x10000
 
-#define CFG_LOAD_ADDR		0 /* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0 /* default load address */
 
-#define CFG_HZ			32000
+#define CONFIG_SYS_HZ			1000
 
 #define CONFIG_CMDLINE_EDITING	1
 
@@ -147,30 +147,30 @@
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_FLASH_BASE		0xa0000000
-#define CFG_MAX_FLASH_BANKS	1           /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	259	     /* max number of sectors on one chip */
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE /* Monitor at beginning of flash */
+#define CONFIG_SYS_FLASH_BASE		0xa0000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1           /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	259	     /* max number of sectors on one chip */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
 
 #define	CONFIG_ENV_IS_IN_EEPROM		1
 #define CONFIG_ENV_OFFSET			0x00	/* environment starts here     */
 #define CONFIG_ENV_SIZE			4096
-#define CFG_I2C_EEPROM_ADDR		0x52
-#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets          */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* between stop and start      */
-#define CFG_I2C_EEPROM_ADDR_LEN		2	/* length of byte address      */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x52
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets          */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* between stop and start      */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* length of byte address      */
 
 /*-----------------------------------------------------------------------
  * CFI FLASH driver setup
  */
-#define CFG_FLASH_CFI		1	/* Flash memory is CFI compliant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash memory is CFI compliant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
-#define CFG_FLASH_PROTECTION	1	/* Use hardware sector protection */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use hardware sector protection */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(100*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(100*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 /*
  * JFFS2 partitions
diff --git a/include/configs/incaip.h b/include/configs/incaip.h
index 5368ac8..a18ba80 100644
--- a/include/configs/incaip.h
+++ b/include/configs/incaip.h
@@ -43,7 +43,7 @@
 #define CONFIG_BAUDRATE		115200
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
 
@@ -108,47 +108,47 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory      */
-#define	CFG_PROMPT		"INCA-IP # "	/* Monitor Command Prompt    */
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory      */
+#define	CONFIG_SYS_PROMPT		"INCA-IP # "	/* Monitor Command Prompt    */
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size   */
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args*/
 
-#define CFG_MALLOC_LEN		128*1024
+#define CONFIG_SYS_MALLOC_LEN		128*1024
 
-#define CFG_BOOTPARAMS_LEN	128*1024
+#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024
 
-#define CFG_MIPS_TIMER_FREQ	(incaip_get_cpuclk() / 2)
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(incaip_get_cpuclk() / 2)
 
-#define CFG_HZ			1000
+#define CONFIG_SYS_HZ			1000
 
-#define CFG_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
 
-#define	CFG_LOAD_ADDR		0x80100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x80100000	/* default load address	*/
 
-#define CFG_MEMTEST_START	0x80100000
-#define CFG_MEMTEST_END		0x80800000
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x80800000
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
 
 #define PHYS_FLASH_1		0xb0000000 /* Flash Bank #1 */
 #define PHYS_FLASH_2		0xb0800000 /* Flash Bank #2 */
 
 /* The following #defines are needed to get flash environment right */
-#define	CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MONITOR_LEN		(192 << 10)
+#define	CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)
 
-#define CFG_INIT_SP_OFFSET	0x400000
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 
@@ -188,8 +188,8 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		4096
-#define CFG_ICACHE_SIZE		4096
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_DCACHE_SIZE		4096
+#define CONFIG_SYS_ICACHE_SIZE		4096
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index 32d4871..e42fa6d 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -33,7 +33,7 @@
 #define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
 #define CONFIG_INKA4X0		1	/* INKA4x0 board			*/
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM		0x02	/* Software reboot			*/
@@ -47,7 +47,7 @@
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*
  * PCI Mapping:
@@ -67,7 +67,7 @@
 #define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
 #define CONFIG_PCI_IO_SIZE	0x01000000
 
-#define CFG_XLB_PIPELINING	1
+#define CONFIG_SYS_XLB_PIPELINING	1
 
 /* Partitions */
 #define CONFIG_MAC_PARTITION
@@ -102,7 +102,7 @@
 #define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
 
 #if (TEXT_BASE == 0xFFE00000)		/* Boot low */
-#   define CFG_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT		1
 #endif
 
 /*
@@ -154,36 +154,36 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * Flash configuration
  */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1
-#define CFG_FLASH_BASE		0xffe00000
-#define CFG_FLASH_SIZE		0x00200000
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
+#define CONFIG_SYS_FLASH_BASE		0xffe00000
+#define CONFIG_SYS_FLASH_SIZE		0x00200000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
 
 /*
  * Environment settings
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x4000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x2000
 #define CONFIG_ENV_OVERWRITE	1
-#define CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /*
  * SDRAM controller configuration
@@ -195,36 +195,37 @@
 #define CONFIG_DDR_K4H511638C
 
 /* Use ON-Chip SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
 #else
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
 #endif
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
 /*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
  */
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
 #define CONFIG_PHY_ADDR		0x00
 #define CONFIG_MII
 
@@ -241,7 +242,7 @@
  * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000):
  *	011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
  */
-#define CFG_GPS_PORT_CONFIG	0x01001004
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x01001004
 
 /*
  * RTC configuration
@@ -251,31 +252,31 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /* Enable an alternate, more extensive memory test */
-#define CFG_ALT_MEMTEST
+#define CONFIG_SYS_ALT_MEMTEST
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 /*
  * Enable loopw command.
@@ -286,36 +287,36 @@
  * Various low-level settings
  */
 #if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 #else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
 #endif
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x00087800 /* for pci_clk  = 66 MHz */
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00087800 /* for pci_clk  = 66 MHz */
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
 /* 32Mbit SRAM @0x30000000 */
-#define CFG_CS1_START		0x30000000
-#define CFG_CS1_SIZE		0x00400000
-#define CFG_CS1_CFG		0x31800 /* for pci_clk = 33 MHz */
+#define CONFIG_SYS_CS1_START		0x30000000
+#define CONFIG_SYS_CS1_SIZE		0x00400000
+#define CONFIG_SYS_CS1_CFG		0x31800 /* for pci_clk = 33 MHz */
 
 /* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
-#define CFG_CS2_START		0x80000000
-#define CFG_CS2_SIZE		0x0001000
-#define CFG_CS2_CFG		0x21800  /* for pci_clk = 33 MHz */
+#define CONFIG_SYS_CS2_START		0x80000000
+#define CONFIG_SYS_CS2_SIZE		0x0001000
+#define CONFIG_SYS_CS2_CFG		0x21800  /* for pci_clk = 33 MHz */
 
 /* GPIO in @0x30400000 */
-#define CFG_CS3_START		0x30400000
-#define CFG_CS3_SIZE		0x00100000
-#define CFG_CS3_CFG		0x31800 /* for pci_clk = 33 MHz */
+#define CONFIG_SYS_CS3_START		0x30400000
+#define CONFIG_SYS_CS3_SIZE		0x00100000
+#define CONFIG_SYS_CS3_CFG		0x31800 /* for pci_clk = 33 MHz */
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
 
 /*-----------------------------------------------------------------------
  * USB stuff
@@ -339,18 +340,18 @@
 #define	CONFIG_IDE_RESET		/* reset for ide supported	*/
 #define CONFIG_IDE_PREINIT
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
-#define CFG_ATA_DATA_OFFSET	0x0060	/* Offset for data I/O		*/
-#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* Offset for normal register accesses */
-#define CFG_ATA_ALT_OFFSET	0x005C	/* Offset for alternate registers */
-#define CFG_ATA_STRIDE          4	/* Interval between registers	*/
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0060	/* Offset for data I/O		*/
+#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x005C	/* Offset for alternate registers */
+#define CONFIG_SYS_ATA_STRIDE          4	/* Interval between registers	*/
 
 #define CONFIG_ATAPI            1
 
-#define CFG_BRIGHTNESS          0xFF	/* LCD Default Brightness (255 = off) */
+#define CONFIG_SYS_BRIGHTNESS          0xFF	/* LCD Default Brightness (255 = off) */
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/innokom.h b/include/configs/innokom.h
index f9535c9..d9b1555 100644
--- a/include/configs/innokom.h
+++ b/include/configs/innokom.h
@@ -73,7 +73,7 @@
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ECHO
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IMI
@@ -102,54 +102,54 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(256*1024)
-#define CFG_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(256*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
 
-#define CFG_LONGHELP				/* undef to save memory         */
-#define CFG_PROMPT		"uboot> "	/* Monitor Command Prompt       */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size      */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory         */
+#define CONFIG_SYS_PROMPT		"uboot> "	/* Monitor Command Prompt       */
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size      */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START	0xa0400000      /* memtest works on     */
-#define CFG_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
+#define CONFIG_SYS_MEMTEST_START	0xa0400000      /* memtest works on     */
+#define CONFIG_SYS_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
 
-#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR           0xa3000000      /* load kernel to this address   */
+#define CONFIG_SYS_LOAD_ADDR           0xa3000000      /* load kernel to this address   */
 
-#define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ			1000
 						/* RS: the oscillator is actually 3680130?? */
 
-#define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
+#define CONFIG_SYS_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
 						/* 0101000001 */
 						/*      ^^^^^ Memory Speed 99.53 MHz         */
 						/*    ^^      Run Mode Speed = 2x Mem Speed  */
 						/* ^^         Turbo Mode Sp. = 1x Run M. Sp. */
 
-#define CFG_MONITOR_LEN		0x20000		/* 128 KiB */
+#define CONFIG_SYS_MONITOR_LEN		0x20000		/* 128 KiB */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * I2C bus
  */
 #define CONFIG_HARD_I2C			1
-#define CFG_I2C_SPEED			50000
-#define CFG_I2C_SLAVE			0xfe
+#define CONFIG_SYS_I2C_SPEED			50000
+#define CONFIG_SYS_I2C_SLAVE			0xfe
 
 #define CONFIG_ENV_IS_IN_EEPROM		1
 
 #define CONFIG_ENV_OFFSET			0x00	/* environment starts here  */
 #define CONFIG_ENV_SIZE			1024	/* 1 KiB                    */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* A0 = 0 (hardwired)       */
-#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets       */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	15	/* between stop and start   */
-#define CFG_I2C_EEPROM_ADDR_LEN		2	/* length of address        */
-#define CFG_EEPROM_SIZE			4096	/* size in bytes            */
-#define CFG_I2C_INIT_BOARD		1	/* board has it's own init  */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* A0 = 0 (hardwired)       */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets       */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	15	/* between stop and start   */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* length of address        */
+#define CONFIG_SYS_EEPROM_SIZE			4096	/* size in bytes            */
+#define CONFIG_SYS_I2C_INIT_BOARD		1	/* board has it's own init  */
 
 /*
  * SMSC91C111 Network Card
@@ -183,10 +183,10 @@
 #define PHYS_FLASH_1		0x00000000	/* Flash Bank #1            */
 #define PHYS_FLASH_SIZE		0x01000000	/* 16 MB                    */
 
-#define CFG_DRAM_BASE		0xa0000000	/* RAM starts here          */
-#define CFG_DRAM_SIZE		0x04000000
+#define CONFIG_SYS_DRAM_BASE		0xa0000000	/* RAM starts here          */
+#define CONFIG_SYS_DRAM_SIZE		0x04000000
 
-#define CFG_FLASH_BASE          PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
 /*
  * JFFS2 partitions
@@ -242,9 +242,9 @@
  * GP79 == nCS3      is 1
  * GP80 == nCS4      is 1
  */
-#define CFG_GPSR0_VAL       0x03008000
-#define CFG_GPSR1_VAL       0xC0028282
-#define CFG_GPSR2_VAL       0x0001C000
+#define CONFIG_SYS_GPSR0_VAL       0x03008000
+#define CONFIG_SYS_GPSR1_VAL       0xC0028282
+#define CONFIG_SYS_GPSR2_VAL       0x0001C000
 
 /* GP02 == DON_RST   is 0
  * GP23 == SCLK      is 0
@@ -253,9 +253,9 @@
  * GP61 == LED_A     is 0
  * GP73 == SWUPD_LED is 0
  */
-#define CFG_GPCR0_VAL       0x00800004
-#define CFG_GPCR1_VAL       0x30002000
-#define CFG_GPCR2_VAL       0x00000100
+#define CONFIG_SYS_GPCR0_VAL       0x00800004
+#define CONFIG_SYS_GPCR1_VAL       0x30002000
+#define CONFIG_SYS_GPCR2_VAL       0x00000100
 
 /* GP00 == DON_READY is input
  * GP01 == DON_OK    is input
@@ -300,9 +300,9 @@
  * GP79 == nCS3      is output
  * GP80 == nCS4      is output
  */
-#define CFG_GPDR0_VAL       0x03808004
-#define CFG_GPDR1_VAL       0xF002A282
-#define CFG_GPDR2_VAL       0x0001C200
+#define CONFIG_SYS_GPDR0_VAL       0x03808004
+#define CONFIG_SYS_GPDR1_VAL       0xF002A282
+#define CONFIG_SYS_GPDR2_VAL       0x0001C200
 
 /* GP15 == nCS1  is AF10
  * GP18 == RDY   is AF01
@@ -322,12 +322,12 @@
  * GP79 == nCS3  is AF10
  * GP80 == nCS4  is AF10
  */
-#define CFG_GAFR0_L_VAL     0x80000000
-#define CFG_GAFR0_U_VAL     0x001A8010
-#define CFG_GAFR1_L_VAL     0x60088058
-#define CFG_GAFR1_U_VAL     0x00000008
-#define CFG_GAFR2_L_VAL     0xA0000000
-#define CFG_GAFR2_U_VAL     0x00000002
+#define CONFIG_SYS_GAFR0_L_VAL     0x80000000
+#define CONFIG_SYS_GAFR0_U_VAL     0x001A8010
+#define CONFIG_SYS_GAFR1_L_VAL     0x60088058
+#define CONFIG_SYS_GAFR1_U_VAL     0x00000008
+#define CONFIG_SYS_GAFR2_L_VAL     0xA0000000
+#define CONFIG_SYS_GAFR2_U_VAL     0x00000002
 
 
 /* FIXME: set GPIO_RER/FER */
@@ -338,7 +338,7 @@
  * BFS = 1
  * SSS = 1
  */
-#define CFG_PSSR_VAL		0x37
+#define CONFIG_SYS_PSSR_VAL		0x37
 
 /*
  * Memory settings
@@ -359,7 +359,7 @@
  * [03]    1    - 16 Bit bus width
  * [02:00] 000  - nonburst RAM or FLASH
  */
-#define CFG_MSC0_VAL		0x25b825b8 /* flash banks                   */
+#define CONFIG_SYS_MSC0_VAL		0x25b825b8 /* flash banks                   */
 
 /* This is the configuration for nCS2/3 -> TDM-Switch, DSP
  * configuration for nCS3: DSP
@@ -377,7 +377,7 @@
  * [03]    1    - 16 Bit bus width
  * [02:00] 100  - variable latency I/O
  */
-#define CFG_MSC1_VAL		0x123C593C /* TDM switch, DSP               */
+#define CONFIG_SYS_MSC1_VAL		0x123C593C /* TDM switch, DSP               */
 
 /* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
  *
@@ -396,7 +396,7 @@
  * [03]    1    - 16 Bit bus width
  * [02:00] 100  - variable latency I/O
  */
-#define CFG_MSC2_VAL		0x123C6CDC /* extra bus, LAN controller     */
+#define CONFIG_SYS_MSC2_VAL		0x123C6CDC /* extra bus, LAN controller     */
 
 /* MDCNFG: SDRAM Configuration Register
  *
@@ -424,7 +424,7 @@
  * [00]      1   - enable  SDRAM partition 0
  */
 /* use the configuration above but disable partition 0 */
-#define CFG_MDCNFG_VAL		0x000019c8
+#define CONFIG_SYS_MDCNFG_VAL		0x000019c8
 
 /* MDREFR: SDRAM Refresh Control Register
  *
@@ -445,7 +445,7 @@
  * [12]    1     - E0PIN: disable SDCKE0
  * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
  */
-#define CFG_MDREFR_VAL		0x0081D018
+#define CONFIG_SYS_MDREFR_VAL		0x0081D018
 
 /* MDMRS: Mode Register Set Configuration Register
  *
@@ -460,18 +460,18 @@
  * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
  * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
  */
-#define CFG_MDMRS_VAL		0x00020022
+#define CONFIG_SYS_MDMRS_VAL		0x00020022
 
 /*
  * PCMCIA and CF Interfaces
  */
-#define CFG_MECR_VAL		0x00000000
-#define CFG_MCMEM0_VAL		0x00000000
-#define CFG_MCMEM1_VAL		0x00000000
-#define CFG_MCATT0_VAL		0x00000000
-#define CFG_MCATT1_VAL		0x00000000
-#define CFG_MCIO0_VAL		0x00000000
-#define CFG_MCIO1_VAL		0x00000000
+#define CONFIG_SYS_MECR_VAL		0x00000000
+#define CONFIG_SYS_MCMEM0_VAL		0x00000000
+#define CONFIG_SYS_MCMEM1_VAL		0x00000000
+#define CONFIG_SYS_MCATT0_VAL		0x00000000
+#define CONFIG_SYS_MCATT1_VAL		0x00000000
+#define CONFIG_SYS_MCIO0_VAL		0x00000000
+#define CONFIG_SYS_MCIO1_VAL		0x00000000
 
 /*
 #define CSB226_USER_LED0	0x00000008
@@ -482,11 +482,11 @@
 /*
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS     1	/* max number of memory banks       */
-#define CFG_MAX_FLASH_SECT	128	/* max number of sect. on one chip  */
+#define CONFIG_SYS_MAX_FLASH_BANKS     1	/* max number of memory banks       */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sect. on one chip  */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase       */
-#define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write       */
+#define CONFIG_SYS_FLASH_ERASE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase       */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Write       */
 
 #endif  /* __CONFIG_H */
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
index f951a01..6ce3b4d 100644
--- a/include/configs/integratorap.h
+++ b/include/configs/integratorap.h
@@ -34,11 +34,11 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CFG_MEMTEST_START	0x100000
-#define CFG_MEMTEST_END		0x10000000
-#define CFG_HZ			1000
-#define CFG_HZ_CLOCK		24000000	/* Timer 1 is clocked at 24Mhz */
-#define CFG_TIMERBASE		0x13000100	/* Timer1		       */
+#define CONFIG_SYS_MEMTEST_START	0x100000
+#define CONFIG_SYS_MEMTEST_END		0x10000000
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_HZ_CLOCK		24000000	/* Timer 1 is clocked at 24Mhz */
+#define CONFIG_SYS_TIMERBASE		0x13000100	/* Timer1		       */
 
 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
 #define CONFIG_SETUP_MEMORY_TAGS	1
@@ -52,8 +52,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * PL010 Configuration
@@ -61,10 +61,10 @@
 #define CONFIG_PL010_SERIAL
 #define CONFIG_CONS_INDEX	0
 #define CONFIG_BAUDRATE		38400
-#define CONFIG_PL01x_PORTS	{ (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1) }
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_SERIAL0		0x16000000
-#define CFG_SERIAL1		0x17000000
+#define CONFIG_PL01x_PORTS	{ (void *) (CONFIG_SYS_SERIAL0), (void *) (CONFIG_SYS_SERIAL1) }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_SERIAL0		0x16000000
+#define CONFIG_SYS_SERIAL1		0x17000000
 
 /*#define CONFIG_NET_MULTI */
 
@@ -94,16 +94,16 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP	/* undef to save memory	    */
-#define CFG_PROMPT	"Integrator-AP # "	/* Monitor Command Prompt   */
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_LONGHELP	/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT	"Integrator-AP # "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size  */
 /* Print Buffer Size */
-#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-#define CFG_LOAD_ADDR	0x7fc0	/* default load address */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#define CONFIG_SYS_LOAD_ADDR	0x7fc0	/* default load address */
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -123,21 +123,21 @@
 #define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
 
-#define CFG_FLASH_BASE		0x24000000
+#define CONFIG_SYS_FLASH_BASE		0x24000000
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
 #define CONFIG_ENV_IS_NOWHERE
-#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of memory banks */
 #define PHYS_FLASH_SIZE		0x01000000	/* 16MB */
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Write */
-#define CFG_MAX_FLASH_SECT	128
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Write */
+#define CONFIG_SYS_MAX_FLASH_SECT	128
 #define CONFIG_ENV_SIZE		32768
 
-#define PHYS_FLASH_1		(CFG_FLASH_BASE)
+#define PHYS_FLASH_1		(CONFIG_SYS_FLASH_BASE)
 
 /*-----------------------------------------------------------------------
  * PCI definitions
@@ -149,7 +149,7 @@
 #define DEBUG
 
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
+#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
 
 
 #define INTEGRATOR_BOOT_ROM_BASE	0x20000000
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
index 6dbe4b3..5b4747a 100644
--- a/include/configs/integratorcp.h
+++ b/include/configs/integratorcp.h
@@ -35,11 +35,11 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CFG_MEMTEST_START	0x100000
-#define CFG_MEMTEST_END		0x10000000
-#define CFG_HZ			1000
-#define CFG_HZ_CLOCK		1000000	/* Timer 1 is clocked at 1Mhz */
-#define CFG_TIMERBASE		0x13000100
+#define CONFIG_SYS_MEMTEST_START	0x100000
+#define CONFIG_SYS_MEMTEST_END		0x10000000
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer 1 is clocked at 1Mhz */
+#define CONFIG_SYS_TIMERBASE		0x13000100
 
 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs  */
 #define CONFIG_SETUP_MEMORY_TAGS	1
@@ -47,8 +47,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -63,12 +63,12 @@
  */
 #define CONFIG_PL011_SERIAL
 #define CONFIG_PL011_CLOCK	14745600
-#define CONFIG_PL01x_PORTS	{ (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
+#define CONFIG_PL01x_PORTS	{ (void *)CONFIG_SYS_SERIAL0, (void *)CONFIG_SYS_SERIAL1 }
 #define CONFIG_CONS_INDEX	0
 #define CONFIG_BAUDRATE		38400
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_SERIAL0		0x16000000
-#define CFG_SERIAL1		0x17000000
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_SERIAL0		0x16000000
+#define CONFIG_SYS_SERIAL1		0x17000000
 
 
 /*
@@ -85,7 +85,7 @@
  */
 #define CONFIG_CMD_BDI
 #define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_IMI
 #define CONFIG_CMD_MEMORY
@@ -113,16 +113,16 @@ SIB at Block62 End Block62 address 0x24f80000
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory */
-#define CFG_PROMPT	"Integrator-CP # "	/* Monitor Command Prompt */
-#define CFG_CBSIZE	256			/* Console I/O Buffer Size*/
+#define CONFIG_SYS_LONGHELP				/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"Integrator-CP # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256			/* Console I/O Buffer Size*/
 /* Print Buffer Size */
-#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS	16			/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE		/* Boot Argument Buffer Size*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16			/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE		/* Boot Argument Buffer Size*/
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-#define CFG_LOAD_ADDR	0x7fc0	/* default load address */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#define CONFIG_SYS_LOAD_ADDR	0x7fc0	/* default load address */
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -155,38 +155,38 @@ SIB at Block62 End Block62 address 0x24f80000
  * Base is always 0x24000000
 
  */
-#define CFG_FLASH_BASE		0x24000000
-#define CFG_MAX_FLASH_SECT	64
-#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define CONFIG_SYS_FLASH_BASE		0x24000000
+#define CONFIG_SYS_MAX_FLASH_SECT	64
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of memory banks */
 #define PHYS_FLASH_SIZE		0x01000000	/* 16MB */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Write */
 
-#define CFG_MONITOR_LEN		0x00100000
+#define CONFIG_SYS_MONITOR_LEN		0x00100000
 #define CONFIG_ENV_IS_IN_FLASH	1
 
 /*
  * Move up the U-Boot & monitor area if more flash is fitted.
  * If this U-Boot is to be run on Integrators with varying flash sizes,
  * drivers/mtd/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG
- * register and dynamically assign CONFIG_ENV_ADDR & CFG_MONITOR_BASE
- * - CFG_MONITOR_BASE is set to indicate that the environment is not
+ * register and dynamically assign CONFIG_ENV_ADDR & CONFIG_SYS_MONITOR_BASE
+ * - CONFIG_SYS_MONITOR_BASE is set to indicate that the environment is not
  * embedded in the boot monitor(s) area
  */
 #if ( PHYS_FLASH_SIZE == 0x04000000 )
 
 #define CONFIG_ENV_ADDR		0x27F00000
-#define CFG_MONITOR_BASE	0x27F40000
+#define CONFIG_SYS_MONITOR_BASE	0x27F40000
 
 #elif (PHYS_FLASH_SIZE == 0x02000000 )
 
 #define CONFIG_ENV_ADDR		0x25F00000
-#define CFG_MONITOR_BASE	0x25F40000
+#define CONFIG_SYS_MONITOR_BASE	0x25F40000
 
 #else
 
 #define CONFIG_ENV_ADDR		0x24F00000
-#define CFG_MONITOR_BASE	0x27F40000
+#define CONFIG_SYS_MONITOR_BASE	0x27F40000
 
 #endif
 
diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h
index b933475..70f3987 100644
--- a/include/configs/ixdp425.h
+++ b/include/configs/ixdp425.h
@@ -45,8 +45,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN      (CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN      (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -73,6 +73,7 @@
 
 
 #define CONFIG_PCI
+#define CONFIG_IXP_PCI
 #define CONFIG_NET_MULTI
 #define CONFIG_EEPRO100
 
@@ -93,23 +94,23 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP                            /* undef to save memory         */
-#define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
-#define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS             16              /* max number of command args   */
-#define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LONGHELP                            /* undef to save memory         */
+#define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt       */
+#define CONFIG_SYS_CBSIZE              256             /* Console I/O Buffer Size      */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS             16              /* max number of command args   */
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE      /* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START       0x00400000      /* memtest works on     */
-#define CFG_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
+#define CONFIG_SYS_MEMTEST_START       0x00400000      /* memtest works on     */
+#define CONFIG_SYS_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
 
-#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR           0x00010000      /* default load address */
+#define CONFIG_SYS_LOAD_ADDR           0x00010000      /* default load address */
 
-#define CFG_HZ                  3333333         /* spec says 66.666 MHz, but it appears to be 33 */
+#define CONFIG_SYS_HZ                  3333333         /* spec says 66.666 MHz, but it appears to be 33 */
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Stack sizes
@@ -134,7 +135,8 @@
 /*
  * select serial console configuration
  */
-#define CFG_IXP425_CONSOLE	IXP425_UART1   /* we use UART1 for console */
+#define CONFIG_IXP_SERIAL
+#define CONFIG_SYS_IXP425_CONSOLE	IXP425_UART1   /* we use UART1 for console */
 
 /*
  * Physical Memory Map
@@ -148,24 +150,24 @@
 #define PHYS_FLASH_BANK_SIZE    0x00800000 /* 8 MB Banks */
 #define PHYS_FLASH_SECT_SIZE    0x00020000 /* 128 KB sectors (x1) */
 
-#define CFG_DRAM_BASE           0x00000000
-#define CFG_DRAM_SIZE           0x01000000
+#define CONFIG_SYS_DRAM_BASE           0x00000000
+#define CONFIG_SYS_DRAM_SIZE           0x01000000
 
-#define CFG_FLASH_BASE          PHYS_FLASH_1
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 
 /*
  * Expansion bus settings
  */
-#define CFG_EXP_CS0				0xbcd23c42
+#define CONFIG_SYS_EXP_CS0				0xbcd23c42
 
 /*
  * SDRAM settings
  */
-#define CFG_SDR_CONFIG		0xd
-#define CFG_SDR_MODE_CONFIG	0x1
-#define CFG_SDRAM_REFRESH_CNT	0x81a
+#define CONFIG_SYS_SDR_CONFIG		0xd
+#define CONFIG_SYS_SDR_MODE_CONFIG	0x1
+#define CONFIG_SYS_SDRAM_REFRESH_CNT	0x81a
 
 /*
  * GPIO settings
@@ -177,21 +179,21 @@
 /*
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
-#define CFG_MAX_FLASH_SECT      128	/* max number of sectors on one chip    */
+#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* max number of memory banks           */
+#define CONFIG_SYS_MAX_FLASH_SECT      128	/* max number of sectors on one chip    */
 
-#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
 #define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
 #define	CONFIG_ENV_IS_IN_FLASH	1
 
-#define CFG_FLASH_BANKS_LIST	{ PHYS_FLASH_1 }
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1 }
 
-#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	*/
 #define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x20000)
diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h
index 241728d..193008e 100644
--- a/include/configs/ixdpg425.h
+++ b/include/configs/ixdpg425.h
@@ -48,7 +48,7 @@
 #define CONFIG_HAS_ETH1
 #define CONFIG_PHY1_ADDR	4	/* NPE1 PHY address		*/
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define CFG_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
 
 /*
  * Misc configuration options
@@ -57,7 +57,7 @@
 #define CONFIG_USE_IRQ          1	/* we need IRQ stuff for timer	*/
 
 #define CONFIG_BOOTCOUNT_LIMIT		/* support for bootcount limit	*/
-#define CFG_BOOTCOUNT_ADDR	0x60003000 /* inside qmrg sram		*/
+#define CONFIG_SYS_BOOTCOUNT_ADDR	0x60003000 /* inside qmrg sram		*/
 
 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
 #define CONFIG_SETUP_MEMORY_TAGS 1
@@ -66,14 +66,15 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(256 << 10)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
+#define CONFIG_IXP_SERIAL
 #define CONFIG_BAUDRATE         115200
-#define CFG_IXP425_CONSOLE	IXP425_UART1   /* we use UART1 for console */
+#define CONFIG_SYS_IXP425_CONSOLE	IXP425_UART1   /* we use UART1 for console */
 
 
 /*
@@ -103,22 +104,22 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP                            /* undef to save memory         */
-#define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
-#define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS             16              /* max number of command args   */
-#define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LONGHELP                            /* undef to save memory         */
+#define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt       */
+#define CONFIG_SYS_CBSIZE              256             /* Console I/O Buffer Size      */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS             16              /* max number of command args   */
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE      /* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START       0x00400000      /* memtest works on     */
-#define CFG_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
-#define CFG_LOAD_ADDR           0x00010000      /* default load address */
+#define CONFIG_SYS_MEMTEST_START       0x00400000      /* memtest works on     */
+#define CONFIG_SYS_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
+#define CONFIG_SYS_LOAD_ADDR           0x00010000      /* default load address */
 
-#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#undef  CONFIG_SYS_CLKS_IN_HZ          /* everything, incl board info, in Hz */
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Stack sizes
@@ -184,46 +185,46 @@
 #define PHYS_FLASH_BANK_SIZE    0x01000000 /* 16 MB Banks */
 #define PHYS_FLASH_SECT_SIZE    0x00020000 /* 128 KB sectors (x1) */
 
-#define CFG_DRAM_BASE           0x00000000
-#define CFG_DRAM_SIZE           0x01000000
+#define CONFIG_SYS_DRAM_BASE           0x00000000
+#define CONFIG_SYS_DRAM_SIZE           0x01000000
 
-#define CFG_FLASH_BASE          PHYS_FLASH_1
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 
 /*
  * Expansion bus settings
  */
-#define CFG_EXP_CS0		0xbcd23c42
+#define CONFIG_SYS_EXP_CS0		0xbcd23c42
 
 /*
  * SDRAM settings
  */
-#define CFG_SDR_CONFIG		0x18
-#define CFG_SDR_MODE_CONFIG	0x1
-#define CFG_SDRAM_REFRESH_CNT	0x81a
+#define CONFIG_SYS_SDR_CONFIG		0x18
+#define CONFIG_SYS_SDR_MODE_CONFIG	0x1
+#define CONFIG_SYS_SDRAM_REFRESH_CNT	0x81a
 
 /*
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
-#define CFG_MAX_FLASH_SECT      128	/* max number of sectors on one chip    */
+#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* max number of memory banks           */
+#define CONFIG_SYS_MAX_FLASH_SECT      128	/* max number of sectors on one chip    */
 
-#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
 #define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
 #define	CONFIG_ENV_IS_IN_FLASH	1
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_PROTECTION	1	/* hardware flash protection		*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware flash protection		*/
 
-#define CFG_FLASH_BANKS_LIST	{ PHYS_FLASH_1 }
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1 }
 
-#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	*/
 #define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x40000)
@@ -236,16 +237,16 @@
 /*
  * GPIO settings
  */
-#define CFG_GPIO_PCI_INTA_N	6
-#define CFG_GPIO_PCI_INTB_N	7
-#define CFG_GPIO_SWITCH_RESET_N	8
-#define CFG_GPIO_SLIC_RESET_N	13
-#define CFG_GPIO_PCI_CLK	14
-#define CFG_GPIO_EXTBUS_CLK	15
+#define CONFIG_SYS_GPIO_PCI_INTA_N	6
+#define CONFIG_SYS_GPIO_PCI_INTB_N	7
+#define CONFIG_SYS_GPIO_SWITCH_RESET_N	8
+#define CONFIG_SYS_GPIO_SLIC_RESET_N	13
+#define CONFIG_SYS_GPIO_PCI_CLK	14
+#define CONFIG_SYS_GPIO_EXTBUS_CLK	15
 
 /*
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SIZE	32
 
 #endif  /* __CONFIG_H */
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
index 5d8e3a6..9c45acf 100644
--- a/include/configs/jupiter.h
+++ b/include/configs/jupiter.h
@@ -33,7 +33,7 @@
 #define CONFIG_MPC5200		1	/* especially an MPC5200 */
 #define CONFIG_JUPITER		1	/* ... on Jupiter board */
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
 
 #define CONFIG_BOARD_EARLY_INIT_R	1
 #define CONFIG_BOARD_EARLY_INIT_F	1
@@ -48,7 +48,7 @@
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*
  * PCI Mapping:
@@ -71,11 +71,11 @@
 #define CONFIG_PCI_IO_SIZE	0x01000000
 #endif
 
-#define CFG_XLB_PIPELINING	1
+#define CONFIG_SYS_XLB_PIPELINING	1
 
 #define CONFIG_NET_MULTI	1
 #define CONFIG_MII		1
-#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
 
 /* Partitions */
 #define CONFIG_MAC_PARTITION
@@ -144,7 +144,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133			/* define for 133MHz speed */
+#undef CONFIG_SYS_IPBSPEED_133			/* define for 133MHz speed */
 
 #if 0
 /* pass open firmware flat tree */
@@ -162,41 +162,41 @@
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
 
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration
  */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
 #endif
 
 /*
  * Flash configuration
  */
-#define CFG_FLASH_BASE		0xFF000000
-#define CFG_FLASH_SIZE		0x01000000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
 
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
 
 #define CONFIG_ENV_ADDR		(TEXT_BASE + 0x40000) /* third sector */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
 
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks */
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
-#define CFG_UPDATE_FLASH_SIZE	1
-#define CFG_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#define CONFIG_SYS_UPDATE_FLASH_SIZE	1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
 
 /*
  * Environment settings
@@ -213,91 +213,92 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
 /*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
  */
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
 #define CONFIG_PHY_ADDR		0x00
 
 /*
  * GPIO configuration
  */
-#define CFG_GPS_PORT_CONFIG	0x10000004
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x10000004
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-#define CFG_ALT_MEMTEST		1
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_ALT_MEMTEST		1
 
-#define CFG_LOAD_ADDR		0x200000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*
  * Various low-level settings
  */
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x00047801
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047801
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
 
-#define CFG_RESET_ADDRESS	0xff000000
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index fac2844..0d89594 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -38,14 +38,13 @@
 #define CONFIG_440			1	/* ... PPC440 family	*/
 #define CONFIG_440SPE			1	/* Specifc SPe support	*/
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
-#define CFG_4xx_RESET_TYPE	0x2	/* use chip reset on this board	*/
+#define CONFIG_SYS_4xx_RESET_TYPE	0x2	/* use chip reset on this board	*/
 
 /*
  * Enable this board for more than 2GB of SDRAM
  */
 #define CONFIG_PHYS_64BIT
 #define	CONFIG_VERY_BIG_RAM
-#define CONFIG_MAX_MEM_MAPPED	((phys_size_t)2 << 30)
 
 /*
  * Include common defines/options for all AMCC eval boards
@@ -53,6 +52,13 @@
 #define CONFIG_HOSTNAME		katmai
 #include "amcc-common.h"
 
+/*
+ * For booting 256K-paged Linux we should have 16MB of memory
+ * for Linux initial memory map
+ */
+#undef CONFIG_SYS_BOOTMAPSZ
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)
+
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_pre_init		*/
 #undef  CONFIG_SHOW_BOOT_PROGRESS
 
@@ -60,53 +66,53 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE		0xff000000	/* start of FLASH	*/
-#define CFG_PERIPHERAL_BASE	0xa0000000	/* internal peripherals	*/
-#define CFG_ISRAM_BASE		0x90000000	/* internal SRAM	*/
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH	*/
+#define CONFIG_SYS_PERIPHERAL_BASE	0xa0000000	/* internal peripherals	*/
+#define CONFIG_SYS_ISRAM_BASE		0x90000000	/* internal SRAM	*/
 
-#define CFG_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
-#define CFG_PCI_BASE		0xd0000000	/* internal PCI regs	*/
-#define CFG_PCI_TARGBASE	CFG_PCI_MEMBASE
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
+#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs	*/
+#define CONFIG_SYS_PCI_TARGBASE	CONFIG_SYS_PCI_MEMBASE
 
-#define CFG_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
-#define CFG_PCIE_MEMSIZE	0x08000000	/* smallest incr for PCIe port */
-#define CFG_PCIE_BASE		0xe0000000	/* PCIe UTL regs */
+#define CONFIG_SYS_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
+#define CONFIG_SYS_PCIE_MEMSIZE	0x08000000	/* smallest incr for PCIe port */
+#define CONFIG_SYS_PCIE_BASE		0xe0000000	/* PCIe UTL regs */
 
-#define CFG_PCIE0_CFGBASE	0xc0000000
-#define CFG_PCIE1_CFGBASE	0xc1000000
-#define CFG_PCIE2_CFGBASE	0xc2000000
-#define CFG_PCIE0_XCFGBASE	0xc3000000
-#define CFG_PCIE1_XCFGBASE	0xc3001000
-#define CFG_PCIE2_XCFGBASE	0xc3002000
+#define CONFIG_SYS_PCIE0_CFGBASE	0xc0000000
+#define CONFIG_SYS_PCIE1_CFGBASE	0xc1000000
+#define CONFIG_SYS_PCIE2_CFGBASE	0xc2000000
+#define CONFIG_SYS_PCIE0_XCFGBASE	0xc3000000
+#define CONFIG_SYS_PCIE1_XCFGBASE	0xc3001000
+#define CONFIG_SYS_PCIE2_XCFGBASE	0xc3002000
 
 /* base address of inbound PCIe window */
-#define CFG_PCIE_INBOUND_BASE	0x0000000000000000ULL
+#define CONFIG_SYS_PCIE_INBOUND_BASE	0x0000000000000000ULL
 
 /* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
 
-#define CFG_ACE_BASE		0xfe000000	/* Xilinx ACE controller - Compact Flash */
+#define CONFIG_SYS_ACE_BASE		0xfe000000	/* Xilinx ACE controller - Compact Flash */
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
-#define CFG_TEMP_STACK_OCM	1
-#define CFG_OCM_DATA_ADDR	CFG_ISRAM_BASE
-#define CFG_INIT_RAM_ADDR	CFG_ISRAM_BASE	/* Initial RAM address	*/
-#define CFG_INIT_RAM_END	0x2000		/* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_END	0x2000		/* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
 
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_POST_WORD_ADDR
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
 #undef CONFIG_UART1_CONSOLE
-#undef CFG_EXT_SERIAL_CLOCK
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK
 
 /*-----------------------------------------------------------------------
  * DDR SDRAM
@@ -120,35 +126,34 @@
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address	*/
 
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
-#define CFG_SPD_BUS_NUM		0	/* The I2C bus for SPD		*/
+#define CONFIG_SYS_SPD_BUS_NUM		0	/* The I2C bus for SPD		*/
 
 #define IIC0_BOOTPROM_ADDR	0x50
 #define IIC0_ALT_BOOTPROM_ADDR	0x54
 
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	(0x50)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0x50)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 
 /* I2C RTC */
 #define CONFIG_RTC_M41T11	1
-#define CFG_RTC_BUS_NUM		1	/* The I2C bus for RTC		*/
-#define CFG_I2C_RTC_ADDR	0x68
-#define CFG_M41T11_BASE_YEAR	1900	/* play along with linux	*/
+#define CONFIG_SYS_RTC_BUS_NUM		1	/* The I2C bus for RTC		*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	1900	/* play along with linux	*/
 
 /* I2C DTT */
 #define CONFIG_DTT_ADM1021	1	/* ADM1021 temp sensor support	*/
-#define CFG_DTT_BUS_NUM		1	/* The I2C bus for DTT		*/
+#define CONFIG_SYS_DTT_BUS_NUM		1	/* The I2C bus for DTT		*/
 /*
  * standard dtt sensor configuration - bottom bit will determine local or
  * remote sensor of the ADM1021, the rest determines index into
- * CFG_DTT_ADM1021 array below.
+ * CONFIG_SYS_DTT_ADM1021 array below.
  */
 #define CONFIG_DTT_SENSORS	{ 0, 1 }
 
@@ -165,7 +170,7 @@
  * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
  * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
  */
-#define CFG_DTT_ADM1021		{ { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
+#define CONFIG_SYS_DTT_ADM1021		{ { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
 
 /*-----------------------------------------------------------------------
  * Environment
@@ -190,6 +195,7 @@
 /*
  * Commands additional to the ones defined in amcc-common.h
  */
+#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SDRAM
@@ -206,21 +212,21 @@
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
 
-#define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
-#define CFG_MAX_FLASH_BANKS     1		    /* number of banks	    */
-#define CFG_MAX_FLASH_SECT	1024		    /* sectors per device   */
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS     1		    /* number of banks	    */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		    /* sectors per device   */
 
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -238,12 +244,12 @@
 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT		/* let board init pci target    */
-#undef	CFG_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */
+#undef	CONFIG_SYS_PCI_MASTER_INIT
 
-#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
-/* #define CFG_PCI_SUBSYS_ID	CFG_PCI_SUBSYS_DEVICEID */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
+/* #define CONFIG_SYS_PCI_SUBSYS_ID	CONFIG_SYS_PCI_SUBSYS_DEVICEID */
 
 /*
  *  NETWORK Support (PCI):
@@ -255,8 +261,8 @@
  * Xilinx System ACE support
  *----------------------------------------------------------------------*/
 #define CONFIG_SYSTEMACE	1	/* Enable SystemACE support	*/
-#define CFG_SYSTEMACE_WIDTH	16	/* Data bus width is 16		*/
-#define CFG_SYSTEMACE_BASE	CFG_ACE_BASE
+#define CONFIG_SYS_SYSTEMACE_WIDTH	16	/* Data bus width is 16		*/
+#define CONFIG_SYS_SYSTEMACE_BASE	CONFIG_SYS_ACE_BASE
 #define CONFIG_DOS_PARTITION	1
 
 /*-----------------------------------------------------------------------
@@ -264,7 +270,7 @@
  *----------------------------------------------------------------------*/
 
 /* Memory Bank 0 (Flash) initialization					*/
-#define CFG_EBC_PB0AP		(EBC_BXAP_BME_DISABLED      |		\
+#define CONFIG_SYS_EBC_PB0AP		(EBC_BXAP_BME_DISABLED      |		\
 				 EBC_BXAP_TWT_ENCODE(7)     |		\
 				 EBC_BXAP_BCE_DISABLE       |		\
 				 EBC_BXAP_BCT_2TRANS        |		\
@@ -277,13 +283,13 @@
 				 EBC_BXAP_SOR_DELAYED       |		\
 				 EBC_BXAP_BEM_WRITEONLY     |		\
 				 EBC_BXAP_PEN_DISABLED)
-#define CFG_EBC_PB0CR		(EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |	\
+#define CONFIG_SYS_EBC_PB0CR		(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |	\
 				 EBC_BXCR_BS_16MB                    |	\
 				 EBC_BXCR_BU_RW                      |	\
 				 EBC_BXCR_BW_16BIT)
 
 /* Memory Bank 1 (Xilinx System ACE controller) initialization		*/
-#define CFG_EBC_PB1AP		(EBC_BXAP_BME_DISABLED      |		\
+#define CONFIG_SYS_EBC_PB1AP		(EBC_BXAP_BME_DISABLED      |		\
 				 EBC_BXAP_TWT_ENCODE(4)     |		\
 				 EBC_BXAP_BCE_DISABLE       |		\
 				 EBC_BXAP_BCT_2TRANS        |		\
@@ -296,7 +302,7 @@
 				 EBC_BXAP_SOR_NONDELAYED    |		\
 				 EBC_BXAP_BEM_WRITEONLY     |		\
 				 EBC_BXAP_PEN_DISABLED)
-#define CFG_EBC_PB1CR		(EBC_BXCR_BAS_ENCODE(CFG_ACE_BASE)  |	\
+#define CONFIG_SYS_EBC_PB1CR		(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE)  |	\
 				 EBC_BXCR_BS_1MB                    |	\
 				 EBC_BXCR_BU_RW                     |	\
 				 EBC_BXCR_BW_16BIT)
@@ -306,7 +312,7 @@
  * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
  * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
  *-------------------------------------------------------------------------*/
-#define CFG_EBC_CFG		(EBC_CFG_LE_UNLOCK    |	\
+#define CONFIG_SYS_EBC_CFG		(EBC_CFG_LE_UNLOCK    |	\
 				 EBC_CFG_PTD_ENABLE   |	\
 				 EBC_CFG_RTC_16PERCLK | \
 				 EBC_CFG_ATC_PREVIOUS | \
@@ -320,17 +326,17 @@
 /*-----------------------------------------------------------------------
  * GPIO Setup
  *----------------------------------------------------------------------*/
-#define CFG_GPIO_PCIE_PRESENT0	17
-#define CFG_GPIO_PCIE_PRESENT1	21
-#define CFG_GPIO_PCIE_PRESENT2	23
-#define CFG_GPIO_RS232_FORCEOFF	30
-
-#define CFG_PFC0		(GPIO_VAL(CFG_GPIO_PCIE_PRESENT0) | \
-				 GPIO_VAL(CFG_GPIO_PCIE_PRESENT1) | \
-				 GPIO_VAL(CFG_GPIO_PCIE_PRESENT2) | \
-				 GPIO_VAL(CFG_GPIO_RS232_FORCEOFF))
-#define CFG_GPIO_OR		GPIO_VAL(CFG_GPIO_RS232_FORCEOFF)
-#define CFG_GPIO_TCR		GPIO_VAL(CFG_GPIO_RS232_FORCEOFF)
-#define CFG_GPIO_ODR		0
+#define CONFIG_SYS_GPIO_PCIE_PRESENT0	17
+#define CONFIG_SYS_GPIO_PCIE_PRESENT1	21
+#define CONFIG_SYS_GPIO_PCIE_PRESENT2	23
+#define CONFIG_SYS_GPIO_RS232_FORCEOFF	30
+
+#define CONFIG_SYS_PFC0		(GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
+				 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
+				 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
+				 GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
+#define CONFIG_SYS_GPIO_OR		GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
+#define CONFIG_SYS_GPIO_TCR		GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
+#define CONFIG_SYS_GPIO_ODR		0
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h
index 3c51417..1ce8c69 100644
--- a/include/configs/kb9202.h
+++ b/include/configs/kb9202.h
@@ -51,8 +51,10 @@
 #define CONFIG_INITRD_TAG	1
 
 #define	CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT	/* undef this for direct boot from */
+									/* NOR flash without preloader */
 
-#define	CFG_LONGHELP
+#define	CONFIG_SYS_LONGHELP
 
 #ifndef roundup
 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
@@ -60,8 +62,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN	(roundup(CONFIG_ENV_SIZE,4096) + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN	(roundup(CONFIG_ENV_SIZE,4096) + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 #define CONFIG_BAUDRATE 115200
 
@@ -109,13 +111,13 @@
 #define PHYS_SDRAM 0x20000000
 #define PHYS_SDRAM_SIZE 0x2000000  /* 32 megs */
 
-#define CFG_MEMTEST_START		PHYS_SDRAM
-#define CFG_MEMTEST_END			CFG_MEMTEST_START + PHYS_SDRAM_SIZE - (512*1024)
+#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END			CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - (512*1024)
 
 #define CONFIG_DRIVER_ETHER
 #define CONFIG_NET_RETRY_COUNT		20
 
-#define CFG_FLASH_BASE			0x10000000
+#define CONFIG_SYS_FLASH_BASE			0x10000000
 
 #ifdef CONFIG_KB9202
 #define PHYS_FLASH_SIZE			0x1000000
@@ -123,8 +125,8 @@
 #define PHYS_FLASH_SIZE			0x200000
 #endif
 
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		256
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		256
 
 #define	CONFIG_HARD_I2C
 
@@ -137,24 +139,24 @@
 #define CONFIG_ENV_OFFSET			0x1000
 #define CONFIG_ENV_SIZE			0x1000
 #endif
-#define	CFG_I2C_EEPROM_ADDR		0x50
-#define	CFG_EEPROM_PAGE_WRITE_BITS	6
-#define	CFG_I2C_EEPROM_ADDR_LEN		2
-#define	CFG_I2C_SPEED			50000
-#define	CFG_I2C_SLAVE			0 /* not used */
-#define	CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define	CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define	CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define	CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define	CONFIG_SYS_I2C_SPEED			50000
+#define	CONFIG_SYS_I2C_SLAVE			0 /* not used */
+#define	CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 
-#define CFG_LOAD_ADDR		0x21000000  /* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
 
-#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
 
-#define CFG_PROMPT		"U-Boot> "	/* Monitor Command Prompt */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_PROMPT		"U-Boot> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 
 #define	CONFIG_FLASH_CFI_DRIVER
-#define	CFG_FLASH_CFI
+#define	CONFIG_SYS_FLASH_CFI
 
 #ifndef __ASSEMBLY__
 /*-----------------------------------------------------------------------
@@ -175,8 +177,8 @@ struct bd_info_ext {
 };
 #endif
 
-#define CFG_HZ 1000
-#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2	/* AT91C_TC0_CMR is implicitly set to */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2	/* AT91C_TC0_CMR is implicitly set to */
 					/* AT91C_TC_TIMER_DIV1_CLOCK */
 
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h
new file mode 100644
index 0000000..d70bc48
--- /dev/null
+++ b/include/configs/keymile-common.h
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_KEYMILE_H
+#define __CONFIG_KEYMILE_H
+
+/* Do boardspecific init for all boards */
+#define CONFIG_BOARD_EARLY_INIT_R       1
+
+#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD)
+#define CONFIG_BOOTCOUNT_LIMIT
+#endif
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+/* should go away, if kmeter I2C support is enabled */
+#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD)
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#endif
+
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+#undef	CONFIG_BOOTARGS			/* the boot command will set bootargs */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size  */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */
+#define CONFIG_CMDLINE_EDITING		1	/* add command line history     */
+
+/* should go away, if kmeter I2C support is enabled */
+#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD)
+#define CONFIG_HUSH_INIT_VAR	1
+#endif
+
+#define CONFIG_SYS_ALT_MEMTEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * How to get access to the slot ID.  Put this here to make it easy
+ * to modify in a centralized location.  This is used in the HDLC
+ * driver to set the MAC.
+*/
+#define CONFIG_CHECK_ETHERNET_PRESENT	1
+#define CONFIG_SYS_SLOT_ID_BASE		CONFIG_SYS_PIGGY_BASE
+#define CONFIG_SYS_SLOT_ID_OFF		(0x07)	/* register offset */
+#define CONFIG_SYS_SLOT_ID_MASK		(0x3f)	/* mask for slot ID bits */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+#endif /* __CONFIG_KEYMILE_H */
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index 58918d4..26cb854 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -53,10 +53,10 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE		0xFC000000
-#define CFG_NAND_ADDR		0xF8000000
-#define CFG_FPGA_BASE		0xF0000000
-#define CFG_PERIPHERAL_BASE	0xEF600000      /* internal peripherals*/
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_NAND_ADDR		0xF8000000
+#define CONFIG_SYS_FPGA_BASE		0xF0000000
+#define CONFIG_SYS_PERIPHERAL_BASE	0xEF600000      /* internal peripherals*/
 
 /*-----------------------------------------------------------------------
  * Initial RAM & Stack Pointer Configuration Options
@@ -72,25 +72,25 @@
  *   the latter of which is less than desireable since it requires
  *   setting up the SDRAM and ECC in assembly code.
  *
- *   To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip
+ *   To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
  *   select on the External Bus Controller (EBC) and then select a
- *   value for 'CFG_INIT_RAM_ADDR' outside of the range of valid,
- *   physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and
- *   select a value for 'CFG_INIT_RAM_ADDR' within the range of valid,
+ *   value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
+ *   physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
+ *   select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
  *   physical SDRAM to use (3).
  *-----------------------------------------------------------------------*/
 
-#define CFG_INIT_DCACHE_CS	4
+#define CONFIG_SYS_INIT_DCACHE_CS	4
 
-#if defined(CFG_INIT_DCACHE_CS)
-#define CFG_INIT_RAM_ADDR	(CFG_SDRAM_BASE + ( 1 << 30))	/*  1 GiB */
+#if defined(CONFIG_SYS_INIT_DCACHE_CS)
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + ( 1 << 30))	/*  1 GiB */
 #else
-#define CFG_INIT_RAM_ADDR	(CFG_SDRAM_BASE + (32 << 20))	/* 32 MiB */
-#endif /* defined(CFG_INIT_DCACHE_CS) */
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + (32 << 20))	/* 32 MiB */
+#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
 
-#define CFG_INIT_RAM_END        (4 << 10)			/*  4 KiB */
-#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_END        (4 << 10)			/*  4 KiB */
+#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 /*
  * If the data cache is being used for the primordial stack and global
@@ -100,20 +100,20 @@
  * for the POST word.
  */
 
-#if defined(CFG_INIT_DCACHE_CS)
-# define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-# define CFG_POST_ALT_WORD_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP6)
+#if defined(CONFIG_SYS_INIT_DCACHE_CS)
+# define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+# define CONFIG_SYS_POST_ALT_WORD_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
 #else
-# define CFG_INIT_EXTRA_SIZE	16
-# define CFG_INIT_SP_OFFSET	(CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE)
-# define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 4)
-# define CFG_OCM_DATA_ADDR	CFG_INIT_RAM_ADDR
-#endif /* defined(CFG_INIT_DCACHE_CS) */
+# define CONFIG_SYS_INIT_EXTRA_SIZE	16
+# define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
+# define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 4)
+# define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_INIT_RAM_ADDR
+#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#define CFG_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
 /* define this if you want console on UART1 */
 #undef CONFIG_UART1_CONSOLE
 
@@ -130,22 +130,22 @@
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI			/* The flash is CFI compatible	*/
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
 
-#define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -171,57 +171,56 @@
  * set up. While still running from location 0xfffff000...0xffffffff the
  * NAND controller cannot be accessed since it is attached to CS0 too.
  */
-#define CFG_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
-#define CFG_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
-#define CFG_NAND_BOOT_SPL_DST	0x00800000	/* Copy SPL here		*/
-#define CFG_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
-#define CFG_NAND_U_BOOT_START	CFG_NAND_U_BOOT_DST /* Start NUB from this addr	*/
-#define CFG_NAND_BOOT_SPL_DELTA	(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
+#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
+#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
+#define CONFIG_SYS_NAND_BOOT_SPL_DST	0x00800000	/* Copy SPL here		*/
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr	*/
+#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 
 /*
  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
  */
-#define CFG_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
-#define CFG_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/
 
 /*
  * Now the NAND chip has to be defined (no autodetection used!)
  */
-#define CFG_NAND_PAGE_SIZE	512		/* NAND chip page size		*/
-#define CFG_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
-#define CFG_NAND_PAGE_COUNT	32		/* NAND chip page count		*/
-#define CFG_NAND_BAD_BLOCK_POS	5		/* Location of bad block marker	*/
-#define CFG_NAND_4_ADDR_CYCLE	1		/* Fourth addr used (>32MB)	*/
-
-#define CFG_NAND_ECCSIZE	256
-#define CFG_NAND_ECCBYTES	3
-#define CFG_NAND_ECCSTEPS	(CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
-#define CFG_NAND_OOBSIZE	16
-#define CFG_NAND_ECCTOTAL	(CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
-#define CFG_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
+#define CONFIG_SYS_NAND_PAGE_SIZE	512		/* NAND chip page size		*/
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
+#define CONFIG_SYS_NAND_PAGE_COUNT	32		/* NAND chip page count		*/
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	5		/* Location of bad block marker	*/
+#define CONFIG_SYS_NAND_4_ADDR_CYCLE	1		/* Fourth addr used (>32MB)	*/
+
+#define CONFIG_SYS_NAND_ECCSIZE	256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_OOBSIZE	16
+#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
+#define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
 
 #ifdef CONFIG_ENV_IS_IN_NAND
 /*
  * For NAND booting the environment is embedded in the U-Boot image. Please take
  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
  */
-#define CONFIG_ENV_SIZE		CFG_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(CFG_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 #endif
 
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/
-#define CFG_MAX_NAND_DEVICE	1
-#define NAND_MAX_CHIPS		1
-#define CFG_NAND_BASE		(CFG_NAND_ADDR + CFG_NAND_CS)
-#define CFG_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
+#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
 
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
-#define CFG_MBYTES_SDRAM        (256)		/* 256MB			*/
+#define CONFIG_SYS_MBYTES_SDRAM        (256)		/* 256MB			*/
 
 /*
  * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
@@ -239,55 +238,55 @@
 #define	DEBUG_PPC4xx_DDR_AUTOCALIBRATION	/* dynamic DDR autocal debug */
 #undef	CONFIG_PPC4xx_DDR_METHOD_A
 
-#define	CFG_SDRAM0_MB0CF_BASE	((  0 << 20) + CFG_SDRAM_BASE)
+#define	CONFIG_SYS_SDRAM0_MB0CF_BASE	((  0 << 20) + CONFIG_SYS_SDRAM_BASE)
 
 /* DDR1/2 SDRAM Device Control Register Data Values */
-#define CFG_SDRAM0_MB0CF	((CFG_SDRAM0_MB0CF_BASE >> 3)	| \
+#define CONFIG_SYS_SDRAM0_MB0CF	((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3)	| \
 				 SDRAM_RXBAS_SDSZ_256MB		| \
 				 SDRAM_RXBAS_SDAM_MODE7		| \
 				 SDRAM_RXBAS_SDBE_ENABLE)
-#define CFG_SDRAM0_MB1CF	SDRAM_RXBAS_SDBE_DISABLE
-#define CFG_SDRAM0_MB2CF	SDRAM_RXBAS_SDBE_DISABLE
-#define CFG_SDRAM0_MB3CF	SDRAM_RXBAS_SDBE_DISABLE
-#define CFG_SDRAM0_MCOPT1	(SDRAM_MCOPT1_PMU_OPEN		| \
+#define CONFIG_SYS_SDRAM0_MB1CF	SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MB2CF	SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MB3CF	SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MCOPT1	(SDRAM_MCOPT1_PMU_OPEN		| \
 				 SDRAM_MCOPT1_8_BANKS		| \
 				 SDRAM_MCOPT1_DDR2_TYPE		| \
 				 SDRAM_MCOPT1_QDEP		| \
 				 SDRAM_MCOPT1_DCOO_DISABLED)
-#define CFG_SDRAM0_MCOPT2	0x00000000
-#define CFG_SDRAM0_MODT0	(SDRAM_MODT_EB0W_ENABLE | \
+#define CONFIG_SYS_SDRAM0_MCOPT2	0x00000000
+#define CONFIG_SYS_SDRAM0_MODT0	(SDRAM_MODT_EB0W_ENABLE | \
 				 SDRAM_MODT_EB0R_ENABLE)
-#define CFG_SDRAM0_MODT1	0x00000000
-#define CFG_SDRAM0_CODT		(SDRAM_CODT_RK0R_ON		| \
+#define CONFIG_SYS_SDRAM0_MODT1	0x00000000
+#define CONFIG_SYS_SDRAM0_CODT		(SDRAM_CODT_RK0R_ON		| \
 				 SDRAM_CODT_CKLZ_36OHM		| \
 				 SDRAM_CODT_DQS_1_8_V_DDR2	| \
 				 SDRAM_CODT_IO_NMODE)
-#define CFG_SDRAM0_RTR		SDRAM_RTR_RINT_ENCODE(1560)
-#define CFG_SDRAM0_INITPLR0	(SDRAM_INITPLR_ENABLE			| \
+#define CONFIG_SYS_SDRAM0_RTR		SDRAM_RTR_RINT_ENCODE(1560)
+#define CONFIG_SYS_SDRAM0_INITPLR0	(SDRAM_INITPLR_ENABLE			| \
 		SDRAM_INITPLR_IMWT_ENCODE(80)				| \
 		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
-#define CFG_SDRAM0_INITPLR1	(SDRAM_INITPLR_ENABLE			| \
+#define CONFIG_SYS_SDRAM0_INITPLR1	(SDRAM_INITPLR_ENABLE			| \
 		SDRAM_INITPLR_IMWT_ENCODE(3)				| \
 		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)		| \
 		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)			| \
 		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
-#define CFG_SDRAM0_INITPLR2	(SDRAM_INITPLR_ENABLE			| \
+#define CONFIG_SYS_SDRAM0_INITPLR2	(SDRAM_INITPLR_ENABLE			| \
 		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
 		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
 		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2)			| \
 		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
-#define CFG_SDRAM0_INITPLR3	(SDRAM_INITPLR_ENABLE			| \
+#define CONFIG_SYS_SDRAM0_INITPLR3	(SDRAM_INITPLR_ENABLE			| \
 		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
 		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
 		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3)			| \
 		SDRAM_INITPLR_IMA_ENCODE(0))
-#define CFG_SDRAM0_INITPLR4	(SDRAM_INITPLR_ENABLE			| \
+#define CONFIG_SYS_SDRAM0_INITPLR4	(SDRAM_INITPLR_ENABLE			| \
 		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
 		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
 		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)			| \
 		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
 					 JEDEC_MA_EMR_RTT_75OHM))
-#define CFG_SDRAM0_INITPLR5	(SDRAM_INITPLR_ENABLE			| \
+#define CONFIG_SYS_SDRAM0_INITPLR5	(SDRAM_INITPLR_ENABLE			| \
 		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
 		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
 		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)			| \
@@ -295,31 +294,31 @@
 					 JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
 					 JEDEC_MA_MR_BLEN_4 | \
 					 JEDEC_MA_MR_DLL_RESET))
-#define CFG_SDRAM0_INITPLR6	(SDRAM_INITPLR_ENABLE			| \
+#define CONFIG_SYS_SDRAM0_INITPLR6	(SDRAM_INITPLR_ENABLE			| \
 		SDRAM_INITPLR_IMWT_ENCODE(3)				| \
 		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)		| \
 		SDRAM_INITPLR_IBA_ENCODE(0x0)				| \
 		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
-#define CFG_SDRAM0_INITPLR7	(SDRAM_INITPLR_ENABLE			| \
+#define CONFIG_SYS_SDRAM0_INITPLR7	(SDRAM_INITPLR_ENABLE			| \
 		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
 		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CFG_SDRAM0_INITPLR8	(SDRAM_INITPLR_ENABLE			| \
+#define CONFIG_SYS_SDRAM0_INITPLR8	(SDRAM_INITPLR_ENABLE			| \
 		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
 		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CFG_SDRAM0_INITPLR9	(SDRAM_INITPLR_ENABLE			| \
+#define CONFIG_SYS_SDRAM0_INITPLR9	(SDRAM_INITPLR_ENABLE			| \
 		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
 		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CFG_SDRAM0_INITPLR10	(SDRAM_INITPLR_ENABLE			| \
+#define CONFIG_SYS_SDRAM0_INITPLR10	(SDRAM_INITPLR_ENABLE			| \
 		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
 		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
-#define CFG_SDRAM0_INITPLR11	(SDRAM_INITPLR_ENABLE			| \
+#define CONFIG_SYS_SDRAM0_INITPLR11	(SDRAM_INITPLR_ENABLE			| \
 		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
 		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
 		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)			| \
 		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
 					 JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
 					 JEDEC_MA_MR_BLEN_4))
-#define CFG_SDRAM0_INITPLR12	(SDRAM_INITPLR_ENABLE			| \
+#define CONFIG_SYS_SDRAM0_INITPLR12	(SDRAM_INITPLR_ENABLE			| \
 		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
 		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
 		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)			| \
@@ -328,7 +327,7 @@
 					 JEDEC_MA_EMR_DQS_DISABLE | \
 					 JEDEC_MA_EMR_RTT_DISABLED | \
 					 JEDEC_MA_EMR_ODS_NORMAL))
-#define CFG_SDRAM0_INITPLR13	(SDRAM_INITPLR_ENABLE			| \
+#define CONFIG_SYS_SDRAM0_INITPLR13	(SDRAM_INITPLR_ENABLE			| \
 		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
 		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
 		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)			| \
@@ -337,54 +336,54 @@
 					 JEDEC_MA_EMR_DQS_DISABLE | \
 					 JEDEC_MA_EMR_RTT_DISABLED | \
 					 JEDEC_MA_EMR_ODS_NORMAL))
-#define CFG_SDRAM0_INITPLR14	(SDRAM_INITPLR_DISABLE)
-#define CFG_SDRAM0_INITPLR15	(SDRAM_INITPLR_DISABLE)
-#define CFG_SDRAM0_RQDC		(SDRAM_RQDC_RQDE_ENABLE | \
+#define CONFIG_SYS_SDRAM0_INITPLR14	(SDRAM_INITPLR_DISABLE)
+#define CONFIG_SYS_SDRAM0_INITPLR15	(SDRAM_INITPLR_DISABLE)
+#define CONFIG_SYS_SDRAM0_RQDC		(SDRAM_RQDC_RQDE_ENABLE | \
 				 SDRAM_RQDC_RQFD_ENCODE(56))
-#define CFG_SDRAM0_RFDC		SDRAM_RFDC_RFFD_ENCODE(521)
-#define CFG_SDRAM0_RDCC		(SDRAM_RDCC_RDSS_T2)
-#define CFG_SDRAM0_DLCR		(SDRAM_DLCR_DCLM_AUTO		| \
+#define CONFIG_SYS_SDRAM0_RFDC		SDRAM_RFDC_RFFD_ENCODE(521)
+#define CONFIG_SYS_SDRAM0_RDCC		(SDRAM_RDCC_RDSS_T2)
+#define CONFIG_SYS_SDRAM0_DLCR		(SDRAM_DLCR_DCLM_AUTO		| \
 				 SDRAM_DLCR_DLCS_CONT_DONE	| \
 				 SDRAM_DLCR_DLCV_ENCODE(165))
-#define CFG_SDRAM0_CLKTR	(SDRAM_CLKTR_CLKP_180_DEG_ADV)
-#define CFG_SDRAM0_WRDTR	0x00000000
-#define CFG_SDRAM0_SDTR1	(SDRAM_SDTR1_LDOF_2_CLK	| \
+#define CONFIG_SYS_SDRAM0_CLKTR	(SDRAM_CLKTR_CLKP_180_DEG_ADV)
+#define CONFIG_SYS_SDRAM0_WRDTR	0x00000000
+#define CONFIG_SYS_SDRAM0_SDTR1	(SDRAM_SDTR1_LDOF_2_CLK	| \
 				 SDRAM_SDTR1_RTW_2_CLK	| \
 				 SDRAM_SDTR1_RTRO_1_CLK)
-#define CFG_SDRAM0_SDTR2	(SDRAM_SDTR2_RCD_3_CLK		| \
+#define CONFIG_SYS_SDRAM0_SDTR2	(SDRAM_SDTR2_RCD_3_CLK		| \
 				 SDRAM_SDTR2_WTR_2_CLK		| \
 				 SDRAM_SDTR2_XSNR_32_CLK	| \
 				 SDRAM_SDTR2_WPC_4_CLK		| \
 				 SDRAM_SDTR2_RPC_2_CLK		| \
 				 SDRAM_SDTR2_RP_3_CLK		| \
 				 SDRAM_SDTR2_RRD_2_CLK)
-#define CFG_SDRAM0_SDTR3	(SDRAM_SDTR3_RAS_ENCODE(8)	| \
+#define CONFIG_SYS_SDRAM0_SDTR3	(SDRAM_SDTR3_RAS_ENCODE(8)	| \
 				 SDRAM_SDTR3_RC_ENCODE(11)	| \
 				 SDRAM_SDTR3_XCS		| \
 				 SDRAM_SDTR3_RFC_ENCODE(26))
-#define CFG_SDRAM0_MMODE	(SDRAM_MMODE_WR_DDR2_3_CYC | \
+#define CONFIG_SYS_SDRAM0_MMODE	(SDRAM_MMODE_WR_DDR2_3_CYC | \
 				 SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
 				 SDRAM_MMODE_BLEN_4)
-#define CFG_SDRAM0_MEMODE	(SDRAM_MEMODE_DQS_DISABLE | \
+#define CONFIG_SYS_SDRAM0_MEMODE	(SDRAM_MEMODE_DQS_DISABLE | \
 				 SDRAM_MEMODE_RTT_75OHM)
 
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */
-#define CFG_I2C_EEPROM_ADDR	0x52	/* I2C boot EEPROM (24C02BN)	*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52	/* I2C boot EEPROM (24C02BN)	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
 
 /* Standard DTT sensor configuration */
 #define CONFIG_DTT_DS1775	1
 #define CONFIG_DTT_SENSORS	{ 0 }
-#define CFG_I2C_DTT_ADDR	0x48
+#define CONFIG_SYS_I2C_DTT_ADDR	0x48
 
 /* RTC configuration */
 #define CONFIG_RTC_DS1338	1
-#define CFG_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
 
 /*-----------------------------------------------------------------------
  * Ethernet
@@ -432,20 +431,20 @@
 #define CONFIG_CMD_SNTP
 
 /* POST support */
-#define CONFIG_POST		(CFG_POST_CACHE		| \
-				 CFG_POST_CPU		| \
-				 CFG_POST_ETHER		| \
-				 CFG_POST_I2C		| \
-				 CFG_POST_MEMORY	| \
-				 CFG_POST_UART)
+#define CONFIG_POST		(CONFIG_SYS_POST_CACHE		| \
+				 CONFIG_SYS_POST_CPU		| \
+				 CONFIG_SYS_POST_ETHER		| \
+				 CONFIG_SYS_POST_I2C		| \
+				 CONFIG_SYS_POST_MEMORY	| \
+				 CONFIG_SYS_POST_UART)
 
 /* Define here the base-addresses of the UARTs to test in POST */
-#define CFG_POST_UART_TABLE	{UART0_BASE, UART1_BASE}
+#define CONFIG_SYS_POST_UART_TABLE	{UART0_BASE, UART1_BASE}
 
 #define CONFIG_LOGBUFFER
-#define CFG_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/
+#define CONFIG_SYS_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/
 
-#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -458,59 +457,59 @@
 /*-----------------------------------------------------------------------
  * PCIe stuff
  *----------------------------------------------------------------------*/
-#define CFG_PCIE_MEMBASE	0x90000000	/* mapped PCIe memory	*/
-#define CFG_PCIE_MEMSIZE	0x08000000      /* 128 Meg, smallest incr per port */
+#define CONFIG_SYS_PCIE_MEMBASE	0x90000000	/* mapped PCIe memory	*/
+#define CONFIG_SYS_PCIE_MEMSIZE	0x08000000      /* 128 Meg, smallest incr per port */
 
-#define	CFG_PCIE0_CFGBASE	0xa0000000      /* remote access */
-#define	CFG_PCIE0_XCFGBASE	0xb0000000      /* local access */
-#define	CFG_PCIE0_CFGMASK	0xe0000001      /* 512 Meg */
+#define	CONFIG_SYS_PCIE0_CFGBASE	0xa0000000      /* remote access */
+#define	CONFIG_SYS_PCIE0_XCFGBASE	0xb0000000      /* local access */
+#define	CONFIG_SYS_PCIE0_CFGMASK	0xe0000001      /* 512 Meg */
 
-#define	CFG_PCIE1_CFGBASE	0xc0000000      /* remote access */
-#define	CFG_PCIE1_XCFGBASE	0xd0000000      /* local access */
-#define	CFG_PCIE1_CFGMASK	0xe0000001      /* 512 Meg */
+#define	CONFIG_SYS_PCIE1_CFGBASE	0xc0000000      /* remote access */
+#define	CONFIG_SYS_PCIE1_XCFGBASE	0xd0000000      /* local access */
+#define	CONFIG_SYS_PCIE1_CFGMASK	0xe0000001      /* 512 Meg */
 
-#define	CFG_PCIE0_UTLBASE	0xef502000
-#define	CFG_PCIE1_UTLBASE	0xef503000
+#define	CONFIG_SYS_PCIE0_UTLBASE	0xef502000
+#define	CONFIG_SYS_PCIE1_UTLBASE	0xef503000
 
 /* base address of inbound PCIe window */
-#define CFG_PCIE_INBOUND_BASE	0x0000000000000000ULL
+#define CONFIG_SYS_PCIE_INBOUND_BASE	0x0000000000000000ULL
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 /* booting from NAND, so NAND chips select has to be on CS 0 */
-#define CFG_NAND_CS		0		/* NAND chip connected to CSx	*/
+#define CONFIG_SYS_NAND_CS		0		/* NAND chip connected to CSx	*/
 
 /* Memory Bank 1 (NOR-FLASH) initialization					*/
-#define CFG_EBC_PB1AP		0x05806500
-#define CFG_EBC_PB1CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB1AP		0x05806500
+#define CONFIG_SYS_EBC_PB1CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
 
 /* Memory Bank 0 (NAND-FLASH) initialization					*/
-#define CFG_EBC_PB0AP		0x018003c0
-#define CFG_EBC_PB0CR		(CFG_NAND_ADDR | 0x1e000)
+#define CONFIG_SYS_EBC_PB0AP		0x018003c0
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1e000)
 #else
-#define CFG_NAND_CS		1		/* NAND chip connected to CSx	*/
+#define CONFIG_SYS_NAND_CS		1		/* NAND chip connected to CSx	*/
 
 /* Memory Bank 0 (NOR-FLASH) initialization					*/
-#define CFG_EBC_PB0AP		0x05806500
-#define CFG_EBC_PB0CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB0AP		0x05806500
+#define CONFIG_SYS_EBC_PB0CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
 
 /* Memory Bank 1 (NAND-FLASH) initialization					*/
-#define CFG_EBC_PB1AP		0x018003c0
-#define CFG_EBC_PB1CR		(CFG_NAND_ADDR | 0x1e000)
+#define CONFIG_SYS_EBC_PB1AP		0x018003c0
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_NAND_ADDR | 0x1e000)
 #endif
 
 /* Memory Bank 2 (FPGA) initialization						*/
-#define CFG_EBC_PB2AP           0x9400C800
-#define CFG_EBC_PB2CR		(CFG_FPGA_BASE | 0x18000)
+#define CONFIG_SYS_EBC_PB2AP           0x9400C800
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA_BASE | 0x18000)
 
-#define CFG_EBC_CFG		0x7FC00000 /*  EBC0_CFG */
+#define CONFIG_SYS_EBC_CFG		0x7FC00000 /*  EBC0_CFG */
 
 /*-----------------------------------------------------------------------
  * GPIO Setup
  *----------------------------------------------------------------------*/
-#define CFG_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
 {											\
 /* GPIO Core 0 */									\
 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0	EBC_DATA_PAR(0)			*/	\
@@ -551,36 +550,36 @@
 /*-----------------------------------------------------------------------
  * Some Kilauea stuff..., mainly fpga registers
  */
-#define CFG_FPGA_REG_BASE		CFG_FPGA_BASE
-#define CFG_FPGA_FIFO_BASE		(in32(CFG_FPGA_BASE) | (1 << 10))
+#define CONFIG_SYS_FPGA_REG_BASE		CONFIG_SYS_FPGA_BASE
+#define CONFIG_SYS_FPGA_FIFO_BASE		(in32(CONFIG_SYS_FPGA_BASE) | (1 << 10))
 
 /* interrupt */
-#define CFG_FPGA_SLIC0_R_DPRAM_INT	0x80000000
-#define CFG_FPGA_SLIC0_W_DPRAM_INT	0x40000000
-#define CFG_FPGA_SLIC1_R_DPRAM_INT	0x20000000
-#define CFG_FPGA_SLIC1_W_DPRAM_INT	0x10000000
-#define CFG_FPGA_PHY0_INT		0x08000000
-#define CFG_FPGA_PHY1_INT		0x04000000
-#define CFG_FPGA_SLIC0_INT		0x02000000
-#define CFG_FPGA_SLIC1_INT		0x01000000
+#define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT	0x80000000
+#define CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT	0x40000000
+#define CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT	0x20000000
+#define CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT	0x10000000
+#define CONFIG_SYS_FPGA_PHY0_INT		0x08000000
+#define CONFIG_SYS_FPGA_PHY1_INT		0x04000000
+#define CONFIG_SYS_FPGA_SLIC0_INT		0x02000000
+#define CONFIG_SYS_FPGA_SLIC1_INT		0x01000000
 
 /* DPRAM setting */
 /* 00: 32B; 01: 64B; 10: 128B; 11: 256B  */
-#define CFG_FPGA_DPRAM_R_INT_LINE	0x00400000	/* 64 B */
-#define CFG_FPGA_DPRAM_W_INT_LINE	0x00100000	/* 64 B */
-#define CFG_FPGA_DPRAM_RW_TYPE		0x00080000
-#define CFG_FPGA_DPRAM_RST		0x00040000
-#define CFG_FPGA_UART0_FO		0x00020000
-#define CFG_FPGA_UART1_FO		0x00010000
+#define CONFIG_SYS_FPGA_DPRAM_R_INT_LINE	0x00400000	/* 64 B */
+#define CONFIG_SYS_FPGA_DPRAM_W_INT_LINE	0x00100000	/* 64 B */
+#define CONFIG_SYS_FPGA_DPRAM_RW_TYPE		0x00080000
+#define CONFIG_SYS_FPGA_DPRAM_RST		0x00040000
+#define CONFIG_SYS_FPGA_UART0_FO		0x00020000
+#define CONFIG_SYS_FPGA_UART1_FO		0x00010000
 
 /* loopback */
-#define CFG_FPGA_CHIPSIDE_LOOPBACK	0x00004000
-#define CFG_FPGA_LINESIDE_LOOPBACK	0x00008000
-#define CFG_FPGA_SLIC0_ENABLE		0x00002000
-#define CFG_FPGA_SLIC1_ENABLE		0x00001000
-#define CFG_FPGA_SLIC0_CS		0x00000800
-#define CFG_FPGA_SLIC1_CS		0x00000400
-#define CFG_FPGA_USER_LED0		0x00000200
-#define CFG_FPGA_USER_LED1		0x00000100
+#define CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK	0x00004000
+#define CONFIG_SYS_FPGA_LINESIDE_LOOPBACK	0x00008000
+#define CONFIG_SYS_FPGA_SLIC0_ENABLE		0x00002000
+#define CONFIG_SYS_FPGA_SLIC1_ENABLE		0x00001000
+#define CONFIG_SYS_FPGA_SLIC0_CS		0x00000800
+#define CONFIG_SYS_FPGA_SLIC1_CS		0x00000400
+#define CONFIG_SYS_FPGA_USER_LED0		0x00000200
+#define CONFIG_SYS_FPGA_USER_LED1		0x00000100
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
new file mode 100644
index 0000000..b86c61d
--- /dev/null
+++ b/include/configs/kmeter1.h
@@ -0,0 +1,457 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *                    Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ *                    Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+#define CONFIG_QE		1 /* Has QE */
+#define CONFIG_MPC83XX		1 /* MPC83XX family */
+#define CONFIG_MPC8360		1 /* MPC8360 CPU specific */
+#define CONFIG_KMETER1		1 /* KMETER1 board specific */
+
+/* include common defines/options for all Keymile boards */
+#include "keymile-common.h"
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN		66000000
+#define CONFIG_SYS_CLK_FREQ		66000000
+#define CONFIG_83XX_PCICLK		66000000
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_CSB_TO_CLKIN_4X1 | \
+	HRCWL_CORE_TO_CSB_2X1 | \
+	HRCWL_CE_PLL_VCO_DIV_2 | \
+	HRCWL_CE_TO_PLL_1X6 )
+
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_CORE_ENABLE | \
+	HRCWH_FROM_0X00000100 | \
+	HRCWH_BOOTSEQ_NORMAL | \
+	HRCWH_SW_WATCHDOG_DISABLE | \
+	HRCWH_ROM_LOC_LOCAL_16BIT | \
+	HRCWH_BIG_ENDIAN | \
+	HRCWH_LDP_CLEAR )
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH		0x00000006
+#define CONFIG_SYS_SICRL		0x00000000
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR		0xE0000000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
+#define CFG_83XX_DDR_USES_CS0
+
+#undef CONFIG_DDR_ECC
+
+/*
+ * DDRCDR - DDR Control Driver Register
+ */
+
+#undef CONFIG_SPD_EEPROM	/* Do not use SPD EEPROM for DDR setup */
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_DDR_II
+#define CONFIG_SYS_DDR_SIZE		256 /* MB */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000000f
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
+					 CSCONFIG_ROW_BIT_13 | \
+					 CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+					 SDRAM_CFG_SREN)
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#define CONFIG_SYS_DDR_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL	((0x100 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+				 (0x406 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_MODE		0x04440242
+#define CONFIG_SYS_DDR_MODE2		0x00800000
+
+#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+				 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+				 (0 << TIMING_CFG0_WWT_SHIFT) | \
+				 (0 << TIMING_CFG0_RRT_SHIFT) | \
+				 (0 << TIMING_CFG0_WRT_SHIFT) | \
+				 (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1	((      TIMING_CFG1_CASLAT_40) | \
+				 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
+				 ( 1 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 ( 2 << TIMING_CFG1_WRREC_SHIFT) | \
+				 ( 2 << TIMING_CFG1_REFREC_SHIFT) | \
+				 ( 2 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 ( 2 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2	((5 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+				 (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+				 (4 << TIMING_CFG2_CPO_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_FLASH_BASE		0xF0000000
+#define CONFIG_SYS_FLASH_BASE_1		0xF2000000
+#define CONFIG_SYS_PIGGY_BASE		0x80000000
+#define CONFIG_SYS_PAXE_BASE		0xA0000000
+#define	CONFIG_SYS_PAXE_SIZE		256
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef	CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4)
+
+/*
+ * Init Local Bus Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Size  Device
+ * ---- ---     ------- ------  -----  ------
+ *  0   Local   GPCM    16 bit  256MB FLASH
+ *  1   Local   GPCM     8 bit  256KB GPIO/PIGGY
+ *  3   Local   GPCM     8 bit  256MB PAXE
+ *
+ */
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#define CONFIG_SYS_FLASH_SIZE		256 /* max FLASH size is 256M */
+#define CONFIG_SYS_FLASH_PROTECTION	1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE /* Window base at flash base */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x8000001b /* 256MB window size */
+
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | \
+				(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+				BR_V)
+
+#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
+				OR_GPCM_SCY_5 | \
+				OR_GPCM_TRLX | OR_GPCM_EAD)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of flash banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 }
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+
+/*
+ * PRIO1/PIGGY on the local bus CS1
+ */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
+#define CONFIG_SYS_LBLAWAR1_PRELIM	0x80000011 /* 256KB window size */
+
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_PIGGY_BASE | \
+				(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
+				BR_V)
+#define CONFIG_SYS_OR1_PRELIM		(0xfffc0000 | /* 256KB */ \
+				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
+				OR_GPCM_SCY_2 | \
+				OR_GPCM_TRLX | OR_GPCM_EAD)
+
+/*
+ * PAXE on the local bus CS3
+ */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_PAXE_BASE /* Window base at flash base */
+#define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000001b /* 256MB window size */
+
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_PAXE_BASE | \
+				(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
+				BR_V)
+#define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
+				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
+				OR_GPCM_SCY_2 | \
+				OR_GPCM_TRLX | OR_GPCM_EAD)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#undef CONFIG_PCI		/* No PCI */
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI	1
+#endif
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME		"FSL UEC0"
+
+#define CONFIG_UEC_ETH1		/* GETH1 */
+#define UEC_VERBOSE_DEBUG	1
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM	3	/* UCC4 */
+#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE	/* not used in RMII Mode */
+#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK17
+#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	0
+#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
+#endif
+
+/*
+ * Environment
+ */
+
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x20000
+#define CONFIG_ENV_OFFSET	(CONFIG_SYS_MONITOR_LEN)
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#else /* CFG_RAMBOOT */
+#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
+#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE		0x2000
+#endif /* CFG_RAMBOOT */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+#if defined(CFG_RAMBOOT)
+#undef CONFIG_CMD_SAVEENV
+#undef CONFIG_CMD_LOADS
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT		0x000000000
+#define CONFIG_SYS_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID2			HID2_HBE
+
+/*
+ * MMU Setup
+ */
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
+				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+
+/* IMMRBAR & PCI IO: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
+				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+
+/* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PIGGY_BASE | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
+				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+
+/* PAXE:  icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PAXE_BASE | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
+				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+
+#ifdef CONFIG_PCI
+/* PCI MEM space: cacheable */
+#define CFG_IBAT6L	(CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U	(CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT6L	CFG_IBAT6L
+#define CFG_DBAT6U	CFG_IBAT6U
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CFG_IBAT7L	(CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
+			 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT7U	(CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT7L	CFG_IBAT7L
+#define CFG_DBAT7U	CFG_IBAT7U
+#else /* CONFIG_PCI */
+#define CONFIG_SYS_IBAT6L	(0)
+#define CONFIG_SYS_IBAT6U	(0)
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+#endif /* CONFIG_PCI */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02 /* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=eth0\0"							\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=ttyS0,${baudrate}\0"				\
+	"fdt_addr=f0080000\0"						\
+	"kernel_addr=f00a0000\0"					\
+	"ramdisk_addr=f03a0000\0"					\
+	"kernel_addr_r=400000\0"					\
+	"fdt_addr_r=800000\0"						\
+	"ramdisk_addr_r=810000\0"					\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_nfs=tftp ${kernel_addr_r} ${boot_file}; "			\
+		"tftp ${fdt_addr_r} ${fdt_file}; "			\
+		"run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"fdt_file=/tftpboot/kmeter1/kmeter1.dtb\0"			\
+	"boot_file=/tftpboot/kmeter1/uImage\0"				\
+	"ramdisk_file=/tftpboot/kmeter1/uRamdisk\0"			\
+	"u-boot=/tftpboot/kmeter1/u-boot.bin\0"				\
+	"loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0"			\
+	"load=tftp $loadaddr ${u-boot}\0"				\
+	"update=protect off " MK_STR(TEXT_BASE) " +$filesize;"		\
+		"erase " MK_STR(TEXT_BASE) " +$filesize;"		\
+		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;"	\
+		"protect on " MK_STR(TEXT_BASE) " +$filesize;"		\
+		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;"	\
+		"setenv filesize;saveenv\0"				\
+	"upd=run load update\0"						\
+	"loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0"		\
+	"loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0"			\
+	"loadkernel=tftp ${kernel_addr_r} ${boot_file}\0"		\
+	"unlock=yes\0"							\
+   ""
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/korat.h b/include/configs/korat.h
index 214cb42..eb2c1d4 100644
--- a/include/configs/korat.h
+++ b/include/configs/korat.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007-2008
+ * (C) Copyright 2007-2009
  * Larry Johnson, lrj@acm.org
  *
  * (C) Copyright 2006-2007
@@ -54,51 +54,51 @@
  * Base addresses -- Note these are effective addresses where the actual
  * resources get mapped (not physical addresses).
  */
-#define CFG_MONITOR_LEN		(384 * 1024) /* Reserve 384 kiB for Monitor  */
-#define CFG_MALLOC_LEN		(256 * 1024) /* Reserve 256 kiB for malloc() */
-
-#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
-#define CFG_FLASH0_SIZE		0x01000000
-#define CFG_FLASH0_ADDR		(-CFG_FLASH0_SIZE)
-#define CFG_FLASH1_TOP		0xF8000000
-#define CFG_FLASH1_MAX_SIZE	0x08000000
-#define CFG_FLASH1_ADDR		(CFG_FLASH1_TOP - CFG_FLASH1_MAX_SIZE)
-#define CFG_FLASH_BASE		CFG_FLASH1_ADDR	/* start of FLASH	*/
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_OCM_BASE		0xe0010000	/* ocm			*/
-#define CFG_OCM_DATA_ADDR	CFG_OCM_BASE
-#define CFG_PCI_BASE		0xe0000000	/* Internal PCI regs	*/
-#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve 384 kiB for Monitor  */
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024) /* Reserve 256 kiB for malloc() */
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CONFIG_SYS_FLASH0_SIZE		0x01000000
+#define CONFIG_SYS_FLASH0_ADDR		(-CONFIG_SYS_FLASH0_SIZE)
+#define CONFIG_SYS_FLASH1_TOP		0xF8000000
+#define CONFIG_SYS_FLASH1_MAX_SIZE	0x08000000
+#define CONFIG_SYS_FLASH1_ADDR		(CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE)
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH1_ADDR	/* start of FLASH	*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_OCM_BASE		0xe0010000	/* ocm			*/
+#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_OCM_BASE
+#define CONFIG_SYS_PCI_BASE		0xe0000000	/* Internal PCI regs	*/
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
 
 /* Don't change either of these */
-#define CFG_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
+#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
 
-#define CFG_USB2D0_BASE		0xe0000100
-#define CFG_USB_DEVICE		0xe0000000
-#define CFG_USB_HOST		0xe0000400
-#define CFG_CPLD_BASE		0xc0000000
+#define CONFIG_SYS_USB2D0_BASE		0xe0000100
+#define CONFIG_SYS_USB_DEVICE		0xe0000000
+#define CONFIG_SYS_USB_HOST		0xe0000400
+#define CONFIG_SYS_CPLD_BASE		0xc0000000
 
 /*
  * Initial RAM & stack pointer
  */
 /* 440EPx has 16KB of internal SRAM, so no need for D-Cache		*/
-#undef CFG_INIT_RAM_DCACHE
-#define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM			*/
-#define CFG_INIT_RAM_END	(4 << 10)
-#define CFG_GBL_DATA_SIZE	256	/* num bytes initial data	*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+#undef CONFIG_SYS_INIT_RAM_DCACHE
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
+#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_SIZE	256	/* num bytes initial data	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_POST_WORD_ADDR
 
 /*
  * Serial Port
  */
-#define CFG_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SERIAL_MULTI	1
 /* define this if you want console on UART1 */
 #undef CONFIG_UART1_CONSOLE
 
-#define CFG_BAUDRATE_TABLE						\
+#define CONFIG_SYS_BAUDRATE_TABLE						\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
 /*
@@ -109,26 +109,26 @@
 /*
  * FLASH related
  */
-#define CFG_FLASH_CFI			/* The flash is CFI compatible	      */
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	      */
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	      */
 #define CONFIG_FLASH_CFI_LEGACY		/* Allow hard-coded config for FLASH0 */
 
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH1_ADDR, CFG_FLASH0_ADDR }
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH1_ADDR, CONFIG_SYS_FLASH0_ADDR }
 
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	      */
-#define CFG_MAX_FLASH_SECT	1024	/* max number of sectors on one chip  */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	      */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* max number of sectors on one chip  */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)    */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)    */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)    */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)    */
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)   */
-#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection      */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)   */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection      */
 
-#define CFG_FLASH_EMPTY_INFO	      /* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash      */
+#define CONFIG_SYS_FLASH_EMPTY_INFO	      /* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash      */
 
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	      */
-#define CONFIG_ENV_ADDR		(CFG_FLASH1_TOP - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH1_TOP - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector   */
 
 /* Address and size of Redundant Environment Sector */
@@ -138,83 +138,100 @@
 /*
  * DDR SDRAM
  */
-#define CFG_MBYTES_SDRAM        (512)	/* 512 MiB	TODO: remove	*/
 #define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization	*/
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup	*/
 #define CONFIG_ZERO_SDRAM		/* Zero SDRAM after setup	*/
 #define CONFIG_DDR_ECC			/* Use ECC when available	*/
 #define SPD_EEPROM_ADDRESS	{0x50}
 #define CONFIG_PROG_SDRAM_TLB
-#define CFG_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
-					/* 440EPx errata CHIP 11	*/
+#define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4 KiB as	*/
+					/* per 440EPx Errata CHIP_11	*/
 
 /*
  * I2C
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 
 /* I2C RTC */
 #define CONFIG_RTC_M41T60	1
-#define CFG_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
 
 /* I2C SYSMON (LM73)							*/
 #define CONFIG_DTT_LM73		1	/* National Semi's LM73		*/
 #define CONFIG_DTT_SENSORS	{2}	/* Sensor addresses		*/
-#define CFG_DTT_MAX_TEMP	70
-#define CFG_DTT_MIN_TEMP	-30
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_MIN_TEMP	-30
 
 #define CONFIG_PREBOOT	"echo;"						\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo Type \\\"run flash_cf\\\" to mount from CompactFlash(R);" \
 	"echo"
 
 #undef	CONFIG_BOOTARGS
 
 /* Setup some board specific values for the default environment variables */
 #define CONFIG_HOSTNAME		korat
-#define CFG_BOOTFILE		"bootfile=/tftpboot/korat/uImage\0"
-#define CFG_ROOTPATH		"rootpath=/opt/eldk/ppc_4xxFP\0"
 
 /* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
 #define CONFIG_EXTRA_ENV_SETTINGS					\
-	CFG_BOOTFILE							\
-	CFG_ROOTPATH							\
+	"u_boot=korat/u-boot.bin\0"					\
+	"load=tftp 200000 ${u_boot}\0"					\
+	"update=protect off F7F60000 F7FBFFFF;erase F7F60000 F7FBFFFF;"	\
+		"cp.b ${fileaddr} F7F60000 ${filesize};protect on "	\
+		"F7F60000 F7FBFFFF\0"					\
+	"upd=run load update\0"						\
+	"bootfile=korat/uImage\0"					\
+	"dtb=korat/korat.dtb\0"						\
+	"kernel_addr=F4000000\0"					\
+	"ramdisk_addr=F4400000\0"					\
+	"dtb_addr=F41E0000\0"						\
+	"udl=tftp 200000 ${bootfile}; erase F4000000 F41DFFFF; "	\
+		"cp.b ${fileaddr} F4000000 ${filesize}\0"		\
+	"udd=tftp 200000 ${dtb}; erase F41E0000 F41FFFFF; "		\
+		"cp.b ${fileaddr} F41E0000 ${filesize}\0"		\
+	"ll=setenv kernel_addr 200000; setenv dtb_addr 1000000; "	\
+		"tftp ${kernel_addr} ${uImage}; tftp ${dtb_addr} "	\
+		"${dtb}\0"						\
+	"rd_size=73728\0"						\
+	"ramargs=setenv bootargs root=/dev/ram rw "			\
+		"ramdisk_size=${rd_size}\0"				\
+	"usbdev=sda1\0"							\
+	"usbargs=setenv bootargs root=/dev/${usbdev} ro rootdelay=10\0"	\
+	"rootpath=/opt/eldk/ppc_4xxFP\0"				\
 	"netdev=eth0\0"							\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"pciclk=33\0"							\
+	"addide=setenv bootargs ${bootargs} ide=reverse "		\
+		"idebus=${pciclk}\0"					\
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
 	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-	        "bootm\0"						\
-	"kernel_addr=F4000000\0"					\
-	"ramdisk_addr=F4400000\0"					\
-	"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"		\
-	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
-		"cp.b 200000 FFFA0000 60000\0"			        \
-	"upd=run load update\0"						\
+	"flash_cf=run usbargs addide addip addtty; "			\
+		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
+	"flash_nfs=run nfsargs addide addip addtty; "			\
+		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
+	"flash_self=run ramargs addip addtty; "				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${dtb_addr}\0"	\
 	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_BOOTCOMMAND	"run flash_cf"
 
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_IBM_EMAC4_V4	1
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		2	/* PHY address, See schematics	*/
@@ -224,7 +241,7 @@
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 
 #define CONFIG_HAS_ETH0
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx	*/
+#define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx	*/
 					/*   buffers & descriptors	*/
 #define CONFIG_NET_MULTI	1
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
@@ -277,47 +294,47 @@
 #define CONFIG_CMD_USB
 
 /* POST support */
-#define CONFIG_POST		(CFG_POST_CACHE	   | \
-				 CFG_POST_CPU	   | \
-				 CFG_POST_ECC	   | \
-				 CFG_POST_ETHER	   | \
-				 CFG_POST_FPU	   | \
-				 CFG_POST_I2C	   | \
-				 CFG_POST_MEMORY   | \
-				 CFG_POST_RTC	   | \
-				 CFG_POST_SPR	   | \
-				 CFG_POST_UART)
-
-#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_POST		(CONFIG_SYS_POST_CACHE	| \
+				 CONFIG_SYS_POST_CPU	| \
+				 CONFIG_SYS_POST_ECC	| \
+				 CONFIG_SYS_POST_ETHER	| \
+				 CONFIG_SYS_POST_FPU	| \
+				 CONFIG_SYS_POST_I2C	| \
+				 CONFIG_SYS_POST_MEMORY	| \
+				 CONFIG_SYS_POST_RTC	| \
+				 CONFIG_SYS_POST_SPR	| \
+				 CONFIG_SYS_POST_UART)
+
+#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 #define CONFIG_LOGBUFFER
-#define CFG_POST_CACHE_ADDR	0xC8000000	/* free virtual address     */
+#define CONFIG_SYS_POST_CACHE_ADDR	0xC8000000	/* free virtual address     */
 
-#define CFG_CONSOLE_IS_IN_ENV	/* Otherwise it catches logbuffer as output */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* Otherwise it catches logbuffer as output */
 
 #define CONFIG_SUPPORT_VFAT
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 					/* Print Buffer Size		*/
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
-#define CFG_EXTBDINFO		1  /* To use extended board_into (bd_t)	*/
+#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
+#define CONFIG_SYS_EXTBDINFO		1  /* To use extended board_into (bd_t)	*/
 
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
+#define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW		1	/* enable loopw command		*/
@@ -328,7 +345,7 @@
 /*
  * Korat-specific options
  */
-#define CFG_KORAT_MAN_RESET_MS	10000	/* timeout for manufacturer reset */
+#define CONFIG_SYS_KORAT_MAN_RESET_MS	10000	/* timeout for manufacturer reset */
 
 /*
  * PCI stuff
@@ -336,50 +353,50 @@
 /* General PCI */
 #define CONFIG_PCI			/* include pci support		*/
 #define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-#define CFG_PCI_CACHE_LINE_SIZE	0	/* to avoid problems with PNP	*/
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	0	/* to avoid problems with PNP	*/
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
-#define CFG_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to	*/
-						/*   CFG_PCI_MEMBASE	*/
+#define CONFIG_SYS_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to	*/
+						/*   CONFIG_SYS_PCI_MEMBASE	*/
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT
-#define CFG_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
 
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
-#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
+#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
 
 /*
  * For booting Linux, the board info and command line data have to be in the
  * first 8 MB of memory, since this is the maximum mapped by the Linux kernel
  * during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*
  * External Bus Controller (EBC) Setup
  */
 
 /* Memory Bank 0 (NOR-FLASH) initialization				*/
-#if CFG_FLASH0_SIZE == 0x01000000
-#define CFG_EBC_PB0AP		0x04017300
-#define CFG_EBC_PB0CR		(CFG_FLASH0_ADDR | 0x0009A000)
-#elif CFG_FLASH0_SIZE == 0x04000000
-#define CFG_EBC_PB0AP		0x04017300
-#define CFG_EBC_PB0CR		(CFG_FLASH0_ADDR | 0x000DA000)
+#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
+#define CONFIG_SYS_EBC_PB0AP		0x04017300
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH0_ADDR | 0x0009A000)
+#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
+#define CONFIG_SYS_EBC_PB0AP		0x04017300
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH0_ADDR | 0x000DA000)
 #else
-#error Unable to configure chip select for current CFG_FLASH0_SIZE
+#error Unable to configure chip select for current CONFIG_SYS_FLASH0_SIZE
 #endif
 
 /* Memory Bank 1 (NOR-FLASH) initialization				*/
-#if CFG_FLASH1_MAX_SIZE == 0x08000000
-#define CFG_EBC_PB1AP		0x04017300
-#define CFG_EBC_PB1CR		(CFG_FLASH1_ADDR | 0x000FA000)
+#if CONFIG_SYS_FLASH1_MAX_SIZE == 0x08000000
+#define CONFIG_SYS_EBC_PB1AP		0x04017300
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_FLASH1_ADDR | 0x000FA000)
 #else
-#error Unable to configure chip select for current CFG_FLASH1_MAX_SIZE
+#error Unable to configure chip select for current CONFIG_SYS_FLASH1_MAX_SIZE
 #endif
 
 /* Memory Bank 2 (CPLD) initialization					*/
-#define CFG_EBC_PB2AP		0x04017300
-#define CFG_EBC_PB2CR		(CFG_CPLD_BASE | 0x00038000)
+#define CONFIG_SYS_EBC_PB2AP		0x04017300
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_CPLD_BASE | 0x00038000)
 
 /*
  * GPIO Setup
@@ -402,7 +419,7 @@
  * GPIO10  Alt1   O    x   PerCS5 to expansion bus connector
  * GPIO11  Alt1   I    x   PerErr
  * GPIO12  GPIO   O    0   ATMega !Reset
- * GPIO13  GPIO   O    1   SPI Atmega !SS
+ * GPIO13  GPIO   x    x   Test Point 2 (TP2)
  * GPIO14  GPIO   O    1   Write protect EEPROM #1 (0xA8)
  * GPIO15  GPIO   O    0   CPU Run LED !On
  * GPIO16  Alt1   O    x   GMC1TxD0
@@ -446,22 +463,22 @@
  * GPIO63  xxxx   x    x   (reserved for trace port)
  */
 
-#define CFG_GPIO_ATMEGA_RESET_	12
-#define CFG_GPIO_ATMEGA_SS_	13
-#define CFG_GPIO_PHY0_FIBER_SEL	27
-#define CFG_GPIO_PHY1_FIBER_SEL	28
-#define CFG_GPIO_SFP0_PRESENT_	30
-#define CFG_GPIO_SFP1_PRESENT_	31
-#define CFG_GPIO_SFP0_TX_EN_	32
-#define CFG_GPIO_SFP1_TX_EN_	33
-#define CFG_GPIO_PHY0_EN	45
-#define CFG_GPIO_PHY1_EN	46
-#define CFG_GPIO_RESET_PRESSED_	47
+#define CONFIG_SYS_GPIO_ATMEGA_RESET_	12
+#define CONFIG_SYS_GPIO_ATMEGA_SS_	13
+#define CONFIG_SYS_GPIO_PHY0_FIBER_SEL	27
+#define CONFIG_SYS_GPIO_PHY1_FIBER_SEL	28
+#define CONFIG_SYS_GPIO_SFP0_PRESENT_	30
+#define CONFIG_SYS_GPIO_SFP1_PRESENT_	31
+#define CONFIG_SYS_GPIO_SFP0_TX_EN_	32
+#define CONFIG_SYS_GPIO_SFP1_TX_EN_	33
+#define CONFIG_SYS_GPIO_PHY0_EN	45
+#define CONFIG_SYS_GPIO_PHY1_EN	46
+#define CONFIG_SYS_GPIO_RESET_PRESSED_	47
 
 /*
  * PPC440 GPIO Configuration
  */
-#define CFG_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
 {											\
 /* GPIO Core 0 */									\
 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
@@ -477,7 +494,7 @@
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)			*/	\
 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR			*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO13				*/	\
+{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO13				*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14				*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15				*/	\
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4)			*/	\
diff --git a/include/configs/kvme080.h b/include/configs/kvme080.h
index 098b92b..0d95263 100644
--- a/include/configs/kvme080.h
+++ b/include/configs/kvme080.h
@@ -56,7 +56,7 @@
 #define CONFIG_MISC_INIT_R
 
 #define CONFIG_LOADS_ECHO	1
-#undef	CFG_LOADS_BAUD_CHANGE
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
 
 #undef	CONFIG_WATCHDOG
 
@@ -99,75 +99,75 @@
 
 #define CONFIG_NETCONSOLE
 
-#define CFG_LONGHELP
-#define CFG_PROMPT		"=> "
-#define CFG_CBSIZE		256
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS		16
-#define CFG_BARGSIZE		CFG_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
-#define CFG_MEMTEST_START	0x00400000
-#define CFG_MEMTEST_END		0x07C00000
+#define CONFIG_SYS_MEMTEST_START	0x00400000
+#define CONFIG_SYS_MEMTEST_END		0x07C00000
 
-#define CFG_LOAD_ADDR		0x00100000
-#define CFG_HZ			1000
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
+#define CONFIG_SYS_HZ			1000
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define CFG_INIT_RAM_ADDR	0x40000000
-#define CFG_INIT_RAM_END	0x1000
-#define CFG_GBL_DATA_SIZE	128
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x7C000000
-#define CFG_EUMB_ADDR		0xFC000000
-#define CFG_NVRAM_BASE_ADDR	0xFF000000
-#define CFG_NS16550_COM1	0xFF080000
-#define CFG_NS16550_COM2	0xFF080010
-#define CFG_NS16550_COM3	0xFF080020
-#define CFG_NS16550_COM4	0xFF080030
-#define CFG_RESET_ADDRESS	0xFFF00100
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x7C000000
+#define CONFIG_SYS_EUMB_ADDR		0xFC000000
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xFF000000
+#define CONFIG_SYS_NS16550_COM1	0xFF080000
+#define CONFIG_SYS_NS16550_COM2	0xFF080010
+#define CONFIG_SYS_NS16550_COM3	0xFF080020
+#define CONFIG_SYS_NS16550_COM4	0xFF080030
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
 
-#define CFG_MAX_RAM_SIZE	0x20000000
-#define CFG_FLASH_SIZE		(16 * 1024 * 1024)
-#define CFG_NVRAM_SIZE		0x7FFF8
+#define CONFIG_SYS_MAX_RAM_SIZE	0x20000000
+#define CONFIG_SYS_FLASH_SIZE		(16 * 1024 * 1024)
+#define CONFIG_SYS_NVRAM_SIZE		0x7FFF8
 
 #define CONFIG_VERY_BIG_RAM
 
-#define CFG_MONITOR_LEN		0x00040000
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MALLOC_LEN		(512 << 10)
+#define CONFIG_SYS_MONITOR_LEN		0x00040000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
 
-#define CFG_BOOTMAPSZ		(8 << 20)
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
 
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_USE_BUFFER_WRITE
-#define CFG_FLASH_PROTECTION
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_PROTECT_CLEAR
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_PROTECT_CLEAR
 
-#define CFG_MAX_FLASH_BANKS	1
-#define CFG_MAX_FLASH_SECT	256
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
 
-#define CFG_FLASH_ERASE_TOUT	120000
-#define CFG_FLASH_WRITE_TOUT	500
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
 
-#define CFG_JFFS2_FIRST_BANK	0
-#define CFG_JFFS2_NUM_BANKS	1
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
 
 #define CONFIG_ENV_IS_IN_NVRAM	1
 #define CONFIG_ENV_OVERWRITE	1
-#define CFG_NVRAM_ACCESS_ROUTINE
-#define CONFIG_ENV_ADDR		CFG_NVRAM_BASE_ADDR
+#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE
+#define CONFIG_ENV_ADDR		CONFIG_SYS_NVRAM_BASE_ADDR
 #define CONFIG_ENV_SIZE		0x400
 #define CONFIG_ENV_OFFSET		0
 
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		14745600
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		14745600
 
 #define CONFIG_PCI
 #define CONFIG_PCI_PNP
@@ -176,97 +176,97 @@
 #define CONFIG_EEPRO100
 #define CONFIG_EEPRO100_SROM_WRITE
 
-#define CFG_RX_ETH_BUFFER	8
+#define CONFIG_SYS_RX_ETH_BUFFER	8
 
 #define CONFIG_HARD_I2C		1
-#define CFG_I2C_SPEED		400000
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR		0x57
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 
 #define CONFIG_SYS_CLK_FREQ	33333333
 
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SIZE	32
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5
+#  define CONFIG_SYS_CACHELINE_SHIFT	5
 #endif
 
-#define CFG_DLL_EXTEND		0x00
-#define CFG_PCI_HOLD_DEL	0x20
-
-#define CFG_ROMNAL		15
-#define CFG_ROMFAL		31
-
-#define CFG_REFINT		430
-
-#define CFG_DBUS_SIZE2		1
-
-#define CFG_BSTOPRE		121
-#define CFG_REFREC		8
-#define CFG_RDLAT		4
-#define CFG_PRETOACT		3
-#define CFG_ACTTOPRE		5
-#define CFG_ACTORW		3
-#define CFG_SDMODE_CAS_LAT	3
-#define CFG_SDMODE_WRAP		0
-
-#define CFG_REGISTERD_TYPE_BUFFER	1
-#define CFG_EXTROM			1
-#define CFG_REGDIMM			0
-
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		(0x4000000 - 1)
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x04000000
-#define CFG_BANK1_END		(0x8000000 - 1)
-#define CFG_BANK1_ENABLE	1
-#define CFG_BANK2_START		0x3ff00000
-#define CFG_BANK2_END		0x3fffffff
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x3ff00000
-#define CFG_BANK3_END		0x3fffffff
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x00000000
-#define CFG_BANK4_END		0x00000000
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x00000000
-#define CFG_BANK5_END		0x00000000
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x00000000
-#define CFG_BANK6_END		0x00000000
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x00000000
-#define CFG_BANK7_END		0x00000000
-#define CFG_BANK7_ENABLE	0
-
-#define CFG_BANK_ENABLE		0x03
-
-#define CFG_ODCR		0x75
-#define CFG_PGMAX		0x32
-
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_DLL_EXTEND		0x00
+#define CONFIG_SYS_PCI_HOLD_DEL	0x20
+
+#define CONFIG_SYS_ROMNAL		15
+#define CONFIG_SYS_ROMFAL		31
+
+#define CONFIG_SYS_REFINT		430
+
+#define CONFIG_SYS_DBUS_SIZE2		1
+
+#define CONFIG_SYS_BSTOPRE		121
+#define CONFIG_SYS_REFREC		8
+#define CONFIG_SYS_RDLAT		4
+#define CONFIG_SYS_PRETOACT		3
+#define CONFIG_SYS_ACTTOPRE		5
+#define CONFIG_SYS_ACTORW		3
+#define CONFIG_SYS_SDMODE_CAS_LAT	3
+#define CONFIG_SYS_SDMODE_WRAP		0
+
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER	1
+#define CONFIG_SYS_EXTROM			1
+#define CONFIG_SYS_REGDIMM			0
+
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		(0x4000000 - 1)
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x04000000
+#define CONFIG_SYS_BANK1_END		(0x8000000 - 1)
+#define CONFIG_SYS_BANK1_ENABLE	1
+#define CONFIG_SYS_BANK2_START		0x3ff00000
+#define CONFIG_SYS_BANK2_END		0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x3ff00000
+#define CONFIG_SYS_BANK3_END		0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x00000000
+#define CONFIG_SYS_BANK4_END		0x00000000
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x00000000
+#define CONFIG_SYS_BANK5_END		0x00000000
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x00000000
+#define CONFIG_SYS_BANK6_END		0x00000000
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x00000000
+#define CONFIG_SYS_BANK7_END		0x00000000
+#define CONFIG_SYS_BANK7_ENABLE	0
+
+#define CONFIG_SYS_BANK_ENABLE		0x03
+
+#define CONFIG_SYS_ODCR		0x75
+#define CONFIG_SYS_PGMAX		0x32
+
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 #define BOOTFLAG_COLD	0x01
 #define BOOTFLAG_WARM	0x02
diff --git a/include/configs/lart.h b/include/configs/lart.h
index d7b8cfc..38b8e75 100644
--- a/include/configs/lart.h
+++ b/include/configs/lart.h
@@ -39,8 +39,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -92,25 +92,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"LART # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"LART # "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0xc0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0xc8000000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0xc8000000	/* default load address	*/
 
-#define	CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x0b		/* set core clock to 220 MHz */
+#define	CONFIG_SYS_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_CPUSPEED		0x0b		/* set core clock to 220 MHz */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -140,17 +140,17 @@
 #define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
 #define PHYS_FLASH_SIZE		0x00400000 /* 4 MB */
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	(31+8)	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	(31+8)	/* max number of sectors on one chip	*/
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x1C000)	/* Addr of Environment Sector	*/
diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h
index be2f71c..2feb3ae 100644
--- a/include/configs/linkstation.h
+++ b/include/configs/linkstation.h
@@ -106,20 +106,20 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 
-#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS		16		/* Max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR		0x00800000	/* Default load address: 8 MB	*/
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16		/* Max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR		0x00800000	/* Default load address: 8 MB	*/
 
 #define CONFIG_BOOTCOMMAND	"run bootcmd1"
 #define CONFIG_BOOTARGS		"root=/dev/sda1 console=ttyS1,57600 netconsole=@192.168.1.7/eth0,@192.168.1.1/00:50:BF:A4:59:71 rtc-rs5c372.probe=0,0x32 debug"
 #define CONFIG_NFSBOOTCOMMAND	"bootp;run nfsargs;bootm"
 
-#define CFG_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
 #define XMK_STR(x)		#x
 #define MK_STR(x)		XMK_STR(x)
@@ -213,30 +213,30 @@
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
 
-#define CFG_FLASH_BASE		0xFFC00000
-#define CFG_FLASH_SIZE		0x00400000
-#define CFG_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_FLASH_BASE		0xFFC00000
+#define CONFIG_SYS_FLASH_SIZE		0x00400000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 
-#define CFG_RESET_ADDRESS	0xFFF00100
-#define CFG_EUMB_ADDR		0x80000000
-#define CFG_PCI_MEM_ADDR	0xB0000000
-#define CFG_MISC_REGION_ADDR	0xFE000000
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
+#define CONFIG_SYS_EUMB_ADDR		0x80000000
+#define CONFIG_SYS_PCI_MEM_ADDR	0xB0000000
+#define CONFIG_SYS_MISC_REGION_ADDR	0xFE000000
 
-#define CFG_MONITOR_LEN		0x00040000	/* 256 kB			*/
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve some kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_LEN		0x00040000	/* 256 kB			*/
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve some kB for malloc()	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x00800000	/* 1M ... 8M in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x00800000	/* 1M ... 8M in DRAM		*/
 
 /* Maximum amount of RAM */
 #if defined(CONFIG_HLAN) || defined(CONFIG_LAN)
-#define CFG_MAX_RAM_SIZE	0x04000000	/* 64MB of SDRAM  */
+#define CONFIG_SYS_MAX_RAM_SIZE	0x04000000	/* 64MB of SDRAM  */
 #elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
-#define CFG_MAX_RAM_SIZE	0x08000000	/* 128MB of SDRAM */
+#define CONFIG_SYS_MAX_RAM_SIZE	0x08000000	/* 128MB of SDRAM */
 #else
 #error Unknown LinkStation type
 #endif
@@ -249,38 +249,38 @@
  *
  * Always do "make clean" after changing the build type
  */
-#if CFG_MONITOR_BASE < CFG_FLASH_BASE
-#define CFG_RAMBOOT
+#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_RAMBOOT
 #endif
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area
  */
 #if 1 /* RAM is available when the first C function is called */
-#define CFG_INIT_RAM_ADDR	(CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE - 0x1000)
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE - 0x1000)
 #else
-#define CFG_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
 #endif
-#define CFG_INIT_RAM_END	0x1000
-#define CFG_GBL_DATA_SIZE	128
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_END	0x1000
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 /*----------------------------------------------------------------------
  * Serial configuration
  */
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		57600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
 
-#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_REG_SIZE	1
 
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4600)	/* Console port	*/
-#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4500)	/* AVR port	*/
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_EUMB_ADDR + 0x4600)	/* Console port	*/
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4500)	/* AVR port	*/
 
 /*
  * Low Level Configuration Settings
@@ -300,54 +300,54 @@
 /* FIXME: 32.768 MHz is the crystal frequency but */
 /* the real frequency is lower by about 0.75%     */
 #define CONFIG_SYS_CLK_FREQ	32768000
-#define CFG_HZ			1000
+#define CONFIG_SYS_HZ			1000
 
 /* Bit-field values for MCCR1.  */
-#define CFG_ROMNAL      0
-#define CFG_ROMFAL      11
-
-#define CFG_BANK0_ROW	2       /* Only bank 0 used: 13 x n x 4 */
-#define CFG_BANK1_ROW	0
-#define CFG_BANK2_ROW	0
-#define CFG_BANK3_ROW	0
-#define CFG_BANK4_ROW	0
-#define CFG_BANK5_ROW	0
-#define CFG_BANK6_ROW	0
-#define CFG_BANK7_ROW	0
+#define CONFIG_SYS_ROMNAL      0
+#define CONFIG_SYS_ROMFAL      11
+
+#define CONFIG_SYS_BANK0_ROW	2       /* Only bank 0 used: 13 x n x 4 */
+#define CONFIG_SYS_BANK1_ROW	0
+#define CONFIG_SYS_BANK2_ROW	0
+#define CONFIG_SYS_BANK3_ROW	0
+#define CONFIG_SYS_BANK4_ROW	0
+#define CONFIG_SYS_BANK5_ROW	0
+#define CONFIG_SYS_BANK6_ROW	0
+#define CONFIG_SYS_BANK7_ROW	0
 
 /* Bit-field values for MCCR2.  */
-#define CFG_TSWAIT      0
+#define CONFIG_SYS_TSWAIT      0
 #if defined(CONFIG_LAN) || defined(CONFIG_HLAN)
-#define CFG_REFINT      0x15e0
+#define CONFIG_SYS_REFINT      0x15e0
 #elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
-#define CFG_REFINT      0x1580
+#define CONFIG_SYS_REFINT      0x1580
 #endif
 
 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
-#define CFG_BSTOPRE	0x91c
+#define CONFIG_SYS_BSTOPRE	0x91c
 
 /* Bit-field values for MCCR3.  */
-#define CFG_REFREC      7
+#define CONFIG_SYS_REFREC      7
 
 /* Bit-field values for MCCR4.  */
-#define CFG_PRETOACT		2
-#define CFG_ACTTOPRE		2	/* Original value was 2	*/
-#define CFG_ACTORW		2
+#define CONFIG_SYS_PRETOACT		2
+#define CONFIG_SYS_ACTTOPRE		2	/* Original value was 2	*/
+#define CONFIG_SYS_ACTORW		2
 #if defined(CONFIG_LAN) || defined(CONFIG_HLAN)
-#define CFG_SDMODE_CAS_LAT	2	/* For 100MHz bus	*/
-/*#define CFG_SDMODE_BURSTLEN	3*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	2	/* For 100MHz bus	*/
+/*#define CONFIG_SYS_SDMODE_BURSTLEN	3*/
 #elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
-#define CFG_SDMODE_CAS_LAT	3	/* For 133MHz bus	*/
-/*#define CFG_SDMODE_BURSTLEN	2*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* For 133MHz bus	*/
+/*#define CONFIG_SYS_SDMODE_BURSTLEN	2*/
 #endif
-#define CFG_REGISTERD_TYPE_BUFFER 1
-#define CFG_EXTROM		1	/* Original setting but there is no EXTROM */
-#define CFG_REGDIMM		0
-#define CFG_DBUS_SIZE2		1
-#define CFG_SDMODE_WRAP		0
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
+#define CONFIG_SYS_EXTROM		1	/* Original setting but there is no EXTROM */
+#define CONFIG_SYS_REGDIMM		0
+#define CONFIG_SYS_DBUS_SIZE2		1
+#define CONFIG_SYS_SDMODE_WRAP		0
 
-#define CFG_PGMAX		0x32	/* All boards use this setting. Original 0x92 */
-#define CFG_SDRAM_DSCD		0x30
+#define CONFIG_SYS_PGMAX		0x32	/* All boards use this setting. Original 0x92 */
+#define CONFIG_SYS_SDRAM_DSCD		0x30
 
 /* Memory bank settings.
  * Only bits 20-29 are actually used from these vales to set the
@@ -356,32 +356,32 @@
  * address. Refer to the MPC8240 book.
  */
 
-#define CFG_BANK0_START	    0x00000000
-#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START     0x3ff00000
-#define CFG_BANK1_END       0x3fffffff
-#define CFG_BANK1_ENABLE    0
-#define CFG_BANK2_START     0x3ff00000
-#define CFG_BANK2_END       0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START     0x3ff00000
-#define CFG_BANK3_END       0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START     0x3ff00000
-#define CFG_BANK4_END       0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START     0x3ff00000
-#define CFG_BANK5_END       0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START     0x3ff00000
-#define CFG_BANK6_END       0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START     0x3ff00000
-#define CFG_BANK7_END       0x3fffffff
-#define CFG_BANK7_ENABLE    0
-
-#define CFG_ODCR	    0x15
+#define CONFIG_SYS_BANK0_START	    0x00000000
+#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE    1
+#define CONFIG_SYS_BANK1_START     0x3ff00000
+#define CONFIG_SYS_BANK1_END       0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE    0
+#define CONFIG_SYS_BANK2_START     0x3ff00000
+#define CONFIG_SYS_BANK2_END       0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE    0
+#define CONFIG_SYS_BANK3_START     0x3ff00000
+#define CONFIG_SYS_BANK3_END       0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE    0
+#define CONFIG_SYS_BANK4_START     0x3ff00000
+#define CONFIG_SYS_BANK4_END       0x3fffffff
+#define CONFIG_SYS_BANK4_ENABLE    0
+#define CONFIG_SYS_BANK5_START     0x3ff00000
+#define CONFIG_SYS_BANK5_END       0x3fffffff
+#define CONFIG_SYS_BANK5_ENABLE    0
+#define CONFIG_SYS_BANK6_START     0x3ff00000
+#define CONFIG_SYS_BANK6_END       0x3fffffff
+#define CONFIG_SYS_BANK6_ENABLE    0
+#define CONFIG_SYS_BANK7_START     0x3ff00000
+#define CONFIG_SYS_BANK7_END       0x3fffffff
+#define CONFIG_SYS_BANK7_ENABLE    0
+
+#define CONFIG_SYS_ODCR	    0x15
 
 /*----------------------------------------------------------------------
  * Initial BAT mappings
@@ -393,32 +393,32 @@
  */
 
 /* SDRAM */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
 
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 
 /* EUMB: 1MB of address space */
-#define CFG_IBAT1L	(CFG_EUMB_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT1U	(CFG_EUMB_ADDR | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_EUMB_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_EUMB_ADDR | BATU_BL_1M | BATU_VS | BATU_VP)
 
-#define CFG_DBAT1L	(CFG_IBAT1L | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT1U	CFG_IBAT1U
+#define CONFIG_SYS_DBAT1L	(CONFIG_SYS_IBAT1L | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 
 /* PCI Mem: 256MB of address space */
-#define CFG_IBAT2L	(CFG_PCI_MEM_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	(CFG_PCI_MEM_ADDR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI_MEM_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI_MEM_ADDR | BATU_BL_256M | BATU_VS | BATU_VP)
 
-#define CFG_DBAT2L	(CFG_IBAT2L | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U	CFG_IBAT2U
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_IBAT2L | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 
 /* PCI and local ROM/Flash: last 32MB of address space */
-#define CFG_IBAT3L	(CFG_MISC_REGION_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(CFG_MISC_REGION_ADDR | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_MISC_REGION_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_MISC_REGION_ADDR | BATU_BL_32M | BATU_VS | BATU_VP)
 
-#define CFG_DBAT3L	(CFG_IBAT3L | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_IBAT3L | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
@@ -428,26 +428,26 @@
  * FIXME: This doesn't appear to be true for the newer kernels
  * which map more that 8 MB
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_FLASH_CFI			/* The flash is CFI compatible	*/
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
 
-#undef  CFG_FLASH_PROTECTION
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
-#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT	72	/* Max number of sectors per flash	*/
+#undef  CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	72	/* Max number of sectors per flash	*/
 
-#define CFG_FLASH_ERASE_TOUT	12000
-#define CFG_FLASH_WRITE_TOUT	1000
+#define CONFIG_SYS_FLASH_ERASE_TOUT	12000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
 
 #define CONFIG_ENV_IS_IN_FLASH
 /*
@@ -463,9 +463,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SIZE	32
 #ifdef CONFIG_CMD_KGDB
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -477,20 +477,20 @@
 #define CONFIG_LBA48				/* 48 bit LBA supported		*/
 
 #if defined(CONFIG_LAN) || defined(CONFIG_HLAN) || defined(CONFIG_HGLAN)
-#define CFG_IDE_MAXBUS		1		/* Scan only 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1		/* Only 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1		/* Scan only 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1		/* Only 1 drive per IDE bus	*/
 #elif defined(CONFIG_HGTL)
-#define CFG_IDE_MAXBUS		2		/* Max. 2 IDE busses		*/
-#define CFG_IDE_MAXDEVICE	2		/* max. 2 drives per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		2		/* Max. 2 IDE busses		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2		/* max. 2 drives per IDE bus	*/
 #else
 #error Config IDE: Unknown LinkStation type
 #endif
 
-#define CFG_ATA_BASE_ADDR	0
+#define CONFIG_SYS_ATA_BASE_ADDR	0
 
-#define CFG_ATA_DATA_OFFSET	0		/* Offset for data I/O		*/
-#define CFG_ATA_REG_OFFSET	0		/* Offset for normal registers	*/
-#define CFG_ATA_ALT_OFFSET	0		/* Offset for alternate registers */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0		/* Offset for data I/O		*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0		/* Offset for normal registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0		/* Offset for alternate registers */
 
 /*-----------------------------------------------------------------------
  * Partitions and file system
diff --git a/include/configs/logodl.h b/include/configs/logodl.h
index dcbae97..cd105da 100644
--- a/include/configs/logodl.h
+++ b/include/configs/logodl.h
@@ -69,7 +69,7 @@
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_ECHO
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_RUN
@@ -96,35 +96,35 @@
  * used for the RAM copy of the uboot code
  *
  */
-#define CFG_MALLOC_LEN		(256*1024)
+#define CONFIG_SYS_MALLOC_LEN		(256*1024)
 
-#define CFG_LONGHELP				/* undef to save memory         */
-#define CFG_PROMPT		"uboot> "	/* Monitor Command Prompt       */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size      */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory         */
+#define CONFIG_SYS_PROMPT		"uboot> "	/* Monitor Command Prompt       */
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size      */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START	0x08000000      /* memtest works on             */
-#define CFG_MEMTEST_END         0x0800ffff	/* 64 KiB                       */
+#define CONFIG_SYS_MEMTEST_START	0x08000000      /* memtest works on             */
+#define CONFIG_SYS_MEMTEST_END         0x0800ffff	/* 64 KiB                       */
 
-#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR           0x08000000      /* load kernel to this address   */
+#define CONFIG_SYS_LOAD_ADDR           0x08000000      /* load kernel to this address   */
 
-#define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ			1000
 						/* RS: the oscillator is actually 3680130?? */
 
-#define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
+#define CONFIG_SYS_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
 						/* 0101000001 */
 						/*      ^^^^^ Memory Speed 99.53 MHz         */
 						/*    ^^      Run Mode Speed = 2x Mem Speed  */
 						/* ^^         Turbo Mode Sp. = 1x Run M. Sp. */
 
-#define CFG_MONITOR_LEN		0x20000		/* 128 KiB */
+#define CONFIG_SYS_MONITOR_LEN		0x20000		/* 128 KiB */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * SMSC91C111 Network Card
@@ -160,10 +160,10 @@
 #define PHYS_FLASH_2		0x01000000	/* Flash Bank #2            */
 #define PHYS_FLASH_SIZE		(32*1024*1024)	/* 32 MB                    */
 
-#define CFG_DRAM_BASE		PHYS_SDRAM_1	/* RAM starts here          */
-#define CFG_DRAM_SIZE		PHYS_SDRAM_1_SIZE
+#define CONFIG_SYS_DRAM_BASE		PHYS_SDRAM_1	/* RAM starts here          */
+#define CONFIG_SYS_DRAM_SIZE		PHYS_SDRAM_1_SIZE
 
-#define CFG_FLASH_BASE          PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
 
 /*
@@ -213,53 +213,53 @@
 #define _BIT31      0x80000000
 
 
-#define CFG_LED_A_BIT           (_BIT18)
-#define CFG_LED_A_SR            GPSR0
-#define CFG_LED_A_CR            GPCR0
+#define CONFIG_SYS_LED_A_BIT           (_BIT18)
+#define CONFIG_SYS_LED_A_SR            GPSR0
+#define CONFIG_SYS_LED_A_CR            GPCR0
 
-#define CFG_LED_B_BIT           (_BIT16)
-#define CFG_LED_B_SR            GPSR1
-#define CFG_LED_B_CR            GPCR1
+#define CONFIG_SYS_LED_B_BIT           (_BIT16)
+#define CONFIG_SYS_LED_B_SR            GPSR1
+#define CONFIG_SYS_LED_B_CR            GPCR1
 
 
 /* LED A: off, LED B: off */
-#define CFG_GPSR0_VAL       (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT18)
-#define CFG_GPSR1_VAL       (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25  +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
-#define CFG_GPSR2_VAL       (_BIT14+_BIT15+_BIT16)
+#define CONFIG_SYS_GPSR0_VAL       (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT18)
+#define CONFIG_SYS_GPSR1_VAL       (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25  +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
+#define CONFIG_SYS_GPSR2_VAL       (_BIT14+_BIT15+_BIT16)
 
-#define CFG_GPCR0_VAL       0x00000000
-#define CFG_GPCR1_VAL       0x00000000
-#define CFG_GPCR2_VAL       0x00000000
+#define CONFIG_SYS_GPCR0_VAL       0x00000000
+#define CONFIG_SYS_GPCR1_VAL       0x00000000
+#define CONFIG_SYS_GPCR2_VAL       0x00000000
 
-#define CFG_GPDR0_VAL       (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT17+_BIT18)
-#define CFG_GPDR1_VAL       (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25  +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
-#define CFG_GPDR2_VAL       (_BIT14+_BIT15+_BIT16)
+#define CONFIG_SYS_GPDR0_VAL       (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT17+_BIT18)
+#define CONFIG_SYS_GPDR1_VAL       (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25  +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
+#define CONFIG_SYS_GPDR2_VAL       (_BIT14+_BIT15+_BIT16)
 
-#define CFG_GAFR0_L_VAL     (_BIT22+_BIT24+_BIT31)
-#define CFG_GAFR0_U_VAL     (_BIT15+_BIT17+_BIT19+\
+#define CONFIG_SYS_GAFR0_L_VAL     (_BIT22+_BIT24+_BIT31)
+#define CONFIG_SYS_GAFR0_U_VAL     (_BIT15+_BIT17+_BIT19+\
 			     _BIT20+_BIT22+_BIT24+_BIT26+_BIT29+_BIT31)
-#define CFG_GAFR1_L_VAL     (_BIT3+_BIT4+_BIT6+_BIT8+_BIT10+_BIT12+_BIT15+_BIT17+_BIT19+\
+#define CONFIG_SYS_GAFR1_L_VAL     (_BIT3+_BIT4+_BIT6+_BIT8+_BIT10+_BIT12+_BIT15+_BIT17+_BIT19+\
 			     _BIT20+_BIT23+_BIT24+_BIT27+_BIT28+_BIT31)
-#define CFG_GAFR1_U_VAL     (_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
-#define CFG_GAFR2_L_VAL     (_BIT1+_BIT3+_BIT5+_BIT7+_BIT9+_BIT11+_BIT13+_BIT15+_BIT17+\
+#define CONFIG_SYS_GAFR1_U_VAL     (_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
+#define CONFIG_SYS_GAFR2_L_VAL     (_BIT1+_BIT3+_BIT5+_BIT7+_BIT9+_BIT11+_BIT13+_BIT15+_BIT17+\
 			     _BIT19+_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
-#define CFG_GAFR2_U_VAL     (_BIT1)
+#define CONFIG_SYS_GAFR2_U_VAL     (_BIT1)
 
-#define CFG_PSSR_VAL        (0x20)
+#define CONFIG_SYS_PSSR_VAL        (0x20)
 
 /*
  * Memory settings
  */
-#define CFG_MSC0_VAL	0x123c2980
-#define CFG_MSC1_VAL	0x123c2661
-#define CFG_MSC2_VAL	0x7ff87ff8
+#define CONFIG_SYS_MSC0_VAL	0x123c2980
+#define CONFIG_SYS_MSC1_VAL	0x123c2661
+#define CONFIG_SYS_MSC2_VAL	0x7ff87ff8
 
 
 /* no sdram/pcmcia here */
-#define CFG_MDCNFG_VAL		0x00000000
-#define CFG_MDREFR_VAL		0x00000000
-#define CFG_MDREFR_VAL_100	0x00000000
-#define CFG_MDMRS_VAL		0x00000000
+#define CONFIG_SYS_MDCNFG_VAL		0x00000000
+#define CONFIG_SYS_MDREFR_VAL		0x00000000
+#define CONFIG_SYS_MDREFR_VAL_100	0x00000000
+#define CONFIG_SYS_MDMRS_VAL		0x00000000
 
 /* only SRAM */
 #define SXCNFG_SETTINGS	0x00000000
@@ -268,24 +268,24 @@
  * PCMCIA and CF Interfaces
  */
 
-#define CFG_MECR_VAL        0x00000000
-#define CFG_MCMEM0_VAL      0x00010504
-#define CFG_MCMEM1_VAL      0x00010504
-#define CFG_MCATT0_VAL      0x00010504
-#define CFG_MCATT1_VAL      0x00010504
-#define CFG_MCIO0_VAL       0x00004715
-#define CFG_MCIO1_VAL       0x00004715
+#define CONFIG_SYS_MECR_VAL        0x00000000
+#define CONFIG_SYS_MCMEM0_VAL      0x00010504
+#define CONFIG_SYS_MCMEM1_VAL      0x00010504
+#define CONFIG_SYS_MCATT0_VAL      0x00010504
+#define CONFIG_SYS_MCATT1_VAL      0x00010504
+#define CONFIG_SYS_MCIO0_VAL       0x00004715
+#define CONFIG_SYS_MCIO1_VAL       0x00004715
 
 
 /*
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
-#define CFG_MAX_FLASH_SECT      128  /* max number of sectors on one chip    */
+#define CONFIG_SYS_MAX_FLASH_BANKS     2       /* max number of memory banks           */
+#define CONFIG_SYS_MAX_FLASH_SECT      128  /* max number of sectors on one chip    */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 /* FIXME */
 #define	CONFIG_ENV_IS_IN_FLASH	1
diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h
index 3d173d7..563d35b 100644
--- a/include/configs/lpc2292sodimm.h
+++ b/include/configs/lpc2292sodimm.h
@@ -49,8 +49,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -96,26 +96,26 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"LPC2292SODIMM # " /* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"LPC2292SODIMM # " /* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x40000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x40000000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x40000000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x40000000	/* 4 ... 8 MB in DRAM	*/
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0x00040000	/* default load address	for	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x00040000	/* default load address	for	*/
 						/* armadillo: kernel img is here*/
 
-#define CFG_SYS_CLK_FREQ	58982400	/* Hz */
-#define	CFG_HZ			2048		/* decrementer freq in Hz */
+#define CONFIG_SYS_SYS_CLK_FREQ	58982400	/* Hz */
+#define	CONFIG_SYS_HZ			2048		/* decrementer freq in Hz */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -138,17 +138,17 @@
 #define PHYS_FLASH_1		0x80000000 /* Flash Bank #1 */
 #define PHYS_FLASH_SIZE		0x00200000 /* 2 MB */
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	1024	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* max number of sectors on one chip	*/
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		(0x0 + 0x3C000)	/* Addr of Environment Sector	*/
diff --git a/include/configs/lpd7a400-10.h b/include/configs/lpd7a400-10.h
index 3722fd2..6145c37 100644
--- a/include/configs/lpd7a400-10.h
+++ b/include/configs/lpd7a400-10.h
@@ -34,7 +34,7 @@
 #define CONFIG_SYS_CLK_FREQ		14745600   /* System Clock PLL Input (Hz) */
 
 /* ticks per second */
-#define CFG_HZ	(508469)
+#define CONFIG_SYS_HZ	(508469)
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -54,17 +54,17 @@
 #define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
 
-#define CFG_FLASH_BASE		0x00000000 /* Flash Bank #1 */
+#define CONFIG_SYS_FLASH_BASE		0x00000000 /* Flash Bank #1 */
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	(64)	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	(64)	/* max number of sectors on one chip */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 /*----------------------------------------------------------------------
  * Using SMC91C111 LAN chip
diff --git a/include/configs/lpd7a400.h b/include/configs/lpd7a400.h
index 9e6ea1a..575f2a1 100644
--- a/include/configs/lpd7a400.h
+++ b/include/configs/lpd7a400.h
@@ -37,8 +37,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * select serial console configuration
@@ -89,31 +89,31 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"LPD7A400> "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"LPD7A400> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0xc0300000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xc0500000	/* 2 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0xc0300000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0xc0500000	/* 2 MB in DRAM	*/
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0xc0f00000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0xc0f00000	/* default load address	*/
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /* size and location of u-boot in flash */
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256<<10)
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256<<10)
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 
 /* Address and size of Primary Environment Sector	*/
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0xFC0000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0xFC0000)
 #define CONFIG_ENV_SIZE		0x40000
 
 #endif  /* __LPD7A400_H_ */
diff --git a/include/configs/lpd7a404-10.h b/include/configs/lpd7a404-10.h
index a8af950..ce23f3d 100644
--- a/include/configs/lpd7a404-10.h
+++ b/include/configs/lpd7a404-10.h
@@ -34,7 +34,7 @@
 #define CONFIG_SYS_CLK_FREQ		14745600   /* System Clock PLL Input (Hz) */
 
 /* ticks per second */
-#define CFG_HZ	(508469)
+#define CONFIG_SYS_HZ	(508469)
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -54,17 +54,17 @@
 #define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
 
-#define CFG_FLASH_BASE		0x00000000 /* Flash Bank #1 */
+#define CONFIG_SYS_FLASH_BASE		0x00000000 /* Flash Bank #1 */
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	(64)	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	(64)	/* max number of sectors on one chip */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 /*----------------------------------------------------------------------
  * Using SMC91C111 LAN chip
diff --git a/include/configs/lpd7a404.h b/include/configs/lpd7a404.h
index 9c95913..3e726a0 100644
--- a/include/configs/lpd7a404.h
+++ b/include/configs/lpd7a404.h
@@ -37,8 +37,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * select serial console configuration
@@ -89,31 +89,31 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"LPD7A404> "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"LPD7A404> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0xc0300000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xc0500000	/* 2 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0xc0300000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0xc0500000	/* 2 MB in DRAM	*/
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0xc0f00000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0xc0f00000	/* default load address	*/
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /* size and location of u-boot in flash */
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(256<<10)
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256<<10)
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 
 /* Address and size of Primary Environment Sector	*/
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0xFC0000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0xFC0000)
 #define CONFIG_ENV_SIZE		0x40000
 
 #endif  /* __LPD7A404_H_ */
diff --git a/include/configs/luan.h b/include/configs/luan.h
index 2259ec3..b158b74 100644
--- a/include/configs/luan.h
+++ b/include/configs/luan.h
@@ -50,44 +50,44 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_LARGE_FLASH		0xffc00000	/* 4MB flash address CS0 */
-#define CFG_SMALL_FLASH		0xff900000	/* 1MB flash address CS2 */
-#define CFG_SRAM_BASE		0xff800000	/* 1MB SRAM  address CS2 */
-#define CFG_EPLD_BASE		0xff000000	/* EPLD and FRAM     CS1 */
+#define CONFIG_SYS_LARGE_FLASH		0xffc00000	/* 4MB flash address CS0 */
+#define CONFIG_SYS_SMALL_FLASH		0xff900000	/* 1MB flash address CS2 */
+#define CONFIG_SYS_SRAM_BASE		0xff800000	/* 1MB SRAM  address CS2 */
+#define CONFIG_SYS_EPLD_BASE		0xff000000	/* EPLD and FRAM     CS1 */
 
-#define CFG_ISRAM_BASE	        0xf8000000	/* internal 8k SRAM (L2 cache) */
+#define CONFIG_SYS_ISRAM_BASE	        0xf8000000	/* internal 8k SRAM (L2 cache) */
 
-#define CFG_PERIPHERAL_BASE     0xf0000000	/* internal peripherals */
+#define CONFIG_SYS_PERIPHERAL_BASE     0xf0000000	/* internal peripherals */
 
-#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory */
-#define CFG_PCI_BASE		0xd0000000	/* internal PCI regs */
-#define CFG_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory */
+#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs */
+#define CONFIG_SYS_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 
-#if CFG_LARGE_FLASH == 0xffc00000
-#define CFG_FLASH_BASE		CFG_LARGE_FLASH
+#if CONFIG_SYS_LARGE_FLASH == 0xffc00000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_LARGE_FLASH
 #else
-#define CFG_FLASH_BASE		CFG_SMALL_FLASH
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_SMALL_FLASH
 #endif
 
-#if CFG_SRAM_BASE
-#define CFG_KBYTES_SDRAM	1024*2
+#if CONFIG_SYS_SRAM_BASE
+#define CONFIG_SYS_KBYTES_SDRAM	1024*2
 #else
-#define CFG_KBYTES_SDRAM	1024
+#define CONFIG_SYS_KBYTES_SDRAM	1024
 #endif
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR	CFG_ISRAM_BASE
-#define CFG_INIT_RAM_END	(8 << 10)
-#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_END	(8 << 10)
+#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#define CFG_EXT_SERIAL_CLOCK	11059200 /* external 11.059MHz clk */
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200 /* external 11.059MHz clk */
 #undef  CONFIG_UART1_CONSOLE		/* define if you want console on UART1 */
 
 /*-----------------------------------------------------------------------
@@ -102,21 +102,21 @@
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS	3	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-#define CFG_FLASH_ADDR0         0x555
-#define CFG_FLASH_ADDR1         0x2aa
-#define CFG_FLASH_WORD_SIZE     unsigned char
+#define CONFIG_SYS_FLASH_ADDR0         0x555
+#define CONFIG_SYS_FLASH_ADDR1         0x2aa
+#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x10000 /* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -134,14 +134,13 @@
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 
 /*
  * Default environment variables
@@ -183,11 +182,11 @@
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT
-#undef  CFG_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_TARGET_INIT
+#undef  CONFIG_SYS_PCI_MASTER_INIT
 
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_DEVICEID 0x4403	/* whatever */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x4403	/* whatever */
 
 #endif
 
diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h
index 3c921c0..69774d7 100644
--- a/include/configs/lubbock.h
+++ b/include/configs/lubbock.h
@@ -40,7 +40,7 @@
 #ifdef CONFIG_LCD
 #define CONFIG_SHARP_LM8V31
 #endif
-#define CONFIG_MMC		1
+#define CONFIG_MMC
 #define BOARD_LATE_INIT		1
 #define CONFIG_DOS_PARTITION
 
@@ -49,8 +49,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -83,7 +83,6 @@
  */
 #include <config_cmd_default.h>
 
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_FAT
 
 
@@ -105,35 +104,39 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_HUSH_PARSER		1
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
-#define CFG_LONGHELP				/* undef to save memory		*/
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT		"$ "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
 #else
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 #endif
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_DEVICE_NULLDEV	1
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1
 
-#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR	(CFG_DRAM_BASE + 0x8000) /* default load address */
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
 
-#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x161		/* set core clock to 400/200/100 MHz */
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CPUSPEED		0x161		/* set core clock to 400/200/100 MHz */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define CFG_MMC_BASE		0xF0000000
+#ifdef CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_SYS_MMC_BASE		0xF0000000
+#endif
 
 /*
  * Stack sizes
@@ -165,54 +168,54 @@
 #define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
 #define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
 
-#define CFG_DRAM_BASE		0xa0000000
-#define CFG_DRAM_SIZE		0x04000000
+#define CONFIG_SYS_DRAM_BASE		0xa0000000
+#define CONFIG_SYS_DRAM_SIZE		0x04000000
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 #define FPGA_REGS_BASE_PHYSICAL 0x08000000
 
 /*
  * GPIO settings
  */
-#define CFG_GPSR0_VAL		0x00008000
-#define CFG_GPSR1_VAL		0x00FC0382
-#define CFG_GPSR2_VAL		0x0001FFFF
-#define CFG_GPCR0_VAL		0x00000000
-#define CFG_GPCR1_VAL		0x00000000
-#define CFG_GPCR2_VAL		0x00000000
-#define CFG_GPDR0_VAL		0x0060A800
-#define CFG_GPDR1_VAL		0x00FF0382
-#define CFG_GPDR2_VAL		0x0001C000
-#define CFG_GAFR0_L_VAL		0x98400000
-#define CFG_GAFR0_U_VAL		0x00002950
-#define CFG_GAFR1_L_VAL		0x000A9558
-#define CFG_GAFR1_U_VAL		0x0005AAAA
-#define CFG_GAFR2_L_VAL		0xA0000000
-#define CFG_GAFR2_U_VAL		0x00000002
-
-#define CFG_PSSR_VAL		0x20
+#define CONFIG_SYS_GPSR0_VAL		0x00008000
+#define CONFIG_SYS_GPSR1_VAL		0x00FC0382
+#define CONFIG_SYS_GPSR2_VAL		0x0001FFFF
+#define CONFIG_SYS_GPCR0_VAL		0x00000000
+#define CONFIG_SYS_GPCR1_VAL		0x00000000
+#define CONFIG_SYS_GPCR2_VAL		0x00000000
+#define CONFIG_SYS_GPDR0_VAL		0x0060A800
+#define CONFIG_SYS_GPDR1_VAL		0x00FF0382
+#define CONFIG_SYS_GPDR2_VAL		0x0001C000
+#define CONFIG_SYS_GAFR0_L_VAL		0x98400000
+#define CONFIG_SYS_GAFR0_U_VAL		0x00002950
+#define CONFIG_SYS_GAFR1_L_VAL		0x000A9558
+#define CONFIG_SYS_GAFR1_U_VAL		0x0005AAAA
+#define CONFIG_SYS_GAFR2_L_VAL		0xA0000000
+#define CONFIG_SYS_GAFR2_U_VAL		0x00000002
+
+#define CONFIG_SYS_PSSR_VAL		0x20
 
 /*
  * Memory settings
  */
-#define CFG_MSC0_VAL		0x23F223F2
-#define CFG_MSC1_VAL		0x3FF1A441
-#define CFG_MSC2_VAL		0x7FF97FF1
-#define CFG_MDCNFG_VAL		0x00001AC9
-#define CFG_MDREFR_VAL		0x00018018
-#define CFG_MDMRS_VAL		0x00000000
+#define CONFIG_SYS_MSC0_VAL		0x23F223F2
+#define CONFIG_SYS_MSC1_VAL		0x3FF1A441
+#define CONFIG_SYS_MSC2_VAL		0x7FF97FF1
+#define CONFIG_SYS_MDCNFG_VAL		0x00001AC9
+#define CONFIG_SYS_MDREFR_VAL		0x00018018
+#define CONFIG_SYS_MDMRS_VAL		0x00000000
 
 /*
  * PCMCIA and CF Interfaces
  */
-#define CFG_MECR_VAL		0x00000000
-#define CFG_MCMEM0_VAL		0x00010504
-#define CFG_MCMEM1_VAL		0x00010504
-#define CFG_MCATT0_VAL		0x00010504
-#define CFG_MCATT1_VAL		0x00010504
-#define CFG_MCIO0_VAL		0x00004715
-#define CFG_MCIO1_VAL		0x00004715
+#define CONFIG_SYS_MECR_VAL		0x00000000
+#define CONFIG_SYS_MCMEM0_VAL		0x00010504
+#define CONFIG_SYS_MCMEM1_VAL		0x00010504
+#define CONFIG_SYS_MCATT0_VAL		0x00010504
+#define CONFIG_SYS_MCATT1_VAL		0x00010504
+#define CONFIG_SYS_MCIO0_VAL		0x00004715
+#define CONFIG_SYS_MCIO1_VAL		0x00004715
 
 #define _LED			0x08000010
 #define LED_BLANK		0x08000040
@@ -220,17 +223,17 @@
 /*
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 /* NOTE: many default partitioning schemes assume the kernel starts at the
  * second sector, not an environment.  You have been warned!
  */
-#define	CFG_MONITOR_LEN		PHYS_FLASH_SECT_SIZE
+#define	CONFIG_SYS_MONITOR_LEN		PHYS_FLASH_SECT_SIZE
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
 #define CONFIG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE
diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h
index e4ee099..d52a5e0 100644
--- a/include/configs/lwmon.h
+++ b/include/configs/lwmon.h
@@ -73,18 +73,18 @@
 #undef	CONFIG_BOOTARGS
 
 /* POST support */
-#define CONFIG_POST		(CFG_POST_CACHE	   | \
-				 CFG_POST_WATCHDOG | \
-				 CFG_POST_RTC	   | \
-				 CFG_POST_MEMORY   | \
-				 CFG_POST_CPU	   | \
-				 CFG_POST_UART	   | \
-				 CFG_POST_ETHER    | \
-				 CFG_POST_I2C	   | \
-				 CFG_POST_SPI	   | \
-				 CFG_POST_USB	   | \
-				 CFG_POST_SPR	   | \
-				 CFG_POST_SYSMON)
+#define CONFIG_POST		(CONFIG_SYS_POST_CACHE	   | \
+				 CONFIG_SYS_POST_WATCHDOG | \
+				 CONFIG_SYS_POST_RTC	   | \
+				 CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_UART	   | \
+				 CONFIG_SYS_POST_ETHER    | \
+				 CONFIG_SYS_POST_I2C	   | \
+				 CONFIG_SYS_POST_SPI	   | \
+				 CONFIG_SYS_POST_USB	   | \
+				 CONFIG_SYS_POST_SPR	   | \
+				 CONFIG_SYS_POST_SYSMON)
 
 /*
  * Keyboard commands:
@@ -135,10 +135,10 @@
 	"verify=no"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/
-#define	CFG_WATCHDOG_FREQ       (CFG_HZ / 20)
+#define	CONFIG_SYS_WATCHDOG_FREQ       (CONFIG_SYS_HZ / 20)
 
 #undef	CONFIG_STATUS_LED		/* Status LED disabled		*/
 
@@ -146,8 +146,8 @@
 #undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/
 
-#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
-#define CFG_I2C_SLAVE		0xFE
+#define CONFIG_SYS_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CONFIG_SYS_I2C_SLAVE		0xFE
 
 #ifdef CONFIG_SOFT_I2C
 /*
@@ -209,39 +209,39 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x00100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */
 
-#define CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+#define CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 /*
  * When the watchdog is enabled, output must be fast enough in Linux.
  */
 #ifdef CONFIG_WATCHDOG
-#define CFG_BAUDRATE_TABLE	{		38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{		38400, 57600, 115200 }
 #else
-#define CFG_BAUDRATE_TABLE	{  9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{  9600, 19200, 38400, 57600, 115200 }
 #endif
 
 /*----------------------------------------------------------------------*/
@@ -266,53 +266,53 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	68  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	68  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
 #if defined(DEBUG) || defined(CONFIG_CMD_IDE)
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	180000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	600	/* Timeout for Flash Write (in ms)	*/
-#define CFG_FLASH_USE_BUFFER_WRITE
-#define CFG_FLASH_BUFFER_WRITE_TOUT	2048	/* Timeout for Flash Buffer Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	180000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	600	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT	2048	/* Timeout for Flash Buffer Write (in ms)	*/
 /* Buffer size.
    We have two flash devices connected in parallel.
    Each device incorporates a Write Buffer of 32 bytes.
  */
-#define CFG_FLASH_BUFFER_SIZE	(2*32)
+#define CONFIG_SYS_FLASH_BUFFER_SIZE	(2*32)
 
 /* Put environment in flash which is much faster to boot than using the EEPROM	*/
 #define CONFIG_ENV_IS_IN_FLASH	1
@@ -324,62 +324,62 @@
  * I2C/EEPROM Configuration
  */
 
-#define CFG_I2C_AUDIO_ADDR	0x28	/* Audio volume control			*/
-#define CFG_I2C_SYSMON_ADDR	0x2E	/* LM87 System Monitor			*/
-#define CFG_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/
-#define CFG_I2C_POWER_A_ADDR	0x52	/* PCMCIA/USB power switch, channel A	*/
-#define CFG_I2C_POWER_B_ADDR	0x53	/* PCMCIA/USB power switch, channel B	*/
-#define CFG_I2C_KEYBD_ADDR	0x56	/* PIC LWE keyboard			*/
-#define CFG_I2C_PICIO_ADDR	0x57	/* PIC IO Expander			*/
+#define CONFIG_SYS_I2C_AUDIO_ADDR	0x28	/* Audio volume control			*/
+#define CONFIG_SYS_I2C_SYSMON_ADDR	0x2E	/* LM87 System Monitor			*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/
+#define CONFIG_SYS_I2C_POWER_A_ADDR	0x52	/* PCMCIA/USB power switch, channel A	*/
+#define CONFIG_SYS_I2C_POWER_B_ADDR	0x53	/* PCMCIA/USB power switch, channel B	*/
+#define CONFIG_SYS_I2C_KEYBD_ADDR	0x56	/* PIC LWE keyboard			*/
+#define CONFIG_SYS_I2C_PICIO_ADDR	0x57	/* PIC IO Expander			*/
 
 #undef	CONFIG_USE_FRAM			/* Use FRAM instead of EEPROM	*/
 
 #ifdef CONFIG_USE_FRAM	/* use FRAM */
-#define CFG_I2C_EEPROM_ADDR	0x55	/* FRAM FM24CL64		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x55	/* FRAM FM24CL64		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
 #else			/* use EEPROM */
-#define CFG_I2C_EEPROM_ADDR	0x58	/* EEPROM AT24C164		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x58	/* EEPROM AT24C164		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec	*/
 #endif	/* CONFIG_USE_FRAM */
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
 
 /* List of I2C addresses to be verified by POST */
 #ifdef CONFIG_USE_FRAM
-#define I2C_ADDR_LIST	{  /*	CFG_I2C_AUDIO_ADDR, */	\
-				CFG_I2C_SYSMON_ADDR,	\
-				CFG_I2C_RTC_ADDR,	\
-				CFG_I2C_POWER_A_ADDR,	\
-				CFG_I2C_POWER_B_ADDR,	\
-				CFG_I2C_KEYBD_ADDR,	\
-				CFG_I2C_PICIO_ADDR,	\
-				CFG_I2C_EEPROM_ADDR,	\
+#define I2C_ADDR_LIST	{  /*	CONFIG_SYS_I2C_AUDIO_ADDR, */	\
+				CONFIG_SYS_I2C_SYSMON_ADDR,	\
+				CONFIG_SYS_I2C_RTC_ADDR,	\
+				CONFIG_SYS_I2C_POWER_A_ADDR,	\
+				CONFIG_SYS_I2C_POWER_B_ADDR,	\
+				CONFIG_SYS_I2C_KEYBD_ADDR,	\
+				CONFIG_SYS_I2C_PICIO_ADDR,	\
+				CONFIG_SYS_I2C_EEPROM_ADDR,	\
 			}
 #else	/* Use EEPROM - which show up on 8 consequtive addresses */
-#define I2C_ADDR_LIST	{  /*	CFG_I2C_AUDIO_ADDR, */	\
-				CFG_I2C_SYSMON_ADDR,	\
-				CFG_I2C_RTC_ADDR,	\
-				CFG_I2C_POWER_A_ADDR,	\
-				CFG_I2C_POWER_B_ADDR,	\
-				CFG_I2C_KEYBD_ADDR,	\
-				CFG_I2C_PICIO_ADDR,	\
-				CFG_I2C_EEPROM_ADDR+0,	\
-				CFG_I2C_EEPROM_ADDR+1,	\
-				CFG_I2C_EEPROM_ADDR+2,	\
-				CFG_I2C_EEPROM_ADDR+3,	\
-				CFG_I2C_EEPROM_ADDR+4,	\
-				CFG_I2C_EEPROM_ADDR+5,	\
-				CFG_I2C_EEPROM_ADDR+6,	\
-				CFG_I2C_EEPROM_ADDR+7,	\
+#define I2C_ADDR_LIST	{  /*	CONFIG_SYS_I2C_AUDIO_ADDR, */	\
+				CONFIG_SYS_I2C_SYSMON_ADDR,	\
+				CONFIG_SYS_I2C_RTC_ADDR,	\
+				CONFIG_SYS_I2C_POWER_A_ADDR,	\
+				CONFIG_SYS_I2C_POWER_B_ADDR,	\
+				CONFIG_SYS_I2C_KEYBD_ADDR,	\
+				CONFIG_SYS_I2C_PICIO_ADDR,	\
+				CONFIG_SYS_I2C_EEPROM_ADDR+0,	\
+				CONFIG_SYS_I2C_EEPROM_ADDR+1,	\
+				CONFIG_SYS_I2C_EEPROM_ADDR+2,	\
+				CONFIG_SYS_I2C_EEPROM_ADDR+3,	\
+				CONFIG_SYS_I2C_EEPROM_ADDR+4,	\
+				CONFIG_SYS_I2C_EEPROM_ADDR+5,	\
+				CONFIG_SYS_I2C_EEPROM_ADDR+6,	\
+				CONFIG_SYS_I2C_EEPROM_ADDR+7,	\
 			}
 #endif	/* CONFIG_USE_FRAM */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -389,10 +389,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if 0 && defined(CONFIG_WATCHDOG)	/* LWMON uses external MAX706TESA WD */
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -402,22 +402,22 @@
  */
 /* EARB, DBGC and DBPC are initialised by the HCW */
 /* => 0x000000C0 */
-#define CFG_SIUMCR	(SIUMCR_GB5E)
-/*#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_GB5E)
+/*#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -426,15 +426,15 @@
  * interrupt status bit, set PLL multiplication factor !
  */
 /* 0x00405000 */
-#define CFG_PLPRCR_MF	4	/* (4+1) * 13.2 = 66 MHz Clock */
-#define CFG_PLPRCR							\
-		(	(CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) |		\
+#define CONFIG_SYS_PLPRCR_MF	4	/* (4+1) * 13.2 = 66 MHz Clock */
+#define CONFIG_SYS_PLPRCR							\
+		(	(CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) |		\
 			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
 			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
 			PLPRCR_CSR    /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/	\
 		)
 
-#define CONFIG_8xx_GCLK_FREQ	((CFG_PLPRCR_MF+1)*13200000)
+#define CONFIG_8xx_GCLK_FREQ	((CONFIG_SYS_PLPRCR_MF+1)*13200000)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -444,7 +444,7 @@
  */
 #define SCCR_MASK	SCCR_EBDF11
 /* 0x01800000 */
-#define CFG_SCCR	(SCCR_COM00	| /*SCCR_TBS|*/		\
+#define CONFIG_SYS_SCCR	(SCCR_COM00	| /*SCCR_TBS|*/		\
 			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
 			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
 			 SCCR_EBDF00 |	 SCCR_DFSYNC00 |	\
@@ -457,41 +457,41 @@
  *-----------------------------------------------------------------------
  */
 /* 0x00C3 => 0x0003 */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration Register		19-4
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR 0x0000
+#define CONFIG_SYS_RCCR 0x0000
 
 /*-----------------------------------------------------------------------
  * RMDS - RISC Microcode Development Support Control Register
  *-----------------------------------------------------------------------
  */
-#define CFG_RMDS 0
+#define CONFIG_SYS_RMDS 0
 
 /*-----------------------------------------------------------------------
  *
  * Interrupt Levels
  *-----------------------------------------------------------------------
  */
-#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
+#define CONFIG_SYS_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0x50000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0x54000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0x58000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0x5C000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0x50000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0x54000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0x58000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0x5C000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -504,21 +504,21 @@
 #undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 #define CONFIG_SUPPORT_VFAT		/* enable VFAT support */
 
@@ -527,7 +527,7 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER 0
+#define CONFIG_SYS_DER 0
 
 /*
  * Init Memory Controller:
@@ -542,22 +542,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0xFF000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFF000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0xFF000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFF000000	/* OR addr mask */
 
 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0	*/
-#define CFG_OR_TIMING_FLASH	(OR_SCY_8_CLK)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_SCY_8_CLK)
 
-#define CFG_OR0_REMAP	( CFG_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
-				CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
-				CFG_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_REMAP	( CONFIG_SYS_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+				CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
+				CONFIG_SYS_OR_TIMING_FLASH)
 /* 16 bit, bank valid */
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
 
 /*
  * BR3/OR3: SDRAM
@@ -570,8 +570,8 @@
 
 #define SDRAM_MAX_SIZE		0x08000000	/* max 128 MB SDRAM */
 
-#define CFG_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /*
  * BR5/OR5: Touch Panel
@@ -582,32 +582,32 @@
 #define TOUCHPNL_OR_AM		0xFFFF8000
 #define TOUCHPNL_TIMING		OR_SCY_0_CLK
 
-#define CFG_OR5_PRELIM	(TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+#define CONFIG_SYS_OR5_PRELIM	(TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
 			 TOUCHPNL_TIMING )
-#define CFG_BR5_PRELIM	((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
+#define CONFIG_SYS_BR5_PRELIM	((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
 
-#define	CFG_MEMORY_75
-#undef	CFG_MEMORY_7E
-#undef	CFG_MEMORY_8E
+#define	CONFIG_SYS_MEMORY_75
+#undef	CONFIG_SYS_MEMORY_7E
+#undef	CONFIG_SYS_MEMORY_8E
 
 /*
  * Memory Periodic Timer Prescaler
  */
 
 /* periodic timer for refresh */
-#define CFG_MPTPR	0x200
+#define CONFIG_SYS_MPTPR	0x200
 
 /*
  * MAMR settings for SDRAM
  */
 
-#define CFG_MAMR_8COL	0x80802114
-#define CFG_MAMR_9COL	0x80904114
+#define CONFIG_SYS_MAMR_8COL	0x80802114
+#define CONFIG_SYS_MAMR_9COL	0x80904114
 
 /*
  * MAR setting for SDRAM
  */
-#define CFG_MAR		0x00000088
+#define CONFIG_SYS_MAR		0x00000088
 
 /*
  * Internal Definitions
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index c09e301..05055c8 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -42,32 +42,32 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserve 512 kB for malloc()	*/
-
-#define CFG_BOOT_BASE_ADDR	0xf0000000
-#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
-#define CFG_FLASH_BASE		0xf8000000	/* start of FLASH	*/
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_LIME_BASE_0         0xc0000000
-#define CFG_LIME_BASE_1         0xc1000000
-#define CFG_LIME_BASE_2         0xc2000000
-#define CFG_LIME_BASE_3         0xc3000000
-#define CFG_FPGA_BASE_0         0xc4000000
-#define CFG_FPGA_BASE_1         0xc4200000
-#define CFG_OCM_BASE		0xe0010000      /* ocm			*/
-#define CFG_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
-#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
-#define CFG_PCI_MEMBASE1	CFG_PCI_MEMBASE  + 0x10000000
-#define CFG_PCI_MEMBASE2	CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3	CFG_PCI_MEMBASE2 + 0x10000000
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)	/* Reserve 512 kB for malloc()	*/
+
+#define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CONFIG_SYS_FLASH_BASE		0xf8000000	/* start of FLASH	*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_LIME_BASE_0         0xc0000000
+#define CONFIG_SYS_LIME_BASE_1         0xc1000000
+#define CONFIG_SYS_LIME_BASE_2         0xc2000000
+#define CONFIG_SYS_LIME_BASE_3         0xc3000000
+#define CONFIG_SYS_FPGA_BASE_0         0xc4000000
+#define CONFIG_SYS_FPGA_BASE_1         0xc4200000
+#define CONFIG_SYS_OCM_BASE		0xe0010000      /* ocm			*/
+#define CONFIG_SYS_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CONFIG_SYS_PCI_MEMBASE1	CONFIG_SYS_PCI_MEMBASE  + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2	CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3	CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
 
 /* Don't change either of these */
-#define CFG_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
+#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
 
-#define CFG_USB2D0_BASE		0xe0000100
-#define CFG_USB_DEVICE		0xe0000000
-#define CFG_USB_HOST		0xe0000400
+#define CONFIG_SYS_USB2D0_BASE		0xe0000100
+#define CONFIG_SYS_USB_DEVICE		0xe0000000
+#define CONFIG_SYS_USB_HOST		0xe0000400
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer
@@ -78,41 +78,41 @@
  * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
  * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
  */
-#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
-#define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
-#define CFG_INIT_RAM_END	(4 << 10)
-#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-#define CFG_POST_ALT_WORD_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP6)
+#define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
+#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000		/* DCache       */
+#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_POST_ALT_WORD_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
 						/* unused GPT0 COMP reg	*/
-#define CFG_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
+#define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
 					/* 440EPx errata CHIP 11	*/
-#define CFG_OCM_SIZE		(16 << 10)
+#define CONFIG_SYS_OCM_SIZE		(16 << 10)
 
 /* Additional registers for watchdog timer post test */
 
-#define CFG_WATCHDOG_TIME_ADDR	(CFG_PERIPHERAL_BASE + GPT0_MASK2)
-#define CFG_WATCHDOG_FLAGS_ADDR	(CFG_PERIPHERAL_BASE + GPT0_MASK1)
-#define CFG_DSPIC_TEST_ADDR	CFG_WATCHDOG_FLAGS_ADDR
-#define CFG_OCM_STATUS_ADDR	CFG_WATCHDOG_FLAGS_ADDR
-#define CFG_WATCHDOG_MAGIC	0x12480000
-#define CFG_WATCHDOG_MAGIC_MASK	0xFFFF0000
-#define CFG_DSPIC_TEST_MASK	0x00000001
-#define CFG_OCM_STATUS_OK	0x00009A00
-#define CFG_OCM_STATUS_FAIL	0x0000A300
-#define CFG_OCM_STATUS_MASK	0x0000FF00
+#define CONFIG_SYS_WATCHDOG_TIME_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
+#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
+#define CONFIG_SYS_DSPIC_TEST_ADDR	CONFIG_SYS_WATCHDOG_FLAGS_ADDR
+#define CONFIG_SYS_OCM_STATUS_ADDR	CONFIG_SYS_WATCHDOG_FLAGS_ADDR
+#define CONFIG_SYS_WATCHDOG_MAGIC	0x12480000
+#define CONFIG_SYS_WATCHDOG_MAGIC_MASK	0xFFFF0000
+#define CONFIG_SYS_DSPIC_TEST_MASK	0x00000001
+#define CONFIG_SYS_OCM_STATUS_OK	0x00009A00
+#define CONFIG_SYS_OCM_STATUS_FAIL	0x0000A300
+#define CONFIG_SYS_OCM_STATUS_MASK	0x0000FF00
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#undef CFG_EXT_SERIAL_CLOCK		/* no external clock provided	*/
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK		/* no external clock provided	*/
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SERIAL_MULTI     1
 /* define this if you want console on UART1 */
 #define CONFIG_UART1_CONSOLE	1	/* use UART1 as console		*/
 
-#define CFG_BAUDRATE_TABLE						\
+#define CONFIG_SYS_BAUDRATE_TABLE						\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
 /*-----------------------------------------------------------------------
@@ -123,27 +123,27 @@
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
 #define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
 
-#define CFG_FLASH0		0xFC000000
-#define CFG_FLASH1		0xF8000000
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH1, CFG_FLASH0 }
+#define CONFIG_SYS_FLASH0		0xFC000000
+#define CONFIG_SYS_FLASH1		0xF8000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
 
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection	*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
 
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* size of one complete sector		*/
-#define CONFIG_ENV_ADDR		((-CFG_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -153,32 +153,32 @@
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
-#define CFG_MBYTES_SDRAM	(256)		/* 256MB			*/
-#define CFG_DDR_CACHED_ADDR	0x40000000	/* setup 2nd TLB cached here	*/
+#define CONFIG_SYS_MBYTES_SDRAM	(256)		/* 256MB			*/
+#define CONFIG_SYS_DDR_CACHED_ADDR	0x40000000	/* setup 2nd TLB cached here	*/
 #define CONFIG_DDR_DATA_EYE	1		/* use DDR2 optimization	*/
 #define CONFIG_DDR_ECC		1		/* enable ECC			*/
-#define CFG_POST_ECC_ON		CFG_POST_ECC
+#define CONFIG_SYS_POST_ECC_ON		CONFIG_SYS_POST_ECC
 
 /* POST support */
-#define CONFIG_POST		(CFG_POST_CACHE    | \
-				 CFG_POST_CPU	   | \
-				 CFG_POST_ECC_ON   | \
-				 CFG_POST_ETHER	   | \
-				 CFG_POST_FPU	   | \
-				 CFG_POST_I2C	   | \
-				 CFG_POST_MEMORY   | \
-				 CFG_POST_OCM      | \
-				 CFG_POST_RTC      | \
-				 CFG_POST_SPR      | \
-				 CFG_POST_UART     | \
-				 CFG_POST_SYSMON   | \
-				 CFG_POST_WATCHDOG | \
-				 CFG_POST_DSP      | \
-				 CFG_POST_BSPEC1   | \
-				 CFG_POST_BSPEC2   | \
-				 CFG_POST_BSPEC3   | \
-				 CFG_POST_BSPEC4   | \
-				 CFG_POST_BSPEC5)
+#define CONFIG_POST		(CONFIG_SYS_POST_CACHE    | \
+				 CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_ECC_ON   | \
+				 CONFIG_SYS_POST_ETHER	   | \
+				 CONFIG_SYS_POST_FPU	   | \
+				 CONFIG_SYS_POST_I2C	   | \
+				 CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_OCM      | \
+				 CONFIG_SYS_POST_RTC      | \
+				 CONFIG_SYS_POST_SPR      | \
+				 CONFIG_SYS_POST_UART     | \
+				 CONFIG_SYS_POST_SYSMON   | \
+				 CONFIG_SYS_POST_WATCHDOG | \
+				 CONFIG_SYS_POST_DSP      | \
+				 CONFIG_SYS_POST_BSPEC1   | \
+				 CONFIG_SYS_POST_BSPEC2   | \
+				 CONFIG_SYS_POST_BSPEC3   | \
+				 CONFIG_SYS_POST_BSPEC4   | \
+				 CONFIG_SYS_POST_BSPEC5)
 
 #define CONFIG_POST_WATCHDOG  {\
 	"Watchdog timer test",				\
@@ -188,7 +188,7 @@
 	&lwmon5_watchdog_post_test,			\
 	NULL,						\
 	NULL,						\
-	CFG_POST_WATCHDOG				\
+	CONFIG_SYS_POST_WATCHDOG				\
 	}
 
 #define CONFIG_POST_BSPEC1    {\
@@ -199,7 +199,7 @@
 	&dspic_init_post_test,				\
 	NULL,						\
 	NULL,						\
-	CFG_POST_BSPEC1					\
+	CONFIG_SYS_POST_BSPEC1					\
 	}
 
 #define CONFIG_POST_BSPEC2    {\
@@ -210,7 +210,7 @@
 	&dspic_post_test,				\
 	NULL,						\
 	NULL,						\
-	CFG_POST_BSPEC2					\
+	CONFIG_SYS_POST_BSPEC2					\
 	}
 
 #define CONFIG_POST_BSPEC3    {\
@@ -221,7 +221,7 @@
 	&fpga_post_test,				\
 	NULL,						\
 	NULL,						\
-	CFG_POST_BSPEC3					\
+	CONFIG_SYS_POST_BSPEC3					\
 	}
 
 #define CONFIG_POST_BSPEC4    {\
@@ -232,7 +232,7 @@
 	&gdc_post_test,					\
 	NULL,						\
 	NULL,						\
-	CFG_POST_BSPEC4					\
+	CONFIG_SYS_POST_BSPEC4					\
 	}
 
 #define CONFIG_POST_BSPEC5    {\
@@ -243,36 +243,35 @@
 	&sysmon1_post_test,				\
 	NULL,						\
 	NULL,						\
-	CFG_POST_BSPEC5					\
+	CONFIG_SYS_POST_BSPEC5					\
 	}
 
-#define CFG_POST_CACHE_ADDR	0x7fff0000 /* free virtual address	*/
+#define CONFIG_SYS_POST_CACHE_ADDR	0x7fff0000 /* free virtual address	*/
 #define CONFIG_LOGBUFFER
 /* Reserve GPT0_COMP1-COMP5 for logbuffer header */
-#define CONFIG_ALT_LH_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP1)
-#define CONFIG_ALT_LB_ADDR	(CFG_OCM_BASE)
-#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+#define CONFIG_ALT_LH_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
+#define CONFIG_ALT_LB_ADDR	(CONFIG_SYS_OCM_BASE)
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C		1		/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		100000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000		/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x53	/* EEPROM AT24C128		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
-#define CFG_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel AT24C128 has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x53	/* EEPROM AT24C128		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel AT24C128 has	*/
 					/* 64 byte page write mode using*/
 					/* last 6 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 #define CONFIG_RTC_PCF8563	1		/* enable Philips PCF8563 RTC	*/
-#define CFG_I2C_RTC_ADDR	0x51		/* Philips PCF8563 RTC address	*/
-#define CFG_I2C_KEYBD_ADDR	0x56		/* PIC LWE keyboard		*/
-#define CFG_I2C_DSPIC_IO_ADDR	0x57		/* PIC I/O addr               */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51		/* Philips PCF8563 RTC address	*/
+#define CONFIG_SYS_I2C_KEYBD_ADDR	0x56		/* PIC LWE keyboard		*/
+#define CONFIG_SYS_I2C_DSPIC_IO_ADDR	0x57		/* PIC I/O addr               */
 
 #define	CONFIG_POST_KEY_MAGIC	"3C+3E"	/* press F3 + F5 keys to force POST */
 #if 0
@@ -325,8 +324,9 @@
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define	CONFIG_IBM_EMAC4_V4	1
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		3	/* PHY address, See schematics	*/
@@ -335,7 +335,7 @@
 #define CONFIG_PHY_RESET_DELAY	300
 
 #define CONFIG_HAS_ETH0
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+#define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
 
 #define CONFIG_NET_MULTI	1
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
@@ -412,30 +412,30 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_SUPPORT_VFAT
 
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
+#define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
@@ -449,14 +449,14 @@
 #define CONFIG_PCI			/* include pci support	        */
 #undef CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
-#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+#define CONFIG_SYS_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT
-#define CFG_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
 
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
-#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
+#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
 
 #define CONFIG_HW_WATCHDOG	1	/* Use external HW-Watchdog	*/
 #define CONFIG_WD_PERIOD	40000	/* in usec */
@@ -467,74 +467,74 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
-#define CFG_FLASH		CFG_FLASH_BASE
+#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE
 
 /* Memory Bank 0 (NOR-FLASH) initialization					*/
-#define CFG_EBC_PB0AP		0x03050200
-#define CFG_EBC_PB0CR		(CFG_FLASH | 0xfc000)
+#define CONFIG_SYS_EBC_PB0AP		0x03050200
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH | 0xfc000)
 
 /* Memory Bank 1 (Lime) initialization						*/
-#define CFG_EBC_PB1AP		0x01004380
-#define CFG_EBC_PB1CR		(CFG_LIME_BASE_0 | 0xdc000)
+#define CONFIG_SYS_EBC_PB1AP		0x01004380
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_LIME_BASE_0 | 0xdc000)
 
 /* Memory Bank 2 (FPGA) initialization						*/
-#define CFG_EBC_PB2AP		0x01004400
-#define CFG_EBC_PB2CR		(CFG_FPGA_BASE_0 | 0x1c000)
+#define CONFIG_SYS_EBC_PB2AP		0x01004400
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
 
 /* Memory Bank 3 (FPGA2) initialization						*/
-#define CFG_EBC_PB3AP		0x01004400
-#define CFG_EBC_PB3CR		(CFG_FPGA_BASE_1 | 0x1c000)
+#define CONFIG_SYS_EBC_PB3AP		0x01004400
+#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
 
-#define CFG_EBC_CFG		0xb8400000
+#define CONFIG_SYS_EBC_CFG		0xb8400000
 
 /*-----------------------------------------------------------------------
  * Graphics (Fujitsu Lime)
  *----------------------------------------------------------------------*/
 /* SDRAM Clock frequency adjustment register */
-#define CFG_LIME_SDRAM_CLOCK	0xC1FC0038
+#define CONFIG_SYS_LIME_SDRAM_CLOCK	0xC1FC0038
 /* Lime Clock frequency is to set 100MHz */
-#define CFG_LIME_CLOCK_100MHZ	0x00000
+#define CONFIG_SYS_LIME_CLOCK_100MHZ	0x00000
 #if 0
 /* Lime Clock frequency for 133MHz */
-#define CFG_LIME_CLOCK_133MHZ	0x10000
+#define CONFIG_SYS_LIME_CLOCK_133MHZ	0x10000
 #endif
 
 /* SDRAM Parameter register */
-#define CFG_LIME_MMR		0xC1FCFFFC
+#define CONFIG_SYS_LIME_MMR		0xC1FCFFFC
 /* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
    and pixel flare on display when 133MHz was configured. According to
    SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
-#ifdef CFG_LIME_CLOCK_133MHZ
-#define CFG_LIME_MMR_VALUE	0x414FB7F3
+#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
+#define CONFIG_SYS_LIME_MMR_VALUE	0x414FB7F3
 #else
-#define CFG_LIME_MMR_VALUE	0x414FB7F2
+#define CONFIG_SYS_LIME_MMR_VALUE	0x414FB7F2
 #endif
 
 /*-----------------------------------------------------------------------
  * GPIO Setup
  *----------------------------------------------------------------------*/
-#define CFG_GPIO_PHY1_RST	12
-#define CFG_GPIO_FLASH_WP	14
-#define CFG_GPIO_PHY0_RST	22
-#define CFG_GPIO_DSPIC_READY	51
-#define CFG_GPIO_EEPROM_EXT_WP	55
-#define CFG_GPIO_HIGHSIDE	56
-#define CFG_GPIO_EEPROM_INT_WP	57
-#define CFG_GPIO_BOARD_RESET	58
-#define CFG_GPIO_LIME_S		59
-#define CFG_GPIO_LIME_RST	60
-#define CFG_GPIO_SYSMON_STATUS	62
-#define CFG_GPIO_WATCHDOG	63
+#define CONFIG_SYS_GPIO_PHY1_RST	12
+#define CONFIG_SYS_GPIO_FLASH_WP	14
+#define CONFIG_SYS_GPIO_PHY0_RST	22
+#define CONFIG_SYS_GPIO_DSPIC_READY	51
+#define CONFIG_SYS_GPIO_EEPROM_EXT_WP	55
+#define CONFIG_SYS_GPIO_HIGHSIDE	56
+#define CONFIG_SYS_GPIO_EEPROM_INT_WP	57
+#define CONFIG_SYS_GPIO_BOARD_RESET	58
+#define CONFIG_SYS_GPIO_LIME_S		59
+#define CONFIG_SYS_GPIO_LIME_RST	60
+#define CONFIG_SYS_GPIO_SYSMON_STATUS	62
+#define CONFIG_SYS_GPIO_WATCHDOG	63
 
 /*-----------------------------------------------------------------------
  * PPC440 GPIO Configuration
  */
-#define CFG_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
 {											\
 /* GPIO Core 0 */									\
 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h
index 32403f7..a432850 100644
--- a/include/configs/m501sk.h
+++ b/include/configs/m501sk.h
@@ -41,35 +41,68 @@
 #define CONFIG_INITRD_TAG		1
 
 #define CONFIG_MENUPROMPT		"."
+/*
+ * LowLevel Init
+ */
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR		1
+/* flash */
+#define CONFIG_SYS_MC_PUIA_VAL	0x00000000
+#define CONFIG_SYS_MC_PUP_VAL	0x00000000
+#define CONFIG_SYS_MC_PUER_VAL	0x00000000
+#define CONFIG_SYS_MC_ASR_VAL	0x00000000
+#define CONFIG_SYS_MC_AASR_VAL	0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define CONFIG_SYS_PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
+#define CONFIG_SYS_MCKR_VAL	0x00000202
+
+/* sdram */
+#define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL	0x2188c155 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM	0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1	0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
 
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* Bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* Bytes reserved for initial data */
 
 #define CONFIG_BAUDRATE			115200
 
 /* Hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
-#define CFG_AT91C_BRGR_DIVISOR	33
+#define CONFIG_SYS_AT91C_BRGR_DIVISOR	33
 
 /*
  * Hardware drivers
  */
-#define CFG_FLASH_CFI		1
+#define CONFIG_SYS_FLASH_CFI		1
 #define CONFIG_FLASH_CFI_DRIVER	1
 #define CONFIG_ENV_SECT_SIZE	0x20000
-#define CFG_FLASH_USE_BUFFER_WRITE
-#define CFG_FLASH_PROTECTION	/*for Intel P30 Flash*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION	/*for Intel P30 Flash*/
 #define CONFIG_HARD_I2C
-#define CFG_I2C_SPEED		100
-#define CFG_I2C_SLAVE		0
-#define CFG_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_I2C_SPEED		100
+#define CONFIG_SYS_I2C_SLAVE		0
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
 #undef CONFIG_ENV_IS_IN_EEPROM
-#define CFG_I2C_EEPROM_ADDR	0x50
-#define CFG_I2C_EEPROM_ADDR_LEN	1
-#define CFG_EEPROM_AT24C16
-#define CFG_I2C_RTC_ADDR		0x32
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_AT24C16
+#define CONFIG_SYS_I2C_RTC_ADDR		0x32
 #undef CONFIG_RTC_DS1338
 #define CONFIG_RTC_RS5C372A
 #undef CONFIG_POST
@@ -121,13 +154,13 @@
 #define CONFIG_CMD_IMI
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_FLASH
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 
-#define CFG_HUSH_PARSER
+#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_AUTO_COMPLETE
-#define CFG_PROMPT_HUSH_PS2	    ">>"
+#define CONFIG_SYS_PROMPT_HUSH_PS2	    ">>"
 
-#define CFG_MAX_NAND_DEVICE	0 /* Max number of NAND devices */
+#define CONFIG_SYS_MAX_NAND_DEVICE	0 /* Max number of NAND devices */
 #define SECTORSIZE			     512
 
 #define ADDR_COLUMN		1
@@ -138,9 +171,9 @@
 #define PHYS_SDRAM		0x20000000
 #define PHYS_SDRAM_SIZE	0x2000000 /* 32 megs */
 
-#define CFG_MEMTEST_START	0x21000000 /* PHYS_SDRAM */
-/* CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 */
-#define CFG_MEMTEST_END	0x00100000
+#define CONFIG_SYS_MEMTEST_START	0x21000000 /* PHYS_SDRAM */
+/* CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 */
+#define CONFIG_SYS_MEMTEST_END	0x00100000
 
 #define CONFIG_DRIVER_ETHER
 #define CONFIG_NET_RETRY_COUNT	20
@@ -148,15 +181,15 @@
 
 #define PHYS_FLASH_1		0x10000000
 #define PHYS_FLASH_SIZE	0x800000 /* 8 megs main flash */
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-#define CFG_MAX_FLASH_BANKS	1
-#define CFG_MAX_FLASH_SECT	256
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #ifdef CONFIG_ENV_IS_IN_DATAFLASH
 #define CONFIG_ENV_OFFSET		0x20000
-#define CONFIG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_SIZE		0x2000
 #else
 #define CONFIG_ENV_IS_IN_FLASH
@@ -169,23 +202,23 @@
 #define CONFIG_ENV_SIZE		1024
 #endif
 
-#define CFG_LOAD_ADDR		0x21000000 /* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x21000000 /* default load address */
 
 /* use for protect flash sectors */
-#define CFG_BOOT_SIZE		0x6000 /* 24 KBytes */
-#define CFG_U_BOOT_BASE	(PHYS_FLASH_1 + 0x10000)
-#define CFG_U_BOOT_SIZE	0x10000 /* 64 KBytes */
+#define CONFIG_SYS_BOOT_SIZE		0x6000 /* 24 KBytes */
+#define CONFIG_SYS_U_BOOT_BASE	(PHYS_FLASH_1 + 0x10000)
+#define CONFIG_SYS_U_BOOT_SIZE	0x10000 /* 64 KBytes */
 
-#define CFG_BAUDRATE_TABLE	{ 115200 , 19200, 38400, 57600, 9600 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 , 19200, 38400, 57600, 9600 }
 
-#define CFG_PROMPT		"U-Boot> " /* Monitor Command Prompt */
-#define CFG_CBSIZE		512 /* Console I/O Buffer Size */
-#define CFG_MAXARGS		16 /* max number of command args */
+#define CONFIG_SYS_PROMPT		"U-Boot> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS		16 /* max number of command args */
 /* Print Buffer Size */
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 
-#define CFG_HZ 1000
-#define CFG_HZ_CLOCK		AT91C_MASTER_CLOCK/2
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_HZ_CLOCK		AT91C_MASTER_CLOCK/2
 
 #define CONFIG_STACKSIZE	(32*1024) /* regular stack */
 
diff --git a/include/configs/makalu.h b/include/configs/makalu.h
index b7dddb7..52339f9 100644
--- a/include/configs/makalu.h
+++ b/include/configs/makalu.h
@@ -53,9 +53,9 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE		0xFC000000
-#define CFG_FPGA_BASE		0xF0000000
-#define CFG_PERIPHERAL_BASE	0xEF600000      /* internal peripherals*/
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FPGA_BASE		0xF0000000
+#define CONFIG_SYS_PERIPHERAL_BASE	0xEF600000      /* internal peripherals*/
 
 /*-----------------------------------------------------------------------
  * Initial RAM & Stack Pointer Configuration Options
@@ -71,25 +71,25 @@
  *   the latter of which is less than desireable since it requires
  *   setting up the SDRAM and ECC in assembly code.
  *
- *   To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip
+ *   To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
  *   select on the External Bus Controller (EBC) and then select a
- *   value for 'CFG_INIT_RAM_ADDR' outside of the range of valid,
- *   physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and
- *   select a value for 'CFG_INIT_RAM_ADDR' within the range of valid,
+ *   value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
+ *   physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
+ *   select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
  *   physical SDRAM to use (3).
  *-----------------------------------------------------------------------*/
 
-#define CFG_INIT_DCACHE_CS	4
+#define CONFIG_SYS_INIT_DCACHE_CS	4
 
-#if defined(CFG_INIT_DCACHE_CS)
-#define CFG_INIT_RAM_ADDR	(CFG_SDRAM_BASE + ( 1 << 30))	/*  1 GiB */
+#if defined(CONFIG_SYS_INIT_DCACHE_CS)
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + ( 1 << 30))	/*  1 GiB */
 #else
-#define CFG_INIT_RAM_ADDR	(CFG_SDRAM_BASE + (32 << 20))	/* 32 MiB */
-#endif /* defined(CFG_INIT_DCACHE_CS) */
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + (32 << 20))	/* 32 MiB */
+#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
 
-#define CFG_INIT_RAM_END        (4 << 10)			/*  4 KiB */
-#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_END        (4 << 10)			/*  4 KiB */
+#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 /*
  * If the data cache is being used for the primordial stack and global
@@ -99,20 +99,20 @@
  * for the POST word.
  */
 
-#if defined(CFG_INIT_DCACHE_CS)
-# define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-# define CFG_POST_ALT_WORD_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP6)
+#if defined(CONFIG_SYS_INIT_DCACHE_CS)
+# define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+# define CONFIG_SYS_POST_ALT_WORD_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
 #else
-# define CFG_INIT_EXTRA_SIZE	16
-# define CFG_INIT_SP_OFFSET	(CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE)
-# define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 4)
-# define CFG_OCM_DATA_ADDR	CFG_INIT_RAM_ADDR
-#endif /* defined(CFG_INIT_DCACHE_CS) */
+# define CONFIG_SYS_INIT_EXTRA_SIZE	16
+# define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
+# define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 4)
+# define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_INIT_RAM_ADDR
+#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#undef CFG_EXT_SERIAL_CLOCK			/* no ext. clk		*/
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK			/* no ext. clk		*/
 /* define this if you want console on UART1 */
 #undef CONFIG_UART1_CONSOLE
 
@@ -124,22 +124,22 @@
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI			/* The flash is CFI compatible	*/
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
 
-#define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -150,73 +150,73 @@
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
-#define CFG_MBYTES_SDRAM        (256)		/* 256MB			*/
+#define CONFIG_SYS_MBYTES_SDRAM        (256)		/* 256MB			*/
 
-#define	CFG_SDRAM0_MB0CF_BASE	((  0 << 20) + CFG_SDRAM_BASE)
-#define	CFG_SDRAM0_MB1CF_BASE	((128 << 20) + CFG_SDRAM_BASE)
+#define	CONFIG_SYS_SDRAM0_MB0CF_BASE	((  0 << 20) + CONFIG_SYS_SDRAM_BASE)
+#define	CONFIG_SYS_SDRAM0_MB1CF_BASE	((128 << 20) + CONFIG_SYS_SDRAM_BASE)
 
 /* DDR1/2 SDRAM Device Control Register Data Values */
-#define CFG_SDRAM0_MB0CF	((CFG_SDRAM0_MB0CF_BASE >> 3)	| \
+#define CONFIG_SYS_SDRAM0_MB0CF	((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3)	| \
 				 SDRAM_RXBAS_SDSZ_128MB 	| \
 				 SDRAM_RXBAS_SDAM_MODE2 	| \
 				 SDRAM_RXBAS_SDBE_ENABLE)
-#define CFG_SDRAM0_MB1CF	((CFG_SDRAM0_MB1CF_BASE >> 3)	| \
+#define CONFIG_SYS_SDRAM0_MB1CF	((CONFIG_SYS_SDRAM0_MB1CF_BASE >> 3)	| \
 				 SDRAM_RXBAS_SDSZ_128MB 	| \
 				 SDRAM_RXBAS_SDAM_MODE2 	| \
 				 SDRAM_RXBAS_SDBE_ENABLE)
-#define CFG_SDRAM0_MB2CF	SDRAM_RXBAS_SDBE_DISABLE
-#define CFG_SDRAM0_MB3CF	SDRAM_RXBAS_SDBE_DISABLE
-#define CFG_SDRAM0_MCOPT1	0x04322000
-#define CFG_SDRAM0_MCOPT2	0x00000000
-#define CFG_SDRAM0_MODT0	0x01800000
-#define CFG_SDRAM0_MODT1	0x00000000
-#define CFG_SDRAM0_CODT		0x0080f837
-#define CFG_SDRAM0_RTR		0x06180000
-#define CFG_SDRAM0_INITPLR0	0xa8380000
-#define CFG_SDRAM0_INITPLR1	0x81900400
-#define CFG_SDRAM0_INITPLR2	0x81020000
-#define CFG_SDRAM0_INITPLR3	0x81030000
-#define CFG_SDRAM0_INITPLR4	0x81010404
-#define CFG_SDRAM0_INITPLR5	0x81000542
-#define CFG_SDRAM0_INITPLR6	0x81900400
-#define CFG_SDRAM0_INITPLR7	0x8D080000
-#define CFG_SDRAM0_INITPLR8	0x8D080000
-#define CFG_SDRAM0_INITPLR9	0x8D080000
-#define CFG_SDRAM0_INITPLR10	0x8D080000
-#define CFG_SDRAM0_INITPLR11	0x81000442
-#define CFG_SDRAM0_INITPLR12	0x81010780
-#define CFG_SDRAM0_INITPLR13	0x81010400
-#define CFG_SDRAM0_INITPLR14	0x00000000
-#define CFG_SDRAM0_INITPLR15	0x00000000
-#define CFG_SDRAM0_RQDC		0x80000038
-#define CFG_SDRAM0_RFDC		0x00000209
-#define CFG_SDRAM0_RDCC		0x40000000
-#define CFG_SDRAM0_DLCR		0x030000a5
-#define CFG_SDRAM0_CLKTR	0x80000000
-#define CFG_SDRAM0_WRDTR	0x00000000
-#define CFG_SDRAM0_SDTR1	0x80201000
-#define CFG_SDRAM0_SDTR2	0x32204232
-#define CFG_SDRAM0_SDTR3	0x080b0d1a
-#define CFG_SDRAM0_MMODE	0x00000442
-#define CFG_SDRAM0_MEMODE	0x00000404
+#define CONFIG_SYS_SDRAM0_MB2CF	SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MB3CF	SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MCOPT1	0x04322000
+#define CONFIG_SYS_SDRAM0_MCOPT2	0x00000000
+#define CONFIG_SYS_SDRAM0_MODT0	0x01800000
+#define CONFIG_SYS_SDRAM0_MODT1	0x00000000
+#define CONFIG_SYS_SDRAM0_CODT		0x0080f837
+#define CONFIG_SYS_SDRAM0_RTR		0x06180000
+#define CONFIG_SYS_SDRAM0_INITPLR0	0xa8380000
+#define CONFIG_SYS_SDRAM0_INITPLR1	0x81900400
+#define CONFIG_SYS_SDRAM0_INITPLR2	0x81020000
+#define CONFIG_SYS_SDRAM0_INITPLR3	0x81030000
+#define CONFIG_SYS_SDRAM0_INITPLR4	0x81010404
+#define CONFIG_SYS_SDRAM0_INITPLR5	0x81000542
+#define CONFIG_SYS_SDRAM0_INITPLR6	0x81900400
+#define CONFIG_SYS_SDRAM0_INITPLR7	0x8D080000
+#define CONFIG_SYS_SDRAM0_INITPLR8	0x8D080000
+#define CONFIG_SYS_SDRAM0_INITPLR9	0x8D080000
+#define CONFIG_SYS_SDRAM0_INITPLR10	0x8D080000
+#define CONFIG_SYS_SDRAM0_INITPLR11	0x81000442
+#define CONFIG_SYS_SDRAM0_INITPLR12	0x81010780
+#define CONFIG_SYS_SDRAM0_INITPLR13	0x81010400
+#define CONFIG_SYS_SDRAM0_INITPLR14	0x00000000
+#define CONFIG_SYS_SDRAM0_INITPLR15	0x00000000
+#define CONFIG_SYS_SDRAM0_RQDC		0x80000038
+#define CONFIG_SYS_SDRAM0_RFDC		0x00000209
+#define CONFIG_SYS_SDRAM0_RDCC		0x40000000
+#define CONFIG_SYS_SDRAM0_DLCR		0x030000a5
+#define CONFIG_SYS_SDRAM0_CLKTR	0x80000000
+#define CONFIG_SYS_SDRAM0_WRDTR	0x00000000
+#define CONFIG_SYS_SDRAM0_SDTR1	0x80201000
+#define CONFIG_SYS_SDRAM0_SDTR2	0x32204232
+#define CONFIG_SYS_SDRAM0_SDTR3	0x080b0d1a
+#define CONFIG_SYS_SDRAM0_MMODE	0x00000442
+#define CONFIG_SYS_SDRAM0_MEMODE	0x00000404
 
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */
-#define CFG_I2C_EEPROM_ADDR	0x52	/* I2C boot EEPROM (24C02BN)	*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52	/* I2C boot EEPROM (24C02BN)	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
 
 /* Standard DTT sensor configuration */
 #define CONFIG_DTT_DS1775	1
 #define CONFIG_DTT_SENSORS	{ 0 }
-#define CFG_I2C_DTT_ADDR	0x48
+#define CONFIG_SYS_I2C_DTT_ADDR	0x48
 
 /* RTC configuration */
 #define CONFIG_RTC_X1205	1
-#define CFG_I2C_RTC_ADDR	0x6f
+#define CONFIG_SYS_I2C_RTC_ADDR	0x6f
 
 /*-----------------------------------------------------------------------
  * Ethernet
@@ -259,20 +259,20 @@
 #define CONFIG_CMD_SNTP
 
 /* POST support */
-#define CONFIG_POST		(CFG_POST_CACHE		| \
-				 CFG_POST_CPU		| \
-				 CFG_POST_ETHER		| \
-				 CFG_POST_I2C		| \
-				 CFG_POST_MEMORY	| \
-				 CFG_POST_UART)
+#define CONFIG_POST		(CONFIG_SYS_POST_CACHE		| \
+				 CONFIG_SYS_POST_CPU		| \
+				 CONFIG_SYS_POST_ETHER		| \
+				 CONFIG_SYS_POST_I2C		| \
+				 CONFIG_SYS_POST_MEMORY	| \
+				 CONFIG_SYS_POST_UART)
 
 /* Define here the base-addresses of the UARTs to test in POST */
-#define CFG_POST_UART_TABLE	{UART0_BASE, UART1_BASE}
+#define CONFIG_SYS_POST_UART_TABLE	{UART0_BASE, UART1_BASE}
 
 #define CONFIG_LOGBUFFER
-#define CFG_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/
+#define CONFIG_SYS_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/
 
-#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -285,40 +285,40 @@
 /*-----------------------------------------------------------------------
  * PCIe stuff
  *----------------------------------------------------------------------*/
-#define CFG_PCIE_MEMBASE	0x90000000	/* mapped PCIe memory	*/
-#define CFG_PCIE_MEMSIZE	0x08000000      /* 128 Meg, smallest incr per port */
+#define CONFIG_SYS_PCIE_MEMBASE	0x90000000	/* mapped PCIe memory	*/
+#define CONFIG_SYS_PCIE_MEMSIZE	0x08000000      /* 128 Meg, smallest incr per port */
 
-#define	CFG_PCIE0_CFGBASE	0xa0000000      /* remote access */
-#define	CFG_PCIE0_XCFGBASE	0xb0000000      /* local access */
-#define	CFG_PCIE0_CFGMASK	0xe0000001      /* 512 Meg */
+#define	CONFIG_SYS_PCIE0_CFGBASE	0xa0000000      /* remote access */
+#define	CONFIG_SYS_PCIE0_XCFGBASE	0xb0000000      /* local access */
+#define	CONFIG_SYS_PCIE0_CFGMASK	0xe0000001      /* 512 Meg */
 
-#define	CFG_PCIE1_CFGBASE	0xc0000000      /* remote access */
-#define	CFG_PCIE1_XCFGBASE	0xd0000000      /* local access */
-#define	CFG_PCIE1_CFGMASK	0xe0000001      /* 512 Meg */
+#define	CONFIG_SYS_PCIE1_CFGBASE	0xc0000000      /* remote access */
+#define	CONFIG_SYS_PCIE1_XCFGBASE	0xd0000000      /* local access */
+#define	CONFIG_SYS_PCIE1_CFGMASK	0xe0000001      /* 512 Meg */
 
-#define	CFG_PCIE0_UTLBASE	0xef502000
-#define	CFG_PCIE1_UTLBASE	0xef503000
+#define	CONFIG_SYS_PCIE0_UTLBASE	0xef502000
+#define	CONFIG_SYS_PCIE1_UTLBASE	0xef503000
 
 /* base address of inbound PCIe window */
-#define CFG_PCIE_INBOUND_BASE	0x0000000000000000ULL
+#define CONFIG_SYS_PCIE_INBOUND_BASE	0x0000000000000000ULL
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
 /* Memory Bank 0 (NOR-FLASH) initialization					*/
-#define CFG_EBC_PB0AP		0x08033700
-#define CFG_EBC_PB0CR		(CFG_FLASH_BASE | 0xda000)
+#define CONFIG_SYS_EBC_PB0AP		0x08033700
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
 
 /* Memory Bank 2 (CPLD) initialization						*/
-#define CFG_EBC_PB2AP           0x9400C800
-#define CFG_EBC_PB2CR           0xF0018000 /*  BAS=0x800,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2AP           0x9400C800
+#define CONFIG_SYS_EBC_PB2CR           0xF0018000 /*  BAS=0x800,BS=1MB,BU=R/W,BW=8bit	*/
 
-#define CFG_EBC_CFG		0x7FC00000 /*  EBC0_CFG */
+#define CONFIG_SYS_EBC_CFG		0x7FC00000 /*  EBC0_CFG */
 
 /*-----------------------------------------------------------------------
  * GPIO Setup
  *----------------------------------------------------------------------*/
-#define CFG_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
 {											\
 /* GPIO Core 0 */									\
 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0	EBC_DATA_PAR(0)			*/	\
@@ -356,8 +356,8 @@
 }												\
 }
 
-#define CFG_GPIO_PCIE_RST	23
-#define CFG_GPIO_PCIE_CLKREQ	27
-#define CFG_GPIO_PCIE_WAKE	28
+#define CONFIG_SYS_GPIO_PCIE_RST	23
+#define CONFIG_SYS_GPIO_PCIE_CLKREQ	27
+#define CONFIG_SYS_GPIO_PCIE_WAKE	28
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index c3a600e..e5812ee 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -33,7 +33,7 @@
 #define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
 #define CONFIG_MCC200		1	/* ... on MCC200 board			*/
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz		*/
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz		*/
 
 #define CONFIG_MISC_INIT_R
 
@@ -81,7 +81,7 @@
 #error "Select only one console device!"
 #endif
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #define CONFIG_MII		1
 
@@ -131,11 +131,11 @@
 #define MK_STR(x)		XMK_STR(x)
 
 #ifdef CONFIG_PRS200
-# define CFG__BOARDNAME		"prs200"
-# define CFG__LINUX_CONSOLE	"ttyS0"
+# define CONFIG_SYS__BOARDNAME		"prs200"
+# define CONFIG_SYS__LINUX_CONSOLE	"ttyS0"
 #else
-# define CFG__BOARDNAME		"mcc200"
-# define CFG__LINUX_CONSOLE	"ttyEU5"
+# define CONFIG_SYS__BOARDNAME		"mcc200"
+# define CONFIG_SYS__LINUX_CONSOLE	"ttyEU5"
 #endif
 
 /* Network */
@@ -148,7 +148,7 @@
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"ubootver=" U_BOOT_VERSION "\0"					\
 	"netdev=eth0\0"							\
-	"hostname=" CFG__BOARDNAME "\0"					\
+	"hostname=" CONFIG_SYS__BOARDNAME "\0"					\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/mtdblock2 "			\
@@ -165,10 +165,10 @@
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"net_nfs=tftp 200000 ${bootfile};"				\
 		"run nfsargs addip addcons;bootm\0"			\
-	"console=" CFG__LINUX_CONSOLE "\0"				\
+	"console=" CONFIG_SYS__LINUX_CONSOLE "\0"				\
 	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0"		\
-	"load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0"	\
+	"bootfile=/tftpboot/" CONFIG_SYS__BOARDNAME "/uImage\0"		\
+	"load=tftp 200000 /tftpboot/" CONFIG_SYS__BOARDNAME "/u-boot.bin\0"	\
 	"text_base=" MK_STR(TEXT_BASE) "\0"				\
 	"kernel_addr=0xFC0C0000\0"					\
 	"update=protect off ${text_base} +${filesize};"			\
@@ -181,22 +181,22 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
 
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * Flash configuration (8,16 or 32 MB)
@@ -207,30 +207,30 @@
  *		 0xFF000000 for 16 MB
  *		 0xFF800000 for  8 MB
  */
-#define CFG_FLASH_BASE		0xfc000000
-#define CFG_FLASH_SIZE		0x04000000
+#define CONFIG_SYS_FLASH_BASE		0xfc000000
+#define CONFIG_SYS_FLASH_SIZE		0x04000000
 
-#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
 #define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
 
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_PROTECTION	1	/* hardware flash protection		*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware flash protection		*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
 
 #define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars	*/
 
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -239,43 +239,44 @@
 
 #define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */
 
-#if TEXT_BASE == CFG_FLASH_BASE
-#define CFG_LOWBOOT	1
+#if TEXT_BASE == CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LOWBOOT	1
 #endif
 
 /*
  * Memory map
  */
-#define CFG_MBAR		0xf0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xf0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
  */
-/*#define CONFIG_MPC5xxx_FEC	1*/
+/* #define CONFIG_MPC5xxx_FEC	1 */
+/* #define CONFIG_MPC5xxx_FEC_MII100 */
 /*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
  */
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
 #define CONFIG_PHY_ADDR		1
 
 /*
@@ -288,7 +289,7 @@
 
 #if defined(CONFIG_LCD)
 #define CONFIG_SPLASH_SCREEN	1
-#define CFG_CONSOLE_IS_IN_ENV	1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
 #define LCD_BPP			LCD_MONOCHROME
 #endif
 
@@ -299,64 +300,64 @@
 /* 0x90000004 = 64MB SDRAM */
 #if defined(CONFIG_LCD)
 /* set PSC2 in UART mode */
-#define CFG_GPS_PORT_CONFIG	0x00000044
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x00000044
 #else
-#define CFG_GPS_PORT_CONFIG	0x00000004
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x00000004
 #endif
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /*
  * Various low-level settings
  */
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x0004fb00
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x0004fb00
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
 /* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
-#define CFG_CS2_START		0x80000000
-#define CFG_CS2_SIZE		0x00001000
-#define CFG_CS2_CFG		0x1d300
+#define CONFIG_SYS_CS2_START		0x80000000
+#define CONFIG_SYS_CS2_SIZE		0x00001000
+#define CONFIG_SYS_CS2_CFG		0x1d300
 
 /* Second Quad UART @0x80010000 */
-#define CFG_CS1_START		0x80010000
-#define CFG_CS1_SIZE		0x00001000
-#define CFG_CS1_CFG		0x1d300
+#define CONFIG_SYS_CS1_START		0x80010000
+#define CONFIG_SYS_CS1_SIZE		0x00001000
+#define CONFIG_SYS_CS1_CFG		0x1d300
 
 /* Leica - build revision resistors */
 /*
-#define CFG_CS3_START		0x80020000
-#define CFG_CS3_SIZE		0x00000004
-#define CFG_CS3_CFG		0x1d300
+#define CONFIG_SYS_CS3_START		0x80020000
+#define CONFIG_SYS_CS3_SIZE		0x00000004
+#define CONFIG_SYS_CS3_CFG		0x1d300
 */
 
 /*
@@ -364,10 +365,10 @@
  * console. If undefined - PSC console
  * wil be default
  */
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
 
-#define CFG_RESET_ADDRESS	0xff000000
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
 
 /*
  * QUART Expanders support
@@ -376,8 +377,8 @@
 /*
  * We'll use NS16550 chip routines,
  */
-#define CFG_NS16550		1
-#define CFG_NS16550_SERIAL	1
+#define CONFIG_SYS_NS16550		1
+#define CONFIG_SYS_NS16550_SERIAL	1
 #define CONFIG_CONS_INDEX	1
 /*
  *  To achieve necessary offset on SC16C554
@@ -386,7 +387,7 @@
  * should be 4, because A0-A2 pins are connected
  * to DA2-DA4 address bus lines.
  */
-#define CFG_NS16550_REG_SIZE	4
+#define CONFIG_SYS_NS16550_REG_SIZE	4
 /*
  * LocalPlus Bus already inited in cpu_init_f(),
  * so can work with QUART's chip selects.
@@ -394,9 +395,9 @@
  * A3-A4 (DA5-DA6) lines.
  */
 #if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
-#define CFG_NS16550_COM1	(CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
 #elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
-#define CFG_NS16550_COM1	(CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
 #elif
 #error "Wrong QUART expander number."
 #endif
@@ -405,7 +406,7 @@
  * SC16C554 chip's external crystal oscillator frequency
  * is 7.3728 MHz
  */
-#define CFG_NS16550_CLK		7372800
+#define CONFIG_SYS_NS16550_CLK		7372800
 #endif /* CONFIG_QUART_CONSOLE */
 /*-----------------------------------------------------------------------
  * USB stuff
diff --git a/include/configs/mcu25.h b/include/configs/mcu25.h
index 9a83f08..5f31198 100644
--- a/include/configs/mcu25.h
+++ b/include/configs/mcu25.h
@@ -35,6 +35,12 @@
 #define CONFIG_4xx		1		/* ... PPC4xx family	*/
 #define CONFIG_405GP 1
 #define CONFIG_4xx   1
+#define CONFIG_HOSTNAME		mcu25
+
+/*
+ * Include common defines/options for all boards produced by Netstal Maschinen
+ */
+#include "netstal-common.h"
 
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
 
@@ -45,46 +51,44 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(320 * 1024) /* Reserve 320 kB for Monitor */
-#define CFG_MALLOC_LEN		(256 * 1024) /* Reserve 256 kB for malloc() */
+#define CONFIG_SYS_MONITOR_LEN		(320 * 1024) /* Reserve 320 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024) /* Reserve 256 kB for malloc() */
 
 
-#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
-#define CFG_FLASH_BASE		0xfff80000	/* start of FLASH	*/
-#define CFG_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CONFIG_SYS_FLASH_BASE		0xfff80000	/* start of FLASH	*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 
 /* ... with on-chip memory here (4KBytes) */
-#define CFG_OCM_DATA_ADDR	0xF4000000
-#define CFG_OCM_DATA_SIZE	0x00001000
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF4000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x00001000
 /* Do not set up locked dcache as init ram. */
-#undef CFG_INIT_DCACHE_CS
+#undef CONFIG_SYS_INIT_DCACHE_CS
 
 /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
-#define CFG_TEMP_STACK_OCM	1
+#define CONFIG_SYS_TEMP_STACK_OCM	1
 
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR	/* OCM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE
-#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* OCM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE
+#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_POST_WORD_ADDR
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
 /*
- * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
  * The Linux BASE_BAUD define should match this configuration.
  *    baseBaud = cpuClock/(uartDivisor*16)
- * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  * set Linux BASE_BAUD to 403200.
  */
-#undef CFG_EXT_SERIAL_CLOCK	       /* external serial clock */
-#define CONFIG_SERIAL_MULTI  1
 /* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO */
-#undef	CFG_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD	    691200
 
 /* Size (bytes) of interrupt driven serial port buffer.
  * Set to 0 to use polling instead of interrupts.
@@ -95,27 +99,23 @@
 /* Set console baudrate to 9600 */
 #define CONFIG_BAUDRATE		9600
 
-
-#define CFG_BAUDRATE_TABLE						\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
 /*-----------------------------------------------------------------------
  * Flash
  *----------------------------------------------------------------------*/
 
 /* Use common CFI driver */
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
 /* board provides its own flash_init code */
 #define CONFIG_FLASH_CFI_LEGACY		1
-#define CFG_FLASH_CFI_WIDTH		FLASH_CFI_8BIT
-#define CFG_FLASH_LEGACY_512Kx8 1
+#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_8BIT
+#define CONFIG_SYS_FLASH_LEGACY_512Kx8 1
 
 /* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip */
 
 /*-----------------------------------------------------------------------
  * Environment
@@ -135,7 +135,7 @@
 #ifdef CONFIG_ENV_IS_IN_FLASH
 /* Put the environment in Flash */
 #define CONFIG_ENV_SECT_SIZE	0x10000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR		((-CFG_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		8*1024	/* 8 KB Environment Sector */
 
 /* Address and size of Redundant Environment Sector	*/
@@ -147,77 +147,15 @@
  * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
  * the first internal I2C controller of the PPC440EPx
  *----------------------------------------------------------------------*/
-#define CFG_SPD_BUS_NUM		0
-
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-
-/* This is the 7bit address of the device, not including P. */
-#define CFG_I2C_EEPROM_ADDR 0x50
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-
-/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#undef CFG_I2C_MULTI_EEPROMS
-
-
-#define CONFIG_PREBOOT	"echo;"						\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
+#define CONFIG_SYS_SPD_BUS_NUM		0
 
 /* Setup some board specific values for the default environment variables */
-#define CONFIG_HOSTNAME		mcu25
-#define CONFIG_IPADDR		172.25.1.99
-#define CONFIG_ETHADDR      00:60:13:00:00:00   /* Netstal Machines AG MAC */
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-#define CONFIG_SERVERIP		172.25.1.3
-
-#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
-
-#define	CONFIG_EXTRA_ENV_SETTINGS				\
-	"netdev=eth0\0"							\
-	"loadaddr=0x01000000\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"		\
-	        "bootm\0"						\
-	"rootpath=/home/diagnose/eldk/ppc_4xx\0"			\
-	"bootfile=/tftpboot/mcu25/uImage\0"				\
-	"load=tftp 100000 mcu25/u-boot.bin\0"				\
-	"update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;"	\
-		"cp.b 100000 FFFB0000 50000\0"			        \
-	"upd=run load;run update\0"					\
-	"vx_rom=mcu25/mcu25_vx_rom\0"					\
-	"vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0"		\
-	"vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}"	\
-	" h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0"	\
-	""
-#define CONFIG_BOOTCOMMAND	"run vx"
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR	1	/* PHY address			*/
+#define CONFIG_IPADDR		172.25.1.25
 
-#define CONFIG_PHY_RESET        1	/* reset phy upon startup */
-
-#define CONFIG_HAS_ETH0
-#define CFG_RX_ETH_BUFFER	16 /* Number of ethernet rx buffers & descr */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_NETSTAL_DEF_ENV						\
+	CONFIG_NETSTAL_DEF_ENV_POWERPC					\
+	""
 
 /*
  * BOOTP options
@@ -253,100 +191,93 @@
 #define SPD_EEPROM_ADDRESS      0x50
 
 /* POST support */
-#define CONFIG_POST		(CFG_POST_MEMORY   | \
-				 CFG_POST_CPU	   | \
-				 CFG_POST_UART	   | \
-				 CFG_POST_I2C	   | \
-				 CFG_POST_CACHE	   | \
-				 CFG_POST_ETHER	   | \
-				 CFG_POST_SPR)
-
-#define CFG_POST_UART_TABLE	{UART0_BASE}
-#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_UART	   | \
+				 CONFIG_SYS_POST_I2C	   | \
+				 CONFIG_SYS_POST_CACHE	   | \
+				 CONFIG_SYS_POST_ETHER	   | \
+				 CONFIG_SYS_POST_SPR)
+
+#define CONFIG_SYS_POST_UART_TABLE	{UART0_BASE}
+#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 #undef  CONFIG_LOGBUFFER
-#define CFG_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/
-#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+#define CONFIG_SYS_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  *----------------------------------------------------------------------*/
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-	#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  */
 
-#define CFG_EBC_CFG            0x98400000
+#define CONFIG_SYS_EBC_CFG            0x98400000
 
 /* Memory Bank 0 (Flash Bank 0) initialization	*/
-#define CFG_EBC_PB0AP		0x02005400
-#define CFG_EBC_PB0CR		0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit*/
+#define CONFIG_SYS_EBC_PB0AP		0x02005400
+#define CONFIG_SYS_EBC_PB0CR		0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit*/
 
-#define CFG_EBC_PB1AP		0x03041200
-#define CFG_EBC_PB1CR		0x7009A000  /* BAS=,BS=MB,BU=R/W,BW=bit	*/
+#define CONFIG_SYS_EBC_PB1AP		0x03041200
+#define CONFIG_SYS_EBC_PB1CR		0x7009A000  /* BAS=,BS=MB,BU=R/W,BW=bit	*/
 
-#define CFG_EBC_PB2AP		0x01845200u  /* BAS=,BS=MB,BU=R/W,BW=bit */
-#define CFG_EBC_PB2CR		0x7A09A000u
+#define CONFIG_SYS_EBC_PB2AP		0x01845200u  /* BAS=,BS=MB,BU=R/W,BW=bit */
+#define CONFIG_SYS_EBC_PB2CR		0x7A09A000u
 
-#define CFG_EBC_PB3AP		0x01845200u  /* BAS=,BS=MB,BU=R/W,BW=bit */
-#define CFG_EBC_PB3CR		0x7B09A000u
+#define CONFIG_SYS_EBC_PB3AP		0x01845200u  /* BAS=,BS=MB,BU=R/W,BW=bit */
+#define CONFIG_SYS_EBC_PB3CR		0x7B09A000u
 
-#define CFG_EBC_PB4AP		0x01845200u  /* BAS=,BS=MB,BU=R/W,BW=bit */
-#define CFG_EBC_PB4CR		0x7C09A000u
+#define CONFIG_SYS_EBC_PB4AP		0x01845200u  /* BAS=,BS=MB,BU=R/W,BW=bit */
+#define CONFIG_SYS_EBC_PB4CR		0x7C09A000u
 
-#define CFG_EBC_PB5AP		0x00800200u
-#define CFG_EBC_PB5CR		0x7D81A000u
+#define CONFIG_SYS_EBC_PB5AP		0x00800200u
+#define CONFIG_SYS_EBC_PB5CR		0x7D81A000u
 
-#define CFG_EBC_PB6AP		0x01040200u
-#define CFG_EBC_PB6CR		0x7D91A000u
+#define CONFIG_SYS_EBC_PB6AP		0x01040200u
+#define CONFIG_SYS_EBC_PB6CR		0x7D91A000u
 
-#define CFG_GPIO0_OR		0x087FFFFF  /* GPIO value */
-#define CFG_GPIO0_TCR		0x7FFF8000  /* GPIO value */
-#define CFG_GPIO0_ODR		0xFFFF0000  /* GPIO value */
+#define CONFIG_SYS_GPIO0_OR		0x087FFFFF  /* GPIO value */
+#define CONFIG_SYS_GPIO0_TCR		0x7FFF8000  /* GPIO value */
+#define CONFIG_SYS_GPIO0_ODR		0xFFFF0000  /* GPIO value */
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /* Init Memory Controller:
  *
  * BR0/1 and OR0/1 (FLASH)
  */
 
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	*/
 #define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
 
 
 /* Configuration Port location */
 #define CONFIG_PORT_ADDR	0xF0000500
 
-#define CFG_HUSH_PARSER                 /* use "hush" command parser    */
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER                 /* use "hush" command parser    */
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
@@ -354,8 +285,4 @@
 #define CONFIG_KGDB_SER_INDEX	2	    /* which serial port to use */
 #endif
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h
index 8b13fc0..4a93b58 100644
--- a/include/configs/mecp5200.h
+++ b/include/configs/mecp5200.h
@@ -45,7 +45,7 @@
 #define CONFIG_MECP5200		1	/* ... on MECP5200  board */
 #define CONFIG_MPC5200_DDR      1       /* ... use DDR RAM      */
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
@@ -61,7 +61,7 @@
 #else
 #define CONFIG_BAUDRATE		9600	/* ... at 115200 bps */
 #endif
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 
 #ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
@@ -70,7 +70,7 @@
 #if 0 /* test-only !!! */
 #define CONFIG_NET_MULTI	1
 #define CONFIG_EEPRO100		1
-#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
 #define CONFIG_NS8382X		1
 #endif
 
@@ -113,12 +113,12 @@
 
 
 #if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
-#   define CFG_LOWBOOT		1
-#   define CFG_LOWBOOT16	1
+#   define CONFIG_SYS_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT16	1
 #endif
 #if (TEXT_BASE == 0xFF800000)		/* Boot low with  8 MB Flash */
-#   define CFG_LOWBOOT		1
-#   define CFG_LOWBOOT08	1
+#   define CONFIG_SYS_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT08	1
 #endif
 
 /*
@@ -156,36 +156,36 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133			/* define for 133MHz speed */
+#undef CONFIG_SYS_IPBSPEED_133			/* define for 133MHz speed */
 #endif
 /*
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
 
-#define CFG_I2C_SPEED		86000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		86000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration
  */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CFG_I2C_EEPROM_ADDR_LEN		2
-#define CFG_EEPROM_PAGE_WRITE_BITS	5
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
-#define CFG_I2C_MULTI_EEPROMS		1
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CONFIG_SYS_I2C_MULTI_EEPROMS		1
 /*
  * Flash configuration
  */
-#define CFG_FLASH_BASE		0xFFC00000
-#define CFG_FLASH_SIZE		0x00400000
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x003E0000)
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CFG_MAX_FLASH_SECT	512
+#define CONFIG_SYS_FLASH_BASE		0xFFC00000
+#define CONFIG_SYS_FLASH_SIZE		0x00400000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x003E0000)
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	512
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
 
 /*
  * Environment settings
@@ -204,49 +204,50 @@
 #endif
 
 #define CONFIG_FLASH_CFI_DRIVER	1	   /* Flash is CFI conformant		*/
-#define CFG_FLASH_CFI		1	   /* Flash is CFI conformant		*/
-#define CFG_FLASH_PROTECTION	1	   /* use hardware protection		*/
+#define CONFIG_SYS_FLASH_CFI		1	   /* Flash is CFI conformant		*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	   /* use hardware protection		*/
 #if 0
-#define CFG_FLASH_USE_BUFFER_WRITE 1       /* use buffered writes (20x faster)  */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1       /* use buffered writes (20x faster)  */
 #endif
-#define CFG_FLASH_INCREMENT	0x00400000 /* size of  flash bank		*/
-#define CFG_FLASH_BANKS_LIST  { CFG_FLASH_BASE }
-#define CFG_FLASH_EMPTY_INFO	1	   /* show if bank is empty		*/
+#define CONFIG_SYS_FLASH_INCREMENT	0x00400000 /* size of  flash bank		*/
+#define CONFIG_SYS_FLASH_BANKS_LIST  { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO	1	   /* show if bank is empty		*/
 
 
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
 /*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
  */
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
 #define CONFIG_PHY_ADDR		0x00
 #define CONFIG_UDP_CHECKSUM     1
 
@@ -254,62 +255,62 @@
 /*
  * GPIO configuration
  */
-#define CFG_GPS_PORT_CONFIG	0x01052444
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x01052444
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
-#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*
  * Various low-level settings
  */
 #if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 #else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
 #endif
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x00085d00
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00085d00
 
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
-#define CFG_CS1_START		0xfd000000
-#define CFG_CS1_SIZE		0x00010000
-#define CFG_CS1_CFG		0x10101410
+#define CONFIG_SYS_CS1_START		0xfd000000
+#define CONFIG_SYS_CS1_SIZE		0x00010000
+#define CONFIG_SYS_CS1_CFG		0x10101410
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
 
-#define CFG_RESET_ADDRESS	0xff000000
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
 
 /*-----------------------------------------------------------------------
  * USB stuff
@@ -331,23 +332,23 @@
 #define	CONFIG_IDE_RESET		/* reset for ide supported	*/
 #define CONFIG_IDE_PREINIT
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(0x0060)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005C)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
 
 /* Interval between registers		*/
-#define CFG_ATA_STRIDE		4
+#define CONFIG_SYS_ATA_STRIDE		4
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h
index 23af3ec..79c7050 100644
--- a/include/configs/mgcoge.h
+++ b/include/configs/mgcoge.h
@@ -32,11 +32,12 @@
 #define CONFIG_MPC8247		1
 #define CONFIG_MPC8272_FAMILY   1
 #define CONFIG_MGCOGE		1
+#define CONFIG_HOSTNAME		mgcoge
 
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
-/* Do boardspecific init */
-#define CONFIG_BOARD_EARLY_INIT_R       1
+/* include common defines/options for all Keymile boards */
+#include "keymile-common.h"
 
 /*
  * Select serial console configuration
@@ -49,6 +50,8 @@
 #undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
 #undef	CONFIG_CONS_NONE		/* It's not on external UART */
 #define CONFIG_CONS_INDEX	2	/* SMC2 is used for console  */
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
 
 /*
  * Select ethernet configuration
@@ -64,27 +67,24 @@
 #define	CONFIG_ETHER_ON_SCC		/* Ethernet is on SCC */
 #undef	CONFIG_ETHER_ON_FCC		/* Ethernet is not on FCC     */
 #undef	CONFIG_ETHER_NONE		/* No external Ethernet   */
+#define CONFIG_NET_MULTI	1
 
 #define CONFIG_ETHER_INDEX	4
-#define CFG_SCC_TOUT_LOOP	10000000
+#define CONFIG_SYS_SCC_TOUT_LOOP	10000000
 
-# define CFG_CMXSCR_VALUE	(CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
+# define CONFIG_SYS_CMXSCR_VALUE	(CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
 
 #ifndef CONFIG_8260_CLKIN
 #define CONFIG_8260_CLKIN	66000000	/* in Hz */
 #endif
 
-#define CONFIG_BAUDRATE		115200
+#define BOOTFLASH_START	FE000000
+#define CONFIG_PRAM	512	/* protected RAM [KBytes] */
 
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
+#define MTDIDS_DEFAULT		"nor0=boot,nor1=app"
+#define MTDPARTS_DEFAULT	\
+	"mtdparts=boot:384k(u-boot),128k(env),128k(envred),3456k(free);" \
+	"app:3m(esw0),10m(rootfs0),3m(esw1),10m(rootfs1),1m(var),5m(cfg)"
 
 /*
  * Default environment settings
@@ -118,111 +118,138 @@
 		"tftp ${ramdisk_addr} ${ramdisk_file}; "			\
 		"run ramargs addip; "						\
 		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"		\
+	"EEprom_ivm=pca9544a:70:4 \0"						\
+	"mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0"				\
 	""
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
-
-#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size  */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */
-
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFE000000
-#define CFG_FLASH_SIZE		32
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_SIZE		32
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_MAX_FLASH_BANKS	2	/* max num of flash banks	*/
-#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of flash banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
 
-#define CFG_FLASH_BASE_1	0x50000000
-#define CFG_FLASH_SIZE_1	64
+#define CONFIG_SYS_FLASH_BASE_1	0x50000000
+#define CONFIG_SYS_FLASH_SIZE_1	64
 
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE_1 }
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 }
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256KB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10)     /* Reserve 384KB for Monitor */
 
 #define CONFIG_ENV_IS_IN_FLASH
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x4000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_OFFSET	CONFIG_SYS_MONITOR_LEN
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
 #endif /* CONFIG_ENV_IS_IN_FLASH */
+#define CONFIG_ENV_BUFFER_PRINT		1
+
+/* enable I2C and select the hardware/software driver */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define	CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+#define CONFIG_SYS_I2C_SPEED		50000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_IMMR		0xF0000000
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
 
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#define CONFIG_I2C_MULTI_BUS	1
+#define CONFIG_I2C_CMD_TREE	1
+#define CONFIG_SYS_MAX_I2C_BUS		2
+#define CONFIG_SYS_I2C_INIT_BOARD	1
+#define CONFIG_I2C_MUX		1
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_MULTI_EEPROMS	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* Support the IVM EEprom */
+#define	CONFIG_SYS_IVM_EEPROM_ADR	0x50
+#define CONFIG_SYS_IVM_EEPROM_MAX_LEN	0x400
+#define CONFIG_SYS_IVM_EEPROM_PAGE_LEN	0x100
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
+#define CONFIG_DTT_LM75		1	/* ON Semi's LM75		*/
+#define CONFIG_DTT_SENSORS	{0}	/* Sensor addresses		*/
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
+#define CONFIG_SYS_DTT_BUS_NUM		(CONFIG_SYS_MAX_I2C_BUS)
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+#define CONFIG_SYS_IMMR		0xF0000000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* Hard reset configuration word */
-#define CFG_HRCW_MASTER		0x0604b211
+#define CONFIG_SYS_HRCW_MASTER		0x0604b211
 
 /* No slaves */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot                  */
 
-#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
 
-#define CFG_HID2		0
+#define CONFIG_SYS_HID2		0
 
-#define CFG_SIUMCR		0x4020c200
-#define CFG_SYPCR		0xFFFFFFC3
-#define CFG_BCR			0x10000000
-#define CFG_SCCR		(SCCR_PCI_MODE | SCCR_PCI_MODCK)
+#define CONFIG_SYS_SIUMCR		0x4020c200
+#define CONFIG_SYS_SYPCR		0xFFFFFFC3
+#define CONFIG_SYS_BCR			0x10000000
+#define CONFIG_SYS_SCCR		(SCCR_PCI_MODE | SCCR_PCI_MODCK)
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register                                     5-5
  *-----------------------------------------------------------------------
  * turn on Checkstop Reset Enable
  */
-#define CFG_RMR         0
+#define CONFIG_SYS_RMR         0
 
 /*-----------------------------------------------------------------------
  * TMCNTSC - Time Counter Status and Control                     4-40
@@ -230,7 +257,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control                 4-42
@@ -238,13 +265,13 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration                         13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR        0
+#define CONFIG_SYS_RCCR        0
 
 /*
  * Init Memory Controller:
@@ -259,12 +286,12 @@
  */
 /* Bank 0 - FLASH
  */
-#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_8			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)	|\
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV2			|\
 			 ORxG_SCY_5_CLK			|\
@@ -274,33 +301,33 @@
 /* Bank 1 - 60x bus SDRAM
  */
 #define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-#define CFG_GLOBAL_SDRAM_LIMIT	(256 << 20)	/* less than 256 MB */
+#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(256 << 20)	/* less than 256 MB */
 
-#define CFG_MPTPR       0x1800
+#define CONFIG_SYS_MPTPR       0x1800
 
 /*-----------------------------------------------------------------------------
  * Address for Mode Register Set (MRS) command
  *-----------------------------------------------------------------------------
  */
-#define CFG_MRS_OFFS	0x00000110
-#define CFG_PSRT        0x0e
+#define CONFIG_SYS_MRS_OFFS	0x00000110
+#define CONFIG_SYS_PSRT        0x0e
 
-#define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_64                      |\
 			 BRx_MS_SDRAM_P                 |\
 			 BRx_V)
 
-#define CFG_OR1_PRELIM	CFG_OR1
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR1
 
 /* SDRAM initialization values
 */
 
-#define CFG_OR1    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+#define CONFIG_SYS_OR1    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_8                     |\
 			 ORxS_ROWST_PBI0_A7		|\
 			 ORxS_NUMR_13)
 
-#define CFG_PSDMR  (PSDMR_SDAM_A14_IS_A5 |\
+#define CONFIG_SYS_PSDMR  (PSDMR_SDAM_A14_IS_A5 |\
 			 PSDMR_BSMA_A14_A16           |\
 			 PSDMR_SDA10_PBI0_A9		|\
 			 PSDMR_RFRC_5_CLK               |\
@@ -312,28 +339,41 @@
 
 /* GPIO/PIGGY on CS3 initialization values
 */
-#define CFG_PIGGY_BASE	0x30000000
-#define CFG_PIGGY_SIZE	128
+#define CONFIG_SYS_PIGGY_BASE	0x30000000
+#define CONFIG_SYS_PIGGY_SIZE	128
 
-#define CFG_BR3_PRELIM	((CFG_PIGGY_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\
 			 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 
-#define CFG_OR3_PRELIM	(MEG_TO_AM(CFG_PIGGY_SIZE) |\
+#define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\
+			 ORxG_CSNT | ORxG_ACS_DIV2 |\
+			 ORxG_SCY_3_CLK | ORxG_TRLX )
+
+/* Board FPGA on CS4 initialization values
+*/
+#define CONFIG_SYS_FPGA_BASE	0x40000000
+#define CONFIG_SYS_FPGA_SIZE	1 /*1KB*/
+
+#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
+			BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
+
+#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
 			 ORxG_CSNT | ORxG_ACS_DIV2 |\
 			 ORxG_SCY_3_CLK | ORxG_TRLX )
 
 /* CFG-Flash on CS5 initialization values
 */
-#define CFG_BR5_PRELIM	((CFG_FLASH_BASE_1 & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR5_PRELIM	((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
 			 BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
 
-#define CFG_OR5_PRELIM	(MEG_TO_AM(CFG_FLASH_SIZE_1) |\
+#define CONFIG_SYS_OR5_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1) |\
 			 ORxG_CSNT | ORxG_ACS_DIV2 |\
 			 ORxG_SCY_5_CLK | ORxG_TRLX )
 
-#define	CFG_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
+#define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
 
 /* pass open firmware flat tree */
+#define CONFIG_FIT		1
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 
diff --git a/include/configs/mgsuvd.h b/include/configs/mgsuvd.h
index 740767e..4623e4c 100644
--- a/include/configs/mgsuvd.h
+++ b/include/configs/mgsuvd.h
@@ -35,30 +35,29 @@
 
 #define CONFIG_MPC866		1	/* This is a MPC866 CPU		*/
 #define CONFIG_MGSUVD		1	/* ...on a mgsuvd board	*/
+#define CONFIG_HOSTNAME		mgsuvd
 
-/* Do boardspecific init */
-#define CONFIG_BOARD_EARLY_INIT_R       1
+/* include common defines/options for all Keymile boards */
+#include "keymile-common.h"
 
 #define CONFIG_8xx_GCLK_FREQ		66000000
 
-#define CFG_SMC_UCODE_PATCH	1	/* Relocate SMC1 */
-#define CFG_SMC_DPMEM_OFFSET	0x1fc0
+#define CONFIG_SYS_SMC_UCODE_PATCH	1	/* Relocate SMC1 */
+#define CONFIG_SYS_SMC_DPMEM_OFFSET	0x1fc0
 #define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
 
-#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+#define CONFIG_SYS_CPM_BOOTCOUNT_ADDR	0x1eb0	/* In case of SMC relocation, the
+					 * default value is not working */
 
-#define CONFIG_BOOTCOUNT_LIMIT
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+#define BOOTFLASH_START	F0000000
+#define CONFIG_PRAM	512	/* protected RAM [KBytes] */
 
 #define CONFIG_PREBOOT	"echo;" \
 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 	"echo"
 
-#undef	CONFIG_BOOTARGS
-
 #define CONFIG_EXTRA_ENV_SETTINGS						\
 	"netdev=eth0\0"								\
 	"addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0"	\
@@ -86,67 +85,12 @@
 		"cp.b 200000 f0000000 ${filesize};"				\
 		"protect on f0000000 +${filesize}\0"				\
 	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
 
 #undef CONFIG_RTC_MPC8xx		/* MPC866 does not support RTC	*/
 
 #define	CONFIG_TIMESTAMP		/* but print image timestmps	*/
 
 /*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
  * You should know what you are doing if you make changes here.
@@ -154,65 +98,64 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xf0000000
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xf0000000
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_FLASH_SIZE		32
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_FLASH_SIZE		32
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
 
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
-#define CONFIG_ENV_SIZE		0x08000 /* Total Size of Environment Sector	*/
-#define CONFIG_ENV_SECT_SIZE	0x40000 /* Total Size of Environment Sector	*/
+#define CONFIG_ENV_OFFSET	CONFIG_SYS_MONITOR_LEN
+#define CONFIG_ENV_SIZE		0x04000 /* Total Size of Environment Sector	*/
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define CONFIG_ENV_BUFFER_PRINT		1
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -221,27 +164,27 @@
  *-----------------------------------------------------------------------
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
-#define CFG_SYPCR	0xffffff89
+#define CONFIG_SYS_SYPCR	0xffffff89
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration				11-6
  *-----------------------------------------------------------------------
  */
-#define CFG_SIUMCR	0x00610480
+#define CONFIG_SYS_SIUMCR	0x00610480
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -250,9 +193,9 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	0x01800000
-#define CFG_SCCR	0x01800000
+#define CONFIG_SYS_SCCR	0x01800000
 
-#define CFG_DER 0
+#define CONFIG_SYS_DER 0
 
 /*
  * Init Memory Controller:
@@ -266,14 +209,14 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing: Default value of OR0 after reset
  */
-#define CFG_OR0_PRELIM	0xfe000954
-#define CFG_BR0_PRELIM	0xf0000401
+#define CONFIG_SYS_OR0_PRELIM	0xfe000954
+#define CONFIG_SYS_BR0_PRELIM	0xf0000401
 
 /*
  * BR1 and OR1 (SDRAM)
@@ -283,16 +226,16 @@
 #define SDRAM_MAX_SIZE		(64 << 20)	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR1_PRELIM	0xfc000800
-#define CFG_BR1_PRELIM	(0x000000C0 | 0x01)
+#define CONFIG_SYS_OR1_PRELIM	0xfc000800
+#define CONFIG_SYS_BR1_PRELIM	(0x000000C0 | 0x01)
 
-#define CFG_MPTPR	0x0200
+#define CONFIG_SYS_MPTPR	0x0200
 /* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
    1 Write loop Cycle (not used), 1 Timer Loop Cycle */
-#define CFG_MBMR	0x10964111
-#define CFG_MAR		0x00000088
+#define CONFIG_SYS_MBMR	0x10964111
+#define CONFIG_SYS_MAR		0x00000088
 
 /*
  * 4096	Rows from SDRAM example configuration
@@ -301,13 +244,13 @@
  * 4	Number of refresh cycles per period
  * 64	Refresh cycle in ms per number of rows
  */
-#define CFG_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))
 
 /* GPIO/PIGGY on CS3 initialization values
 */
-#define CFG_PIGGY_BASE	(0x30000000)
-#define CFG_OR3_PRELIM	(0xfe000d24)
-#define CFG_BR3_PRELIM	(0x30000401)
+#define CONFIG_SYS_PIGGY_BASE	(0x30000000)
+#define CONFIG_SYS_OR3_PRELIM	(0xfe000d24)
+#define CONFIG_SYS_BR3_PRELIM	(0x30000401)
 
 /*
  * Internal Definitions
@@ -325,9 +268,72 @@
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 
-#define OF_CPU			"PowerPC,866@0"
-#define OF_SOC			"soc@fff00000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
 #define OF_STDOUT_PATH		"/soc/cpm/serial@a80"
 
+/* enable I2C and select the hardware/software driver */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define	CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+#define CONFIG_SYS_I2C_SPEED		50000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define I2C_SOFT_DECLARATIONS
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define I2C_BASE_DIR	((u16 *)(CONFIG_SYS_PIGGY_BASE + 0x04))
+#define I2C_BASE_PORT	((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x09))
+
+#define SDA_BIT		0x40
+#define SCL_BIT		0x80
+#define SDA_CONF	0x1000
+#define SCL_CONF	0x2000
+
+#define I2C_ACTIVE	do {} while (0)
+#define I2C_TRISTATE	do {} while (0)
+#define I2C_READ	((in_8(I2C_BASE_PORT) & SDA_BIT) == SDA_BIT)
+#define I2C_SDA(bit)	if(bit) { \
+				clrbits(be16, I2C_BASE_DIR, SDA_CONF); \
+			} else { \
+				clrbits(8, I2C_BASE_PORT, SDA_BIT); \
+				setbits(be16, I2C_BASE_DIR, SDA_CONF); \
+			}
+#define I2C_SCL(bit)	if(bit) { \
+				clrbits(be16, I2C_BASE_DIR, SCL_CONF); \
+			} else { \
+				clrbits(8, I2C_BASE_PORT, SCL_BIT); \
+				setbits(be16, I2C_BASE_DIR, SCL_CONF); \
+			}
+#define I2C_DELAY	udelay(50)	/* 1/4 I2C clock duration */
+
+#define CONFIG_I2C_MULTI_BUS	1
+#define CONFIG_I2C_CMD_TREE	1
+#define CONFIG_SYS_MAX_I2C_BUS		2
+#define CONFIG_SYS_I2C_INIT_BOARD	1
+#define CONFIG_I2C_MUX		1
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_MULTI_EEPROMS	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* Support the IVM EEprom */
+#define	CONFIG_SYS_IVM_EEPROM_ADR	0x50
+#define CONFIG_SYS_IVM_EEPROM_MAX_LEN	0x400
+#define CONFIG_SYS_IVM_EEPROM_PAGE_LEN	0x100
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
+#define CONFIG_DTT_LM75		1	/* ON Semi's LM75		*/
+#define CONFIG_DTT_SENSORS	{0, 2, 4, 6}	/* Sensor addresses		*/
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
+#define CONFIG_SYS_DTT_BUS_NUM		(CONFIG_SYS_MAX_I2C_BUS)
+
+#define MTDIDS_DEFAULT		"nor0=app"
+#define MTDPARTS_DEFAULT ( \
+	"mtdparts=app:384k(u-boot),128k(env),128k(envred),128k(free),"	\
+	"1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)")
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
new file mode 100644
index 0000000..ac18c87
--- /dev/null
+++ b/include/configs/microblaze-generic.h
@@ -0,0 +1,302 @@
+/*
+ * (C) Copyright 2007-2008 Michal Simek
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "../board/xilinx/microblaze-generic/xparameters.h"
+
+#define	CONFIG_MICROBLAZE	1	/* MicroBlaze CPU */
+#define	MICROBLAZE_V5		1
+
+/* uart */
+#ifdef XILINX_UARTLITE_BASEADDR
+	#define	CONFIG_XILINX_UARTLITE
+	#define	CONFIG_SERIAL_BASE	XILINX_UARTLITE_BASEADDR
+	#define	CONFIG_BAUDRATE		XILINX_UARTLITE_BAUDRATE
+	#define	CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
+	#define CONSOLE_ARG	"console=console=ttyUL0,115200\0"
+#elif XILINX_UART16550_BASEADDR
+	#define CONFIG_SYS_NS16550	1
+	#define CONFIG_SYS_NS16550_SERIAL
+	#define CONFIG_SYS_NS16550_REG_SIZE	-4
+	#define CONFIG_CONS_INDEX	1
+	#define CONFIG_SYS_NS16550_COM1	(XILINX_UART16550_BASEADDR + 0x1000 + 0x3)
+	#define CONFIG_SYS_NS16550_CLK	XILINX_UART16550_CLOCK_HZ
+	#define	CONFIG_BAUDRATE		115200
+
+	/* The following table includes the supported baudrates */
+	#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+	#define CONSOLE_ARG	"console=console=ttyS0,115200\0"
+#else
+	#error Undefined uart
+#endif
+
+/* setting reset address */
+/*#define	CONFIG_SYS_RESET_ADDRESS	TEXT_BASE*/
+
+/* ethernet */
+#ifdef XILINX_EMAC_BASEADDR
+	#define CONFIG_XILINX_EMAC	1
+	#define CONFIG_SYS_ENET
+#elif XILINX_EMACLITE_BASEADDR
+	#define CONFIG_XILINX_EMACLITE	1
+	#define CONFIG_SYS_ENET
+#elif XILINX_LLTEMAC_BASEADDR
+	#define CONFIG_XILINX_LL_TEMAC	1
+	#define CONFIG_SYS_ENET
+#endif
+
+#undef ET_DEBUG
+
+/* gpio */
+#ifdef XILINX_GPIO_BASEADDR
+	#define	CONFIG_SYS_GPIO_0		1
+	#define	CONFIG_SYS_GPIO_0_ADDR		XILINX_GPIO_BASEADDR
+#endif
+
+/* interrupt controller */
+#ifdef XILINX_INTC_BASEADDR
+	#define	CONFIG_SYS_INTC_0		1
+	#define	CONFIG_SYS_INTC_0_ADDR		XILINX_INTC_BASEADDR
+	#define	CONFIG_SYS_INTC_0_NUM		XILINX_INTC_NUM_INTR_INPUTS
+#endif
+
+/* timer */
+#ifdef XILINX_TIMER_BASEADDR
+	#if (XILINX_TIMER_IRQ != -1)
+		#define	CONFIG_SYS_TIMER_0		1
+		#define	CONFIG_SYS_TIMER_0_ADDR	XILINX_TIMER_BASEADDR
+		#define	CONFIG_SYS_TIMER_0_IRQ		XILINX_TIMER_IRQ
+		#define	FREQUENCE		XILINX_CLOCK_FREQ
+		#define	CONFIG_SYS_TIMER_0_PRELOAD	( FREQUENCE/1000 )
+	#endif
+#elif XILINX_CLOCK_FREQ
+	#define	CONFIG_XILINX_CLOCK_FREQ	XILINX_CLOCK_FREQ
+#else
+	#error BAD CLOCK FREQ
+#endif
+/* FSL */
+/* #define	CONFIG_SYS_FSL_2 */
+/* #define	FSL_INTR_2	1 */
+
+/*
+ * memory layout - Example
+ * TEXT_BASE = 0x1200_0000;
+ * CONFIG_SYS_SRAM_BASE = 0x1000_0000;
+ * CONFIG_SYS_SRAM_SIZE = 0x0400_0000;
+ *
+ * CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
+ * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
+ * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
+ *
+ * 0x1000_0000	CONFIG_SYS_SDRAM_BASE
+ *					FREE
+ * 0x1200_0000	TEXT_BASE
+ *		U-BOOT code
+ * 0x1202_0000
+ *					FREE
+ *
+ *					STACK
+ * 0x13F7_F000	CONFIG_SYS_MALLOC_BASE
+ *					MALLOC_AREA	256kB	Alloc
+ * 0x11FB_F000	CONFIG_SYS_MONITOR_BASE
+ *					MONITOR_CODE	256kB	Env
+ * 0x13FF_F000	CONFIG_SYS_GBL_DATA_OFFSET
+ *					GLOBAL_DATA	4kB	bd, gd
+ * 0x1400_0000	CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE
+ */
+
+/* ddr sdram - main memory */
+#define	CONFIG_SYS_SDRAM_BASE		XILINX_RAM_START
+#define	CONFIG_SYS_SDRAM_SIZE		XILINX_RAM_SIZE
+#define	CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define	CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)
+
+/* global pointer */
+#define	CONFIG_SYS_GBL_DATA_SIZE	0x1000	/* size of global data */
+/* start of global data */
+#define	CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
+
+/* monitor code */
+#define	SIZE			0x40000
+#define	CONFIG_SYS_MONITOR_LEN		SIZE
+#define	CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN)
+#define	CONFIG_SYS_MONITOR_END		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define	CONFIG_SYS_MALLOC_LEN		SIZE
+#define	CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+
+/* stack */
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_MONITOR_BASE
+
+/*#define	RAMENV */
+#define	FLASH
+
+#ifdef FLASH
+	#define	CONFIG_SYS_FLASH_BASE		XILINX_FLASH_START
+	#define	CONFIG_SYS_FLASH_SIZE		XILINX_FLASH_SIZE
+	#define	CONFIG_SYS_FLASH_CFI		1
+	#define	CONFIG_FLASH_CFI_DRIVER	1
+	#define	CONFIG_SYS_FLASH_EMPTY_INFO	1	/* ?empty sector */
+	#define	CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+	#define	CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip */
+	#define	CONFIG_SYS_FLASH_PROTECTION		/* hardware flash protection */
+
+	#ifdef	RAMENV
+		#define	CONFIG_ENV_IS_NOWHERE	1
+		#define	CONFIG_ENV_SIZE		0x1000
+		#define	CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+
+	#else	/* !RAMENV */
+		#define	CONFIG_ENV_IS_IN_FLASH	1
+		#define	CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+		#define	CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
+		#define	CONFIG_ENV_SIZE		0x20000
+	#endif /* !RAMBOOT */
+#else /* !FLASH */
+	/* ENV in RAM */
+	#define	CONFIG_SYS_NO_FLASH		1
+	#define	CONFIG_ENV_IS_NOWHERE	1
+	#define	CONFIG_ENV_SIZE		0x1000
+	#define	CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+	#define	CONFIG_SYS_FLASH_PROTECTION		/* hardware flash protection */
+#endif /* !FLASH */
+
+/* system ace */
+#ifdef XILINX_SYSACE_BASEADDR
+	#define	CONFIG_SYSTEMACE
+	/* #define DEBUG_SYSTEMACE */
+	#define	SYSTEMACE_CONFIG_FPGA
+	#define	CONFIG_SYS_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
+	#define	CONFIG_SYS_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
+	#define	CONFIG_DOS_PARTITION
+#endif
+
+#if defined(XILINX_USE_ICACHE)
+	#define CONFIG_ICACHE
+#else
+	#undef CONFIG_ICACHE
+#endif
+
+#if defined(XILINX_USE_DCACHE)
+	#define CONFIG_DCACHE
+#else
+	#undef CONFIG_DCACHE
+#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MFSL
+#define CONFIG_CMD_ECHO
+
+#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
+	#define CONFIG_CMD_CACHE
+#else
+	#undef CONFIG_CMD_CACHE
+#endif
+
+#ifndef CONFIG_SYS_ENET
+	#undef CONFIG_CMD_NET
+#else
+	#define CONFIG_CMD_PING
+#endif
+
+#if defined(CONFIG_SYSTEMACE)
+	#define CONFIG_CMD_EXT2
+	#define CONFIG_CMD_FAT
+#endif
+
+#if defined(FLASH)
+	#define CONFIG_CMD_ECHO
+	#define CONFIG_CMD_FLASH
+	#define CONFIG_CMD_IMLS
+	#define CONFIG_CMD_JFFS2
+
+	#if !defined(RAMENV)
+		#define CONFIG_CMD_SAVEENV
+		#define CONFIG_CMD_SAVES
+	#endif
+#else
+	#undef CONFIG_CMD_IMLS
+	#undef CONFIG_CMD_FLASH
+	#undef CONFIG_CMD_JFFS2
+#endif
+
+#if defined(CONFIG_CMD_JFFS2)
+/* JFFS2 partitions */
+#define CONFIG_JFFS2_CMDLINE	/* mtdparts command line support */
+#define MTDIDS_DEFAULT		"nor0=ml401-0"
+
+/* default mtd partition table */
+#define MTDPARTS_DEFAULT	"mtdparts=ml401-0:256k(u-boot),"\
+				"256k(env),3m(kernel),1m(romfs),"\
+				"1m(cramfs),-(jffs2)"
+#endif
+
+/* Miscellaneous configurable options */
+#define	CONFIG_SYS_PROMPT	"U-Boot-mONStR> "
+#define	CONFIG_SYS_CBSIZE	512	/* size of console buffer */
+#define	CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
+#define	CONFIG_SYS_MAXARGS	15	/* max number of command args */
+#define	CONFIG_SYS_LONGHELP
+#define	CONFIG_SYS_LOAD_ADDR	XILINX_RAM_START /* default load address */
+
+#define	CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
+#define	CONFIG_BOOTARGS		"root=romfs"
+#define	CONFIG_HOSTNAME		XILINX_BOARD_NAME
+#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
+#define	CONFIG_IPADDR		192.168.0.3
+#define	CONFIG_SERVERIP		192.168.0.5
+#define	CONFIG_GATEWAYIP	192.168.0.1
+#define	CONFIG_ETHADDR		00:E0:0C:00:00:FD
+
+/* architecture dependent code */
+#define	CONFIG_SYS_USR_EXCEP	/* user exception */
+#define CONFIG_SYS_HZ	1000
+
+#define	CONFIG_PREBOOT		"echo U-BOOT for $(hostname);setenv preboot;echo"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" /* hardware flash protection */\
+					"nor0=ml401-0\0"\
+					"mtdparts=mtdparts=ml401-0:"\
+					"256k(u-boot),256k(env),3m(kernel),"\
+					"1m(romfs),1m(cramfs),-(jffs2)\0"
+
+#define CONFIG_CMDLINE_EDITING
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h
index 0345b4a..8ff2f8a 100644
--- a/include/configs/mimc200.h
+++ b/include/configs/mimc200.h
@@ -33,7 +33,7 @@
 
 #define CONFIG_MIMC200_EXT_FLASH	1
 
-#define CFG_HZ				1000
+#define CONFIG_SYS_HZ				1000
 
 /*
  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
@@ -41,15 +41,15 @@
  * and the PBA bus to run at 1/4 the PLL frequency.
  */
 #define CONFIG_PLL			1
-#define CFG_POWER_MANAGER		1
-#define CFG_OSC0_HZ			10000000
-#define CFG_PLL0_DIV			1
-#define CFG_PLL0_MUL			15
-#define CFG_PLL0_SUPPRESS_CYCLES	16
-#define CFG_CLKDIV_CPU			0
-#define CFG_CLKDIV_HSB			1
-#define CFG_CLKDIV_PBA			2
-#define CFG_CLKDIV_PBB			1
+#define CONFIG_SYS_POWER_MANAGER		1
+#define CONFIG_SYS_OSC0_HZ			10000000
+#define CONFIG_SYS_PLL0_DIV			1
+#define CONFIG_SYS_PLL0_MUL			15
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
+#define CONFIG_SYS_CLKDIV_CPU			0
+#define CONFIG_SYS_CLKDIV_HSB			1
+#define CONFIG_SYS_CLKDIV_PBA			2
+#define CONFIG_SYS_CLKDIV_PBB			1
 
 /*
  * The PLLOPT register controls the PLL like this:
@@ -58,7 +58,7 @@
  *
  * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
  */
-#define CFG_PLL0_OPT			0x04
+#define CONFIG_SYS_PLL0_OPT			0x04
 
 #define CONFIG_USART1			1
 #define CONFIG_MIMC200_DBGLINK		1
@@ -80,7 +80,7 @@
 
 #define CONFIG_SILENT_CONSOLE		1	/* enable silent startup */
 #define CONFIG_DISABLE_CONSOLE		1	/* disable console */
-#define CFG_DEVICE_NULLDEV		1	/* include nulldev device */
+#define CONFIG_SYS_DEVICE_NULLDEV		1	/* include nulldev device */
 
 /*
  * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
@@ -121,57 +121,57 @@
 
 #define CONFIG_ATMEL_USART		1
 #define CONFIG_MACB			1
-#define CONFIG_PIO2			1
-#define CFG_NR_PIOS			5
-#define CFG_HSDRAMC			1
+#define CONFIG_PORTMUX_PIO		1
+#define CONFIG_SYS_NR_PIOS			5
+#define CONFIG_SYS_HSDRAMC			1
 #define CONFIG_MMC			1
 #define CONFIG_ATMEL_MCI		1
 
-#define CFG_DCACHE_LINESZ		32
-#define CFG_ICACHE_LINESZ		32
+#define CONFIG_SYS_DCACHE_LINESZ		32
+#define CONFIG_SYS_ICACHE_LINESZ		32
 
 #define CONFIG_NR_DRAM_BANKS		1
 
-#define CFG_FLASH_CFI			1
+#define CONFIG_SYS_FLASH_CFI			1
 #define CONFIG_FLASH_CFI_DRIVER		1
 
-#define CFG_FLASH_BASE			0x00000000
-#define CFG_FLASH_SIZE			0x800000
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		135
+#define CONFIG_SYS_FLASH_BASE			0x00000000
+#define CONFIG_SYS_FLASH_SIZE			0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		135
 
-#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 
-#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
-#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
-#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
+#define CONFIG_SYS_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE			EBI_SDRAM_BASE
 
-#define CFG_FRAM_BASE			0x08000000
-#define CFG_FRAM_SIZE			0x20000
+#define CONFIG_SYS_FRAM_BASE			0x08000000
+#define CONFIG_SYS_FRAM_SIZE			0x20000
 
 #define CONFIG_ENV_IS_IN_FLASH		1
 #define CONFIG_ENV_SIZE			65536
-#define CONFIG_ENV_ADDR			(CFG_FLASH_BASE + CFG_FLASH_SIZE - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
 
-#define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
 
-#define CFG_MALLOC_LEN			(1024*1024)
-#define CFG_DMA_ALLOC_LEN		(16384)
+#define CONFIG_SYS_MALLOC_LEN			(1024*1024)
+#define CONFIG_SYS_DMA_ALLOC_LEN		(16384)
 
 /* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
-#define CFG_BOOTPARAMS_LEN		(16 * 1024)
+#define CONFIG_SYS_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT			"U-Boot> "
-#define CFG_CBSIZE			256
-#define CFG_MAXARGS			16
-#define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_LONGHELP			1
+#define CONFIG_SYS_PROMPT			"U-Boot> "
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP			1
 
-#define CFG_MEMTEST_START		EBI_SDRAM_BASE
-#define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x1f00000)
+#define CONFIG_SYS_MEMTEST_START		EBI_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + 0x1f00000)
 
-#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/ml300.h b/include/configs/ml300.h
index 8d48221..68d0c85 100644
--- a/include/configs/ml300.h
+++ b/include/configs/ml300.h
@@ -59,15 +59,15 @@
 
 #define CONFIG_SYSTEMACE	1
 #define CONFIG_DOS_PARTITION	1
-#define CFG_SYSTEMACE_BASE	XPAR_OPB_SYSACE_0_BASEADDR
-#define CFG_SYSTEMACE_WIDTH	XPAR_XSYSACE_MEM_WIDTH
+#define CONFIG_SYS_SYSTEMACE_BASE	XPAR_OPB_SYSACE_0_BASEADDR
+#define CONFIG_SYS_SYSTEMACE_WIDTH	XPAR_XSYSACE_MEM_WIDTH
 
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* environment is in EEPROM */
 
 /* following are used only if env is in EEPROM */
 #ifdef	CONFIG_ENV_IS_IN_EEPROM
-#define CFG_I2C_EEPROM_ADDR	XPAR_PERSISTENT_0_IIC_0_EEPROMADDR
-#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	XPAR_PERSISTENT_0_IIC_0_EEPROMADDR
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 #define CONFIG_ENV_OFFSET		XPAR_PERSISTENT_0_IIC_0_BASEADDR
 #define CONFIG_MISC_INIT_R	1	/* used to call out convert_env() */
 #define CONFIG_ENV_OVERWRITE	1	/* allow users to update ethaddr and serial# */
@@ -75,7 +75,7 @@
 
 #include "../board/xilinx/ml300/xparameters.h"
 
-#define CFG_NO_FLASH		1	/* no flash */
+#define CONFIG_SYS_NO_FLASH		1	/* no flash */
 #define CONFIG_ENV_SIZE		XPAR_PERSISTENT_0_IIC_0_HIGHADDR - XPAR_PERSISTENT_0_IIC_0_BASEADDR + 1
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
@@ -86,7 +86,7 @@
 				"root=/dev/xsysace/disc0/part3 rw"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 
 /*
@@ -117,58 +117,58 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory		*/
-#define CFG_PROMPT	"=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP		/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt	*/
 
-#define CFG_CBSIZE	256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size	*/
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS	16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_DUART_CHAN		0
-#define CFG_NS16550_REG_SIZE -4
-#define CFG_NS16550 1
-#define CFG_INIT_CHAN1	 1
+#define CONFIG_SYS_DUART_CHAN		0
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550 1
+#define CONFIG_SYS_INIT_CHAN1	 1
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
-#define CFG_LOAD_ADDR		0x400000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MONITOR_BASE	0x04000000
-#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_BASE	0x04000000
+#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 
-#define CFG_INIT_RAM_ADDR	0x800000  /* inside of SDRAM */
-#define CFG_INIT_RAM_END	0x2000	  /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE	128	  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x800000  /* inside of SDRAM */
+#define CONFIG_SYS_INIT_RAM_END	0x2000	  /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	128	  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Internal Definitions
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
deleted file mode 100644
index 2a6c68c..0000000
--- a/include/configs/ml401.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * (C) Copyright 2007-2008 Michal Simek
- *
- * Michal SIMEK <monstr@monstr.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "../board/xilinx/ml401/xparameters.h"
-
-#define	CONFIG_MICROBLAZE	1	/* MicroBlaze CPU */
-#define	MICROBLAZE_V5		1
-#define	CONFIG_ML401		1	/* ML401 Board */
-
-/* uart */
-#ifdef XILINX_UARTLITE_BASEADDR
-#define	CONFIG_XILINX_UARTLITE
-#define	CONFIG_SERIAL_BASE	XILINX_UARTLITE_BASEADDR
-#define	CONFIG_BAUDRATE		XILINX_UARTLITE_BAUDRATE
-#define	CFG_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
-#else
-#ifdef XILINX_UART16550_BASEADDR
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	4
-#define CONFIG_CONS_INDEX	1
-#define CFG_NS16550_COM1	XILINX_UART16550_BASEADDR
-#define CFG_NS16550_CLK		XILINX_UART16550_CLOCK_HZ
-#define	CONFIG_BAUDRATE		115200
-#define	CFG_BAUDRATE_TABLE	{ 9600, 115200 }
-#endif
-#endif
-
-/* setting reset address */
-/*#define	CFG_RESET_ADDRESS	TEXT_BASE*/
-
-/* ethernet */
-#ifdef XILINX_EMAC_BASEADDR
-#define CONFIG_XILINX_EMAC	1
-#define CFG_ENET
-#else
-#ifdef XILINX_EMACLITE_BASEADDR
-#define CONFIG_XILINX_EMACLITE	1
-#define CFG_ENET
-#endif
-#endif
-#undef ET_DEBUG
-
-/* gpio */
-#ifdef XILINX_GPIO_BASEADDR
-#define	CFG_GPIO_0		1
-#define	CFG_GPIO_0_ADDR		XILINX_GPIO_BASEADDR
-#endif
-
-/* interrupt controller */
-#ifdef XILINX_INTC_BASEADDR
-#define	CFG_INTC_0		1
-#define	CFG_INTC_0_ADDR		XILINX_INTC_BASEADDR
-#define	CFG_INTC_0_NUM		XILINX_INTC_NUM_INTR_INPUTS
-#endif
-
-/* timer */
-#ifdef XILINX_TIMER_BASEADDR
-#if (XILINX_TIMER_IRQ != -1)
-#define	CFG_TIMER_0		1
-#define	CFG_TIMER_0_ADDR	XILINX_TIMER_BASEADDR
-#define	CFG_TIMER_0_IRQ		XILINX_TIMER_IRQ
-#define	FREQUENCE		XILINX_CLOCK_FREQ
-#define	CFG_TIMER_0_PRELOAD	( FREQUENCE/1000 )
-#endif
-#else
-#ifdef XILINX_CLOCK_FREQ
-#define	CONFIG_XILINX_CLOCK_FREQ	XILINX_CLOCK_FREQ
-#else
-#error BAD CLOCK FREQ
-#endif
-#endif
-/* FSL */
-/* #define	CFG_FSL_2 */
-/* #define	FSL_INTR_2	1 */
-
-/*
- * memory layout - Example
- * TEXT_BASE = 0x1200_0000;
- * CFG_SRAM_BASE = 0x1000_0000;
- * CFG_SRAM_SIZE = 0x0400_0000;
- *
- * CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
- * CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
- * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
- *
- * 0x1000_0000	CFG_SDRAM_BASE
- *					FREE
- * 0x1200_0000	TEXT_BASE
- *		U-BOOT code
- * 0x1202_0000
- *					FREE
- *
- *					STACK
- * 0x13F7_F000	CFG_MALLOC_BASE
- *					MALLOC_AREA	256kB	Alloc
- * 0x11FB_F000	CFG_MONITOR_BASE
- *					MONITOR_CODE	256kB	Env
- * 0x13FF_F000	CFG_GBL_DATA_OFFSET
- *					GLOBAL_DATA	4kB	bd, gd
- * 0x1400_0000	CFG_SDRAM_BASE + CFG_SDRAM_SIZE
- */
-
-/* ddr sdram - main memory */
-#define	CFG_SDRAM_BASE		XILINX_RAM_START
-#define	CFG_SDRAM_SIZE		XILINX_RAM_SIZE
-#define	CFG_MEMTEST_START	CFG_SDRAM_BASE
-#define	CFG_MEMTEST_END		(CFG_SDRAM_BASE + 0x1000)
-
-/* global pointer */
-#define	CFG_GBL_DATA_SIZE	0x1000	/* size of global data */
-/* start of global data */
-#define	CFG_GBL_DATA_OFFSET	(CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
-
-/* monitor code */
-#define	SIZE			0x40000
-#define	CFG_MONITOR_LEN		SIZE
-#define	CFG_MONITOR_BASE	(CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
-#define	CFG_MONITOR_END		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define	CFG_MALLOC_LEN		SIZE
-#define	CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-
-/* stack */
-#define	CFG_INIT_SP_OFFSET	CFG_MONITOR_BASE
-
-/*#define	RAMENV */
-#define	FLASH
-
-#ifdef FLASH
-	#define	CFG_FLASH_BASE		XILINX_FLASH_START
-	#define	CFG_FLASH_SIZE		XILINX_FLASH_SIZE
-	#define	CFG_FLASH_CFI		1
-	#define	CONFIG_FLASH_CFI_DRIVER	1
-	#define	CFG_FLASH_EMPTY_INFO	1	/* ?empty sector */
-	#define	CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-	#define	CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
-	#define	CFG_FLASH_PROTECTION		/* hardware flash protection */
-
-	#ifdef	RAMENV
-		#define	CONFIG_ENV_IS_NOWHERE	1
-		#define	CONFIG_ENV_SIZE		0x1000
-		#define	CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - CONFIG_ENV_SIZE)
-
-	#else	/* !RAMENV */
-		#define	CONFIG_ENV_IS_IN_FLASH	1
-		#define	CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
-		#define	CONFIG_ENV_ADDR		(CFG_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
-		#define	CONFIG_ENV_SIZE		0x40000
-	#endif /* !RAMBOOT */
-#else /* !FLASH */
-	/* ENV in RAM */
-	#define	CFG_NO_FLASH		1
-	#define	CONFIG_ENV_IS_NOWHERE	1
-	#define	CONFIG_ENV_SIZE		0x1000
-	#define	CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - CONFIG_ENV_SIZE)
-	#define	CFG_FLASH_PROTECTION		/* hardware flash protection */
-#endif /* !FLASH */
-
-/* system ace */
-#ifdef XILINX_SYSACE_BASEADDR
-	#define	CONFIG_SYSTEMACE
-	/* #define DEBUG_SYSTEMACE */
-	#define	SYSTEMACE_CONFIG_FPGA
-	#define	CFG_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
-	#define	CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
-	#define	CONFIG_DOS_PARTITION
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MFSL
-
-#ifndef CFG_ENET
-	#undef CONFIG_CMD_NET
-#else
-	#define CONFIG_CMD_PING
-#endif
-
-#if defined(CONFIG_SYSTEMACE)
-	#define CONFIG_CMD_EXT2
-	#define CONFIG_CMD_FAT
-#endif
-
-#if defined(FLASH)
-	#define CONFIG_CMD_ECHO
-	#define CONFIG_CMD_FLASH
-	#define CONFIG_CMD_IMLS
-	#define CONFIG_CMD_JFFS2
-
-	#if !defined(RAMENV)
-		#define CONFIG_CMD_ENV
-		#define CONFIG_CMD_SAVES
-	#endif
-#else
-	#undef CONFIG_CMD_FLASH
-#endif
-
-#if defined(CONFIG_CMD_JFFS2)
-/* JFFS2 partitions */
-#define CONFIG_JFFS2_CMDLINE	/* mtdparts command line support */
-#define MTDIDS_DEFAULT		"nor0=ml401-0"
-
-/* default mtd partition table */
-#define MTDPARTS_DEFAULT	"mtdparts=ml401-0:256k(u-boot),"\
-				"256k(env),3m(kernel),1m(romfs),"\
-				"1m(cramfs),-(jffs2)"
-#endif
-
-/* Miscellaneous configurable options */
-#define	CFG_PROMPT	"U-Boot-mONStR> "
-#define	CFG_CBSIZE	512	/* size of console buffer */
-#define	CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
-#define	CFG_MAXARGS	15	/* max number of command args */
-#define	CFG_LONGHELP
-#define	CFG_LOAD_ADDR	0x12000000 /* default load address */
-
-#define	CONFIG_BOOTDELAY	30
-#define	CONFIG_BOOTARGS		"root=romfs"
-#define	CONFIG_HOSTNAME		"ml401"
-#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
-#define	CONFIG_IPADDR		192.168.0.3
-#define	CONFIG_SERVERIP		192.168.0.5
-#define	CONFIG_GATEWAYIP	192.168.0.1
-#define	CONFIG_ETHADDR		00:E0:0C:00:00:FD
-
-/* architecture dependent code */
-#define	CFG_USR_EXCEP	/* user exception */
-#define CFG_HZ	1000
-
-#define	CONFIG_PREBOOT		"echo U-BOOT for ML401;setenv preboot;echo"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" /* hardware flash protection */\
-					"nor0=ml401-0\0"\
-					"mtdparts=mtdparts=ml401-0:"\
-					"256k(u-boot),256k(env),3m(kernel),"\
-					"1m(romfs),1m(cramfs),-(jffs2)\0"
-
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_OF_LIBFDT	1
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ml507.h b/include/configs/ml507.h
index 22a972f..a7319e4 100644
--- a/include/configs/ml507.h
+++ b/include/configs/ml507.h
@@ -24,22 +24,22 @@
 #include "../board/xilinx/ml507/xparameters.h"
 
 /*Mem Map*/
-#define CFG_SDRAM_SIZE_MB	256
+#define CONFIG_SYS_SDRAM_SIZE_MB	256
 
 /*Env*/
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_SIZE		0x20000
 #define	CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_OFFSET		0x340000
+#define CONFIG_ENV_OFFSET	0x340000
 #define CONFIG_ENV_ADDR		(XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
 
 /*Misc*/
-#define CFG_PROMPT		"ml507:/# "	/* Monitor Command Prompt    */
+#define CONFIG_SYS_PROMPT	"ml507:/# "	/* Monitor Command Prompt    */
 #define CONFIG_PREBOOT		"echo U-Boot is up and runnining;"
 
 /*Flash*/
-#define	CFG_FLASH_SIZE		(32*1024*1024)
-#define	CFG_MAX_FLASH_SECT	259
+#define	CONFIG_SYS_FLASH_SIZE	(32*1024*1024)
+#define	CONFIG_SYS_MAX_FLASH_SECT	259
 #define MTDIDS_DEFAULT		"nor0=ml507-flash"
 #define MTDPARTS_DEFAULT	"mtdparts=ml507-flash:-(user)"
 
diff --git a/include/configs/modnet50.h b/include/configs/modnet50.h
index 8f4011a..c4f5286 100644
--- a/include/configs/modnet50.h
+++ b/include/configs/modnet50.h
@@ -45,8 +45,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 /*
  * Hardware drivers
@@ -84,7 +84,7 @@
 #define CONFIG_NETMASK          255.255.255.0
 #define CONFIG_IPADDR		192.168.30.2
 #define CONFIG_SERVERIP         192.168.30.122
-#define CFG_ETH_PHY_ADDR        0x100
+#define CONFIG_SYS_ETH_PHY_ADDR        0x100
 #define CONFIG_CMDLINE_TAG      /* submit bootargs to kernel */
 
 /*#define CONFIG_BOOTDELAY	10*/
@@ -101,24 +101,24 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory	*/
-#define	CFG_PROMPT		"modnet50 # "	/* Monitor Command Prompt */
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size */
-#define	CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory	*/
+#define	CONFIG_SYS_PROMPT		"modnet50 # "	/* Monitor Command Prompt */
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
+#define	CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00800000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00800000	/* 4 ... 8 MB in DRAM	*/
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0x00500000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x00500000	/* default load address	*/
 
-#define	CFG_HZ			900		/* decrementer freq: 2 kHz */
+#define	CONFIG_SYS_HZ			900		/* decrementer freq: 2 kHz */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -155,19 +155,19 @@
 #define PHYS_EXT_1		0x30000000 /* Extensions Bank #1 */
 #define PHYS_EXT_SIZE		0x01000000 /* 32 MB memory mapped I/O */
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-#define CFG_FLASH_SIZE		PHYS_FLASH_1_SIZE
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_SIZE		PHYS_FLASH_1_SIZE
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	35	/* max number of sectors on one chip */
-#define CFG_MAIN_SECT_SIZE      0x00010000  /* main size of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	35	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAIN_SECT_SIZE      0x00010000  /* main size of sectors on one chip */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 /* environment settings */
 #define	CONFIG_ENV_IS_IN_FLASH
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 73a03a8..e6e3729 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -75,13 +75,14 @@
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
 #define CONFIG_NETCONSOLE	1	/* network console */
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
 #define CONFIG_PHY_ADDR		0x2
 #define CONFIG_PHY_TYPE		0x79c874
 #define CONFIG_RESET_PHY_R	1
@@ -166,13 +167,13 @@
 /*
  * Clock configuration: SYS_XTALIN = 33MHz
  */
-#define CFG_MPC5XXX_CLKIN	33000000
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
 
 
 /*
  * Set IPB speed to 100MHz
  */
-#define CFG_IPBCLK_EQUALS_XLBCLK
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
 
 
 /*
@@ -183,8 +184,8 @@
  * Setting MBAR to otherwise will cause system hang when using SmartDMA such
  * as network commands.
  */
-#define CFG_MBAR		0xf0000000
-#define CFG_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MBAR		0xf0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
 
 /*
  * If building for running out of SDRAM, then MBAR has been set up beforehand
@@ -192,61 +193,61 @@
  * MBAR, as given in the doccumentation.
  */
 #if TEXT_BASE == 0x00100000
-#define CFG_DEFAULT_MBAR	0xf0000000
+#define CONFIG_SYS_DEFAULT_MBAR	0xf0000000
 #else /* TEXT_BASE != 0x00100000 */
-#define CFG_DEFAULT_MBAR	0x80000000
-#define CFG_LOWBOOT		1
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_LOWBOOT		1
 #endif /* TEXT_BASE == 0x00100000 */
 
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(1024 << 10)	/* 1 MiB for malloc() */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* initial mem map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)	/* 1 MiB for malloc() */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* initial mem map for Linux */
 
 
 /*
  * Chip selects configuration
  */
 /* Boot Chipselect */
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x00045D00
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00045D00
 
 /* Flash memory addressing */
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
-#define CFG_CS0_CFG		CFG_BOOTCS_CFG
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS0_CFG		CONFIG_SYS_BOOTCS_CFG
 
 /* Dual Port SRAM -- Kollmorgen Drive memory addressing */
-#define CFG_CS1_START		0x50000000
-#define CFG_CS1_SIZE		0x10000
-#define CFG_CS1_CFG		0x05055800
+#define CONFIG_SYS_CS1_START		0x50000000
+#define CONFIG_SYS_CS1_SIZE		0x10000
+#define CONFIG_SYS_CS1_CFG		0x05055800
 
 /* Local register access */
-#define CFG_CS2_START		0x50010000
-#define CFG_CS2_SIZE		0x10000
-#define CFG_CS2_CFG		0x05055800
+#define CONFIG_SYS_CS2_START		0x50010000
+#define CONFIG_SYS_CS2_SIZE		0x10000
+#define CONFIG_SYS_CS2_CFG		0x05055800
 
 /* Anybus CompactCom Module memory addressing */
-#define CFG_CS3_START		0x50020000
-#define CFG_CS3_SIZE		0x10000
-#define CFG_CS3_CFG		0x05055800
+#define CONFIG_SYS_CS3_START		0x50020000
+#define CONFIG_SYS_CS3_SIZE		0x10000
+#define CONFIG_SYS_CS3_CFG		0x05055800
 
 /* No burst and dead cycle = 2 for all CSs */
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x22222222
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x22222222
 
 
 /*
@@ -262,13 +263,13 @@
 /*
  * Flash configuration
  */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1
-#define CFG_FLASH_BASE		0xff000000
-#define CFG_FLASH_SIZE		0x01000000
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_BASE		0xff000000
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
 #define CONFIG_FLASH_16BIT		/* Flash is 16-bit */
 
 /*
@@ -284,14 +285,14 @@
 /*
  * IDE/ATA configuration
  */
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
-#define CFG_IDE_MAXBUS		1
-#define CFG_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	1
 #define CONFIG_IDE_PREINIT
 
-#define CFG_ATA_DATA_OFFSET	0x0060
-#define CFG_ATA_REG_OFFSET	CFG_ATA_DATA_OFFSET
-#define CFG_ATA_STRIDE		4
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0060
+#define CONFIG_SYS_ATA_REG_OFFSET	CONFIG_SYS_ATA_DATA_OFFSET
+#define CONFIG_SYS_ATA_STRIDE		4
 #define CONFIG_DOS_PARTITION
 
 
@@ -299,26 +300,25 @@
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		2	/* select I2C module #2 */
-#define CFG_I2C_SPEED		100000	/* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_MODULE		2	/* select I2C module #2 */
+#define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 
 /*
  * EEPROM configuration
  */
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE	1	/* DTT driver needs this */
-#define CFG_EEPROM_PAGE_WRITE_BITS	1	/* 2 bytes per write cycle */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	5	/* 2ms/cycle + 3ms extra */
-#define CFG_I2C_MULTI_EEPROMS		1	/* 2 EEPROMs (addr:50,52) */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	1	/* 2 bytes per write cycle */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5	/* 2ms/cycle + 3ms extra */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS		1	/* 2 EEPROMs (addr:50,52) */
 
 
 /*
  * RTC configuration
  */
 #define CONFIG_RTC_DS1337	1
-#define CFG_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
 
 
 /*
@@ -355,7 +355,7 @@ extern void __led_set(led_id_t id, int state);
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
 /* This has to be a multiple of the Flash sector size */
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_ENV_SIZE		0x1000
 #define CONFIG_ENV_SECT_SIZE	0x20000
 
@@ -375,48 +375,48 @@ extern void __led_set(led_id_t id, int state);
  * Timer: CAN2/GPIO
  * PSC6/IRDA: GPIO (default)
  */
-#define CFG_GPS_PORT_CONFIG	0x1105a004
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x1105a004
 
 
 /*
  * Motion-PRO's CPLD revision control register
  */
-#define CPLD_REV_REGISTER	(CFG_CS2_START + 0x06)
+#define CPLD_REV_REGISTER	(CONFIG_SYS_CS2_START + 0x06)
 
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x03e00000	/* 1 ... 62 MiB in DRAM */
-#define CFG_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x03e00000	/* 1 ... 62 MiB in DRAM */
+#define CONFIG_SYS_ALT_MEMTEST
 
-#define CFG_LOAD_ADDR		0x200000	/* default kernel load addr */
+#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default kernel load addr */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 
 /*
  * Various low-level settings
  */
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 
 
 /* Not needed for MPC 5xxx U-Boot, but used by tools/updater */
-#define CFG_RESET_ADDRESS	0xfff00100
+#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
 
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h
index ba1ed0d..9ac7e9a 100644
--- a/include/configs/mp2usb.h
+++ b/include/configs/mp2usb.h
@@ -45,48 +45,50 @@
 #define CONFIG_SETUP_MEMORY_TAGS 1
 #define CONFIG_INITRD_TAG	1
 
-#define CFG_ATMEL_PLL_INIT_BUG	1
+#define CONFIG_SYS_ATMEL_PLL_INIT_BUG	1
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#define CFG_USE_MAIN_OSCILLATOR	1
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR	1
 /* flash */
-#define MC_PUIA_VAL	0x00000000
-#define MC_PUP_VAL	0x00000000
-#define MC_PUER_VAL	0x00000000
-#define MC_ASR_VAL	0x00000000
-#define MC_AASR_VAL	0x00000000
-#define EBI_CFGR_VAL	0x00000000
-#define SMC_CSR0_VAL	0x00003084 /* 16bit, 2 TDF, 4 WS */
+#define CONFIG_SYS_MC_PUIA_VAL	0x00000000
+#define CONFIG_SYS_MC_PUP_VAL	0x00000000
+#define CONFIG_SYS_MC_PUER_VAL	0x00000000
+#define CONFIG_SYS_MC_ASR_VAL	0x00000000
+#define CONFIG_SYS_MC_AASR_VAL	0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL	0x00003084 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
-#define PLLAR_VAL	0x20263E04 /* 180 MHz for PCK */
-#define PLLBR_VAL	0x1048bE0E /* 48 MHz (divider by 2 for USB) */
-#define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */
+#define CONFIG_SYS_PLLAR_VAL	0x20263E04 /* 180 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL	0x1048bE0E /* 48 MHz (divider by 2 for USB) */
+#define CONFIG_SYS_MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */
 
 /* sdram */
-#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR_VAL	0x00000000
-#define PIOC_PDR_VAL	0xFFFF0000
-#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
-#define SDRC_CR_VAL	0x3211295A /* set up the SDRAM */
-#define SDRAM		0x20000000 /* address of the SDRAM */
-#define SDRAM1		0x20000020 /* address of the SDRAM */
-#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
-#define SDRC_MR_VAL	0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1	0x00000004 /* refresh */
-#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
-#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL	0x3211295A /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM	0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1	0x20000020 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#else
+#define CONFIG_SKIP_RELOCATE_UBOOT
 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
 
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 #define CONFIG_BAUDRATE		115200
 
-#define CFG_AT91C_BRGR_DIVISOR	33	/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK /(baudrate * 16) */
+#define CONFIG_SYS_AT91C_BRGR_DIVISOR	33	/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK /(baudrate * 16) */
 
 /*
  * Hardware drivers
@@ -107,25 +109,25 @@
 #define CONFIG_DOS_PARTITION	1
 #define CONFIG_AT91C_PQFP_UHPBUG 1
 
-#undef CFG_USB_OHCI_BOARD_INIT
-#define CFG_USB_OHCI_CPU_INIT		1
-#define CFG_USB_OHCI_REGS_BASE		AT91_USB_HOST_BASE
-#define CFG_USB_OHCI_SLOT_NAME		"at91rm9200"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS	15
+#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		AT91_USB_HOST_BASE
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91rm9200"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
 
 #undef CONFIG_HARD_I2C
 
 #ifdef CONFIG_HARD_I2C
-#define CFG_I2C_SPEED		0	/* not used */
-#define CFG_I2C_SLAVE		0	/* not used */
+#define CONFIG_SYS_I2C_SPEED		0	/* not used */
+#define CONFIG_SYS_I2C_SLAVE		0	/* not used */
 #define CONFIG_RTC_RS5C372A		/* RICOH I2C RTC */
-#define CFG_I2C_RTC_ADDR	0x32
-#define CFG_I2C_EEPROM_ADDR	0x50
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW
+#define CONFIG_SYS_I2C_RTC_ADDR	0x32
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 #endif
 /* still about 20 kB free with this defined */
-#define CFG_LONGHELP
+#define CONFIG_SYS_LONGHELP
 
 #define CONFIG_BOOTDELAY      3
 
@@ -174,14 +176,14 @@
 #endif
 
 
-#define CFG_LONGHELP
+#define CONFIG_SYS_LONGHELP
 
 #define CONFIG_NR_DRAM_BANKS	1
 #define PHYS_SDRAM		0x20000000
 #define PHYS_SDRAM_SIZE		0x08000000	/* 128 megs */
 
-#define CFG_MEMTEST_START	PHYS_SDRAM
-#define CFG_MEMTEST_END		CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
 
 #define CONFIG_DRIVER_ETHER
 #define CONFIG_NET_RETRY_COUNT		20
@@ -189,35 +191,34 @@
 
 #define PHYS_FLASH_1			0x10000000
 #define PHYS_FLASH_SIZE			0x1000000  /* 16 megs main flash */
-#define CFG_FLASH_BASE			PHYS_FLASH_1
-#define CFG_MONITOR_BASE		CFG_FLASH_BASE
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		256
-#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
-#define CFG_FLASH_LOCK_TOUT		(10*CFG_HZ)	/* Timeout for Flash Set Lock Bit */
-#define CFG_FLASH_UNLOCK_TOUT		(10*CFG_HZ)	/* Timeout for Flash Clear Lock Bits */
-#define CFG_FLASH_PROTECTION				/* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		256
+#define CONFIG_SYS_FLASH_ERASE_TOUT		(2 * CONFIG_SYS_HZ)	/* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT		(2 * CONFIG_SYS_HZ)	/* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_LOCK_TOUT		(10*CONFIG_SYS_HZ)	/* Timeout for Flash Set Lock Bit */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT		(10*CONFIG_SYS_HZ)	/* Timeout for Flash Clear Lock Bits */
+#define CONFIG_SYS_FLASH_PROTECTION				/* "Real" (hardware) sectors protection */
 
 #define CONFIG_ENV_IS_IN_FLASH		1
 #define CONFIG_ENV_OFFSET			0x20000		/* after u-boot.bin */
-#define CONFIG_ENV_ADDR			(CFG_FLASH_BASE+CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE+CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_SIZE			0x20000
 
-#define CFG_LOAD_ADDR		0x21000000  /* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
 
-#define CFG_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
 
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
-#define CFG_MAXARGS		32		/* max number of command args */
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS		32		/* max number of command args */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 
-#define CFG_DEVICE_DEREGISTER           /* needs device_deregister */
-#define LITTLEENDIAN            1       /* used by usb_ohci.c  */
+#define CONFIG_SYS_DEVICE_DEREGISTER           /* needs device_deregister */
 
-#define CFG_HZ 1000
-#define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2)	/* AT91C_TC0_CMR is implicitly set to */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK/2)	/* AT91C_TC0_CMR is implicitly set to */
 						/* AT91C_TC_TIMER_DIV1_CLOCK */
 
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
@@ -226,7 +227,7 @@
 #error CONFIG_USE_IRQ not supported
 #endif
 
-#define CFG_DEVICE_NULLDEV	 1	/* enble null device		*/
+#define CONFIG_SYS_DEVICE_NULLDEV	 1	/* enble null device		*/
 #undef CONFIG_SILENT_CONSOLE		/* enable silent startup	*/
 
 #define CONFIG_AUTOBOOT_KEYED
diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h
index 308a7b9..a1783b2 100644
--- a/include/configs/mpc7448hpc2.h
+++ b/include/configs/mpc7448hpc2.h
@@ -42,18 +42,18 @@
 #define CONFIG_HIGH_BATS	/* High BATs supported */
 #define CONFIG_ALTIVEC		/* undef to disable */
 
-#define CFG_BOARD_NAME		"MPC7448 HPC II"
+#define CONFIG_SYS_BOARD_NAME		"MPC7448 HPC II"
 #define CONFIG_IDENT_STRING	" Freescale MPC7448 HPC II"
 
-#define CFG_OCN_CLK		133000000	/* 133 MHz */
-#define CFG_CONFIG_BUS_CLK	133000000
+#define CONFIG_SYS_OCN_CLK		133000000	/* 133 MHz */
+#define CONFIG_SYS_CONFIG_BUS_CLK	133000000
 
-#define CFG_CLK_SPREAD		/* Enable Spread-Spectrum Clock generation */
+#define CONFIG_SYS_CLK_SPREAD		/* Enable Spread-Spectrum Clock generation */
 
 #undef  CONFIG_ECC		/* disable ECC support */
 
 /* Board-specific Initialization Functions to be called */
-#define CFG_BOARD_ASM_INIT
+#define CONFIG_SYS_BOARD_ASM_INIT
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_MISC_INIT_R
@@ -70,10 +70,10 @@
 
 #define CONFIG_BAUDRATE		115200	/* console baudrate = 115000 */
 
-/*#define CFG_HUSH_PARSER */
-#undef CFG_HUSH_PARSER
+/*#define CONFIG_SYS_HUSH_PARSER */
+#undef CONFIG_SYS_HUSH_PARSER
 
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 /* Pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
@@ -90,19 +90,19 @@
  *
  * what to do:
  * If you have hacked a serial cable onto the second DUART channel,
- * change the CFG_DUART port from 1 to 0 below.
+ * change the CONFIG_SYS_DUART port from 1 to 0 below.
  *
  */
 
 #define CONFIG_CONS_INDEX	1
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		CFG_OCN_CLK * 8
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_OCN_CLK * 8
 
-#define CFG_NS16550_COM1	(CFG_TSI108_CSR_RST_BASE+0x7808)
-#define CFG_NS16550_COM2	(CFG_TSI108_CSR_RST_BASE+0x7C08)
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_TSI108_CSR_RST_BASE+0x7808)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_TSI108_CSR_RST_BASE+0x7C08)
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */
 #define CONFIG_ZERO_BOOTDELAY_CHECK
@@ -137,7 +137,7 @@
 /*-------------------------------------------------------------------------- */
 
 #define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
-#define CFG_LOADS_BAUD_CHANGE	/* allow baudrate changes */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate changes */
 
 #undef CONFIG_WATCHDOG		/* watchdog disabled */
 
@@ -163,7 +163,7 @@
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_FLASH
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING
@@ -172,37 +172,37 @@
 
 /*set date in u-boot*/
 #define CONFIG_RTC_M48T35A
-#define CFG_NVRAM_BASE_ADDR	0xfc000000
-#define CFG_NVRAM_SIZE		0x8000
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xfc000000
+#define CONFIG_SYS_NVRAM_SIZE		0x8000
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_VERSION_VARIABLE		1
 #define CONFIG_TSI108_I2C
 
-#define CFG_I2C_EEPROM_ADDR		0x50	/* I2C EEPROM page 1 */
-#define CFG_I2C_EEPROM_ADDR_LEN		1	/* Bytes of address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* I2C EEPROM page 1 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1	/* Bytes of address */
 
-#define CFG_LONGHELP		/* undef to save memory */
-#define CFG_PROMPT	"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 #define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)/* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on */
-#define CFG_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
 
-#define CFG_LOAD_ADDR	0x00400000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR	0x00400000	/* default load address */
 
-#define CFG_HZ		1000		/* decr freq: 1ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decr freq: 1ms ticks */
 
 /*
  * Low Level Configuration Settings
@@ -215,46 +215,46 @@
  */
 
 /*
- * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
+ * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
  * To an unused memory region. The stack will remain in cache until RAM
  * is initialized
  */
-#undef  CFG_INIT_RAM_LOCK
-#define CFG_INIT_RAM_ADDR	0x07d00000	/* unused memory region */
-#define CFG_INIT_RAM_END	0x4000/* larger space - we have SDRAM initialized */
+#undef  CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0x07d00000	/* unused memory region */
+#define CONFIG_SYS_INIT_RAM_END	0x4000/* larger space - we have SDRAM initialized */
 
-#define CFG_GBL_DATA_SIZE	128/* size in bytes reserved for init data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_SIZE	128/* size in bytes reserved for init data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
 
-#define CFG_SDRAM_BASE		0x00000000	/* first 256 MB of SDRAM */
-#define CFG_SDRAM1_BASE		0x10000000	/* next 256MB of SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* first 256 MB of SDRAM */
+#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* next 256MB of SDRAM */
 
-#define CFG_SDRAM2_BASE	0x40000000	/* beginning of non-cacheable alias for SDRAM - first 256MB */
-#define CFG_SDRAM3_BASE	0x50000000	/* next Non-Cacheable 256MB of SDRAM */
+#define CONFIG_SYS_SDRAM2_BASE	0x40000000	/* beginning of non-cacheable alias for SDRAM - first 256MB */
+#define CONFIG_SYS_SDRAM3_BASE	0x50000000	/* next Non-Cacheable 256MB of SDRAM */
 
-#define CFG_PCI_PFM_BASE	0x80000000	/* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */
+#define CONFIG_SYS_PCI_PFM_BASE	0x80000000	/* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */
 
-#define CFG_PCI_MEM32_BASE	0xE0000000	/* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */
+#define CONFIG_SYS_PCI_MEM32_BASE	0xE0000000	/* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */
 
-#define CFG_MISC_REGION_BASE	0xf0000000	/* Base Address for (PCI/X + Flash) region */
+#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000	/* Base Address for (PCI/X + Flash) region */
 
-#define CFG_FLASH_BASE	0xff000000	/* Base Address of Flash device */
-#define CFG_FLASH_BASE2	0xfe000000	/* Alternate Flash Base Address */
+#define CONFIG_SYS_FLASH_BASE	0xff000000	/* Base Address of Flash device */
+#define CONFIG_SYS_FLASH_BASE2	0xfe000000	/* Alternate Flash Base Address */
 
 #define CONFIG_VERY_BIG_RAM	/* we will use up to 256M memory for cause we are short of BATS */
 
 #define PCI0_IO_BASE_BOOTM	0xfd000000
 
-#define CFG_RESET_ADDRESS	0x3fffff00
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MONITOR_BASE	TEXT_BASE	/* u-boot code base */
-#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+#define CONFIG_SYS_RESET_ADDRESS	0x3fffff00
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* u-boot code base */
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
 
 /* Peripheral Device section */
 
@@ -262,8 +262,8 @@
  * Resources on the Tsi108
  */
 
-#define CFG_TSI108_CSR_RST_BASE	0xC0000000	/* Tsi108 CSR base after reset */
-#define CFG_TSI108_CSR_BASE	CFG_TSI108_CSR_RST_BASE	/* Runtime Tsi108 CSR base */
+#define CONFIG_SYS_TSI108_CSR_RST_BASE	0xC0000000	/* Tsi108 CSR base after reset */
+#define CONFIG_SYS_TSI108_CSR_BASE	CONFIG_SYS_TSI108_CSR_RST_BASE	/* Runtime Tsi108 CSR base */
 
 #define ENABLE_PCI_CSR_BAR	/* enables access to Tsi108 CSRs from the PCI/X bus */
 
@@ -287,74 +287,74 @@
 /* PCI MEMORY MAP section */
 
 /* PCI view of System Memory */
-#define CFG_PCI_MEMORY_BUS	0x00000000
-#define CFG_PCI_MEMORY_PHYS	0x00000000
-#define CFG_PCI_MEMORY_SIZE	0x80000000
+#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
+#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
+#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
 
 /* PCI Memory Space */
-#define CFG_PCI_MEM_BUS		(CFG_PCI_MEM_PHYS)
-#define CFG_PCI_MEM_PHYS	(CFG_PCI_MEM32_BASE)	/* 0xE0000000 */
-#define CFG_PCI_MEM_SIZE	0x10000000	/* 256 MB space for PCI/X Mem + SDRAM OCN */
+#define CONFIG_SYS_PCI_MEM_BUS		(CONFIG_SYS_PCI_MEM_PHYS)
+#define CONFIG_SYS_PCI_MEM_PHYS	(CONFIG_SYS_PCI_MEM32_BASE)	/* 0xE0000000 */
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000	/* 256 MB space for PCI/X Mem + SDRAM OCN */
 
 /* PCI I/O Space */
-#define CFG_PCI_IO_BUS		0x00000000
-#define CFG_PCI_IO_PHYS		0xfa000000	/* Changed from fd000000 */
+#define CONFIG_SYS_PCI_IO_BUS		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0xfa000000	/* Changed from fd000000 */
 
-#define CFG_PCI_IO_SIZE		0x01000000	/* 16MB */
+#define CONFIG_SYS_PCI_IO_SIZE		0x01000000	/* 16MB */
 
 #define _IO_BASE		0x00000000	/* points to PCI I/O space      */
 
 /* PCI Config Space mapping */
-#define CFG_PCI_CFG_BASE	0xfb000000	/* Changed from FE000000 */
-#define CFG_PCI_CFG_SIZE	0x01000000	/* 16MB */
+#define CONFIG_SYS_PCI_CFG_BASE	0xfb000000	/* Changed from FE000000 */
+#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000	/* 16MB */
 
-#define CFG_IBAT0U	0xFE0003FF
-#define CFG_IBAT0L	0xFE000002
+#define CONFIG_SYS_IBAT0U	0xFE0003FF
+#define CONFIG_SYS_IBAT0L	0xFE000002
 
-#define CFG_IBAT1U	0x00007FFF
-#define CFG_IBAT1L	0x00000012
+#define CONFIG_SYS_IBAT1U	0x00007FFF
+#define CONFIG_SYS_IBAT1L	0x00000012
 
-#define CFG_IBAT2U	0x80007FFF
-#define CFG_IBAT2L	0x80000022
+#define CONFIG_SYS_IBAT2U	0x80007FFF
+#define CONFIG_SYS_IBAT2L	0x80000022
 
-#define CFG_IBAT3U	0x00000000
-#define CFG_IBAT3L	0x00000000
+#define CONFIG_SYS_IBAT3U	0x00000000
+#define CONFIG_SYS_IBAT3L	0x00000000
 
-#define CFG_IBAT4U	0x00000000
-#define CFG_IBAT4L	0x00000000
+#define CONFIG_SYS_IBAT4U	0x00000000
+#define CONFIG_SYS_IBAT4L	0x00000000
 
-#define CFG_IBAT5U	0x00000000
-#define CFG_IBAT5L	0x00000000
+#define CONFIG_SYS_IBAT5U	0x00000000
+#define CONFIG_SYS_IBAT5L	0x00000000
 
-#define CFG_IBAT6U	0x00000000
-#define CFG_IBAT6L	0x00000000
+#define CONFIG_SYS_IBAT6U	0x00000000
+#define CONFIG_SYS_IBAT6L	0x00000000
 
-#define CFG_IBAT7U	0x00000000
-#define CFG_IBAT7L	0x00000000
+#define CONFIG_SYS_IBAT7U	0x00000000
+#define CONFIG_SYS_IBAT7L	0x00000000
 
-#define CFG_DBAT0U	0xE0003FFF
-#define CFG_DBAT0L	0xE000002A
+#define CONFIG_SYS_DBAT0U	0xE0003FFF
+#define CONFIG_SYS_DBAT0L	0xE000002A
 
-#define CFG_DBAT1U	0x00007FFF
-#define CFG_DBAT1L	0x00000012
+#define CONFIG_SYS_DBAT1U	0x00007FFF
+#define CONFIG_SYS_DBAT1L	0x00000012
 
-#define CFG_DBAT2U	0x00000000
-#define CFG_DBAT2L	0x00000000
+#define CONFIG_SYS_DBAT2U	0x00000000
+#define CONFIG_SYS_DBAT2L	0x00000000
 
-#define CFG_DBAT3U	0xC0000003
-#define CFG_DBAT3L	0xC000002A
+#define CONFIG_SYS_DBAT3U	0xC0000003
+#define CONFIG_SYS_DBAT3L	0xC000002A
 
-#define CFG_DBAT4U	0x00000000
-#define CFG_DBAT4L	0x00000000
+#define CONFIG_SYS_DBAT4U	0x00000000
+#define CONFIG_SYS_DBAT4L	0x00000000
 
-#define CFG_DBAT5U	0x00000000
-#define CFG_DBAT5L	0x00000000
+#define CONFIG_SYS_DBAT5U	0x00000000
+#define CONFIG_SYS_DBAT5L	0x00000000
 
-#define CFG_DBAT6U	0x00000000
-#define CFG_DBAT6L	0x00000000
+#define CONFIG_SYS_DBAT6U	0x00000000
+#define CONFIG_SYS_DBAT6L	0x00000000
 
-#define CFG_DBAT7U	0x00000000
-#define CFG_DBAT7L	0x00000000
+#define CONFIG_SYS_DBAT7U	0x00000000
+#define CONFIG_SYS_DBAT7L	0x00000000
 
 /* I2C addresses for the two DIMM SPD chips */
 #define DIMM0_I2C_ADDR	0x51
@@ -365,21 +365,21 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8<<20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	(8<<20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1		/* Flash can be at one of two addresses */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Flash can be at one of two addresses */
 #define FLASH_BANK_SIZE		0x01000000	/* 16 MB Total */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, /* CFG_FLASH_BASE2 */ }
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, /* CONFIG_SYS_FLASH_BASE2 */ }
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_WRITE_SWAPPED_DATA
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
 
 #define PHYS_FLASH_SIZE		0x01000000
-#define CFG_MAX_FLASH_SECT	(128)
+#define CONFIG_SYS_MAX_FLASH_SECT	(128)
 
 #define CONFIG_ENV_IS_IN_NVRAM
 #define CONFIG_ENV_ADDR		0xFC000000
@@ -390,16 +390,16 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
  * L2CR setup -- make sure this is right for your board!
  * look in include/mpc74xx.h for the defines used here
  */
-#undef CFG_L2
+#undef CONFIG_SYS_L2
 
 #define L2_INIT		0
 #define L2_ENABLE	(L2_INIT | L2CR_L2E)
@@ -411,5 +411,5 @@
  */
 #define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02	/* Software reboot */
-#define CFG_SERIAL_HANG_IN_EXCEPTION
+#define CONFIG_SYS_SERIAL_HANG_IN_EXCEPTION
 #endif	/* __CONFIG_H */
diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h
index 6b378ac..86f6a93 100644
--- a/include/configs/mpr2.h
+++ b/include/configs/mpr2.h
@@ -27,7 +27,7 @@
 #define __MPR2_H
 
 /* Supported commands */
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_FLASH
@@ -46,44 +46,44 @@
 #define CONFIG_MPR2		1
 
 /* U-Boot internals */
-#define CFG_LONGHELP			/* undef to save memory	*/
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
-#define CFG_CBSIZE		256	/* Buffer size for input from the Console */
-#define CFG_PBSIZE		256	/* Buffer size for Console output */
-#define CFG_MAXARGS		16	/* max args accepted for monitor commands */
-#define CFG_BARGSIZE		512	/* Buffer size for Boot Arguments passed to kernel */
-#define CFG_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */
-#define CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 32 * 1024 * 1024)
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(128 * 1024)
-#define CFG_MALLOC_LEN		(256 * 1024)
-#define CFG_GBL_DATA_SIZE	256
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		256	/* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE		256	/* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS		16	/* max args accepted for monitor commands */
+#define CONFIG_SYS_BARGSIZE		512	/* Buffer size for Boot Arguments passed to kernel */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	256
 
 /* Memory */
-#define CFG_SDRAM_BASE		0x8C000000
-#define CFG_SDRAM_SIZE		(64 * 1024 * 1024)
-#define CFG_MEMTEST_START	CFG_SDRAM_BASE
-#define CFG_MEMTEST_END		(CFG_MEMTEST_START + (60 * 1024 * 1024))
+#define CONFIG_SYS_SDRAM_BASE		0x8C000000
+#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
 
 /* Flash */
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_BASE		0xA0000000
-#define CFG_MAX_FLASH_SECT	256
-#define CFG_MAX_FLASH_BANKS	1
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BASE		0xA0000000
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	(128 * 1024)
 #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_FLASH_ERASE_TOUT	120000
-#define CFG_FLASH_WRITE_TOUT	500
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
 
 /* Clocks */
 #define CONFIG_SYS_CLK_FREQ	24000000
 #define TMU_CLK_DIVIDER		4	/* 4 (default), 16, 64, 256 or 1024 */
-#define CFG_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
 
 /* UART */
 #define CONFIG_SCIF_CONSOLE	1
diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h
index f308460..9a88ec7 100644
--- a/include/configs/ms7720se.h
+++ b/include/configs/ms7720se.h
@@ -31,7 +31,7 @@
 #define CONFIG_MS7720SE		1
 
 #define CONFIG_CMD_FLASH
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_CACHE
@@ -52,75 +52,75 @@
 #define MS7720SE_FLASH_BASE_1		0xA0000000
 #define MS7720SE_FLASH_BANK_SIZE	(8 * 1024 * 1024)
 
-#define CFG_LONGHELP		/* undef to save memory	*/
-#define CFG_PROMPT	"=> "	/* Monitor Command Prompt */
-#define CFG_CBSIZE	256	/* Buffer size for input from the Console */
-#define CFG_PBSIZE	256	/* Buffer size for Console output */
-#define CFG_MAXARGS	16	/* max args accepted for monitor commands */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
+#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256	/* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE	256	/* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS	16	/* max args accepted for monitor commands */
 /* Buffer size for Boot Arguments passed to kernel */
-#define CFG_BARGSIZE	512
+#define CONFIG_SYS_BARGSIZE	512
 /* List of legal baudrate settings for this board */
-#define CFG_BAUDRATE_TABLE	{ 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
 
 /* SCIF */
 #define CONFIG_SCIF_CONSOLE	1
 #define CONFIG_CONS_SCIF0	1
 
-#define CFG_MEMTEST_START	MS7720SE_SDRAM_BASE
-#define CFG_MEMTEST_END		(CFG_MEMTEST_START + (60 * 1024 * 1024))
+#define CONFIG_SYS_MEMTEST_START	MS7720SE_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
 
-#define CFG_SDRAM_BASE		MS7720SE_SDRAM_BASE
-#define CFG_SDRAM_SIZE		(64 * 1024 * 1024)
+#define CONFIG_SYS_SDRAM_BASE		MS7720SE_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
 
-#define CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 32 * 1024 * 1024)
-#define CFG_MONITOR_BASE	MS7720SE_FLASH_BASE_1
-#define CFG_MONITOR_LEN		(128 * 1024)
-#define CFG_MALLOC_LEN		(256 * 1024)
-#define CFG_GBL_DATA_SIZE	256
-#define CFG_BOOTMAPSZ		(8 * 1024 * 1024)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
+#define CONFIG_SYS_MONITOR_BASE	MS7720SE_FLASH_BASE_1
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	256
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 
 
 /* FLASH */
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#undef  CFG_FLASH_QUIET_TEST
-#define CFG_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
 
-#define CFG_FLASH_BASE		MS7720SE_FLASH_BASE_1
+#define CONFIG_SYS_FLASH_BASE		MS7720SE_FLASH_BASE_1
 
-#define CFG_MAX_FLASH_SECT	150
-#define CFG_MAX_FLASH_BANKS	1
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT	150
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	(64 * 1024)
 #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_FLASH_ERASE_TOUT	120000
-#define CFG_FLASH_WRITE_TOUT	500
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
 #define TMU_CLK_DIVIDER		4	/* 4 (default), 16, 64, 256 or 1024 */
-#define CFG_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
 
 /* PCMCIA */
 #define CONFIG_IDE_PCMCIA	1
 #define CONFIG_MARUBUN_PCCARD	1
 #define CONFIG_PCMCIA_SLOT_A	1
-#define CFG_IDE_MAXDEVICE	1
-#define CFG_MARUBUN_MRSHPC	0xb83fffe0
-#define CFG_MARUBUN_MW1		0xb8400000
-#define CFG_MARUBUN_MW2		0xb8500000
-#define CFG_MARUBUN_IO		0xb8600000
-
-#define CFG_PIO_MODE		1
-#define CFG_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_MARUBUN_MRSHPC	0xb83fffe0
+#define CONFIG_SYS_MARUBUN_MW1		0xb8400000
+#define CONFIG_SYS_MARUBUN_MW2		0xb8500000
+#define CONFIG_SYS_MARUBUN_IO		0xb8600000
+
+#define CONFIG_SYS_PIO_MODE		1
+#define CONFIG_SYS_IDE_MAXBUS		1
 #define CONFIG_DOS_PARTITION	1
-#define CFG_ATA_BASE_ADDR	CFG_MARUBUN_IO	/* base address */
-#define CFG_ATA_IDE0_OFFSET	0x01F0		/* ide0 offste */
-#define CFG_ATA_DATA_OFFSET	0		/* data reg offset */
-#define CFG_ATA_REG_OFFSET	0		/* reg offset */
-#define CFG_ATA_ALT_OFFSET	0x200		/* alternate register offset */
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_MARUBUN_IO	/* base address */
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x01F0		/* ide0 offste */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0		/* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET	0		/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x200		/* alternate register offset */
 
 #endif	/* __MS7720SE_H */
diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h
index 5f5970b..53ffbee 100644
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@@ -31,11 +31,14 @@
 #define CONFIG_MS7722SE		1
 
 #define CONFIG_CMD_FLASH
+#define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DFL
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_SAVEENV
 
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTDELAY	3
@@ -53,79 +56,79 @@
 #define MS7722SE_FLASH_BASE_1	(0xA0000000)
 #define MS7722SE_FLASH_BANK_SIZE	(8*1024 * 1024)
 
-#define CFG_LONGHELP				/* undef to save memory	*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
-#define CFG_CBSIZE		256		/* Buffer size for input from the Console */
-#define CFG_PBSIZE		256		/* Buffer size for Console output */
-#define CFG_MAXARGS		16		/* max args accepted for monitor commands */
-#define CFG_BARGSIZE		512		/* Buffer size for Boot Arguments passed to kernel */
-#define CFG_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory	*/
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		256		/* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE		256		/* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS		16		/* max args accepted for monitor commands */
+#define CONFIG_SYS_BARGSIZE		512		/* Buffer size for Boot Arguments passed to kernel */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */
 
 /* SCIF */
 #define CONFIG_SCIF_CONSOLE	1
 #define CONFIG_CONS_SCIF0	1
-#undef  CFG_CONSOLE_INFO_QUIET			/* Suppress display of console information at boot */
-#undef  CFG_CONSOLE_OVERWRITE_ROUTINE
-#undef  CFG_CONSOLE_ENV_OVERWRITE
+#undef  CONFIG_SYS_CONSOLE_INFO_QUIET			/* Suppress display of console information at boot */
+#undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 
-#define CFG_MEMTEST_START	(MS7722SE_SDRAM_BASE)
-#define CFG_MEMTEST_END		(CFG_MEMTEST_START + (60 * 1024 * 1024))
+#define CONFIG_SYS_MEMTEST_START	(MS7722SE_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
 
-#undef  CFG_ALT_MEMTEST		/* Enable alternate, more extensive, memory test */
-#undef  CFG_MEMTEST_SCRATCH	/* Scratch address used by the alternate memory test */
+#undef  CONFIG_SYS_ALT_MEMTEST		/* Enable alternate, more extensive, memory test */
+#undef  CONFIG_SYS_MEMTEST_SCRATCH	/* Scratch address used by the alternate memory test */
 
-#undef  CFG_LOADS_BAUD_CHANGE	/* Enable temporary baudrate change while serial download */
+#undef  CONFIG_SYS_LOADS_BAUD_CHANGE	/* Enable temporary baudrate change while serial download */
 
-#define CFG_SDRAM_BASE	(MS7722SE_SDRAM_BASE)
-#define CFG_SDRAM_SIZE	(64 * 1024 * 1024)	/* maybe more, but if so u-boot doesn't know about it... */
+#define CONFIG_SYS_SDRAM_BASE	(MS7722SE_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE	(64 * 1024 * 1024)	/* maybe more, but if so u-boot doesn't know about it... */
 
-#define CFG_LOAD_ADDR	(CFG_SDRAM_BASE + 4 * 1024 * 1024)	/* default load address for scripts ?!? */
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)	/* default load address for scripts ?!? */
 
-#define CFG_MONITOR_BASE	(MS7722SE_FLASH_BASE_1)	/* Address of u-boot image
+#define CONFIG_SYS_MONITOR_BASE	(MS7722SE_FLASH_BASE_1)	/* Address of u-boot image
 							in Flash (NOT run time address in SDRAM) ?!? */
-#define CFG_MONITOR_LEN	(128 * 1024)		/* */
-#define CFG_MALLOC_LEN	(256 * 1024)		/* Size of DRAM reserved for malloc() use */
-#define CFG_GBL_DATA_SIZE	(256)		/* size in bytes reserved for initial data */
-#define CFG_BOOTMAPSZ	(8 * 1024 * 1024)
+#define CONFIG_SYS_MONITOR_LEN	(128 * 1024)		/* */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)		/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_GBL_DATA_SIZE	(256)		/* size in bytes reserved for initial data */
+#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
 
 /* FLASH */
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#undef  CFG_FLASH_QUIET_TEST
-#define CFG_FLASH_EMPTY_INFO			/* print 'E' for empty sector on flinfo */
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO			/* print 'E' for empty sector on flinfo */
 
-#define CFG_FLASH_BASE		(MS7722SE_FLASH_BASE_1)	/* Physical start address of Flash memory */
+#define CONFIG_SYS_FLASH_BASE		(MS7722SE_FLASH_BASE_1)	/* Physical start address of Flash memory */
 
-#define CFG_MAX_FLASH_SECT	150		/* Max number of sectors on each
+#define CONFIG_SYS_MAX_FLASH_SECT	150		/* Max number of sectors on each
 							Flash chip */
 
 /* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */
-#define CFG_MAX_FLASH_BANKS	2
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE + (0 * MS7722SE_FLASH_BANK_SIZE), \
-				  CFG_FLASH_BASE + (1 * MS7722SE_FLASH_BANK_SIZE), \
+#define CONFIG_SYS_MAX_FLASH_BANKS	2
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE + (0 * MS7722SE_FLASH_BANK_SIZE), \
+				  CONFIG_SYS_FLASH_BASE + (1 * MS7722SE_FLASH_BANK_SIZE), \
 				}
 
-#define CFG_FLASH_ERASE_TOUT	(3 * 1000)	/* Timeout for Flash erase operations (in ms) */
-#define CFG_FLASH_WRITE_TOUT	(3 * 1000)	/* Timeout for Flash write operations (in ms) */
-#define CFG_FLASH_LOCK_TOUT	(3 * 1000)	/* Timeout for Flash set sector lock bit operations (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	(3 * 1000)	/* Timeout for Flash clear lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)	/* Timeout for Flash erase operations (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)	/* Timeout for Flash write operations (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)	/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)	/* Timeout for Flash clear lock bit operations (in ms) */
 
-#undef  CFG_FLASH_PROTECTION			/* Use hardware flash sectors protection instead of U-Boot software protection */
+#undef  CONFIG_SYS_FLASH_PROTECTION			/* Use hardware flash sectors protection instead of U-Boot software protection */
 
-#undef  CFG_DIRECT_FLASH_TFTP
+#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
 
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_OVERWRITE	1
 #define CONFIG_ENV_SECT_SIZE	(8 * 1024)
 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
-#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CFG_FLASH_BASE)	/* Offset of env Flash sector relative to CFG_FLASH_BASE */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
+#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)	/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
 #define TMU_CLK_DIVIDER		(4)	/* 4 (default), 16, 64, 256 or 1024 */
-#define CFG_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
 
 #endif	/* __MS7722SE_H */
diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h
index acb4d6d..5eed3ab 100644
--- a/include/configs/ms7750se.h
+++ b/include/configs/ms7750se.h
@@ -40,7 +40,7 @@
 
 #define CONFIG_CMD_DFL
 #define CONFIG_CMD_FLASH
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 
 #define CONFIG_SCIF_CONSOLE	1
 #define CONFIG_BAUDRATE		38400
@@ -52,56 +52,56 @@
 #define CONFIG_ENV_OVERWRITE	1
 
 /* SDRAM */
-#define CFG_SDRAM_BASE		(0x8C000000)
-#define CFG_SDRAM_SIZE		(64 * 1024 * 1024)
-
-#define CFG_LONGHELP
-#define CFG_PROMPT		"=> "
-#define CFG_CBSIZE		256
-#define CFG_PBSIZE		256
-#define CFG_MAXARGS		16
-#define CFG_BARGSIZE		512
+#define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
+#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
 /* List of legal baudrate settings for this board */
-#define CFG_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
 
-#define CFG_MEMTEST_START	(CFG_SDRAM_BASE)
-#define CFG_MEMTEST_END		(TEXT_BASE - 0x100000)
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(TEXT_BASE - 0x100000)
 
 /* NOR Flash */
-/* #define CFG_FLASH_BASE		(0xA1000000)*/
-#define CFG_FLASH_BASE		(0xA0000000)
-#define CFG_MAX_FLASH_BANKS	(1)	/* Max number of
+/* #define CONFIG_SYS_FLASH_BASE		(0xA1000000)*/
+#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
+#define CONFIG_SYS_MAX_FLASH_BANKS	(1)	/* Max number of
 					 * Flash memory banks
 					 */
-#define CFG_MAX_FLASH_SECT	142
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT	142
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 
-#define CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 4 * 1024 * 1024)
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE)	/* Address of u-boot image in Flash */
-#define CFG_MONITOR_LEN		(128 * 1024)
-#define CFG_MALLOC_LEN		(256 * 1024)		/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)	/* Address of u-boot image in Flash */
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)		/* Size of DRAM reserved for malloc() use */
 
-#define CFG_GBL_DATA_SIZE	(256)			/* size in bytes reserved for initial data */
-#define CFG_BOOTMAPSZ		(8 * 1024 * 1024)
-#define CFG_RX_ETH_BUFFER	(8)
+#define CONFIG_SYS_GBL_DATA_SIZE	(256)			/* size in bytes reserved for initial data */
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+#define CONFIG_SYS_RX_ETH_BUFFER	(8)
 
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#undef CFG_FLASH_CFI_BROKEN_TABLE
-#undef  CFG_FLASH_QUIET_TEST
-#define CFG_FLASH_EMPTY_INFO				/* print 'E' for empty sector on flinfo */
+#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO				/* print 'E' for empty sector on flinfo */
 
 
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000
 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_FLASH_ERASE_TOUT	120000
-#define CFG_FLASH_WRITE_TOUT	500
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
 #define TMU_CLK_DIVIDER		4
-#define CFG_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
 
 #endif /* __MS7750SE_H */
diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h
index c661829..f031a17 100644
--- a/include/configs/muas3001.h
+++ b/include/configs/muas3001.h
@@ -80,39 +80,39 @@
  * - Rx-CLK is CLK11
  * - Tx-CLK is CLK12
  */
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
-# define CFG_CMXFCR_MASK	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
 /*
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  */
-# define CFG_CPMFCR_RAMTYPE	(0)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	(0)
 /* know on local Bus */
-/* define CFG_CPMFCR_RAMTYPE	(CPMFCR_DTB | CPMFCR_BDB) */
+/* define CONFIG_SYS_CPMFCR_RAMTYPE	(CPMFCR_DTB | CPMFCR_BDB) */
 /*
  * - Enable Full Duplex in FSMR
  */
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 #define CONFIG_MII			/* MII PHY management		*/
 #define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
-# define CFG_PHY_ADDR		1
+# define CONFIG_SYS_PHY_ADDR		1
 /*
  * GPIO pins used for bit-banged MII communications
  */
 #define MDIO_PORT	0		/* Port A */
 
-#define CFG_MDIO_PIN	0x00200000	/* PA10 */
-#define CFG_MDC_PIN	0x00400000	/* PA9  */
+#define CONFIG_SYS_MDIO_PIN	0x00200000	/* PA10 */
+#define CONFIG_SYS_MDC_PIN	0x00400000	/* PA9  */
 
-#define MDIO_ACTIVE	(iop->pdir |=  CFG_MDIO_PIN)
-#define MDIO_TRISTATE	(iop->pdir &= ~CFG_MDIO_PIN)
-#define MDIO_READ	((iop->pdat &  CFG_MDIO_PIN) != 0)
+#define MDIO_ACTIVE	(iop->pdir |=  CONFIG_SYS_MDIO_PIN)
+#define MDIO_TRISTATE	(iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
+#define MDIO_READ	((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 
-#define MDIO(bit)	if(bit) iop->pdat |=  CFG_MDIO_PIN; \
-			else	iop->pdat &= ~CFG_MDIO_PIN
+#define MDIO(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
+			else	iop->pdat &= ~CONFIG_SYS_MDIO_PIN
 
-#define MDC(bit)	if(bit) iop->pdat |=  CFG_MDC_PIN; \
-			else	iop->pdat &= ~CFG_MDC_PIN
+#define MDC(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
+			else	iop->pdat &= ~CONFIG_SYS_MDC_PIN
 
 #define MIIDELAY	udelay(1)
 
@@ -188,108 +188,107 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size  */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size  */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFF000000
-#define CFG_FLASH_SIZE		32
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_FLASH_SIZE		32
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
-#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
 
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256KB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256KB for Monitor */
 
 #define CONFIG_ENV_IS_IN_FLASH
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #endif /* CONFIG_ENV_IS_IN_FLASH */
 
 /*
  * I2C Bus
  */
 #define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define	CFG_EEPROM_PAGE_WRITE_ENABLE
-#define	CFG_EEPROM_PAGE_WRITE_BITS 3
+#define	CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 #define	CONFIG_DTT_LM75		1	/* ON Semi's LM75               */
 #define	CONFIG_DTT_SENSORS	{0}	/* Sensor addresses             */
-#define	CFG_DTT_MAX_TEMP	70
-#define	CFG_DTT_LOW_TEMP	-30
-#define	CFG_DTT_HYSTERESIS	3
+#define	CONFIG_SYS_DTT_MAX_TEMP	70
+#define	CONFIG_SYS_DTT_LOW_TEMP	-30
+#define	CONFIG_SYS_DTT_HYSTERESIS	3
 
-#define CFG_IMMR		0xF0000000
-#define CFG_DEFAULT_IMMR	0x0F010000
+#define CONFIG_SYS_IMMR		0xF0000000
+#define CONFIG_SYS_DEFAULT_IMMR	0x0F010000
 
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* Hard reset configuration word */
-#define CFG_HRCW_MASTER		0x0E028200	/* BPS=11 CIP=1 ISB=010 BMS=1 */
+#define CONFIG_SYS_HRCW_MASTER		0x0E028200	/* BPS=11 CIP=1 ISB=010 BMS=1 */
 
 /* No slaves */
-#define CFG_HRCW_SLAVE1 	0
-#define CFG_HRCW_SLAVE2 	0
-#define CFG_HRCW_SLAVE3 	0
-#define CFG_HRCW_SLAVE4 	0
-#define CFG_HRCW_SLAVE5 	0
-#define CFG_HRCW_SLAVE6 	0
-#define CFG_HRCW_SLAVE7 	0
+#define CONFIG_SYS_HRCW_SLAVE1 	0
+#define CONFIG_SYS_HRCW_SLAVE2 	0
+#define CONFIG_SYS_HRCW_SLAVE3 	0
+#define CONFIG_SYS_HRCW_SLAVE4 	0
+#define CONFIG_SYS_HRCW_SLAVE5 	0
+#define CONFIG_SYS_HRCW_SLAVE6 	0
+#define CONFIG_SYS_HRCW_SLAVE7 	0
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot                  */
 
-#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
 
-#define CFG_HID2		0
+#define CONFIG_SYS_HID2		0
 
-#define CFG_SIUMCR		0x00200000
-#define CFG_BCR			0x004c0000
-#define CFG_SCCR		0x0
+#define CONFIG_SYS_SIUMCR		0x00200000
+#define CONFIG_SYS_BCR			0x004c0000
+#define CONFIG_SYS_SCCR		0x0
 
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control                             4-35
@@ -298,10 +297,10 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
@@ -310,7 +309,7 @@
  *-----------------------------------------------------------------------
  * turn on Checkstop Reset Enable
  */
-#define CFG_RMR         0
+#define CONFIG_SYS_RMR         0
 
 /*-----------------------------------------------------------------------
  * TMCNTSC - Time Counter Status and Control                     4-40
@@ -318,7 +317,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control                 4-42
@@ -326,13 +325,13 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration                         13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR        0
+#define CONFIG_SYS_RCCR        0
 
 /*
  * Init Memory Controller:
@@ -346,60 +345,60 @@
  */
 /* Bank 0 - FLASH
  */
-#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_32			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM (0xff000020)
+#define CONFIG_SYS_OR0_PRELIM (0xff000020)
 
 /* Bank 1 - 60x bus SDRAM
  */
-#define CFG_GLOBAL_SDRAM_LIMIT	(256 << 20)	/* less than 256 MB */
+#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(256 << 20)	/* less than 256 MB */
 
-#define CFG_MPTPR       0x2800
+#define CONFIG_SYS_MPTPR       0x2800
 
 /*-----------------------------------------------------------------------------
  * Address for Mode Register Set (MRS) command
  *-----------------------------------------------------------------------------
  */
-#define CFG_MRS_OFFS	0x00000110
-#define CFG_PSRT        0x13
+#define CONFIG_SYS_MRS_OFFS	0x00000110
+#define CONFIG_SYS_PSRT        0x13
 
-#define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_64                      |\
 			 BRx_MS_SDRAM_P                 |\
 			 BRx_V)
 
-#define CFG_OR1_PRELIM	CFG_OR1_LITTLE
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR1_LITTLE
 
 /* SDRAM initialization values
 */
-#define CFG_OR1_LITTLE	((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+#define CONFIG_SYS_OR1_LITTLE	((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI1_A7		|\
 			 ORxS_NUMR_12)
 
-#define CFG_PSDMR_LITTLE	0x004b36a3
+#define CONFIG_SYS_PSDMR_LITTLE	0x004b36a3
 
-#define CFG_OR1_BIG	((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+#define CONFIG_SYS_OR1_BIG	((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI1_A4		|\
 			 ORxS_NUMR_12)
 
-#define CFG_PSDMR_BIG		0x014f36a3
+#define CONFIG_SYS_PSDMR_BIG		0x014f36a3
 
 /* IO on CS4 initialization values
 */
-#define CFG_IO_BASE	0xc0000000
-#define CFG_IO_SIZE	1
+#define CONFIG_SYS_IO_BASE	0xc0000000
+#define CONFIG_SYS_IO_SIZE	1
 
-#define CFG_BR4_PRELIM	((CFG_IO_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR4_PRELIM	((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\
 			 BRx_PS_16 | BRx_MS_GPCM_L | BRx_V)
 
-#define CFG_OR4_PRELIM	(0xfff80020)
+#define CONFIG_SYS_OR4_PRELIM	(0xfff80020)
 
-#define	CFG_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
+#define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
 
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
diff --git a/include/configs/mucmc52.h b/include/configs/mucmc52.h
index 8971f0b..ae60cd2 100644
--- a/include/configs/mucmc52.h
+++ b/include/configs/mucmc52.h
@@ -36,14 +36,14 @@
 #define	CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
 #define	CONFIG_MUCMC52		1	/* MUCMC52 board			*/
 
-#define	CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
+#define	CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
 
 #define	BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
 #define	BOOTFLAG_WARM		0x02	/* Software reboot			*/
 
-#define	CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define	CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#define	CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
+#if (CONFIG_COMMANDS & CONFIG_SYS_CMD_KGDB)
+#  define	CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 #define	CONFIG_BOARD_EARLY_INIT_R
@@ -56,7 +56,7 @@
  */
 #define	CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
 #define	CONFIG_BAUDRATE		38400	/* ... at 38400 bps	*/
-#define	CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define	CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /* Partitions */
 #define	CONFIG_DOS_PARTITION
@@ -83,7 +83,7 @@
 #define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
 
 #if (TEXT_BASE == 0xFFF00000) /* Boot low */
-#   define	CFG_LOWBOOT		1
+#   define	CONFIG_SYS_LOWBOOT		1
 #endif
 
 /*
@@ -118,58 +118,56 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef	CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#undef	CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * I2C configuration
  */
 #define	CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define	CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+#define	CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
 
-#define	CFG_I2C_SPEED		100000 /* 100 kHz */
-#define	CFG_I2C_SLAVE		0x7F
+#define	CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define	CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration
  */
-#define	CFG_I2C_EEPROM_ADDR		0x58
-#define	CFG_I2C_EEPROM_ADDR_LEN		1
-#define	CFG_EEPROM_PAGE_WRITE_BITS	4
-#define	CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
-/* for LM81 */
-#define	CFG_EEPROM_PAGE_WRITE_ENABLE
+#define	CONFIG_SYS_I2C_EEPROM_ADDR		0x58
+#define	CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define	CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define	CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 
 /*
  * RTC configuration
  */
 #define	CONFIG_RTC_PCF8563
-#define	CFG_I2C_RTC_ADDR		0x51
+#define	CONFIG_SYS_I2C_RTC_ADDR		0x51
 
 /* I2C SYSMON (LM75) */
 #define	CONFIG_DTT_LM81			1	/* ON Semi's LM75		*/
 #define	CONFIG_DTT_SENSORS		{0}	/* Sensor addresses		*/
-#define	CFG_DTT_MAX_TEMP		70
-#define	CFG_DTT_LOW_TEMP		-30
-#define	CFG_DTT_HYSTERESIS		3
+#define	CONFIG_SYS_DTT_MAX_TEMP		70
+#define	CONFIG_SYS_DTT_LOW_TEMP		-30
+#define	CONFIG_SYS_DTT_HYSTERESIS		3
 
 /*
  * Flash configuration
  */
-#define	CFG_FLASH_BASE		0xFF800000
+#define	CONFIG_SYS_FLASH_BASE		0xFF800000
 
-#define	CFG_FLASH_SIZE		0x00800000 /* 8 MByte */
-#define	CFG_MAX_FLASH_SECT	67	/* max num of sects on one chip */
+#define	CONFIG_SYS_FLASH_SIZE		0x00800000 /* 8 MByte */
+#define	CONFIG_SYS_MAX_FLASH_SECT	67	/* max num of sects on one chip */
 
 #define	CONFIG_ENV_ADDR		(TEXT_BASE+0x40000) /* second sector */
-#define	CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+#define	CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
 					   (= chip selects) */
-#define	CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define	CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define	CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define	CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
 
 #define	CONFIG_FLASH_CFI_DRIVER
-#define	CFG_FLASH_CFI
-#define	CFG_FLASH_EMPTY_INFO
-#define	CFG_FLASH_CFI_AMD_RESET
+#define	CONFIG_SYS_FLASH_CFI
+#define	CONFIG_SYS_FLASH_EMPTY_INFO
+#define	CONFIG_SYS_FLASH_CFI_AMD_RESET
 
 /*
  * Environment settings
@@ -183,14 +181,14 @@
 /*
  * Memory map
  */
-#define	CFG_MBAR		0xF0000000
-#define	CFG_SDRAM_BASE		0x00000000
-#define	CFG_DEFAULT_MBAR	0x80000000
-#define	CFG_DISPLAY_BASE	0x80600000
-#define	CFG_STATUS1_BASE	0x80600200
-#define	CFG_STATUS2_BASE	0x80600300
-#define	CFG_PMI_UNI_BASE	0x80800000
-#define	CFG_PMI_BROAD_BASE	0x80810000
+#define	CONFIG_SYS_MBAR		0xF0000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define	CONFIG_SYS_DEFAULT_MBAR	0x80000000
+#define	CONFIG_SYS_DISPLAY_BASE	0x80600000
+#define	CONFIG_SYS_STATUS1_BASE	0x80600200
+#define	CONFIG_SYS_STATUS2_BASE	0x80600300
+#define	CONFIG_SYS_PMI_UNI_BASE	0x80800000
+#define	CONFIG_SYS_PMI_BROAD_BASE	0x80810000
 
 /* Settings for XLB = 132 MHz */
 #define	SDRAM_DDR	 1
@@ -202,38 +200,39 @@
 #define	SDRAM_TAPDELAY  0x10000000
 
 /* Use ON-Chip SRAM until RAM will be available */
-#define	CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define	CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-#define	CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#define	CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
 #else
-#define	CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define	CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
 #endif
 
-#define	CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define	CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define	CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define	CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define	CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define	CFG_RAMBOOT	1
+#define	CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define	CONFIG_SYS_RAMBOOT	1
 #endif
 
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define	CFG_MALLOC_LEN		(512 << 10)	/* Reserve 128 kB for malloc()	*/
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define	CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
  */
 #define	CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
 #define	CONFIG_PHY_ADDR		0x00
 #define	CONFIG_MII		1		/* MII PHY management		*/
 
 /*
  * GPIO configuration
  */
-#define	CFG_GPS_PORT_CONFIG	0x8D550644
+#define	CONFIG_SYS_GPS_PORT_CONFIG	0x8D550644
 
 /*use  Hardware WDT */
 #define CONFIG_HW_WATCHDOG
@@ -241,29 +240,29 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory	    */
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CONFIG_SYS_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args	*/
-#define	CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
 /* Enable an alternate, more extensive memory test */
-#define	CFG_ALT_MEMTEST
+#define	CONFIG_SYS_ALT_MEMTEST
 
-#define	CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define	CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define	CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define	CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address */
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 /*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
+ * Enable loopw commando. This has only affect, if CONFIG_SYS_CMD_MEM is defined,
  * which is normally part of the default commands (CFV_CMD_DFL)
  */
 #define	CONFIG_LOOPW
@@ -272,46 +271,46 @@
  * Various low-level settings
  */
 #if defined(CONFIG_MPC5200)
-#define	CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define	CFG_HID0_FINAL		HID0_ICE
+#define	CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define	CONFIG_SYS_HID0_FINAL		HID0_ICE
 #else
-#define	CFG_HID0_INIT		0
-#define	CFG_HID0_FINAL		0
+#define	CONFIG_SYS_HID0_INIT		0
+#define	CONFIG_SYS_HID0_FINAL		0
 #endif
 
-#define	CFG_BOOTCS_START	CFG_FLASH_BASE
-#define	CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define	CFG_BOOTCS_CFG		0x0004FB00
-#define	CFG_CS0_START		CFG_FLASH_BASE
-#define	CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define	CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define	CONFIG_SYS_BOOTCS_CFG		0x0004FB00
+#define	CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
 /* 8Mbit SRAM @0x80100000 */
-#define	CFG_CS1_START		0x80100000
-#define	CFG_CS1_SIZE		0x00100000
-#define	CFG_CS1_CFG		0x00019B00
+#define	CONFIG_SYS_CS1_START		0x80100000
+#define	CONFIG_SYS_CS1_SIZE		0x00100000
+#define	CONFIG_SYS_CS1_CFG		0x00019B00
 
 /* FRAM 32Kbyte @0x80700000 */
-#define	CFG_CS2_START		0x80700000
-#define	CFG_CS2_SIZE		0x00008000
-#define	CFG_CS2_CFG		0x00019800
+#define	CONFIG_SYS_CS2_START		0x80700000
+#define	CONFIG_SYS_CS2_SIZE		0x00008000
+#define	CONFIG_SYS_CS2_CFG		0x00019800
 
 /* Display H1, Status Inputs, EPLD @0x80600000 */
-#define	CFG_CS3_START		0x80600000
-#define	CFG_CS3_SIZE		0x00100000
-#define	CFG_CS3_CFG		0x00019800
+#define	CONFIG_SYS_CS3_START		0x80600000
+#define	CONFIG_SYS_CS3_SIZE		0x00100000
+#define	CONFIG_SYS_CS3_CFG		0x00019800
 
 /* PMI Unicast 32Kbyte @0x80800000 */
-#define	CFG_CS6_START		CFG_PMI_UNI_BASE
-#define	CFG_CS6_SIZE		0x00008000
-#define	CFG_CS6_CFG		0xFFFFF930
+#define	CONFIG_SYS_CS6_START		CONFIG_SYS_PMI_UNI_BASE
+#define	CONFIG_SYS_CS6_SIZE		0x00008000
+#define	CONFIG_SYS_CS6_CFG		0xFFFFF930
 
 /* PMI Broadcast 32Kbyte @0x80810000 */
-#define	CFG_CS7_START		CFG_PMI_BROAD_BASE
-#define	CFG_CS7_SIZE		0x00008000
-#define	CFG_CS7_CFG		0xFF00F930
+#define	CONFIG_SYS_CS7_START		CONFIG_SYS_PMI_BROAD_BASE
+#define	CONFIG_SYS_CS7_SIZE		0x00008000
+#define	CONFIG_SYS_CS7_CFG		0xFF00F930
 
-#define	CFG_CS_BURST		0x00000000
-#define	CFG_CS_DEADCYCLE	0x33333333
+#define	CONFIG_SYS_CS_BURST		0x00000000
+#define	CONFIG_SYS_CS_DEADCYCLE	0x33333333
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff Supports IDE harddisk
@@ -323,26 +322,26 @@
 #undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 
-#define	CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define	CFG_IDE_MAXDEVICE	1	/* max. 2 drives per IDE bus	*/
+#define	CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define	CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 2 drives per IDE bus	*/
 
 #define	CONFIG_IDE_PREINIT	1
 
-#define	CFG_ATA_IDE0_OFFSET	0x0000
+#define	CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define	CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define	CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
 
 /* Offset for data I/O			*/
-#define	CFG_ATA_DATA_OFFSET	(0x0060)
+#define	CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
 
 /* Offset for normal register accesses	*/
-#define	CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+#define	CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
 
 /* Offset for alternate registers	*/
-#define	CFG_ATA_ALT_OFFSET	(0x005C)
+#define	CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
 
 /* Interval between registers           */
-#define	CFG_ATA_STRIDE          4
+#define	CONFIG_SYS_ATA_STRIDE          4
 
 #define	CONFIG_ATAPI            1
 
@@ -364,13 +363,13 @@
 #define	CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
 #define	CONFIG_PCI_IO_SIZE	0x01000000
 
-#define	CFG_ISA_IO		CONFIG_PCI_IO_BUS
+#define	CONFIG_SYS_ISA_IO		CONFIG_PCI_IO_BUS
 
 /*---------------------------------------------------------------------*/
 /* Display addresses						       */
 /*---------------------------------------------------------------------*/
 
-#define	CFG_DISP_CHR_RAM	(CFG_DISPLAY_BASE + 0x38)
-#define	CFG_DISP_CWORD		(CFG_DISPLAY_BASE + 0x30)
+#define	CONFIG_SYS_DISP_CHR_RAM	(CONFIG_SYS_DISPLAY_BASE + 0x38)
+#define	CONFIG_SYS_DISP_CWORD		(CONFIG_SYS_DISPLAY_BASE + 0x30)
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/munices.h b/include/configs/munices.h
index 8f3071a..fa5230f 100644
--- a/include/configs/munices.h
+++ b/include/configs/munices.h
@@ -31,10 +31,10 @@
 #define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
 #define CONFIG_MPC5200_DDR	1	/* (with DDR-SDRAM) */
 #define CONFIG_MUNICES		1	/* ... on MUNICes board */
-#define CFG_MPC5XXX_CLKIN	33333333 /* ... running at 33.333333MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33333333 /* ... running at 33.333333MHz */
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /*
@@ -50,7 +50,7 @@
 #define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*
@@ -58,7 +58,7 @@
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
 #define CONFIG_BOOTDELAY	5   /* autoboot after 5 seconds */
@@ -91,63 +91,63 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define  CFG_IPBSPEED_133		/* define for 133MHz speed */
-#if defined(CFG_IPBSPEED_133)
+#define  CONFIG_SYS_IPBSPEED_133		/* define for 133MHz speed */
+#if defined(CONFIG_SYS_IPBSPEED_133)
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
+ * CONFIG_SYS_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
  * been tested with a IPB Bus Clock of 66 MHz.
  */
-#define CFG_PCISPEED_66		/* define for 66MHz speed */
+#define CONFIG_SYS_PCISPEED_66		/* define for 66MHz speed */
 #else
-#undef CFG_PCISPEED_66			/* for 33MHz speed */
+#undef CONFIG_SYS_PCISPEED_66			/* for 33MHz speed */
 #endif
 
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000 /* MBAR hast to be switched by other bootloader or debugger config  */
+#define CONFIG_SYS_MBAR		0xF0000000 /* MBAR hast to be switched by other bootloader or debugger config  */
 
-#define CFG_DEFAULT_MBAR	0x80000000
-#define CFG_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Flash configuration
  */
-#define CFG_FLASH_BASE		0xFF000000
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_SIZE		0x01000000 /* 16 MByte */
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-#define CFG_MAX_FLASH_BANKS	1	 /* max num of flash banks (= chip selects) */
-#define CFG_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_SIZE		0x01000000 /* 16 MByte */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	 /* max num of flash banks (= chip selects) */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
 
 /*
  * Chip selects configuration
  */
 /* Boot Chipselect */
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x00047800
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047800
 
 /*
  * Environment settings
@@ -166,30 +166,31 @@
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
 #define CONFIG_PHY_ADDR		0x01
 #define CONFIG_MII		1
 
 /*
  * GPIO configuration
  */
-#define CFG_GPS_PORT_CONFIG	0x00058044 /* PSC1=UART, PSC2=UART ; Ether=100MBit with MD
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x00058044 /* PSC1=UART, PSC2=UART ; Ether=100MBit with MD
 						no PCI */
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x200000	/* default load address */
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_DISPLAY_BOARDINFO 1
 #define CONFIG_CMDLINE_EDITING  1
@@ -197,12 +198,12 @@
 /*
  * Various low-level settings
  */
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
-#define CFG_RESET_ADDRESS	0xff000000
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
 
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h
index 2eb43bf..f136b0c 100644
--- a/include/configs/mx1ads.h
+++ b/include/configs/mx1ads.h
@@ -48,19 +48,19 @@
 #define USE_920T_MMU		1
 
 #if 0
-#define CFG_MX1_GPCR		0x000003AB	/* for MX1ADS 0L44N		*/
-#define CFG_MX1_GPCR		0x000003AB	/* for MX1ADS 0L44N		*/
-#define CFG_MX1_GPCR		0x000003AB	/* for MX1ADS 0L44N		*/
+#define CONFIG_SYS_MX1_GPCR		0x000003AB	/* for MX1ADS 0L44N		*/
+#define CONFIG_SYS_MX1_GPCR		0x000003AB	/* for MX1ADS 0L44N		*/
+#define CONFIG_SYS_MX1_GPCR		0x000003AB	/* for MX1ADS 0L44N		*/
 #endif
 
 /*
  * Size of malloc() pool
  */
 
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  *  CS8900 Ethernet drivers
@@ -113,34 +113,34 @@
  * Miscellaneous configurable options
  */
 
-#define CFG_HUSH_PARSER		1
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
-#define CFG_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
 
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT		"MX1ADS$ "	/* Monitor Command Prompt */
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"MX1ADS$ "	/* Monitor Command Prompt */
 #else
-#define CFG_PROMPT		"MX1ADS=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT		"MX1ADS=> "	/* Monitor Command Prompt */
 #endif
 
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 						/* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x09000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0AF00000	/* 63 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x09000000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0AF00000	/* 63 MB in DRAM	*/
 
-#undef	CFG_CLKS_IN_HZ				/* everything, incl board info, in Hz */
-#define CFG_LOAD_ADDR		0x08800000	/* default load address */
-/*#define	CFG_HZ			1000 */
-#define CFG_HZ			3686400
-#define CFG_CPUSPEED		0x141
+#undef	CONFIG_SYS_CLKS_IN_HZ				/* everything, incl board info, in Hz */
+#define CONFIG_SYS_LOAD_ADDR		0x08800000	/* default load address */
+/*#define	CONFIG_SYS_HZ			1000 */
+#define CONFIG_SYS_HZ			3686400
+#define CONFIG_SYS_CPUSPEED		0x141
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -161,8 +161,8 @@
 #define PHYS_SDRAM_1		0x08000000	/* SDRAM  on CSD0		*/
 #define PHYS_SDRAM_1_SIZE	0x04000000	/* 64 MB			*/
 
-#define CFG_MAX_FLASH_BANKS	1		/* 1 bank of SyncFlash		*/
-#define CFG_FLASH_BASE		0x0C000000	/* SyncFlash on CSD1		*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* 1 bank of SyncFlash		*/
+#define CONFIG_SYS_FLASH_BASE		0x0C000000	/* SyncFlash on CSD1		*/
 #define FLASH_BANK_SIZE		0x01000000	/* 16 MB Total			*/
 
 /*-----------------------------------------------------------------------
@@ -171,8 +171,8 @@
 
 #define CONFIG_SYNCFLASH	1
 #define PHYS_FLASH_SIZE		0x01000000
-#define CFG_MAX_FLASH_SECT	(16)
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE+0x00ff8000)
+#define CONFIG_SYS_MAX_FLASH_SECT	(16)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x00ff8000)
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SIZE		0x04000 /* Total Size of Environment Sector */
diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h
index 39950dc..aaa4e98 100644
--- a/include/configs/mx1fs2.h
+++ b/include/configs/mx1fs2.h
@@ -70,22 +70,22 @@
 /*
  * General options for u-boot. Modify to save memory foot print
  */
-#define CFG_LONGHELP				      /* undef saves memory  */
-#define CFG_PROMPT		"mx1fs2> "	      /* prompt string	     */
-#define CFG_CBSIZE		256		      /* console I/O buffer  */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size   */
-#define CFG_MAXARGS		16		      /* max command args    */
-#define CFG_BARGSIZE		CFG_CBSIZE	      /* boot args buf size  */
+#define CONFIG_SYS_LONGHELP				      /* undef saves memory  */
+#define CONFIG_SYS_PROMPT		"mx1fs2> "	      /* prompt string	     */
+#define CONFIG_SYS_CBSIZE		256		      /* console I/O buffer  */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size   */
+#define CONFIG_SYS_MAXARGS		16		      /* max command args    */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	      /* boot args buf size  */
 
-#define CFG_MEMTEST_START	0x08100000	      /* memtest test area   */
-#define CFG_MEMTEST_END		0x08F00000
+#define CONFIG_SYS_MEMTEST_START	0x08100000	      /* memtest test area   */
+#define CONFIG_SYS_MEMTEST_END		0x08F00000
 
-#undef	CFG_CLKS_IN_HZ			     /* use HZ for freq. display     */
+#undef	CONFIG_SYS_CLKS_IN_HZ			     /* use HZ for freq. display     */
 
-#define CFG_HZ			3686400	     /* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x141	     /* core clock - register value  */
+#define CONFIG_SYS_HZ			3686400	     /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_CPUSPEED		0x141	     /* core clock - register value  */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 #define CONFIG_BAUDRATE 115200
 /*
  * Definitions related to passing arguments to kernel.
@@ -98,10 +98,10 @@
 /*
  * Malloc pool need to host env + 128 Kb reserve for other allocations.
  */
-#define CFG_MALLOC_LEN	  (CONFIG_ENV_SIZE + (128<<10) )
+#define CONFIG_SYS_MALLOC_LEN	  (CONFIG_ENV_SIZE + (128<<10) )
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 #define CONFIG_STACKSIZE	(120<<10)      /* stack size */
 
@@ -135,8 +135,8 @@
  * Flash Controller settings
  */
 
-#define CFG_MAX_FLASH_BANKS	1	/* FLASH banks count (not chip count)*/
-#define CFG_MAX_FLASH_SECT	256	/* number of sector in FLASH bank    */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* FLASH banks count (not chip count)*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* number of sector in FLASH bank    */
 
 #ifdef BUS32BIT_VERSION
 #define MX1FS2_FLASH_BUS_WIDTH	4	/* we use 32 bit FLASH memory...     */
@@ -156,12 +156,12 @@
    is not so clear to me. In other words we can provide more informations
    to user, but this expects more complex flash handling we do not provide
    now.*/
-#undef	CFG_FLASH_CFI
+#undef	CONFIG_SYS_FLASH_CFI
 
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)    /* timeout for Erase operation */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)    /* timeout for Write operation */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ)    /* timeout for Erase operation */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ)    /* timeout for Write operation */
 
-#define CFG_FLASH_BASE		MX1FS2_FLASH_BASE
+#define CONFIG_SYS_FLASH_BASE		MX1FS2_FLASH_BASE
 
 /*
  * This is setting for JFFS2 support in u-boot.
@@ -205,8 +205,8 @@
  * env. has no sense to us.
  */
 
-#define CFG_MONITOR_BASE	0x10000000
-#define CFG_MONITOR_LEN		0x20000		/* 128b ( 1 flash sector )   */
+#define CONFIG_SYS_MONITOR_BASE	0x10000000
+#define CONFIG_SYS_MONITOR_LEN		0x20000		/* 128b ( 1 flash sector )   */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		0x10020000	/* absolute address for now  */
 #define CONFIG_ENV_SIZE		0x20000
@@ -214,7 +214,7 @@
 #define	 CONFIG_ENV_OVERWRITE	1		/* env is not writable now   */
 
 /* Setup CS4 and CS5 */
-#define CFG_GIUS_A_VAL		0x0003fffe
+#define CONFIG_SYS_GIUS_A_VAL		0x0003fffe
 
 /*
  * CSxU_VAL:
@@ -226,14 +226,14 @@
  *   |	 OEA   |   OEN	 |   WEA   |   WEN   |	 CSA   |EBC| DSZ  | 0|SP|0|WP| 0 0|PA|CSEN|
  */
 
-#define CFG_CS0U_VAL 0x00008C00
-#define CFG_CS0L_VAL 0x22222601
-#define CFG_CS1U_VAL 0x00008C00
-#define CFG_CS1L_VAL 0x22222301
-#define CFG_CS4U_VAL 0x00008C00
-#define CFG_CS4L_VAL 0x22222301
-#define CFG_CS5U_VAL 0x00008C00
-#define CFG_CS5L_VAL 0x22222301
+#define CONFIG_SYS_CS0U_VAL 0x00008C00
+#define CONFIG_SYS_CS0L_VAL 0x22222601
+#define CONFIG_SYS_CS1U_VAL 0x00008C00
+#define CONFIG_SYS_CS1L_VAL 0x22222301
+#define CONFIG_SYS_CS4U_VAL 0x00008C00
+#define CONFIG_SYS_CS4L_VAL 0x22222301
+#define CONFIG_SYS_CS5U_VAL 0x00008C00
+#define CONFIG_SYS_CS5L_VAL 0x22222301
 
 /* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
    f_ref=16,777MHz
@@ -252,25 +252,25 @@
    31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
       |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------|	    */
 
-#define CFG_MPCTL0_VAL		0x07E723AD
-#define CFG_MPCTL1_VAL		0x00000040
-#define CFG_PCDR_VAL		0x00010005
-#define CFG_GPCR_VAL		0x00000FFB
+#define CONFIG_SYS_MPCTL0_VAL		0x07E723AD
+#define CONFIG_SYS_MPCTL1_VAL		0x00000040
+#define CONFIG_SYS_PCDR_VAL		0x00010005
+#define CONFIG_SYS_GPCR_VAL		0x00000FFB
 
 #define USE_16M_OSZI /* If you have one, you want to use it
 			The internal 32kHz oszillator jitters */
 #ifdef USE_16M_OSZI
 
-#define CFG_SPCTL0_VAL		0x04001401
-#define CFG_SPCTL1_VAL		0x0C000040
-#define CFG_CSCR_VAL		0x07030003
+#define CONFIG_SYS_SPCTL0_VAL		0x04001401
+#define CONFIG_SYS_SPCTL1_VAL		0x0C000040
+#define CONFIG_SYS_CSCR_VAL		0x07030003
 #define CONFIG_SYS_CLK_FREQ	16780000
 #define CONFIG_SYSPLL_CLK_FREQ	16000000
 
 #else
 
-#define CFG_SPCTL0_VAL		0x07E716D1
-#define CFG_CSCR_VAL		0x06000003
+#define CONFIG_SYS_SPCTL0_VAL		0x07E716D1
+#define CONFIG_SYS_CSCR_VAL		0x06000003
 #define CONFIG_SYS_CLK_FREQ	16780000
 #define CONFIG_SYSPLL_CLK_FREQ	16780000
 
@@ -281,9 +281,9 @@
  * one may expect. For instance loadb command do not cares :-)
  * So advice is - do not relay on this...
  */
-#define CFG_LOAD_ADDR		0x08400000
+#define CONFIG_SYS_LOAD_ADDR		0x08400000
 
-#define CFG_FMCR_VAL		0x00000003 /* Reset Default */
+#define CONFIG_SYS_FMCR_VAL		0x00000003 /* Reset Default */
 
 /* Bit[0:3] contain PERCLK1DIV for UART 1
    0x000b00b ->b<- -> 192MHz/12=16MHz
@@ -296,15 +296,15 @@
 #define CONFIG_IMX_SERIAL2
 #elif defined _CONFIG_UART3 | defined _CONFIG_UART4
 #define CONFIG_IMX_SERIAL_NONE
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_CLK		3686400
-#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK		3686400
+#define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_CONS_INDEX	1
 #ifdef _CONFIG_UART3
-#define CFG_NS16550_COM1	0x15000000
+#define CONFIG_SYS_NS16550_COM1	0x15000000
 #elif defined _CONFIG_UART4
-#define CFG_NS16550_COM1	0x16000000
+#define CONFIG_SYS_NS16550_COM1	0x16000000
 #endif
 #endif
 
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index b904d81..1649f1f 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -50,15 +50,15 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
  */
 
 #define CONFIG_MX31_UART	1
-#define CFG_MX31_UART1		1
+#define CONFIG_SYS_MX31_UART1		1
 
 #define CONFIG_HARD_SPI		1
 #define CONFIG_MXC_SPI		1
@@ -74,7 +74,7 @@
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
 
 /***********************************************************
  * Command definition
@@ -128,22 +128,20 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory */
-#define CFG_PROMPT		"=> "
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
 /* Print Buffer Size */
-#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
-#define CFG_MEMTEST_START	0		/* memtest works on */
-#define CFG_MEMTEST_END		0x10000
+#define CONFIG_SYS_MEMTEST_START	0		/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x10000
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 
-#define CFG_LOAD_ADDR		CONFIG_LOADADDR
-
-#define CFG_HZ			CONFIG_MX31_CLK32 /* use 32kHz clock as source */
+#define CONFIG_SYS_HZ			1000
 
 #define CONFIG_CMDLINE_EDITING	1
 
@@ -164,11 +162,11 @@
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_FLASH_BASE		CS0_BASE
-#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	262		/* max number of sectors on one chip */
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE	/* Monitor at beginning of flash */
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256KiB */
+#define CONFIG_SYS_FLASH_BASE		CS0_BASE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	262		/* max number of sectors on one chip */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE	/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256KiB */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SECT_SIZE	(32 * 1024)
@@ -182,16 +180,16 @@
  * The rest of 32MiB is in 128KiB big sectors. U-Boot occupies the low 4 sectors,
  * if we put environment next to it, we will have to occupy 128KiB for it.
  * Putting it at the top of flash we use only 32KiB. */
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
 
 /*-----------------------------------------------------------------------
  * CFI FLASH driver setup
  */
-#define CFG_FLASH_CFI			1 /* Flash memory is CFI compliant */
+#define CONFIG_SYS_FLASH_CFI			1 /* Flash memory is CFI compliant */
 #define CONFIG_FLASH_CFI_DRIVER		1 /* Use drivers/cfi_flash.c */
 #define CONFIG_FLASH_SPANSION_S29WS_N	1 /* A non-standard buffered write algorithm */
-#define CFG_FLASH_USE_BUFFER_WRITE	1 /* Use buffered writes (~10x faster) */
-#define CFG_FLASH_PROTECTION		1 /* Use hardware sector protection */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1 /* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION		1 /* Use hardware sector protection */
 
 /*
  * JFFS2 partitions
diff --git a/include/configs/neo.h b/include/configs/neo.h
new file mode 100644
index 0000000..f275c7b
--- /dev/null
+++ b/include/configs/neo.h
@@ -0,0 +1,231 @@
+/*
+ * (C) Copyright 2007-2008
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+#define CONFIG_405EP		1	/* this is a PPC405 CPU */
+#define CONFIG_4xx		1	/*  member of PPC4xx family */
+#define CONFIG_NEO	        1	/*  on a Neo board */
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		neo
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F 	/* call board_early_init_f */
+
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
+
+/*
+ * Configure PLL
+ */
+#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+#define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"fdt_addr=fc1e0000\0"						\
+	"ramdisk_addr=fc200000\0"					\
+	""
+
+#define CONFIG_PHY_ADDR		4	/* PHY address			*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR	0xc	/* EMAC1 PHY address		*/
+#define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL            3	/* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE command period */
+#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC		66	/* Auto refresh period */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
+#undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		691200
+
+/*
+ * I2C stuff
+ */
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address	*/
+
+/* RTC */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+
+/* Temp sensor/hwmon/dtt */
+#define CONFIG_DTT_LM63		1	/* National LM63	*/
+#define CONFIG_DTT_SENSORS	{ 0 }	/* Sensor addresses	*/
+#define CONFIG_DTT_PWM_LOOKUPTABLE	\
+		{ { 40, 10 }, { 50, 20 }, { 60, 40 } }
+#define CONFIG_DTT_TACH_LIMIT	0xa10
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection	*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif
+
+/*
+ * PPC405 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*				GPIO	Alternate1	*/	\
+{											\
+/* GPIO Core 0 */									\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast    	*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E		*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E		*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O		*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O		*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO5	TS3		*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4		*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7	TS5		*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6		*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk		*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1		*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2		*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3		*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4		*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03   	*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04   	*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05   	*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0	    	*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1	    	*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2	    	*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3	    	*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4	    	*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5	    	*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6	    	*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD   	*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR	*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI	*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR	*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx    	*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx	*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0  	*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1  	*/	\
+}											\
+}
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM        1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (NOR-FLASH) initialization                    */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (NVRAM) initialization                                        */
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFB85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 2 (FPGA) initialization                 */
+#define CONFIG_FPGA_BASE	0x7f100000
+#define CONFIG_SYS_EBC_PB2AP		0x92015480
+#define CONFIG_SYS_EBC_PB2CR		0x7f11a000  /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 3 (Latches) initialization                      */
+#define CONFIG_SYS_EBC_PB3AP		0x92015480
+#define CONFIG_SYS_EBC_PB3CR		0x7f21a000  /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/netstal-common.h b/include/configs/netstal-common.h
new file mode 100644
index 0000000..4d5c1ab
--- /dev/null
+++ b/include/configs/netstal-common.h
@@ -0,0 +1,255 @@
+/*
+ * (C) Copyright 2008
+ * Niklaus Giger, Netstal Maschinen AG, niklaus.giger@netstal.com
+ * adapted from amcc-common.h by
+ * (C) Copyright 2008
+ *  * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Common configuration options for all Netstal boards
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __NETSTAL_COMMON_H
+#define __NETSTAL_COMMON_H
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* Start of U-Boot	*/
+#define CONFIG_SYS_MONITOR_LEN		(320 * 1024)	/* Reserve 320 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc() */
+
+/*
+ * UART
+ */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/* This is the 7bit address of the device, not including P. */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
+
+/*
+ * Ethernet/EMAC/PHY
+ */
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII			/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		1	/* PHY address			*/
+#if defined(CONFIG_440)
+#define CONFIG_NET_MULTI	1
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+#define CONFIG_SYS_RX_ETH_BUFFER	32	/* number of eth rx buffers	*/
+#else
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* number of eth rx buffers	*/
+#endif
+#define CONFIG_HAS_ETH0
+
+/*
+ * Commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#if defined(CONFIG_440)
+#define CONFIG_CMD_CACHE
+#endif
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_BOOT_RETRY_TIME 30
+#define CONFIG_RESET_TO_RETRY
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
+#define CONFIG_SYS_EXTBDINFO			/* To use extended board_into (bd_t) */
+
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support	*/
+#define CONFIG_LOOPW			/* enable loopw command         */
+#define CONFIG_MX_CYCLIC		/* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 	/* include version env variable */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET		/* don't print console @ startup*/
+
+#define CONFIG_SYS_HUSH_PARSER			/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate change	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Internal Definitions
+ */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port*/
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use	*/
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+/*
+ * Booting and default environment
+ */
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run net_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+#define CONFIG_BOOTCOMMAND	"run vx"
+
+/*
+ * Only very few boards have default console not on ttyS0 (like Taishan)
+ */
+#if !defined(CONFIG_USE_TTY)
+#define CONFIG_USE_TTY	ttyS0
+#endif
+
+/*
+ * Only some 4xx PPC's are equipped with an FPU
+ */
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define CONFIG_NETSTAL_DEF_ENV_ROOTPATH	"rootpath=/opt/eldk/ppc_4xxFP\0"
+#else
+#define CONFIG_NETSTAL_DEF_ENV_ROOTPATH	"rootpath=/opt/eldk/ppc_4xx\0"
+#endif
+
+/*
+ * Only some boards need to extend the bootargs by some additional
+ * parameters (like Makalu)
+ */
+#if !defined(CONFIG_ADDMISC)
+#define CONFIG_ADDMISC	"addmisc=setenv bootargs ${bootargs}\0"
+#endif
+
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+/* Setup some values for the default environment variables */
+#define CONFIG_SERVERIP		172.25.1.1
+#define CONFIG_ETHADDR      00:60:13:00:00:00   /* Netstal Machines AG MAC */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#define CONFIG_SYS_TFTP_LOADADDR	0x01000000
+#define CONFIG_SYS_VXWORKS_ADD_PARAMS	"u=dpu pw=netstal8752"
+#define CONFIG_SYS_VXWORKS_SERVERNAME	"c"
+/*
+ * General common environment variables shared by all boards produced by Netstal Maschinen
+ */
+#define CONFIG_NETSTAL_DEF_ENV						\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=" xstr(CONFIG_USE_TTY) ",${baudrate}\0"	\
+	CONFIG_ADDMISC							\
+	"initrd_high=30000000\0"					\
+	"kernel_addr_r=400000\0"					\
+	"fdt_addr_r=800000\0"						\
+	"hostname=" xstr(CONFIG_HOSTNAME) "\0"				\
+	"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0"			\
+	"uload=tftp " xstr(CONFIG_SYS_TFTP_LOADADDR) " "		\
+		xstr(CONFIG_HOSTNAME) "/u-boot.bin\0"			\
+	"vx_rom=" xstr(CONFIG_HOSTNAME) "/"				\
+		xstr(CONFIG_HOSTNAME) "_vx_rom\0"			\
+	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;"\
+		"era " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;"	\
+		"cp.b ${fileaddr} "xstr(CONFIG_SYS_MONITOR_BASE) 	\
+		" ${filesize}; setenv filesize\0"			\
+	"upd=run uload update\0"					\
+	"vx=setenv bootfile ${vx_rom}; tftp " 				\
+		xstr(CONFIG_SYS_TFTP_LOADADDR) "; bootvx\0"		\
+	CONFIG_NETSTAL_DEF_ENV_ROOTPATH
+
+/*
+ * Default environment for arch/powerpc booting
+ * for boards that are ported to arch/powerpc
+ */
+#define CONFIG_NETSTAL_DEF_ENV_POWERPC					\
+	"flash_self=run ramargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"flash_nfs=run nfsargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"tftp ${fdt_addr_r} ${fdt_file}; "			\
+		"run nfsargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0"
+
+#endif /* __NETSTAL_COMMON_H */
diff --git a/include/configs/netstar.h b/include/configs/netstar.h
index 23fd18b..2c90265 100644
--- a/include/configs/netstar.h
+++ b/include/configs/netstar.h
@@ -49,7 +49,7 @@
 #define CONFIG_INITRD_TAG		1
 
 #define CONFIG_SILENT_CONSOLE		1	/* enable silent startup */
-#define CFG_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
 
 /*
  * Physical Memory Map
@@ -62,15 +62,15 @@
 /*
  * FLASH organization
  */
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-#define CFG_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define PHYS_FLASH_1_SIZE	(1 * 1024 * 1024)
-#define CFG_MAX_FLASH_SECT	19
-#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* in ticks */
-#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ)
+#define CONFIG_SYS_MAX_FLASH_SECT	19
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(5*CONFIG_SYS_HZ) /* in ticks */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(5*CONFIG_SYS_HZ)
 
-#define CFG_MONITOR_BASE	PHYS_FLASH_1
-#define CFG_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MONITOR_BASE	PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
 
 /*
  * Environment settings
@@ -86,8 +86,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_MALLOC_LEN		(4 * 1024 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 
 /*
  * The stack size is set up in start.S using the settings below
@@ -103,15 +103,15 @@
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	(-4)
-#define CFG_NS16550_CLK		(CONFIG_XTAL_FREQ)	/* can be 12M/32Khz or 48Mhz  */
-#define CFG_NS16550_COM1	OMAP1510_UART1_BASE	/* uart1 */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		(CONFIG_XTAL_FREQ)	/* can be 12M/32Khz or 48Mhz  */
+#define CONFIG_SYS_NS16550_COM1	OMAP1510_UART1_BASE	/* uart1 */
 
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*#define CONFIG_SKIP_RELOCATE_UBOOT*/
 /*#define CONFIG_SKIP_LOWLEVEL_INIT */
@@ -119,9 +119,8 @@
 /*
  * NAND flash
  */
-#define CFG_MAX_NAND_DEVICE	1
-#define NAND_MAX_CHIPS		1
-#define CFG_NAND_BASE	0x04000000 + (2 << 23)
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE	0x04000000 + (2 << 23)
 #define NAND_ALLOW_ERASE_ALL	1
 
 /*
@@ -141,7 +140,7 @@
 #define CONFIG_CMD_BDI
 #define CONFIG_CMD_BOOTD
 #define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_IMI
 #define CONFIG_CMD_JFFS2
@@ -168,7 +167,7 @@
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow to break in always */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs*/
-#define CFG_AUTOLOAD		"n"		/* No autoload */
+#define CONFIG_SYS_AUTOLOAD		"n"		/* No autoload */
 #define CONFIG_BOOTCOMMAND	"run fboot"
 #define CONFIG_PREBOOT		"run setup"
 #define	CONFIG_EXTRA_ENV_SETTINGS						\
@@ -203,31 +202,31 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"# "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"# "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_AUTO_COMPLETE
 
-#define CFG_MEMTEST_START	PHYS_SDRAM_1
-#define CFG_MEMTEST_END		PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \
-				(CFG_MONITOR_LEN + CFG_MALLOC_LEN + CONFIG_STACKSIZE)
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \
+				(CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE)
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR		PHYS_SDRAM_1 + 0x400000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM_1 + 0x400000	/* default load address */
 
 /* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
  * This time is further subdivided by a local divisor.
  */
-#define CFG_TIMERBASE		OMAP1510_TIMER1_BASE
-#define CFG_PVT			7		/* 2^(pvt+1), divide by 256 */
-#define CFG_HZ			((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+#define CONFIG_SYS_TIMERBASE		OMAP1510_TIMER1_BASE
+#define CONFIG_SYS_PVT			7		/* 2^(pvt+1), divide by 256 */
+#define CONFIG_SYS_HZ			((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
 
 #define OMAP5910_DPLL_DIV	1
 #define OMAP5910_DPLL_MUL	((CONFIG_SYS_CLK_FREQ * \
diff --git a/include/configs/nmdk8815.h b/include/configs/nmdk8815.h
new file mode 100644
index 0000000..543780d
--- /dev/null
+++ b/include/configs/nmdk8815.h
@@ -0,0 +1,168 @@
+/*
+ * (C) Copyright 2005
+ * STMicroelectronics.
+ * Configuration settings for the STn8815 nomadik board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <nomadik.h>
+
+#define CONFIG_ARM926EJS
+#define CONFIG_NOMADIK
+#define CONFIG_NOMADIK_8815
+#define CONFIG_NOMADIK_NDK15
+#define CONFIG_NOMADIK_NHK15
+
+#define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */
+
+/* commands */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+/* There is no NOR flash, so undefine these commands */
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_SYS_NO_FLASH
+/* There is NAND storage */
+#define CONFIG_NAND_NOMADIK
+#define CONFIG_CMD_JFFS2
+
+/* user interface */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"Nomadik> "
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_LOAD_ADDR	0x800000	/* default load address */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/* boot config */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_BOOTDELAY	1
+#define CONFIG_BOOTARGS	"root=/dev/ram0 console=ttyAMA1,115200n8 init=linuxrc"
+#define CONFIG_BOOTCOMMAND	"fsload 0x100000 kernel.uimg;" \
+				" fsload 0x800000 initrd.gz.uimg;" \
+				" bootm 0x100000 0x800000"
+
+/* memory-related information */
+#define CONFIG_NR_DRAM_BANKS	2
+#define PHYS_SDRAM_1		0x00000000	/* DDR-SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x04000000	/* 64 MB */
+#define PHYS_SDRAM_2		0x08000000	/* SDR-SDRAM BANK #2*/
+#define PHYS_SDRAM_2_SIZE	0x04000000	/* 64 MB */
+
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#  define CONFIG_STACKSIZE_IRQ	(4 * 1024)	/* IRQ stack */
+#  define CONFIG_STACKSIZE_FIQ	(4 * 1024)	/* FIQ stack */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END		0x0FFFFFFF
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 256 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* for initial data */
+
+#define CONFIG_MISC_INIT_R	/* call misc_init_r during start up */
+
+/* timing informazion */
+#define CONFIG_SYS_HZ		(2400000 / 256)	/* Timer0: 2.4Mhz + divider */
+#define CONFIG_SYS_TIMERBASE	0x101E2000
+#undef	CONFIG_SYS_CLKS_IN_HZ
+
+/* serial port (PL011) configuration */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CFG_SERIAL0		0x101FD000
+#define CFG_SERIAL1		0x101FB000
+
+#define CONFIG_PL01x_PORTS	{ (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
+#define CONFIG_PL011_CLOCK	48000000
+
+/* Ethernet */
+#define PCI_MEMORY_VADDR	0xe8000000
+#define PCI_IO_VADDR		0xee000000
+#define __io(a)			((void __iomem *)(PCI_IO_VADDR + (a)))
+#define __mem_isa(a)		((a) + PCI_MEMORY_VADDR)
+
+#define CONFIG_DRIVER_SMC91111	/* Using SMC91c111*/
+#define CONFIG_SMC91111_BASE	0x34000300
+#undef  CONFIG_SMC91111_EXT_PHY	/* Internal PHY */
+#define CONFIG_SMC_USE_32_BIT
+#define CONFIG_BOOTFILE		"uImage"
+
+/* flash memory and filesystem information */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MTD_ONENAND_VERIFY_WRITE
+#define CONFIG_SYS_ONENAND_BASE		0x30000000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000 /* SMPS0n */
+
+#ifdef CONFIG_BOOT_ONENAND
+
+#   define CONFIG_CMD_ONENAND /* Temporary: nand and onenand can't coexist */
+   /* Partition				Size	Start
+    * XloaderTOC + X-Loader		256KB	0x00000000
+    * Memory init function		256KB	0x00040000
+    * U-Boot				2MB	0x00080000
+    * Sysimage (kernel + ramdisk)	4MB	0x00280000
+    * JFFS2 Root filesystem		22MB	0x00680000
+    * JFFS2 User Data			227.5MB	0x01C80000
+    */
+#   define CONFIG_JFFS2_PART_SIZE	0x400000
+#   define CONFIG_JFFS2_PART_OFFSET	0x280000
+
+#   define CONFIG_ENV_IS_IN_ONENAND
+#   define CONFIG_ENV_SIZE		(256 * 1024)
+#   define CONFIG_ENV_ADDR		0x30300000
+
+#else /* ! CONFIG_BOOT_ONENAND */
+
+#   define CONFIG_CMD_NAND /* Temporary: nand and onenand can't coexist */
+
+#   define CONFIG_JFFS2_DEV		"nand0"
+#   define CONFIG_JFFS2_NAND		1 /* For the jffs2 support*/
+#   define CONFIG_JFFS2_PART_SIZE	0x00300000
+#   define CONFIG_JFFS2_PART_OFFSET	0x00280000
+
+#   define CONFIG_ENV_IS_IN_NAND
+#   define CONFIG_ENV_SIZE		0x20000 /* 128 Kb - one sector */
+#   define CONFIG_ENV_OFFSET		(0x8000000 - CONFIG_ENV_SIZE)
+
+#endif /* CONFIG_BOOT_ONENAND */
+
+/* this is needed to make hello_world.c and other stuff happy */
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h
index 5b5c6eb..b22c33c 100644
--- a/include/configs/ns9750dev.h
+++ b/include/configs/ns9750dev.h
@@ -49,8 +49,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE       128     /* size in bytes reserved for initial
 					 * data */
 
 /*
@@ -112,24 +112,24 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"NS9750DEV # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"NS9750DEV # "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00780000	/* 7,5 MB in DRAM	*/ /* @TODO */
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00780000	/* 7,5 MB in DRAM	*/ /* @TODO */
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0x00600000	/* default load address	*/ /* @TODO */
+#define	CONFIG_SYS_LOAD_ADDR		0x00600000	/* default load address	*/ /* @TODO */
 
-#define	CFG_HZ			(CPU_CLK_FREQ/64)
+#define	CONFIG_SYS_HZ			(CPU_CLK_FREQ/64)
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define NS9750_ETH_PHY_ADDRESS	(0x0000)
 
@@ -156,7 +156,7 @@
 
 #define PHYS_FLASH_1		0x50000000 /* Flash Bank #1 */
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
@@ -168,21 +168,21 @@
 #define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */
 #endif
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
 #ifdef CONFIG_AMD_LV800
 #define PHYS_FLASH_SIZE		0x00100000 /* 1MB */
-#define CFG_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
+#define CONFIG_SYS_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
 #endif
 #ifdef CONFIG_AMD_LV400
 #define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
-#define CFG_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x070000) /* addr of environment */
+#define CONFIG_SYS_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
 #endif
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 /* @TODO */
 /*#define	CONFIG_ENV_IS_IN_FLASH	1*/
diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
index b515388..18e7cc2 100644
--- a/include/configs/o2dnt.h
+++ b/include/configs/o2dnt.h
@@ -32,7 +32,7 @@
 #define CONFIG_MPC5200
 #define CONFIG_O2DNT		1	/* ... on O2DNT board */
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
@@ -44,7 +44,7 @@
  */
 #define CONFIG_PSC_CONSOLE	5	/* console is on PSC5 */
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*
  * PCI Mapping:
@@ -64,11 +64,11 @@
 #define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
 #define CONFIG_PCI_IO_SIZE	0x01000000
 
-#define CFG_XLB_PIPELINING	1
+#define CONFIG_SYS_XLB_PIPELINING	1
 
 #define CONFIG_NET_MULTI	1
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
 #define CONFIG_NS8382X		1
 
 /* Partitions */
@@ -103,7 +103,7 @@
 
 
 #if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
-#   define CFG_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT		1
 #else
 #   error "TEXT_BASE must be 0xFF000000"
 #endif
@@ -142,17 +142,17 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
-#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
+#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
  *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
+#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
 #endif
 
@@ -160,10 +160,10 @@
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		1	/* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_MODULE		1	/* Select I2C module #1 or #2 */
 
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration:
@@ -174,31 +174,31 @@
  * 0x50 ... 0x57 each 256 bytes in size
  *
  */
-#define CFG_I2C_FRAM
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_I2C_FRAM
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
 /*
  * There is no write delay with FRAM, write operations are performed at bus
  * speed. Thus, no status polling or write delay is needed.
  */
-/*#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70*/
+/*#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70*/
 
 
 /*
  * Flash configuration
  */
-#define CFG_FLASH_BASE		0xFF000000
-#define CFG_FLASH_SIZE		0x01000000
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000)
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
 
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
 
 /*
  * Environment settings
@@ -211,96 +211,97 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
 /*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
  */
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
 #define CONFIG_PHY_ADDR		0x00
 
 /*
  * GPIO configuration
  */
-/*#define CFG_GPS_PORT_CONFIG	0x10002004 */
-#define CFG_GPS_PORT_CONFIG	0x00002006	/* no CAN */
+/*#define CONFIG_SYS_GPS_PORT_CONFIG	0x10002004 */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x00002006	/* no CAN */
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*
  * Various low-level settings
  */
 #if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 #else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
 #endif
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
 
-#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
+#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
 /*
  * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
  */
-#define CFG_BOOTCS_CFG		0x00057801 /* for pci_clk = 66 MHz */
+#define CONFIG_SYS_BOOTCS_CFG		0x00057801 /* for pci_clk = 66 MHz */
 #else
-#define CFG_BOOTCS_CFG		0x00047801 /* for pci_clk = 33 MHz */
+#define CONFIG_SYS_BOOTCS_CFG		0x00047801 /* for pci_clk = 33 MHz */
 #endif
 
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
 
-#define CFG_RESET_ADDRESS	0xff000000
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h
index 6a8665e..2e809b0 100644
--- a/include/configs/ocotea.h
+++ b/include/configs/ocotea.h
@@ -56,33 +56,33 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
-#define CFG_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
-#define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
-#define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
-#define CFG_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/
+#define CONFIG_SYS_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
+#define CONFIG_SYS_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
+#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
+#define CONFIG_SYS_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
+#define CONFIG_SYS_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/
 
-#define CFG_FPGA_BASE	    (CFG_PERIPHERAL_BASE + 0x08300000)
-#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
+#define CONFIG_SYS_FPGA_BASE	    (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
+#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
-#define CFG_TEMP_STACK_OCM  1
-#define CFG_OCM_DATA_ADDR   CFG_ISRAM_BASE
-#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
-#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE   128		    /* num bytes initial data	*/
+#define CONFIG_SYS_TEMP_STACK_OCM  1
+#define CONFIG_SYS_OCM_DATA_ADDR   CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR   CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE   128		    /* num bytes initial data	*/
 
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_POST_WORD_ADDR
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
 
 /*-----------------------------------------------------------------------
  * Environment
@@ -106,35 +106,35 @@
  * The DS1743 code assumes this condition (i.e. -- it assumes the base
  * address for the RTC registers is:
  *
- *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *	CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
  *
  *----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
+#define CONFIG_SYS_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
 #define CONFIG_RTC_DS174x	1		    /* DS1743 RTC		*/
 
 #ifdef CONFIG_ENV_IS_IN_NVRAM
 #define CONFIG_ENV_SIZE		0x1000	    /* Size of Environment vars */
 #define CONFIG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE)
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)
 #endif /* CONFIG_ENV_IS_IN_NVRAM */
 
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS	3		    /* number of banks	    */
-#define CFG_MAX_FLASH_SECT	64		    /* sectors per device   */
+#define CONFIG_SYS_MAX_FLASH_BANKS	3		    /* number of banks	    */
+#define CONFIG_SYS_MAX_FLASH_SECT	64		    /* sectors per device   */
 
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_ADDR0         0x5555
-#define CFG_FLASH_ADDR1         0x2aaa
-#define CFG_FLASH_WORD_SIZE     unsigned char
+#define CONFIG_SYS_FLASH_ADDR0         0x5555
+#define CONFIG_SYS_FLASH_ADDR1         0x2aaa
+#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -152,14 +152,13 @@
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 
 /*
  * Default environment variables
@@ -201,12 +200,12 @@
 #define CONFIG_PCI			/* include pci support		*/
 #define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
-#define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
+#define CONFIG_SYS_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT		/* let board init pci target    */
+#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */
 
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/omap1510inn.h b/include/configs/omap1510inn.h
index d390d85..c7d1b6c 100644
--- a/include/configs/omap1510inn.h
+++ b/include/configs/omap1510inn.h
@@ -49,8 +49,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -67,11 +67,11 @@
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	(-4)
-#define CFG_NS16550_CLK		(CONFIG_SYS_CLK_FREQ)	/* can be 12M/32Khz or 48Mhz  */
-#define CFG_NS16550_COM1	0xfffb0000		/* uart1, bluetooth uart on helen */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		(CONFIG_SYS_CLK_FREQ)	/* can be 12M/32Khz or 48Mhz  */
+#define CONFIG_SYS_NS16550_COM1	0xfffb0000		/* uart1, bluetooth uart on helen */
 
 /*
  * select serial console configuration
@@ -84,7 +84,7 @@
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 
 /*
@@ -109,7 +109,7 @@
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=bootp"
 #define CONFIG_BOOTCOMMAND	"bootp;tftp;bootm"
-#define CFG_AUTOLOAD		"n"		/* No autoload */
+#define CONFIG_SYS_AUTOLOAD		"n"		/* No autoload */
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
@@ -120,26 +120,26 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"OMAP1510 Innovator # " /* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"OMAP1510 Innovator # " /* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x10000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x12000000	/* 32 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x10000000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x12000000	/* 32 MB in DRAM	*/
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR		0x10000000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x10000000	/* default load address */
 
 /* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
  * This time is further subdivided by a local divisor.
  */
-#define CFG_TIMERBASE	0xFFFEC500	    /* use timer 1 */
-#define CFG_PVT		7		    /* 2^(pvt+1), divide by 256 */
-#define CFG_HZ			((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+#define CONFIG_SYS_TIMERBASE	0xFFFEC500	    /* use timer 1 */
+#define CONFIG_SYS_PVT		7		    /* 2^(pvt+1), divide by 256 */
+#define CONFIG_SYS_HZ			((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -161,35 +161,35 @@
 
 #define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
 #define PHYS_FLASH_SIZE		0x01000000 /* 16MB */
 #define PHYS_FLASH_SECT_SIZE	(128*1024)	/* Size of a sector (128kB) */
-#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + PHYS_FLASH_SECT_SIZE)
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE	/* Monitor at beginning of flash */
-#define CFG_MONITOR_LEN		PHYS_FLASH_SECT_SIZE	/* Reserve 1 sector */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE }
+#define CONFIG_SYS_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SECT_SIZE)
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE	/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_LEN		PHYS_FLASH_SECT_SIZE	/* Reserve 1 sector */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE }
 
 /*-----------------------------------------------------------------------
  * FLASH driver setup
  */
-#define CFG_FLASH_CFI		1	/* Flash memory is CFI compliant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash memory is CFI compliant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use drivers/mtd/cfi_flash.c */
-#define CFG_FLASH_USE_BUFFER_WRITE	1	/* Use buffered writes (~10x faster) */
-#define CFG_FLASH_PROTECTION	1	/* Use hardware sector protection */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1	/* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use hardware sector protection */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE	/* Total Size of Environment Sector */
 #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_OFFSET		( CFG_MONITOR_BASE + CFG_MONITOR_LEN )	/* Environment after Monitor */
+#define CONFIG_ENV_OFFSET		( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN )	/* Environment after Monitor */
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/omap1610h2.h b/include/configs/omap1610h2.h
index aeb2fec..e2a6360 100644
--- a/include/configs/omap1610h2.h
+++ b/include/configs/omap1610h2.h
@@ -51,8 +51,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -64,11 +64,11 @@
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	(-4)
-#define CFG_NS16550_CLK	(48000000)		/* can be 12M/32Khz or 48Mhz */
-#define CFG_NS16550_COM1	0xfffb0000	/* uart1, bluetooth uart */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK	(48000000)		/* can be 12M/32Khz or 48Mhz */
+#define CONFIG_SYS_NS16550_COM1	0xfffb0000	/* uart1, bluetooth uart */
 
 /*
  * select serial console configuration
@@ -79,7 +79,7 @@
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE	115200
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 
 /*
@@ -104,7 +104,7 @@
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS	"console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=dhcp"
 #define CONFIG_BOOTCOMMAND      "bootp;tftp;bootm"
-#define CFG_AUTOLOAD            "n"             /* No autoload */
+#define CONFIG_SYS_AUTOLOAD            "n"             /* No autoload */
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
@@ -114,27 +114,27 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP	/* undef to save memory */
-#define CFG_PROMPT	"OMAP1610 H2 # "	/* Monitor Command Prompt */
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"OMAP1610 H2 # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 /* Print Buffer Size */
-#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
-#define CFG_MEMTEST_START	0x10000000	/* memtest works on */
-#define CFG_MEMTEST_END	0x12000000	/* 32 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	0x10000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END	0x12000000	/* 32 MB in DRAM */
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR	0x10000000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR	0x10000000	/* default load address */
 
 /* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
  * DPLL1. This time is further subdivided by a local divisor.
  */
-#define CFG_TIMERBASE	0xFFFEC500	/* use timer 1 */
-#define CFG_PVT	7	/* 2^(pvt+1), divide by 256 */
-#define CFG_HZ	((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+#define CONFIG_SYS_TIMERBASE	0xFFFEC500	/* use timer 1 */
+#define CONFIG_SYS_PVT	7	/* 2^(pvt+1), divide by 256 */
+#define CONFIG_SYS_HZ	((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -162,30 +162,30 @@
 #ifndef __ASSEMBLY__
 extern unsigned long omap_flash_base;		/* set in flash__init */
 #endif
-#define CFG_FLASH_BASE		omap_flash_base
+#define CONFIG_SYS_FLASH_BASE		omap_flash_base
 
 #elif defined(CONFIG_CS0_BOOT)
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1_BM0
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1_BM0
 
 #else
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1_BM1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1_BM1
 
 #endif
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
 #define PHYS_FLASH_SIZE	0x02000000	/* 32MB */
-#define CFG_MAX_FLASH_SECT	(259)	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	(259)	/* max number of sectors on one chip */
 /* addr of environment */
-#define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + 0x020000)
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + 0x020000)
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(20*CONFIG_SYS_HZ)	/* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(20*CONFIG_SYS_HZ)	/* Timeout for Flash Write */
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SIZE	0x20000	/* Total Size of Environment Sector */
diff --git a/include/configs/omap1610inn.h b/include/configs/omap1610inn.h
index 68cf91c..5dcfce1 100644
--- a/include/configs/omap1610inn.h
+++ b/include/configs/omap1610inn.h
@@ -50,8 +50,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -65,11 +65,11 @@
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	(-4)
-#define CFG_NS16550_CLK		(48000000)	/* can be 12M/32Khz or 48Mhz */
-#define CFG_NS16550_COM1	0xfffb0000	/* uart1, bluetooth uart on helen */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		(48000000)	/* can be 12M/32Khz or 48Mhz */
+#define CONFIG_SYS_NS16550_COM1	0xfffb0000	/* uart1, bluetooth uart on helen */
 
 /*
  * select serial console configuration
@@ -80,7 +80,7 @@
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE	115200
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 
 /*
@@ -119,27 +119,27 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP	/* undef to save memory     */
-#define CFG_PROMPT	"OMAP1610 Innovator # "	/* Monitor Command Prompt   */
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_LONGHELP	/* undef to save memory     */
+#define CONFIG_SYS_PROMPT	"OMAP1610 Innovator # "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size  */
 /* Print Buffer Size */
-#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS	16		/* max number of command args   */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START	0x10000000	/* memtest works on */
-#define CFG_MEMTEST_END	0x12000000	/* 32 MB in DRAM    */
+#define CONFIG_SYS_MEMTEST_START	0x10000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END	0x12000000	/* 32 MB in DRAM    */
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR	0x10000000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR	0x10000000	/* default load address */
 
 /* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
  * DPLL1. This time is further subdivided by a local divisor.
  */
-#define CFG_TIMERBASE	0xFFFEC500	/* use timer 1 */
-#define CFG_PVT	7	/* 2^(pvt+1), divide by 256 */
-#define CFG_HZ	((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+#define CONFIG_SYS_TIMERBASE	0xFFFEC500	/* use timer 1 */
+#define CONFIG_SYS_PVT	7	/* 2^(pvt+1), divide by 256 */
+#define CONFIG_SYS_HZ	((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -167,30 +167,30 @@
 #ifndef __ASSEMBLY__
 extern unsigned long omap_flash_base;		/* set in flash__init */
 #endif
-#define CFG_FLASH_BASE		omap_flash_base
+#define CONFIG_SYS_FLASH_BASE		omap_flash_base
 
 #elif defined(CONFIG_CS0_BOOT)
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1_BM0
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1_BM0
 
 #else
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1_BM1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1_BM1
 
 #endif
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
 #define PHYS_FLASH_SIZE	0x02000000	/* 32MB */
-#define CFG_MAX_FLASH_SECT	(259)	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	(259)	/* max number of sectors on one chip */
 /* addr of environment */
-#define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + 0x020000)
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + 0x020000)
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(20*CONFIG_SYS_HZ)	/* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(20*CONFIG_SYS_HZ)	/* Timeout for Flash Write */
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SIZE	0x20000	/* Total Size of Environment Sector */
diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h
index 9018440..92df0b4 100644
--- a/include/configs/omap2420h4.h
+++ b/include/configs/omap2420h4.h
@@ -47,7 +47,7 @@
 /* On H4, NOR and NAND flash are mutual exclusive.
    Define this if you want to use NAND
  */
-/*#define CFG_NAND_BOOT */
+/*#define CONFIG_SYS_NAND_BOOT */
 
 #ifdef CONFIG_APTIX
 #define V_SCLK                   1500000
@@ -71,8 +71,8 @@
  * Size of malloc() pool
  */
 #define CONFIG_ENV_SIZE             SZ_128K     /* Total Size of Environment Sector */
-#define CFG_MALLOC_LEN           (CONFIG_ENV_SIZE + SZ_128K)
-#define CFG_GBL_DATA_SIZE        128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + SZ_128K)
+#define CONFIG_SYS_GBL_DATA_SIZE        128  /* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -94,11 +94,11 @@
 #define V_NS16550_CLK            (48000000)  /* 48MHz (APLL96/2) */
 #endif
 
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE     (-4)
-#define CFG_NS16550_CLK          V_NS16550_CLK   /* 3MHz (1.5MHz*2) */
-#define CFG_NS16550_COM1         OMAP2420_UART1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE     (-4)
+#define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK   /* 3MHz (1.5MHz*2) */
+#define CONFIG_SYS_NS16550_COM1         OMAP2420_UART1
 
 /*
  * select serial console configuration
@@ -109,15 +109,15 @@
    * I2C configuration
    */
 #define CONFIG_HARD_I2C
-#define CFG_I2C_SPEED          100000
-#define CFG_I2C_SLAVE          1
+#define CONFIG_SYS_I2C_SPEED          100000
+#define CONFIG_SYS_I2C_SLAVE          1
 #define CONFIG_DRIVER_OMAP24XX_I2C
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX        1
 #define CONFIG_BAUDRATE          115200
-#define CFG_BAUDRATE_TABLE       {9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_BAUDRATE_TABLE       {9600, 19200, 38400, 57600, 115200}
 
 
 /*
@@ -125,7 +125,7 @@
  */
 #include <config_cmd_default.h>
 
-#ifdef CFG_NAND_BOOT
+#ifdef CONFIG_SYS_NAND_BOOT
     #define CONFIG_CMD_DHCP
     #define CONFIG_CMD_I2C
     #define CONFIG_CMD_NAND
@@ -152,9 +152,9 @@
  *  Board NAND Info.
  */
 #define CONFIG_NAND_LEGACY
-#define CFG_NAND_ADDR 0x04000000  /* physical address to access nand at CS0*/
+#define CONFIG_SYS_NAND_ADDR 0x04000000  /* physical address to access nand at CS0*/
 
-#define CFG_MAX_NAND_DEVICE 1	/* Max number of NAND devices */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1	/* Max number of NAND devices */
 #define SECTORSIZE          512
 
 #define ADDR_COLUMN         1
@@ -163,7 +163,6 @@
 
 #define NAND_ChipID_UNKNOWN 0x00
 #define NAND_MAX_FLOORS     1
-#define NAND_MAX_CHIPS      1
 
 #define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0)
 #define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0)
@@ -173,7 +172,7 @@
 
 #define NAND_NO_RB          1
 
-#define CFG_NAND_WP
+#define CONFIG_SYS_NAND_WP
 #define NAND_WP_OFF()  do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
 #define NAND_WP_ON()  do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
 
@@ -206,20 +205,20 @@
 #define V_PROMPT                 "OMAP242x H4 # "
 #endif
 
-#define CFG_LONGHELP             /* undef to save memory */
-#define CFG_PROMPT               V_PROMPT
-#define CFG_CBSIZE               256  /* Console I/O Buffer Size */
+#define CONFIG_SYS_LONGHELP             /* undef to save memory */
+#define CONFIG_SYS_PROMPT               V_PROMPT
+#define CONFIG_SYS_CBSIZE               256  /* Console I/O Buffer Size */
 /* Print Buffer Size */
-#define CFG_PBSIZE               (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS              16          /* max number of command args */
-#define CFG_BARGSIZE             CFG_CBSIZE  /* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS              16          /* max number of command args */
+#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
 
-#define CFG_MEMTEST_START        (OMAP2420_SDRC_CS0)  /* memtest works on */
-#define CFG_MEMTEST_END          (OMAP2420_SDRC_CS0+SZ_31M)
+#define CONFIG_SYS_MEMTEST_START        (OMAP2420_SDRC_CS0)  /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END          (OMAP2420_SDRC_CS0+SZ_31M)
 
-#undef	CFG_CLKS_IN_HZ           /* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ           /* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR            (OMAP2420_SDRC_CS0) /* default load address */
+#define CONFIG_SYS_LOAD_ADDR            (OMAP2420_SDRC_CS0) /* default load address */
 
 /* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
  * 32KHz clk, or from external sig. This rate is divided by a local divisor.
@@ -230,9 +229,9 @@
 #define V_PVT                    7  /* use with 12MHz/128 */
 #endif
 
-#define CFG_TIMERBASE            OMAP2420_GPT2
-#define CFG_PVT                  V_PVT  /* 2^(pvt+1) */
-#define CFG_HZ	                 ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+#define CONFIG_SYS_TIMERBASE            OMAP2420_GPT2
+#define CONFIG_SYS_PVT                  V_PVT  /* 2^(pvt+1) */
+#define CONFIG_SYS_HZ	                 ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -262,36 +261,36 @@
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_FLASH_BASE           PHYS_FLASH_1
-#define CFG_MAX_FLASH_BANKS      2           /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT       (259)	     /* max number of sectors on one chip */
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE /* Monitor at beginning of flash */
-#define CFG_MONITOR_LEN		SZ_128K      /* Reserve 1 sector */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE_1 }
-
-#ifdef CFG_NAND_BOOT
+#define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_BANKS      2           /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT       (259)	     /* max number of sectors on one chip */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_LEN		SZ_128K      /* Reserve 1 sector */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE_1 }
+
+#ifdef CONFIG_SYS_NAND_BOOT
 #define CONFIG_ENV_IS_IN_NAND	1
 #define CONFIG_ENV_OFFSET	0x80000	/* environment starts here  */
 #else
-#define CONFIG_ENV_ADDR             (CFG_FLASH_BASE + SZ_128K)
+#define CONFIG_ENV_ADDR             (CONFIG_SYS_FLASH_BASE + SZ_128K)
 #define	CONFIG_ENV_IS_IN_FLASH      1
 #define CONFIG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE
-#define CONFIG_ENV_OFFSET	( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */
+#define CONFIG_ENV_OFFSET	( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */
 #endif
 
 /*-----------------------------------------------------------------------
  * CFI FLASH driver setup
  */
-#define CFG_FLASH_CFI		1	/* Flash memory is CFI compliant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash memory is CFI compliant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use drivers/mtd/cfi_flash.c */
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
-#define CFG_FLASH_PROTECTION	1	/* Use hardware sector protection */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use hardware sector protection */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT     (100*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT     (100*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT     (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT     (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
-#define CFG_JFFS2_MEM_NAND
+#define CONFIG_SYS_JFFS2_MEM_NAND
 
 /*
  * JFFS2 partitions
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
new file mode 100644
index 0000000..9057606
--- /dev/null
+++ b/include/configs/omap3_beagle.h
@@ -0,0 +1,325 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the TI OMAP3530 Beagle board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3430		1	/* which is in a 3430 */
+#define CONFIG_OMAP3_BEAGLE	1	/* working with BEAGLE */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ				/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			SZ_128K	/* Total Size Environment */
+						/* Sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_128K)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
+						/* initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3	/* UART3 on Beagle Rev 2 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_MMC			1
+#define CONFIG_OMAP3_MMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#undef CONFIG_CMD_NFS		/* NFS support			*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
+							/* devices */
+#define SECTORSIZE			512
+
+#define NAND_ALLOW_ERASE_ALL
+#define ADDR_COLUMN			1
+#define ADDR_PAGE			2
+#define ADDR_COLUMN_PAGE		3
+
+#define NAND_ChipID_UNKNOWN		0x00
+#define NAND_MAX_FLOORS			1
+#define NAND_MAX_CHIPS			1
+#define NAND_NO_RB			1
+#define CONFIG_SYS_NAND_WP
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
+							/* partition */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY		10
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyS2,115200n8\0" \
+	"videomode=1024x768@60,vxres=1024,vyres=768\0" \
+	"videospec=omapfb:vram:2M,vram:4M\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"video=${videospec},mode:${videomode} " \
+		"root=/dev/mmcblk0p2 rw " \
+		"rootfstype=ext3 rootwait\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"video=${videospec},mode:${videomode} " \
+		"root=/dev/mtdblock4 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"autoscr ${loadaddr}\0" \
+	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmcinit; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE		1
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT			"OMAP3 beagleboard.org # "
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		V_PROMPT
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
+								/* works on */
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
+							/* load address */
+
+/*
+ * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
+ * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ */
+#define V_PVT				7
+
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PVT			V_PVT	/* 2^(pvt+1) */
+#define CONFIG_SYS_HZ			((V_SCLK) / (2 << CONFIG_SYS_PVT))
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	SZ_128K	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	SZ_4K	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	SZ_4K	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	SZ_32M	/* at least 32 meg */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C		1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors on */
+						/* one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN		SZ_256K	/* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE		boot_flash_base
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#define CONFIG_ENV_IS_IN_NAND		1
+#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
+#define CONFIG_ENV_OFFSET		boot_flash_off
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
+					CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#ifndef __ASSEMBLY__
+extern gpmc_csx_t *nand_cs_base;
+extern gpmc_t *gpmc_cfg_base;
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+
+#define WRITE_NAND_COMMAND(d, adr)\
+			writel(d, &nand_cs_base->nand_cmd)
+#define WRITE_NAND_ADDRESS(d, adr)\
+			writel(d, &nand_cs_base->nand_adr)
+#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
+#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
+
+/* Other NAND Access APIs */
+#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
+			while (0)
+#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
+			while (0)
+#define NAND_DISABLE_CE(nand)
+#define NAND_ENABLE_CE(nand)
+#define NAND_WAIT_READY(nand)	udelay(10)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
new file mode 100644
index 0000000..f4498a9
--- /dev/null
+++ b/include/configs/omap3_evm.h
@@ -0,0 +1,345 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Author :
+ *	Manikandan Pillai <mani.pillai@ti.com>
+ * Derived from Beagle Board and 3430 SDP code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * Manikandan Pillai <mani.pillai@ti.com>
+ *
+ * Configuration settings for the TI OMAP3 EVM board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3430		1	/* which is in a 3430 */
+#define CONFIG_OMAP3_EVM	1	/* working with EVM */
+
+#include <asm/arch/cpu.h>	/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ			/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			SZ_128K	/* Total Size Environment */
+						/* Sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_128K)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
+						/* initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
+#define CONFIG_SERIAL1			1	/* UART1 on OMAP3 EVM */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_MMC			1
+#define CONFIG_OMAP3_MMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access */
+							/* nand at CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
+							/* NAND devices */
+#define SECTORSIZE			512
+
+#define NAND_ALLOW_ERASE_ALL
+#define ADDR_COLUMN			1
+#define ADDR_PAGE			2
+#define ADDR_COLUMN_PAGE		3
+
+#define NAND_ChipID_UNKNOWN		0x00
+#define NAND_MAX_FLOORS			1
+#define NAND_MAX_CHIPS			1
+#define NAND_NO_RB			1
+#define CONFIG_SYS_NAND_WP
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY	10
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyS2,115200n8\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=/dev/mmcblk0p2 rw " \
+		"rootfstype=ext3 rootwait\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=/dev/mtdblock4 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"autoscr ${loadaddr}\0" \
+	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"onenand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmcinit; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE	1
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT		"OMAP3_EVM # "
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		V_PROMPT
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command */
+						/* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, */
+					/* in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
+ * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ */
+#define V_PVT				7
+
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PVT			V_PVT	/* 2^(pvt+1) */
+#define CONFIG_SYS_HZ			((V_SCLK) / (2 << CONFIG_SYS_PVT))
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	SZ_128K	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	SZ_4K	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	SZ_4K	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	SZ_32M	/* at least 32 meg */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C		1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
+						/* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN		SZ_256K	/* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE		boot_flash_base
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#define CONFIG_ENV_IS_IN_ONENAND	1
+#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
+#define CONFIG_ENV_OFFSET		boot_flash_off
+#define CONFIG_ENV_ADDR			boot_flash_env_addr
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
+					CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#ifndef __ASSEMBLY__
+extern gpmc_csx_t *nand_cs_base;
+extern gpmc_t *gpmc_cfg_base;
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+
+#define WRITE_NAND_COMMAND(d, adr)\
+			writel(d, &nand_cs_base->nand_cmd)
+#define WRITE_NAND_ADDRESS(d, adr)\
+			writel(d, &nand_cs_base->nand_adr)
+#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
+#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
+
+/* Other NAND Access APIs */
+#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
+			while (0)
+#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
+			while (0)
+#define NAND_DISABLE_CE(nand)
+#define NAND_ENABLE_CE(nand)
+#define NAND_WAIT_READY(nand)	udelay(10)
+
+/*----------------------------------------------------------------------------
+ * SMSC9115 Ethernet from SMSC9118 family
+ *----------------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NET)
+
+#define CONFIG_DRIVER_SMC911X
+#define CONFIG_DRIVER_SMC911X_32_BIT
+#define CONFIG_DRIVER_SMC911X_BASE	0x2C000000
+
+#endif /* (CONFIG_CMD_NET) */
+
+/*
+ * BOOTP fields
+ */
+
+#define CONFIG_BOOTP_SUBNETMASK		0x00000001
+#define CONFIG_BOOTP_GATEWAY		0x00000002
+#define CONFIG_BOOTP_HOSTNAME		0x00000004
+#define CONFIG_BOOTP_BOOTPATH		0x00000010
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
new file mode 100644
index 0000000..dee0417
--- /dev/null
+++ b/include/configs/omap3_overo.h
@@ -0,0 +1,318 @@
+/*
+ * Configuration settings for the Gumstix Overo board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3430		1	/* which is in a 3430 */
+#define CONFIG_OMAP3_OVERO		1	/* working with overo */
+
+#include <asm/arch/cpu.h>	/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ		/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			SZ_128K	/* Total Size Environment */
+						/* Sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_128K)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
+						/* initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
+					115200}
+#define CONFIG_MMC			1
+#define CONFIG_OMAP3_MMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#undef CONFIG_CMD_NFS		/* NFS support			*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand */
+							/* at CS0 */
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND */
+						/* devices */
+#define SECTORSIZE			512
+
+#define NAND_ALLOW_ERASE_ALL
+#define ADDR_COLUMN			1
+#define ADDR_PAGE			2
+#define ADDR_COLUMN_PAGE		3
+
+#define NAND_ChipID_UNKNOWN		0x00
+#define NAND_MAX_FLOORS			1
+#define NAND_MAX_CHIPS			1
+#define NAND_NO_RB			1
+#define CONFIG_SYS_NAND_WP
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
+							/* partition */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY		5
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyS2,115200n8\0" \
+	"videomode=1024x768@60,vxres=1024,vyres=768\0" \
+	"videospec=omapfb:vram:2M,vram:4M\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"video=${videospec},mode:${videomode} " \
+		"root=/dev/mmcblk0p2 rw " \
+		"rootfstype=ext3 rootwait\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"video=${videospec},mode:${videomode} " \
+		"root=/dev/mtdblock4 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"autoscr ${loadaddr}\0" \
+	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmcinit; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE	1
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT		"Overo # "
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		V_PROMPT
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command */
+						/* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, */
+					/* in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
+ * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ */
+#define V_PVT				7
+
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PVT			V_PVT	/* 2^(pvt+1) */
+#define CONFIG_SYS_HZ			((V_SCLK) / (2 << CONFIG_SYS_PVT))
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	SZ_128K	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	SZ_4K	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	SZ_4K	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	SZ_32M	/* at least 32 meg */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C		1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors on */
+						/* one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN		SZ_256K	/* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE		boot_flash_base
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#define CONFIG_ENV_IS_IN_NAND		1
+#define ONENAND_ENV_OFFSET		0x240000 /* environment starts here */
+#define SMNAND_ENV_OFFSET		0x240000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
+#define CONFIG_ENV_OFFSET		boot_flash_off
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
+					CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#ifndef __ASSEMBLY__
+extern gpmc_csx_t *nand_cs_base;
+extern gpmc_t *gpmc_cfg_base;
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+
+#define WRITE_NAND_COMMAND(d, adr)\
+			writel(d, &nand_cs_base->nand_cmd)
+#define WRITE_NAND_ADDRESS(d, adr)\
+			writel(d, &nand_cs_base->nand_adr)
+#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
+#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
+
+/* Other NAND Access APIs */
+#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
+			while (0)
+#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
+			while (0)
+#define NAND_DISABLE_CE(nand)
+#define NAND_ENABLE_CE(nand)
+#define NAND_WAIT_READY(nand)	udelay(10)
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
new file mode 100644
index 0000000..00c0374
--- /dev/null
+++ b/include/configs/omap3_pandora.h
@@ -0,0 +1,320 @@
+/*
+ * (C) Copyright 2008
+ * Grazvydas Ignotas <notasas@gmail.com>
+ *
+ * Configuration settings for the OMAP3 Pandora.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3430		1	/* which is in a 3430 */
+#define CONFIG_OMAP3_PANDORA	1	/* working with pandora */
+
+#include <asm/arch/cpu.h>	/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ		/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			SZ_128K	/* Total Size Environment */
+						/* Sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_128K)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
+						/* initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
+					115200}
+#define CONFIG_MMC			1
+#define CONFIG_OMAP3_MMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#undef CONFIG_CMD_NFS		/* NFS support			*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand */
+							/* at CS0 */
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND */
+						/* devices */
+#define SECTORSIZE			512
+
+#define NAND_ALLOW_ERASE_ALL
+#define ADDR_COLUMN			1
+#define ADDR_PAGE			2
+#define ADDR_COLUMN_PAGE		3
+
+#define NAND_ChipID_UNKNOWN		0x00
+#define NAND_MAX_FLOORS			1
+#define NAND_MAX_CHIPS			1
+#define NAND_NO_RB			1
+#define CONFIG_SYS_NAND_WP
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
+							/* partition */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY		1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyS0,115200n8\0" \
+	"videospec=omapfb:vram:2M,vram:4M\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"video=${videospec} " \
+		"root=/dev/mmcblk0p2 rw " \
+		"rootfstype=ext3 rootwait\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"video=${videospec} " \
+		"root=/dev/mtdblock4 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"autoscr ${loadaddr}\0" \
+	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmcinit; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE	1
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT		"Pandora # "
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		V_PROMPT
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command */
+						/* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, */
+					/* in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
+ * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ */
+#define V_PVT				7
+
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PVT			V_PVT	/* 2^(pvt+1) */
+#define CONFIG_SYS_HZ			((V_SCLK) / (2 << CONFIG_SYS_PVT))
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	SZ_128K	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	SZ_4K	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	SZ_4K	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	SZ_32M	/* at least 32 meg */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C		1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors on */
+						/* one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN		SZ_256K	/* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE		boot_flash_base
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#define CONFIG_ENV_IS_IN_NAND		1
+#define ONENAND_ENV_OFFSET		0x240000 /* environment starts here */
+#define SMNAND_ENV_OFFSET		0x240000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
+#define CONFIG_ENV_OFFSET		boot_flash_off
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
+					CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#ifndef __ASSEMBLY__
+extern gpmc_csx_t *nand_cs_base;
+extern gpmc_t *gpmc_cfg_base;
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+
+#define WRITE_NAND_COMMAND(d, adr)\
+			writel(d, &nand_cs_base->nand_cmd)
+#define WRITE_NAND_ADDRESS(d, adr)\
+			writel(d, &nand_cs_base->nand_adr)
+#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
+#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
+
+/* Other NAND Access APIs */
+#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
+			while (0)
+#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
+			while (0)
+#define NAND_DISABLE_CE(nand)
+#define NAND_ENABLE_CE(nand)
+#define NAND_WAIT_READY(nand)	udelay(10)
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
new file mode 100644
index 0000000..f8ae163
--- /dev/null
+++ b/include/configs/omap3_zoom1.h
@@ -0,0 +1,327 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ * Nishanth Menon <nm@ti.com>
+ *
+ * Configuration settings for the TI OMAP3430 Zoom MDK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3430		1	/* which is in a 3430 */
+#define CONFIG_OMAP3_ZOOM1	1	/* working with Zoom MDK Rev1 */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ				/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			SZ_128K	/* Total Size Environment */
+						/* Sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_128K)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
+						/* initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3	/* UART3 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_MMC			1
+#define CONFIG_OMAP3_MMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#undef CONFIG_CMD_NFS		/* NFS support			*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
+							/* devices */
+#define SECTORSIZE			512
+
+#define NAND_ALLOW_ERASE_ALL
+#define ADDR_COLUMN			1
+#define ADDR_PAGE			2
+#define ADDR_COLUMN_PAGE		3
+
+#define NAND_ChipID_UNKNOWN		0x00
+#define NAND_MAX_FLOORS			1
+#define NAND_MAX_CHIPS			1
+#define NAND_NO_RB			1
+#define CONFIG_SYS_NAND_WP
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
+							/* partition */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY		10
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyS2,115200n8\0" \
+	"videomode=1024x768@60,vxres=1024,vyres=768\0" \
+	"videospec=omapfb:vram:2M,vram:4M\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"video=${videospec},mode:${videomode} " \
+		"root=/dev/mmcblk0p2 rw " \
+		"rootfstype=ext3 rootwait\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"video=${videospec},mode:${videomode} " \
+		"root=/dev/mtdblock4 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"autoscr ${loadaddr}\0" \
+	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmcinit; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE		1
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT			"OMAP3 Zoom1# "
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		V_PROMPT
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
+								/* works on */
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
+							/* load address */
+
+/*
+ * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
+ * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ */
+#define V_PVT				7
+
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PVT			V_PVT	/* 2^(pvt+1) */
+#define CONFIG_SYS_HZ			((V_SCLK) / (2 << CONFIG_SYS_PVT))
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	SZ_128K	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	SZ_4K	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	SZ_4K	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	SZ_32M	/* at least 32 meg */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C		1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors on */
+						/* one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN		SZ_256K	/* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE		boot_flash_base
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#define CONFIG_ENV_IS_IN_NAND		1
+#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
+#define CONFIG_ENV_OFFSET		boot_flash_off
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
+					CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#ifndef __ASSEMBLY__
+extern gpmc_csx_t *nand_cs_base;
+extern gpmc_t *gpmc_cfg_base;
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+
+#define WRITE_NAND_COMMAND(d, adr)\
+			writel(d, &nand_cs_base->nand_cmd)
+#define WRITE_NAND_ADDRESS(d, adr)\
+			writel(d, &nand_cs_base->nand_adr)
+#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
+#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
+
+/* Other NAND Access APIs */
+#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
+			while (0)
+#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
+			while (0)
+#define NAND_DISABLE_CE(nand)
+#define NAND_ENABLE_CE(nand)
+#define NAND_WAIT_READY(nand)	udelay(10)
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h
index dd3f7de..63cd9c6 100644
--- a/include/configs/omap5912osk.h
+++ b/include/configs/omap5912osk.h
@@ -53,8 +53,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -68,11 +68,11 @@
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	(-4)
-#define CFG_NS16550_CLK	(48000000)	/* can be 12M/32Khz or 48Mhz */
-#define CFG_NS16550_COM1	0xfffb0000	/* uart1, bluetooth uart
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK	(48000000)	/* can be 12M/32Khz or 48Mhz */
+#define CONFIG_SYS_NS16550_COM1	0xfffb0000	/* uart1, bluetooth uart
 						on helen */
 
 /*
@@ -84,7 +84,7 @@
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE	115200
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 
 /*
@@ -123,27 +123,27 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP	/* undef to save memory     */
-#define CFG_PROMPT	"OMAP5912 OSK # "	/* Monitor Command Prompt   */
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_LONGHELP	/* undef to save memory     */
+#define CONFIG_SYS_PROMPT	"OMAP5912 OSK # "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size  */
 /* Print Buffer Size */
-#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS	16		/* max number of command args   */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START	0x10000000	/* memtest works on */
-#define CFG_MEMTEST_END	0x12000000	/* 32 MB in DRAM    */
+#define CONFIG_SYS_MEMTEST_START	0x10000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END	0x12000000	/* 32 MB in DRAM    */
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR	0x10000000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR	0x10000000	/* default load address */
 
 /* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
  * DPLL1. This time is further subdivided by a local divisor.
  */
-#define CFG_TIMERBASE	0xFFFEC500	/* use timer 1 */
-#define CFG_PVT	7	/* 2^(pvt+1), divide by 256 */
-#define CFG_HZ	((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+#define CONFIG_SYS_TIMERBASE	0xFFFEC500	/* use timer 1 */
+#define CONFIG_SYS_PVT	7	/* 2^(pvt+1), divide by 256 */
+#define CONFIG_SYS_HZ	((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -166,37 +166,37 @@
 #define PHYS_FLASH_1		0x00000000	/* Flash Bank #1 */
 #define PHYS_FLASH_2		0x01000000	/* Flash Bank #2 */
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
-#define CFG_MONITOR_BASE       CFG_FLASH_BASE  /* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE       CONFIG_SYS_FLASH_BASE  /* Monitor at beginning of flash */
 
 /*-----------------------------------------------------------------------
  * FLASH driver setup
  */
-#define CFG_FLASH_CFI          1       /* Flash memory is CFI compliant */
+#define CONFIG_SYS_FLASH_CFI          1       /* Flash memory is CFI compliant */
 #define CONFIG_FLASH_CFI_DRIVER   1       /* Use drivers/mtd/cfi_flash.c */
 
-#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
 
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
 #define PHYS_FLASH_SIZE	0x02000000	/* 32MB */
-#define CFG_MAX_FLASH_SECT	(259)	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	(259)	/* max number of sectors on one chip */
 
-#define CFG_FLASH_USE_BUFFER_WRITE     1       /* Use buffered writes (~10x faster) */
-#define CFG_FLASH_PROTECTION   1       /* Use hardware sector protection */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE     1       /* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION   1       /* Use hardware sector protection */
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(20*CONFIG_SYS_HZ)	/* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(20*CONFIG_SYS_HZ)	/* Timeout for Flash Write */
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
 /* addr of environment */
-#define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + 0x020000)
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + 0x020000)
 
 #define CONFIG_ENV_SIZE	0x20000	/* Total Size of Environment Sector */
 #define CONFIG_ENV_OFFSET	0x20000	/* environment starts here  */
diff --git a/include/configs/omap730p2.h b/include/configs/omap730p2.h
index b1c4a30..166d592 100644
--- a/include/configs/omap730p2.h
+++ b/include/configs/omap730p2.h
@@ -58,8 +58,8 @@
  * Size of malloc() pool
  */
 
-#define CFG_MALLOC_LEN		   (CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	   128	     /* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		   (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	   128	     /* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -73,11 +73,11 @@
  * NS16550 Configuration
  */
 
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	   (1)
-#define CFG_NS16550_CLK		   (48000000)	  /* can be 12M/32Khz or 48Mhz */
-#define CFG_NS16550_COM1	   0xfffb0000	  /* uart1, bluetooth uart
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	   (1)
+#define CONFIG_SYS_NS16550_CLK		   (48000000)	  /* can be 12M/32Khz or 48Mhz */
+#define CONFIG_SYS_NS16550_COM1	   0xfffb0000	  /* uart1, bluetooth uart
 						   * on perseus */
 
 /*
@@ -88,7 +88,7 @@
 
 #define CONFIG_CONS_INDEX	   1
 #define CONFIG_BAUDRATE		   115200
-#define CFG_BAUDRATE_TABLE	   { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	   { 9600, 19200, 38400, 57600, 115200 }
 
 
 /*
@@ -131,29 +131,29 @@
  * Miscellaneous configurable options
  */
 
-#define CFG_LONGHELP				       /* undef to save memory	   */
-#define CFG_PROMPT		   "OMAP730 P2 # "     /* Monitor Command Prompt   */
-#define CFG_CBSIZE		   256		       /* Console I/O Buffer Size  */
+#define CONFIG_SYS_LONGHELP				       /* undef to save memory	   */
+#define CONFIG_SYS_PROMPT		   "OMAP730 P2 # "     /* Monitor Command Prompt   */
+#define CONFIG_SYS_CBSIZE		   256		       /* Console I/O Buffer Size  */
 /* Print Buffer Size */
-#define CFG_PBSIZE		   (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS		   16		       /* max number of command args   */
-#define CFG_BARGSIZE		   CFG_CBSIZE	       /* Boot Argument Buffer Size    */
+#define CONFIG_SYS_PBSIZE		   (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		   16		       /* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		   CONFIG_SYS_CBSIZE	       /* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START	   0x10000000	       /* memtest works on */
-#define CFG_MEMTEST_END		   0x12000000	       /* 32 MB in DRAM	   */
+#define CONFIG_SYS_MEMTEST_START	   0x10000000	       /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		   0x12000000	       /* 32 MB in DRAM	   */
 
-#undef CFG_CLKS_IN_HZ		     /* everything, incl board info, in Hz */
+#undef CONFIG_SYS_CLKS_IN_HZ		     /* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR		   0x10000000	       /* default load address */
+#define CONFIG_SYS_LOAD_ADDR		   0x10000000	       /* default load address */
 
 /* The OMAP730 has 3 general purpose MPU timers, they can be driven by
  * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
  * local divisor.
  */
 
-#define CFG_TIMERBASE		   0xFFFEC500	       /* use timer 1 */
-#define CFG_PVT			   7		       /* 2^(pvt+1), divide by 256 */
-#define CFG_HZ			   ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+#define CONFIG_SYS_TIMERBASE		   0xFFFEC500	       /* use timer 1 */
+#define CONFIG_SYS_PVT			   7		       /* 2^(pvt+1), divide by 256 */
+#define CONFIG_SYS_HZ			   ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -183,21 +183,21 @@
 #error Unknown Boot Chip-Select number
 #endif
 
-#define CFG_FLASH_BASE		   PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		   PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
 
-#define CFG_MAX_FLASH_BANKS	   1		  /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS	   1		  /* max number of memory banks */
 #define PHYS_FLASH_SIZE		   0x02000000	  /* 32MB */
-#define CFG_MAX_FLASH_SECT	   (259)	  /* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	   (259)	  /* max number of sectors on one chip */
 /* addr of environment */
-#define CONFIG_ENV_ADDR		   (CFG_FLASH_BASE + 0x020000)
+#define CONFIG_ENV_ADDR		   (CONFIG_SYS_FLASH_BASE + 0x020000)
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	    (20*CFG_HZ)	  /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	    (20*CFG_HZ)	  /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	    (20*CONFIG_SYS_HZ)	  /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	    (20*CONFIG_SYS_HZ)	  /* Timeout for Flash Write */
 
 #define CONFIG_ENV_IS_IN_FLASH	   1
 #define CONFIG_ENV_SIZE		   0x20000	  /* Total Size of Environment Sector */
diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h
index 2df1d9d..5e4d30b 100644
--- a/include/configs/p3mx.h
+++ b/include/configs/p3mx.h
@@ -43,21 +43,21 @@
 #if defined (CONFIG_P3M750)
 #define CONFIG_750FX			/* 750GL/GX/FX			*/
 #define CONFIG_HIGH_BATS		/* High BATs supported		*/
-#define CFG_BOARD_NAME		"P3M750"
-#define CFG_BUS_HZ		100000000
-#define CFG_BUS_CLK		CFG_BUS_HZ
-#define CFG_TCLK		100000000
+#define CONFIG_SYS_BOARD_NAME		"P3M750"
+#define CONFIG_SYS_BUS_HZ		100000000
+#define CONFIG_SYS_BUS_CLK		CONFIG_SYS_BUS_HZ
+#define CONFIG_SYS_TCLK		100000000
 #elif defined (CONFIG_P3M7448)
 #define CONFIG_74xx
-#define CFG_BOARD_NAME		"P3M7448"
-#define CFG_BUS_HZ		133333333
-#define CFG_BUS_CLK		CFG_BUS_HZ
-#define CFG_TCLK		133333333
+#define CONFIG_SYS_BOARD_NAME		"P3M7448"
+#define CONFIG_SYS_BUS_HZ		133333333
+#define CONFIG_SYS_BUS_CLK		CONFIG_SYS_BUS_HZ
+#define CONFIG_SYS_TCLK		133333333
 #endif
-#define CFG_GT_DUAL_CPU			/* also for JTAG even with one cpu */
+#define CONFIG_SYS_GT_DUAL_CPU			/* also for JTAG even with one cpu */
 
 /* which initialization functions to call for this board */
-#define CFG_BOARD_ASM_INIT	1
+#define CONFIG_SYS_BOARD_ASM_INIT	1
 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
 #define CONFIG_BOARD_EARLY_INIT_R 1     /* Call board_early_init_f	*/
 #define CONFIG_MISC_INIT_R      1	/* Call misc_init_r()		*/
@@ -66,42 +66,42 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
 #ifdef CONFIG_P3M750
-#define CFG_SDRAM1_BASE		0x10000000	/* each 256 MByte	*/
+#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* each 256 MByte	*/
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
 #if defined (CONFIG_P3M750)
-#define CFG_FLASH_BASE		0xff800000	/* start of flash banks	*/
-#define CFG_BOOT_SIZE		_8M		/* boot flash		*/
+#define CONFIG_SYS_FLASH_BASE		0xff800000	/* start of flash banks	*/
+#define CONFIG_SYS_BOOT_SIZE		_8M		/* boot flash		*/
 #elif defined (CONFIG_P3M7448)
-#define CFG_FLASH_BASE		0xff000000	/* start of flash banks	*/
-#define CFG_BOOT_SIZE		_16M		/* boot flash		*/
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of flash banks	*/
+#define CONFIG_SYS_BOOT_SIZE		_16M		/* boot flash		*/
 #endif
-#define CFG_BOOT_SPACE		CFG_FLASH_BASE	/* BOOT_CS0 flash 0    */
-#define CFG_MONITOR_BASE	0xfff00000
-#define CFG_RESET_ADDRESS	0xfff00100
-#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
-#define CFG_MISC_REGION_BASE	0xf0000000
+#define CONFIG_SYS_BOOT_SPACE		CONFIG_SYS_FLASH_BASE	/* BOOT_CS0 flash 0    */
+#define CONFIG_SYS_MONITOR_BASE	0xfff00000
+#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
 
-#define CFG_DFL_GT_REGS		0xf1000000	/* boot time GT_REGS */
-#define CFG_GT_REGS		0xf1000000	/* GT Registers are mapped here */
-#define CFG_INT_SRAM_BASE	0x42000000	/* GT offers 256k internal SRAM */
+#define CONFIG_SYS_DFL_GT_REGS		0xf1000000	/* boot time GT_REGS */
+#define CONFIG_SYS_GT_REGS		0xf1000000	/* GT Registers are mapped here */
+#define CONFIG_SYS_INT_SRAM_BASE	0x42000000	/* GT offers 256k internal SRAM */
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
  /*
- * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
+ * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
  * To an unused memory region. The stack will remain in cache until RAM
  * is initialized
 */
-#undef	CFG_INIT_RAM_LOCK
-#define CFG_INIT_RAM_ADDR	0x42000000
-#define CFG_INIT_RAM_END	0x1000
-#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#undef	CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0x42000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 
 /*-----------------------------------------------------------------------
@@ -110,15 +110,15 @@
 #define CONFIG_MPSC			/* MV64460 Serial		*/
 #define CONFIG_MPSC_PORT	0
 #define CONFIG_BAUDRATE		115200	/* console baudrate		*/
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 /*-----------------------------------------------------------------------
  * Ethernet
  *----------------------------------------------------------------------*/
 /* Change the default ethernet port, use this define (options: 0, 1, 2) */
-#define CFG_ETH_PORT		ETH_0
+#define CONFIG_SYS_ETH_PORT		ETH_0
 #define CONFIG_NET_MULTI
 #define MV_ETH_DEVS		2
 #define CONFIG_PHY_RESET        1	/* reset phy upon startup         */
@@ -127,15 +127,15 @@
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI			/* The flash is CFI compatible		*/
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible		*/
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver		*/
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection	*/
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
 #if defined (CONFIG_P3M750)
@@ -144,7 +144,7 @@
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* two sectors (2 devices parallel	*/
 #endif
 #define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 
 /*-----------------------------------------------------------------------
  * DDR SDRAM
@@ -154,12 +154,12 @@
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CFG_I2C_SPEED		100000		/* I2C speed default	*/
+#define CONFIG_SYS_I2C_SPEED		100000		/* I2C speed default	*/
 
 /* I2C RTC */
 #define CONFIG_RTC_M41T11	1
-#define CFG_I2C_RTC_ADDR	0x68
-#define CFG_M41T11_BASE_YEAR	1900	/* play along with linux	*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	1900	/* play along with linux	*/
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -176,27 +176,27 @@
 #endif /* CONFIG_PCI */
 
 /* PCI MEMORY MAP section */
-#define CFG_PCI0_MEM_BASE	0x80000000
-#define CFG_PCI0_MEM_SIZE	_128M
-#define CFG_PCI1_MEM_BASE	0x88000000
-#define CFG_PCI1_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
 
-#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
-#define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
+#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
+#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
 
 /* PCI I/O MAP section */
-#define CFG_PCI0_IO_BASE	0xfa000000
-#define CFG_PCI0_IO_SIZE	_16M
-#define CFG_PCI1_IO_BASE	0xfb000000
-#define CFG_PCI1_IO_SIZE	_16M
+#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
+#define CONFIG_SYS_PCI0_IO_SIZE	_16M
+#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
+#define CONFIG_SYS_PCI1_IO_SIZE	_16M
 
-#define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
-#define CFG_PCI0_IO_SPACE_PCI	0x00000000
-#define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
-#define CFG_PCI1_IO_SPACE_PCI	0x00000000
+#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
+#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000
+#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
+#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000
 
-#define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE)
-#define CFG_PCI_IDSEL 0x30
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
+#define CONFIG_SYS_PCI_IDSEL 0x30
 
 #undef	CONFIG_BOOTARGS
 #define	CONFIG_EXTRA_ENV_SETTINGS_COMMON				\
@@ -285,26 +285,26 @@
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  *----------------------------------------------------------------------*/
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on	        */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x08000000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x08000000	/* default load address */
 
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
@@ -317,9 +317,9 @@
  *----------------------------------------------------------------------*/
 /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */
 #if defined (CONFIG_P3M750)
-#define CFG_BOOT_PAR		0x8FDFF87F	/* 16 bit flash, disable burst*/
+#define CONFIG_SYS_BOOT_PAR		0x8FDFF87F	/* 16 bit flash, disable burst*/
 #elif defined (CONFIG_P3M7448)
-#define CFG_BOOT_PAR		0x8FEFFFFF	/* 32 bit flash, burst enabled */
+#define CONFIG_SYS_BOOT_PAR		0x8FEFFFFF	/* 32 bit flash, burst enabled */
 #endif
 
 /*
@@ -356,11 +356,11 @@
  * MPP[30]	Module reset		GPIO	OUT	Board reset
  * MPP[31]	PCI EReady		GPIO	IN	Connected to P12
  */
-#define CFG_MPP_CONTROL_0	0x00303022
-#define CFG_MPP_CONTROL_1	0x00000000
-#define CFG_MPP_CONTROL_2	0x00004000
-#define CFG_MPP_CONTROL_3	0x00000004
-#define CFG_GPP_LEVEL_CONTROL	0x280730D0
+#define CONFIG_SYS_MPP_CONTROL_0	0x00303022
+#define CONFIG_SYS_MPP_CONTROL_1	0x00000000
+#define CONFIG_SYS_MPP_CONTROL_2	0x00004000
+#define CONFIG_SYS_MPP_CONTROL_3	0x00000004
+#define CONFIG_SYS_GPP_LEVEL_CONTROL	0x280730D0
 
 /*----------------------------------------------------------------------
  * Initial BAT mappings
@@ -371,75 +371,75 @@
  * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
  */
 /* SDRAM */
-#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
-#define CFG_DBAT0U CFG_IBAT0U
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
 
 /* init ram */
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 
 /* PCI0, PCI1 in one BAT */
-#define CFG_IBAT2L BATL_NO_ACCESS
-#define CFG_IBAT2U CFG_DBAT2U
-#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
+#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* GT regs, bootrom, all the devices, PCI I/O */
-#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 
-#define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT4U CFG_IBAT4U
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
 
 /* set rest out of range for Linux !!!!!!!!!!! */
 
 /* IBAT5 and DBAT5 */
-#define CFG_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT5U CFG_IBAT5U
+#define CONFIG_SYS_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
 
 /* IBAT6 and DBAT6 */
-#define CFG_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT6U CFG_IBAT6U
+#define CONFIG_SYS_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
 
 /* IBAT7 and DBAT7 */
-#define CFG_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT7U CFG_IBAT7U
+#define CONFIG_SYS_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
-#define CFG_VXWORKS_MAC_PTR	0x42010000 /* use some memory in SRAM that's not used!!! */
+#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_VXWORKS_MAC_PTR	0x42010000 /* use some memory in SRAM that's not used!!! */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
  * L2CR setup -- make sure this is right for your board!
  * look in include/mpc74xx.h for the defines used here
  */
-#define CFG_L2
+#define CONFIG_SYS_L2
 
 #if defined (CONFIG_750CX) || defined (CONFIG_750FX)
 #define L2_INIT 0
diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h
index 5cef3ea..729ca6a 100644
--- a/include/configs/p3p440.h
+++ b/include/configs/p3p440.h
@@ -45,45 +45,45 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
-#define CFG_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
-#define CFG_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
-#define CFG_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
-#define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
-#define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
-#define CFG_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/
+#define CONFIG_SYS_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
+#define CONFIG_SYS_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
+#define CONFIG_SYS_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
+#define CONFIG_SYS_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
+#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
+#define CONFIG_SYS_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
+#define CONFIG_SYS_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/
 
-#define CFG_USB_BASE	    (CFG_PERIPHERAL_BASE + 0x00000000)
+#define CONFIG_SYS_USB_BASE	    (CONFIG_SYS_PERIPHERAL_BASE + 0x00000000)
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR	CFG_ISRAM_BASE  /* Initial RAM address	*/
-#define CFG_INIT_RAM_END	0x2000	    /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE	128	    /* num bytes initial data	*/
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_END	0x2000	    /* End of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128	    /* num bytes initial data	*/
 
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc*/
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc*/
 
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
 #define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0*/
 #define CONFIG_SDRAM_ECC		/* enable ECC support		*/
-#define CFG_SDRAM_TABLE	{ \
+#define CONFIG_SYS_SDRAM_TABLE	{ \
 		{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
 		{(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)	*/
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#undef CFG_EXT_SERIAL_CLOCK
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK
 #define CONFIG_BAUDRATE		115200
 
-#define CFG_BAUDRATE_TABLE						\
+#define CONFIG_SYS_BAUDRATE_TABLE						\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,		\
 			57600, 115200, 230400, 460800, 921600 }
 
@@ -92,9 +92,9 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs	*/
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs	*/
 
 /*-----------------------------------------------------------------------
  * I2C RTC
@@ -104,15 +104,14 @@
 /*-----------------------------------------------------------------------
  * I2C EEPROM (PCF8594C) for environment
  *----------------------------------------------------------------------*/
-#define CFG_I2C_EEPROM_ADDR	0x54	/* EEPROM PCF8594C		*/
-#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x54	/* EEPROM PCF8594C		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 3	/* The Philips PCF8594C has	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3	/* The Philips PCF8594C has	*/
 					/* 8 byte page write mode using */
 					/* last 3 bits of the address	*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	40   /* and takes up to 40 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	40   /* and takes up to 40 msec */
 
 /*-----------------------------------------------------------------------
  * Default configuration (environment varibles...)
@@ -157,14 +156,15 @@
 #define CONFIG_BAUDRATE		115200
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0x1c	/* PHY address			*/
 #define CONFIG_HAS_ETH1
 #define CONFIG_PHY1_ADDR	0x1d	/* EMAC1 PHY address		*/
 #define CONFIG_NET_MULTI	1
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+#define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
 
 #define CONFIG_NETCONSOLE		/* include NetConsole support	*/
 
@@ -205,24 +205,24 @@
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  *----------------------------------------------------------------------*/
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
 #define CONFIG_LOOPW            1       /* enable loopw command         */
@@ -236,69 +236,69 @@
 #define CONFIG_PCI			            /* include pci support	        */
 #define CONFIG_PCI_PNP			        /* do pci plug-and-play         */
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
-#define CFG_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CFG_PCI_MEMBASE */
+#define CONFIG_SYS_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT	            /* let board init pci target    */
+#define CONFIG_SYS_PCI_TARGET_INIT	            /* let board init pci target    */
 
 #define CONFIG_DISABLE_PISE_TEST	/* disable PISE test (PCIX only)*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
-#define CFG_FLASH0		0xFF800000
-#define CFG_FLASH1		0xFF000000
-#define CFG_FLASH2		0xFE800000
-#define CFG_FLASH3		0xFE000000
-#define CFG_USB			0xF0000000
+#define CONFIG_SYS_FLASH0		0xFF800000
+#define CONFIG_SYS_FLASH1		0xFF000000
+#define CONFIG_SYS_FLASH2		0xFE800000
+#define CONFIG_SYS_FLASH3		0xFE000000
+#define CONFIG_SYS_USB			0xF0000000
 
 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x03050200
-#define CFG_EBC_PB0CR		(CFG_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x03050200
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB1AP		0x03050200
-#define CFG_EBC_PB1CR		(CFG_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB1AP		0x03050200
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB2AP		0x03050200
-#define CFG_EBC_PB2CR		(CFG_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB2AP		0x03050200
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB3AP		0x03050200
-#define CFG_EBC_PB3CR		(CFG_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3AP		0x03050200
+#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 7 (USB controller) initialization				*/
-#define CFG_EBC_PB7AP		0x02015000
-#define CFG_EBC_PB7CR		(CFG_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB7AP		0x02015000
+#define CONFIG_SYS_EBC_PB7CR		(CONFIG_SYS_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/
 
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
 #define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
 
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH3, CFG_FLASH2, CFG_FLASH1, CFG_FLASH0 }
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH3, CONFIG_SYS_FLASH2, CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
 
-#define CFG_MAX_FLASH_BANKS	4	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	4	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection	*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
 
 #define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
 
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -310,7 +310,7 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Internal Definitions
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index 480a59f..5ad745e 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -53,7 +53,7 @@
 #define CONFIG_BAUDRATE		115200
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
 #undef	CONFIG_BOOTARGS
@@ -71,50 +71,50 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory      */
-#define	CFG_PROMPT		"Pb1x00 # "	/* Monitor Command Prompt    */
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory      */
+#define	CONFIG_SYS_PROMPT		"Pb1x00 # "	/* Monitor Command Prompt    */
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size   */
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args*/
 
-#define CFG_MALLOC_LEN		128*1024
+#define CONFIG_SYS_MALLOC_LEN		128*1024
 
-#define CFG_BOOTPARAMS_LEN	128*1024
+#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024
 
-#define CFG_MIPS_TIMER_FREQ	396000000
+#define CONFIG_SYS_MIPS_TIMER_FREQ	396000000
 
-#define CFG_HZ			1000
+#define CONFIG_SYS_HZ			1000
 
-#define CFG_SDRAM_BASE		0x80000000     /* Cached addr */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000     /* Cached addr */
 
-#define	CFG_LOAD_ADDR		0x81000000     /* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x81000000     /* default load address	*/
 
-#define CFG_MEMTEST_START	0x80100000
-#undef CFG_MEMTEST_START
-#define CFG_MEMTEST_START       0x80200000
-#define CFG_MEMTEST_END		0x83800000
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#undef CONFIG_SYS_MEMTEST_START
+#define CONFIG_SYS_MEMTEST_START       0x80200000
+#define CONFIG_SYS_MEMTEST_END		0x83800000
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
 
 #define PHYS_FLASH_1		0xbec00000 /* Flash Bank #1 */
 #define PHYS_FLASH_2		0xbfc00000 /* Flash Bank #2 */
 
 /* The following #defines are needed to get flash environment right */
-#define	CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MONITOR_LEN		(192 << 10)
+#define	CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)
 
-#define CFG_INIT_SP_OFFSET	0x4000000
+#define CONFIG_SYS_INIT_SP_OFFSET	0x4000000
 
 /* We boot from this flash, selected with dip switch */
-#define CFG_FLASH_BASE		PHYS_FLASH_2
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_2
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define	CONFIG_ENV_IS_NOWHERE	1
 
@@ -140,8 +140,8 @@
 
 /*---ATA PCMCIA ------------------------------------*/
 #if 0
-#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
-#define CFG_PCMCIA_MEM_ADDR 0x20000000
+#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
 #define CONFIG_PCMCIA_SLOT_A
 
 #define CONFIG_ATAPI 1
@@ -151,32 +151,32 @@
 #define CONFIG_IDE_PCMCIA 1
 
 /* We only support one slot for now */
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR       CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET     8
+#define CONFIG_SYS_ATA_DATA_OFFSET     8
 
 /* Offset for normal register accesses  */
-#define CFG_ATA_REG_OFFSET      0
+#define CONFIG_SYS_ATA_REG_OFFSET      0
 
 /* Offset for alternate registers       */
-#define CFG_ATA_ALT_OFFSET      0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET      0x0100
 
 #endif
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		16384
-#define CFG_ICACHE_SIZE		16384
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_DCACHE_SIZE		16384
+#define CONFIG_SYS_ICACHE_SIZE		16384
+#define CONFIG_SYS_CACHELINE_SIZE	32
 
 
 /*
@@ -198,7 +198,7 @@
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
 
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
 #undef CONFIG_CMD_FAT
 #undef CONFIG_CMD_FLASH
 #undef CONFIG_CMD_FPGA
diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h
index 62f13f2..000ae5c 100644
--- a/include/configs/pcs440ep.h
+++ b/include/configs/pcs440ep.h
@@ -49,44 +49,44 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
-#define CFG_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
-#define CFG_FLASH_BASE	        0xfff00000	    /* start of FLASH	*/
-#define CFG_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
-#define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
-#define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	(-CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
+#define CONFIG_SYS_FLASH_BASE	        0xfff00000	    /* start of FLASH	*/
+#define CONFIG_SYS_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
+#define CONFIG_SYS_PCI_MEMBASE1        CONFIG_SYS_PCI_MEMBASE  + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2        CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3        CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
 
 /*Don't change either of these*/
-#define CFG_PERIPHERAL_BASE     0xef600000	    /* internal peripherals*/
-#define CFG_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
+#define CONFIG_SYS_PERIPHERAL_BASE     0xef600000	    /* internal peripherals*/
+#define CONFIG_SYS_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
 /*Don't change either of these*/
 
-#define CFG_USB_DEVICE          0x50000000
-#define CFG_BOOT_BASE_ADDR      0xf0000000
+#define CONFIG_SYS_USB_DEVICE          0x50000000
+#define CONFIG_SYS_BOOT_BASE_ADDR      0xf0000000
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
-#define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
-#define CFG_INIT_RAM_END	(4 << 10)
-#define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
+#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000		/* DCache       */
+#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_SIZE	256			/* num bytes initial data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#undef CFG_EXT_SERIAL_CLOCK		/* no external clk used		*/
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK		/* no external clk used		*/
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SERIAL_MULTI     1
 /*define this if you want console on UART1*/
 #undef CONFIG_UART1_CONSOLE
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
 /*-----------------------------------------------------------------------
@@ -97,21 +97,21 @@
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector		*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
 #define CONFIG_ENV_OVERWRITE	1
@@ -138,14 +138,13 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
-#define CFG_I2C_SPEED		100000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	(0xa4>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa4>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
@@ -190,8 +189,8 @@
 
 /* check U-Boot image with SHA1 sum */
 #define CONFIG_SHA1_CHECK_UB_IMG	1
-#define CONFIG_SHA1_START		CFG_MONITOR_BASE
-#define CONFIG_SHA1_LEN			CFG_MONITOR_LEN
+#define CONFIG_SHA1_START		CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SHA1_LEN			CONFIG_SYS_MONITOR_LEN
 
 /*-----------------------------------------------------------------------
  * Definitions for status LED
@@ -200,16 +199,16 @@
 #define CONFIG_BOARD_SPECIFIC_LED	1
 
 #define STATUS_LED_BIT		0x08			/* DIAG1 is on GPIO_PPC_1 */
-#define STATUS_LED_PERIOD	((CFG_HZ / 2) / 5)	/* blink at 5 Hz */
+#define STATUS_LED_PERIOD	((CONFIG_SYS_HZ / 2) / 5)	/* blink at 5 Hz */
 #define STATUS_LED_STATE	STATUS_LED_OFF
 #define STATUS_LED_BIT1		0x04			/* DIAG2 is on GPIO_PPC_2 */
-#define STATUS_LED_PERIOD1	((CFG_HZ / 2) / 5)	/* blink at 5 Hz */
+#define STATUS_LED_PERIOD1	((CONFIG_SYS_HZ / 2) / 5)	/* blink at 5 Hz */
 #define STATUS_LED_STATE1	STATUS_LED_ON
 #define STATUS_LED_BIT2		0x02			/* DIAG3 is on GPIO_PPC_3 */
-#define STATUS_LED_PERIOD2	((CFG_HZ / 2) / 5)	/* blink at 5 Hz */
+#define STATUS_LED_PERIOD2	((CONFIG_SYS_HZ / 2) / 5)	/* blink at 5 Hz */
 #define STATUS_LED_STATE2	STATUS_LED_OFF
 #define STATUS_LED_BIT3		0x01			/* DIAG4 is on GPIO_PPC_4 */
-#define STATUS_LED_PERIOD3	((CFG_HZ / 2) / 5)	/* blink at 5 Hz */
+#define STATUS_LED_PERIOD3	((CONFIG_SYS_HZ / 2) / 5)	/* blink at 5 Hz */
 #define STATUS_LED_STATE3	STATUS_LED_OFF
 
 #define CONFIG_SHOW_BOOT_PROGRESS	1
@@ -217,15 +216,16 @@
 #define CONFIG_BAUDRATE		115200
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_NET_MULTI        1	/* required for netconsole      */
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
 #define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
 #define CONFIG_PHY1_ADDR        2
 
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+#define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
 
 #define CONFIG_NETCONSOLE		/* include NetConsole support	*/
 
@@ -288,25 +288,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on	        */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 #define CONFIG_LYNXKDI          1       /* support kdi files            */
 
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -316,21 +316,21 @@
 #define CONFIG_PCI			/* include pci support	        */
 #undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
-#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+#define CONFIG_SYS_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT
-#define CFG_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
 
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
@@ -338,36 +338,36 @@
 #define FLASH_BASE0_PRELIM	0xFFF00000	/* FLASH bank #0	*/
 #define FLASH_BASE1_PRELIM	0xFFF80000	/* FLASH bank #1	*/
 
-#define CFG_FLASH		FLASH_BASE0_PRELIM
-#define CFG_SRAM		0xF1000000
-#define CFG_FPGA		0xF2000000
-#define CFG_CF1			0xF0000000
-#define CFG_CF2			0xF0100000
+#define CONFIG_SYS_FLASH		FLASH_BASE0_PRELIM
+#define CONFIG_SYS_SRAM		0xF1000000
+#define CONFIG_SYS_FPGA		0xF2000000
+#define CONFIG_SYS_CF1			0xF0000000
+#define CONFIG_SYS_CF2			0xF0100000
 
 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CFG_EBC_PB0AP		0x02010000	/* TWT=4,OEN=1			*/
-#define CFG_EBC_PB0CR		(CFG_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB0AP		0x02010000	/* TWT=4,OEN=1			*/
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit	*/
 
 /* Memory Bank 1 (SRAM) initialization						*/
-#define CFG_EBC_PB1AP		0x01810040	/* TWT=3,OEN=1,BEM=1		*/
-#define CFG_EBC_PB1CR		(CFG_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit	*/
+#define CONFIG_SYS_EBC_PB1AP		0x01810040	/* TWT=3,OEN=1,BEM=1		*/
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit	*/
 
 /* Memory Bank 2 (FPGA) initialization						*/
-#define CFG_EBC_PB2AP		0x01010440	/* TWT=2,OEN=1,TH=2,BEM=1	*/
-#define CFG_EBC_PB2CR		(CFG_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit	*/
+#define CONFIG_SYS_EBC_PB2AP		0x01010440	/* TWT=2,OEN=1,TH=2,BEM=1	*/
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit	*/
 
 /* Memory Bank 3 (CompactFlash) initialization					*/
-#define CFG_EBC_PB3AP		0x080BD400
-#define CFG_EBC_PB3CR		(CFG_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit	*/
+#define CONFIG_SYS_EBC_PB3AP		0x080BD400
+#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit	*/
 
 /* Memory Bank 4 (CompactFlash) initialization					*/
-#define CFG_EBC_PB4AP		0x080BD400
-#define CFG_EBC_PB4CR		(CFG_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit	*/
+#define CONFIG_SYS_EBC_PB4AP		0x080BD400
+#define CONFIG_SYS_EBC_PB4CR		(CONFIG_SYS_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit	*/
 
 /*-----------------------------------------------------------------------
  * PPC440 GPIO Configuration
  */
-#define CFG_4xx_GPIO_TABLE { /*	  Out		       GPIO	Alternate1	Alternate2   Alternate3 */ \
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		       GPIO	Alternate1	Alternate2   Alternate3 */ \
 {											\
 /* GPIO Core 0 */									\
 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/ \
@@ -463,23 +463,23 @@
 #undef  CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
 #undef  CONFIG_IDE_LED			/* LED   for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 2 drives per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 2 drives per IDE bus	*/
 
 #define CONFIG_IDE_PREINIT	1
 #define CONFIG_IDE_RESET	1
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_CF1
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_CF1
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	0
+#define CONFIG_SYS_ATA_DATA_OFFSET	0
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x0000)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0000)
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h
index 664a885..9214519 100644
--- a/include/configs/pcu_e.h
+++ b/include/configs/pcu_e.h
@@ -61,7 +61,7 @@
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -75,8 +75,8 @@
 #define	CONFIG_SPI_X			/* 16 bit EEPROM addressing	*/
 
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 
 /* ----------------------------------------------------------------
@@ -87,7 +87,7 @@
  * far enough from the start of the data area (as well as from the
  * stack pointer).
  * ---------------------------------------------------------------- */
-#define CFG_SPI_INIT_OFFSET		0xB00
+#define CONFIG_SYS_SPI_INIT_OFFSET		0xB00
 
 
 /*
@@ -114,60 +114,60 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address	*/
 
-#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+#define	CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
 
 /* Ethernet hardware configuration done using port pins */
-#define CFG_PB_ETH_RESET	0x00000020		/* PB 26	*/
+#define CONFIG_SYS_PB_ETH_RESET	0x00000020		/* PB 26	*/
 #if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CFG_PA_ETH_MDDIS	0x4000			/* PA  1	*/
-#define CFG_PB_ETH_POWERDOWN	0x00000800		/* PB 20	*/
-#define CFG_PB_ETH_CFG1		0x00000400		/* PB 21	*/
-#define CFG_PB_ETH_CFG2		0x00000200		/* PB 22	*/
-#define CFG_PB_ETH_CFG3		0x00000100		/* PB 23	*/
+#define CONFIG_SYS_PA_ETH_MDDIS	0x4000			/* PA  1	*/
+#define CONFIG_SYS_PB_ETH_POWERDOWN	0x00000800		/* PB 20	*/
+#define CONFIG_SYS_PB_ETH_CFG1		0x00000400		/* PB 21	*/
+#define CONFIG_SYS_PB_ETH_CFG2		0x00000200		/* PB 22	*/
+#define CONFIG_SYS_PB_ETH_CFG3		0x00000100		/* PB 23	*/
 #else /* XXX */
-#define CFG_PB_ETH_MDDIS	0x00000010		/* PB 27	*/
-#define CFG_PB_ETH_POWERDOWN	0x00000100		/* PB 23	*/
-#define CFG_PB_ETH_CFG1		0x00000200		/* PB 22	*/
-#define CFG_PB_ETH_CFG2		0x00000400		/* PB 21	*/
-#define CFG_PB_ETH_CFG3		0x00000800		/* PB 20	*/
+#define CONFIG_SYS_PB_ETH_MDDIS	0x00000010		/* PB 27	*/
+#define CONFIG_SYS_PB_ETH_POWERDOWN	0x00000100		/* PB 23	*/
+#define CONFIG_SYS_PB_ETH_CFG1		0x00000200		/* PB 22	*/
+#define CONFIG_SYS_PB_ETH_CFG2		0x00000400		/* PB 21	*/
+#define CONFIG_SYS_PB_ETH_CFG3		0x00000800		/* PB 20	*/
 #endif /* XXX */
 
 /* Ethernet settings:
  * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex
  */
-#define CFG_ETH_MDDIS_VALUE	0
-#define CFG_ETH_CFG1_VALUE	1
-#define CFG_ETH_CFG2_VALUE	1
-#define CFG_ETH_CFG3_VALUE	1
+#define CONFIG_SYS_ETH_MDDIS_VALUE	0
+#define CONFIG_SYS_ETH_CFG1_VALUE	1
+#define CONFIG_SYS_ETH_CFG2_VALUE	1
+#define CONFIG_SYS_ETH_CFG3_VALUE	1
 
 /* PUMA configuration */
 #if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CFG_PB_PUMA_PROG	0x00000010		/* PB 27	*/
+#define CONFIG_SYS_PB_PUMA_PROG	0x00000010		/* PB 27	*/
 #else /* XXX */
-#define CFG_PA_PUMA_PROG	0x4000			/* PA  1	*/
+#define CONFIG_SYS_PA_PUMA_PROG	0x4000			/* PA  1	*/
 #endif /* XXX */
-#define CFG_PC_PUMA_DONE	0x0008			/* PC 12	*/
-#define CFG_PC_PUMA_INIT	0x0004			/* PC 13	*/
+#define CONFIG_SYS_PC_PUMA_DONE	0x0008			/* PC 12	*/
+#define CONFIG_SYS_PC_PUMA_INIT	0x0004			/* PC 13	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -177,53 +177,53 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFE000000
+#define CONFIG_SYS_IMMR		0xFE000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Address accessed to reset the board - must not be mapped/assigned
  */
-#define	CFG_RESET_ADDRESS	0xFEFFFFFF
+#define	CONFIG_SYS_RESET_ADDRESS	0xFEFFFFFF
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
 /* this is an ugly hack needed because of the silly non-constant address map */
-#define CFG_FLASH_BASE		(0-flash_info[0].size-flash_info[1].size)
+#define CONFIG_SYS_FLASH_BASE		(0-flash_info[0].size-flash_info[1].size)
 
 #if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	160	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	160	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	180000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	180000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
 #if 0
 /* Start port with environment in flash; switch to SPI EEPROM later */
@@ -235,8 +235,8 @@
 #else
 /* Final version: environment in EEPROM */
 #define CONFIG_ENV_IS_IN_EEPROM	1
-#define CFG_I2C_EEPROM_ADDR	0
-#define CFG_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
 #define CONFIG_ENV_OFFSET		1024
 #define CONFIG_ENV_SIZE		1024
 #endif
@@ -244,8 +244,8 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control				11-9
@@ -254,10 +254,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -268,21 +268,21 @@
  * Asynchronous external master enable.
  */
 /* => 0x70600200 */
-#define CFG_SIUMCR	(SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -291,15 +291,15 @@
  * interrupt status bit, set PLL multiplication factor !
  */
 /* 0x00004080 */
-#define	CFG_PLPRCR_MF	0	/* (0+1) * 50 = 50 MHz Clock */
-#define CFG_PLPRCR							\
-		(	(CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) |		\
+#define	CONFIG_SYS_PLPRCR_MF	0	/* (0+1) * 50 = 50 MHz Clock */
+#define CONFIG_SYS_PLPRCR							\
+		(	(CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) |		\
 			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
 			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
 			PLPRCR_CSR    /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/	\
 		)
 
-#define	CONFIG_8xx_GCLK_FREQ	((CFG_PLPRCR_MF+1)*50000000)
+#define	CONFIG_8xx_GCLK_FREQ	((CONFIG_SYS_PLPRCR_MF+1)*50000000)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -311,7 +311,7 @@
  */
 #define SCCR_MASK	SCCR_EBDF11
 /* 0x01800000 */
-#define CFG_SCCR	(SCCR_COM00	| /*SCCR_TBS|*/		\
+#define CONFIG_SYS_SCCR	(SCCR_COM00	| /*SCCR_TBS|*/		\
 			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
 			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
 			 SCCR_EBDF00 |   SCCR_DFSYNC00 |	\
@@ -328,34 +328,34 @@
  * Don't expect the "date" command to work without a 32kHz clock input!
  */
 /* 0x00C3 => 0x0003 */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration Register		19-4
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR 0x0000
+#define CONFIG_SYS_RCCR 0x0000
 
 /*-----------------------------------------------------------------------
  * RMDS - RISC Microcode Development Support Control Register
  *-----------------------------------------------------------------------
  */
-#define CFG_RMDS 0
+#define CONFIG_SYS_RMDS 0
 
 /*-----------------------------------------------------------------------
  *
  * Interrupt Levels
  *-----------------------------------------------------------------------
  */
-#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
+#define CONFIG_SYS_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -374,27 +374,27 @@
  * used to re-map FLASH: restrict access enough but not too much to
  * meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0xFF800000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0xFF800000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
 
 /* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1			*/
-#define CFG_OR_TIMING_FLASH	(OR_SCY_8_CLK | OR_EHTR)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_SCY_8_CLK | OR_EHTR)
 
-#define CFG_OR0_REMAP	( CFG_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \
-				CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
-				CFG_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_REMAP	( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \
+				CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
+				CONFIG_SYS_OR_TIMING_FLASH)
 /* 16 bit, bank valid */
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 
 #if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CFG_OR6_REMAP	CFG_OR0_REMAP
-#define CFG_OR6_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR6_PRELIM	((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_OR6_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR6_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR6_PRELIM	((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 #else /* XXX */
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 #endif /* XXX */
 
 /*
@@ -413,11 +413,11 @@
 #define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
 
 #if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CFG_OR5_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CFG_BR5_PRELIM	((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR5_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
+#define CONFIG_SYS_BR5_PRELIM	((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else /* XXX */
-#define CFG_OR2_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #endif /* XXX */
 
 /*
@@ -429,11 +429,11 @@
 #define CAN_CTRLR_TIMING	(OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR)
 
 #if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CFG_BR4_PRELIM		((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CFG_OR4_PRELIM		(CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
+#define CONFIG_SYS_BR4_PRELIM		((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR4_PRELIM		(CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
 #else /* XXX */
-#define CFG_BR3_PRELIM		((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CFG_OR3_PRELIM		(CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
+#define CONFIG_SYS_BR3_PRELIM		((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM		(CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
 #endif /* XXX */
 
 /*
@@ -461,11 +461,11 @@
 #define PUMA_CONF_OR_READ	(PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
 
 #if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CFG_BR3_PRELIM		PUMA_CONF_BR_READ
-#define CFG_OR3_PRELIM		PUMA_CONF_OR_READ
+#define CONFIG_SYS_BR3_PRELIM		PUMA_CONF_BR_READ
+#define CONFIG_SYS_OR3_PRELIM		PUMA_CONF_OR_READ
 #else /* XXX */
-#define CFG_BR4_PRELIM		PUMA_CONF_BR_READ
-#define CFG_OR4_PRELIM		PUMA_CONF_OR_READ
+#define CONFIG_SYS_BR4_PRELIM		PUMA_CONF_BR_READ
+#define CONFIG_SYS_OR4_PRELIM		PUMA_CONF_OR_READ
 #endif /* XXX */
 
 /*
@@ -477,11 +477,11 @@
 #define PUMA_SMA8_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)
 
 #if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CFG_BR2_PRELIM		((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CFG_OR2_PRELIM		(PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
+#define CONFIG_SYS_BR2_PRELIM		((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR2_PRELIM		(PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
 #else /* XXX */
-#define CFG_BR5_PRELIM		((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CFG_OR5_PRELIM		(PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
+#define CONFIG_SYS_BR5_PRELIM		((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR5_PRELIM		(PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
 #endif /* XXX */
 
 /*
@@ -493,11 +493,11 @@
 #define PUMA_SMA16_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)
 
 #if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CFG_BR1_PRELIM		((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CFG_OR1_PRELIM		(PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
+#define CONFIG_SYS_BR1_PRELIM		((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM		(PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
 #else /* XXX */
-#define CFG_BR6_PRELIM		((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CFG_OR6_PRELIM		(PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
+#define CONFIG_SYS_BR6_PRELIM		((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR6_PRELIM		(PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
 #endif /* XXX */
 
 /*
@@ -508,15 +508,15 @@
 #define PUMA_FLASH_OR_AM	0xFE000000	/* 32 MB */
 #define PUMA_FLASH_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)
 
-#define CFG_BR7_PRELIM		((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CFG_OR7_PRELIM		(PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
+#define CONFIG_SYS_BR7_PRELIM		((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR7_PRELIM		(PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
 
 /*
  * Memory Periodic Timer Prescaler
  */
 
 /* periodic timer for refresh */
-#define CFG_MPTPR	0x0200
+#define CONFIG_SYS_MPTPR	0x0200
 
 /*
  * MAMR settings for SDRAM
@@ -525,9 +525,9 @@
  * 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X
  */
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	0x30	/* = 48 */
+#define CONFIG_SYS_MAMR_PTA	0x30	/* = 48 */
 
-#define CFG_MAMR	( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \
+#define CONFIG_SYS_MAMR	( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | \
 			  MAMR_AMA_TYPE_1	| \
 			  MAMR_G0CLA_A10	| \
 			  MAMR_RLFA_1X		| \
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
index 856917e..4da401f 100644
--- a/include/configs/pdnb3.h
+++ b/include/configs/pdnb3.h
@@ -45,7 +45,7 @@
 #define CONFIG_HAS_ETH1
 #define CONFIG_PHY1_ADDR	18	/* NPE1 PHY address		*/
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define CFG_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
 
 /*
  * Misc configuration options
@@ -53,7 +53,7 @@
 #define CONFIG_USE_IRQ          1	/* we need IRQ stuff for timer	*/
 
 #define CONFIG_BOOTCOUNT_LIMIT		/* support for bootcount limit	*/
-#define CFG_BOOTCOUNT_ADDR	0x60003000 /* inside qmrg sram		*/
+#define CONFIG_SYS_BOOTCOUNT_ADDR	0x60003000 /* inside qmrg sram		*/
 
 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
 #define CONFIG_SETUP_MEMORY_TAGS 1
@@ -62,14 +62,15 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(1 << 20)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
+#define CONFIG_IXP_SERIAL
 #define CONFIG_BAUDRATE         115200
-#define CFG_IXP425_CONSOLE	IXP425_UART1   /* we use UART1 for console */
+#define CONFIG_SYS_IXP425_CONSOLE	IXP425_UART1   /* we use UART1 for console */
 
 
 /*
@@ -105,21 +106,21 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP                            /* undef to save memory         */
-#define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
-#define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS             16              /* max number of command args   */
-#define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
-
-#define CFG_MEMTEST_START       0x00400000      /* memtest works on     */
-#define CFG_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
-#define CFG_LOAD_ADDR           0x00010000      /* default load address */
-
-#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_LONGHELP                            /* undef to save memory         */
+#define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt       */
+#define CONFIG_SYS_CBSIZE              256             /* Console I/O Buffer Size      */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS             16              /* max number of command args   */
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE      /* Boot Argument Buffer Size    */
+
+#define CONFIG_SYS_MEMTEST_START       0x00400000      /* memtest works on     */
+#define CONFIG_SYS_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
+#define CONFIG_SYS_LOAD_ADDR           0x00010000      /* default load address */
+
+#undef  CONFIG_SYS_CLKS_IN_HZ          /* everything, incl board info, in Hz */
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Stack sizes
@@ -188,64 +189,64 @@
 #define PHYS_SDRAM_1            0x00000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE       0x02000000 /* 32 MB */
 
-#define CFG_FLASH_BASE          0x50000000
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CONFIG_SYS_FLASH_BASE          0x50000000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
 #if defined(CONFIG_SCPU)
-#define CFG_MONITOR_LEN		(384 << 10)	/* Reserve 512 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 512 kB for Monitor	*/
 #else
-#define CFG_MONITOR_LEN		(504 << 10)	/* Reserve 512 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_LEN		(504 << 10)	/* Reserve 512 kB for Monitor	*/
 #endif
 
 /*
  * Expansion bus settings
  */
 #if defined(CONFIG_SCPU)
-#define CFG_EXP_CS0		0x94d23C42	/* 8bit, max size		*/
+#define CONFIG_SYS_EXP_CS0		0x94d23C42	/* 8bit, max size		*/
 #else
-#define CFG_EXP_CS0		0x94913C43	/* 8bit, max size		*/
+#define CONFIG_SYS_EXP_CS0		0x94913C43	/* 8bit, max size		*/
 #endif
-#define CFG_EXP_CS1		0x85000043	/* 8bit, 512bytes		*/
+#define CONFIG_SYS_EXP_CS1		0x85000043	/* 8bit, 512bytes		*/
 
 /*
  * SDRAM settings
  */
-#define CFG_SDR_CONFIG		0x18
-#define CFG_SDR_MODE_CONFIG	0x1
-#define CFG_SDRAM_REFRESH_CNT	0x81a
+#define CONFIG_SYS_SDR_CONFIG		0x18
+#define CONFIG_SYS_SDR_MODE_CONFIG	0x1
+#define CONFIG_SYS_SDRAM_REFRESH_CNT	0x81a
 
 /*
  * FLASH and environment organization
  */
 #if defined(CONFIG_SCPU)
-#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
 #define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
-#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/
 #endif
 
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE		/* FLASH bank #0	*/
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE		/* FLASH bank #0	*/
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 #if defined(CONFIG_SCPU)
 /* no redundant environment on SCPU */
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* size of one complete sector		*/
@@ -263,9 +264,8 @@
 /*
  * NAND-FLASH stuff
  */
-#define CFG_MAX_NAND_DEVICE	1
-#define NAND_MAX_CHIPS		1
-#define CFG_NAND_BASE		0x51000000	/* NAND FLASH Base Address	*/
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x51000000	/* NAND FLASH Base Address	*/
 #endif
 
 /*
@@ -273,22 +273,22 @@
  */
 
 /* FPGA program pin configuration */
-#define CFG_GPIO_PRG		12		/* FPGA program pin (cpu output)*/
-#define CFG_GPIO_CLK		10		/* FPGA clk pin (cpu output)    */
-#define CFG_GPIO_DATA		14		/* FPGA data pin (cpu output)   */
-#define CFG_GPIO_INIT		13		/* FPGA init pin (cpu input)    */
-#define CFG_GPIO_DONE		11		/* FPGA done pin (cpu input)    */
+#define CONFIG_SYS_GPIO_PRG		12		/* FPGA program pin (cpu output)*/
+#define CONFIG_SYS_GPIO_CLK		10		/* FPGA clk pin (cpu output)    */
+#define CONFIG_SYS_GPIO_DATA		14		/* FPGA data pin (cpu output)   */
+#define CONFIG_SYS_GPIO_INIT		13		/* FPGA init pin (cpu input)    */
+#define CONFIG_SYS_GPIO_DONE		11		/* FPGA done pin (cpu input)    */
 
 /* other GPIO's */
-#define CFG_GPIO_RESTORE_INT	0
-#define CFG_GPIO_RESTART_INT	1
-#define CFG_GPIO_SYS_RUNNING	2
-#define CFG_GPIO_PCI_INTA	3
-#define CFG_GPIO_PCI_INTB	4
-#define CFG_GPIO_I2C_SCL	6
-#define CFG_GPIO_I2C_SDA	7
-#define CFG_GPIO_FPGA_RESET	9
-#define CFG_GPIO_CLK_33M	15
+#define CONFIG_SYS_GPIO_RESTORE_INT	0
+#define CONFIG_SYS_GPIO_RESTART_INT	1
+#define CONFIG_SYS_GPIO_SYS_RUNNING	2
+#define CONFIG_SYS_GPIO_PCI_INTA	3
+#define CONFIG_SYS_GPIO_PCI_INTB	4
+#define CONFIG_SYS_GPIO_I2C_SCL	6
+#define CONFIG_SYS_GPIO_I2C_SDA	7
+#define CONFIG_SYS_GPIO_FPGA_RESET	9
+#define CONFIG_SYS_GPIO_CLK_33M	15
 
 /*
  * I2C stuff
@@ -298,23 +298,23 @@
 #undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define	CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
 
-#define CFG_I2C_SPEED		83000	/* 83 kHz is supposed to work	*/
-#define CFG_I2C_SLAVE		0xFE
+#define CONFIG_SYS_I2C_SPEED		83000	/* 83 kHz is supposed to work	*/
+#define CONFIG_SYS_I2C_SLAVE		0xFE
 
 /*
  * Software (bit-bang) I2C driver configuration
  */
-#define PB_SCL		(1 << CFG_GPIO_I2C_SCL)
-#define PB_SDA		(1 << CFG_GPIO_I2C_SDA)
+#define PB_SCL		(1 << CONFIG_SYS_GPIO_I2C_SCL)
+#define PB_SDA		(1 << CONFIG_SYS_GPIO_I2C_SDA)
 
-#define I2C_INIT	GPIO_OUTPUT_ENABLE(CFG_GPIO_I2C_SCL)
-#define I2C_ACTIVE	GPIO_OUTPUT_ENABLE(CFG_GPIO_I2C_SDA)
-#define I2C_TRISTATE	GPIO_OUTPUT_DISABLE(CFG_GPIO_I2C_SDA)
+#define I2C_INIT	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SCL)
+#define I2C_ACTIVE	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SDA)
+#define I2C_TRISTATE	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_I2C_SDA)
 #define I2C_READ	((*IXP425_GPIO_GPINR & PB_SDA) != 0)
-#define I2C_SDA(bit)	if (bit) GPIO_OUTPUT_SET(CFG_GPIO_I2C_SDA);	\
-	                else     GPIO_OUTPUT_CLEAR(CFG_GPIO_I2C_SDA)
-#define I2C_SCL(bit)	if (bit) GPIO_OUTPUT_SET(CFG_GPIO_I2C_SCL);	\
-			else     GPIO_OUTPUT_CLEAR(CFG_GPIO_I2C_SCL)
+#define I2C_SDA(bit)	if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SDA);	\
+	                else     GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SDA)
+#define I2C_SCL(bit)	if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SCL);	\
+			else     GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SCL)
 #define I2C_DELAY	udelay(3)	/* 1/4 I2C clock duration */
 
 /*
@@ -322,28 +322,28 @@
  */
 #if 0 /* test-only */
 #define CONFIG_RTC_DS1340	1
-#define CFG_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
 #else
 /* M41T11 Serial Access Timekeeper(R) SRAM */
 #define CONFIG_RTC_M41T11	1
-#define CFG_I2C_RTC_ADDR	0x68
-#define CFG_M41T11_BASE_YEAR	1900	/* play along with the linux driver */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	1900	/* play along with the linux driver */
 #endif
 
 /*
  * Spartan3 FPGA configuration support
  */
-#define CFG_FPGA_MAX_SIZE	700*1024	/* 700kByte for XC3S500E	*/
+#define CONFIG_SYS_FPGA_MAX_SIZE	700*1024	/* 700kByte for XC3S500E	*/
 
-#define CFG_FPGA_PRG	(1 << CFG_GPIO_PRG)	/* FPGA program pin (cpu output)*/
-#define CFG_FPGA_CLK	(1 << CFG_GPIO_CLK)	/* FPGA clk pin (cpu output)    */
-#define CFG_FPGA_DATA	(1 << CFG_GPIO_DATA)	/* FPGA data pin (cpu output)   */
-#define CFG_FPGA_INIT	(1 << CFG_GPIO_INIT)	/* FPGA init pin (cpu input)    */
-#define CFG_FPGA_DONE	(1 << CFG_GPIO_DONE)	/* FPGA done pin (cpu input)    */
+#define CONFIG_SYS_FPGA_PRG	(1 << CONFIG_SYS_GPIO_PRG)	/* FPGA program pin (cpu output)*/
+#define CONFIG_SYS_FPGA_CLK	(1 << CONFIG_SYS_GPIO_CLK)	/* FPGA clk pin (cpu output)    */
+#define CONFIG_SYS_FPGA_DATA	(1 << CONFIG_SYS_GPIO_DATA)	/* FPGA data pin (cpu output)   */
+#define CONFIG_SYS_FPGA_INIT	(1 << CONFIG_SYS_GPIO_INIT)	/* FPGA init pin (cpu input)    */
+#define CONFIG_SYS_FPGA_DONE	(1 << CONFIG_SYS_GPIO_DONE)	/* FPGA done pin (cpu input)    */
 
 /*
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SIZE	32
 
 #endif  /* __CONFIG_H */
diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h
index 66ad01f..8ca55d7 100644
--- a/include/configs/pf5200.h
+++ b/include/configs/pf5200.h
@@ -44,7 +44,7 @@
 #define CONFIG_PF5200		1	/* ... on PF5200  board */
 #define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM	*/
 
-#define CFG_MPC5XXX_CLKIN	33000000	/* ... running at 33.000000MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* ... running at 33.000000MHz */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
@@ -59,7 +59,7 @@
 #else
 #define CONFIG_BAUDRATE		9600	/* ... at 115200 bps */
 #endif
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #ifdef CONFIG_MPC5200		/* MPC5100 PCI is not supported yet. */
 /*
@@ -84,7 +84,7 @@
 #if 0				/* test-only !!! */
 #define CONFIG_NET_MULTI	1
 #define CONFIG_EEPRO100		1
-#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
+#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
 #define CONFIG_NS8382X		1
 #endif
 #endif
@@ -127,12 +127,12 @@
 
 
 #if (TEXT_BASE == 0xFF000000)	/* Boot low with 16 MB Flash */
-#   define CFG_LOWBOOT		1
-#   define CFG_LOWBOOT16	1
+#   define CONFIG_SYS_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT16	1
 #endif
 #if (TEXT_BASE == 0xFF800000)	/* Boot low with  8 MB Flash */
-#   define CFG_LOWBOOT		1
-#   define CFG_LOWBOOT08	1
+#   define CONFIG_SYS_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT08	1
 #endif
 
 /*
@@ -170,36 +170,36 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 #endif
 /*
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
 
-#define CFG_I2C_SPEED		86000	/* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		86000	/* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration
  */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CFG_I2C_EEPROM_ADDR_LEN		2
-#define CFG_EEPROM_PAGE_WRITE_BITS	5
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
-#define CFG_I2C_MULTI_EEPROMS		1
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CONFIG_SYS_I2C_MULTI_EEPROMS		1
 /*
  * Flash configuration
  */
-#define CFG_FLASH_BASE		0xFE000000
-#define CFG_FLASH_SIZE		0x02000000
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00000000)
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	512
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_SIZE		0x02000000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00000000)
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
 
 /*
  * Environment settings
@@ -220,97 +220,98 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
 /*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
  */
-/* #define CONFIG_FEC_10MBIT 1 */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
 #define CONFIG_PHY_ADDR		0x00
 #define CONFIG_UDP_CHECKSUM	1
 
 /*
  * GPIO configuration
  */
-#define CFG_GPS_PORT_CONFIG	0x01052444
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x01052444
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*
  * Various low-level settings
  */
 #if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 #else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
 #endif
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x0004DD00
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x0004DD00
 
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
-#define CFG_CS1_START		0xfd000000
-#define CFG_CS1_SIZE		0x00010000
-#define CFG_CS1_CFG		0x10101410
+#define CONFIG_SYS_CS1_START		0xfd000000
+#define CONFIG_SYS_CS1_SIZE		0x00010000
+#define CONFIG_SYS_CS1_CFG		0x10101410
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
 
-#define CFG_RESET_ADDRESS	0xff000000
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
 
 /*-----------------------------------------------------------------------
  * USB stuff
@@ -332,71 +333,71 @@
 #define	CONFIG_IDE_RESET	/* reset for ide supported	*/
 #define CONFIG_IDE_PREINIT
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(0x0060)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005C)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
 
 /* Interval between registers						     */
-#define CFG_ATA_STRIDE		4
+#define CONFIG_SYS_ATA_STRIDE		4
 
 /*-----------------------------------------------------------------------
  * CPLD stuff
  */
-#define CFG_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD	 */
-#define CFG_FPGA_MAX_SIZE	32*1024	/* 32kByte is enough for CPLD	 */
+#define CONFIG_SYS_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD	 */
+#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	/* 32kByte is enough for CPLD	 */
 
 /* CPLD program pin configuration */
-#define CFG_FPGA_PRG		0x20000000	/* JTAG TMS pin (ppc output)	       */
-#define CFG_FPGA_CLK		0x10000000	/* JTAG TCK pin (ppc output)	       */
-#define CFG_FPGA_DATA		0x20000000	/* JTAG TDO->TDI data pin (ppc output) */
-#define CFG_FPGA_DONE		0x10000000	/* JTAG TDI->TDO pin (ppc input)       */
+#define CONFIG_SYS_FPGA_PRG		0x20000000	/* JTAG TMS pin (ppc output)	       */
+#define CONFIG_SYS_FPGA_CLK		0x10000000	/* JTAG TCK pin (ppc output)	       */
+#define CONFIG_SYS_FPGA_DATA		0x20000000	/* JTAG TDO->TDI data pin (ppc output) */
+#define CONFIG_SYS_FPGA_DONE		0x10000000	/* JTAG TDI->TDO pin (ppc input)       */
 
-#define JTAG_GPIO_ADDR_TMS	(CFG_MBAR + 0xB10)	/* JTAG TMS pin (GPS data out value reg.)      */
-#define JTAG_GPIO_ADDR_TCK	(CFG_MBAR + 0xC0C)	/* JTAG TCK pin (GPW data out value reg.)      */
-#define JTAG_GPIO_ADDR_TDI	(CFG_MBAR + 0xC0C)	/* JTAG TDO->TDI pin (GPW data out value reg.) */
-#define JTAG_GPIO_ADDR_TDO	(CFG_MBAR + 0xB14)	/* JTAG TDI->TDO pin (GPS data in value reg.)  */
+#define JTAG_GPIO_ADDR_TMS	(CONFIG_SYS_MBAR + 0xB10)	/* JTAG TMS pin (GPS data out value reg.)      */
+#define JTAG_GPIO_ADDR_TCK	(CONFIG_SYS_MBAR + 0xC0C)	/* JTAG TCK pin (GPW data out value reg.)      */
+#define JTAG_GPIO_ADDR_TDI	(CONFIG_SYS_MBAR + 0xC0C)	/* JTAG TDO->TDI pin (GPW data out value reg.) */
+#define JTAG_GPIO_ADDR_TDO	(CONFIG_SYS_MBAR + 0xB14)	/* JTAG TDI->TDO pin (GPS data in value reg.)  */
 
-#define JTAG_GPIO_ADDR_CFG	(CFG_MBAR + 0xB00)
+#define JTAG_GPIO_ADDR_CFG	(CONFIG_SYS_MBAR + 0xB00)
 #define JTAG_GPIO_CFG_SET	0x00000000
 #define JTAG_GPIO_CFG_RESET	0x00F00000
 
-#define JTAG_GPIO_ADDR_EN_TMS	(CFG_MBAR + 0xB04)
+#define JTAG_GPIO_ADDR_EN_TMS	(CONFIG_SYS_MBAR + 0xB04)
 #define JTAG_GPIO_TMS_EN_SET	0x20000000	/* Enable for GPIO */
 #define JTAG_GPIO_TMS_EN_RESET	0x00000000
-#define JTAG_GPIO_ADDR_DDR_TMS	(CFG_MBAR + 0xB0C)
+#define JTAG_GPIO_ADDR_DDR_TMS	(CONFIG_SYS_MBAR + 0xB0C)
 #define JTAG_GPIO_TMS_DDR_SET	0x20000000	/* Set as output   */
 #define JTAG_GPIO_TMS_DDR_RESET 0x00000000
 
-#define JTAG_GPIO_ADDR_EN_TCK	(CFG_MBAR + 0xC00)
+#define JTAG_GPIO_ADDR_EN_TCK	(CONFIG_SYS_MBAR + 0xC00)
 #define JTAG_GPIO_TCK_EN_SET	0x20000000	/* Enable for GPIO */
 #define JTAG_GPIO_TCK_EN_RESET	0x00000000
-#define JTAG_GPIO_ADDR_DDR_TCK	(CFG_MBAR + 0xC08)
+#define JTAG_GPIO_ADDR_DDR_TCK	(CONFIG_SYS_MBAR + 0xC08)
 #define JTAG_GPIO_TCK_DDR_SET	0x20000000	/* Set as output   */
 #define JTAG_GPIO_TCK_DDR_RESET 0x00000000
 
-#define JTAG_GPIO_ADDR_EN_TDI	(CFG_MBAR + 0xC00)
+#define JTAG_GPIO_ADDR_EN_TDI	(CONFIG_SYS_MBAR + 0xC00)
 #define JTAG_GPIO_TDI_EN_SET	0x10000000	/* Enable as GPIO  */
 #define JTAG_GPIO_TDI_EN_RESET	0x00000000
-#define JTAG_GPIO_ADDR_DDR_TDI	(CFG_MBAR + 0xC08)
+#define JTAG_GPIO_ADDR_DDR_TDI	(CONFIG_SYS_MBAR + 0xC08)
 #define JTAG_GPIO_TDI_DDR_SET	0x10000000	/* Set as output   */
 #define JTAG_GPIO_TDI_DDR_RESET 0x00000000
 
-#define JTAG_GPIO_ADDR_EN_TDO	(CFG_MBAR + 0xB04)
+#define JTAG_GPIO_ADDR_EN_TDO	(CONFIG_SYS_MBAR + 0xB04)
 #define JTAG_GPIO_TDO_EN_SET	0x10000000	/* Enable as GPIO  */
 #define JTAG_GPIO_TDO_EN_RESET	0x00000000
-#define JTAG_GPIO_ADDR_DDR_TDO	(CFG_MBAR + 0xB0C)
+#define JTAG_GPIO_ADDR_DDR_TDO	(CONFIG_SYS_MBAR + 0xB0C)
 #define JTAG_GPIO_TDO_DDR_SET	0x00000000
 #define JTAG_GPIO_TDO_DDR_RESET 0x10000000	/* Set as input	   */
 
diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h
index 66e76e8..59741a9 100644
--- a/include/configs/pleb2.h
+++ b/include/configs/pleb2.h
@@ -45,8 +45,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -104,33 +104,38 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_HUSH_PARSER		1
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
-#define CFG_LONGHELP				/* undef to save memory		*/
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT		"$ "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
 #else
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 #endif
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_DEVICE_NULLDEV	1
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1
 
-#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR		0xa2000000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0xa2000000	/* default load address */
 
-#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x141		/* set core clock to 200/200/100 MHz */
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CPUSPEED		0x141		/* set core clock to 200/200/100 MHz */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#ifdef CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_CMD_MMC
+#endif
 
 /*
  * Stack sizes
@@ -164,86 +169,86 @@
 #define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
 #define PHYS_FLASH_SECT_SIZE	0x00010000 /* 64 KB sectors (x2) */
 
-#define CFG_DRAM_BASE		PHYS_SDRAM_1
-#define CFG_DRAM_SIZE		PHYS_SDRAM_1_SIZE
+#define CONFIG_SYS_DRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_DRAM_SIZE		PHYS_SDRAM_1_SIZE
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
 
 /*
  * GPIO settings
  */
-#define CFG_GPSR0_VAL		0x00000000  /* Don't set anything */
-#define CFG_GPSR1_VAL		0x00000080
-#define CFG_GPSR2_VAL		0x00000000
+#define CONFIG_SYS_GPSR0_VAL		0x00000000  /* Don't set anything */
+#define CONFIG_SYS_GPSR1_VAL		0x00000080
+#define CONFIG_SYS_GPSR2_VAL		0x00000000
 
-#define CFG_GPCR0_VAL		0x00000000  /* Don't clear anything */
-#define CFG_GPCR1_VAL		0x00000000
-#define CFG_GPCR2_VAL		0x00000000
+#define CONFIG_SYS_GPCR0_VAL		0x00000000  /* Don't clear anything */
+#define CONFIG_SYS_GPCR1_VAL		0x00000000
+#define CONFIG_SYS_GPCR2_VAL		0x00000000
 
-#define CFG_GPDR0_VAL		0x00000000
-#define CFG_GPDR1_VAL		0x000007C3
-#define CFG_GPDR2_VAL		0x00000000
+#define CONFIG_SYS_GPDR0_VAL		0x00000000
+#define CONFIG_SYS_GPDR1_VAL		0x000007C3
+#define CONFIG_SYS_GPDR2_VAL		0x00000000
 
 /* Edge detect registers (these are set by the kernel) */
-#define CFG_GRER0_VAL	    0x00000000
-#define CFG_GRER1_VAL	    0x00000000
-#define CFG_GRER2_VAL	    0x00000000
-#define CFG_GFER0_VAL	    0x00000000
-#define CFG_GFER1_VAL	    0x00000000
-#define CFG_GFER2_VAL	    0x00000000
-
-#define CFG_GAFR0_L_VAL		0x00000000
-#define CFG_GAFR0_U_VAL		0x00000000
-#define CFG_GAFR1_L_VAL		0x00008010  /* Use FF UART Send and Receive */
-#define CFG_GAFR1_U_VAL		0x00000000
-#define CFG_GAFR2_L_VAL		0x00000000
-#define CFG_GAFR2_U_VAL		0x00000000
-
-#define CFG_PSSR_VAL		0x20
-#define CFG_CCCR_VAL	    0x00000141	/* 100 MHz memory, 200 MHz CPU	*/
-#define CFG_CKEN_VAL	    0x00000060	/* FFUART and STUART enabled	*/
-#define CFG_ICMR_VAL	    0x00000000	/* No interrupts enabled	*/
+#define CONFIG_SYS_GRER0_VAL	    0x00000000
+#define CONFIG_SYS_GRER1_VAL	    0x00000000
+#define CONFIG_SYS_GRER2_VAL	    0x00000000
+#define CONFIG_SYS_GFER0_VAL	    0x00000000
+#define CONFIG_SYS_GFER1_VAL	    0x00000000
+#define CONFIG_SYS_GFER2_VAL	    0x00000000
+
+#define CONFIG_SYS_GAFR0_L_VAL		0x00000000
+#define CONFIG_SYS_GAFR0_U_VAL		0x00000000
+#define CONFIG_SYS_GAFR1_L_VAL		0x00008010  /* Use FF UART Send and Receive */
+#define CONFIG_SYS_GAFR1_U_VAL		0x00000000
+#define CONFIG_SYS_GAFR2_L_VAL		0x00000000
+#define CONFIG_SYS_GAFR2_U_VAL		0x00000000
+
+#define CONFIG_SYS_PSSR_VAL		0x20
+#define CONFIG_SYS_CCCR_VAL	    0x00000141	/* 100 MHz memory, 200 MHz CPU	*/
+#define CONFIG_SYS_CKEN_VAL	    0x00000060	/* FFUART and STUART enabled	*/
+#define CONFIG_SYS_ICMR_VAL	    0x00000000	/* No interrupts enabled	*/
 
 /*
  * Memory settings
  */
-#define CFG_MSC0_VAL		0x00007FF0 /* Not properly calculated - FIXME (DS) */
-#define CFG_MSC1_VAL		0x00000000
-#define CFG_MSC2_VAL		0x00000000
+#define CONFIG_SYS_MSC0_VAL		0x00007FF0 /* Not properly calculated - FIXME (DS) */
+#define CONFIG_SYS_MSC1_VAL		0x00000000
+#define CONFIG_SYS_MSC2_VAL		0x00000000
 
-#define CFG_MDCNFG_VAL		0x00000aC9 /* Memory timings for the SDRAM.
+#define CONFIG_SYS_MDCNFG_VAL		0x00000aC9 /* Memory timings for the SDRAM.
 					      tRP=2, CL=2, tRCD=2, tRAS=5, tRC=8 */
 
-#define CFG_MDREFR_VAL		0x00403018 /* Initial setting, individual	*/
+#define CONFIG_SYS_MDREFR_VAL		0x00403018 /* Initial setting, individual	*/
 					   /* bits set in lowlevel_init.S	*/
-#define CFG_MDMRS_VAL		0x00000000
+#define CONFIG_SYS_MDMRS_VAL		0x00000000
 
 /*
  * PCMCIA and CF Interfaces
  */
-#define CFG_MECR_VAL		0x00000000  /* Hangover from Lubbock.
+#define CONFIG_SYS_MECR_VAL		0x00000000  /* Hangover from Lubbock.
 					       Needs calculating. (DS/CHC) */
-#define CFG_MCMEM0_VAL		0x00010504
-#define CFG_MCMEM1_VAL		0x00010504
-#define CFG_MCATT0_VAL		0x00010504
-#define CFG_MCATT1_VAL		0x00010504
-#define CFG_MCIO0_VAL		0x00004715
-#define CFG_MCIO1_VAL		0x00004715
+#define CONFIG_SYS_MCMEM0_VAL		0x00010504
+#define CONFIG_SYS_MCMEM1_VAL		0x00010504
+#define CONFIG_SYS_MCATT0_VAL		0x00010504
+#define CONFIG_SYS_MCATT1_VAL		0x00010504
+#define CONFIG_SYS_MCIO0_VAL		0x00004715
+#define CONFIG_SYS_MCIO1_VAL		0x00004715
 
 /*
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
 
 /* timeout values are in ticks */
 /* FIXME */
-#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 /* Flash protection */
-#define CFG_FLASH_PROTECTION	1
+#define CONFIG_SYS_FLASH_PROTECTION	1
 
 /* FIXME */
 #define CONFIG_ENV_IS_IN_FLASH	1
@@ -252,6 +257,6 @@
 #define CONFIG_ENV_SECT_SIZE	0x20000
 
 /* Option added to get around byte ordering issues in the flash driver */
-#define CFG_LITTLE_ENDIAN	1
+#define CONFIG_SYS_LITTLE_ENDIAN	1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h
index fd05c7e..0fd8635 100644
--- a/include/configs/ppmc7xx.h
+++ b/include/configs/ppmc7xx.h
@@ -83,7 +83,7 @@
 #include <config_cmd_default.h>
 
 #define CONFIG_CMD_FLASH
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_RUN
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_NET
@@ -206,69 +206,69 @@
 /*
  * SDRAM config - see memory map details above.
  *
- * CFG_SDRAM_BASE		- Start address of SDRAM, this _must_ be zero!
- * CFG_SDRAM_SIZE		- Total size of contiguous SDRAM bank(s)
+ * CONFIG_SYS_SDRAM_BASE		- Start address of SDRAM, this _must_ be zero!
+ * CONFIG_SYS_SDRAM_SIZE		- Total size of contiguous SDRAM bank(s)
  */
 
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_SIZE		0x04000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000
 
 
 /*
  * Flash config - see memory map details above.
  *
- * CFG_FLASH_BASE		- Start address of flash memory
- * CFG_FLASH_SIZE		- Total size of contiguous flash mem
- * CFG_FLASH_ERASE_TOUT		- Erase timeout in ms
- * CFG_FLASH_WRITE_TOUT		- Write timeout in ms
- * CFG_MAX_FLASH_BANKS		- Number of banks of flash on board
- * CFG_MAX_FLASH_SECT		- Number of sectors in a bank
+ * CONFIG_SYS_FLASH_BASE		- Start address of flash memory
+ * CONFIG_SYS_FLASH_SIZE		- Total size of contiguous flash mem
+ * CONFIG_SYS_FLASH_ERASE_TOUT		- Erase timeout in ms
+ * CONFIG_SYS_FLASH_WRITE_TOUT		- Write timeout in ms
+ * CONFIG_SYS_MAX_FLASH_BANKS		- Number of banks of flash on board
+ * CONFIG_SYS_MAX_FLASH_SECT		- Number of sectors in a bank
  */
 
-#define CFG_FLASH_BASE		0xFFC00000
-#define CFG_FLASH_SIZE		0x00400000
-#define CFG_FLASH_ERASE_TOUT	250000
-#define CFG_FLASH_WRITE_TOUT	5000
-#define CFG_MAX_FLASH_BANKS	1
-#define CFG_MAX_FLASH_SECT	19
+#define CONFIG_SYS_FLASH_BASE		0xFFC00000
+#define CONFIG_SYS_FLASH_SIZE		0x00400000
+#define CONFIG_SYS_FLASH_ERASE_TOUT	250000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	5000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	19
 
 
 /*
  * Monitor config - see memory map details above
  *
- * CFG_MONITOR_BASE		- Base address of monitor code
- * CFG_MALLOC_LEN		- Size of malloc pool (128KB)
+ * CONFIG_SYS_MONITOR_BASE		- Base address of monitor code
+ * CONFIG_SYS_MALLOC_LEN		- Size of malloc pool (128KB)
  */
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MALLOC_LEN		0x20000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN		0x20000
 
 
 /*
  * Command shell settings
  *
- * CFG_BARGSIZE			- Boot Argument buffer size
- * CFG_BOOTMAPSZ		- Size of app's mapped RAM at boot (Linux=8MB)
- * CFG_CBSIZE			- Console Buffer (input) size
- * CFG_LOAD_ADDR		- Default load address
- * CFG_LONGHELP			- Provide more detailed help
- * CFG_MAXARGS			- Number of args accepted by monitor commands
- * CFG_MEMTEST_START		- Start address of test to run on RAM
- * CFG_MEMTEST_END		- End address of RAM test
- * CFG_PBSIZE			- Print Buffer (output) size
- * CFG_PROMPT			- Prompt string
+ * CONFIG_SYS_BARGSIZE			- Boot Argument buffer size
+ * CONFIG_SYS_BOOTMAPSZ		- Size of app's mapped RAM at boot (Linux=8MB)
+ * CONFIG_SYS_CBSIZE			- Console Buffer (input) size
+ * CONFIG_SYS_LOAD_ADDR		- Default load address
+ * CONFIG_SYS_LONGHELP			- Provide more detailed help
+ * CONFIG_SYS_MAXARGS			- Number of args accepted by monitor commands
+ * CONFIG_SYS_MEMTEST_START		- Start address of test to run on RAM
+ * CONFIG_SYS_MEMTEST_END		- End address of RAM test
+ * CONFIG_SYS_PBSIZE			- Print Buffer (output) size
+ * CONFIG_SYS_PROMPT			- Prompt string
  */
 
-#define CFG_BARGSIZE		1024
-#define CFG_BOOTMAPSZ		0x800000
-#define CFG_CBSIZE		1024
-#define CFG_LOAD_ADDR		0x100000
-#define CFG_LONGHELP
-#define CFG_MAXARGS		16
-#define CFG_MEMTEST_START	0x00040000
-#define CFG_MEMTEST_END		0x00040100
-#define CFG_PBSIZE		1024
-#define CFG_PROMPT		"=> "
+#define CONFIG_SYS_BARGSIZE		1024
+#define CONFIG_SYS_BOOTMAPSZ		0x800000
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_LOAD_ADDR		0x100000
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_MEMTEST_START	0x00040000
+#define CONFIG_SYS_MEMTEST_END		0x00040100
+#define CONFIG_SYS_PBSIZE		1024
+#define CONFIG_SYS_PROMPT		"=> "
 
 
 /*
@@ -295,16 +295,16 @@
  * in the main system RAM just above the exception vectors. The contents are
  * copied to top of RAM by the init code.
  *
- * CFG_INIT_RAM_ADDR		- Address of Init RAM, above exception vect
- * CFG_INIT_RAM_END		- Size of Init RAM
- * CFG_GBL_DATA_SIZE		- Ammount of RAM to reserve for global data
- * CFG_GBL_DATA_OFFSET		- Start of global data, top of stack
+ * CONFIG_SYS_INIT_RAM_ADDR		- Address of Init RAM, above exception vect
+ * CONFIG_SYS_INIT_RAM_END		- Size of Init RAM
+ * CONFIG_SYS_GBL_DATA_SIZE		- Ammount of RAM to reserve for global data
+ * CONFIG_SYS_GBL_DATA_OFFSET		- Start of global data, top of stack
  */
 
-#define CFG_INIT_RAM_ADDR	(CFG_SDRAM_BASE + 0x4000)
-#define CFG_INIT_RAM_END	0x4000
-#define CFG_GBL_DATA_SIZE	128
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x4000)
+#define CONFIG_SYS_INIT_RAM_END	0x4000
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 
 /*
@@ -316,38 +316,38 @@
  * BAT3 - PCI I/O including Flash Memory
  */
 
-#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L CFG_IBAT0L
-#define CFG_DBAT0U CFG_IBAT0U
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
 
-#define CFG_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
-#define CFG_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
-#define CFG_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
 
 /*
  * Cache config
  *
- * CFG_CACHELINE_SIZE		- Size of a cache line (CPU specific)
- * CFG_L2			- L2 cache enabled if defined
+ * CONFIG_SYS_CACHELINE_SIZE		- Size of a cache line (CPU specific)
+ * CONFIG_SYS_L2			- L2 cache enabled if defined
  * L2_INIT			- L2 cache init flags
  * L2_ENABLE			- L2 cache enable flags
  */
 
-#define CFG_CACHELINE_SIZE	32
-#undef	CFG_L2
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#undef	CONFIG_SYS_L2
 #define L2_INIT			0
 #define L2_ENABLE		0
 
@@ -355,66 +355,66 @@
 /*
  * Clocks config
  *
- * CFG_BUS_HZ			- Bus clock frequency in Hz
- * CFG_BUS_CLK			- As above (?)
- * CFG_HZ			- Decrementer freq in Hz
+ * CONFIG_SYS_BUS_HZ			- Bus clock frequency in Hz
+ * CONFIG_SYS_BUS_CLK			- As above (?)
+ * CONFIG_SYS_HZ			- Decrementer freq in Hz
  */
 
-#define CFG_BUS_HZ		CONFIG_BUS_CLK
-#define CFG_BUS_CLK		CONFIG_BUS_CLK
-#define CFG_HZ			1000
+#define CONFIG_SYS_BUS_HZ		CONFIG_BUS_CLK
+#define CONFIG_SYS_BUS_CLK		CONFIG_BUS_CLK
+#define CONFIG_SYS_HZ			1000
 
 
 /*
  * Serial port config
  *
- * CFG_BAUDRATE_TABLE		- List of valid baud rates
- * CFG_NS16550			- Include the NS16550 driver
- * CFG_NS16550_SERIAL		- Include the serial (wrapper) driver
- * CFG_NS16550_CLK		- Frequency of reference clock
- * CFG_NS16550_REG_SIZE		- 64-bit accesses to 8-bit port
- * CFG_NS16550_COM1		- Base address of 1st serial port
+ * CONFIG_SYS_BAUDRATE_TABLE		- List of valid baud rates
+ * CONFIG_SYS_NS16550			- Include the NS16550 driver
+ * CONFIG_SYS_NS16550_SERIAL		- Include the serial (wrapper) driver
+ * CONFIG_SYS_NS16550_CLK		- Frequency of reference clock
+ * CONFIG_SYS_NS16550_REG_SIZE		- 64-bit accesses to 8-bit port
+ * CONFIG_SYS_NS16550_COM1		- Base address of 1st serial port
  */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_CLK		3686400
-#define CFG_NS16550_REG_SIZE	-8
-#define CFG_NS16550_COM1	0x7C000000
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK		3686400
+#define CONFIG_SYS_NS16550_REG_SIZE	-8
+#define CONFIG_SYS_NS16550_COM1	0x7C000000
 
 
 /*
  * PCI Config - Address Map B (CHRP)
  */
 
-#define CFG_PCI_MEMORY_BUS	0x00000000
-#define CFG_PCI_MEMORY_PHYS	0x00000000
-#define CFG_PCI_MEMORY_SIZE	0x40000000
-#define CFG_PCI_MEM_BUS		0x80000000
-#define CFG_PCI_MEM_PHYS	0x80000000
-#define CFG_PCI_MEM_SIZE	0x7D000000
-#define CFG_ISA_MEM_BUS		0x00000000
-#define CFG_ISA_MEM_PHYS	0xFD000000
-#define CFG_ISA_MEM_SIZE	0x01000000
-#define CFG_PCI_IO_BUS		0x00800000
-#define CFG_PCI_IO_PHYS		0xFE800000
-#define CFG_PCI_IO_SIZE		0x00400000
-#define CFG_ISA_IO_BUS		0x00000000
-#define CFG_ISA_IO_PHYS		0xFE000000
-#define CFG_ISA_IO_SIZE		0x00800000
-#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
-#define CFG_ISA_IO		CFG_ISA_IO_PHYS
-#define CFG_60X_PCI_IO_OFFSET	CFG_ISA_IO_PHYS
+#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
+#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
+#define CONFIG_SYS_PCI_MEMORY_SIZE	0x40000000
+#define CONFIG_SYS_PCI_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI_MEM_SIZE	0x7D000000
+#define CONFIG_SYS_ISA_MEM_BUS		0x00000000
+#define CONFIG_SYS_ISA_MEM_PHYS	0xFD000000
+#define CONFIG_SYS_ISA_MEM_SIZE	0x01000000
+#define CONFIG_SYS_PCI_IO_BUS		0x00800000
+#define CONFIG_SYS_PCI_IO_PHYS		0xFE800000
+#define CONFIG_SYS_PCI_IO_SIZE		0x00400000
+#define CONFIG_SYS_ISA_IO_BUS		0x00000000
+#define CONFIG_SYS_ISA_IO_PHYS		0xFE000000
+#define CONFIG_SYS_ISA_IO_SIZE		0x00800000
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
+#define CONFIG_SYS_ISA_IO		CONFIG_SYS_ISA_IO_PHYS
+#define CONFIG_SYS_60X_PCI_IO_OFFSET	CONFIG_SYS_ISA_IO_PHYS
 
 
 /*
  * Extra init functions
  *
- * CFG_BOARD_ASM_INIT		- Call assembly init code
+ * CONFIG_SYS_BOARD_ASM_INIT		- Call assembly init code
  */
 
-#define CFG_BOARD_ASM_INIT
+#define CONFIG_SYS_BOARD_ASM_INIT
 
 
 /*
diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h
index dd71862..ff7d614 100644
--- a/include/configs/ppmc8260.h
+++ b/include/configs/ppmc8260.h
@@ -65,7 +65,7 @@
  * 0x6	     0x1	 66	133    266   Close  Close  Open
  * 0x6	     0x2	 66	133    300   Close  Open   Close
  */
-#define CFG_PPMC_MODCK_H 0x05
+#define CONFIG_SYS_PPMC_MODCK_H 0x05
 
 /* Define this if you want to boot from 0x00000100. If you don't define
  * this, you will need to program the bootloader to 0xfff00000, and
@@ -73,53 +73,53 @@
  * way to do that is to program the bootloader at both addresses.
  * It is suggested that you just let U-Boot live at 0x00000000.
  */
-#define CFG_PPMC_BOOT_LOW 1
+#define CONFIG_SYS_PPMC_BOOT_LOW 1
 
 /* What should the base address of the main FLASH be and how big is
  * it (in MBytes)? This must contain TEXT_BASE from board/ppmc8260/config.mk
  * The main FLASH is whichever is connected to *CS0. U-Boot expects
  * this to be the SIMM.
  */
-#define CFG_FLASH0_BASE 0xFE000000
-#define CFG_FLASH0_SIZE 16
+#define CONFIG_SYS_FLASH0_BASE 0xFE000000
+#define CONFIG_SYS_FLASH0_SIZE 16
 
 /* What should be the base address of the first SDRAM DIMM and how big is
  * it (in Mbytes)?
 */
-#define CFG_SDRAM0_BASE 0x00000000
-#define CFG_SDRAM0_SIZE 128
+#define CONFIG_SYS_SDRAM0_BASE 0x00000000
+#define CONFIG_SYS_SDRAM0_SIZE 128
 
 /* What should be the base address of the second SDRAM DIMM and how big is
  * it (in Mbytes)?
 */
-#define CFG_SDRAM1_BASE 0x08000000
-#define CFG_SDRAM1_SIZE 128
+#define CONFIG_SYS_SDRAM1_BASE 0x08000000
+#define CONFIG_SYS_SDRAM1_SIZE 128
 
 /* What should be the base address of the on board SDRAM and how big is
  * it (in Mbytes)?
 */
-#define CFG_SDRAM2_BASE 0x38000000
-#define CFG_SDRAM2_SIZE 16
+#define CONFIG_SYS_SDRAM2_BASE 0x38000000
+#define CONFIG_SYS_SDRAM2_SIZE 16
 
 /* What should be the base address of the MAILBOX  and how big is it
  * (in Bytes)
- * The eeprom lives at CFG_MAILBOX_BASE + 0x80000000
+ * The eeprom lives at CONFIG_SYS_MAILBOX_BASE + 0x80000000
  */
-#define CFG_MAILBOX_BASE 0x32000000
-#define CFG_MAILBOX_SIZE 8192
+#define CONFIG_SYS_MAILBOX_BASE 0x32000000
+#define CONFIG_SYS_MAILBOX_SIZE 8192
 
 /* What is the base address of the I/O select lines and how big is it
  * (In Mbytes)?
  */
 
-#define CFG_IOSELECT_BASE 0xE0000000
-#define CFG_IOSELECT_SIZE 32
+#define CONFIG_SYS_IOSELECT_BASE 0xE0000000
+#define CONFIG_SYS_IOSELECT_SIZE 32
 
 
 /* What should be the base address of the LEDs and switch S0?
  * If you don't want them enabled, don't define this.
  */
-#define CFG_LED_BASE 0xF1000000
+#define CONFIG_SYS_LED_BASE 0xF1000000
 
 /*
  * PPMC8260 with 256 16 MB DIMM:
@@ -138,10 +138,10 @@
  *     0x0FF5 FFB0     Board Info Data
  *     0x0FF6 0000     Malloc Arena
  *	     :		    CONFIG_ENV_SECT_SIZE, 256k
- *	     :		    CFG_MALLOC_LEN,    128k
+ *	     :		    CONFIG_SYS_MALLOC_LEN,    128k
  *     0x0FFC 0000     RAM Copy of Monitor Code
- *	     :		    CFG_MONITOR_LEN,   256k
- *     0x0FFF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
+ *	     :		    CONFIG_SYS_MONITOR_LEN,   256k
+ *     0x0FFF FFFF     [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
  */
 
 
@@ -274,10 +274,10 @@
 
 
 /* undef this to save memory */
-#define CFG_LONGHELP
+#define CONFIG_SYS_LONGHELP
 
 /* Monitor Command Prompt */
-#define CFG_PROMPT		"=> "
+#define CONFIG_SYS_PROMPT		"=> "
 
 
 /*
@@ -296,7 +296,7 @@
 
 
 /* Where do the internal registers live? */
-#define CFG_IMMR		0xf0000000
+#define CONFIG_SYS_IMMR		0xf0000000
 
 /*****************************************************************************
  *
@@ -312,36 +312,36 @@
  * Miscellaneous configurable options
  */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CBSIZE		1024	/* Console I/O Buffer Size	     */
+#  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	     */
 #else
-#  define CFG_CBSIZE		256	/* Console I/O Buffer Size	     */
+#  define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	     */
 #endif
 
 /* Print Buffer Size */
-#define CFG_PBSIZE	  (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
+#define CONFIG_SYS_PBSIZE	  (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 
-#define CFG_MAXARGS		32	/* max number of command args	*/
+#define CONFIG_SYS_MAXARGS		32	/* max number of command args	*/
 
-#define CFG_BARGSIZE		CFG_CBSIZE /* Boot Argument Buffer Size	   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	   */
 
-#define CFG_LOAD_ADDR		0x140000   /* default load address */
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_LOAD_ADDR		0x140000   /* default load address */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_MEMTEST_START	0x2000	/* memtest works from the end of */
+#define CONFIG_SYS_MEMTEST_START	0x2000	/* memtest works from the end of */
 					/* the exception vector table */
 					/* to the end of the DRAM  */
 					/* less monitor and malloc area */
-#define CFG_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
-#define CFG_MEM_END_USAGE	( CFG_MONITOR_LEN \
-				+ CFG_MALLOC_LEN \
+#define CONFIG_SYS_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
+#define CONFIG_SYS_MEM_END_USAGE	( CONFIG_SYS_MONITOR_LEN \
+				+ CONFIG_SYS_MALLOC_LEN \
 				+ CONFIG_ENV_SECT_SIZE \
-				+ CFG_STACK_USAGE )
+				+ CONFIG_SYS_STACK_USAGE )
 
-#define CFG_MEMTEST_END		( CFG_SDRAM_SIZE * 1024 * 1024 \
-				- CFG_MEM_END_USAGE )
+#define CONFIG_SYS_MEMTEST_END		( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
+				- CONFIG_SYS_MEM_END_USAGE )
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -355,7 +355,7 @@
  *  - RX clk is CLK11
  *  - TX clk is CLK12
  */
-#define CFG_CMXSCR_VALUE       (CMXSCR_RS1CS_CLK11  |\
+#define CONFIG_SYS_CMXSCR_VALUE       (CMXSCR_RS1CS_CLK11  |\
 				CMXSCR_TS1CS_CLK12)
 
 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
@@ -366,126 +366,126 @@
  * - Select bus for bd/buffers (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-#define CFG_CMXFCR_MASK		(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-#define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-#define CFG_CPMFCR_RAMTYPE	0
-#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+#define CONFIG_SYS_CMXFCR_MASK		(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 #endif	/* CONFIG_ETHER_INDEX */
 
-#define CFG_FLASH_BASE	CFG_FLASH0_BASE
-#define CFG_FLASH_SIZE	CFG_FLASH0_SIZE
-#define CFG_SDRAM_BASE	CFG_SDRAM0_BASE
-#define CFG_SDRAM_SIZE	(CFG_SDRAM0_SIZE + CFG_SDRAM1_SIZE)
+#define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_FLASH_SIZE	CONFIG_SYS_FLASH0_SIZE
+#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_SDRAM0_BASE
+#define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SYS_SDRAM0_SIZE + CONFIG_SYS_SDRAM1_SIZE)
 
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  */
-#if defined(CFG_PPMC_BOOT_LOW)
-#  define  CFG_PPMC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#if defined(CONFIG_SYS_PPMC_BOOT_LOW)
+#  define  CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 #else
-#  define  CFG_PPMC_HRCW_BOOT_FLAGS  (0)
-#endif /* defined(CFG_PPMC_BOOT_LOW) */
+#  define  CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS  (0)
+#endif /* defined(CONFIG_SYS_PPMC_BOOT_LOW) */
 
-/* get the HRCW ISB field from CFG_IMMR */
-#define CFG_PPMC_HRCW_IMMR	( ((CFG_IMMR & 0x10000000) >> 10) | \
-				  ((CFG_IMMR & 0x01000000) >>  7) | \
-				  ((CFG_IMMR & 0x00100000) >>  4) )
+/* get the HRCW ISB field from CONFIG_SYS_IMMR */
+#define CONFIG_SYS_PPMC_HRCW_IMMR	( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
+				  ((CONFIG_SYS_IMMR & 0x01000000) >>  7) | \
+				  ((CONFIG_SYS_IMMR & 0x00100000) >>  4) )
 
-#define CFG_HRCW_MASTER		( HRCW_EBM				| \
+#define CONFIG_SYS_HRCW_MASTER		( HRCW_EBM				| \
 				  HRCW_BPS11				| \
 				  HRCW_L2CPC10				| \
 				  HRCW_DPPC00				| \
-				  CFG_PPMC_HRCW_IMMR			| \
+				  CONFIG_SYS_PPMC_HRCW_IMMR			| \
 				  HRCW_MMR00				| \
 				  HRCW_LBPC00				| \
 				  HRCW_APPC10				| \
 				  HRCW_CS10PC00				| \
-				  (CFG_PPMC_MODCK_H & HRCW_MODCK_H1111) | \
-				  CFG_PPMC_HRCW_BOOT_FLAGS )
+				  (CONFIG_SYS_PPMC_MODCK_H & HRCW_MODCK_H1111) | \
+				  CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS )
 
 /* no slaves */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
  */
-#define CFG_MONITOR_BASE	CFG_FLASH0_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH0_BASE
 
-#ifndef CFG_MONITOR_BASE
-#define CFG_MONITOR_BASE	0x0ff80000
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	0x0ff80000
 #endif
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#  define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#  define CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 374 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 374 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
 
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver		*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_FLASH_INCREMENT	0	/* there is only one bank		*/
-#define CFG_FLASH_PROTECTION	1	/* use hardware protection		*/
-#define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_FLASH_INCREMENT	0	/* there is only one bank		*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware protection		*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 
 #  define CONFIG_ENV_IS_IN_FLASH	1
 #  ifdef CONFIG_ENV_IN_OWN_SECT
-#    define CONFIG_ENV_ADDR	(CFG_MONITOR_BASE + 0x40000)
+#    define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE + 0x40000)
 #    define CONFIG_ENV_SECT_SIZE	0x40000
 #  else
-#    define CONFIG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
+#    define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
 #    define CONFIG_ENV_SIZE	0x1000	/* Total Size of Environment Sector	*/
 #    define CONFIG_ENV_SECT_SIZE	0x40000 /* see README - env sect real size	*/
 #  endif /* CONFIG_ENV_IN_OWN_SECT */
 
 #else
 #  define CONFIG_ENV_IS_IN_FLASH	1
-#  define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x40000)
+#  define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
 #define CONFIG_ENV_SIZE		0x1000
 #  define CONFIG_ENV_SECT_SIZE	0x40000
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU */
 
 #if defined(CONFIG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -498,30 +498,30 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT	(HID0_ICE  |\
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE  |\
 			 HID0_DCE  |\
 			 HID0_ICFI |\
 			 HID0_DCI  |\
 			 HID0_IFEM |\
 			 HID0_ABE)
 
-#define CFG_HID0_FINAL	(HID0_ICE  |\
+#define CONFIG_SYS_HID0_FINAL	(HID0_ICE  |\
 			 HID0_IFEM |\
 			 HID0_ABE  |\
 			 HID0_EMCP)
-#define CFG_HID2	0
+#define CONFIG_SYS_HID2	0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register
  *-----------------------------------------------------------------------
  */
-#define CFG_RMR		0
+#define CONFIG_SYS_RMR		0
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration					 4-25
  *-----------------------------------------------------------------------
  */
-#define CFG_BCR		(BCR_EBM      |\
+#define CONFIG_SYS_BCR		(BCR_EBM      |\
 			 0x30000000)
 
 /*-----------------------------------------------------------------------
@@ -530,7 +530,7 @@
  *-----------------------------------------------------------------------
  */
 
-#define CFG_SIUMCR	(SIUMCR_ESE	 |\
+#define CONFIG_SYS_SIUMCR	(SIUMCR_ESE	 |\
 			 SIUMCR_DPPC00	 |\
 			 SIUMCR_L2CPC10	 |\
 			 SIUMCR_LBPC00	 |\
@@ -546,7 +546,7 @@
  *-----------------------------------------------------------------------
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
-#define CFG_SYPCR	(SYPCR_SWTC |\
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC |\
 			 SYPCR_BMT  |\
 			 SYPCR_PBME |\
 			 SYPCR_LBME |\
@@ -559,7 +559,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC	(TMCNTSC_SEC |\
+#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC |\
 			 TMCNTSC_ALR |\
 			 TMCNTSC_TCF |\
 			 TMCNTSC_TCE)
@@ -570,7 +570,7 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR	(PISCR_PS  |\
+#define CONFIG_SYS_PISCR	(PISCR_PS  |\
 			 PISCR_PTF |\
 			 PISCR_PTE)
 
@@ -578,13 +578,13 @@
  * SCCR - System Clock Control					 9-8
  *-----------------------------------------------------------------------
  */
-#define CFG_SCCR	0
+#define CONFIG_SYS_SCCR	0
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration				13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR	0
+#define CONFIG_SYS_RCCR	0
 
 /*
  * Initialize Memory Controller:
@@ -635,7 +635,7 @@
  *     - No data pipelining is done
  *     - Valid
  */
-#define CFG_BR0_PRELIM	((CFG_FLASH0_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
 			 BRx_PS_32			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
@@ -654,7 +654,7 @@
  *     - One idle clock is inserted between a read access from the
  *	 current bank and the next access.
  */
-#define CFG_OR0_PRELIM	(MEG_TO_AM(CFG_FLASH0_SIZE)	|\
+#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_5_CLK			|\
@@ -685,12 +685,12 @@
  *     - No data pipelining is done
  *     - Valid
  */
-#define CFG_BR2_PRELIM	((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
 			 BRx_PS_64			|\
 			 BRx_MS_SDRAM_P			|\
 			 BRx_V)
 
-#define CFG_BR3_PRELIM	((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
 			 BRx_PS_64			|\
 			 BRx_MS_SDRAM_P			|\
 			 BRx_V)
@@ -705,12 +705,12 @@
  *     - Internal bank interleaving within save device enabled
  */
 
-#define CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM0_SIZE)	|\
+#define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE)	|\
 			 ORxS_BPD_4			|\
 			 ORxS_ROWST_PBI0_A7		|\
 			 ORxS_NUMR_13)
 
-#define CFG_OR3_PRELIM	(MEG_TO_AM(CFG_SDRAM1_SIZE)	|\
+#define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE)	|\
 			 ORxS_BPD_4			|\
 			 ORxS_ROWST_PBI0_A7		|\
 			 ORxS_NUMR_13)
@@ -741,7 +741,7 @@
  *     - External Address Multiplexing enabled
  *     - CAS Latency is 2.
  */
-#define CFG_PSDMR	(PSDMR_RFEN	      |\
+#define CONFIG_SYS_PSDMR	(PSDMR_RFEN	      |\
 			 PSDMR_SDAM_A14_IS_A5 |\
 			 PSDMR_BSMA_A13_A15   |\
 			 PSDMR_SDA10_PBI0_A9  |\
@@ -754,8 +754,8 @@
 			 PSDMR_CL_2)
 
 
-#define CFG_PSRT	0x0e
-#define CFG_MPTPR	MPTPR_PTP_DIV32
+#define CONFIG_SYS_PSRT	0x0e
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV32
 
 
 /*-----------------------------------------------------------------------
@@ -783,7 +783,7 @@
  *
  */
 
-#define CFG_BR4_PRELIM	((CFG_SDRAM2_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR4_PRELIM	((CONFIG_SYS_SDRAM2_BASE & BRx_BA_MSK) |\
 			 BRx_PS_32			|\
 			 BRx_DECC_NONE			|\
 			 BRx_MS_SDRAM_L			|\
@@ -798,7 +798,7 @@
  *     - Internal bank interleaving within save device enabled
  */
 
-#define CFG_OR4_PRELIM	(MEG_TO_AM(CFG_SDRAM2_SIZE)	|\
+#define CONFIG_SYS_OR4_PRELIM	(MEG_TO_AM(CONFIG_SYS_SDRAM2_SIZE)	|\
 			 ORxS_BPD_4			|\
 			 ORxS_ROWST_PBI0_A10		|\
 			 ORxS_NUMR_12)
@@ -830,7 +830,7 @@
  *     - External Address Multiplexing disabled
  *     - CAS Latency is 2.
  */
-#define CFG_LSDMR	(PSDMR_RFEN	      |\
+#define CONFIG_SYS_LSDMR	(PSDMR_RFEN	      |\
 			 PSDMR_SDAM_A13_IS_A5 |\
 			 PSDMR_BSMA_A15_A17   |\
 			 PSDMR_SDA10_PBI0_A11 |\
@@ -842,7 +842,7 @@
 			 PSDMR_WRC_1C	      |\
 			 PSDMR_CL_2)
 
-#define CFG_LSRT	0x0e
+#define CONFIG_SYS_LSRT	0x0e
 
 /*-----------------------------------------------------------------------
  * BR5 - Base Register
@@ -873,7 +873,7 @@
  *     - Valid
  */
 
-#define CFG_BR5_PRELIM	((CFG_MAILBOX_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR5_PRELIM	((CONFIG_SYS_MAILBOX_BASE & BRx_BA_MSK) |\
 			 BRx_PS_8			 |\
 			 BRx_DECC_NONE			 |\
 			 BRx_MS_GPCM_P			 |\
@@ -891,7 +891,7 @@
  *	 current bank and the next access.
  */
 
-#define CFG_OR5_PRELIM ((P2SZ_TO_AM(CFG_MAILBOX_SIZE) & ~0x80000000) |\
+#define CONFIG_SYS_OR5_PRELIM ((P2SZ_TO_AM(CONFIG_SYS_MAILBOX_SIZE) & ~0x80000000) |\
 			 ORxG_ACS_DIV2				     |\
 			 ORxG_SCY_15_CLK			     |\
 			 ORxG_TRLX				     |\
@@ -921,7 +921,7 @@
  *     - No data pipelining is done
  *     - Valid
  */
-#define CFG_BR6_PRELIM	((CFG_IOSELECT_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR6_PRELIM	((CONFIG_SYS_IOSELECT_BASE & BRx_BA_MSK) |\
 			   BRx_PS_16			  |\
 			   BRx_MS_GPCM_P		  |\
 			   BRx_V)
@@ -939,7 +939,7 @@
  *	 current bank and the next access.
  */
 
-#define CFG_OR6_PRELIM (MEG_TO_AM(CFG_IOSELECT_SIZE) |\
+#define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_IOSELECT_SIZE) |\
 			 ORxG_ACS_DIV2		     |\
 			 ORxG_SCY_15_CLK	     |\
 			 ORxG_TRLX		     |\
@@ -959,7 +959,7 @@
  *  LEDs     are at 0x00001 (write only)
  *  switches are at 0x00001 (read only)
  */
-#ifdef CFG_LED_BASE
+#ifdef CONFIG_SYS_LED_BASE
 
 /* BR7 is configured as follows:
  *
@@ -973,7 +973,7 @@
  *     - No data pipelining is done
  *     - Valid
  */
-#define CFG_BR7_PRELIM	((CFG_LED_BASE & BRx_BA_MSK)	 |\
+#define CONFIG_SYS_BR7_PRELIM	((CONFIG_SYS_LED_BASE & BRx_BA_MSK)	 |\
 			   BRx_PS_8			 |\
 			   BRx_DECC_NONE		 |\
 			   BRx_MS_GPCM_P		 |\
@@ -993,13 +993,13 @@
  *     - One idle clock is inserted between a read access from the
  *	 current bank and the next access.
  */
-#define CFG_OR7_PRELIM	(ORxG_AM_MSK		       |\
+#define CONFIG_SYS_OR7_PRELIM	(ORxG_AM_MSK		       |\
 			 ORxG_CSNT		       |\
 			 ORxG_ACS_DIV1		       |\
 			 ORxG_SCY_15_CLK	       |\
 			 ORxG_TRLX		       |\
 			 ORxG_EHTR)
-#endif /* CFG_LED_BASE */
+#endif /* CONFIG_SYS_LED_BASE */
 
 /*
  * Internal Definitions
diff --git a/include/configs/purple.h b/include/configs/purple.h
index 5cc4fc7..2573aa1 100644
--- a/include/configs/purple.h
+++ b/include/configs/purple.h
@@ -43,7 +43,7 @@
 #define CONFIG_BAUDRATE		19200
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
 
@@ -99,49 +99,49 @@
 #define CONFIG_CMD_ELF
 
 
-#define CFG_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
 
-#define CFG_INIT_SP_OFFSET      0x400000
+#define CONFIG_SYS_INIT_SP_OFFSET      0x400000
 
-#define CFG_MALLOC_LEN		128*1024
+#define CONFIG_SYS_MALLOC_LEN		128*1024
 
-#define CFG_BOOTPARAMS_LEN	128*1024
+#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024
 
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory      */
-#define	CFG_PROMPT		"PURPLE # "	/* Monitor Command Prompt    */
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define CFG_MIPS_TIMER_FREQ	(CPU_CLOCK_RATE/2)
-#define CFG_HZ			1000
-#define	CFG_MAXARGS		16		/* max number of command args*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory      */
+#define	CONFIG_SYS_PROMPT		"PURPLE # "	/* Monitor Command Prompt    */
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size   */
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CPU_CLOCK_RATE/2)
+#define CONFIG_SYS_HZ			1000
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args*/
 
-#define	CFG_LOAD_ADDR		0x80500000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x80500000	/* default load address	*/
 
-#define CFG_MEMTEST_START	0x80200000
-#define CFG_MEMTEST_END		0x80800000
+#define CONFIG_SYS_MEMTEST_START	0x80200000
+#define CONFIG_SYS_MEMTEST_END		0x80800000
 
 #define	CONFIG_MISC_INIT_R
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	(35)	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	(35)	/* max number of sectors on one chip */
 
 #define PHYS_FLASH_1		0xb0000000 /* Flash Bank #1 */
 
 /* The following #defines are needed to get flash environment right */
-#define	CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MONITOR_LEN		(192 << 10)
+#define	CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(6 * CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(6 * CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(6 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(6 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 
@@ -158,16 +158,16 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		16384
-#define CFG_ICACHE_SIZE		16384
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_DCACHE_SIZE		16384
+#define CONFIG_SYS_ICACHE_SIZE		16384
+#define CONFIG_SYS_CACHELINE_SIZE	32
 
 /*
  * Temporary buffer for serial data until the real serial driver
  * is initialised (memtest will destroy this buffer)
  */
-#define CFG_SCONSOLE_ADDR     (CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET - \
-			       CFG_DCACHE_SIZE / 2)
-#define CFG_SCONSOLE_SIZE     (CFG_DCACHE_SIZE / 4)
+#define CONFIG_SYS_SCONSOLE_ADDR     (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET - \
+			       CONFIG_SYS_DCACHE_SIZE / 2)
+#define CONFIG_SYS_SCONSOLE_SIZE     (CONFIG_SYS_DCACHE_SIZE / 4)
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
index 1afff5e..d1c2c65 100644
--- a/include/configs/pxa255_idp.h
+++ b/include/configs/pxa255_idp.h
@@ -71,8 +71,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * PXA250 IDP memory map information
@@ -119,7 +119,6 @@
  */
 #include <config_cmd_default.h>
 
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_DHCP
 
@@ -219,37 +218,41 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_HUSH_PARSER		1
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
-#define CFG_LONGHELP				/* undef to save memory		*/
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT		"$ "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
 #else
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 #endif
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_DEVICE_NULLDEV	1
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1
 
-#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR		0xa0800000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0xa0800000	/* default load address */
 
-#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x161		/* set core clock to 400/200/100 MHz */
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CPUSPEED		0x161		/* set core clock to 400/200/100 MHz */
 
 #define RTC	1				/* enable 32KHz osc */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define CFG_MMC_BASE		0xF0000000
+#ifdef CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_SYS_MMC_BASE		0xF0000000
+#endif
 
 /*
  * Stack sizes
@@ -281,71 +284,71 @@
 #define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
 #define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
 
-#define CFG_DRAM_BASE		0xa0000000
-#define CFG_DRAM_SIZE		0x04000000
+#define CONFIG_SYS_DRAM_BASE		0xa0000000
+#define CONFIG_SYS_DRAM_SIZE		0x04000000
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*
  * GPIO settings
  */
 
-#define CFG_GAFR0_L_VAL	0x80001005
-#define CFG_GAFR0_U_VAL	0xa5128012
-#define CFG_GAFR1_L_VAL	0x699a9558
-#define CFG_GAFR1_U_VAL	0xaaa5aa6a
-#define CFG_GAFR2_L_VAL	0xaaaaaaaa
-#define CFG_GAFR2_U_VAL	0x2
-#define CFG_GPCR0_VAL	0x1800400
-#define CFG_GPCR1_VAL	0x0
-#define CFG_GPCR2_VAL	0x0
-#define CFG_GPDR0_VAL	0xc1818440
-#define CFG_GPDR1_VAL	0xfcffab82
-#define CFG_GPDR2_VAL	0x1ffff
-#define CFG_GPSR0_VAL	0x8000
-#define CFG_GPSR1_VAL	0x3f0002
-#define CFG_GPSR2_VAL	0x1c000
-
-#define CFG_PSSR_VAL		0x20
+#define CONFIG_SYS_GAFR0_L_VAL	0x80001005
+#define CONFIG_SYS_GAFR0_U_VAL	0xa5128012
+#define CONFIG_SYS_GAFR1_L_VAL	0x699a9558
+#define CONFIG_SYS_GAFR1_U_VAL	0xaaa5aa6a
+#define CONFIG_SYS_GAFR2_L_VAL	0xaaaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL	0x2
+#define CONFIG_SYS_GPCR0_VAL	0x1800400
+#define CONFIG_SYS_GPCR1_VAL	0x0
+#define CONFIG_SYS_GPCR2_VAL	0x0
+#define CONFIG_SYS_GPDR0_VAL	0xc1818440
+#define CONFIG_SYS_GPDR1_VAL	0xfcffab82
+#define CONFIG_SYS_GPDR2_VAL	0x1ffff
+#define CONFIG_SYS_GPSR0_VAL	0x8000
+#define CONFIG_SYS_GPSR1_VAL	0x3f0002
+#define CONFIG_SYS_GPSR2_VAL	0x1c000
+
+#define CONFIG_SYS_PSSR_VAL		0x20
 
 /*
  * Memory settings
  */
-#define CFG_MSC0_VAL		0x29DCA4D2
-#define CFG_MSC1_VAL		0x43AC494C
-#define CFG_MSC2_VAL		0x39D449D4
-#define CFG_MDCNFG_VAL		0x090009C9
-#define CFG_MDREFR_VAL		0x0085C017
-#define CFG_MDMRS_VAL		0x00220022
+#define CONFIG_SYS_MSC0_VAL		0x29DCA4D2
+#define CONFIG_SYS_MSC1_VAL		0x43AC494C
+#define CONFIG_SYS_MSC2_VAL		0x39D449D4
+#define CONFIG_SYS_MDCNFG_VAL		0x090009C9
+#define CONFIG_SYS_MDREFR_VAL		0x0085C017
+#define CONFIG_SYS_MDMRS_VAL		0x00220022
 
 /*
  * PCMCIA and CF Interfaces
  */
-#define CFG_MECR_VAL		0x00000003
-#define CFG_MCMEM0_VAL		0x00014405
-#define CFG_MCMEM1_VAL		0x00014405
-#define CFG_MCATT0_VAL		0x00014405
-#define CFG_MCATT1_VAL		0x00014405
-#define CFG_MCIO0_VAL		0x00014405
-#define CFG_MCIO1_VAL		0x00014405
+#define CONFIG_SYS_MECR_VAL		0x00000003
+#define CONFIG_SYS_MCMEM0_VAL		0x00014405
+#define CONFIG_SYS_MCMEM1_VAL		0x00014405
+#define CONFIG_SYS_MCATT0_VAL		0x00014405
+#define CONFIG_SYS_MCATT1_VAL		0x00014405
+#define CONFIG_SYS_MCIO0_VAL		0x00014405
+#define CONFIG_SYS_MCIO1_VAL		0x00014405
 
 /*
  * FLASH and environment organization
  */
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER	1
 
-#define CFG_MONITOR_BASE	0
-#define CFG_MONITOR_LEN		PHYS_FLASH_SECT_SIZE
+#define CONFIG_SYS_MONITOR_BASE	0
+#define CONFIG_SYS_MONITOR_LEN		PHYS_FLASH_SECT_SIZE
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
 
-#define CFG_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 /* put cfg at end of flash for now */
 #define CONFIG_ENV_IS_IN_FLASH	1
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index faaa889..8444462 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -41,7 +41,7 @@
 #define CONFIG_BAUDRATE		115200
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_TIMESTAMP		/* Print image info with timestamp */
 #undef CONFIG_BOOTARGS
@@ -79,78 +79,78 @@
 #define CONFIG_DRIVER_NE2000
 #define CONFIG_DRIVER_NE2000_BASE	(0xb4000300)
 
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		115200
-#define CFG_NS16550_COM1	(0xb40003f8)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		115200
+#define CONFIG_SYS_NS16550_COM1	(0xb40003f8)
 #define CONFIG_CONS_INDEX	1
 
 #define CONFIG_CMD_IDE
 #define CONFIG_DOS_PARTITION
 
-#define CFG_IDE_MAXBUS		2
-#define CFG_ATA_IDE0_OFFSET	(0x1f0)
-#define CFG_ATA_IDE1_OFFSET	(0x170)
-#define CFG_ATA_DATA_OFFSET	(0)
-#define CFG_ATA_REG_OFFSET	(0)
-#define CFG_ATA_BASE_ADDR	(0xb4000000)
+#define CONFIG_SYS_IDE_MAXBUS		2
+#define CONFIG_SYS_ATA_IDE0_OFFSET	(0x1f0)
+#define CONFIG_SYS_ATA_IDE1_OFFSET	(0x170)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0)
+#define CONFIG_SYS_ATA_REG_OFFSET	(0)
+#define CONFIG_SYS_ATA_BASE_ADDR	(0xb4000000)
 
-#define CFG_IDE_MAXDEVICE	(4)
+#define CONFIG_SYS_IDE_MAXDEVICE	(4)
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory */
 
-#define CFG_PROMPT		"qemu-mips # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT		"qemu-mips # "	/* Monitor Command Prompt */
 
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
 
-#define CFG_MALLOC_LEN		128*1024
+#define CONFIG_SYS_MALLOC_LEN		128*1024
 
-#define CFG_BOOTPARAMS_LEN	128*1024
+#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024
 
-#define CFG_MHZ			132
+#define CONFIG_SYS_MHZ			132
 
-#define CFG_MIPS_TIMER_FREQ	(CFG_MHZ * 1000000)
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
 
-#define CFG_HZ			1000
+#define CONFIG_SYS_HZ			1000
 
-#define CFG_SDRAM_BASE		0x80000000	/* Cached addr */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000	/* Cached addr */
 
-#define CFG_LOAD_ADDR		0x81000000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x81000000	/* default load address */
 
-#define CFG_MEMTEST_START	0x80100000
-#define CFG_MEMTEST_END		0x80800000
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x80800000
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
 
 /* The following #defines are needed to get flash environment right */
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(192 << 10)
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)
 
-#define CFG_INIT_SP_OFFSET	0x400000
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
 
 /* We boot from this flash, selected with dip switch */
-#define CFG_FLASH_BASE		0xbfc00000
-#define CFG_MAX_FLASH_BANKS	1
-#define CFG_MAX_FLASH_SECT	128
-#define CFG_FLASH_CFI		1	/* Flash memory is CFI compliant */
+#define CONFIG_SYS_FLASH_BASE		0xbfc00000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash memory is CFI compliant */
 #define CONFIG_FLASH_CFI_DRIVER	1
-#define CFG_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
 
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 
 /* Address and size of Primary Environment Sector */
 #define CONFIG_ENV_SIZE		0x8000
@@ -166,8 +166,8 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		16384
-#define CFG_ICACHE_SIZE		16384
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_DCACHE_SIZE		16384
+#define CONFIG_SYS_ICACHE_SIZE		16384
+#define CONFIG_SYS_CACHELINE_SIZE	32
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/qong.h b/include/configs/qong.h
new file mode 100644
index 0000000..ccc2625
--- /dev/null
+++ b/include/configs/qong.h
@@ -0,0 +1,221 @@
+/*
+ * Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
+ *
+ * Configuration settings for the Dave/DENX QongEVB-LITE board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx31-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136		1	/* This is an arm1136 CPU core */
+#define CONFIG_MX31		1	/* in a mx31 */
+#define CONFIG_QONG		1
+#define CONFIG_MX31_HCLK_FREQ	26000000	/* 26MHz */
+#define CONFIG_MX31_CLK32	32768
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MX31_UART	1
+#define CONFIG_SYS_MX31_UART1	1
+
+/* FPGA */
+#define CONFIG_QONG_FPGA	1
+#define CONFIG_FPGA_BASE	(CS1_BASE)
+
+#ifdef CONFIG_QONG_FPGA
+/* Ethernet */
+#define CONFIG_DNET		1
+#define CONFIG_DNET_BASE	(CS1_BASE + QONG_FPGA_PERIPH_SIZE)
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
+ * initial TFTP transfer, should the user wish one, significantly.
+ */
+#define CONFIG_ARP_TIMEOUT	200UL
+
+#endif /* CONFIG_QONG_FPGA */
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_JFFS2
+
+/*
+ * You can compile in a MAC address and your custom net settings by using
+ * the following syntax.
+ *
+ * #define CONFIG_ETHADDR		xx:xx:xx:xx:xx:xx
+ * #define CONFIG_SERVERIP		<server ip>
+ * #define CONFIG_IPADDR		<board ip>
+ * #define CONFIG_GATEWAYIP		<gateway ip>
+ * #define CONFIG_NETMASK		<your netmask>
+ */
+
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
+
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=ttymxc0,${baudrate}\0"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
+	"uboot_addr=a0000000\0"						\
+	"kernel_addr=a0080000\0"					\
+	"ramdisk_addr=a0300000\0"					\
+	"u-boot=qong/u-boot.bin\0"					\
+	"kernel_addr_r=80800000\0"					\
+	"hostname=qong\0"						\
+	"bootfile=qong/uImage\0"					\
+	"rootpath=/opt/eldk-4.2-arm/armVFP\0"				\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm\0"						\
+	"bootcmd=run flash_self\0"					\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE)		\
+		" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize};cp.b ${fileaddr} "			\
+		xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"		\
+	"upd=run load update\0"						\
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+		sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		32	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/* memtest works on first 255MB of RAM */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + 0xff000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_CMDLINE_EDITING	1
+
+#define CONFIG_MISC_INIT_R	1
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE
+#define PHYS_SDRAM_1_SIZE	0x10000000	/* 256 MB */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE		CS0_BASE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		0x40000		/* Reserve 256KiB */
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* Flash memory is CFI compliant */
+#define CONFIG_SYS_FLASH_CFI			1
+/* Use drivers/cfi_flash.c */
+#define CONFIG_FLASH_CFI_DRIVER			1
+/* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+/* Use hardware sector protection */
+#define CONFIG_SYS_FLASH_PROTECTION		1
+
+/*
+ * JFFS2 partitions
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT	\
+	"mtdparts=physmap-flash.0:256k(U-Boot),128k(env1),"	\
+	"128k(env2),2560k(kernel),13m(ramdisk),-(user)"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h
index 2e73ff7..3ea854b 100644
--- a/include/configs/quad100hd.h
+++ b/include/configs/quad100hd.h
@@ -45,11 +45,12 @@
 #define CONFIG_ENV_IS_IN_EEPROM
 #undef CONFIG_ENV_IS_IN_FLASH
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_NET_MULTI	1
 #define CONFIG_HAS_ETH1		1
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0x01	/* PHY address			*/
-#define CFG_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
 #define CONFIG_PHY_RESET	1
 #define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/
 
@@ -84,59 +85,59 @@
 #define CONFIG_SDRAM_BANK0  1
 
 /* FIX! SDRAM timings used in datasheet */
-#define CFG_SDRAM_CL            3       /* CAS latency */
-#define CFG_SDRAM_tRP           20      /* PRECHARGE command period */
-#define CFG_SDRAM_tRC           66      /* ACTIVE-to-ACTIVE command period */
-#define CFG_SDRAM_tRCD          20      /* ACTIVE-to-READ delay */
-#define CFG_SDRAM_tRFC          66      /* Auto refresh period */
+#define CONFIG_SYS_SDRAM_CL            3       /* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP           20      /* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC           66      /* ACTIVE-to-ACTIVE command period */
+#define CONFIG_SYS_SDRAM_tRCD          20      /* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC          66      /* Auto refresh period */
 
 /*
  * JFFS2
  */
-#define CFG_JFFS2_FIRST_BANK    0
-#ifdef  CFG_KERNEL_IN_JFFS2
-#define CFG_JFFS2_FIRST_SECTOR  0   /* JFFS starts at block 0 */
+#define CONFIG_SYS_JFFS2_FIRST_BANK    0
+#ifdef  CONFIG_SYS_KERNEL_IN_JFFS2
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR  0   /* JFFS starts at block 0 */
 #else /* kernel not in JFFS */
-#define CFG_JFFS2_FIRST_SECTOR  8   /* block 0-7 is kernel (1MB = 8 sectors) */
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR  8   /* block 0-7 is kernel (1MB = 8 sectors) */
 #endif
-#define CFG_JFFS2_NUM_BANKS     1
+#define CONFIG_SYS_JFFS2_NUM_BANKS     1
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#undef	CFG_EXT_SERIAL_CLOCK			/* external serial clock */
-#define CFG_BASE_BAUD		691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK			/* external serial clock */
+#define CONFIG_SYS_BASE_BAUD		691200
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SERIAL_MULTI
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  *----------------------------------------------------------------------*/
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
-#define CFG_EXTBDINFO		1	/* To use extended board_info (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_info (bd_t) */
 
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
+#define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
@@ -149,53 +150,53 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C		1		/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CFG_I2C_EEPROM_ADDR	0x50		/* base address */
-#define CFG_I2C_EEPROM_ADDR_LEN	2		/* bytes of address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2		/* bytes of address */
 
-#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 8 byte write page size */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-#define CFG_EEPROM_SIZE			0x2000
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 8 byte write page size */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_EEPROM_SIZE			0x2000
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFC00000
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-#define CFG_MONITOR_BASE	(TEXT_BASE)
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFC00000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	(TEXT_BASE)
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_FLASH_CFI			/* The flash is CFI compatible	*/
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
 #define	CONFIG_FLASH_CFI_DRIVER
 
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
-#define CFG_FLASH_INCREMENT      0       /* there is only one bank         */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
+#define CONFIG_SYS_FLASH_INCREMENT      0       /* there is only one bank         */
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash */
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
@@ -210,21 +211,20 @@
 #ifdef CONFIG_ENV_IS_IN_EEPROM
 #define CONFIG_ENV_SIZE		0x400		/* Size of Environment vars */
 #define CONFIG_ENV_OFFSET		0x00000000
-#define CFG_ENABLE_CRC_16	1       /* Intrinsyc formatting used crc16 */
+#define CONFIG_SYS_ENABLE_CRC_16	1       /* Intrinsyc formatting used crc16 */
 #endif
 
 /* partly from PPCBoot */
 /* NAND */
 #define CONFIG_NAND
 #ifdef CONFIG_NAND
-#define CFG_NAND_BASE   0x60000000
-#define CFG_NAND_CS	10   /* our CS is GPIO10 */
-#define CFG_NAND_RDY	23   /* our RDY is GPIO23 */
-#define CFG_NAND_CE	24   /* our CE is GPIO24  */
-#define CFG_NAND_CLE	31   /* our CLE is GPIO31 */
-#define CFG_NAND_ALE	30   /* our ALE is GPIO30 */
-#define NAND_MAX_CHIPS	1
-#define CFG_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE   0x60000000
+#define CONFIG_SYS_NAND_CS	10   /* our CS is GPIO10 */
+#define CONFIG_SYS_NAND_RDY	23   /* our RDY is GPIO23 */
+#define CONFIG_SYS_NAND_CE	24   /* our CE is GPIO24  */
+#define CONFIG_SYS_NAND_CLE	31   /* our CLE is GPIO31 */
+#define CONFIG_SYS_NAND_ALE	30   /* our ALE is GPIO30 */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
 #endif
 
 /*-----------------------------------------------------------------------
@@ -232,17 +232,17 @@
  */
 /* use on chip memory (OCM) for temperary stack until sdram is tested */
 /* see ./cpu/ppc4xx/start.S */
-#define CFG_TEMP_STACK_OCM	1
+#define CONFIG_SYS_TEMP_STACK_OCM	1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of OCM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
 
-#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
@@ -250,17 +250,17 @@
  */
 
 /* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
-#define CFG_EBC_PB0AP		0x04002480
+#define CONFIG_SYS_EBC_PB0AP		0x04002480
 /* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
-#define CFG_EBC_PB0CR		0xFFC5A000
-#define CFG_EBC_PB1AP           0x04005480
-#define CFG_EBC_PB1CR           0x60018000
-#define CFG_EBC_PB2AP           0x00000000
-#define CFG_EBC_PB2CR           0x00000000
-#define CFG_EBC_PB3AP           0x00000000
-#define CFG_EBC_PB3CR           0x00000000
-#define CFG_EBC_PB4AP           0x00000000
-#define CFG_EBC_PB4CR           0x00000000
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000
+#define CONFIG_SYS_EBC_PB1AP           0x04005480
+#define CONFIG_SYS_EBC_PB1CR           0x60018000
+#define CONFIG_SYS_EBC_PB2AP           0x00000000
+#define CONFIG_SYS_EBC_PB2CR           0x00000000
+#define CONFIG_SYS_EBC_PB3AP           0x00000000
+#define CONFIG_SYS_EBC_PB3CR           0x00000000
+#define CONFIG_SYS_EBC_PB4AP           0x00000000
+#define CONFIG_SYS_EBC_PB4CR           0x00000000
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup (PPC405EP specific)
@@ -268,14 +268,14 @@
  * Taken in part from PPCBoot board/icecube/icecube.h
  */
 /* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
-#define CFG_GPIO0_OSRH		0x55555550
-#define CFG_GPIO0_OSRL		0x00000110
-#define CFG_GPIO0_ISR1H		0x00000000
-#define CFG_GPIO0_ISR1L		0x15555445
-#define CFG_GPIO0_TSRH		0x00000000
-#define CFG_GPIO0_TSRL		0x00000000
-#define CFG_GPIO0_TCR		0xFFFF8097
-#define CFG_GPIO0_ODR		0x00000000
+#define CONFIG_SYS_GPIO0_OSRH		0x55555550
+#define CONFIG_SYS_GPIO0_OSRL		0x00000110
+#define CONFIG_SYS_GPIO0_ISR1H		0x00000000
+#define CONFIG_SYS_GPIO0_ISR1L		0x15555445
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0xFFFF8097
+#define CONFIG_SYS_GPIO0_ODR		0x00000000
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
diff --git a/include/configs/quantum.h b/include/configs/quantum.h
index f264615..e440e93 100644
--- a/include/configs/quantum.h
+++ b/include/configs/quantum.h
@@ -72,10 +72,10 @@
 /*
  * Select the more full-featured memory test (Barr embedded systems)
  */
-#define CFG_ALT_MEMTEST
+#define CONFIG_SYS_ALT_MEMTEST
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 
 /* M48T02 Paralled access timekeeper with same interface as the M48T35A*/
@@ -88,8 +88,8 @@
 #endif
 
 /*  NVRAM and RTC */
-#define CFG_NVRAM_BASE_ADDR 0xFA000000
-#define CFG_NVRAM_SIZE 2048
+#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA000000
+#define CONFIG_SYS_NVRAM_SIZE 2048
 
 
 /*
@@ -122,25 +122,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00040000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x01f00000	/* 256K ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00040000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x01f00000	/* 256K ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -150,24 +150,24 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFA200000
+#define CONFIG_SYS_IMMR		0xFA200000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE	0xFF000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE	0xFF000000
 
 #if 1
     #define CONFIG_FLASH_CFI_DRIVER
@@ -177,42 +177,42 @@
 
 
 #ifdef CONFIG_FLASH_CFI_DRIVER
-    #define CFG_FLASH_CFI 1
-    #undef CFG_FLASH_USE_BUFFER_WRITE
-    #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
+    #define CONFIG_SYS_FLASH_CFI 1
+    #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+    #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
 #endif
 
-/*%%% #define CFG_FLASH_BASE		0xFFF00000 */
+/*%%% #define CONFIG_SYS_FLASH_BASE		0xFFF00000 */
 #if defined(DEBUG) || defined(CONFIG_CMD_IDE)
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	0xFFF00000
-/*%%% #define CFG_MONITOR_BASE	CFG_FLASH_BASE */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	0xFFF00000
+/*%%% #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET	    0x00F40000	/*   Offset   of Environment Sector	absolute address 0xfff40000*/
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* Total Size of Environment Sector	*/
 #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 
 /* Address and size of Redundant Environment Sector	*/
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
@@ -220,21 +220,21 @@
 
 /* FPGA */
 #define CONFIG_MISC_INIT_R
-#define CFG_FPGA_SPARTAN2
-#define CFG_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_SPARTAN2
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
 
 
 /*-----------------------------------------------------------------------
  * Reset address
  */
-#define CFG_RESET_ADDRESS	((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
+#define CONFIG_SYS_RESET_ADDRESS	((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -244,10 +244,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -255,28 +255,28 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_MLRC10)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_MLRC10)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-/*%%%#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_RTE)
+/*%%%#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -287,7 +287,7 @@
  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  */
 /* up to 50 MHz we use a 1:1 clock */
-#define CFG_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
+#define CONFIG_SYS_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -297,21 +297,21 @@
  */
 #define SCCR_MASK	SCCR_EBDF00
 /* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_COM00 | SCCR_TBS)
+#define CONFIG_SYS_SCCR	(SCCR_COM00 | SCCR_TBS)
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -324,29 +324,29 @@
 #undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-/*#define	CFG_DER 0x2002000F*/
-#define CFG_DER 0
+/*#define	CONFIG_SYS_DER 0x2002000F*/
+#define CONFIG_SYS_DER 0
 
 /*
  * Init Memory Controller:
@@ -355,13 +355,13 @@
  */
 
 #define FLASH_BASE_PRELIM	0xFE000000	/* FLASH base */
-#define CFG_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
 
 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
-#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
+#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
 
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
 
 /*
  * BR1 and OR1 (SDRAM)
@@ -371,36 +371,36 @@
 #define SDRAM_MAX_SIZE		0x08000000	/* max 128 MB */
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000E00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000E00
 
-#define CFG_OR1_PRELIM	(0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */
-#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR1_PRELIM	(0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */
+#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /* RPXLITE mem setting */
-#define CFG_BR3_PRELIM	0xFA400001		/* FPGA */
-#define CFG_OR3_PRELIM	0xFFFF8910
+#define CONFIG_SYS_BR3_PRELIM	0xFA400001		/* FPGA */
+#define CONFIG_SYS_OR3_PRELIM	0xFFFF8910
 
-#define CFG_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
-#define CFG_OR4_PRELIM	0xFFFE0970
+#define CONFIG_SYS_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
+#define CONFIG_SYS_OR4_PRELIM	0xFFFE0970
 
 /*
  * Memory Periodic Timer Prescaler
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	20
+#define CONFIG_SYS_MAMR_PTA	20
 
 /*
  * Refresh clock Prescalar
  */
-#define CFG_MPTPR	MPTPR_PTP_DIV2
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV2
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
 
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index 41a2a15..6921759 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -36,66 +36,66 @@
 #define CONFIG_ENV_OVERWRITE	1
 
 /* SDRAM */
-#define CFG_SDRAM_BASE		(0x8C000000)
-#define CFG_SDRAM_SIZE		(0x04000000)
-
-#define CFG_LONGHELP
-#define CFG_PROMPT		"=> "
-#define CFG_CBSIZE		256
-#define CFG_PBSIZE		256
-#define CFG_MAXARGS		16
-#define CFG_BARGSIZE		512
+#define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
+#define CONFIG_SYS_SDRAM_SIZE		(0x04000000)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
 /* List of legal baudrate settings for this board */
-#define CFG_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
 
-#define CFG_MEMTEST_START	(CFG_SDRAM_BASE)
-#define CFG_MEMTEST_END		(TEXT_BASE - 0x100000)
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(TEXT_BASE - 0x100000)
 
-#define CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 32 * 1024 * 1024)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
 /* Address of u-boot image in Flash */
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE)
-#define CFG_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
 /* Size of DRAM reserved for malloc() use */
-#define CFG_MALLOC_LEN		(1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_SIZE	(256)
-#define CFG_BOOTMAPSZ		(8 * 1024 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	(256)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 
 /*
  * NOR Flash ( Spantion S29GL256P )
  */
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_BASE		(0xA0000000)
-#define CFG_MAX_FLASH_BANKS (1)
-#define CFG_MAX_FLASH_SECT  256
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
+#define CONFIG_SYS_MAX_FLASH_BANKS (1)
+#define CONFIG_SYS_MAX_FLASH_SECT  256
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x40000
 #define CONFIG_ENV_SIZE        (CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR        (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 
 /*
  * SuperH Clock setting
  */
 #define CONFIG_SYS_CLK_FREQ	60000000
 #define TMU_CLK_DIVIDER		4
-#define CFG_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
-#define	CFG_PLL_SETTLING_TIME	100/* in us */
+#define CONFIG_SYS_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define	CONFIG_SYS_PLL_SETTLING_TIME	100/* in us */
 
 /*
  * IDE support
  */
 #define CONFIG_IDE_RESET	1
-#define CFG_PIO_MODE		1
-#define CFG_IDE_MAXBUS		1 /* IDE bus */
-#define CFG_IDE_MAXDEVICE	1
-#define CFG_ATA_BASE_ADDR	0xb4000000
-#define CFG_ATA_STRIDE		2 /* 1bit shift */
-#define CFG_ATA_DATA_OFFSET	0x1000	/* data reg offset */
-#define CFG_ATA_REG_OFFSET	0x1000	/* reg offset */
-#define CFG_ATA_ALT_OFFSET	0x800	/* alternate register offset */
+#define CONFIG_SYS_PIO_MODE		1
+#define CONFIG_SYS_IDE_MAXBUS		1 /* IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_BASE_ADDR	0xb4000000
+#define CONFIG_SYS_ATA_STRIDE		2 /* 1bit shift */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x1000	/* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x1000	/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x800	/* alternate register offset */
 
 /*
  * SuperH PCI Bridge Configration
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
index 4f3f8e5..72a3b5c 100644
--- a/include/configs/r7780mp.h
+++ b/include/configs/r7780mp.h
@@ -31,7 +31,7 @@
 #define CONFIG_SH4A		1
 #define CONFIG_CPU_SH7780	1
 #define CONFIG_R7780MP		1
-#define CFG_R7780MP_OLD_FLASH	1
+#define CONFIG_SYS_R7780MP_OLD_FLASH	1
 #define __LITTLE_ENDIAN__ 1
 
 /*
@@ -43,7 +43,7 @@
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_EXT2
@@ -60,69 +60,69 @@
 /* check for keypress on bootdelay==0 */
 /*#define CONFIG_ZERO_BOOTDELAY_CHECK*/
 
-#define CFG_SDRAM_BASE		(0x08000000)
-#define CFG_SDRAM_SIZE		(128 * 1024 * 1024)
+#define CONFIG_SYS_SDRAM_BASE		(0x08000000)
+#define CONFIG_SYS_SDRAM_SIZE		(128 * 1024 * 1024)
 
-#define CFG_LONGHELP
-#define CFG_PROMPT		"=> "
-#define CFG_CBSIZE		256
-#define CFG_PBSIZE		256
-#define CFG_MAXARGS		16
-#define CFG_BARGSIZE	512
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE	512
 /* List of legal baudrate settings for this board */
-#define CFG_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
 
-#define CFG_MEMTEST_START	(CFG_SDRAM_BASE)
-#define CFG_MEMTEST_END		(TEXT_BASE - 0x100000)
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(TEXT_BASE - 0x100000)
 
 /* Flash board support */
-#define CFG_FLASH_BASE		(0xA0000000)
-#ifdef CFG_R7780MP_OLD_FLASH
+#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
+#ifdef CONFIG_SYS_R7780MP_OLD_FLASH
 /* NOR Flash (S29PL127J60TFI130) */
-# define CFG_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
-# define CFG_MAX_FLASH_BANKS	(2)
-# define CFG_MAX_FLASH_SECT	270
-# define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE,\
-				CFG_FLASH_BASE + 0x100000,\
-				CFG_FLASH_BASE + 0x400000,\
-				CFG_FLASH_BASE + 0x700000, }
-#else /* CFG_R7780MP_OLD_FLASH */
+# define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
+# define CONFIG_SYS_MAX_FLASH_BANKS	(2)
+# define CONFIG_SYS_MAX_FLASH_SECT	270
+# define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
+				CONFIG_SYS_FLASH_BASE + 0x100000,\
+				CONFIG_SYS_FLASH_BASE + 0x400000,\
+				CONFIG_SYS_FLASH_BASE + 0x700000, }
+#else /* CONFIG_SYS_R7780MP_OLD_FLASH */
 /* NOR Flash (Spantion S29GL256P) */
-# define CFG_MAX_FLASH_BANKS	(1)
-# define CFG_MAX_FLASH_SECT		256
-# define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
-#endif /* CFG_R7780MP_OLD_FLASH */
+# define CONFIG_SYS_MAX_FLASH_BANKS	(1)
+# define CONFIG_SYS_MAX_FLASH_SECT		256
+# define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#endif /* CONFIG_SYS_R7780MP_OLD_FLASH */
 
-#define CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 4 * 1024 * 1024)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
 /* Address of u-boot image in Flash */
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE)
-#define CFG_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
 /* Size of DRAM reserved for malloc() use */
-#define CFG_MALLOC_LEN		(1204 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1204 * 1024)
 
 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_SIZE	(256)
-#define CFG_BOOTMAPSZ		(8 * 1024 * 1024)
-#define CFG_RX_ETH_BUFFER	(8)
+#define CONFIG_SYS_GBL_DATA_SIZE	(256)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+#define CONFIG_SYS_RX_ETH_BUFFER	(8)
 
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#undef CFG_FLASH_CFI_BROKEN_TABLE
-#undef  CFG_FLASH_QUIET_TEST
+#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
 /* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	(256 * 1024)
 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_FLASH_ERASE_TOUT	120000
-#define CFG_FLASH_WRITE_TOUT	500
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
 #define TMU_CLK_DIVIDER		4
-#define CFG_HZ	(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_HZ	(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
 
 /* PCI Controller */
 #if defined(CONFIG_CMD_PCI)
@@ -157,14 +157,14 @@
 /* Compact flash Support */
 #if defined(CONFIG_CMD_IDE)
 #define CONFIG_IDE_RESET        1
-#define CFG_PIO_MODE            1
-#define CFG_IDE_MAXBUS          1   /* IDE bus */
-#define CFG_IDE_MAXDEVICE       1
-#define CFG_ATA_BASE_ADDR       0xb4000000
-#define CFG_ATA_STRIDE          2               /* 1bit shift */
-#define CFG_ATA_DATA_OFFSET     0x1000          /* data reg offset */
-#define CFG_ATA_REG_OFFSET      0x1000          /* reg offset */
-#define CFG_ATA_ALT_OFFSET      0x800           /* alternate register offset */
+#define CONFIG_SYS_PIO_MODE            1
+#define CONFIG_SYS_IDE_MAXBUS          1   /* IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE       1
+#define CONFIG_SYS_ATA_BASE_ADDR       0xb4000000
+#define CONFIG_SYS_ATA_STRIDE          2               /* 1bit shift */
+#define CONFIG_SYS_ATA_DATA_OFFSET     0x1000          /* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET      0x1000          /* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET      0x800           /* alternate register offset */
 #endif /* CONFIG_CMD_IDE */
 
 #endif /* __R7780RP_H */
diff --git a/include/configs/redwood.h b/include/configs/redwood.h
index dac323b..4b744a7 100644
--- a/include/configs/redwood.h
+++ b/include/configs/redwood.h
@@ -46,49 +46,49 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE		0xfff00000	/* start of FLASH	*/
-#define CFG_PERIPHERAL_BASE	0xa0000000	/* internal peripherals	*/
-#define CFG_ISRAM_BASE		0x90000000	/* internal SRAM	*/
+#define CONFIG_SYS_FLASH_BASE		0xfff00000	/* start of FLASH	*/
+#define CONFIG_SYS_PERIPHERAL_BASE	0xa0000000	/* internal peripherals	*/
+#define CONFIG_SYS_ISRAM_BASE		0x90000000	/* internal SRAM	*/
 
-#define CFG_PCI_BASE		0xd0000000	/* internal PCI regs	*/
+#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs	*/
 
-#define CFG_PCIE_MEMBASE	0x90000000	/* mapped PCIe memory	*/
-#define CFG_PCIE0_MEMBASE	0x90000000	/* mapped PCIe memory	*/
-#define CFG_PCIE1_MEMBASE	0xa0000000	/* mapped PCIe memory	*/
-#define CFG_PCIE_MEMSIZE	0x01000000
+#define CONFIG_SYS_PCIE_MEMBASE	0x90000000	/* mapped PCIe memory	*/
+#define CONFIG_SYS_PCIE0_MEMBASE	0x90000000	/* mapped PCIe memory	*/
+#define CONFIG_SYS_PCIE1_MEMBASE	0xa0000000	/* mapped PCIe memory	*/
+#define CONFIG_SYS_PCIE_MEMSIZE	0x01000000
 
-#define CFG_PCIE0_XCFGBASE	0xb0000000
-#define CFG_PCIE1_XCFGBASE	0xb2000000
-#define CFG_PCIE2_XCFGBASE	0xb4000000
-#define CFG_PCIE0_CFGBASE	0xb6000000
-#define CFG_PCIE1_CFGBASE	0xb8000000
-#define CFG_PCIE2_CFGBASE	0xba000000
+#define CONFIG_SYS_PCIE0_XCFGBASE	0xb0000000
+#define CONFIG_SYS_PCIE1_XCFGBASE	0xb2000000
+#define CONFIG_SYS_PCIE2_XCFGBASE	0xb4000000
+#define CONFIG_SYS_PCIE0_CFGBASE	0xb6000000
+#define CONFIG_SYS_PCIE1_CFGBASE	0xb8000000
+#define CONFIG_SYS_PCIE2_CFGBASE	0xba000000
 
 /* PCIe mapped UTL registers */
-#define CFG_PCIE0_REGBASE   0xd0000000
-#define CFG_PCIE1_REGBASE   0xd0010000
-#define CFG_PCIE2_REGBASE   0xd0020000
+#define CONFIG_SYS_PCIE0_REGBASE   0xd0000000
+#define CONFIG_SYS_PCIE1_REGBASE   0xd0010000
+#define CONFIG_SYS_PCIE2_REGBASE   0xd0020000
 
 /* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
 
-#define CFG_FPGA_BASE		0xe2000000	/* epld			*/
-#define CFG_OPER_FLASH		0xe7000000	/* SRAM - OPER Flash	*/
+#define CONFIG_SYS_FPGA_BASE		0xe2000000	/* epld			*/
+#define CONFIG_SYS_OPER_FLASH		0xe7000000	/* SRAM - OPER Flash	*/
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
-#define CFG_TEMP_STACK_OCM	1
-#define CFG_OCM_DATA_ADDR	CFG_ISRAM_BASE
-#define CFG_INIT_RAM_ADDR	CFG_ISRAM_BASE	/* Initial RAM address	*/
-#define CFG_INIT_RAM_END	0x2000		/* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_END	0x2000		/* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
 
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_POST_WORD_ADDR
 
 /*-----------------------------------------------------------------------
  * DDR SDRAM
@@ -96,7 +96,7 @@
 #define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
 #define CONFIG_DDR_ECC		1	/* with ECC support		*/
 
-#define CFG_SPD_MAX_DIMMS	2
+#define CONFIG_SYS_SPD_MAX_DIMMS	2
 
 /* SPD i2c spd addresses */
 #define SPD_EEPROM_ADDRESS     {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR}
@@ -106,15 +106,15 @@
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CFG_I2C_SPEED		400000	/* I2C speed			*/
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed			*/
 
 #define IIC0_BOOTPROM_ADDR	0x50
 #define IIC0_ALT_BOOTPROM_ADDR	0x54
 
 /* Don't probe these addrs */
-#define CFG_I2C_NOPROBES	{0x50, 0x52, 0x53, 0x54}
+#define CONFIG_SYS_I2C_NOPROBES	{0x50, 0x52, 0x53, 0x54}
 
-#define CFG_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
 
 /*-----------------------------------------------------------------------
  * Environment
@@ -164,16 +164,16 @@
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI			/* The flash is CFI compatible	*/
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
-#define CFG_FLASH_CFI_AMD_RESET 1	/* Use AMD (Spansion) reset cmd */
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1	/* Use AMD (Spansion) reset cmd */
 
-#define CFG_MAX_FLASH_BANKS	3	/* number of banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* sectors per device		*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* number of banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* sectors per device		*/
 
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
diff --git a/include/configs/rmu.h b/include/configs/rmu.h
index 0c0b206..d88ae81 100644
--- a/include/configs/rmu.h
+++ b/include/configs/rmu.h
@@ -57,14 +57,14 @@
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 /* enable I2C and select the hardware/software driver */
 #undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
 
-#define CFG_I2C_SPEED		40000	/* 40 kHz is supposed to work	*/
-#define CFG_I2C_SLAVE		0xFE
+#define CONFIG_SYS_I2C_SPEED		40000	/* 40 kHz is supposed to work	*/
+#define CONFIG_SYS_I2C_SLAVE		0xFE
 
 /* Software (bit-bang) I2C driver configuration */
 #define PB_SCL		0x00000020	/* PB 26 */
@@ -82,8 +82,8 @@
 
 /* M41T11 Serial Access Timekeeper(R) SRAM */
 #define CONFIG_RTC_M41T11 1
-#define CFG_I2C_RTC_ADDR 0x68
-#define CFG_M41T11_BASE_YEAR 1900	/* play along with the linux driver */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 1900	/* play along with the linux driver */
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -118,25 +118,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0040000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00C0000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0040000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00C0000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -146,47 +146,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFA200000
+#define CONFIG_SYS_IMMR		0xFA200000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		(0-flash_info[0].size)	/* Put flash at end	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		(0-flash_info[0].size)	/* Put flash at end	*/
 #if defined(DEBUG) || defined(CONFIG_CMD_IDE)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		((TEXT_BASE) + 0x40000)
@@ -199,14 +199,14 @@
 /*-----------------------------------------------------------------------
  * Reset address
  */
-#define	CFG_RESET_ADDRESS	((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
+#define	CONFIG_SYS_RESET_ADDRESS	((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -216,10 +216,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -227,28 +227,28 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_MLRC10)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_MLRC10)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-/*%%%#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_RTE)
+/*%%%#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -259,7 +259,7 @@
  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  */
 /* up to 50 MHz we use a 1:1 clock */
-#define CFG_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
+#define CONFIG_SYS_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -269,21 +269,21 @@
  */
 #define SCCR_MASK	SCCR_EBDF00
 /* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_COM00 | SCCR_TBS)
+#define CONFIG_SYS_SCCR	(SCCR_COM00 | SCCR_TBS)
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -296,29 +296,29 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -327,13 +327,13 @@
  */
 
 #define FLASH_BASE_PRELIM	0xFC000000	/* FLASH base - up to 64 MB of flash */
-#define CFG_PRELIM_OR_AM	0xFC000000	/* OR addr mask - map 64 MB */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFC000000	/* OR addr mask - map 64 MB */
 
 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
-#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
+#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
 
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
 
 /*
  * BR1 and OR1 (SDRAM)
@@ -343,39 +343,39 @@
 #define	SDRAM_MAX_SIZE		0x08000000	/* max 128 MB */
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000E00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000E00
 
-#define CFG_OR1_PRELIM	(0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */
-#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR1_PRELIM	(0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */
+#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /* RPXLITE mem setting */
-#define CFG_NVRAM_BASE	0xFA000000		/* NVRAM & SRAM base */
+#define CONFIG_SYS_NVRAM_BASE	0xFA000000		/* NVRAM & SRAM base */
 /*      IMMR:		0xFA200000		   IMMR base address - see above */
-#define	CFG_BCSR_BASE	0xFA400000		/* BCSR base address */
+#define	CONFIG_SYS_BCSR_BASE	0xFA400000		/* BCSR base address */
 
-#define	CFG_BR3_PRELIM	(CFG_BCSR_BASE | BR_V)			/* BCSR */
-#define CFG_OR3_PRELIM	0xFFFF8910
-#define CFG_BR4_PRELIM  (CFG_NVRAM_BASE | BR_PS_8 | BR_V)	/* NVRAM & SRAM */
-#define CFG_OR4_PRELIM	0xFFFE0970
+#define	CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_BCSR_BASE | BR_V)			/* BCSR */
+#define CONFIG_SYS_OR3_PRELIM	0xFFFF8910
+#define CONFIG_SYS_BR4_PRELIM  (CONFIG_SYS_NVRAM_BASE | BR_PS_8 | BR_V)	/* NVRAM & SRAM */
+#define CONFIG_SYS_OR4_PRELIM	0xFFFE0970
 
 /*
  * Memory Periodic Timer Prescaler
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	20
+#define CONFIG_SYS_MAMR_PTA	20
 
 /*
  * Refresh clock Prescalar
  */
-#define CFG_MPTPR	MPTPR_PTP_DIV2
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV2
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
 
@@ -394,10 +394,10 @@
  *
  */
 
-#define BCSR0	(CFG_BCSR_BASE + 0)
-#define BCSR1	(CFG_BCSR_BASE + 1)
-#define BCSR2	(CFG_BCSR_BASE + 2)
-#define BCSR3	(CFG_BCSR_BASE + 3)
+#define BCSR0	(CONFIG_SYS_BCSR_BASE + 0)
+#define BCSR1	(CONFIG_SYS_BCSR_BASE + 1)
+#define BCSR2	(CONFIG_SYS_BCSR_BASE + 2)
+#define BCSR3	(CONFIG_SYS_BCSR_BASE + 3)
 
 #define BCSR0_ENMONXCVR	0x01	/* Monitor XVCR Control */
 #define BCSR0_ENNVRAM	0x02	/* CS4# Control */
diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h
index 09913a9..8207844 100644
--- a/include/configs/rsdproto.h
+++ b/include/configs/rsdproto.h
@@ -79,10 +79,10 @@
  * - Select bus for bd/buffers (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	(0)
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	(0)
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 
 #endif /* CONFIG_ETHER_INDEX */
 
@@ -92,8 +92,8 @@
 
 /* enable I2C */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_SPEED		50000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x30
+#define CONFIG_SYS_I2C_SPEED		50000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x30
 
 
 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
@@ -125,7 +125,7 @@
  * way to do that is to program the bootloader at both addresses.
  * It is suggested that you just let U-Boot live at 0x00000000.
  */
-#define CFG_RSD_BOOT_LOW 1
+#define CONFIG_SYS_RSD_BOOT_LOW 1
 
 #define CONFIG_BOOTDELAY	5
 #define CONFIG_BOOTARGS		"devfs=mount root=ramfs"
@@ -140,26 +140,26 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ			1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks	*/
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -199,94 +199,94 @@
 #define PHYS_FLASH		0xFF000000 /* Flash (60x Bus) */
 #define PHYS_FLASH_SIZE		0x01000000 /* 16 MB */
 
-#define CFG_IMMR		PHYS_IMMR
+#define CONFIG_SYS_IMMR		PHYS_IMMR
 
 /*-----------------------------------------------------------------------
  * Reset Address
  *
  * In order to reset the CPU, U-Boot jumps to a special address which
  * causes a machine check exception. The default address for this is
- * CFG_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when
+ * CONFIG_SYS_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when
  * testing the monitor in RAM using a JTAG debugger.
  *
- * Just set CFG_RESET_ADDRESS to an address that you know is sure to
+ * Just set CONFIG_SYS_RESET_ADDRESS to an address that you know is sure to
  * cause a bus error on your hardware.
  */
-#define CFG_RESET_ADDRESS	0x20000000
+#define CONFIG_SYS_RESET_ADDRESS	0x20000000
 
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  */
 
-#if defined(CFG_RSD_BOOT_LOW)
-#  define  CFG_RSD_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#if defined(CONFIG_SYS_RSD_BOOT_LOW)
+#  define  CONFIG_SYS_RSD_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 #else
-#  define  CFG_RSD_HRCW_BOOT_FLAGS  (0)
-#endif /* defined(CFG_RSD_BOOT_LOW) */
+#  define  CONFIG_SYS_RSD_HRCW_BOOT_FLAGS  (0)
+#endif /* defined(CONFIG_SYS_RSD_BOOT_LOW) */
 
-/* get the HRCW ISB field from CFG_IMMR */
-#define CFG_RSD_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
-			    ((CFG_IMMR & 0x01000000) >> 7)  |\
-			    ((CFG_IMMR & 0x00100000) >> 4) )
+/* get the HRCW ISB field from CONFIG_SYS_IMMR */
+#define CONFIG_SYS_RSD_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\
+			    ((CONFIG_SYS_IMMR & 0x01000000) >> 7)  |\
+			    ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
 
-#define CFG_HRCW_MASTER	(HRCW_L2CPC10 | \
+#define CONFIG_SYS_HRCW_MASTER	(HRCW_L2CPC10 | \
 			 HRCW_DPPC11 | \
-			 CFG_RSD_HRCW_IMMR |\
+			 CONFIG_SYS_RSD_HRCW_IMMR |\
 			 HRCW_MMR00 | \
 			 HRCW_APPC10 | \
 			 HRCW_CS10PC00 | \
 			 HRCW_MODCK_H0000 |\
-			 CFG_RSD_HRCW_BOOT_FLAGS)
+			 CONFIG_SYS_RSD_HRCW_BOOT_FLAGS)
 
 /* no slaves */
-#define CFG_HRCW_SLAVE1	0
-#define CFG_HRCW_SLAVE2	0
-#define CFG_HRCW_SLAVE3	0
-#define CFG_HRCW_SLAVE4	0
-#define CFG_HRCW_SLAVE5	0
-#define CFG_HRCW_SLAVE6	0
-#define CFG_HRCW_SLAVE7	0
+#define CONFIG_SYS_HRCW_SLAVE1	0
+#define CONFIG_SYS_HRCW_SLAVE2	0
+#define CONFIG_SYS_HRCW_SLAVE3	0
+#define CONFIG_SYS_HRCW_SLAVE4	0
+#define CONFIG_SYS_HRCW_SLAVE5	0
+#define CONFIG_SYS_HRCW_SLAVE6	0
+#define CONFIG_SYS_HRCW_SLAVE7	0
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CFG_RAMBOOT is platform dependend.
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependend.
  */
-#define	CFG_SDRAM_BASE		PHYS_SDRAM_60X
-#define CFG_FLASH_BASE		PHYS_FLASH
-/*#define	CFG_MONITOR_BASE	0x200000 */
-#define	CFG_MONITOR_BASE	CFG_FLASH_BASE
-#if CFG_MONITOR_BASE < CFG_FLASH_BASE
-#define CFG_RAMBOOT
+#define	CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_60X
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH
+/*#define	CONFIG_SYS_MONITOR_BASE	0x200000 */
+#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_RAMBOOT
 #endif
-#define	CFG_MONITOR_LEN		(160 << 10)	/* Reserve 160 kB for Monitor	*/
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_MONITOR_LEN		(160 << 10)	/* Reserve 160 kB for Monitor	*/
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	63	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	63	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	12000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	3000	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	12000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	3000	/* Timeout for Flash Write (in ms)	*/
 
 /* turn off NVRAM env feature */
 #undef CONFIG_NVRAM_ENV
@@ -298,9 +298,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU			*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -313,28 +313,28 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP)
-#define CFG_HID2	0
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP)
+#define CONFIG_SYS_HID2	0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register
  *-----------------------------------------------------------------------
  */
-#define CFG_RMR		0
+#define CONFIG_SYS_RMR		0
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration					 4-25
  *-----------------------------------------------------------------------
  */
-#define CFG_BCR		0x100c0000
+#define CONFIG_SYS_BCR		0x100c0000
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration				 4-31
  *-----------------------------------------------------------------------
  */
 
-#define CFG_SIUMCR	(SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \
 					 SIUMCR_CS10PC01 | SIUMCR_BCTLC01)
 
 /*-----------------------------------------------------------------------
@@ -343,7 +343,7 @@
  *-----------------------------------------------------------------------
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \
 			 SYPCR_SWRI | SYPCR_SWP)
 
 /*-----------------------------------------------------------------------
@@ -352,7 +352,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC	(TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		 4-42
@@ -360,63 +360,63 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control					 9-8
  *-----------------------------------------------------------------------
  */
-#define CFG_SCCR	0x00000000
+#define CONFIG_SYS_SCCR	0x00000000
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration				13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR	0
+#define CONFIG_SYS_RCCR	0
 
 /*
  * Init Memory Controller:
  */
 
-#define CFG_PSDMR	0x494D2452
-#define CFG_LSDMR	0x49492552
+#define CONFIG_SYS_PSDMR	0x494D2452
+#define CONFIG_SYS_LSDMR	0x49492552
 
 /* Flash */
-#define CFG_BR0_PRELIM	(PHYS_FLASH | BRx_V)
-#define CFG_OR0_PRELIM	(P2SZ_TO_AM(PHYS_FLASH_SIZE) | \
+#define CONFIG_SYS_BR0_PRELIM	(PHYS_FLASH | BRx_V)
+#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(PHYS_FLASH_SIZE) | \
 			 ORxG_BCTLD | \
 			 ORxG_SCY_5_CLK)
 
 /* DPRAM to the PCI BUS on the protocol board */
-#define CFG_BR1_PRELIM	(PHYS_DPRAM_PCI | BRx_V)
-#define CFG_OR1_PRELIM	(P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \
+#define CONFIG_SYS_BR1_PRELIM	(PHYS_DPRAM_PCI | BRx_V)
+#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \
 			 ORxG_ACS_DIV4)
 
 /* 60x Bus SDRAM */
-#define CFG_BR2_PRELIM	(PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V)
-#define CFG_OR2_PRELIM	(ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \
+#define CONFIG_SYS_BR2_PRELIM	(PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V)
+#define CONFIG_SYS_OR2_PRELIM	(ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \
 			 ORxS_BPD_4 | \
 			 ORxS_ROWST_PBI1_A2 | \
 			 ORxS_NUMR_13 | \
 			 ORxS_IBID)
 
 /* Virtex-FPGA - Register */
-#define CFG_BR3_PRELIM  (PHYS_VIRTEX_REGISTER | BRx_V)
-#define CFG_OR3_PRELIM  (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \
+#define CONFIG_SYS_BR3_PRELIM  (PHYS_VIRTEX_REGISTER | BRx_V)
+#define CONFIG_SYS_OR3_PRELIM  (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \
 			 ORxG_SCY_1_CLK | \
 			 ORxG_ACS_DIV2 | \
 			 ORxG_CSNT )
 
 /* local bus SDRAM */
-#define CFG_BR4_PRELIM	(PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V)
-#define CFG_OR4_PRELIM	(ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \
+#define CONFIG_SYS_BR4_PRELIM	(PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V)
+#define CONFIG_SYS_OR4_PRELIM	(ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \
 			 ORxS_BPD_4 | \
 			 ORxS_ROWST_PBI1_A4 | \
 			 ORxS_NUMR_13)
 
 /* DPRAM to the Sharc-Bus on the protocol board */
-#define CFG_BR5_PRELIM	(PHYS_DPRAM_SHARC | BRx_V)
-#define CFG_OR5_PRELIM	(P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \
+#define CONFIG_SYS_BR5_PRELIM	(PHYS_DPRAM_SHARC | BRx_V)
+#define CONFIG_SYS_OR5_PRELIM	(P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \
 			 ORxG_ACS_DIV4)
 
 /*
diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h
index d99e4f3..36e4c01 100644
--- a/include/configs/rsk7203.h
+++ b/include/configs/rsk7203.h
@@ -37,7 +37,7 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_CACHE
@@ -54,54 +54,59 @@
 #define RSK7203_FLASH_BASE_1	0x20000000	/* Non cache */
 #define RSK7203_FLASH_BANK_SIZE	(4 * 1024 * 1024)
 
-#define CFG_LONGHELP		/* undef to save memory	*/
-#define CFG_PROMPT	"=> "	/* Monitor Command Prompt */
-#define CFG_CBSIZE	256	/* Buffer size for input from the Console */
-#define CFG_PBSIZE	256	/* Buffer size for Console output */
-#define CFG_MAXARGS	16	/* max args accepted for monitor commands */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
+#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256	/* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE	256	/* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS	16	/* max args accepted for monitor commands */
 /* Buffer size for Boot Arguments passed to kernel */
-#define CFG_BARGSIZE	512
+#define CONFIG_SYS_BARGSIZE	512
 /* List of legal baudrate settings for this board */
-#define CFG_BAUDRATE_TABLE	{ 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
 
 /* SCIF */
 #define CONFIG_SCIF_CONSOLE	1
 #define CONFIG_CONS_SCIF0	1
 
-#define CFG_MEMTEST_START	RSK7203_SDRAM_BASE
-#define CFG_MEMTEST_END		(CFG_MEMTEST_START + (3 * 1024 * 1024))
+#define CONFIG_SYS_MEMTEST_START	RSK7203_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024))
 
-#define CFG_SDRAM_BASE		RSK7203_SDRAM_BASE
-#define CFG_SDRAM_SIZE		(32 * 1024 * 1024)
+#define CONFIG_SYS_SDRAM_BASE		RSK7203_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		(32 * 1024 * 1024)
 
-#define CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 1024 * 1024)
-#define CFG_MONITOR_BASE	RSK7203_FLASH_BASE_1
-#define CFG_MONITOR_LEN		(128 * 1024)
-#define CFG_MALLOC_LEN		(256 * 1024)
-#define CFG_GBL_DATA_SIZE	256
-#define CFG_BOOTMAPSZ		(8 * 1024 * 1024)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 1024 * 1024)
+#define CONFIG_SYS_MONITOR_BASE	RSK7203_FLASH_BASE_1
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	256
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 
 /* FLASH */
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#undef	CFG_FLASH_QUIET_TEST
-#define CFG_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_BASE		RSK7203_FLASH_BASE_1
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
-#define CFG_MAX_FLASH_SECT	64
-#define CFG_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#undef	CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_BASE		RSK7203_FLASH_BASE_1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT	64
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
 
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	(64 * 1024)
 #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_FLASH_ERASE_TOUT	12000
-#define CFG_FLASH_WRITE_TOUT	500
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_FLASH_ERASE_TOUT	12000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
 #define CMT_CLK_DIVIDER	32	/* 8 (default), 32, 128 or 512 */
-#define CFG_HZ			(CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
+#define CONFIG_SYS_HZ			(CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
+
+/* Network interface */
+#define CONFIG_DRIVER_SMC911X
+#define CONFIG_DRIVER_SMC911X_16_BIT
+#define CONFIG_DRIVER_SMC911X_BASE (0x24000000)
 
 #endif	/* __RSK7203_H */
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index 560bf05..f4e08c6 100644
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -74,7 +74,7 @@
  * 0x6	     0x1	 66	133    266   Close  Close  Open
  * 0x6	     0x2	 66	133    300   Close  Open   Close
  */
-#define CFG_SBC_MODCK_H 0x05
+#define CONFIG_SYS_SBC_MODCK_H 0x05
 
 /* Define this if you want to boot from 0x00000100. If you don't define
  * this, you will need to program the bootloader to 0xfff00000, and
@@ -82,21 +82,21 @@
  * way to do that is to program the bootloader at both addresses.
  * It is suggested that you just let U-Boot live at 0x00000000.
  */
-#define CFG_SBC_BOOT_LOW 1
+#define CONFIG_SYS_SBC_BOOT_LOW 1
 
 /* What should the base address of the main FLASH be and how big is
  * it (in MBytes)?  This must contain TEXT_BASE from board/sacsng/config.mk
  * The main FLASH is whichever is connected to *CS0.
  */
-#define CFG_FLASH0_BASE 0x40000000
-#define CFG_FLASH0_SIZE 2
+#define CONFIG_SYS_FLASH0_BASE 0x40000000
+#define CONFIG_SYS_FLASH0_SIZE 2
 
 /* What should the base address of the secondary FLASH be and how big
  * is it (in Mbytes)?  The secondary FLASH is whichever is connected
  * to *CS6.
  */
-#define CFG_FLASH1_BASE 0x60000000
-#define CFG_FLASH1_SIZE 2
+#define CONFIG_SYS_FLASH1_BASE 0x60000000
+#define CONFIG_SYS_FLASH1_SIZE 2
 
 /* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
  */
@@ -105,8 +105,8 @@
 /* What should be the base address of SDRAM DIMM and how big is
  * it (in Mbytes)?  This will normally auto-configure via the SPD.
 */
-#define CFG_SDRAM0_BASE 0x00000000
-#define CFG_SDRAM0_SIZE 64
+#define CONFIG_SYS_SDRAM0_BASE 0x00000000
+#define CONFIG_SYS_SDRAM0_SIZE 64
 
 /*
  * Memory map example with 64 MB DIMM:
@@ -125,14 +125,14 @@
  *     0x03F5 FFB0     Board Info Data
  *     0x03F6 0000     Malloc Arena
  *	     :		    CONFIG_ENV_SECT_SIZE, 16k
- *	     :		    CFG_MALLOC_LEN,    128k
+ *	     :		    CONFIG_SYS_MALLOC_LEN,    128k
  *     0x03FC 0000     RAM Copy of Monitor Code
- *	     :		    CFG_MONITOR_LEN,   256k
- *     0x03FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
+ *	     :		    CONFIG_SYS_MONITOR_LEN,   256k
+ *     0x03FF FFFF     [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
  */
 
-#define CONFIG_POST		(CFG_POST_MEMORY | \
-				 CFG_POST_CPU)
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY | \
+				 CONFIG_SYS_POST_CPU)
 
 
 /*
@@ -198,7 +198,7 @@
  *  - RX clk is CLK11
  *  - TX clk is CLK12
  */
-# define CFG_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11  | CMXSCR_TS1CS_CLK12)
+# define CONFIG_SYS_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11  | CMXSCR_TS1CS_CLK12)
 
 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 
@@ -208,10 +208,10 @@
  * - Select bus for bd/buffers (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 
 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 
@@ -220,7 +220,7 @@
 /*
  * Configure for RAM tests.
  */
-#undef  CFG_DRAM_TEST			/* calls other tests in board.c	*/
+#undef  CONFIG_SYS_DRAM_TEST			/* calls other tests in board.c	*/
 
 
 /*
@@ -234,13 +234,13 @@
 #define STATUS_LED_DAT		im_ioport.iop_pdata
 
 #define STATUS_LED_BIT		0x00000800	/* LED 0 is on PA.20	*/
-#define STATUS_LED_PERIOD	(CFG_HZ)
+#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ)
 #define STATUS_LED_STATE	STATUS_LED_OFF
 #define STATUS_LED_BIT1		0x00001000	/* LED 1 is on PA.19	*/
-#define STATUS_LED_PERIOD1	(CFG_HZ)
+#define STATUS_LED_PERIOD1	(CONFIG_SYS_HZ)
 #define STATUS_LED_STATE1	STATUS_LED_OFF
 #define STATUS_LED_BIT2		0x00002000	/* LED 2 is on PA.18	*/
-#define STATUS_LED_PERIOD2	(CFG_HZ/2)
+#define STATUS_LED_PERIOD2	(CONFIG_SYS_HZ/2)
 #define STATUS_LED_STATE2	STATUS_LED_ON
 
 #define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
@@ -293,8 +293,8 @@
  */
 #undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * Software (bit-bang) I2C driver configuration
@@ -486,14 +486,14 @@
 
 
 /* undef this to save memory */
-#define CFG_LONGHELP
+#define CONFIG_SYS_LONGHELP
 
 /* Monitor Command Prompt */
-#define CFG_PROMPT		"=> "
+#define CONFIG_SYS_PROMPT		"=> "
 
-#undef  CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2     "> "
+#undef  CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
 #endif
 
 /* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
@@ -530,7 +530,7 @@
 
 
 /* Where do the internal registers live? */
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR		0xF0000000
 
 #undef	CONFIG_WATCHDOG			/* disable the watchdog */
 
@@ -548,76 +548,76 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_BOOTM_HEADER_QUIET 1        /* Suppress the image header dump    */
+#define CONFIG_SYS_BOOTM_HEADER_QUIET 1        /* Suppress the image header dump    */
 					/* in the bootm command.             */
-#define CFG_BOOTM_PROGESS_QUIET 1       /* Suppress the progress displays,   */
+#define CONFIG_SYS_BOOTM_PROGESS_QUIET 1       /* Suppress the progress displays,   */
 					/* "## <message>" from the bootm cmd */
-#define CFG_BOOTP_CHECK_HOSTNAME 1      /* If checkhostname environment is   */
+#define CONFIG_SYS_BOOTP_CHECK_HOSTNAME 1      /* If checkhostname environment is   */
 					/* defined, then the hostname param  */
 					/* validated against checkhostname.  */
-#define CFG_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up   */
-#define CFG_BOOTP_SHORT_RANDOM_DELAY 1  /* Use a short random delay value    */
+#define CONFIG_SYS_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up   */
+#define CONFIG_SYS_BOOTP_SHORT_RANDOM_DELAY 1  /* Use a short random delay value    */
 					/* (limited to maximum of 1024 msec) */
-#define CFG_CHK_FOR_ABORT_AT_LEAST_ONCE 1
+#define CONFIG_SYS_CHK_FOR_ABORT_AT_LEAST_ONCE 1
 					/* Check for abort key presses       */
 					/* at least once in dependent of the */
 					/* CONFIG_BOOTDELAY value.           */
-#define CFG_CONSOLE_INFO_QUIET 1        /* Don't print console @ startup     */
-#define CFG_FAULT_ECHO_LINK_DOWN 1      /* Echo the inverted Ethernet link   */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET 1        /* Don't print console @ startup     */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1      /* Echo the inverted Ethernet link   */
 					/* state to the fault LED.           */
-#define CFG_FAULT_MII_ADDR 0x02         /* MII addr of the PHY to check for  */
+#define CONFIG_SYS_FAULT_MII_ADDR 0x02         /* MII addr of the PHY to check for  */
 					/* the Ethernet link state.          */
-#define CFG_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing  */
+#define CONFIG_SYS_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing  */
 					/* until the TFTP is successful.     */
-#define CFG_STATUS_OFF_AFTER_NETBOOT 1  /* After a successful netboot,       */
+#define CONFIG_SYS_STATUS_OFF_AFTER_NETBOOT 1  /* After a successful netboot,       */
 					/* turn off the STATUS LEDs.         */
-#define CFG_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on      */
+#define CONFIG_SYS_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on      */
 					/* incoming data.                    */
-#define CFG_TFTP_BLOCKS_PER_HASH 100    /* For every XX blocks, output a '#' */
+#define CONFIG_SYS_TFTP_BLOCKS_PER_HASH 100    /* For every XX blocks, output a '#' */
 					/* to signify that tftp is moving.   */
-#define CFG_TFTP_HASHES_PER_FLASH 200   /* For every '#' hashes,             */
+#define CONFIG_SYS_TFTP_HASHES_PER_FLASH 200   /* For every '#' hashes,             */
 					/* flash the status LED.             */
-#define CFG_TFTP_HASHES_PER_LINE 65     /* Only output XX '#'s per line      */
+#define CONFIG_SYS_TFTP_HASHES_PER_LINE 65     /* Only output XX '#'s per line      */
 					/* during the tftp file transfer.    */
-#define CFG_TFTP_PROGESS_QUIET 1        /* Suppress the progress displays    */
+#define CONFIG_SYS_TFTP_PROGESS_QUIET 1        /* Suppress the progress displays    */
 					/* '#'s from the tftp command.       */
-#define CFG_TFTP_STATUS_QUIET 1         /* Suppress the status displays      */
+#define CONFIG_SYS_TFTP_STATUS_QUIET 1         /* Suppress the status displays      */
 					/* issued during the tftp command.   */
-#define CFG_TFTP_TIMEOUT_COUNT 5        /* How many timeouts TFTP will allow */
+#define CONFIG_SYS_TFTP_TIMEOUT_COUNT 5        /* How many timeouts TFTP will allow */
 					/* before it gives up.               */
 
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CBSIZE		1024	/* Console I/O Buffer Size	     */
+#  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	     */
 #else
-#  define CFG_CBSIZE		256	/* Console I/O Buffer Size	     */
+#  define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	     */
 #endif
 
 /* Print Buffer Size */
-#define CFG_PBSIZE	  (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
+#define CONFIG_SYS_PBSIZE	  (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 
-#define CFG_MAXARGS		32	/* max number of command args	*/
+#define CONFIG_SYS_MAXARGS		32	/* max number of command args	*/
 
-#define CFG_BARGSIZE		CFG_CBSIZE /* Boot Argument Buffer Size	   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	   */
 
-#define CFG_LOAD_ADDR		0x400000   /* default load address */
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_LOAD_ADDR		0x400000   /* default load address */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_ALT_MEMTEST                 /* Select full-featured memory test */
-#define CFG_MEMTEST_START	0x2000	/* memtest works from the end of */
+#define CONFIG_SYS_ALT_MEMTEST                 /* Select full-featured memory test */
+#define CONFIG_SYS_MEMTEST_START	0x2000	/* memtest works from the end of */
 					/* the exception vector table */
 					/* to the end of the DRAM  */
 					/* less monitor and malloc area */
-#define CFG_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
-#define CFG_MEM_END_USAGE	( CFG_MONITOR_LEN \
-				+ CFG_MALLOC_LEN \
+#define CONFIG_SYS_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
+#define CONFIG_SYS_MEM_END_USAGE	( CONFIG_SYS_MONITOR_LEN \
+				+ CONFIG_SYS_MALLOC_LEN \
 				+ CONFIG_ENV_SECT_SIZE \
-				+ CFG_STACK_USAGE )
+				+ CONFIG_SYS_STACK_USAGE )
 
-#define CFG_MEMTEST_END		( CFG_SDRAM_SIZE * 1024 * 1024 \
-				- CFG_MEM_END_USAGE )
+#define CONFIG_SYS_MEMTEST_END		( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
+				- CONFIG_SYS_MEM_END_USAGE )
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -625,112 +625,112 @@
  * You should know what you are doing if you make changes here.
  */
 
-#define CFG_FLASH_BASE	CFG_FLASH0_BASE
-#define CFG_FLASH_SIZE	CFG_FLASH0_SIZE
-#define CFG_SDRAM_BASE	CFG_SDRAM0_BASE
-#define CFG_SDRAM_SIZE	CFG_SDRAM0_SIZE
+#define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_FLASH_SIZE	CONFIG_SYS_FLASH0_SIZE
+#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_SDRAM0_BASE
+#define CONFIG_SYS_SDRAM_SIZE	CONFIG_SYS_SDRAM0_SIZE
 
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  */
-#if defined(CFG_SBC_BOOT_LOW)
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#if defined(CONFIG_SYS_SBC_BOOT_LOW)
+#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 #else
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (0)
-#endif /* defined(CFG_SBC_BOOT_LOW) */
+#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (0)
+#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
 
-/* get the HRCW ISB field from CFG_IMMR */
-#define CFG_SBC_HRCW_IMMR	( ((CFG_IMMR & 0x10000000) >> 10) | \
-				  ((CFG_IMMR & 0x01000000) >>  7) | \
-				  ((CFG_IMMR & 0x00100000) >>  4) )
+/* get the HRCW ISB field from CONFIG_SYS_IMMR */
+#define CONFIG_SYS_SBC_HRCW_IMMR	( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
+				  ((CONFIG_SYS_IMMR & 0x01000000) >>  7) | \
+				  ((CONFIG_SYS_IMMR & 0x00100000) >>  4) )
 
-#define CFG_HRCW_MASTER		( HRCW_BPS10				| \
+#define CONFIG_SYS_HRCW_MASTER		( HRCW_BPS10				| \
 				  HRCW_DPPC11				| \
-				  CFG_SBC_HRCW_IMMR			| \
+				  CONFIG_SYS_SBC_HRCW_IMMR			| \
 				  HRCW_MMR00				| \
 				  HRCW_LBPC11				| \
 				  HRCW_APPC10				| \
 				  HRCW_CS10PC00				| \
-				  (CFG_SBC_MODCK_H & HRCW_MODCK_H1111)	| \
-				  CFG_SBC_HRCW_BOOT_FLAGS )
+				  (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111)	| \
+				  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
 
 /* no slaves */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
  */
-#define CFG_MONITOR_BASE	CFG_FLASH0_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH0_BASE
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#  define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#  define CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
 
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
-#undef  CFG_FLASH_PROTECTION		/* use hardware protection		*/
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	(64+4)	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#undef  CONFIG_SYS_FLASH_PROTECTION		/* use hardware protection		*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	(64+4)	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1	/* Timeout for Flash Write (in ms)	*/
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 #  define CONFIG_ENV_IS_IN_FLASH	1
 
 #  ifdef CONFIG_ENV_IN_OWN_SECT
-#    define CONFIG_ENV_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#    define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #    define CONFIG_ENV_SECT_SIZE	0x10000
 #  else
-#    define CONFIG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
+#    define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
 #    define CONFIG_ENV_SIZE	0x1000	/* Total Size of Environment Sector	*/
 #    define CONFIG_ENV_SECT_SIZE	0x10000 /* see README - env sect real size	*/
 #  endif /* CONFIG_ENV_IN_OWN_SECT */
 
 #else
 #  define CONFIG_ENV_IS_IN_NVRAM	1
-#  define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#  define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #  define CONFIG_ENV_SIZE		0x200
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU */
 
 #if defined(CONFIG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -743,37 +743,37 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT	(HID0_ICE  |\
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE  |\
 			 HID0_DCE  |\
 			 HID0_ICFI |\
 			 HID0_DCI  |\
 			 HID0_IFEM |\
 			 HID0_ABE)
 
-#define CFG_HID0_FINAL	(HID0_ICE  |\
+#define CONFIG_SYS_HID0_FINAL	(HID0_ICE  |\
 			 HID0_IFEM |\
 			 HID0_ABE  |\
 			 HID0_EMCP)
-#define CFG_HID2	0
+#define CONFIG_SYS_HID2	0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register
  *-----------------------------------------------------------------------
  */
-#define CFG_RMR		0
+#define CONFIG_SYS_RMR		0
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration					 4-25
  *-----------------------------------------------------------------------
  */
-#define CFG_BCR		(BCR_ETM)
+#define CONFIG_SYS_BCR		(BCR_ETM)
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration				 4-31
  *-----------------------------------------------------------------------
  */
 
-#define CFG_SIUMCR	(SIUMCR_DPPC11	|\
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC11	|\
 			 SIUMCR_L2CPC00 |\
 			 SIUMCR_APPC10	|\
 			 SIUMCR_MMR00)
@@ -786,7 +786,7 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC |\
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC |\
 			 SYPCR_BMT  |\
 			 SYPCR_PBME |\
 			 SYPCR_LBME |\
@@ -794,7 +794,7 @@
 			 SYPCR_SWP  |\
 			 SYPCR_SWE)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC |\
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC |\
 			 SYPCR_BMT  |\
 			 SYPCR_PBME |\
 			 SYPCR_LBME |\
@@ -808,7 +808,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC	(TMCNTSC_SEC |\
+#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC |\
 			 TMCNTSC_ALR |\
 			 TMCNTSC_TCF |\
 			 TMCNTSC_TCE)
@@ -819,7 +819,7 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR	(PISCR_PS  |\
+#define CONFIG_SYS_PISCR	(PISCR_PS  |\
 			 PISCR_PTF |\
 			 PISCR_PTE)
 
@@ -827,13 +827,13 @@
  * SCCR - System Clock Control					 9-8
  *-----------------------------------------------------------------------
  */
-#define CFG_SCCR	0
+#define CONFIG_SYS_SCCR	0
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration				13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR	0
+#define CONFIG_SYS_RCCR	0
 
 /*
  * Initialize Memory Controller:
@@ -872,7 +872,7 @@
  *     - No data pipelining is done
  *     - Valid
  */
-#define CFG_BR0_PRELIM	((CFG_FLASH0_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
 			 BRx_PS_16			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
@@ -891,7 +891,7 @@
  *     - One idle clock is inserted between a read access from the
  *	 current bank and the next access.
  */
-#define CFG_OR0_PRELIM	(MEG_TO_AM(CFG_FLASH0_SIZE)	|\
+#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_5_CLK			|\
@@ -921,12 +921,12 @@
  *     - No data pipelining is done
  *     - Valid
  */
-#define CFG_BR2_PRELIM	((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
 			 BRx_PS_64			|\
 			 BRx_MS_SDRAM_P			|\
 			 BRx_V)
 
-#define CFG_BR3_PRELIM	((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
 			 BRx_PS_64			|\
 			 BRx_MS_SDRAM_P			|\
 			 BRx_V)
@@ -940,8 +940,8 @@
  *     - Back-to-back page mode
  *     - Internal bank interleaving within save device enabled
  */
-#if (CFG_SDRAM0_SIZE == 64)
-#define CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM0_SIZE)	|\
+#if (CONFIG_SYS_SDRAM0_SIZE == 64)
+#define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE)	|\
 			 ORxS_BPD_4			|\
 			 ORxS_ROWST_PBI0_A8		|\
 			 ORxS_NUMR_12)
@@ -959,7 +959,7 @@
  */
 #define SDRAM_SPD_ADDR 0x50
 
-#if (CFG_SDRAM0_SIZE == 64)
+#if (CONFIG_SYS_SDRAM0_SIZE == 64)
 /* With a 64 MB DIMM, the PSDMR is configured as follows:
  *
  *     - Bank Based Interleaving,
@@ -977,7 +977,7 @@
  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
  *     - CAS Latency is 2.
  */
-#define CFG_PSDMR	(PSDMR_RFEN	      |\
+#define CONFIG_SYS_PSDMR	(PSDMR_RFEN	      |\
 			 PSDMR_SDAM_A14_IS_A5 |\
 			 PSDMR_BSMA_A14_A16   |\
 			 PSDMR_SDA10_PBI0_A9  |\
@@ -995,14 +995,14 @@
  * Shoot for approximately 1MHz on the prescaler.
  */
 #if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
-#define CFG_MPTPR	MPTPR_PTP_DIV64
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV64
 #elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
-#define CFG_MPTPR	MPTPR_PTP_DIV32
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV32
 #else
-#warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK"
-#define CFG_MPTPR	MPTPR_PTP_DIV32
+#warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK"
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV32
 #endif
-#define CFG_PSRT	14
+#define CONFIG_SYS_PSRT	14
 
 
 /*-----------------------------------------------------------------------
@@ -1017,7 +1017,7 @@
  *
  * The secondary FLASH is connected to *CS6
  */
-#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE))
+#if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE))
 
 /* BR6 is configured as follows:
  *
@@ -1031,7 +1031,7 @@
  *     - No data pipelining is done
  *     - Valid
  */
-#  define CFG_BR6_PRELIM  ((CFG_FLASH1_BASE & BRx_BA_MSK) |\
+#  define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\
 			   BRx_PS_16			  |\
 			   BRx_MS_GPCM_P		  |\
 			   BRx_V)
@@ -1050,13 +1050,13 @@
  *     - One idle clock is inserted between a read access from the
  *	 current bank and the next access.
  */
-#  define CFG_OR6_PRELIM  (MEG_TO_AM(CFG_FLASH1_SIZE)  |\
+#  define CONFIG_SYS_OR6_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE)  |\
 			   ORxG_CSNT		       |\
 			   ORxG_ACS_DIV1	       |\
 			   ORxG_SCY_5_CLK	       |\
 			   ORxG_TRLX		       |\
 			   ORxG_EHTR)
-#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */
+#endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */
 
 /*
  * Internal Definitions
diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h
index 110ab39..bf4a14e 100644
--- a/include/configs/sbc2410x.h
+++ b/include/configs/sbc2410x.h
@@ -57,8 +57,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -125,26 +125,26 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"[ ~ljh@GDLC ]# "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"[ ~ljh@GDLC ]# "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x30000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x33F00000	/* 63 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x30000000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x33F00000	/* 63 MB in DRAM	*/
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0x33000000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x33000000	/* default load address	*/
 
 /* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
 /* it to wrap 100 times (total 1562500) to get 1 sec. */
-#define	CFG_HZ			1562500
+#define	CONFIG_SYS_HZ			1562500
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -166,7 +166,7 @@
 
 #define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
@@ -175,23 +175,23 @@
 
 #define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
 
 #ifdef CONFIG_AMD_LV800
 #define PHYS_FLASH_SIZE		0x00100000 /* 1MB */
-#define CFG_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
+#define CONFIG_SYS_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
 #endif
 
 #ifdef CONFIG_AMD_LV400
 #define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
-#define CFG_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x070000) /* addr of environment */
+#define CONFIG_SYS_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
 #endif
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */
@@ -200,7 +200,7 @@
  * NAND flash settings
  */
 #if defined(CONFIG_CMD_NAND)
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
 #define SECTORSIZE 512
 
 #define ADDR_COLUMN 1
@@ -209,7 +209,6 @@
 
 #define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
 
 #define NAND_WAIT_READY(nand)	NF_WaitRB()
 #define NAND_DISABLE_CE(nand)	NF_SetCE(NFCE_HIGH)
@@ -231,8 +230,8 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_CMDLINE_TAG
 
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2   "> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2   "> "
 
 #define CONFIG_CMDLINE_EDITING
 
diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h
index 759e4e2..7197aaf 100644
--- a/include/configs/sbc405.h
+++ b/include/configs/sbc405.h
@@ -58,6 +58,7 @@
 #define CONFIG_BOOTCOMMAND      "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx"      /* autoboot command     */
 
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_PHY_RESET_DELAY	300	/* Intel LXT971A needs this	*/
@@ -125,48 +126,47 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#undef CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef CFG_EXT_SERIAL_CLOCK		/* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD		691200
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK		/* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD		691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE					\
+#define CONFIG_SYS_BAUDRATE_TABLE					\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,	\
 	 57600, 115200, 230400, 460800, 921600 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address */
-#define CFG_EXTBDINFO	1		/* To use extended board_info (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_info (bd_t) */
 
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_VERSION_VARIABLE	1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
 #undef  CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -183,51 +183,51 @@
 
 #define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
-#define CFG_PCI_SUBSYS_VENDORID	0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID	0x0408	/* PCI Device ID: PMC-405	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI	0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI	0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID	0x0408	/* PCI Device ID: PMC-405	*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI	0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI	0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MONITOR_BASE	0xFFFC0000
-#define CFG_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN	(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_BASE	0xFFFC0000
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_FLASH_BASE		0xFF000000
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)		*/
-#define CFG_FLASH_INCREMENT	0x01000000
-#undef CFG_FLASH_PROTECTION		/* don't use hardware protection	*/
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)		*/
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)		*/
+#define CONFIG_SYS_FLASH_INCREMENT	0x01000000
+#undef CONFIG_SYS_FLASH_PROTECTION		/* don't use hardware protection	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)		*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
 
 /*-----------------------------------------------------------------------
  * Environment Variable setup
  */
-#define CONFIG_ENV_ADDR	CFG_FLASH_BASE	/* starting right at the beginning	*/
+#define CONFIG_ENV_ADDR	CONFIG_SYS_FLASH_BASE	/* starting right at the beginning	*/
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0	/* starting right at the beginning	*/
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* see README - env sector total size	*/
@@ -236,28 +236,28 @@
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  */
-#define FLASH0_BA	CFG_FLASH_BASE		/* FLASH 0 Base Address		*/
+#define FLASH0_BA	CONFIG_SYS_FLASH_BASE		/* FLASH 0 Base Address		*/
 
 /* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP	0x92015480
-#define CFG_EBC_PB0CR	FLASH0_BA | 0x9C000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=32bit*/
+#define CONFIG_SYS_EBC_PB0AP	0x92015480
+#define CONFIG_SYS_EBC_PB0CR	FLASH0_BA | 0x9C000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=32bit*/
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	1
+#define CONFIG_SYS_TEMP_STACK_OCM	1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for Serial Presence Detect EEPROM address
diff --git a/include/configs/sbc8240.h b/include/configs/sbc8240.h
index 10ff7ab..1cc2920 100644
--- a/include/configs/sbc8240.h
+++ b/include/configs/sbc8240.h
@@ -45,7 +45,7 @@
 
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		9600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_PREBOOT  "echo;echo Welcome to U-Boot for the sbc8240;echo;echo Type \"? or help\" to get on-line help;echo"
 
@@ -96,7 +96,7 @@
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_ELF
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
@@ -106,15 +106,15 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 
 #if 1
-#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
 #endif
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #define CONFIG_ETHADDR          DE:AD:BE:EF:01:01    /* Ethernet address */
@@ -126,7 +126,7 @@
 #define CONFIG_BOARD_SPECIFIC_LED       /* version has board specific leds */
 
 #define STATUS_LED_BIT          0x00000001
-#define STATUS_LED_PERIOD       (CFG_HZ / 2)
+#define STATUS_LED_PERIOD       (CONFIG_SYS_HZ / 2)
 #define STATUS_LED_STATE        STATUS_LED_BLINKING
 #define STATUS_LED_ACTIVE       0       /* LED on for bit == 0  */
 #define STATUS_LED_BOOT         0       /* LED 0 used for boot status */
@@ -137,15 +137,15 @@ typedef unsigned int led_id_t;
 
 #define __led_toggle(_msk) \
 	do { \
-		*((volatile char *) (CFG_LED_BASE)) ^= (_msk); \
+		*((volatile char *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
 	} while(0)
 
 #define __led_set(_msk, _st) \
 	do { \
 		if ((_st)) \
-			*((volatile char *) (CFG_LED_BASE)) |= (_msk); \
+			*((volatile char *) (CONFIG_SYS_LED_BASE)) |= (_msk); \
 		else \
-			*((volatile char *) (CFG_LED_BASE)) &= ~(_msk); \
+			*((volatile char *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
 	} while(0)
 
 #define __led_init(msk, st) __led_set(msk, st)
@@ -153,44 +153,44 @@ typedef unsigned int led_id_t;
 #endif
 
 #define CONFIG_MISC_INIT_R
-#define CFG_LED_BASE	0xFFE80000
+#define CONFIG_SYS_LED_BASE	0xFFE80000
 
 /* Print Buffer Size
  */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE	    0x00000000
-#define CFG_FLASH_BASE	    0xFFF00000
+#define CONFIG_SYS_SDRAM_BASE	    0x00000000
+#define CONFIG_SYS_FLASH_BASE	    0xFFF00000
 
-#define CFG_RESET_ADDRESS   0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 
-#define CFG_EUMB_ADDR	    0xFCE00000
+#define CONFIG_SYS_EUMB_ADDR	    0xFCE00000
 
-#define CFG_MONITOR_BASE    TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
 
-#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
 
-#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
 
 	/* Maximum amount of RAM.
 	 */
-#define CFG_MAX_RAM_SIZE    0x10000000
+#define CONFIG_SYS_MAX_RAM_SIZE    0x10000000
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#undef CFG_RAMBOOT
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#undef CONFIG_SYS_RAMBOOT
 #else
-#define CFG_RAMBOOT
+#define CONFIG_SYS_RAMBOOT
 #endif
 
 /*-----------------------------------------------------------------------
@@ -199,23 +199,23 @@ typedef unsigned int led_id_t;
 
 	/* Size in bytes reserved for initial data
 	 */
-#define CFG_GBL_DATA_SIZE    128
+#define CONFIG_SYS_GBL_DATA_SIZE    128
 
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_END      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
 
-#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_REG_SIZE	1
 
-#define CFG_NS16550_CLK		3686400
+#define CONFIG_SYS_NS16550_CLK		3686400
 
-#define CFG_NS16550_COM1	0xFFF80000
+#define CONFIG_SYS_NS16550_COM1	0xFFF80000
 
 /*
  * Low Level Configuration Settings
@@ -225,36 +225,36 @@ typedef unsigned int led_id_t;
  */
 
 #define CONFIG_SYS_CLK_FREQ  33000000
-#define CFG_HZ		     1000
+#define CONFIG_SYS_HZ		     1000
 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
 
 	/* Bit-field values for MCCR1.
 	 */
-#define CFG_ROMNAL	    0
-#define CFG_ROMFAL	    7
+#define CONFIG_SYS_ROMNAL	    0
+#define CONFIG_SYS_ROMFAL	    7
 
 	/* Bit-field values for MCCR2.
 	 */
-#define CFG_REFINT	    430	    /* Refresh interval			*/
+#define CONFIG_SYS_REFINT	    430	    /* Refresh interval			*/
 
 	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 	 */
-#define CFG_BSTOPRE	    192
+#define CONFIG_SYS_BSTOPRE	    192
 
 	/* Bit-field values for MCCR3.
 	 */
-#define CFG_REFREC	    2	    /* Refresh to activate interval	*/
-#define CFG_RDLAT	    3	    /* Data latancy from read command	*/
+#define CONFIG_SYS_REFREC	    2	    /* Refresh to activate interval	*/
+#define CONFIG_SYS_RDLAT	    3	    /* Data latancy from read command	*/
 
 	/* Bit-field values for MCCR4.
 	 */
-#define CFG_PRETOACT	    2	    /* Precharge to activate interval	*/
-#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval	*/
-#define CFG_SDMODE_CAS_LAT  2	    /* SDMODE CAS latancy		*/
-#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type			*/
-#define CFG_SDMODE_BURSTLEN 2	    /* SDMODE Burst length		*/
-#define CFG_ACTORW	    2
-#define CFG_REGISTERD_TYPE_BUFFER 1
+#define CONFIG_SYS_PRETOACT	    2	    /* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE	    5	    /* Activate to Precharge interval	*/
+#define CONFIG_SYS_SDMODE_CAS_LAT  2	    /* SDMODE CAS latancy		*/
+#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type			*/
+#define CONFIG_SYS_SDMODE_BURSTLEN 2	    /* SDMODE Burst length		*/
+#define CONFIG_SYS_ACTORW	    2
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
 
 /* Memory bank settings.
  * Only bits 20-29 are actually used from these vales to set the
@@ -263,69 +263,69 @@ typedef unsigned int led_id_t;
  * address. Refer to the MPC8240 book.
  */
 
-#define CFG_BANK0_START	    0x00000000
-#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START	    0x3ff00000
-#define CFG_BANK1_END	    0x3fffffff
-#define CFG_BANK1_ENABLE    0
-#define CFG_BANK2_START	    0x3ff00000
-#define CFG_BANK2_END	    0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START	    0x3ff00000
-#define CFG_BANK3_END	    0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START	    0x3ff00000
-#define CFG_BANK4_END	    0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START	    0x3ff00000
-#define CFG_BANK5_END	    0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START	    0x3ff00000
-#define CFG_BANK6_END	    0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START	    0x3ff00000
-#define CFG_BANK7_END	    0x3fffffff
-#define CFG_BANK7_ENABLE    0
-
-#define CFG_ODCR	    0xff
-
-#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L  CFG_IBAT0L
-#define CFG_DBAT0U  CFG_IBAT0U
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-#define CFG_DBAT2L  CFG_IBAT2L
-#define CFG_DBAT2U  CFG_IBAT2U
-#define CFG_DBAT3L  CFG_IBAT3L
-#define CFG_DBAT3U  CFG_IBAT3U
+#define CONFIG_SYS_BANK0_START	    0x00000000
+#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE    1
+#define CONFIG_SYS_BANK1_START	    0x3ff00000
+#define CONFIG_SYS_BANK1_END	    0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE    0
+#define CONFIG_SYS_BANK2_START	    0x3ff00000
+#define CONFIG_SYS_BANK2_END	    0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE    0
+#define CONFIG_SYS_BANK3_START	    0x3ff00000
+#define CONFIG_SYS_BANK3_END	    0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE    0
+#define CONFIG_SYS_BANK4_START	    0x3ff00000
+#define CONFIG_SYS_BANK4_END	    0x3fffffff
+#define CONFIG_SYS_BANK4_ENABLE    0
+#define CONFIG_SYS_BANK5_START	    0x3ff00000
+#define CONFIG_SYS_BANK5_END	    0x3fffffff
+#define CONFIG_SYS_BANK5_ENABLE    0
+#define CONFIG_SYS_BANK6_START	    0x3ff00000
+#define CONFIG_SYS_BANK6_END	    0x3fffffff
+#define CONFIG_SYS_BANK6_ENABLE    0
+#define CONFIG_SYS_BANK7_START	    0x3ff00000
+#define CONFIG_SYS_BANK7_END	    0x3fffffff
+#define CONFIG_SYS_BANK7_ENABLE    0
+
+#define CONFIG_SYS_ODCR	    0xff
+
+#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* Max number of sectors in one bank	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* Max number of sectors in one bank	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 /*
  * Init Memory Controller:
@@ -333,7 +333,7 @@ typedef unsigned int led_id_t;
  * BR0/1 and OR0/1 (FLASH)
  */
 
-#define FLASH_BASE0_PRELIM      CFG_FLASH_BASE  /* FLASH bank #0        */
+#define FLASH_BASE0_PRELIM      CONFIG_SYS_FLASH_BASE  /* FLASH bank #0        */
 #define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */
 
 	/* Warining: environment is not EMBEDDED in the U-Boot code.
@@ -348,9 +348,9 @@ typedef unsigned int led_id_t;
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SIZE	32
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /*
@@ -370,5 +370,5 @@ typedef unsigned int led_id_t;
 #define CONFIG_NET_MULTI		/* Multi ethernet cards support */
 #define CONFIG_TULIP
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8       /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8       /* use 8 rx buffer on eepro100  */
 #endif /* __CONFIG_H */
diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h
index e96adb9..26ed557 100644
--- a/include/configs/sbc8260.h
+++ b/include/configs/sbc8260.h
@@ -73,7 +73,7 @@
  * 0x6	     0x1	 66	133    266   Close  Close  Open
  * 0x6	     0x2	 66	133    300   Close  Open   Close
  */
-#define CFG_SBC_MODCK_H 0x05
+#define CONFIG_SYS_SBC_MODCK_H 0x05
 
 /* Define this if you want to boot from 0x00000100. If you don't define
  * this, you will need to program the bootloader to 0xfff00000, and
@@ -81,34 +81,34 @@
  * way to do that is to program the bootloader at both addresses.
  * It is suggested that you just let U-Boot live at 0x00000000.
  */
-#define CFG_SBC_BOOT_LOW 1
+#define CONFIG_SYS_SBC_BOOT_LOW 1
 
 /* What should the base address of the main FLASH be and how big is
  * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
  * The main FLASH is whichever is connected to *CS0. U-Boot expects
  * this to be the SIMM.
  */
-#define CFG_FLASH0_BASE 0x40000000
-#define CFG_FLASH0_SIZE 4
+#define CONFIG_SYS_FLASH0_BASE 0x40000000
+#define CONFIG_SYS_FLASH0_SIZE 4
 
 /* What should the base address of the secondary FLASH be and how big
  * is it (in Mbytes)? The secondary FLASH is whichever is connected
  * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
  * want it enabled, don't define these constants.
  */
-#define CFG_FLASH1_BASE 0x60000000
-#define CFG_FLASH1_SIZE 2
+#define CONFIG_SYS_FLASH1_BASE 0x60000000
+#define CONFIG_SYS_FLASH1_SIZE 2
 
 /* What should be the base address of SDRAM DIMM and how big is
  * it (in Mbytes)?
 */
-#define CFG_SDRAM0_BASE 0x00000000
-#define CFG_SDRAM0_SIZE 64
+#define CONFIG_SYS_SDRAM0_BASE 0x00000000
+#define CONFIG_SYS_SDRAM0_SIZE 64
 
 /* What should be the base address of the LEDs and switch S0?
  * If you don't want them enabled, don't define this.
  */
-#define CFG_LED_BASE 0xa0000000
+#define CONFIG_SYS_LED_BASE 0xa0000000
 
 
 /*
@@ -128,10 +128,10 @@
  *     0x00F5 FFB0     Board Info Data
  *     0x00F6 0000     Malloc Arena
  *	     :		    CONFIG_ENV_SECT_SIZE, 256k
- *	     :		    CFG_MALLOC_LEN,    128k
+ *	     :		    CONFIG_SYS_MALLOC_LEN,    128k
  *     0x00FC 0000     RAM Copy of Monitor Code
- *	     :		    CFG_MONITOR_LEN,   256k
- *     0x00FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
+ *	     :		    CONFIG_SYS_MONITOR_LEN,   256k
+ *     0x00FF FFFF     [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
  */
 
 /*
@@ -151,10 +151,10 @@
  *     0x03F5 FFB0     Board Info Data
  *     0x03F6 0000     Malloc Arena
  *	     :		    CONFIG_ENV_SECT_SIZE, 256k
- *	     :		    CFG_MALLOC_LEN,    128k
+ *	     :		    CONFIG_SYS_MALLOC_LEN,    128k
  *     0x03FC 0000     RAM Copy of Monitor Code
- *	     :		    CFG_MONITOR_LEN,   256k
- *     0x03FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
+ *	     :		    CONFIG_SYS_MONITOR_LEN,   256k
+ *     0x03FF FFFF     [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
  */
 
 
@@ -220,7 +220,7 @@
  *  - RX clk is CLK11
  *  - TX clk is CLK12
  */
-# define CFG_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11  | CMXSCR_TS1CS_CLK12)
+# define CONFIG_SYS_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11  | CMXSCR_TS1CS_CLK12)
 
 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 
@@ -230,10 +230,10 @@
  * - Select bus for bd/buffers (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 
 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 
@@ -251,8 +251,8 @@
  */
 #undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * Software (bit-bang) I2C driver configuration
@@ -425,14 +425,14 @@
 
 
 /* undef this to save memory */
-#define CFG_LONGHELP
+#define CONFIG_SYS_LONGHELP
 
 /* Monitor Command Prompt */
-#define CFG_PROMPT		"=> "
+#define CONFIG_SYS_PROMPT		"=> "
 
-#undef  CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef  CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 /* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
@@ -469,7 +469,7 @@
 #undef CONFIG_WATCHDOG				/* disable the watchdog */
 
 /* Where do the internal registers live? */
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR		0xF0000000
 
 /*****************************************************************************
  *
@@ -486,37 +486,37 @@
  * Miscellaneous configurable options
  */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CBSIZE		1024	/* Console I/O Buffer Size	     */
+#  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	     */
 #else
-#  define CFG_CBSIZE		256	/* Console I/O Buffer Size	     */
+#  define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	     */
 #endif
 
 /* Print Buffer Size */
-#define CFG_PBSIZE	  (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
+#define CONFIG_SYS_PBSIZE	  (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 
-#define CFG_MAXARGS		32	/* max number of command args	*/
+#define CONFIG_SYS_MAXARGS		32	/* max number of command args	*/
 
-#define CFG_BARGSIZE		CFG_CBSIZE /* Boot Argument Buffer Size	   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	   */
 
-#define CFG_LOAD_ADDR		0x400000   /* default load address */
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_LOAD_ADDR		0x400000   /* default load address */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_ALT_MEMTEST			/* Select full-featured memory test */
-#define CFG_MEMTEST_START	0x2000	/* memtest works from the end of */
+#define CONFIG_SYS_ALT_MEMTEST			/* Select full-featured memory test */
+#define CONFIG_SYS_MEMTEST_START	0x2000	/* memtest works from the end of */
 					/* the exception vector table */
 					/* to the end of the DRAM  */
 					/* less monitor and malloc area */
-#define CFG_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
-#define CFG_MEM_END_USAGE	( CFG_MONITOR_LEN \
-				+ CFG_MALLOC_LEN \
+#define CONFIG_SYS_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
+#define CONFIG_SYS_MEM_END_USAGE	( CONFIG_SYS_MONITOR_LEN \
+				+ CONFIG_SYS_MALLOC_LEN \
 				+ CONFIG_ENV_SECT_SIZE \
-				+ CFG_STACK_USAGE )
+				+ CONFIG_SYS_STACK_USAGE )
 
-#define CFG_MEMTEST_END		( CFG_SDRAM_SIZE * 1024 * 1024 \
-				- CFG_MEM_END_USAGE )
+#define CONFIG_SYS_MEMTEST_END		( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
+				- CONFIG_SYS_MEM_END_USAGE )
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -524,109 +524,109 @@
  * You should know what you are doing if you make changes here.
  */
 
-#define CFG_FLASH_BASE	CFG_FLASH0_BASE
-#define CFG_FLASH_SIZE	CFG_FLASH0_SIZE
-#define CFG_SDRAM_BASE	CFG_SDRAM0_BASE
-#define CFG_SDRAM_SIZE	CFG_SDRAM0_SIZE
+#define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_FLASH_SIZE	CONFIG_SYS_FLASH0_SIZE
+#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_SDRAM0_BASE
+#define CONFIG_SYS_SDRAM_SIZE	CONFIG_SYS_SDRAM0_SIZE
 
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  */
-#if defined(CFG_SBC_BOOT_LOW)
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#if defined(CONFIG_SYS_SBC_BOOT_LOW)
+#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 #else
-#  define  CFG_SBC_HRCW_BOOT_FLAGS  (0)
-#endif /* defined(CFG_SBC_BOOT_LOW) */
+#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (0)
+#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
 
-/* get the HRCW ISB field from CFG_IMMR */
-#define CFG_SBC_HRCW_IMMR	( ((CFG_IMMR & 0x10000000) >> 10) | \
-				  ((CFG_IMMR & 0x01000000) >>  7) | \
-				  ((CFG_IMMR & 0x00100000) >>  4) )
+/* get the HRCW ISB field from CONFIG_SYS_IMMR */
+#define CONFIG_SYS_SBC_HRCW_IMMR	( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
+				  ((CONFIG_SYS_IMMR & 0x01000000) >>  7) | \
+				  ((CONFIG_SYS_IMMR & 0x00100000) >>  4) )
 
-#define CFG_HRCW_MASTER		( HRCW_BPS11				| \
+#define CONFIG_SYS_HRCW_MASTER		( HRCW_BPS11				| \
 				  HRCW_DPPC11				| \
-				  CFG_SBC_HRCW_IMMR			| \
+				  CONFIG_SYS_SBC_HRCW_IMMR			| \
 				  HRCW_MMR00				| \
 				  HRCW_LBPC11				| \
 				  HRCW_APPC10				| \
 				  HRCW_CS10PC00				| \
-				  (CFG_SBC_MODCK_H & HRCW_MODCK_H1111)	| \
-				  CFG_SBC_HRCW_BOOT_FLAGS )
+				  (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111)	| \
+				  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
 
 /* no slaves */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
  */
-#define CFG_MONITOR_BASE	CFG_FLASH0_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH0_BASE
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#  define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#  define CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	16	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	16	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1	/* Timeout for Flash Write (in ms)	*/
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 #  define CONFIG_ENV_IS_IN_FLASH	1
 
 #  ifdef CONFIG_ENV_IN_OWN_SECT
-#    define CONFIG_ENV_ADDR	(CFG_MONITOR_BASE + 0x40000)
+#    define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE + 0x40000)
 #    define CONFIG_ENV_SECT_SIZE	0x40000
 #  else
-#    define CONFIG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
+#    define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
 #    define CONFIG_ENV_SIZE	0x1000	/* Total Size of Environment Sector	*/
 #    define CONFIG_ENV_SECT_SIZE	0x10000 /* see README - env sect real size	*/
 #  endif /* CONFIG_ENV_IN_OWN_SECT */
 
 #else
 #  define CONFIG_ENV_IS_IN_NVRAM	1
-#  define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#  define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #  define CONFIG_ENV_SIZE		0x200
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU */
 
 #if defined(CONFIG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -639,37 +639,37 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT	(HID0_ICE  |\
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE  |\
 			 HID0_DCE  |\
 			 HID0_ICFI |\
 			 HID0_DCI  |\
 			 HID0_IFEM |\
 			 HID0_ABE)
 
-#define CFG_HID0_FINAL	(HID0_ICE  |\
+#define CONFIG_SYS_HID0_FINAL	(HID0_ICE  |\
 			 HID0_IFEM |\
 			 HID0_ABE  |\
 			 HID0_EMCP)
-#define CFG_HID2	0
+#define CONFIG_SYS_HID2	0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register
  *-----------------------------------------------------------------------
  */
-#define CFG_RMR		0
+#define CONFIG_SYS_RMR		0
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration					 4-25
  *-----------------------------------------------------------------------
  */
-#define CFG_BCR		(BCR_ETM)
+#define CONFIG_SYS_BCR		(BCR_ETM)
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration				 4-31
  *-----------------------------------------------------------------------
  */
 
-#define CFG_SIUMCR	(SIUMCR_DPPC11	|\
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC11	|\
 			 SIUMCR_L2CPC00 |\
 			 SIUMCR_APPC10	|\
 			 SIUMCR_MMR00)
@@ -682,7 +682,7 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC |\
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC |\
 			 SYPCR_BMT  |\
 			 SYPCR_PBME |\
 			 SYPCR_LBME |\
@@ -690,7 +690,7 @@
 			 SYPCR_SWP  |\
 			 SYPCR_SWE)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC |\
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC |\
 			 SYPCR_BMT  |\
 			 SYPCR_PBME |\
 			 SYPCR_LBME |\
@@ -704,7 +704,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC	(TMCNTSC_SEC |\
+#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC |\
 			 TMCNTSC_ALR |\
 			 TMCNTSC_TCF |\
 			 TMCNTSC_TCE)
@@ -715,7 +715,7 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR	(PISCR_PS  |\
+#define CONFIG_SYS_PISCR	(PISCR_PS  |\
 			 PISCR_PTF |\
 			 PISCR_PTE)
 
@@ -723,13 +723,13 @@
  * SCCR - System Clock Control					 9-8
  *-----------------------------------------------------------------------
  */
-#define CFG_SCCR	0
+#define CONFIG_SYS_SCCR	0
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration				13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR	0
+#define CONFIG_SYS_RCCR	0
 
 /*
  * Initialize Memory Controller:
@@ -780,7 +780,7 @@
  *     - No data pipelining is done
  *     - Valid
  */
-#define CFG_BR0_PRELIM	((CFG_FLASH0_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
 			 BRx_PS_32			|\
 			 BRx_MS_GPCM_P			|\
 			 BRx_V)
@@ -799,7 +799,7 @@
  *     - One idle clock is inserted between a read access from the
  *	 current bank and the next access.
  */
-#define CFG_OR0_PRELIM	(MEG_TO_AM(CFG_FLASH0_SIZE)	|\
+#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE)	|\
 			 ORxG_CSNT			|\
 			 ORxG_ACS_DIV1			|\
 			 ORxG_SCY_5_CLK			|\
@@ -834,12 +834,12 @@
  *     - No data pipelining is done
  *     - Valid
  */
-#define CFG_BR2_PRELIM	((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
 			 BRx_PS_64			|\
 			 BRx_MS_SDRAM_P			|\
 			 BRx_V)
 
-#define CFG_BR3_PRELIM	((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
 			 BRx_PS_64			|\
 			 BRx_MS_SDRAM_P			|\
 			 BRx_V)
@@ -853,8 +853,8 @@
  *     - Back-to-back page mode
  *     - Internal bank interleaving within save device enabled
  */
-#if (CFG_SDRAM0_SIZE == 16)
-#define CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM0_SIZE)	|\
+#if (CONFIG_SYS_SDRAM0_SIZE == 16)
+#define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE)	|\
 			 ORxS_BPD_2			|\
 			 ORxS_ROWST_PBI0_A9		|\
 			 ORxS_NUMR_11)
@@ -869,8 +869,8 @@
  *     - Back-to-back page mode
  *     - Internal bank interleaving within save device enabled
  */
-#if (CFG_SDRAM0_SIZE == 64)
-#define CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM0_SIZE)	|\
+#if (CONFIG_SYS_SDRAM0_SIZE == 64)
+#define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE)	|\
 			 ORxS_BPD_4			|\
 			 ORxS_ROWST_PBI0_A8		|\
 			 ORxS_NUMR_12)
@@ -886,7 +886,7 @@
  */
 #define SDRAM_SPD_ADDR 0x54
 
-#if (CFG_SDRAM0_SIZE == 16)
+#if (CONFIG_SYS_SDRAM0_SIZE == 16)
 /* With a 16 MB DIMM, the PSDMR is configured as follows:
  *
  *     - Bank Based Interleaving,
@@ -904,7 +904,7 @@
  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
  *     - CAS Latency is 2.
  */
-#define CFG_PSDMR	(PSDMR_RFEN	      |\
+#define CONFIG_SYS_PSDMR	(PSDMR_RFEN	      |\
 			 PSDMR_SDAM_A14_IS_A5 |\
 			 PSDMR_BSMA_A16_A18   |\
 			 PSDMR_SDA10_PBI0_A9  |\
@@ -916,7 +916,7 @@
 			 PSDMR_CL_2)
 #endif
 
-#if (CFG_SDRAM0_SIZE == 64)
+#if (CONFIG_SYS_SDRAM0_SIZE == 64)
 /* With a 64 MB DIMM, the PSDMR is configured as follows:
  *
  *     - Bank Based Interleaving,
@@ -934,7 +934,7 @@
  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
  *     - CAS Latency is 2.
  */
-#define CFG_PSDMR	(PSDMR_RFEN	      |\
+#define CONFIG_SYS_PSDMR	(PSDMR_RFEN	      |\
 			 PSDMR_SDAM_A14_IS_A5 |\
 			 PSDMR_BSMA_A14_A16   |\
 			 PSDMR_SDA10_PBI0_A9  |\
@@ -950,14 +950,14 @@
  * Shoot for approximately 1MHz on the prescaler.
  */
 #if (CONFIG_8260_CLKIN == (66 * 1000 * 1000))
-#define CFG_MPTPR	MPTPR_PTP_DIV64
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV64
 #elif (CONFIG_8260_CLKIN == (33 * 1000 * 1000))
-#define CFG_MPTPR	MPTPR_PTP_DIV32
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV32
 #else
-#warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK"
-#define CFG_MPTPR	MPTPR_PTP_DIV32
+#warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK"
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV32
 #endif
-#define CFG_PSRT	14
+#define CONFIG_SYS_PSRT	14
 
 
 /* Bank 4 - On board SDRAM
@@ -978,7 +978,7 @@
  * This expects the on board FLASH SIMM to be connected to *CS6
  * It consists of 1 AM29F016A part.
  */
-#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE))
+#if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE))
 
 /* BR6 is configured as follows:
  *
@@ -992,7 +992,7 @@
  *     - No data pipelining is done
  *     - Valid
  */
-#  define CFG_BR6_PRELIM  ((CFG_FLASH1_BASE & BRx_BA_MSK) |\
+#  define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\
 			   BRx_PS_8			  |\
 			   BRx_MS_GPCM_P		  |\
 			   BRx_V)
@@ -1011,13 +1011,13 @@
  *     - One idle clock is inserted between a read access from the
  *	 current bank and the next access.
  */
-#  define CFG_OR6_PRELIM  (MEG_TO_AM(CFG_FLASH1_SIZE)  |\
+#  define CONFIG_SYS_OR6_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE)  |\
 			   ORxG_CSNT		       |\
 			   ORxG_ACS_DIV1	       |\
 			   ORxG_SCY_5_CLK	       |\
 			   ORxG_TRLX		       |\
 			   ORxG_EHTR)
-#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */
+#endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */
 
 /*-----------------------------------------------------------------------
  * BR7 - Base Register
@@ -1032,7 +1032,7 @@
  *  LEDs     are at 0x00001 (write only)
  *  switches are at 0x00001 (read only)
  */
-#ifdef CFG_LED_BASE
+#ifdef CONFIG_SYS_LED_BASE
 
 /* BR7 is configured as follows:
  *
@@ -1046,7 +1046,7 @@
  *     - No data pipelining is done
  *     - Valid
  */
-#  define CFG_BR7_PRELIM  ((CFG_LED_BASE & BRx_BA_MSK)	 |\
+#  define CONFIG_SYS_BR7_PRELIM  ((CONFIG_SYS_LED_BASE & BRx_BA_MSK)	 |\
 			   BRx_PS_8			 |\
 			   BRx_MS_GPCM_P		 |\
 			   BRx_V)
@@ -1065,13 +1065,13 @@
  *     - One idle clock is inserted between a read access from the
  *	 current bank and the next access.
  */
-#  define CFG_OR7_PRELIM  (ORxG_AM_MSK		       |\
+#  define CONFIG_SYS_OR7_PRELIM  (ORxG_AM_MSK		       |\
 			   ORxG_CSNT		       |\
 			   ORxG_ACS_DIV1	       |\
 			   ORxG_SCY_15_CLK	       |\
 			   ORxG_TRLX		       |\
 			   ORxG_EHTR)
-#endif /* CFG_LED_BASE */
+#endif /* CONFIG_SYS_LED_BASE */
 
 /*
  * Internal Definitions
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index dc5a101..f476e3e 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -63,11 +63,11 @@
 
 #undef CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
 
-#define CFG_IMMR		0xE0000000
+#define CONFIG_SYS_IMMR		0xE0000000
 
-#undef CFG_DRAM_TEST				/* memory test, takes time */
-#define CFG_MEMTEST_START	0x00000000	/* memtest region */
-#define CFG_MEMTEST_END		0x00100000
+#undef CONFIG_SYS_DRAM_TEST				/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
 
 /*
  * DDR Setup
@@ -75,7 +75,7 @@
 #undef CONFIG_DDR_ECC			/* only for ECC DDR module */
 #undef CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
 #define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
-#define CFG_83XX_DDR_USES_CS0		/* WRS; Fsl board uses CS2/CS3 */
+#define CONFIG_SYS_83XX_DDR_USES_CS0		/* WRS; Fsl board uses CS2/CS3 */
 
 /*
  * 32-bit data path mode.
@@ -89,10 +89,10 @@
  */
 #undef CONFIG_DDR_32BIT
 
-#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
-#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING
 
@@ -107,72 +107,71 @@
  * Manually set up DDR parameters
  * NB: manual DDR setup untested on sbc834x
  */
-#define CFG_DDR_SIZE		256		/* MB */
-#define CFG_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
-#define CFG_DDR_TIMING_1	0x36332321
-#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
-#define CFG_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
-#define CFG_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
+#define CONFIG_SYS_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_TIMING_1	0x36332321
+#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
 
 #if defined(CONFIG_DDR_32BIT)
 /* set burst length to 8 for 32-bit data path */
-#define CFG_DDR_MODE		0x00000023	/* DLL,normal,seq,4/2.5, 8 burst len */
+#define CONFIG_SYS_DDR_MODE		0x00000023	/* DLL,normal,seq,4/2.5, 8 burst len */
 #else
 /* the default burst length is 4 - for 64-bit data path */
-#define CFG_DDR_MODE		0x00000022	/* DLL,normal,seq,4/2.5, 4 burst len */
+#define CONFIG_SYS_DDR_MODE		0x00000022	/* DLL,normal,seq,4/2.5, 4 burst len */
 #endif
 #endif
 
 /*
  * SDRAM on the Local Bus
  */
-#define CFG_LBC_SDRAM_BASE	0x10000000	/* Localbus SDRAM */
-#define CFG_LBC_SDRAM_SIZE	128		/* LBC SDRAM is 128MB */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0x10000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	128		/* LBC SDRAM is 128MB */
 
 /*
  * FLASH on the Local Bus
  */
-#define CFG_FLASH_CFI				/* use the Common Flash Interface */
+#define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
-#define CFG_FLASH_BASE		0xFF800000	/* start of FLASH   */
-#define CFG_FLASH_SIZE		8		/* flash size in MB */
-/* #define CFG_FLASH_USE_BUFFER_WRITE */
+#define CONFIG_SYS_FLASH_BASE		0xFF800000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		8		/* flash size in MB */
+/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE |	/* flash Base address */ \
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE |	/* flash Base address */ \
 				(2 << BR_PS_SHIFT) |	/* 32 bit port size */	 \
 				BR_V)			/* valid */
 
-#define CFG_OR0_PRELIM		0xFF806FF7	/* 8 MB flash size */
-#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* window base at flash base */
-#define CFG_LBLAWAR0_PRELIM	0x80000016	/* 8 MB window size */
+#define CONFIG_SYS_OR0_PRELIM		0xFF806FF7	/* 8 MB flash size */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE	/* window base at flash base */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016	/* 8 MB window size */
 
-#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_MAX_FLASH_SECT	64		/* sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device */
 
-#undef CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MID_FLASH_JUMP	0x7F000000
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MID_FLASH_JUMP	0x7F000000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef  CFG_RAMBOOT
+#undef  CONFIG_SYS_RAMBOOT
 #endif
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xFD000000		/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x1000			/* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000		/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x1000			/* End of used area in RAM*/
 
-#define CFG_GBL_DATA_SIZE	0x100			/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100			/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)		/* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)		/* Reserved for malloc */
 
 /*
  * Local Bus LCRR and LBCR regs
@@ -180,16 +179,16 @@
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CFG_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
-#define CFG_LBC_LBCR	0x00000000
+#define CONFIG_SYS_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LBC_LBCR	0x00000000
 
-#undef CFG_LB_SDRAM	/* if board has SDRAM on local bus */
+#undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */
 
-#ifdef CFG_LB_SDRAM
+#ifdef CONFIG_SYS_LB_SDRAM
 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
 /*
  * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  *
  * For BR2, need:
  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
@@ -201,16 +200,16 @@
  * 0    4    8    12   16   20   24   28
  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
  *
- * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  * FIXME: the top 17 bits of BR2.
  */
 
-#define CFG_BR2_PRELIM		0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
-#define CFG_LBLAWBAR2_PRELIM	0xF0000000
-#define CFG_LBLAWAR2_PRELIM	0x80000019 /* 64M */
+#define CONFIG_SYS_BR2_PRELIM		0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	0xF0000000
+#define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000019 /* 64M */
 
 /*
- * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  *
  * For OR2, need:
  *    64MB mask for AM, OR2[0:7] = 1111 1100
@@ -223,65 +222,65 @@
  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
  */
 
-#define CFG_OR2_PRELIM	0xFC006901
+#define CONFIG_SYS_OR2_PRELIM	0xFC006901
 
-#define CFG_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
-#define CFG_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32 */
 
 /*
  * LSDMR masks
  */
-#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CFG_LBC_LSDMR_RFCR5	(3 << (31 - 16))
-#define CFG_LBC_LSDMR_RFCR8	(5 << (31 - 16))
-#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CFG_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
-#define CFG_LBC_LSDMR_PRETOACT6	(5 << (31 - 19))
-#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CFG_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CFG_LBC_LSDMR_WRC2	(2 << (31 - 27))
-#define CFG_LBC_LSDMR_WRC3	(3 << (31 - 27))
-#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CFG_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
-#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
-#define CFG_LBC_LSDMR_COMMON    ( CFG_LBC_LSDMR_RFEN            \
-				| CFG_LBC_LSDMR_BSMA1516	\
-				| CFG_LBC_LSDMR_RFCR8		\
-				| CFG_LBC_LSDMR_PRETOACT6	\
-				| CFG_LBC_LSDMR_ACTTORW3	\
-				| CFG_LBC_LSDMR_BL8		\
-				| CFG_LBC_LSDMR_WRC3		\
-				| CFG_LBC_LSDMR_CL3		\
+#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_RFCR5	(3 << (31 - 16))
+#define CONFIG_SYS_LBC_LSDMR_RFCR8	(5 << (31 - 16))
+#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CONFIG_SYS_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
+#define CONFIG_SYS_LBC_LSDMR_PRETOACT6	(5 << (31 - 19))
+#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CONFIG_SYS_LBC_LSDMR_WRC2	(2 << (31 - 27))
+#define CONFIG_SYS_LBC_LSDMR_WRC3	(3 << (31 - 27))
+#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CONFIG_SYS_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
+#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+#define CONFIG_SYS_LBC_LSDMR_COMMON    ( CONFIG_SYS_LBC_LSDMR_RFEN            \
+				| CONFIG_SYS_LBC_LSDMR_BSMA1516	\
+				| CONFIG_SYS_LBC_LSDMR_RFCR8		\
+				| CONFIG_SYS_LBC_LSDMR_PRETOACT6	\
+				| CONFIG_SYS_LBC_LSDMR_ACTTORW3	\
+				| CONFIG_SYS_LBC_LSDMR_BL8		\
+				| CONFIG_SYS_LBC_LSDMR_WRC3		\
+				| CONFIG_SYS_LBC_LSDMR_CL3		\
 				)
 
 /*
  * SDRAM Controller configuration sequence.
  */
-#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_PCHALL)
-#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_MRW)
-#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_NORMAL)
+#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
 #endif
 
 /*
@@ -289,22 +288,22 @@
  */
 #define CONFIG_CONS_INDEX     1
 #undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
-#define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* pass open firmware flat tree */
@@ -317,43 +316,43 @@
 #undef CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_CMD_TREE
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
-#define CFG_I2C1_OFFSET		0x3000
-#define CFG_I2C2_OFFSET		0x3100
-#define CFG_I2C_OFFSET		CFG_I2C2_OFFSET
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C1_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
+#define CONFIG_SYS_I2C_OFFSET		CONFIG_SYS_I2C2_OFFSET
 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */
 
 /* TSEC */
-#define CFG_TSEC1_OFFSET 0x24000
-#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
-#define CFG_TSEC2_OFFSET 0x25000
-#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCI1_MMIO_BASE	0x90000000
-#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
-#define CFG_PCI1_MMIO_SIZE	0x10000000	/* 256M */
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xE2000000
-#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
-
-#define CFG_PCI2_MEM_BASE	0xA0000000
-#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCI2_MMIO_BASE	0xB0000000
-#define CFG_PCI2_MMIO_PHYS	CFG_PCI2_MMIO_BASE
-#define CFG_PCI2_MMIO_SIZE	0x10000000	/* 256M */
-#define CFG_PCI2_IO_BASE	0x00000000
-#define CFG_PCI2_IO_PHYS	0xE2100000
-#define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
+#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS	0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE	0x00100000	/* 1M */
 
 #if defined(CONFIG_PCI)
 
@@ -378,7 +377,7 @@
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
 #endif	/* CONFIG_PCI */
 
@@ -412,9 +411,9 @@
 /*
  * Environment
  */
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
 	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
 	#define CONFIG_ENV_SIZE		0x2000
 
@@ -423,14 +422,14 @@
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
 #else
-	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 	#define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 
 /*
@@ -455,8 +454,8 @@
     #define CONFIG_CMD_PCI
 #endif
 
-#if defined(CFG_RAMBOOT)
-    #undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 
@@ -466,60 +465,60 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory */
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-	#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
-#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 
 #if 1 /*528/264*/
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X2 |\
 	HRCWL_CORE_TO_CSB_2X1)
 #elif 0 /*396/132*/
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X4 |\
 	HRCWL_CORE_TO_CSB_3X1)
 #elif 0 /*264/132*/
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X4 |\
 	HRCWL_CORE_TO_CSB_2X1)
 #elif 0 /*132/132*/
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X4 |\
 	HRCWL_CORE_TO_CSB_1X1)
 #elif 0 /*264/264 */
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
@@ -528,7 +527,7 @@
 #endif
 
 #if defined(PCI_64BIT)
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_64_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
@@ -541,7 +540,7 @@
 	HRCWH_TSEC1M_IN_GMII |\
 	HRCWH_TSEC2M_IN_GMII )
 #else
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_32_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
@@ -556,78 +555,78 @@
 #endif
 
 /* System IO Config */
-#define CFG_SICRH SICRH_TSOBI1
-#define CFG_SICRL SICRL_LDP_A
+#define CONFIG_SYS_SICRH SICRH_TSOBI1
+#define CONFIG_SYS_SICRL SICRL_LDP_A
 
-#define CFG_HID0_INIT	0x000000000
-#define CFG_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
 
-/* #define CFG_HID0_FINAL		(\
+/* #define CONFIG_SYS_HID0_FINAL		(\
 	HID0_ENABLE_INSTRUCTION_CACHE |\
 	HID0_ENABLE_M_BIT |\
 	HID0_ENABLE_ADDRESS_BROADCAST ) */
 
 
-#define CFG_HID2 HID2_HBE
+#define CONFIG_SYS_HID2 HID2_HBE
 
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR @ 0x00000000 */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* PCI @ 0x80000000 */
 #ifdef CONFIG_PCI
-#define CFG_IBAT1L	(CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT2L	(CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT2U	(CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #else
-#define CFG_IBAT1L	(0)
-#define CFG_IBAT1U	(0)
-#define CFG_IBAT2L	(0)
-#define CFG_IBAT2U	(0)
+#define CONFIG_SYS_IBAT1L	(0)
+#define CONFIG_SYS_IBAT1U	(0)
+#define CONFIG_SYS_IBAT2L	(0)
+#define CONFIG_SYS_IBAT2U	(0)
 #endif
 
 #ifdef CONFIG_MPC83XX_PCI2
-#define CFG_IBAT3L	(CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT3U	(CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT4L	(CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT4U	(CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #else
-#define CFG_IBAT3L	(0)
-#define CFG_IBAT3U	(0)
-#define CFG_IBAT4L	(0)
-#define CFG_IBAT4U	(0)
+#define CONFIG_SYS_IBAT3L	(0)
+#define CONFIG_SYS_IBAT3U	(0)
+#define CONFIG_SYS_IBAT4L	(0)
+#define CONFIG_SYS_IBAT4U	(0)
 #endif
 
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
-#define CFG_IBAT5L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT5U	(CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CFG_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT7L	(0)
-#define CFG_IBAT7U	(0)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
-#define CFG_DBAT4L	CFG_IBAT4L
-#define CFG_DBAT4U	CFG_IBAT4U
-#define CFG_DBAT5L	CFG_IBAT5L
-#define CFG_DBAT5U	CFG_IBAT5U
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 
 /*
  * Internal Definitions
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 9d436c6..8141a46 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -59,7 +59,6 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 #define CONFIG_CLEAR_LAW0		/* Clear LAW0 in cpu_init_r */
 
 /*
@@ -69,22 +68,22 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
 
-#undef	CFG_DRAM_TEST			/* memory test, takes time */
-#define CFG_MEMTEST_START	0x00200000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00400000
+#undef	CONFIG_SYS_DRAM_TEST			/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
 
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
-#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
-#define CFG_PCI1_ADDR	(CFG_CCSRBAR+0x8000)
-#define CFG_PCI2_ADDR	(CFG_CCSRBAR+0x9000)
-#define CFG_PCIE1_ADDR	(CFG_CCSRBAR+0xa000)
+#define CONFIG_SYS_PCI1_ADDR	(CONFIG_SYS_CCSRBAR+0x8000)
+#define CONFIG_SYS_PCI2_ADDR	(CONFIG_SYS_CCSRBAR+0x9000)
+#define CONFIG_SYS_PCIE1_ADDR	(CONFIG_SYS_CCSRBAR+0xa000)
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR2
@@ -96,8 +95,8 @@
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_VERY_BIG_RAM
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
@@ -111,7 +110,7 @@
  * Make sure required options are set
  */
 #ifndef CONFIG_SPD_EEPROM
-	#define CFG_SDRAM_SIZE	256		/* DDR is 256MB */
+	#define CONFIG_SYS_SDRAM_SIZE	256		/* DDR is 256MB */
 #endif
 
 #undef CONFIG_CLOCKS_IN_MHZ
@@ -165,47 +164,47 @@
  * 1111 1000 0000 0000 0110 1110 0110 0101 = f8006e65    OR6
  */
 
-#define CFG_BOOT_BLOCK		0xff800000	/* start of 8MB Flash */
-#define CFG_FLASH_BASE		CFG_BOOT_BLOCK	/* start of FLASH 16M */
+#define CONFIG_SYS_BOOT_BLOCK		0xff800000	/* start of 8MB Flash */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_BOOT_BLOCK	/* start of FLASH 16M */
 
-#define CFG_BR0_PRELIM		0xff800801
-#define CFG_BR6_PRELIM		0xfb801801
+#define CONFIG_SYS_BR0_PRELIM		0xff800801
+#define CONFIG_SYS_BR6_PRELIM		0xfb801801
 
-#define	CFG_OR0_PRELIM		0xff806e65
-#define	CFG_OR6_PRELIM		0xf8006e65
+#define	CONFIG_SYS_OR0_PRELIM		0xff806e65
+#define	CONFIG_SYS_OR6_PRELIM		0xf8006e65
 
-#define CFG_FLASH_BANKS_LIST	{CFG_FLASH_BASE}
-#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 /* CS5 = Local bus peripherals controlled by the EPLD */
 
-#define CFG_BR5_PRELIM		0xf8000801
-#define CFG_OR5_PRELIM		0xff006e65
-#define CFG_EPLD_BASE		0xf8000000
-#define CFG_LED_DISP_BASE	0xf8000000
-#define CFG_USER_SWITCHES_BASE	0xf8100000
-#define CFG_BD_REV		0xf8300000
-#define CFG_EEPROM_BASE		0xf8b00000
+#define CONFIG_SYS_BR5_PRELIM		0xf8000801
+#define CONFIG_SYS_OR5_PRELIM		0xff006e65
+#define CONFIG_SYS_EPLD_BASE		0xf8000000
+#define CONFIG_SYS_LED_DISP_BASE	0xf8000000
+#define CONFIG_SYS_USER_SWITCHES_BASE	0xf8100000
+#define CONFIG_SYS_BD_REV		0xf8300000
+#define CONFIG_SYS_EEPROM_BASE		0xf8b00000
 
 /*
  * SDRAM on the Local Bus
  */
-#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
-#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
 
 /*
  * Base Register 3 and Option Register 3 configure SDRAM.
- * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  *
  * For BR3, need:
  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
@@ -219,10 +218,10 @@
  *
  */
 
-#define CFG_BR3_PRELIM		0xf0001861
+#define CONFIG_SYS_BR3_PRELIM		0xf0001861
 
 /*
- * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  *
  * For OR3, need:
  *    64MB mask for AM, OR3[0:7] = 1111 1100
@@ -235,35 +234,35 @@
  * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
  */
 
-#define CFG_OR3_PRELIM		0xfc006cc0
+#define CONFIG_SYS_OR3_PRELIM		0xfc006cc0
 
-#define CFG_LBC_LCRR		0x00000002    /* LB clock ratio reg */
-#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
-#define CFG_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
-#define CFG_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
+#define CONFIG_SYS_LBC_LCRR		0x00000002    /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
 
 /*
  * LSDMR masks
  */
-#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
 
 /*
  * Common settings for all Local Bus SDRAM commands.
@@ -271,47 +270,46 @@
  *                  or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
-#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_RFCR16		\
-				| CFG_LBC_LSDMR_PRETOACT7	\
-				| CFG_LBC_LSDMR_ACTTORW7	\
-				| CFG_LBC_LSDMR_BL8		\
-				| CFG_LBC_LSDMR_WRC4		\
-				| CFG_LBC_LSDMR_CL3		\
-				| CFG_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_RFCR16		\
+				| CONFIG_SYS_LBC_LSDMR_PRETOACT7	\
+				| CONFIG_SYS_LBC_LSDMR_ACTTORW7	\
+				| CONFIG_SYS_LBC_LSDMR_BL8		\
+				| CONFIG_SYS_LBC_LSDMR_WRC4		\
+				| CONFIG_SYS_LBC_LSDMR_CL3		\
+				| CONFIG_SYS_LBC_LSDMR_RFEN		\
 				)
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_INIT_L2_ADDR	0xf8f80000	/* relocate boot L2SRAM */
+#define CONFIG_SYS_INIT_L2_ADDR	0xf8f80000	/* relocate boot L2SRAM */
 
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		400000000 /* get_bus_freq(0) */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		400000000 /* get_bus_freq(0) */
 
-#define CFG_BAUDRATE_TABLE \
+#define CONFIG_SYS_BAUDRATE_TABLE \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* pass open firmware flat tree */
@@ -325,48 +323,48 @@
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_EEPROM_ADDR	0x50
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x3000
 
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CFG_PCI_PHYS		0x80000000	/* 1G PCI TLB */
+#define CONFIG_SYS_PCI_PHYS		0x80000000	/* 1G PCI TLB */
 
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xe2000000
-#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
 
 #ifdef CONFIG_PCI2
-#define CFG_PCI2_MEM_BASE	0xa0000000
-#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI2_IO_BASE	0x00000000
-#define CFG_PCI2_IO_PHYS	0xe2800000
-#define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCI2_MEM_BASE	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS	0xe2800000
+#define CONFIG_SYS_PCI2_IO_SIZE	0x00100000	/* 1M */
 #endif
 
 #ifdef CONFIG_PCIE1
-#define CFG_PCIE1_MEM_BASE	0xa0000000
-#define CFG_PCIE1_MEM_PHYS	CFG_PCIE1_MEM_BASE
-#define CFG_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCIE1_IO_BASE	0x00000000
-#define CFG_PCIE1_IO_PHYS	0xe3000000
-#define CFG_PCIE1_IO_SIZE	0x00100000	/*   1M */
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/*   1M */
 #endif
 
 #ifdef CONFIG_RIO
 /*
  * RapidIO MMU
  */
-#define CFG_RIO_MEM_BASE	0xC0000000
-#define CFG_RIO_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_RIO_MEM_BASE	0xC0000000
+#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 512M */
 #endif
 
 #ifdef CONFIG_LEGACY
@@ -387,11 +385,6 @@
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 
-/* PCI view of System Memory */
-#define CFG_PCI_MEMORY_BUS	0x00000000
-#define CFG_PCI_MEMORY_PHYS	0x00000000
-#define CFG_PCI_MEMORY_SIZE	0x80000000
-
 #endif	/* CONFIG_PCI */
 
 
@@ -406,25 +399,16 @@
 #define CONFIG_TSEC1_NAME	"eTSEC0"
 #define CONFIG_TSEC2	1
 #define CONFIG_TSEC2_NAME	"eTSEC1"
-#define CONFIG_TSEC3	1
-#define CONFIG_TSEC3_NAME	"eTSEC2"
-#define CONFIG_TSEC4
-#define CONFIG_TSEC4_NAME	"eTSEC3"
 #undef CONFIG_MPC85XX_FEC
 
-#define TSEC1_PHY_ADDR		0
-#define TSEC2_PHY_ADDR		1
-#define TSEC3_PHY_ADDR		2
-#define TSEC4_PHY_ADDR		3
+#define TSEC1_PHY_ADDR		0x19
+#define TSEC2_PHY_ADDR		0x1a
 
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
-#define TSEC3_PHYIDX		0
-#define TSEC4_PHYIDX		0
+
 #define TSEC1_FLAGS		TSEC_GIGABIT
 #define TSEC2_FLAGS		TSEC_GIGABIT
-#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 
 /* Options are: eTSEC[0-3] */
 #define CONFIG_ETHPRIME		"eTSEC0"
@@ -435,12 +419,12 @@
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
 #define CONFIG_ENV_SIZE		0x2000
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -471,25 +455,26 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	*/
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_CMDLINE_EDITING			/* undef to save memory */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
@@ -514,10 +499,6 @@
 #define CONFIG_ETHADDR	 02:E0:0C:00:00:FD
 #define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR	 02:E0:0C:00:01:FD
-#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR	 02:E0:0C:00:02:FD
-#define CONFIG_HAS_ETH3
-#define CONFIG_ETH3ADDR	 02:E0:0C:00:03:FD
 #endif
 
 #define CONFIG_IPADDR	 192.168.0.55
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index 38ae1b1..4fa501d 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -69,13 +69,12 @@
 /* below can be toggled for performance analysis. otherwise use default */
 #define CONFIG_L2_CACHE			    /* toggle L2 cache		*/
 #undef	CONFIG_BTB			    /* toggle branch predition	*/
-#undef	CONFIG_ADDR_STREAMING		    /* toggle addr streaming	*/
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
 
-#undef	CFG_DRAM_TEST			    /* memory test, takes time	*/
-#define CFG_MEMTEST_START	0x00200000  /* memtest region */
-#define CFG_MEMTEST_END		0x00400000
+#undef	CONFIG_SYS_DRAM_TEST			    /* memory test, takes time	*/
+#define CONFIG_SYS_MEMTEST_START	0x00200000  /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
 
 #if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
      defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
@@ -87,17 +86,17 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
 
 #if XXX
-  #define CFG_CCSRBAR		0xfdf00000	/* relocated CCSRBAR	*/
+  #define CONFIG_SYS_CCSRBAR		0xfdf00000	/* relocated CCSRBAR	*/
 #else
-  #define CFG_CCSRBAR		0xff700000	/* default CCSRBAR	*/
+  #define CONFIG_SYS_CCSRBAR		0xff700000	/* default CCSRBAR	*/
 #endif
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR	*/
 
-#define CFG_SDRAM_SIZE		512		/* DDR is 512MB */
+#define CONFIG_SYS_SDRAM_SIZE		512		/* DDR is 512MB */
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR1
@@ -114,8 +113,8 @@
 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_VERY_BIG_RAM
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
@@ -128,69 +127,68 @@
 #undef CONFIG_CLOCKS_IN_MHZ
 
 #if defined(CONFIG_RAM_AS_FLASH)
-  #define CFG_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
-  #define CFG_FLASH_BASE	0xf8000000      /* start of FLASH 8M  */
-  #define CFG_BR0_PRELIM	0xf8000801      /* port size 8bit */
-  #define CFG_OR0_PRELIM	0xf8000ff7	/* 8MB Flash		*/
+  #define CONFIG_SYS_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
+  #define CONFIG_SYS_FLASH_BASE	0xf8000000      /* start of FLASH 8M  */
+  #define CONFIG_SYS_BR0_PRELIM	0xf8000801      /* port size 8bit */
+  #define CONFIG_SYS_OR0_PRELIM	0xf8000ff7	/* 8MB Flash		*/
 #else /* Boot from real Flash */
-  #define CFG_LBC_SDRAM_BASE	0xf8000000	/* Localbus SDRAM */
-  #define CFG_FLASH_BASE	0xff800000      /* start of FLASH 8M    */
-  #define CFG_BR0_PRELIM	0xff800801      /* port size 8bit      */
-  #define CFG_OR0_PRELIM	0xff800ff7	/* 8MB Flash		*/
+  #define CONFIG_SYS_LBC_SDRAM_BASE	0xf8000000	/* Localbus SDRAM */
+  #define CONFIG_SYS_FLASH_BASE	0xff800000      /* start of FLASH 8M    */
+  #define CONFIG_SYS_BR0_PRELIM	0xff800801      /* port size 8bit      */
+  #define CONFIG_SYS_OR0_PRELIM	0xff800ff7	/* 8MB Flash		*/
 #endif
-#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB	*/
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB	*/
 
 /* local bus definitions */
-#define CFG_BR1_PRELIM		0xe4001801	/* 64M, 32-bit flash */
-#define CFG_OR1_PRELIM		0xfc000ff7
+#define CONFIG_SYS_BR1_PRELIM		0xe4001801	/* 64M, 32-bit flash */
+#define CONFIG_SYS_OR1_PRELIM		0xfc000ff7
 
-#define CFG_BR2_PRELIM		0x00000000	/* CS2 not used */
-#define CFG_OR2_PRELIM		0x00000000
+#define CONFIG_SYS_BR2_PRELIM		0x00000000	/* CS2 not used */
+#define CONFIG_SYS_OR2_PRELIM		0x00000000
 
-#define CFG_BR3_PRELIM		0xf0001861	/* 64MB localbus SDRAM	*/
-#define CFG_OR3_PRELIM		0xfc000cc1
+#define CONFIG_SYS_BR3_PRELIM		0xf0001861	/* 64MB localbus SDRAM	*/
+#define CONFIG_SYS_OR3_PRELIM		0xfc000cc1
 
 #if defined(CONFIG_RAM_AS_FLASH)
-  #define CFG_BR4_PRELIM	0xf4001861	/* 64M localbus SDRAM */
+  #define CONFIG_SYS_BR4_PRELIM	0xf4001861	/* 64M localbus SDRAM */
 #else
-  #define CFG_BR4_PRELIM	0xf8001861	/* 64M localbus SDRAM */
+  #define CONFIG_SYS_BR4_PRELIM	0xf8001861	/* 64M localbus SDRAM */
 #endif
-#define CFG_OR4_PRELIM		0xfc000cc1
+#define CONFIG_SYS_OR4_PRELIM		0xfc000cc1
 
-#define CFG_BR5_PRELIM		0xfc000801	/* 16M CS5 misc devices */
+#define CONFIG_SYS_BR5_PRELIM		0xfc000801	/* 16M CS5 misc devices */
 #if 1
-  #define CFG_OR5_PRELIM	0xff000ff7
+  #define CONFIG_SYS_OR5_PRELIM	0xff000ff7
 #else
-  #define CFG_OR5_PRELIM	0xff0000f0
+  #define CONFIG_SYS_OR5_PRELIM	0xff0000f0
 #endif
 
-#define CFG_BR6_PRELIM		0xe0001801	/* 64M, 32-bit flash */
-#define CFG_OR6_PRELIM		0xfc000ff7
-#define CFG_LBC_LCRR		0x00030002	/* local bus freq	*/
-#define CFG_LBC_LBCR		0x00000000
-#define CFG_LBC_LSRT		0x20000000
-#define CFG_LBC_MRTPR		0x20000000
-#define CFG_LBC_LSDMR_1		0x2861b723
-#define CFG_LBC_LSDMR_2		0x0861b723
-#define CFG_LBC_LSDMR_3		0x0861b723
-#define CFG_LBC_LSDMR_4		0x1861b723
-#define CFG_LBC_LSDMR_5		0x4061b723
+#define CONFIG_SYS_BR6_PRELIM		0xe0001801	/* 64M, 32-bit flash */
+#define CONFIG_SYS_OR6_PRELIM		0xfc000ff7
+#define CONFIG_SYS_LBC_LCRR		0x00030002	/* local bus freq	*/
+#define CONFIG_SYS_LBC_LBCR		0x00000000
+#define CONFIG_SYS_LBC_LSRT		0x20000000
+#define CONFIG_SYS_LBC_MRTPR		0x20000000
+#define CONFIG_SYS_LBC_LSDMR_1		0x2861b723
+#define CONFIG_SYS_LBC_LSDMR_2		0x0861b723
+#define CONFIG_SYS_LBC_LSDMR_3		0x0861b723
+#define CONFIG_SYS_LBC_LSDMR_4		0x1861b723
+#define CONFIG_SYS_LBC_LSDMR_5		0x4061b723
 
 /* just hijack the MOT BCSR def for SBC8560 misc devices */
-#define CFG_BCSR		((CFG_BR5_PRELIM & 0xff000000)|0x00400000)
+#define CONFIG_SYS_BCSR		((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
 /* the size of CS5 needs to be >= 16M for TLB and LAW setups */
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0x70000000	/* Initial RAM address	*/
-#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000	/* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #undef  CONFIG_CONS_ON_SCC	/* define if console on SCC */
@@ -198,22 +196,22 @@
 
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		1843200 /* get_bus_freq(0) */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		1843200 /* get_bus_freq(0) */
 #define CONFIG_BAUDRATE		9600
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1	((CFG_BR5_PRELIM & 0xff000000)+0x00700000)
-#define CFG_NS16550_COM2	((CFG_BR5_PRELIM & 0xff000000)+0x00800000)
+#define CONFIG_SYS_NS16550_COM1	((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
+#define CONFIG_SYS_NS16550_COM2	((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* pass open firmware flat tree */
@@ -227,14 +225,14 @@
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
 
-#define CFG_PCI_MEM_BASE	0xC0000000
-#define CFG_PCI_MEM_PHYS	0xC0000000
-#define CFG_PCI_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCI_MEM_BASE	0xC0000000
+#define CONFIG_SYS_PCI_MEM_PHYS	0xC0000000
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000
 
 #ifdef CONFIG_TSEC_ENET
 
@@ -272,10 +270,10 @@
      * - Select bus for bd/buffers
      * - Full duplex
      */
-    #define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-    #define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-    #define CFG_CPMFCR_RAMTYPE	0
-    #define CFG_FCC_PSMR	(FCC_PSMR_FDE)
+    #define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+    #define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+    #define CONFIG_SYS_CPMFCR_RAMTYPE	0
+    #define CONFIG_SYS_FCC_PSMR	(FCC_PSMR_FDE)
 
   #elif (CONFIG_ETHER_INDEX == 3)
     /* need more definitions here for FE3 */
@@ -305,46 +303,46 @@
  * FLASH and environment organization
  */
 
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant	*/
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant	*/
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver	*/
 #if 0
-#define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)   */
-#define CFG_FLASH_PROTECTION		/* use hardware protection	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)   */
+#define CONFIG_SYS_FLASH_PROTECTION		/* use hardware protection	*/
 #endif
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	*/
 
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	200000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	50000	/* Timeout for Flash Write (in ms) */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	200000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	50000	/* Timeout for Flash Write (in ms) */
 
-#define CFG_MONITOR_BASE	TEXT_BASE /* start of monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE /* start of monitor	*/
 
 #if 0
 /* XXX This doesn't work and I don't want to fix it */
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-  #define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+  #define CONFIG_SYS_RAMBOOT
 #else
-  #undef  CFG_RAMBOOT
+  #undef  CONFIG_SYS_RAMBOOT
 #endif
 #endif
 
 /* Environment */
-#if !defined(CFG_RAMBOOT)
+#if !defined(CONFIG_SYS_RAMBOOT)
   #if defined(CONFIG_RAM_AS_FLASH)
     #define CONFIG_ENV_IS_NOWHERE
-    #define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + 0x100000)
+    #define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + 0x100000)
     #define CONFIG_ENV_SIZE	0x2000
   #else
     #define CONFIG_ENV_IS_IN_FLASH	1
     #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
-    #define CONFIG_ENV_ADDR	(CFG_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+    #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
     #define CONFIG_ENV_SIZE	0x2000 /* CONFIG_ENV_SECT_SIZE */
   #endif
 #else
-  #define CFG_NO_FLASH		1	/* Flash is not usable now	*/
+  #define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now	*/
   #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
-  #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
   #define CONFIG_ENV_SIZE		0x2000
 #endif
 
@@ -353,7 +351,7 @@
 #define CONFIG_BOOTDELAY	5	/* -1 disable autoboot */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 
 /*
@@ -381,8 +379,8 @@
     #define CONFIG_CMD_MII
 #endif
 
-#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
-    #undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 
@@ -392,25 +390,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"SBC8560=> " /* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"SBC8560=> " /* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-  #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+  #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-  #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+  #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x1000000	/* default load address */
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*
  * Internal Definitions
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 01003a3..1008812 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -44,10 +44,16 @@
 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
 
 #ifdef RUN_DIAG
-#define CFG_DIAG_ADDR        0xff800000
+#define CONFIG_SYS_DIAG_ADDR        0xff800000
 #endif
 
-#define CFG_RESET_ADDRESS    0xfff00100
+#define CONFIG_SYS_RESET_ADDRESS    0xfff00100
+
+/*
+ * virtual address to be used for temporary mappings.  There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA	0xe8000000
 
 #define CONFIG_PCI		1	/* Enable PCIE */
 #define CONFIG_PCI1		1	/* PCIE controler 1 (slot 1) */
@@ -76,7 +82,7 @@
 /*
  * L2CR setup -- make sure this is right for your board!
  */
-#define CFG_L2
+#define CONFIG_SYS_L2
 #define L2_INIT		0
 #define L2_ENABLE	(L2CR_L2E)
 
@@ -86,28 +92,32 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
 
-#undef	CFG_DRAM_TEST				/* memory test, takes time */
-#define CFG_MEMTEST_START	0x00200000	/* memtest region */
-#define CFG_MEMTEST_END		0x00400000
+#undef	CONFIG_SYS_DRAM_TEST				/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
 
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
-#define CFG_CCSRBAR		0xf8000000	/* relocated CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xf8000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
-#define CFG_PCI1_ADDR		(CFG_CCSRBAR+0x8000)
-#define CFG_PCI2_ADDR		(CFG_CCSRBAR+0x9000)
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
+
+#define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)
+#define CONFIG_SYS_PCI2_ADDR		(CONFIG_SYS_CCSRBAR+0x9000)
 
 /*
  * DDR Setup
  */
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory */
-#define CFG_DDR_SDRAM_BASE2	0x10000000	/* DDR bank 2 */
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
-#define CFG_SDRAM_BASE2		CFG_DDR_SDRAM_BASE2
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory */
+#define CONFIG_SYS_DDR_SDRAM_BASE2	0x10000000	/* DDR bank 2 */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_BASE2		CONFIG_SYS_DDR_SDRAM_BASE2
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
 #define CONFIG_VERY_BIG_RAM
 
 #define MPC86xx_DDR_SDRAM_CLK_CNTL
@@ -130,51 +140,51 @@
      * Manually set up DDR1 & DDR2 parameters
      */
 
-    #define CFG_SDRAM_SIZE	512		/* DDR is 512MB */
-
-    #define CFG_DDR_CS0_BNDS	0x0000000F
-    #define CFG_DDR_CS1_BNDS	0x00000000
-    #define CFG_DDR_CS2_BNDS	0x00000000
-    #define CFG_DDR_CS3_BNDS	0x00000000
-    #define CFG_DDR_CS0_CONFIG	0x80010102
-    #define CFG_DDR_CS1_CONFIG	0x00000000
-    #define CFG_DDR_CS2_CONFIG	0x00000000
-    #define CFG_DDR_CS3_CONFIG	0x00000000
-    #define CFG_DDR_TIMING_3 0x00000000
-    #define CFG_DDR_TIMING_0	0x00220802
-    #define CFG_DDR_TIMING_1	0x38377322
-    #define CFG_DDR_TIMING_2	0x002040c7
-    #define CFG_DDR_CFG_1A	0x43008008
-    #define CFG_DDR_CFG_2	0x24401000
-    #define CFG_DDR_MODE_1	0x23c00542
-    #define CFG_DDR_MODE_2	0x00000000
-    #define CFG_DDR_MODE_CTL	0x00000000
-    #define CFG_DDR_INTERVAL	0x05080100
-    #define CFG_DDR_DATA_INIT	0x00000000
-    #define CFG_DDR_CLK_CTRL	0x03800000
-    #define CFG_DDR_CFG_1B	0xC3008008
-
-    #define CFG_DDR2_CS0_BNDS	0x0010001F
-    #define CFG_DDR2_CS1_BNDS	0x00000000
-    #define CFG_DDR2_CS2_BNDS	0x00000000
-    #define CFG_DDR2_CS3_BNDS	0x00000000
-    #define CFG_DDR2_CS0_CONFIG	0x80010102
-    #define CFG_DDR2_CS1_CONFIG	0x00000000
-    #define CFG_DDR2_CS2_CONFIG	0x00000000
-    #define CFG_DDR2_CS3_CONFIG	0x00000000
-    #define CFG_DDR2_EXT_REFRESH 0x00000000
-    #define CFG_DDR2_TIMING_0	0x00220802
-    #define CFG_DDR2_TIMING_1	0x38377322
-    #define CFG_DDR2_TIMING_2	0x002040c7
-    #define CFG_DDR2_CFG_1A	0x43008008
-    #define CFG_DDR2_CFG_2	0x24401000
-    #define CFG_DDR2_MODE_1	0x23c00542
-    #define CFG_DDR2_MODE_2	0x00000000
-    #define CFG_DDR2_MODE_CTL	0x00000000
-    #define CFG_DDR2_INTERVAL	0x05080100
-    #define CFG_DDR2_DATA_INIT	0x00000000
-    #define CFG_DDR2_CLK_CTRL	0x03800000
-    #define CFG_DDR2_CFG_1B	0xC3008008
+    #define CONFIG_SYS_SDRAM_SIZE	512		/* DDR is 512MB */
+
+    #define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
+    #define CONFIG_SYS_DDR_CS1_BNDS	0x00000000
+    #define CONFIG_SYS_DDR_CS2_BNDS	0x00000000
+    #define CONFIG_SYS_DDR_CS3_BNDS	0x00000000
+    #define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102
+    #define CONFIG_SYS_DDR_CS1_CONFIG	0x00000000
+    #define CONFIG_SYS_DDR_CS2_CONFIG	0x00000000
+    #define CONFIG_SYS_DDR_CS3_CONFIG	0x00000000
+    #define CONFIG_SYS_DDR_TIMING_3 0x00000000
+    #define CONFIG_SYS_DDR_TIMING_0	0x00220802
+    #define CONFIG_SYS_DDR_TIMING_1	0x38377322
+    #define CONFIG_SYS_DDR_TIMING_2	0x002040c7
+    #define CONFIG_SYS_DDR_CFG_1A	0x43008008
+    #define CONFIG_SYS_DDR_CFG_2	0x24401000
+    #define CONFIG_SYS_DDR_MODE_1	0x23c00542
+    #define CONFIG_SYS_DDR_MODE_2	0x00000000
+    #define CONFIG_SYS_DDR_MODE_CTL	0x00000000
+    #define CONFIG_SYS_DDR_INTERVAL	0x05080100
+    #define CONFIG_SYS_DDR_DATA_INIT	0x00000000
+    #define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
+    #define CONFIG_SYS_DDR_CFG_1B	0xC3008008
+
+    #define CONFIG_SYS_DDR2_CS0_BNDS	0x0010001F
+    #define CONFIG_SYS_DDR2_CS1_BNDS	0x00000000
+    #define CONFIG_SYS_DDR2_CS2_BNDS	0x00000000
+    #define CONFIG_SYS_DDR2_CS3_BNDS	0x00000000
+    #define CONFIG_SYS_DDR2_CS0_CONFIG	0x80010102
+    #define CONFIG_SYS_DDR2_CS1_CONFIG	0x00000000
+    #define CONFIG_SYS_DDR2_CS2_CONFIG	0x00000000
+    #define CONFIG_SYS_DDR2_CS3_CONFIG	0x00000000
+    #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
+    #define CONFIG_SYS_DDR2_TIMING_0	0x00220802
+    #define CONFIG_SYS_DDR2_TIMING_1	0x38377322
+    #define CONFIG_SYS_DDR2_TIMING_2	0x002040c7
+    #define CONFIG_SYS_DDR2_CFG_1A	0x43008008
+    #define CONFIG_SYS_DDR2_CFG_2	0x24401000
+    #define CONFIG_SYS_DDR2_MODE_1	0x23c00542
+    #define CONFIG_SYS_DDR2_MODE_2	0x00000000
+    #define CONFIG_SYS_DDR2_MODE_CTL	0x00000000
+    #define CONFIG_SYS_DDR2_INTERVAL	0x05080100
+    #define CONFIG_SYS_DDR2_DATA_INIT	0x00000000
+    #define CONFIG_SYS_DDR2_CLK_CTRL	0x03800000
+    #define CONFIG_SYS_DDR2_CFG_1B	0xC3008008
 
 
 #endif
@@ -185,88 +195,88 @@
 /*
  * The SBC8641D contains 16MB flash space at ff000000.
  */
-#define CFG_FLASH_BASE      0xff000000  /* start of FLASH 16M */
+#define CONFIG_SYS_FLASH_BASE      0xff000000  /* start of FLASH 16M */
 
 /* Flash */
-#define CFG_BR0_PRELIM		0xff001001	/* port size 16bit */
-#define CFG_OR0_PRELIM		0xff006e65	/* 16MB Boot Flash area */
+#define CONFIG_SYS_BR0_PRELIM		0xff001001	/* port size 16bit */
+#define CONFIG_SYS_OR0_PRELIM		0xff006e65	/* 16MB Boot Flash area */
 
 /* 64KB EEPROM */
-#define CFG_BR1_PRELIM		0xf0000801	/* port size 16bit */
-#define CFG_OR1_PRELIM		0xffff6e65	/* 64K EEPROM area */
+#define CONFIG_SYS_BR1_PRELIM		0xf0000801	/* port size 16bit */
+#define CONFIG_SYS_OR1_PRELIM		0xffff6e65	/* 64K EEPROM area */
 
 /* EPLD - User switches, board id, LEDs */
-#define CFG_BR2_PRELIM		0xf1000801	/* port size 16bit */
-#define CFG_OR2_PRELIM		0xfff06e65	/* EPLD (switches, board ID, LEDs) area */
+#define CONFIG_SYS_BR2_PRELIM		0xf1000801	/* port size 16bit */
+#define CONFIG_SYS_OR2_PRELIM		0xfff06e65	/* EPLD (switches, board ID, LEDs) area */
 
 /* Local bus SDRAM 128MB */
-#define CFG_BR3_PRELIM		0xe0001861	/* port size ?bit */
-#define CFG_OR3_PRELIM		0xfc006cc0	/* 128MB local bus SDRAM area (1st half) */
-#define CFG_BR4_PRELIM		0xe4001861	/* port size ?bit */
-#define CFG_OR4_PRELIM		0xfc006cc0	/* 128MB local bus SDRAM area (2nd half) */
+#define CONFIG_SYS_BR3_PRELIM		0xe0001861	/* port size ?bit */
+#define CONFIG_SYS_OR3_PRELIM		0xfc006cc0	/* 128MB local bus SDRAM area (1st half) */
+#define CONFIG_SYS_BR4_PRELIM		0xe4001861	/* port size ?bit */
+#define CONFIG_SYS_OR4_PRELIM		0xfc006cc0	/* 128MB local bus SDRAM area (2nd half) */
 
 /* Disk on Chip (DOC) 128MB */
-#define CFG_BR5_PRELIM		0xe8001001	/* port size ?bit */
-#define CFG_OR5_PRELIM		0xf8006e65	/* 128MB local bus SDRAM area (2nd half) */
+#define CONFIG_SYS_BR5_PRELIM		0xe8001001	/* port size ?bit */
+#define CONFIG_SYS_OR5_PRELIM		0xf8006e65	/* 128MB local bus SDRAM area (2nd half) */
 
 /* LCD */
-#define CFG_BR6_PRELIM		0xf4000801	/* port size ?bit */
-#define CFG_OR6_PRELIM		0xfff06e65	/* 128MB local bus SDRAM area (2nd half) */
+#define CONFIG_SYS_BR6_PRELIM		0xf4000801	/* port size ?bit */
+#define CONFIG_SYS_OR6_PRELIM		0xfff06e65	/* 128MB local bus SDRAM area (2nd half) */
 
 /* Control logic & misc peripherals */
-#define CFG_BR7_PRELIM		0xf2000801	/* port size ?bit */
-#define CFG_OR7_PRELIM		0xfff06e65	/* 128MB local bus SDRAM area (2nd half) */
+#define CONFIG_SYS_BR7_PRELIM		0xf2000801	/* port size ?bit */
+#define CONFIG_SYS_OR7_PRELIM		0xfff06e65	/* 128MB local bus SDRAM area (2nd half) */
 
-#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_MAX_FLASH_SECT	131		/* sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	131		/* sectors per device */
 
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_WRITE_SWAPPED_DATA
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_PROTECTION
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#ifndef CFG_INIT_RAM_LOCK
-#define CFG_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#ifndef CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
 #else
-#define CFG_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
 #endif
-#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /*
@@ -276,8 +286,8 @@
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
-#define CFG_64BIT_VSPRINTF	1
-#define CFG_64BIT_STRTOUL	1
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
 
 /*
  * I2C
@@ -285,46 +295,45 @@
 #define	CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define	CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
-#define CFG_I2C_OFFSET		0x3100
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3100
 
 /*
  * RapidIO MMU
  */
-#define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
-#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
-#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M */
+#define CONFIG_SYS_RIO_MEM_BASE	0xc0000000	/* base address */
+#define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BASE
+#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
 
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0xe2000000
-#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
-
-/* PCI view of System Memory */
-#define CFG_PCI_MEMORY_BUS      0x00000000
-#define CFG_PCI_MEMORY_PHYS     0x00000000
-#define CFG_PCI_MEMORY_SIZE     0x80000000
-
-#define CFG_PCI2_MEM_BASE	0xa0000000
-#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCI2_IO_BASE	0xe3000000
-#define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
-#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_VIRT	CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_BUS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BUS
+#define CONFIG_SYS_PCI1_IO_VIRT	CONFIG_SYS_PCI1_IO_BUS
+#define CONFIG_SYS_PCI1_IO_SIZE	0x1000000	/* 16M */
+
+#define CONFIG_SYS_PCI2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BUS
+#define CONFIG_SYS_PCI2_MEM_VIRT	CONFIG_SYS_PCI2_MEM_BUS
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_IO_BUS	0xe3000000
+#define CONFIG_SYS_PCI2_IO_PHYS	CONFIG_SYS_PCI2_IO_BUS
+#define CONFIG_SYS_PCI2_IO_VIRT	CONFIG_SYS_PCI2_IO_BUS
+#define CONFIG_SYS_PCI2_IO_SIZE	0x1000000	/* 16M */
 
 #if defined(CONFIG_PCI)
 
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 
-#undef CFG_SCSI_SCAN_BUS_REVERSE
+#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
 
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
@@ -345,10 +354,10 @@
 
 #ifdef CONFIG_SCSI_AHCI
 #define CONFIG_SATA_ULI5288
-#define CFG_SCSI_MAX_SCSI_ID	4
-#define CFG_SCSI_MAX_LUN	1
-#define CFG_SCSI_MAX_DEVICE	(CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
-#define CFG_SCSI_MAXDEVICE	CFG_SCSI_MAX_DEVICE
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
+#define CONFIG_SYS_SCSI_MAX_LUN	1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
 #endif
 
 #endif	/* CONFIG_PCI */
@@ -383,7 +392,7 @@
 #define TSEC3_FLAGS		TSEC_GIGABIT
 #define TSEC4_FLAGS		TSEC_GIGABIT
 
-#define CFG_TBIPA_VALUE	0x1e	/* Set TBI address not to conflict with TSEC1_PHY_ADDR */
+#define CONFIG_SYS_TBIPA_VALUE	0x1e	/* Set TBI address not to conflict with TSEC1_PHY_ADDR */
 
 #define CONFIG_ETHPRIME		"eTSEC1"
 
@@ -393,10 +402,10 @@
  * BAT0         2G     Cacheable, non-guarded
  * 0x0000_0000  2G     DDR
  */
-#define CFG_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_DBAT0U	(BATU_BL_2G | BATU_VS | BATU_VP)
-#define CFG_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE )
-#define CFG_IBAT0U	CFG_DBAT0U
+#define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT0U	(BATU_BL_2G | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE )
+#define CONFIG_SYS_IBAT0U	CONFIG_SYS_DBAT0U
 
 /*
  * BAT1         1G     Cache-inhibited, guarded
@@ -404,31 +413,42 @@
  * 0xa000_0000  512M   PCI-Express 2 Memory
  *	Changed it for operating from 0xd0000000
  */
-#define CFG_DBAT1L	( CFG_PCI1_MEM_BASE | BATL_PP_RW \
+#define CONFIG_SYS_DBAT1L	( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT1U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT1L	(CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT1U	CFG_DBAT1U
+#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
 
 /*
  * BAT2         512M   Cache-inhibited, guarded
  * 0xc000_0000  512M   RapidIO Memory
  */
-#define CFG_DBAT2L	(CFG_RIO_MEM_BASE | BATL_PP_RW \
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U	(CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
-#define CFG_IBAT2L	(CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	CFG_DBAT2U
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
 
 /*
  * BAT3         4M     Cache-inhibited, guarded
  * 0xf800_0000  4M     CCSR
  */
-#define CFG_DBAT3L	( CFG_CCSRBAR | BATL_PP_RW \
+#define CONFIG_SYS_DBAT3L	( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U	(CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
-#define CFG_IBAT3L	(CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	CFG_DBAT3U
+#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
+
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT \
+				       | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
 
 /*
  * BAT4         32M    Cache-inhibited, guarded
@@ -436,46 +456,54 @@
  * 0xe300_0000  16M    PCI-Express 2 I/0
  *    Note that this is at 0xe0000000
  */
-#define CFG_DBAT4L	( CFG_PCI1_IO_BASE | BATL_PP_RW \
+#define CONFIG_SYS_DBAT4L	( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT4U	(CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_IBAT4L	(CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT4U	CFG_DBAT4U
+#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
 
 /*
  * BAT5         128K   Cacheable, non-guarded
  * 0xe401_0000  128K   Init RAM for stack in the CPU DCache (no backing memory)
  */
-#define CFG_DBAT5L	(CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_DBAT5U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_IBAT5L	CFG_DBAT5L
-#define CFG_IBAT5U	CFG_DBAT5U
+#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
+#define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
 
 /*
  * BAT6         32M    Cache-inhibited, guarded
  * 0xfe00_0000  32M    FLASH
  */
-#define CFG_DBAT6L	((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
+#define CONFIG_SYS_DBAT6L	((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT6U	((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_IBAT6L	((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U	CFG_DBAT6U
-
-#define CFG_DBAT7L	0x00000000
-#define CFG_DBAT7U	0x00000000
-#define CFG_IBAT7L	0x00000000
-#define CFG_IBAT7U	0x00000000
+#define CONFIG_SYS_DBAT6U	((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L	((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
+
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY	(TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
+
+#define CONFIG_SYS_DBAT7L	0x00000000
+#define CONFIG_SYS_DBAT7U	0x00000000
+#define CONFIG_SYS_IBAT7L	0x00000000
+#define CONFIG_SYS_IBAT7U	0x00000000
 
 /*
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
 #define CONFIG_ENV_SIZE		0x2000
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 #include <config_cmd_default.h>
     #define CONFIG_CMD_PING
@@ -491,33 +519,33 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	*/
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /* Cache Configuration */
-#define CFG_DCACHE_SIZE		32768
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_DCACHE_SIZE		32768
+#define CONFIG_SYS_CACHELINE_SIZE	32
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
 #endif
 
 /*
diff --git a/include/configs/sc3.h b/include/configs/sc3.h
index 88a24b8..515b097 100644
--- a/include/configs/sc3.h
+++ b/include/configs/sc3.h
@@ -128,7 +128,7 @@
 #undef CONFIG_BOOTCOMMAND
 
 #define CONFIG_SILENT_CONSOLE	1	/* enable silent startup */
-#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
 #if 1	/* feel free to disable for development */
 #define CONFIG_AUTOBOOT_KEYED		/* Enable password protection	*/
@@ -160,12 +160,14 @@
 #undef CONFIG_ISP1161_PRESENT
 
 #undef CONFIG_LOADS_ECHO   /* no echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_NET_MULTI
 /* #define CONFIG_EEPRO100_SROM_WRITE */
 /* #define CONFIG_SHOW_MAC */
 #define CONFIG_EEPRO100
+
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII 1			/* add 405GP MII PHY management		*/
 #define CONFIG_PHY_ADDR 1	/* the connected Phy defaults to address 1 */
 
@@ -205,42 +207,42 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP	1		/* undef to save memory		*/
-#define CFG_PROMPT	"SC3> "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_LONGHELP	1		/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"SC3> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
 /*
- * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
  * The Linux BASE_BAUD define should match this configuration.
  *    baseBaud = cpuClock/(uartDivisor*16)
- * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  * set Linux BASE_BAUD to 403200.
  *
  * Consider the OPB clock! If it get lower the BASE_BAUD must be lower to
  * (see 405GP datasheet for descritpion)
  */
-#undef	CFG_EXT_SERIAL_CLOCK		/* external serial clock */
-#undef	CFG_405_UART_ERRATA_59		/* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD		921600	/* internal clock */
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK		/* external serial clock */
+#undef	CONFIG_SYS_405_UART_ERRATA_59		/* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		921600	/* internal clock */
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
-#define CFG_LOAD_ADDR		0x1000000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x1000000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
 /*-----------------------------------------------------------------------
  * IIC stuff
@@ -253,11 +255,11 @@
 #define I2C_ACTIVE 0
 #define I2C_TRISTATE 0
 
-#define CFG_I2C_SPEED		100000	/* use the standard 100kHz speed */
-#define CFG_I2C_SLAVE		0x7F		/* mask valid bits */
+#define CONFIG_SYS_I2C_SPEED		100000	/* use the standard 100kHz speed */
+#define CONFIG_SYS_I2C_SLAVE		0x7F		/* mask valid bits */
 
 #define CONFIG_RTC_DS1337
-#define CFG_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -275,14 +277,14 @@
 /* If you want to see, whats connected to your PCI bus */
 /* #define CONFIG_PCI_SCAN_SHOW */
 
-#define CFG_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * External peripheral base address
@@ -306,103 +308,103 @@
 
 #define	CONFIG_ATAPI
 #define	CONFIG_DOS_PARTITION
-#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define	CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 
 #ifndef IDE_USES_ISA_EMULATION
 
 /* New and faster access */
-#define	CFG_ATA_BASE_ADDR		0x7A000000	/* start of ISA IO emulation */
+#define	CONFIG_SYS_ATA_BASE_ADDR		0x7A000000	/* start of ISA IO emulation */
 
 /* How many IDE busses are available */
-#define	CFG_IDE_MAXBUS		1
+#define	CONFIG_SYS_IDE_MAXBUS		1
 
 /* What IDE ports are available */
-#define	CFG_ATA_IDE0_OFFSET	0x000		/* first is available */
-#undef	CFG_ATA_IDE1_OFFSET			/* second not available */
+#define	CONFIG_SYS_ATA_IDE0_OFFSET	0x000		/* first is available */
+#undef	CONFIG_SYS_ATA_IDE1_OFFSET			/* second not available */
 
 /* access to the data port is calculated:
-   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
+   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
 
 /* access to the registers is calculated:
-   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
-#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */
+#define	CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
 
 /* access to the alternate register is calculated:
-   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
-#define CFG_ATA_ALT_OFFSET	0x008		/* Offset for alternate registers	*/
+   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x008		/* Offset for alternate registers	*/
 
 #else /* IDE_USES_ISA_EMULATION */
 
-#define	CFG_ATA_BASE_ADDR		0x79000000	/* start of ISA IO emulation */
+#define	CONFIG_SYS_ATA_BASE_ADDR		0x79000000	/* start of ISA IO emulation */
 
 /* How many IDE busses are available */
-#define	CFG_IDE_MAXBUS		1
+#define	CONFIG_SYS_IDE_MAXBUS		1
 
 /* What IDE ports are available */
-#define	CFG_ATA_IDE0_OFFSET	0x01F0	/* first is available */
-#undef	CFG_ATA_IDE1_OFFSET				/* second not available */
+#define	CONFIG_SYS_ATA_IDE0_OFFSET	0x01F0	/* first is available */
+#undef	CONFIG_SYS_ATA_IDE1_OFFSET				/* second not available */
 
 /* access to the data port is calculated:
-   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
-#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
+   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
 
 /* access to the registers is calculated:
-   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
-#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */
+#define	CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
 
 /* access to the alternate register is calculated:
-   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
-#define CFG_ATA_ALT_OFFSET	0x03F0		/* Offset for alternate registers	*/
+   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x03F0		/* Offset for alternate registers	*/
 
 #endif /* IDE_USES_ISA_EMULATION */
 
 #endif
 
 /*
-#define	CFG_KEY_REG_BASE_ADDR	0xF0100000
-#define	CFG_IR_REG_BASE_ADDR	0xF0200000
-#define	CFG_FPGA_REG_BASE_ADDR	0xF0300000
+#define	CONFIG_SYS_KEY_REG_BASE_ADDR	0xF0100000
+#define	CONFIG_SYS_IR_REG_BASE_ADDR	0xF0200000
+#define	CONFIG_SYS_FPGA_REG_BASE_ADDR	0xF0300000
 */
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  *
- * CFG_FLASH_BASE   -> start address of internal flash
- * CFG_MONITOR_BASE -> start of u-boot
+ * CONFIG_SYS_FLASH_BASE   -> start address of internal flash
+ * CONFIG_SYS_MONITOR_BASE -> start of u-boot
  */
 #ifndef __ASSEMBLER__
 extern unsigned long offsetOfBigFlash;
 extern unsigned long offsetOfEnvironment;
 #endif
 
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFE00000
-#define CFG_MONITOR_BASE	0xFFFC0000     /* placed last 256k */
-#define CFG_MONITOR_LEN		(224 * 1024)	/* Reserve 224 KiB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 KiB for malloc()	*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFE00000
+#define CONFIG_SYS_MONITOR_BASE	0xFFFC0000     /* placed last 256k */
+#define CONFIG_SYS_MONITOR_LEN		(224 * 1024)	/* Reserve 224 KiB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 KiB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MiB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization ## FIXME: lookup in datasheet
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_CFI			/* flash is CFI compat.	*/
+#define CONFIG_SYS_FLASH_CFI			/* flash is CFI compat.	*/
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver*/
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
-#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-#define CFG_WRITE_SWAPPED_DATA		/* swap Databytes between reading/writing */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_WRITE_SWAPPED_DATA		/* swap Databytes between reading/writing */
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #ifdef CONFIG_ENV_IS_IN_FLASH
@@ -421,9 +423,8 @@ extern unsigned long offsetOfEnvironment;
 /*
  * NAND-FLASH stuff
  */
-#define CFG_MAX_NAND_DEVICE	1
-#define NAND_MAX_CHIPS		1
-#define CFG_NAND_BASE		0x77D00000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x77D00000
 
 
 #define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
@@ -439,55 +440,55 @@ extern unsigned long offsetOfEnvironment;
  *
  */
 
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE
 #define FLASH_BASE1_PRELIM	0
 
 /*-----------------------------------------------------------------------
  * Some informations about the internal SRAM (OCM=On Chip Memory)
  *
- * CFG_OCM_DATA_ADDR -> location
- * CFG_OCM_DATA_SIZE -> size
+ * CONFIG_SYS_OCM_DATA_ADDR -> location
+ * CONFIG_SYS_OCM_DATA_SIZE -> size
 */
 
-#define CFG_TEMP_STACK_OCM	1
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM):
  * - we are using the internal 4k SRAM, so we don't need data cache mapping
- * - internal SRAM (OCM=On Chip Memory) is placed to CFG_OCM_DATA_ADDR
+ * - internal SRAM (OCM=On Chip Memory) is placed to CONFIG_SYS_OCM_DATA_ADDR
  * - Stackpointer will be located to
- *   (CFG_INIT_RAM_ADDR&0xFFFF0000) | (CFG_INIT_SP_OFFSET&0x0000FFFF)
+ *   (CONFIG_SYS_INIT_RAM_ADDR&0xFFFF0000) | (CONFIG_SYS_INIT_SP_OFFSET&0x0000FFFF)
  *   in cpu/ppc4xx/start.S
  */
 
-#undef CFG_INIT_DCACHE_CS
+#undef CONFIG_SYS_INIT_DCACHE_CS
 /* Where the internal SRAM starts */
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR
 /* Where the internal SRAM ends (only offset) */
-#define CFG_INIT_RAM_END	0x0F00
+#define CONFIG_SYS_INIT_RAM_END	0x0F00
 
 /*
 
- CFG_INIT_RAM_ADDR ------> ------------ lower address
+ CONFIG_SYS_INIT_RAM_ADDR ------> ------------ lower address
 			   |	      |
 			   |  ^       |
 			   |  |       |
 			   |  | Stack |
- CFG_GBL_DATA_OFFSET ----> ------------
+ CONFIG_SYS_GBL_DATA_OFFSET ----> ------------
 			   |	      |
 			   | 64 Bytes |
 			   |	      |
- CFG_INIT_RAM_END  ------> ------------ higher address
+ CONFIG_SYS_INIT_RAM_END  ------> ------------ higher address
   (offset only)
 
 */
 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_SIZE     64
-#define CFG_GBL_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_SIZE     64
+#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 /* Initial value of the stack pointern in internal SRAM */
-#define CFG_INIT_SP_OFFSET    CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Internal Definitions
@@ -504,31 +505,31 @@ extern unsigned long offsetOfEnvironment;
 /* This chip select accesses the boot device */
 /* It depends on boot select switch if this device is 16 or 8 bit */
 
-#undef CFG_EBC_PB0AP
-#undef CFG_EBC_PB0CR
+#undef CONFIG_SYS_EBC_PB0AP
+#undef CONFIG_SYS_EBC_PB0CR
 
-#undef CFG_EBC_PB1AP
-#undef CFG_EBC_PB1CR
+#undef CONFIG_SYS_EBC_PB1AP
+#undef CONFIG_SYS_EBC_PB1CR
 
-#undef CFG_EBC_PB2AP
-#undef CFG_EBC_PB2CR
+#undef CONFIG_SYS_EBC_PB2AP
+#undef CONFIG_SYS_EBC_PB2CR
 
-#undef CFG_EBC_PB3AP
-#undef CFG_EBC_PB3CR
+#undef CONFIG_SYS_EBC_PB3AP
+#undef CONFIG_SYS_EBC_PB3CR
 
-#undef CFG_EBC_PB4AP
-#undef CFG_EBC_PB4CR
+#undef CONFIG_SYS_EBC_PB4AP
+#undef CONFIG_SYS_EBC_PB4CR
 
-#undef CFG_EBC_PB5AP
-#undef CFG_EBC_PB5CR
+#undef CONFIG_SYS_EBC_PB5AP
+#undef CONFIG_SYS_EBC_PB5CR
 
-#undef CFG_EBC_PB6AP
-#undef CFG_EBC_PB6CR
+#undef CONFIG_SYS_EBC_PB6AP
+#undef CONFIG_SYS_EBC_PB6CR
 
-#undef CFG_EBC_PB7AP
-#undef CFG_EBC_PB7CR
+#undef CONFIG_SYS_EBC_PB7AP
+#undef CONFIG_SYS_EBC_PB7CR
 
-#define CFG_EBC_CFG    0xb84ef000
+#define CONFIG_SYS_EBC_CFG    0xb84ef000
 
 #define CONFIG_SDRAM_BANK0	/* use the standard SDRAM initialization */
 #undef CONFIG_SPD_EEPROM
@@ -543,15 +544,15 @@ extern unsigned long offsetOfEnvironment;
  * External peripheral base address
  ***********************************************************************/
 
-#define CFG_ISA_MEM_BASE_ADDRESS 0x78000000
+#define CONFIG_SYS_ISA_MEM_BASE_ADDRESS 0x78000000
 /*
  Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu.
  Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die
  das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen
  auf ISA- und PCI-Zyklen)
  */
-#define CFG_ISA_IO_BASE_ADDRESS  0xE8000000
-/*#define CFG_ISA_IO_BASE_ADDRESS  0x79000000 */
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS  0xE8000000
+/*#define CONFIG_SYS_ISA_IO_BASE_ADDRESS  0x79000000 */
 
 /************************************************************
  * Video support
diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h
index 0042e30..9f2357b 100644
--- a/include/configs/sc520_cdp.h
+++ b/include/configs/sc520_cdp.h
@@ -38,24 +38,23 @@
 #define CONFIG_SC520		1	/* Include support for AMD SC520 */
 #define CONFIG_ALI152X		1	/* Include support for Ali 152x SIO */
 
-#define CFG_SDRAM_PRECHARGE_DELAY 6     /* 6T */
-#define CFG_SDRAM_REFRESH_RATE    78    /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
-#define CFG_SDRAM_RAS_CAS_DELAY   3     /* 3T */
+#define CONFIG_SYS_SDRAM_PRECHARGE_DELAY 6     /* 6T */
+#define CONFIG_SYS_SDRAM_REFRESH_RATE    78    /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
+#define CONFIG_SYS_SDRAM_RAS_CAS_DELAY   3     /* 3T */
 
 /* define at most one of these */
-#undef CFG_SDRAM_CAS_LATENCY_2T
-#define CFG_SDRAM_CAS_LATENCY_3T
-
-#define CFG_SC520_HIGH_SPEED    0       /* 100 or 133MHz */
-#define CFG_RESET_GENERIC       1       /* use tripple-fault to reset cpu */
-#undef  CFG_RESET_SC520                 /* use SC520 MMCR's to reset cpu */
-#undef  CFG_TIMER_SC520                 /* use SC520 swtimers */
-#define CFG_TIMER_GENERIC       1       /* use the i8254 PIT timers */
-#undef  CFG_TIMER_TSC                   /* use the Pentium TSC timers */
-#define  CFG_USE_SIO_UART       0       /* prefer the uarts on the SIO to those
+#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
+#define CONFIG_SYS_SDRAM_CAS_LATENCY_3T
+
+#define CONFIG_SYS_SC520_HIGH_SPEED    0       /* 100 or 133MHz */
+#undef  CONFIG_SYS_RESET_SC520                 /* use SC520 MMCR's to reset cpu */
+#undef  CONFIG_SYS_TIMER_SC520                 /* use SC520 swtimers */
+#define CONFIG_SYS_TIMER_GENERIC       1       /* use the i8254 PIT timers */
+#undef  CONFIG_SYS_TIMER_TSC                   /* use the Pentium TSC timers */
+#define  CONFIG_SYS_USE_SIO_UART       0       /* prefer the uarts on the SIO to those
 					 * in the SC520 on the CDP */
 
-#define CFG_STACK_SIZE          0x8000  /* Size of bootloader stack */
+#define CONFIG_SYS_STACK_SIZE          0x8000  /* Size of bootloader stack */
 
 #define CONFIG_SHOW_BOOT_PROGRESS 1
 #define CONFIG_LAST_STAGE_INIT    1
@@ -103,24 +102,24 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"boot > "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"boot > "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x01000000	/* 1 ... 16 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x01000000	/* 1 ... 16 MB in DRAM	*/
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ			1024		/* incrementer freq: 1kHz */
+#define	CONFIG_SYS_HZ			1024		/* incrementer freq: 1kHz */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
@@ -130,12 +129,12 @@
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	3	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define CONFIG_SPI_EEPROM      /* Support for SPI EEPROMs (AT25128) */
 #define CONFIG_MW_EEPROM       /* Support for MicroWire EEPROMs (AT93LC46) */
@@ -181,14 +180,14 @@
 *SATA/Native Stuff
 ************************************************************/
 #ifndef GRUSS_TESTING
-#define CFG_SATA_MAXBUS         2       /*Max Sata buses supported */
-#define CFG_SATA_DEVS_PER_BUS   2      /*Max no. of devices per bus/port */
-#define CFG_SATA_MAX_DEVICE     (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS)
+#define CONFIG_SYS_SATA_MAXBUS         2       /*Max Sata buses supported */
+#define CONFIG_SYS_SATA_DEVS_PER_BUS   2      /*Max no. of devices per bus/port */
+#define CONFIG_SYS_SATA_MAX_DEVICE     (CONFIG_SYS_SATA_MAXBUS* CONFIG_SYS_SATA_DEVS_PER_BUS)
 #define CONFIG_ATA_PIIX		1       /*Supports ata_piix driver */
 #else
-#undef CFG_SATA_MAXBUS
-#undef CFG_SATA_DEVS_PER_BUS
-#undef CFG_SATA_MAX_DEVICE
+#undef CONFIG_SYS_SATA_MAXBUS
+#undef CONFIG_SYS_SATA_DEVS_PER_BUS
+#undef CONFIG_SYS_SATA_MAX_DEVICE
 #undef CONFIG_ATA_PIIX
 #endif
 
@@ -209,7 +208,7 @@
 #undef CONFIG_VIDEO
 #endif
 #define CONFIG_I8042_KBD
-#define CFG_ISA_IO 0
+#define CONFIG_SYS_ISA_IO 0
 
 /************************************************************
  * RTC
@@ -225,10 +224,10 @@
 #define CONFIG_PCI_PNP                            /* pci plug-and-play */
 #define CONFIG_PCI_SCAN_SHOW
 
-#define	CFG_FIRST_PCI_IRQ   10
-#define	CFG_SECOND_PCI_IRQ  9
-#define CFG_THIRD_PCI_IRQ   11
-#define	CFG_FORTH_PCI_IRQ   15
+#define	CONFIG_SYS_FIRST_PCI_IRQ   10
+#define	CONFIG_SYS_SECOND_PCI_IRQ  9
+#define CONFIG_SYS_THIRD_PCI_IRQ   11
+#define	CONFIG_SYS_FORTH_PCI_IRQ   15
 #else
 #undef CONFIG_PCI
 #undef CONFIG_PCI_PNP
diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h
index 4e5798c..50af732 100644
--- a/include/configs/sc520_spunk.h
+++ b/include/configs/sc520_spunk.h
@@ -36,22 +36,21 @@
 #define CONFIG_X86		1	/* This is a X86 CPU		*/
 #define CONFIG_SC520		1	/* Include support for AMD SC520 */
 
-#define CFG_SDRAM_PRECHARGE_DELAY 6     /* 6T */
-#define CFG_SDRAM_REFRESH_RATE    78    /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
-#define CFG_SDRAM_RAS_CAS_DELAY   3     /* 3T */
+#define CONFIG_SYS_SDRAM_PRECHARGE_DELAY 6     /* 6T */
+#define CONFIG_SYS_SDRAM_REFRESH_RATE    78    /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
+#define CONFIG_SYS_SDRAM_RAS_CAS_DELAY   3     /* 3T */
 
 /* define at most one of these */
-#undef CFG_SDRAM_CAS_LATENCY_2T
-#define CFG_SDRAM_CAS_LATENCY_3T
+#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
+#define CONFIG_SYS_SDRAM_CAS_LATENCY_3T
 
-#define CFG_SC520_HIGH_SPEED    0       /* 100 or 133MHz */
-#define CFG_RESET_GENERIC       1       /* use tripple-fault to reset cpu */
-#undef  CFG_RESET_SC520                 /* use SC520 MMCR's to reset cpu */
-#undef  CFG_TIMER_SC520                 /* use SC520 swtimers */
-#define CFG_TIMER_GENERIC       1       /* use the i8254 PIT timers */
-#undef  CFG_TIMER_TSC                   /* use the Pentium TSC timers */
+#define CONFIG_SYS_SC520_HIGH_SPEED    0       /* 100 or 133MHz */
+#undef  CONFIG_SYS_RESET_SC520                 /* use SC520 MMCR's to reset cpu */
+#undef  CONFIG_SYS_TIMER_SC520                 /* use SC520 swtimers */
+#define CONFIG_SYS_TIMER_GENERIC       1       /* use the i8254 PIT timers */
+#undef  CONFIG_SYS_TIMER_TSC                   /* use the Pentium TSC timers */
 
-#define CFG_STACK_SIZE          0x8000  /* Size of bootloader stack */
+#define CONFIG_SYS_STACK_SIZE          0x8000  /* Size of bootloader stack */
 
 #define CONFIG_SHOW_BOOT_PROGRESS 1
 #define CONFIG_LAST_STAGE_INIT    1
@@ -104,24 +103,24 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"boot > "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"boot > "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x01000000	/* 1 ... 16 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x01000000	/* 1 ... 16 MB in DRAM	*/
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ			1024		/* incrementer freq: 1kHz */
+#define	CONFIG_SYS_HZ			1024		/* incrementer freq: 1kHz */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 
 /*-----------------------------------------------------------------------
@@ -134,12 +133,12 @@
  */
 
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 
 #define CONFIG_SPI_EEPROM       /* SPI EEPROMs such as AT25010 or AT25640 */
@@ -192,31 +191,31 @@
  */
 #define CONFIG_NET_MULTI        /* Multi ethernet cards support */
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
 
 /************************************************************
  * IDE/ATA stuff
  ************************************************************/
-#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-#define CFG_ATA_BASE_ADDR       0
-#define CFG_ATA_IDE0_OFFSET	0x01f0	/* ide0 offset */
-#define CFG_ATA_IDE1_OFFSET	0xe000	/* ide1 offset */
-#define CFG_ATA_DATA_OFFSET	0	/* data reg offset	*/
-#define CFG_ATA_REG_OFFSET	0	/* reg offset */
-#define CFG_ATA_ALT_OFFSET	0x200	/* alternate register offset */
+#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+#define CONFIG_SYS_ATA_BASE_ADDR       0
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x01f0	/* ide0 offset */
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0xe000	/* ide1 offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0	/* data reg offset	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0	/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x200	/* alternate register offset */
 
-#define CFG_FIRST_PCMCIA_BUS    1
+#define CONFIG_SYS_FIRST_PCMCIA_BUS    1
 
 #undef	CONFIG_IDE_LED			/* no led for ide supported	*/
 #undef  CONFIG_IDE_RESET		/* reset for ide unsupported...	*/
 #undef  CONFIG_IDE_RESET_ROUTINE	/* no special reset function */
 
 #define CONFIG_IDE_TI_CARDBUS
-#define CFG_PCMCIA_CIS_WIN          0x27f00000
-#define CFG_PCMCIA_CIS_WIN_SIZE     0x00100000
-#define CFG_PCMCIA_IO_WIN           0xe000
-#define CFG_PCMCIA_IO_WIN_SIZE      16
+#define CONFIG_SYS_PCMCIA_CIS_WIN          0x27f00000
+#define CONFIG_SYS_PCMCIA_CIS_WIN_SIZE     0x00100000
+#define CONFIG_SYS_PCMCIA_IO_WIN           0xe000
+#define CONFIG_SYS_PCMCIA_IO_WIN_SIZE      16
 
 /************************************************************
  * DISK Partition support
@@ -239,9 +238,9 @@
 #define CONFIG_PCI_PNP                            /* pci plug-and-play */
 #define CONFIG_PCI_SCAN_SHOW
 
-#define	CFG_FIRST_PCI_IRQ   9
-#define	CFG_SECOND_PCI_IRQ  10
-#define	CFG_THIRD_PCI_IRQ   11
-#define	CFG_FORTH_PCI_IRQ   12
+#define	CONFIG_SYS_FIRST_PCI_IRQ   9
+#define	CONFIG_SYS_SECOND_PCI_IRQ  10
+#define	CONFIG_SYS_THIRD_PCI_IRQ   11
+#define	CONFIG_SYS_FORTH_PCI_IRQ   12
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h
index 1279955..5971df7 100644
--- a/include/configs/scb9328.h
+++ b/include/configs/scb9328.h
@@ -76,22 +76,22 @@
 /*
  * General options for u-boot. Modify to save memory foot print
  */
-#define CFG_LONGHELP				      /* undef saves memory  */
-#define CFG_PROMPT		"scb9328> "	      /* prompt string	     */
-#define CFG_CBSIZE		256		      /* console I/O buffer  */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size   */
-#define CFG_MAXARGS		16		      /* max command args    */
-#define CFG_BARGSIZE		CFG_CBSIZE	      /* boot args buf size  */
+#define CONFIG_SYS_LONGHELP				      /* undef saves memory  */
+#define CONFIG_SYS_PROMPT		"scb9328> "	      /* prompt string	     */
+#define CONFIG_SYS_CBSIZE		256		      /* console I/O buffer  */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size   */
+#define CONFIG_SYS_MAXARGS		16		      /* max command args    */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	      /* boot args buf size  */
 
-#define CFG_MEMTEST_START	0x08100000	      /* memtest test area   */
-#define CFG_MEMTEST_END		0x08F00000
+#define CONFIG_SYS_MEMTEST_START	0x08100000	      /* memtest test area   */
+#define CONFIG_SYS_MEMTEST_END		0x08F00000
 
-#undef	CFG_CLKS_IN_HZ			     /* use HZ for freq. display     */
+#undef	CONFIG_SYS_CLKS_IN_HZ			     /* use HZ for freq. display     */
 
-#define CFG_HZ			3686400	     /* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x141	     /* core clock - register value  */
+#define CONFIG_SYS_HZ			3686400	     /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_CPUSPEED		0x141	     /* core clock - register value  */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 #define CONFIG_BAUDRATE 115200
 /*
  * Definitions related to passing arguments to kernel.
@@ -105,10 +105,10 @@
 /*
  * Malloc pool need to host env + 128 Kb reserve for other allocations.
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + (128<<10) )
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128<<10) )
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 #define CONFIG_STACKSIZE	(120<<10)      /* stack size		     */
 
@@ -152,8 +152,8 @@
 
 /* 32MB */
 #ifdef SCB9328_FLASH_32M
-#define CFG_MAX_FLASH_BANKS		1	/* FLASH banks count (not chip count)*/
-#define CFG_MAX_FLASH_SECT		256	/* number of sector in FLASH bank    */
+#define CONFIG_SYS_MAX_FLASH_BANKS		1	/* FLASH banks count (not chip count)*/
+#define CONFIG_SYS_MAX_FLASH_SECT		256	/* number of sector in FLASH bank    */
 #define SCB9328_FLASH_BUS_WIDTH		2	/* we use 16 bit FLASH memory...     */
 #define SCB9328_FLASH_INTERLEAVE	1	/* ... made of 1 chip		     */
 #define SCB9328_FLASH_BANK_SIZE	 0x02000000	/* size of one flash bank	     */
@@ -163,8 +163,8 @@
 #else
 
 /* 16MB */
-#define CFG_MAX_FLASH_BANKS		1	/* FLASH banks count (not chip count)*/
-#define CFG_MAX_FLASH_SECT		128	/* number of sector in FLASH bank    */
+#define CONFIG_SYS_MAX_FLASH_BANKS		1	/* FLASH banks count (not chip count)*/
+#define CONFIG_SYS_MAX_FLASH_SECT		128	/* number of sector in FLASH bank    */
 #define SCB9328_FLASH_BUS_WIDTH		2	/* we use 16 bit FLASH memory...     */
 #define SCB9328_FLASH_INTERLEAVE	1	/* ... made of 1 chip		     */
 #define SCB9328_FLASH_BANK_SIZE	 0x01000000	/* size of one flash bank	     */
@@ -177,12 +177,12 @@
    is not so clear to me. In other words we can provide more informations
    to user, but this expects more complex flash handling we do not provide
    now.*/
-#undef	CFG_FLASH_CFI
+#undef	CONFIG_SYS_FLASH_CFI
 
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)    /* timeout for Erase operation */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)    /* timeout for Write operation */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ)    /* timeout for Erase operation */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ)    /* timeout for Write operation */
 
-#define CFG_FLASH_BASE		SCB9328_FLASH_BASE
+#define CONFIG_SYS_FLASH_BASE		SCB9328_FLASH_BASE
 
 /*
  * This is setting for JFFS2 support in u-boot.
@@ -191,9 +191,9 @@
  * footprint.
  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
  */
-#define CFG_JFFS2_FIRST_BANK		0
-#define CFG_JFFS2_FIRST_SECTOR		5
-#define CFG_JFFS2_NUM_BANKS		1
+#define CONFIG_SYS_JFFS2_FIRST_BANK		0
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR		5
+#define CONFIG_SYS_JFFS2_NUM_BANKS		1
 
 /*
  * Environment setup. Definitions of monitor location and size with
@@ -210,11 +210,11 @@
 /* Setup for PA23 which is Reset Default PA23 but has to become
    CS5 */
 
-#define CFG_GPR_A_VAL		0x00800000
-#define CFG_GIUS_A_VAL		0x0043fffe
+#define CONFIG_SYS_GPR_A_VAL		0x00800000
+#define CONFIG_SYS_GIUS_A_VAL		0x0043fffe
 
-#define CFG_MONITOR_BASE	0x10000000
-#define CFG_MONITOR_LEN		0x20000		/* 128b ( 1 flash sector )  */
+#define CONFIG_SYS_MONITOR_BASE	0x10000000
+#define CONFIG_SYS_MONITOR_LEN		0x20000		/* 128b ( 1 flash sector )  */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		0x10020000	/* absolute address for now  */
 #define CONFIG_ENV_SIZE		0x20000
@@ -231,30 +231,30 @@
  *   |	 OEA   |   OEN	 |   WEA   |   WEN   |	 CSA   |EBC| DSZ  | 0|SP|0|WP| 0 0|PA|CSEN|
  */
 
-#define CFG_CS0U_VAL 0x000F2000
-#define CFG_CS0L_VAL 0x11110d01
-#define CFG_CS1U_VAL 0x000F0a00
-#define CFG_CS1L_VAL 0x11110601
-#define CFG_CS2U_VAL 0x0
-#define CFG_CS2L_VAL 0x0
+#define CONFIG_SYS_CS0U_VAL 0x000F2000
+#define CONFIG_SYS_CS0L_VAL 0x11110d01
+#define CONFIG_SYS_CS1U_VAL 0x000F0a00
+#define CONFIG_SYS_CS1L_VAL 0x11110601
+#define CONFIG_SYS_CS2U_VAL 0x0
+#define CONFIG_SYS_CS2L_VAL 0x0
 
-#define CFG_CS3U_VAL 0x000FFFFF
-#define CFG_CS3L_VAL 0x00000303
+#define CONFIG_SYS_CS3U_VAL 0x000FFFFF
+#define CONFIG_SYS_CS3L_VAL 0x00000303
 
-#define CFG_CS4U_VAL 0x000F0a00
-#define CFG_CS4L_VAL 0x11110301
+#define CONFIG_SYS_CS4U_VAL 0x000F0a00
+#define CONFIG_SYS_CS4L_VAL 0x11110301
 
 /* CNC == 3 too long
-   #define CFG_CS5U_VAL 0x0000C210 */
+   #define CONFIG_SYS_CS5U_VAL 0x0000C210 */
 
-/* #define CFG_CS5U_VAL 0x00008400
+/* #define CONFIG_SYS_CS5U_VAL 0x00008400
    mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
    kaum langsamer ist */
-/* #define CFG_CS5U_VAL 0x00009400
-   #define CFG_CS5L_VAL 0x11010D03 */
+/* #define CONFIG_SYS_CS5U_VAL 0x00009400
+   #define CONFIG_SYS_CS5L_VAL 0x11010D03 */
 
-#define CFG_CS5U_VAL 0x00008400
-#define CFG_CS5L_VAL 0x00000D03
+#define CONFIG_SYS_CS5U_VAL 0x00008400
+#define CONFIG_SYS_CS5L_VAL 0x00000D03
 
 #define CONFIG_DRIVER_DM9000		1
 #define CONFIG_DM9000_BASE		0x16000000
@@ -281,24 +281,24 @@
 #define CPU200
 
 #ifdef CPU200
-#define CFG_MPCTL0_VAL 0x00321431
+#define CONFIG_SYS_MPCTL0_VAL 0x00321431
 #else
-#define CFG_MPCTL0_VAL 0x040e200e
+#define CONFIG_SYS_MPCTL0_VAL 0x040e200e
 #endif
 
 /* #define BUS64 */
 #define BUS72
 
 #ifdef BUS72
-#define CFG_SPCTL0_VAL 0x04002400
+#define CONFIG_SYS_SPCTL0_VAL 0x04002400
 #endif
 
 #ifdef BUS96
-#define CFG_SPCTL0_VAL 0x04001800
+#define CONFIG_SYS_SPCTL0_VAL 0x04001800
 #endif
 
 #ifdef BUS64
-#define CFG_SPCTL0_VAL 0x08001800
+#define CONFIG_SYS_SPCTL0_VAL 0x08001800
 #endif
 
 /* Das ist der BCLK Divider, der aus der System PLL
@@ -312,11 +312,11 @@
    Bit 21: MPLL Restart */
 
 #ifdef BUS64
-#define CFG_CSCR_VAL 0x2f030003
+#define CONFIG_SYS_CSCR_VAL 0x2f030003
 #endif
 
 #ifdef BUS72
-#define CFG_CSCR_VAL 0x2f030403
+#define CONFIG_SYS_CSCR_VAL 0x2f030403
 #endif
 
 /*
@@ -324,7 +324,7 @@
  * one may expect. For instance loadb command do not cares :-)
  * So advice is - do not relay on this...
  */
-#define CFG_LOAD_ADDR 0x08400000
+#define CONFIG_SYS_LOAD_ADDR 0x08400000
 
 #define MHZ16QUARZINUSE
 
@@ -337,7 +337,7 @@
 #define CONFIG_SYS_CLK_FREQ 16780000
 
 /* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
-#define CFG_FMCR_VAL 0x00000001
+#define CONFIG_SYS_FMCR_VAL 0x00000001
 
 /* Bit[0:3] contain PERCLK1DIV for UART 1
    0x000b00b ->b<- -> 192MHz/12=16MHz
@@ -345,15 +345,15 @@
    0x000b00b ->3<- -> 64MHz/4=16MHz */
 
 #ifdef BUS96
-#define CFG_PCDR_VAL 0x000b00b5
+#define CONFIG_SYS_PCDR_VAL 0x000b00b5
 #endif
 
 #ifdef BUS64
-#define CFG_PCDR_VAL 0x000b00b3
+#define CONFIG_SYS_PCDR_VAL 0x000b00b3
 #endif
 
 #ifdef BUS72
-#define CFG_PCDR_VAL 0x000b00b8
+#define CONFIG_SYS_PCDR_VAL 0x000b00b8
 #endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index d39a894..a3e2fce 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -48,7 +48,7 @@
 #include "amcc-common.h"
 
 /* Detect Sequoia PLL input clock automatically via CPLD bit		*/
-#define CONFIG_SYS_CLK_FREQ    ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
+#define CONFIG_SYS_CLK_FREQ    ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
 				33333333 : 33000000)
 
 /*
@@ -72,40 +72,40 @@
  * Base addresses -- Note these are effective addresses where the actual
  * resources get mapped (not physical addresses).
  */
-#define CFG_TLB_FOR_BOOT_FLASH	0x0003
-#define CFG_BOOT_BASE_ADDR	0xf0000000
-#define CFG_FLASH_BASE		0xfc000000	/* start of FLASH	*/
-#define CFG_NAND_ADDR		0xd0000000	/* NAND Flash		*/
-#define CFG_OCM_BASE		0xe0010000	/* ocm			*/
-#define CFG_OCM_DATA_ADDR	CFG_OCM_BASE
-#define CFG_PCI_BASE		0xe0000000	/* Internal PCI regs	*/
-#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
-#define CFG_PCI_MEMBASE1	CFG_PCI_MEMBASE  + 0x10000000
-#define CFG_PCI_MEMBASE2	CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3	CFG_PCI_MEMBASE2 + 0x10000000
+#define CONFIG_SYS_TLB_FOR_BOOT_FLASH	0x0003
+#define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
+#define CONFIG_SYS_FLASH_BASE		0xfc000000	/* start of FLASH	*/
+#define CONFIG_SYS_NAND_ADDR		0xd0000000	/* NAND Flash		*/
+#define CONFIG_SYS_OCM_BASE		0xe0010000	/* ocm			*/
+#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_OCM_BASE
+#define CONFIG_SYS_PCI_BASE		0xe0000000	/* Internal PCI regs	*/
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CONFIG_SYS_PCI_MEMBASE1	CONFIG_SYS_PCI_MEMBASE  + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2	CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3	CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
 
 /* Don't change either of these */
-#define CFG_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
+#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
 
-#define CFG_USB2D0_BASE		0xe0000100
-#define CFG_USB_DEVICE		0xe0000000
-#define CFG_USB_HOST		0xe0000400
-#define CFG_BCSR_BASE		0xc0000000
+#define CONFIG_SYS_USB2D0_BASE		0xe0000100
+#define CONFIG_SYS_USB_DEVICE		0xe0000000
+#define CONFIG_SYS_USB_HOST		0xe0000400
+#define CONFIG_SYS_BCSR_BASE		0xc0000000
 
 /*
  * Initial RAM & stack pointer
  */
 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
-#define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM			*/
-#define CFG_INIT_RAM_END	(4 << 10)
-#define CFG_GBL_DATA_SIZE	256	/* num bytes initial data	*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
+#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_SIZE	256	/* num bytes initial data	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_POST_WORD_ADDR
 
 /*
  * Serial Port
  */
-#define CFG_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
 /* define this if you want console on UART1 */
 #undef CONFIG_UART1_CONSOLE
 
@@ -122,26 +122,26 @@
 /*
  * FLASH related
  */
-#define CFG_FLASH_CFI			/* The flash is CFI compatible	*/
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
 
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	      */
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip  */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	      */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip  */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)    */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)    */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)    */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)    */
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)   */
-#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection      */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)   */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection      */
 
-#define CFG_FLASH_EMPTY_INFO	      /* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash      */
+#define CONFIG_SYS_FLASH_EMPTY_INFO	      /* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash      */
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	      */
-#define CONFIG_ENV_ADDR		((-CFG_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector   */
 
 /* Address and size of Redundant Environment Sector	*/
@@ -167,75 +167,74 @@
  * set up. While still running from cache, I experienced problems accessing
  * the NAND controller.	sr - 2006-08-25
  */
-#define CFG_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location		      */
-#define CFG_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size		      */
-#define CFG_NAND_BOOT_SPL_DST	(CFG_OCM_BASE + (12 << 10)) /* Copy SPL here  */
-#define CFG_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr      */
-#define CFG_NAND_U_BOOT_START	CFG_NAND_U_BOOT_DST	/* Start NUB from     */
+#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location		      */
+#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size		      */
+#define CONFIG_SYS_NAND_BOOT_SPL_DST	(CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here  */
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr      */
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST	/* Start NUB from     */
 							/*   this addr	      */
-#define CFG_NAND_BOOT_SPL_DELTA	(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
+#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 
 /*
  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
  */
-#define CFG_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image */
-#define CFG_NAND_U_BOOT_SIZE	(512 << 10)	/* Size of RAM U-Boot image   */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image */
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 << 10)	/* Size of RAM U-Boot image   */
 
 /*
  * Now the NAND chip has to be defined (no autodetection used!)
  */
-#define CFG_NAND_PAGE_SIZE	512		/* NAND chip page size	      */
-#define CFG_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size	      */
-#define CFG_NAND_PAGE_COUNT	32		/* NAND chip page count	      */
-#define CFG_NAND_BAD_BLOCK_POS	5	      /* Location of bad block marker */
-#undef CFG_NAND_4_ADDR_CYCLE		      /* No fourth addr used (<=32MB) */
-
-#define CFG_NAND_ECCSIZE	256
-#define CFG_NAND_ECCBYTES	3
-#define CFG_NAND_ECCSTEPS	(CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
-#define CFG_NAND_OOBSIZE	16
-#define CFG_NAND_ECCTOTAL	(CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
-#define CFG_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
+#define CONFIG_SYS_NAND_PAGE_SIZE	512		/* NAND chip page size	      */
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size	      */
+#define CONFIG_SYS_NAND_PAGE_COUNT	32		/* NAND chip page count	      */
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	5	      /* Location of bad block marker */
+#undef CONFIG_SYS_NAND_4_ADDR_CYCLE		      /* No fourth addr used (<=32MB) */
+
+#define CONFIG_SYS_NAND_ECCSIZE	256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_OOBSIZE	16
+#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
+#define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
 
 #ifdef CONFIG_ENV_IS_IN_NAND
 /*
  * For NAND booting the environment is embedded in the U-Boot image. Please take
  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
  */
-#define CONFIG_ENV_SIZE		CFG_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(CFG_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 #endif
 
 /*
  * DDR SDRAM
  */
-#define CFG_MBYTES_SDRAM        (256)	/* 256MB			*/
+#define CONFIG_SYS_MBYTES_SDRAM        (256)	/* 256MB			*/
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization	*/
 #endif
-#define CFG_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
+#define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
 					/* 440EPx errata CHIP 11	*/
 
 /*
  * I2C
  */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 
 /* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
 #define CONFIG_DTT_LM75		1	/* ON Semi's LM75		*/
 #define CONFIG_DTT_AD7414	1	/* use AD7414			*/
 #define CONFIG_DTT_SENSORS	{0}	/* Sensor addresses		*/
-#define CFG_DTT_MAX_TEMP	70
-#define CFG_DTT_LOW_TEMP	-30
-#define CFG_DTT_HYSTERESIS	3
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
 
 /*
  * Default environment variables
@@ -265,13 +264,13 @@
 #ifdef CONFIG_440EPX
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_STORAGE
-#define CFG_OHCI_BE_CONTROLLER
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
 
-#undef CFG_USB_OHCI_BOARD_INIT
-#define CFG_USB_OHCI_CPU_INIT	1
-#define CFG_USB_OHCI_REGS_BASE	CFG_USB_HOST
-#define CFG_USB_OHCI_SLOT_NAME	"ppc440"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	CONFIG_SYS_USB_HOST
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ppc440"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 
 /* Comment this out to enable USB 1.1 device */
 #define USB_2_0_DEVICE
@@ -297,26 +296,26 @@
 #endif
 
 #ifndef CONFIG_RAINIER
-#define CFG_POST_FPU_ON		CFG_POST_FPU
+#define CONFIG_SYS_POST_FPU_ON		CONFIG_SYS_POST_FPU
 #else
-#define CFG_POST_FPU_ON		0
+#define CONFIG_SYS_POST_FPU_ON		0
 #endif
 
 /* POST support */
-#define CONFIG_POST		(CFG_POST_CACHE	   | \
-				 CFG_POST_CPU	   | \
-				 CFG_POST_ETHER	   | \
-				 CFG_POST_FPU_ON   | \
-				 CFG_POST_I2C	   | \
-				 CFG_POST_MEMORY   | \
-				 CFG_POST_SPR	   | \
-				 CFG_POST_UART)
-
-#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_POST		(CONFIG_SYS_POST_CACHE	   | \
+				 CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_ETHER	   | \
+				 CONFIG_SYS_POST_FPU_ON   | \
+				 CONFIG_SYS_POST_I2C	   | \
+				 CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_SPR	   | \
+				 CONFIG_SYS_POST_UART)
+
+#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 #define CONFIG_LOGBUFFER
-#define CFG_POST_CACHE_ADDR	0x7fff0000	/* free virtual address     */
+#define CONFIG_SYS_POST_CACHE_ADDR	0x7fff0000	/* free virtual address     */
 
-#define CFG_CONSOLE_IS_IN_ENV	/* Otherwise it catches logbuffer as output */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* Otherwise it catches logbuffer as output */
 
 #define CONFIG_SUPPORT_VFAT
 
@@ -326,16 +325,16 @@
 /* General PCI */
 #define CONFIG_PCI			/* include pci support		*/
 #define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-#define CFG_PCI_CACHE_LINE_SIZE	0	/* to avoid problems with PNP	*/
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	0	/* to avoid problems with PNP	*/
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
-#define CFG_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to	*/
-						/*   CFG_PCI_MEMBASE	*/
+#define CONFIG_SYS_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to	*/
+						/*   CONFIG_SYS_PCI_MEMBASE	*/
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT
-#define CFG_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
 
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
-#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
+#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
 
 /*
  * External Bus Controller (EBC) Setup
@@ -345,44 +344,43 @@
  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
  */
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-#define CFG_NAND_CS		3	/* NAND chip connected to CSx	*/
+#define CONFIG_SYS_NAND_CS		3	/* NAND chip connected to CSx	*/
 /* Memory Bank 0 (NOR-FLASH) initialization				*/
-#define CFG_EBC_PB0AP		0x03017200
-#define CFG_EBC_PB0CR		(CFG_FLASH_BASE | 0xda000)
+#define CONFIG_SYS_EBC_PB0AP		0x03017200
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
 
 /* Memory Bank 3 (NAND-FLASH) initialization				*/
-#define CFG_EBC_PB3AP		0x018003c0
-#define CFG_EBC_PB3CR		(CFG_NAND_ADDR | 0x1c000)
+#define CONFIG_SYS_EBC_PB3AP		0x018003c0
+#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
 #else
-#define CFG_NAND_CS		0	/* NAND chip connected to CSx	*/
+#define CONFIG_SYS_NAND_CS		0	/* NAND chip connected to CSx	*/
 /* Memory Bank 3 (NOR-FLASH) initialization				*/
-#define CFG_EBC_PB3AP		0x03017200
-#define CFG_EBC_PB3CR		(CFG_FLASH_BASE | 0xda000)
+#define CONFIG_SYS_EBC_PB3AP		0x03017200
+#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
 
 /* Memory Bank 0 (NAND-FLASH) initialization				*/
-#define CFG_EBC_PB0AP		0x018003c0
-#define CFG_EBC_PB0CR		(CFG_NAND_ADDR | 0x1c000)
+#define CONFIG_SYS_EBC_PB0AP		0x018003c0
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
 #endif
 
 /* Memory Bank 2 (CPLD) initialization					*/
-#define CFG_EBC_PB2AP		0x24814580
-#define CFG_EBC_PB2CR		(CFG_BCSR_BASE | 0x38000)
+#define CONFIG_SYS_EBC_PB2AP		0x24814580
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_BCSR_BASE | 0x38000)
 
-#define CFG_BCSR5_PCI66EN	0x80
+#define CONFIG_SYS_BCSR5_PCI66EN	0x80
 
 /*
  * NAND FLASH
  */
-#define CFG_MAX_NAND_DEVICE	1
-#define NAND_MAX_CHIPS		1
-#define CFG_NAND_BASE		(CFG_NAND_ADDR + CFG_NAND_CS)
-#define CFG_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
+#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips */
 
 /*
  * PPC440 GPIO Configuration
  */
 /* test-only: take GPIO init from pcs440ep ???? in config file */
-#define CFG_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
 {											\
 /* GPIO Core 0 */									\
 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
@@ -459,7 +457,7 @@
 #define CONFIG_BIOSEMU			/* x86 bios emulator for vga bios */
 #define CONFIG_ATI_RADEON_FB		/* use radeon framebuffer driver */
 #define VIDEO_IO_OFFSET			0xe8000000
-#define CFG_ISA_IO_BASE_ADDRESS		VIDEO_IO_OFFSET
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS		VIDEO_IO_OFFSET
 #define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_CFB_CONSOLE
diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h
index 2daaeb0..8d7456e 100644
--- a/include/configs/sh7763rdp.h
+++ b/include/configs/sh7763rdp.h
@@ -40,7 +40,7 @@
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_JFFS2
 
@@ -56,68 +56,69 @@
 #define CONFIG_BAUDRATE         115200
 #define CONFIG_CONS_SCIF2		1
 
-#define CFG_LONGHELP		/* undef to save memory */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
-#define CFG_CBSIZE		256	/* Buffer size for input from the Console */
-#define CFG_PBSIZE		256	/* Buffer size for Console output */
-#define CFG_MAXARGS		16	/* max args accepted for monitor commands */
-#define CFG_BARGSIZE	512	/* Buffer size for Boot Arguments
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		256	/* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE		256	/* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS		16	/* max args accepted for monitor commands */
+#define CONFIG_SYS_BARGSIZE	512	/* Buffer size for Boot Arguments
 								passed to kernel */
-#define CFG_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate
 												settings for this board */
 
 /* SDRAM */
-#define CFG_SDRAM_BASE		(0x8C000000)
-#define CFG_SDRAM_SIZE		(64 * 1024 * 1024)
-#define CFG_MEMTEST_START	(CFG_SDRAM_BASE)
-#define CFG_MEMTEST_END		(CFG_MEMTEST_START + (60 * 1024 * 1024))
+#define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
+#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
 
 /* Flash(NOR) */
-#define CFG_FLASH_BASE		(0xA0000000)
-#define CFG_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
-#define CFG_MAX_FLASH_BANKS (1)
-#define CFG_MAX_FLASH_SECT  (520)
+#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
+#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
+#define CONFIG_SYS_MAX_FLASH_BANKS (1)
+#define CONFIG_SYS_MAX_FLASH_SECT  (520)
 
 /* U-boot setting */
-#define CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 4 * 1024 * 1024)
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE)
-#define CFG_MONITOR_LEN		(128 * 1024)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
 /* Size of DRAM reserved for malloc() use */
-#define CFG_MALLOC_LEN		(1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_SIZE	(256)
-#define CFG_BOOTMAPSZ		(8 * 1024 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	(256)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#undef  CFG_FLASH_QUIET_TEST
-#define CFG_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
 /* Timeout for Flash erase operations (in ms) */
-#define CFG_FLASH_ERASE_TOUT	(3 * 1000)
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
 /* Timeout for Flash write operations (in ms) */
-#define CFG_FLASH_WRITE_TOUT	(3 * 1000)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
 /* Timeout for Flash set sector lock bit operations (in ms) */
-#define CFG_FLASH_LOCK_TOUT		(3 * 1000)
+#define CONFIG_SYS_FLASH_LOCK_TOUT		(3 * 1000)
 /* Timeout for Flash clear lock bit operations (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	(3 * 1000)
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
 /* Use hardware flash sectors protection instead of U-Boot software protection */
-#undef  CFG_FLASH_PROTECTION
-#undef  CFG_DIRECT_FLASH_TFTP
+#undef  CONFIG_SYS_FLASH_PROTECTION
+#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	(128 * 1024)
 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
-/* Offset of env Flash sector relative to CFG_FLASH_BASE */
-#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CFG_FLASH_BASE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
+/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
+#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
 
 /* Clock */
 #define CONFIG_SYS_CLK_FREQ	66666666
 #define TMU_CLK_DIVIDER		(4)	/* 4 (default), 16, 64, 256 or 1024 */
-#define CFG_HZ				(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_HZ				(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
 
 /* Ether */
+#define CONFIG_NET_MULTI 1
 #define CONFIG_SH_ETHER 1
 #define CONFIG_SH_ETHER_USE_PORT (1)
 #define CONFIG_SH_ETHER_PHY_ADDR (0x01)
diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h
index bf06f62..537ec4e 100644
--- a/include/configs/sh7785lcr.h
+++ b/include/configs/sh7785lcr.h
@@ -40,7 +40,7 @@
 #define CONFIG_CMD_DFL
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_RUN
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 
 #define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
@@ -67,63 +67,62 @@
 #define SH7785LCR_FLASH_BANK_SIZE	(64 * 1024 * 1024)
 #define SH7785LCR_USB_BASE		(0xb4000000)
 
-#define CFG_LONGHELP
-#define CFG_PROMPT		"=> "
-#define CFG_CBSIZE		256
-#define CFG_PBSIZE		256
-#define CFG_MAXARGS		16
-#define CFG_BARGSIZE		512
-#define CFG_BAUDRATE_TABLE	{ 115200 }
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
 
 /* SCIF */
 #define CONFIG_SCIF_CONSOLE	1
 #define CONFIG_CONS_SCIF1	1
 #define CONFIG_SCIF_EXT_CLOCK	1
-#undef	CFG_CONSOLE_INFO_QUIET
-#undef	CFG_CONSOLE_OVERWRITE_ROUTINE
-#undef	CFG_CONSOLE_ENV_OVERWRITE
+#undef	CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 
 
-#define CFG_MEMTEST_START	(SH7785LCR_SDRAM_BASE)
-#define CFG_MEMTEST_END		(CFG_MEMTEST_START + \
+#define CONFIG_SYS_MEMTEST_START	(SH7785LCR_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
 					(SH7785LCR_SDRAM_SIZE) - \
 					 4 * 1024 * 1024)
-#undef	CFG_ALT_MEMTEST
-#undef	CFG_MEMTEST_SCRATCH
-#undef	CFG_LOADS_BAUD_CHANGE
+#undef	CONFIG_SYS_ALT_MEMTEST
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
 
-#define CFG_SDRAM_BASE	(SH7785LCR_SDRAM_BASE)
-#define CFG_SDRAM_SIZE	(SH7785LCR_SDRAM_SIZE)
-#define CFG_LOAD_ADDR	(CFG_SDRAM_BASE + 16 * 1024 * 1024)
+#define CONFIG_SYS_SDRAM_BASE	(SH7785LCR_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE	(SH7785LCR_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
 
-#define CFG_MONITOR_BASE	(SH7785LCR_FLASH_BASE_1)
-#define CFG_MONITOR_LEN		(512 * 1024)
-#define CFG_MALLOC_LEN		(512 * 1024)
-#define CFG_GBL_DATA_SIZE	(256)
-#define CFG_BOOTMAPSZ		(8 * 1024 * 1024)
+#define CONFIG_SYS_MONITOR_BASE	(SH7785LCR_FLASH_BASE_1)
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	(256)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 
 /* FLASH */
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#undef	CFG_FLASH_QUIET_TEST
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_BASE		(SH7785LCR_FLASH_BASE_1)
-#define CFG_MAX_FLASH_SECT	512
-
-#define CFG_MAX_FLASH_BANKS	1
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE + \
+#define CONFIG_SYS_FLASH_CFI
+#undef	CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BASE		(SH7785LCR_FLASH_BASE_1)
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE + \
 				 (0 * SH7785LCR_FLASH_BANK_SIZE) }
 
-#define CFG_FLASH_ERASE_TOUT	(3 * 1000)
-#define CFG_FLASH_WRITE_TOUT	(3 * 1000)
-#define CFG_FLASH_LOCK_TOUT	(3 * 1000)
-#define CFG_FLASH_UNLOCK_TOUT	(3 * 1000)
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
+#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
 
-#undef	CFG_FLASH_PROTECTION
-#undef	CFG_DIRECT_FLASH_TFTP
+#undef	CONFIG_SYS_FLASH_PROTECTION
+#undef	CONFIG_SYS_DIRECT_FLASH_TFTP
 
 /* R8A66597 */
-#define LITTLEENDIAN			/* for include/usb.h */
 #define CONFIG_USB_R8A66597_HCD
 #define CONFIG_R8A66597_BASE_ADDR	SH7785LCR_USB_BASE
 #define CONFIG_R8A66597_XTAL		0x0000	/* 12MHz */
@@ -154,14 +153,14 @@
 #define CONFIG_ENV_OVERWRITE	1
 #define CONFIG_ENV_SECT_SIZE	(256 * 1024)
 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN)
-#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CFG_FLASH_BASE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
 
 /* Board Clock */
 /* The SCIF used external clock. system clock only used timer. */
 #define CONFIG_SYS_CLK_FREQ	50000000
 #define TMU_CLK_DIVIDER		4
-#define CFG_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CONFIG_SYS_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
 
 #endif	/* __SH7785LCR_H */
diff --git a/include/configs/shannon.h b/include/configs/shannon.h
index edc9a2e..75ba34c 100644
--- a/include/configs/shannon.h
+++ b/include/configs/shannon.h
@@ -48,8 +48,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -95,25 +95,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"TuxScreen # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"TuxScreen # "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0xc0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0xd0000000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0xd0000000	/* default load address	*/
 
-#define	CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x09		/* 190 MHz for Shannon */
+#define	CONFIG_SYS_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_CPUSPEED		0x09		/* 190 MHz for Shannon */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_DOS_PARTITION	1		/* DOS partitiion support */
 
@@ -146,17 +146,17 @@
 #define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
 #define PHYS_FLASH_SIZE		0x00400000 /* 4 MB */
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	(31+4)	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	(31+4)	/* max number of sectors on one chip	*/
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #ifdef CONFIG_INFERNO
@@ -178,14 +178,14 @@
 
 #define CONFIG_PCMCIA_SLOT_A
 
-#define CFG_PCMCIA_IO_ADDR	(0x20000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0x24000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0x2C000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_MEM_ADDR	(0x28000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0x20000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0x24000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0x2C000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0x28000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
 
 /* in fact, MEM and ATTRB are swapped - has to be corrected soon in cmd_pcmcia or so */
 
@@ -200,22 +200,22 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
 /* it's simple, all regs are in I/O space */
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_ATTRB_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_ATTRB_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	0
+#define CONFIG_SYS_ATA_DATA_OFFSET	0
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	0
+#define CONFIG_SYS_ATA_REG_OFFSET	0
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0
+#define CONFIG_SYS_ATA_ALT_OFFSET	0
 
 /*-----------------------------------------------------------------------
  */
diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h
index 15ae3da..6388be4 100644
--- a/include/configs/smdk2400.h
+++ b/include/configs/smdk2400.h
@@ -50,8 +50,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -127,26 +127,26 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"SMDK2400 # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"SMDK2400 # "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0c000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0e000000	/* 32 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0c000000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0e000000	/* 32 MB in DRAM	*/
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0x0cf00000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x0cf00000	/* default load address	*/
 
 /* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
 /* it to wrap 100 times (total 1562500) to get 1 sec. */
-#define	CFG_HZ			1562500
+#define	CONFIG_SYS_HZ			1562500
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -166,22 +166,22 @@
 #define PHYS_SDRAM_1		0x0c000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
 
-#define CFG_FLASH_BASE		0x00000000 /* Flash Bank #1 */
+#define CONFIG_SYS_FLASH_BASE		0x00000000 /* Flash Bank #1 */
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	(64)	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	(64)	/* max number of sectors on one chip */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 
 /* Address and size of Primary Environment Sector	*/
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
 #define CONFIG_ENV_SIZE		0x40000
 
 /* Address and size of Redundant Environment Sector	*/
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index cd0093e..ecd958b 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -47,8 +47,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -110,26 +110,26 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"SMDK2410 # "	/* Monitor Command Prompt	*/
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"SMDK2410 # "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x30000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x33F00000	/* 63 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x30000000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x33F00000	/* 63 MB in DRAM	*/
 
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0x33000000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x33000000	/* default load address	*/
 
 /* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
 /* it to wrap 100 times (total 1562500) to get 1 sec. */
-#define	CFG_HZ			1562500
+#define	CONFIG_SYS_HZ			1562500
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -151,7 +151,7 @@
 
 #define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
@@ -162,21 +162,21 @@
 #define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */
 #endif
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
 #ifdef CONFIG_AMD_LV800
 #define PHYS_FLASH_SIZE		0x00100000 /* 1MB */
-#define CFG_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
+#define CONFIG_SYS_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
 #endif
 #ifdef CONFIG_AMD_LV400
 #define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
-#define CFG_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x070000) /* addr of environment */
+#define CONFIG_SYS_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
 #endif
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */
diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index ea65c0e..06d6a88 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -40,7 +40,7 @@
 #define CONFIG_S3C64XX		1	/* in a SAMSUNG S3C64XX Family  */
 #define CONFIG_SMDK6400		1	/* on a SAMSUNG SMDK6400 Board  */
 
-#define CFG_SDRAM_BASE	0x50000000
+#define CONFIG_SYS_SDRAM_BASE	0x50000000
 
 /* input clock of PLL: SMDK6400 has 12MHz input clock */
 #define CONFIG_SYS_CLK_FREQ	12000000
@@ -68,8 +68,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes for initial data */
 
 /*
  * Hardware drivers
@@ -83,9 +83,9 @@
  */
 #define CONFIG_SERIAL1          1	/* we use SERIAL 1 on SMDK6400	*/
 
-#define CFG_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #define CONFIG_CMDLINE_EDITING
@@ -104,7 +104,7 @@
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_LOADS
 #define CONFIG_CMD_LOADB
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_NAND
 #if defined(CONFIG_BOOT_ONENAND)
 #define CONFIG_CMD_ONENAND
@@ -126,22 +126,22 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory	      */
-#define CFG_PROMPT		"SMDK6400 # "	/* Monitor Command Prompt     */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size    */
-#define CFG_PBSIZE		384		/* Print Buffer Size          */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory	      */
+#define CONFIG_SYS_PROMPT		"SMDK6400 # "	/* Monitor Command Prompt     */
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size    */
+#define CONFIG_SYS_PBSIZE		384		/* Print Buffer Size          */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */
 
-#define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* memtest works on	      */
-#define CFG_MEMTEST_END		(CFG_SDRAM_BASE + 0x7e00000) /* 126MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE	/* memtest works on	      */
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x7e00000) /* 126MB in DRAM */
 
-#define CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* default load address	*/
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE	/* default load address	*/
 
-#define CFG_HZ			1000
+#define CONFIG_SYS_HZ			1000
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -171,30 +171,30 @@
 
 /* SMDK6400 has 2 banks of DRAM, but we use only one in U-Boot */
 #define CONFIG_NR_DRAM_BANKS	1
-#define PHYS_SDRAM_1		CFG_SDRAM_BASE	/* SDRAM Bank #1	*/
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE	/* SDRAM Bank #1	*/
 #define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB in Bank #1	*/
 
-#define CFG_FLASH_BASE		0x10000000
-#define CFG_MONITOR_BASE	0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x10000000
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	*/
 /* AM29LV160B has 35 sectors, AM29LV800B - 19 */
-#define CFG_MAX_FLASH_SECT	40
+#define CONFIG_SYS_MAX_FLASH_SECT	40
 
 #define CONFIG_AMD_LV800
-#define CFG_FLASH_CFI		1	/* Use CFI parameters (needed?) */
+#define CONFIG_SYS_FLASH_CFI		1	/* Use CFI parameters (needed?) */
 /* Use drivers/cfi_flash.c, even though the flash is not CFI-compliant	*/
 #define CONFIG_FLASH_CFI_DRIVER	1
-#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 #define CONFIG_FLASH_CFI_LEGACY
-#define CFG_FLASH_LEGACY_512Kx16
+#define CONFIG_SYS_FLASH_LEGACY_512Kx16
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(5 * CFG_HZ) /* Timeout for Flash Erase	*/
-#define CFG_FLASH_WRITE_TOUT	(5 * CFG_HZ) /* Timeout for Flash Write	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(5 * CONFIG_SYS_HZ) /* Timeout for Flash Erase	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(5 * CONFIG_SYS_HZ) /* Timeout for Flash Write	*/
 
 #define CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector */
 
@@ -205,65 +205,64 @@
 #define CONFIG_IDENT_STRING	" for SMDK6400"
 
 /* base address for uboot */
-#define CFG_PHY_UBOOT_BASE	(CFG_SDRAM_BASE + 0x07e00000)
+#define CONFIG_SYS_PHY_UBOOT_BASE	(CONFIG_SYS_SDRAM_BASE + 0x07e00000)
 /* total memory available to uboot */
-#define CFG_UBOOT_SIZE		(1024 * 1024)
+#define CONFIG_SYS_UBOOT_SIZE		(1024 * 1024)
 
 #ifdef CONFIG_ENABLE_MMU
-#define CFG_MAPPED_RAM_BASE	0xc0000000
+#define CONFIG_SYS_MAPPED_RAM_BASE	0xc0000000
 #define CONFIG_BOOTCOMMAND	"nand read 0xc0018000 0x60000 0x1c0000;" \
 				"bootm 0xc0018000"
 #else
-#define CFG_MAPPED_RAM_BASE	CFG_SDRAM_BASE
+#define CONFIG_SYS_MAPPED_RAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_BOOTCOMMAND	"nand read 0x50018000 0x60000 0x1c0000;" \
 				"bootm 0x50018000"
 #endif
 
 /* NAND U-Boot load and start address */
-#define CFG_UBOOT_BASE		(CFG_MAPPED_RAM_BASE + 0x07e00000)
+#define CONFIG_SYS_UBOOT_BASE		(CONFIG_SYS_MAPPED_RAM_BASE + 0x07e00000)
 
 #define CONFIG_ENV_OFFSET		0x0040000
 
 /* NAND configuration */
-#define CFG_MAX_NAND_DEVICE	1
-#define CFG_NAND_BASE		0x70200010
-#define NAND_MAX_CHIPS		1
-#define CFG_S3C_NAND_HWECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x70200010
+#define CONFIG_SYS_S3C_NAND_HWECC
 
-#define CFG_NAND_SKIP_BAD_DOT_I	1  /* ".i" read skips bad blocks	      */
-#define CFG_NAND_WP		1
-#define CFG_NAND_YAFFS_WRITE	1  /* support yaffs write		      */
-#define CFG_NAND_BBT_2NDPAGE	1  /* bad-block markers in 1st and 2nd pages  */
+#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I	1  /* ".i" read skips bad blocks	      */
+#define CONFIG_SYS_NAND_WP		1
+#define CONFIG_SYS_NAND_YAFFS_WRITE	1  /* support yaffs write		      */
+#define CONFIG_SYS_NAND_BBT_2NDPAGE	1  /* bad-block markers in 1st and 2nd pages  */
 
-#define CFG_NAND_U_BOOT_DST	CFG_PHY_UBOOT_BASE	/* NUB load-addr      */
-#define CFG_NAND_U_BOOT_START	CFG_NAND_U_BOOT_DST	/* NUB start-addr     */
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_PHY_UBOOT_BASE	/* NUB load-addr      */
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST	/* NUB start-addr     */
 
-#define CFG_NAND_U_BOOT_OFFS	(4 * 1024)	/* Offset to RAM U-Boot image */
-#define CFG_NAND_U_BOOT_SIZE	(252 * 1024)	/* Size of RAM U-Boot image   */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(4 * 1024)	/* Offset to RAM U-Boot image */
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(252 * 1024)	/* Size of RAM U-Boot image   */
 
 /* NAND chip page size		*/
-#define CFG_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
 /* NAND chip block size		*/
-#define CFG_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
 /* NAND chip page per block count  */
-#define CFG_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
 /* Location of the bad-block label */
-#define CFG_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
 /* Extra address cycle for > 128MiB */
-#define CFG_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
 
 /* Size of the block protected by one OOB (Spare Area in Samsung terminology) */
-#define CFG_NAND_ECCSIZE	CFG_NAND_PAGE_SIZE
+#define CONFIG_SYS_NAND_ECCSIZE	CONFIG_SYS_NAND_PAGE_SIZE
 /* Number of ECC bytes per OOB - S3C6400 calculates 4 bytes ECC in 1-bit mode */
-#define CFG_NAND_ECCBYTES	4
+#define CONFIG_SYS_NAND_ECCBYTES	4
 /* Number of ECC-blocks per NAND page */
-#define CFG_NAND_ECCSTEPS	(CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
 /* Size of a single OOB region */
-#define CFG_NAND_OOBSIZE	64
+#define CONFIG_SYS_NAND_OOBSIZE	64
 /* Number of ECC bytes per page */
-#define CFG_NAND_ECCTOTAL	(CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
+#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
 /* ECC byte positions */
-#define CFG_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47, \
+#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47, \
 				 48, 49, 50, 51, 52, 53, 54, 55, \
 				 56, 57, 58, 59, 60, 61, 62, 63}
 
@@ -290,11 +289,10 @@
 #if !defined(CONFIG_ENABLE_MMU)
 #define CONFIG_CMD_USB			1
 #define CONFIG_USB_OHCI_NEW		1
-#define CFG_USB_OHCI_REGS_BASE		0x74300000
-#define CFG_USB_OHCI_SLOT_NAME		"s3c6400"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS	3
-#define CFG_USB_OHCI_CPU_INIT		1
-#define LITTLEENDIAN			1	/* used by usb_ohci.c	*/
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x74300000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"s3c6400"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
 
 #define CONFIG_USB_STORAGE	1
 #endif
diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h
index fd13dcd..a3f2677 100644
--- a/include/configs/smmaco4.h
+++ b/include/configs/smmaco4.h
@@ -37,7 +37,7 @@
 #define CONFIG_TQM5200		1	/* ... on TQM5200 module */
 #undef CONFIG_TQM5200_REV100		/*  define for revision 100 modules */
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
@@ -49,7 +49,7 @@
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /* Partitions */
 #define CONFIG_MAC_PARTITION
@@ -57,9 +57,9 @@
 #define CONFIG_ISO_PARTITION
 
 /* POST support */
-#define CONFIG_POST		(CFG_POST_MEMORY   | \
-				 CFG_POST_CPU	   | \
-				 CFG_POST_I2C)
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_I2C)
 
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
@@ -101,7 +101,7 @@
 #define	CONFIG_TIMESTAMP		/* display image timestamps */
 
 #if (TEXT_BASE == 0xFC000000)		/* Boot low */
-#   define CFG_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT		1
 #endif
 
 /*
@@ -143,17 +143,17 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
-#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
+#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
  * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
+#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
 
 /*
@@ -161,9 +161,9 @@
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
 #ifdef CONFIG_TQM5200_REV100
-#define CFG_I2C_MODULE		1	/* Select I2C module #1 for rev. 100 board */
+#define CONFIG_SYS_I2C_MODULE		1	/* Select I2C module #1 for rev. 100 board */
 #else
-#define CFG_I2C_MODULE		2	/* Select I2C module #2 for all other revs */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #2 for all other revs */
 #endif
 
 /*
@@ -172,11 +172,11 @@
  * Please notice, that the resulting clock frequency could differ from the
  * configured value. This is because the I2C clock is derived from system
  * clock over a frequency divider with only a few divider values. U-boot
- * calculates the best approximation for CFG_I2C_SPEED. However the calculated
+ * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
  * approximation allways lies below the configured value, never above.
  */
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
@@ -184,34 +184,34 @@
  * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
  * same configuration could be used.
  */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CFG_I2C_EEPROM_ADDR_LEN		2
-#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
 
 /*
  * Flash configuration
  */
-#define CFG_FLASH_BASE		TEXT_BASE /* 0xFC000000 */
+#define CONFIG_SYS_FLASH_BASE		TEXT_BASE /* 0xFC000000 */
 
 /* use CFI flash driver if no module variant is spezified */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
-#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
-#undef CFG_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
-
-#if !defined(CFG_LOWBOOT)
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00760000 + 0x00800000)
-#else	/* CFG_LOWBOOT */
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
-#endif	/* CFG_LOWBOOT */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_BOOTCS_START }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MByte */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
+
+#if !defined(CONFIG_SYS_LOWBOOT)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
+#else	/* CONFIG_SYS_LOWBOOT */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
+#endif	/* CONFIG_SYS_LOWBOOT */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
 					   (= chip selects) */
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
 
 /* Dynamic MTD partition support */
 #define CONFIG_JFFS2_CMDLINE
@@ -235,32 +235,32 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /* Use ON-Chip SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
 #else
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
 #endif
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
@@ -299,19 +299,19 @@
  *   tests.
  */
 #if defined (CONFIG_MINIFAP)
-# define CFG_GPS_PORT_CONFIG	0x91000004
+# define CONFIG_SYS_GPS_PORT_CONFIG	0x91000004
 #elif defined (CONFIG_STK52XX)
 # if defined (CONFIG_STK52XX_REV100)
-#  define CFG_GPS_PORT_CONFIG	0x81500014
+#  define CONFIG_SYS_GPS_PORT_CONFIG	0x81500014
 # else /* STK52xx REV200 and above */
 #  if defined (CONFIG_TQM5200_REV100)
 #   error TQM5200 REV100 not supported on STK52XX REV200 or above
 #  else/* TQM5200 REV200 and above */
-#   define CFG_GPS_PORT_CONFIG	0x91500004
+#   define CONFIG_SYS_GPS_PORT_CONFIG	0x91500004
 #  endif
 # endif
 #else  /* TMQ5200 Inbetriebnahme-Board */
-# define CFG_GPS_PORT_CONFIG	0x81000004
+# define CONFIG_SYS_GPS_PORT_CONFIG	0x81000004
 #endif
 
 /*
@@ -322,30 +322,30 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
 /* Enable an alternate, more extensive memory test */
-#define CFG_ALT_MEMTEST
+#define CONFIG_SYS_ALT_MEMTEST
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*
@@ -357,26 +357,26 @@
  * Various low-level settings
  */
 #if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 #else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
 #endif
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
-#define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
+#define CONFIG_SYS_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
 #else
-#define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
+#define CONFIG_SYS_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
 #endif
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
 
-#define CFG_RESET_ADDRESS	0xff000000
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index bbb9d18..becd13e 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -82,22 +82,21 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache		*/
 #define CONFIG_BTB			/* toggle branch predition	*/
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming	*/
 
-#define CFG_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions	*/
+#define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions	*/
 
-#undef	CFG_DRAM_TEST			/* memory test, takes time	*/
-#define CFG_MEMTEST_START	0x00400000
-#define CFG_MEMTEST_END		0x00C00000
+#undef	CONFIG_SYS_DRAM_TEST			/* memory test, takes time	*/
+#define CONFIG_SYS_MEMTEST_START	0x00400000
+#define CONFIG_SYS_MEMTEST_END		0x00C00000
 
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT	0xFF700000	/* CCSRBAR Default	*/
-#define CFG_CCSRBAR		0xE0000000	/* relocated CCSRBAR	*/
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xFF700000	/* CCSRBAR Default	*/
+#define CONFIG_SYS_CCSRBAR		0xE0000000	/* relocated CCSRBAR	*/
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR	*/
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR2
@@ -108,8 +107,8 @@
 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_VERY_BIG_RAM
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
@@ -122,80 +121,78 @@
 #define CONFIG_DDR_DEFAULT_CL	30		/* CAS latency 3	*/
 
 /* Hardcoded values, to use instead of SPD */
-#define CFG_DDR_CS0_BNDS		0x0000000f
-#define CFG_DDR_CS0_CONFIG		0x80010102
-#define CFG_DDR_TIMING_0		0x00260802
-#define CFG_DDR_TIMING_1		0x3935D322
-#define CFG_DDR_TIMING_2		0x14904CC8
-#define CFG_DDR_MODE			0x00480432
-#define CFG_DDR_INTERVAL		0x030C0100
-#define CFG_DDR_CONFIG_2		0x04400000
-#define CFG_DDR_CONFIG			0xC3008000
-#define CFG_DDR_CLK_CONTROL		0x03800000
-#define CFG_SDRAM_SIZE			256 /* in Megs */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000000f
+#define CONFIG_SYS_DDR_CS0_CONFIG		0x80010102
+#define CONFIG_SYS_DDR_TIMING_0		0x00260802
+#define CONFIG_SYS_DDR_TIMING_1		0x3935D322
+#define CONFIG_SYS_DDR_TIMING_2		0x14904CC8
+#define CONFIG_SYS_DDR_MODE			0x00480432
+#define CONFIG_SYS_DDR_INTERVAL		0x030C0100
+#define CONFIG_SYS_DDR_CONFIG_2		0x04400000
+#define CONFIG_SYS_DDR_CONFIG			0xC3008000
+#define CONFIG_SYS_DDR_CLK_CONTROL		0x03800000
+#define CONFIG_SYS_SDRAM_SIZE			256 /* in Megs */
 
 /*
  * Flash on the LocalBus
  */
-#define CFG_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable	 */
+#define CONFIG_SYS_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable	 */
 
-#define CFG_FLASH0		0xFE000000
-#define CFG_FLASH1		0xFC000000
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH1, CFG_FLASH0 }
+#define CONFIG_SYS_FLASH0		0xFE000000
+#define CONFIG_SYS_FLASH1		0xFC000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
 
-#define CFG_LBC_FLASH_BASE	CFG_FLASH1	/* Localbus flash start	*/
-#define CFG_FLASH_BASE		CFG_LBC_FLASH_BASE /* start of FLASH	*/
+#define CONFIG_SYS_LBC_FLASH_BASE	CONFIG_SYS_FLASH1	/* Localbus flash start	*/
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH	*/
 
-#define CFG_BR0_PRELIM		0xfe001001	/* port size 16bit	*/
-#define CFG_OR0_PRELIM		0xfe000030	/* 32MB Flash		*/
-#define CFG_BR1_PRELIM		0xfc001001	/* port size 16bit	*/
-#define CFG_OR1_PRELIM		0xfe000030	/* 32MB Flash		*/
+#define CONFIG_SYS_BR0_PRELIM		0xfe001001	/* port size 16bit	*/
+#define CONFIG_SYS_OR0_PRELIM		0xfe000030	/* 32MB Flash		*/
+#define CONFIG_SYS_BR1_PRELIM		0xfc001001	/* port size 16bit	*/
+#define CONFIG_SYS_OR1_PRELIM		0xfe000030	/* 32MB Flash		*/
 
-#define CFG_FLASH_CFI				/* flash is CFI compat.	*/
+#define CONFIG_SYS_FLASH_CFI				/* flash is CFI compat.	*/
 #define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver*/
 
-#define CFG_MAX_FLASH_BANKS	2		/* number of banks	*/
-#define CFG_MAX_FLASH_SECT	256		/* sectors per device	*/
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms)	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256		/* sectors per device	*/
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms)	*/
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
 
-#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg	*/
-#define CFG_LBC_LBCR		0x00000000    /* LB config reg		*/
-#define CFG_LBC_LSRT		0x20000000    /* LB sdram refresh timer	*/
-#define CFG_LBC_MRTPR		0x20000000    /* LB refresh timer presc.*/
+#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg	*/
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg		*/
+#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer	*/
+#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer presc.*/
 
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address	*/
-#define CFG_INIT_RAM_END	0x4000		/* End used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End used area in RAM	*/
 
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256kB for Mon */
-#define CFG_MALLOC_LEN		(4 << 20)	/* Reserve 4 MB for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* Reserve 4 MB for malloc */
 
 /* FPGA and NAND */
-#define CFG_FPGA_BASE		0xc0000000
-#define CFG_FPGA_SIZE		0x00100000	/* 1 MB		*/
-#define CFG_HMI_BASE		0xc0010000
-#define CFG_BR3_PRELIM		0xc0001881	/* UPMA, 32-bit */
-#define CFG_OR3_PRELIM		0xfff00000	/* 1 MB 	*/
-
-#define CFG_NAND_BASE		(CFG_FPGA_BASE + 0x70)
-#define CFG_MAX_NAND_DEVICE	1
-#define NAND_MAX_CHIPS		1
+#define CONFIG_SYS_FPGA_BASE		0xc0000000
+#define CONFIG_SYS_FPGA_SIZE		0x00100000	/* 1 MB		*/
+#define CONFIG_SYS_HMI_BASE		0xc0010000
+#define CONFIG_SYS_BR3_PRELIM		0xc0001881	/* UPMA, 32-bit */
+#define CONFIG_SYS_OR3_PRELIM		0xfff00000	/* 1 MB 	*/
+
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_FPGA_BASE + 0x70)
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_CMD_NAND
 
 /* LIME GDC */
-#define CFG_LIME_BASE		0xc8000000
-#define CFG_LIME_SIZE		0x04000000	/* 64 MB	*/
-#define CFG_BR2_PRELIM		0xc80018a1	/* UPMB, 32-bit	*/
-#define CFG_OR2_PRELIM		0xfc000000	/* 64 MB	*/
+#define CONFIG_SYS_LIME_BASE		0xc8000000
+#define CONFIG_SYS_LIME_SIZE		0x04000000	/* 64 MB	*/
+#define CONFIG_SYS_BR2_PRELIM		0xc80018a1	/* UPMB, 32-bit	*/
+#define CONFIG_SYS_OR2_PRELIM		0xfc000000	/* 64 MB	*/
 
 #define CONFIG_VIDEO
 #define CONFIG_VIDEO_MB862xx
@@ -205,33 +202,33 @@
 #define CONFIG_CONSOLE_EXTRA_INFO
 #define VIDEO_FB_16BPP_PIXEL_SWAP
 #define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CFG_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_VIDEO_BMP_GZIP
-#define CFG_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */
 
 /* Serial Port */
 
 #define CONFIG_CONS_INDEX     1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
 #define CONFIG_BAUDRATE         115200
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 
@@ -241,45 +238,44 @@
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		102124	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C_SPEED		102124	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x3000
 
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
-#define CFG_I2C2_OFFSET		0x3100
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
 
 /* I2C RTC */
 #define CONFIG_RTC_RX8025		/* Use Epson rx8025 rtc via i2c	*/
-#define CFG_I2C_RTC_ADDR	0x32	/* at address 0x32		*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x32	/* at address 0x32		*/
 
 /* I2C W83782G HW-Monitoring IC */
-#define CFG_I2C_W83782G_ADDR	0x28	/* W83782G address 		*/
+#define CONFIG_SYS_I2C_W83782G_ADDR	0x28	/* W83782G address 		*/
 
 /* I2C temp sensor */
 /* Socrates uses Maxim's	DS75, which is compatible with LM75 */
 #define CONFIG_DTT_LM75		1
 #define CONFIG_DTT_SENSORS	{4}		/* Sensor addresses	*/
-#define CFG_DTT_MAX_TEMP	125
-#define CFG_DTT_LOW_TEMP	-55
-#define CFG_DTT_HYSTERESIS	3
-#define CFG_EEPROM_PAGE_WRITE_ENABLE	/* necessary for the LM75 chip */
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_DTT_MAX_TEMP	125
+#define CONFIG_SYS_DTT_LOW_TEMP	-55
+#define CONFIG_SYS_DTT_HYSTERESIS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
 
 /*
  * General PCI
  * Memory space is mapped 1-1.
  */
-#define CFG_PCI_PHYS		0x80000000	/* 1G PCI TLB */
+#define CONFIG_SYS_PCI_PHYS		0x80000000	/* 1G PCI TLB */
 
 /* PCI is clocked by the external source at 33 MHz */
 #define CONFIG_PCI_CLK_FREQ	33000000
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M			*/
-#define CFG_PCI1_IO_BASE	0xE2000000
-#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE	0x01000000	/* 16M			*/
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M			*/
+#define CONFIG_SYS_PCI1_IO_BASE	0xE2000000
+#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000	/* 16M			*/
 
 #if defined(CONFIG_PCI)
 #define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
@@ -315,13 +311,13 @@
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env	*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x4000
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define	CONFIG_TIMESTAMP		/* Print image info with ts	*/
 
@@ -363,27 +359,27 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_LOAD_ADDR	0x2000000	/* default load address		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address		*/
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #if defined(CONFIG_CMD_KGDB)
-    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-    #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size	*/
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size	*/
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*
  * Internal Definitions
@@ -474,9 +470,9 @@
 #define CONFIG_PCI_OHCI			1
 #define CONFIG_PCI_OHCI_DEVNO		3 /* Number in PCI list */
 #define CONFIG_PCI_EHCI_DEVNO		(CONFIG_PCI_OHCI_DEVNO / 2)
-#define CFG_USB_OHCI_MAX_ROOT_PORTS	15
-#define CFG_USB_OHCI_SLOT_NAME		"ohci_pci"
-#define CFG_OHCI_SWAP_REG_ACCESS	1
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ohci_pci"
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
 #define CONFIG_DOS_PARTITION		1
 #define CONFIG_USB_STORAGE		1
 
diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h
index 4bc4afb..5db1379 100644
--- a/include/configs/sorcery.h
+++ b/include/configs/sorcery.h
@@ -35,8 +35,8 @@
 
 /* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
    determine the CPU speed. */
-#define CFG_MPC8220_CLKIN	60000000 /* ... running at 60MHz */
-#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */
+#define CONFIG_SYS_MPC8220_CLKIN	60000000 /* ... running at 60MHz */
+#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	*/
@@ -47,7 +47,7 @@
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC */
 
 #define CONFIG_BAUDRATE		115200	    /* ... at 115200 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /* PCI */
 #define CONFIG_PCI              1
@@ -136,14 +136,14 @@
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1
-#define CFG_I2C_MODULE		1
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_MODULE		1
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /*
@@ -154,51 +154,51 @@
  */
 
 /* Flash */
-#define CFG_CS0_BASE		0xf800
-#define CFG_CS0_MASK		0x08000000 /* 128 MB (two chips) */
-#define CFG_CS0_CTRL		0x001019c0
+#define CONFIG_SYS_CS0_BASE		0xf800
+#define CONFIG_SYS_CS0_MASK		0x08000000 /* 128 MB (two chips) */
+#define CONFIG_SYS_CS0_CTRL		0x001019c0
 
 /* NVM */
-#define CFG_CS1_BASE		0xf7e8
-#define CFG_CS1_MASK		0x00040000 /* 256K */
-#define CFG_CS1_CTRL		0x00101940 /* 8bit port size */
+#define CONFIG_SYS_CS1_BASE		0xf7e8
+#define CONFIG_SYS_CS1_MASK		0x00040000 /* 256K */
+#define CONFIG_SYS_CS1_CTRL		0x00101940 /* 8bit port size */
 
 /* Atlas2 + Gemini */
-#define CFG_CS2_BASE		0xf7e7
-#define CFG_CS2_MASK		0x00010000 /* 64K*/
-#define CFG_CS2_CTRL		0x001011c0 /* 16bit port size */
+#define CONFIG_SYS_CS2_BASE		0xf7e7
+#define CONFIG_SYS_CS2_MASK		0x00010000 /* 64K*/
+#define CONFIG_SYS_CS2_CTRL		0x001011c0 /* 16bit port size */
 
 /* CAN Controller */
-#define CFG_CS3_BASE		0xf7e6
-#define CFG_CS3_MASK		0x00010000 /* 64K */
-#define CFG_CS3_CTRL		0x00102140 /* 8Bit port size */
+#define CONFIG_SYS_CS3_BASE		0xf7e6
+#define CONFIG_SYS_CS3_MASK		0x00010000 /* 64K */
+#define CONFIG_SYS_CS3_CTRL		0x00102140 /* 8Bit port size */
 
 /* Foreign interface */
-#define CFG_CS4_BASE		0xf7e5
-#define CFG_CS4_MASK		0x00010000 /* 64K */
-#define CFG_CS4_CTRL		0x00101dc0 /* 16bit port size */
+#define CONFIG_SYS_CS4_BASE		0xf7e5
+#define CONFIG_SYS_CS4_MASK		0x00010000 /* 64K */
+#define CONFIG_SYS_CS4_CTRL		0x00101dc0 /* 16bit port size */
 
 /* CPLD */
-#define CFG_CS5_BASE		0xf7e4
-#define CFG_CS5_MASK		0x00010000 /* 64K */
-#define CFG_CS5_CTRL		0x001000c0 /* 16bit port size */
+#define CONFIG_SYS_CS5_BASE		0xf7e4
+#define CONFIG_SYS_CS5_MASK		0x00010000 /* 64K */
+#define CONFIG_SYS_CS5_CTRL		0x001000c0 /* 16bit port size */
 
-#define CFG_FLASH0_BASE		(CFG_CS0_BASE << 16)
-#define CFG_FLASH_BASE		(CFG_FLASH0_BASE)
+#define CONFIG_SYS_FLASH0_BASE		(CONFIG_SYS_CS0_BASE << 16)
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_FLASH0_BASE)
 
-#define CFG_MAX_FLASH_BANKS	2	/* max num of flash banks */
-#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE,  \
-				CFG_FLASH_BASE+0x04000000 } /* two banks */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,  \
+				CONFIG_SYS_FLASH_BASE+0x04000000 } /* two banks */
 
 /*
  * Environment settings
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x8000000 - 0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x8000000 - 0x40000)
 #define CONFIG_ENV_SIZE		0x4000                       /* 16K */
 #define CONFIG_ENV_SECT_SIZE	0x20000
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + 0x20000)
@@ -220,37 +220,37 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
-#define CFG_SRAM_BASE		(CFG_MBAR + 0x20000)
-#define CFG_SRAM_SIZE		0x8000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_SRAM_BASE		(CONFIG_SYS_MBAR + 0x20000)
+#define CONFIG_SYS_SRAM_SIZE		0x8000
 
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	(CFG_MBAR + 0x20000)
-#define CFG_INIT_RAM_END	0x8000	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MBAR + 0x20000)
+#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in DPRAM */
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10) /* Reserve 256 kB for Monitor   */
-#define CFG_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
-#define CFG_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10) /* Reserve 256 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
 
 /* SDRAM configuration (for SPD) */
-#define CFG_SDRAM_TOTAL_BANKS		1
-#define CFG_SDRAM_SPD_I2C_ADDR		0x50		/* 7bit */
-#define CFG_SDRAM_SPD_SIZE		0x100
-#define CFG_SDRAM_CAS_LATENCY		5		/* (CL=2.5)x2 */
+#define CONFIG_SYS_SDRAM_TOTAL_BANKS		1
+#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR		0x50		/* 7bit */
+#define CONFIG_SYS_SDRAM_SPD_SIZE		0x100
+#define CONFIG_SYS_SDRAM_CAS_LATENCY		5		/* (CL=2.5)x2 */
 
 /* SDRAM drive strength register (for SSTL_2 class II)*/
-#define CFG_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
+#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
 					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
 					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \
 					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \
@@ -267,38 +267,38 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			    /* undef to save memory	*/
-#define CFG_PROMPT		"=> "	    /* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			    /* undef to save memory	*/
+#define CONFIG_SYS_PROMPT		"=> "	    /* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	    /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		1024	    /* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE		256	    /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		256	    /* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	    /* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size    */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	    /* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START	0x00100000  /* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000  /* 1 ... 15 MB in DRAM  */
+#define CONFIG_SYS_MEMTEST_START	0x00100000  /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000  /* 1 ... 15 MB in DRAM  */
 
-#define CFG_LOAD_ADDR		0x100000    /* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000    /* default load address */
 
-#define CFG_HZ			1000	    /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	    /* decrementer freq: 1 ms ticks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*
  * Various low-level settings
  */
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
 
 /*
-#define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL          HID0_ICE
+#define CONFIG_SYS_HID0_INIT           HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL          HID0_ICE
 */
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h
index 592cef1..1fe2a04 100644
--- a/include/configs/spc1920.h
+++ b/include/configs/spc1920.h
@@ -40,14 +40,14 @@
 #define CONFIG_BAUDRATE		19200
 
 /* use PLD CLK4 instead of brg */
-#define CFG_SPC1920_SMC1_CLK4
+#define CONFIG_SYS_SPC1920_SMC1_CLK4
 
 #define CONFIG_8xx_OSCLK		10000000 /* 10 MHz oscillator on EXTCLK  */
 #define CONFIG_8xx_CPUCLK_DEFAULT	50000000
-#define CFG_8xx_CPUCLK_MIN		40000000
-#define CFG_8xx_CPUCLK_MAX		133000000
+#define CONFIG_SYS_8xx_CPUCLK_MIN		40000000
+#define CONFIG_SYS_8xx_CPUCLK_MAX		133000000
 
-#define CFG_RESET_ADDRESS		0xC0000000
+#define CONFIG_SYS_RESET_ADDRESS		0xC0000000
 
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_LAST_STAGE_INIT
@@ -105,26 +105,26 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"=>"		/* Monitor Command Prompt	*/
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=>"		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #endif
 
-#define	CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size	*/
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size	*/
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_LOAD_ADDR		0x00100000
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
 
-#define	CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
+#define	CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 2400, 4800, 9600, 19200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 2400, 4800, 9600, 19200 }
 
 /*
  * Low Level Configuration Settings
@@ -135,42 +135,42 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR		0xF0000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for monitor	*/
 
 #ifdef CONFIG_BZIP2
-#define	CFG_MALLOC_LEN		(2500 << 10)	/* Reserve ~2.5 MB for malloc()	*/
+#define	CONFIG_SYS_MALLOC_LEN		(2500 << 10)	/* Reserve ~2.5 MB for malloc()	*/
 #else
-#define	CFG_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
+#define	CONFIG_SYS_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
 #endif /* CONFIG_BZIP2 */
 
-#define	CFG_ALLOC_DPRAM		1	/* use allocation routines	*/
+#define	CONFIG_SYS_ALLOC_DPRAM		1	/* use allocation routines	*/
 
 /*
  * Flash
@@ -178,28 +178,28 @@
 /*-----------------------------------------------------------------------
  * Flash organisation
  */
-#define CFG_FLASH_BASE          0xFE000000
-#define CFG_FLASH_CFI                           /* The flash is CFI compatible  */
+#define CONFIG_SYS_FLASH_BASE          0xFE000000
+#define CONFIG_SYS_FLASH_CFI                           /* The flash is CFI compatible  */
 #define CONFIG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
-#define CFG_MAX_FLASH_BANKS     1               /* Max number of flash banks    */
-#define CFG_MAX_FLASH_SECT      128             /* Max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS     1               /* Max number of flash banks    */
+#define CONFIG_SYS_MAX_FLASH_SECT      128             /* Max num of sects on one chip */
 
 /* Environment is in flash */
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE       0x40000         /* We use one complete sector   */
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 
 #define CONFIG_ENV_OVERWRITE
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 
 #ifdef CONFIG_CMD_DATE
 # define CONFIG_RTC_DS3231
-# define CFG_I2C_RTC_ADDR      0x68
+# define CONFIG_SYS_I2C_RTC_ADDR      0x68
 #endif
 
 /*-----------------------------------------------------------------------
@@ -210,8 +210,8 @@
 #undef CONFIG_HARD_I2C                 /* I2C with hardware support    */
 #define CONFIG_SOFT_I2C                1       /* I2C bit-banged               */
 
-#define CFG_I2C_SPEED          93000   /* 93 kHz is supposed to work   */
-#define CFG_I2C_SLAVE          0xFE
+#define CONFIG_SYS_I2C_SPEED          93000   /* 93 kHz is supposed to work   */
+#define CONFIG_SYS_I2C_SLAVE          0xFE
 
 #ifdef CONFIG_SOFT_I2C
 /*
@@ -239,10 +239,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -250,21 +250,21 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR      (SIUMCR_FRC)
+#define CONFIG_SYS_SIUMCR      (SIUMCR_FRC)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -273,8 +273,8 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-/* #define CFG_SCCR	SCCR_TBS */
-#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+/* #define CONFIG_SYS_SCCR	SCCR_TBS */
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 
@@ -283,7 +283,7 @@
  *-----------------------------------------------------------------------
  * Set to zero to prevent the processor from entering debug mode
  */
-#define CFG_DER		 0
+#define CONFIG_SYS_DER		 0
 
 
 /* Because of the way the 860 starts up and assigns CS0 the entire
@@ -299,51 +299,51 @@
  */
 
 /* BR0 and OR0 (FLASH) */
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0 */
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0 */
 
 
 /* used to re-map FLASH both when starting from SRAM or FLASH:
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_6_CLK | OR_EHTR | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
 
 /*
  * SDRAM CS1 UPMB
  */
-#define	CFG_SDRAM_BASE	0x00000000
-#define CFG_SDRAM_BASE_PRELIM CFG_SDRAM_BASE
+#define	CONFIG_SYS_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE_PRELIM CONFIG_SYS_SDRAM_BASE
 #define SDRAM_MAX_SIZE	0x4000000 /* max 64 MB */
 
-#define CFG_PRELIM_OR1_AM	0xF0000000
-/* #define CFG_OR1_TIMING  OR_CSNT_SAM/\*  | OR_G5LS /\\* *\\/ *\/ */
+#define CONFIG_SYS_PRELIM_OR1_AM	0xF0000000
+/* #define CONFIG_SYS_OR1_TIMING  OR_CSNT_SAM/\*  | OR_G5LS /\\* *\\/ *\/ */
 #define SDRAM_TIMING	OR_SCY_0_CLK	/* SDRAM-Timing */
 
-#define CFG_OR1_PRELIM	(CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING)
-#define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V)
+#define CONFIG_SYS_OR1_PRELIM	(CONFIG_SYS_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING)
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V)
 
-/* #define CFG_OR1_FINAL   ((CFG_OR1_AM & OR_AM_MSK) | CFG_OR1_TIMING) */
-/* #define CFG_BR1_FINAL   ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */
+/* #define CONFIG_SYS_OR1_FINAL   ((CONFIG_SYS_OR1_AM & OR_AM_MSK) | CONFIG_SYS_OR1_TIMING) */
+/* #define CONFIG_SYS_BR1_FINAL   ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */
 
-#define CFG_PTB_PER_CLK	((4096 * 16 * 1000) / (4 * 64))
-#define CFG_PTA_PER_CLK 195
-#define CFG_MBMR_PTB	195
-#define CFG_MPTPR	MPTPR_PTP_DIV16
-#define CFG_MAR		0x88
+#define CONFIG_SYS_PTB_PER_CLK	((4096 * 16 * 1000) / (4 * 64))
+#define CONFIG_SYS_PTA_PER_CLK 195
+#define CONFIG_SYS_MBMR_PTB	195
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV16
+#define CONFIG_SYS_MAR		0x88
 
-#define CFG_MBMR_8COL  ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
+#define CONFIG_SYS_MBMR_8COL  ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
 			MBMR_AMB_TYPE_0 | \
 			MBMR_G0CLB_A10 | \
 			MBMR_DSB_1_CYCL | \
@@ -351,7 +351,7 @@
 			MBMR_WLFB_1X | \
 			MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
 
-#define CFG_MBMR_9COL  ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
+#define CONFIG_SYS_MBMR_9COL  ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
 			MBMR_AMB_TYPE_1 | \
 			MBMR_G0CLB_A10 | \
 			MBMR_DSB_1_CYCL | \
@@ -363,27 +363,27 @@
 /*
  * DSP Host Port Interface CS3
  */
-#define CFG_SPC1920_HPI_BASE   0x90000000
-#define CFG_PRELIM_OR3_AM      0xF8000000
+#define CONFIG_SYS_SPC1920_HPI_BASE   0x90000000
+#define CONFIG_SYS_PRELIM_OR3_AM      0xF8000000
 
-#define CFG_OR3         (CFG_PRELIM_OR3_AM | \
+#define CONFIG_SYS_OR3         (CONFIG_SYS_PRELIM_OR3_AM | \
 				       OR_G5LS | \
 				       OR_SCY_0_CLK | \
 				       OR_BI)
 
-#define CFG_BR3 ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \
+#define CONFIG_SYS_BR3 ((CONFIG_SYS_SPC1920_HPI_BASE & BR_BA_MSK) | \
 					       BR_MS_UPMA | \
 					       BR_PS_16 | \
-					       BR_V);
+					       BR_V)
 
-#define CFG_MAMR (MAMR_GPL_A4DIS | \
+#define CONFIG_SYS_MAMR (MAMR_GPL_A4DIS | \
 		MAMR_RLFA_5X | \
 		MAMR_WLFA_5X)
 
 #define CONFIG_SPC1920_HPI_TEST
 
 #ifdef CONFIG_SPC1920_HPI_TEST
-#define HPI_REG(x)             (*((volatile u16 *) (CFG_SPC1920_HPI_BASE + x)))
+#define HPI_REG(x)             (*((volatile u16 *) (CONFIG_SYS_SPC1920_HPI_BASE + x)))
 #define HPI_HPIC_1             HPI_REG(0)
 #define HPI_HPIC_2             HPI_REG(2)
 #define HPI_HPIA_1             HPI_REG(0x2000008)
@@ -397,30 +397,30 @@
 /*
  * Ramtron FM18L08 FRAM 32KB on CS4
  */
-#define CFG_SPC1920_FRAM_BASE	0x80100000
-#define CFG_PRELIM_OR4_AM	0xffff8000
-#define CFG_OR4		(CFG_PRELIM_OR4_AM | \
+#define CONFIG_SYS_SPC1920_FRAM_BASE	0x80100000
+#define CONFIG_SYS_PRELIM_OR4_AM	0xffff8000
+#define CONFIG_SYS_OR4		(CONFIG_SYS_PRELIM_OR4_AM | \
 					OR_ACS_DIV2 | \
 					OR_BI | \
 					OR_SCY_4_CLK | \
 					OR_TRLX)
 
-#define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+#define CONFIG_SYS_BR4 ((CONFIG_SYS_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 
 /*
  * PLD CS5
  */
-#define CFG_SPC1920_PLD_BASE	0x80000000
-#define CFG_PRELIM_OR5_AM	0xffff8000
+#define CONFIG_SYS_SPC1920_PLD_BASE	0x80000000
+#define CONFIG_SYS_PRELIM_OR5_AM	0xffff8000
 
-#define CFG_OR5_PRELIM		(CFG_PRELIM_OR5_AM | \
+#define CONFIG_SYS_OR5_PRELIM		(CONFIG_SYS_PRELIM_OR5_AM | \
 					OR_CSNT_SAM | \
 					OR_ACS_DIV1 | \
 					OR_BI | \
 					OR_SCY_0_CLK | \
 					OR_TRLX)
 
-#define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 
 /*
  * Internal Definitions
diff --git a/include/configs/spieval.h b/include/configs/spieval.h
index ab1c6f4..27dda25 100644
--- a/include/configs/spieval.h
+++ b/include/configs/spieval.h
@@ -39,7 +39,7 @@
 #define CONFIG_STK52XX		1	/* ... on a STK52XX base board */
 #define CONFIG_STK52XX_REV100	1	/*  define for revision 100 baseboards */
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
@@ -51,13 +51,13 @@
  */
 #define CONFIG_PSC_CONSOLE	6	/* console is on PSC6 */
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #ifdef CONFIG_STK52XX
 #undef CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
 #define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
 #define CONFIG_PS2SERIAL	6	/* .. on PSC6			*/
-#define CONFIG_PS2MULT_DELAY	(CFG_HZ/2)	/* Initial delay	*/
+#define CONFIG_PS2MULT_DELAY	(CONFIG_SYS_HZ/2)	/* Initial delay	*/
 #define CONFIG_BOARD_EARLY_INIT_R
 #endif /* CONFIG_STK52XX */
 
@@ -81,7 +81,7 @@
 
 #define CONFIG_NET_MULTI	1
 #define CONFIG_EEPRO100		1
-#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
 #define CONFIG_NS8382X		1
 #endif	/* CONFIG_STK52XX */
 
@@ -98,7 +98,7 @@
 #define CONFIG_CONSOLE_EXTRA_INFO
 #define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_SPLASH_SCREEN
-#define CFG_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #endif
 
 /* Partitions */
@@ -113,9 +113,9 @@
 #endif
 
 /* POST support */
-#define CONFIG_POST		(CFG_POST_MEMORY   | \
-				 CFG_POST_CPU	   | \
-				 CFG_POST_I2C)
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_I2C)
 
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
@@ -177,7 +177,7 @@
 #define	CONFIG_TIMESTAMP		/* display image timestamps */
 
 #if (TEXT_BASE == 0xFC000000)		/* Boot low */
-#   define CFG_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT		1
 #endif
 
 /*
@@ -219,17 +219,17 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
-#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
+#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
  * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
+#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
 
 /*
@@ -237,9 +237,9 @@
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
 #ifdef CONFIG_TQM5200_REV100
-#define CFG_I2C_MODULE		1	/* Select I2C module #1 for rev. 100 board */
+#define CONFIG_SYS_I2C_MODULE		1	/* Select I2C module #1 for rev. 100 board */
 #else
-#define CFG_I2C_MODULE		2	/* Select I2C module #2 for all other revs */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #2 for all other revs */
 #endif
 
 /*
@@ -248,11 +248,11 @@
  * Please notice, that the resulting clock frequency could differ from the
  * configured value. This is because the I2C clock is derived from system
  * clock over a frequency divider with only a few divider values. U-boot
- * calculates the best approximation for CFG_I2C_SPEED. However the calculated
+ * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
  * approximation allways lies below the configured value, never above.
  */
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
@@ -260,49 +260,49 @@
  * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
  * same configuration could be used.
  */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CFG_I2C_EEPROM_ADDR_LEN		2
-#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
 
 /*
  * HW-Monitor configuration on Mini-FAP
  */
 #if defined (CONFIG_MINIFAP)
-#define CFG_I2C_HWMON_ADDR		0x2C
+#define CONFIG_SYS_I2C_HWMON_ADDR		0x2C
 #endif
 
 /* List of I2C addresses to be verified by POST */
 #if defined (CONFIG_MINIFAP)
 #undef I2C_ADDR_LIST
-#define I2C_ADDR_LIST	{	CFG_I2C_EEPROM_ADDR,	\
-				CFG_I2C_HWMON_ADDR,	\
-				CFG_I2C_SLAVE }
+#define I2C_ADDR_LIST	{	CONFIG_SYS_I2C_EEPROM_ADDR,	\
+				CONFIG_SYS_I2C_HWMON_ADDR,	\
+				CONFIG_SYS_I2C_SLAVE }
 #endif
 
 /*
  * Flash configuration
  */
-#define CFG_FLASH_BASE		TEXT_BASE /* 0xFC000000 */
+#define CONFIG_SYS_FLASH_BASE		TEXT_BASE /* 0xFC000000 */
 
 /* use CFI flash driver if no module variant is spezified */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
-#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
-#undef CFG_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
-
-#if !defined(CFG_LOWBOOT)
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00760000 + 0x00800000)
-#else	/* CFG_LOWBOOT */
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
-#endif	/* CFG_LOWBOOT */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_BOOTCS_START }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MByte */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
+
+#if !defined(CONFIG_SYS_LOWBOOT)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
+#else	/* CONFIG_SYS_LOWBOOT */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
+#endif	/* CONFIG_SYS_LOWBOOT */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
 					   (= chip selects) */
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
 
 
 /*
@@ -317,32 +317,32 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /* Use ON-Chip SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
 #else
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
 #endif
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
@@ -381,19 +381,19 @@
  *   tests.
  */
 #if defined (CONFIG_MINIFAP)
-# define CFG_GPS_PORT_CONFIG	0x91000004
+# define CONFIG_SYS_GPS_PORT_CONFIG	0x91000004
 #elif defined (CONFIG_STK52XX)
 # if defined (CONFIG_STK52XX_REV100)
-#  define CFG_GPS_PORT_CONFIG	0x81500014
+#  define CONFIG_SYS_GPS_PORT_CONFIG	0x81500014
 # else /* STK52xx REV200 and above */
 #  if defined (CONFIG_TQM5200_REV100)
 #   error TQM5200 REV100 not supported on STK52XX REV200 or above
 #  else/* TQM5200 REV200 and above */
-#   define CFG_GPS_PORT_CONFIG	0x91500004
+#   define CONFIG_SYS_GPS_PORT_CONFIG	0x91500004
 #  endif
 # endif
 #else  /* TMQ5200 Inbetriebnahme-Board */
-# define CFG_GPS_PORT_CONFIG	0x81000004
+# define CONFIG_SYS_GPS_PORT_CONFIG	0x81000004
 #endif
 
 /*
@@ -404,30 +404,30 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
 /* Enable an alternate, more extensive memory test */
-#define CFG_ALT_MEMTEST
+#define CONFIG_SYS_ALT_MEMTEST
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*
@@ -439,22 +439,22 @@
  * Various low-level settings
  */
 #if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 #else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
 #endif
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
-#define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
+#define CONFIG_SYS_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
 #else
-#define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
+#define CONFIG_SYS_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
 #endif
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
 #define CONFIG_LAST_STAGE_INIT
 
@@ -462,24 +462,24 @@
  * SRAM - Do not map below 2 GB in address space, because this area is used
  * for SDRAM autosizing.
  */
-#define CFG_CS2_START		0xE5000000
-#define CFG_CS2_SIZE		0x100000	/* 1 MByte */
-#define CFG_CS2_CFG		0x0004D930
+#define CONFIG_SYS_CS2_START		0xE5000000
+#define CONFIG_SYS_CS2_SIZE		0x100000	/* 1 MByte */
+#define CONFIG_SYS_CS2_CFG		0x0004D930
 
 /*
  * Grafic controller - Do not map below 2 GB in address space, because this
  * area is used for SDRAM autosizing.
  */
 #define SM501_FB_BASE		0xE0000000
-#define CFG_CS1_START		(SM501_FB_BASE)
-#define CFG_CS1_SIZE		0x4000000	/* 64 MByte */
-#define CFG_CS1_CFG		0x8F48FF70
-#define SM501_MMIO_BASE		CFG_CS1_START + 0x03E00000
+#define CONFIG_SYS_CS1_START		(SM501_FB_BASE)
+#define CONFIG_SYS_CS1_SIZE		0x4000000	/* 64 MByte */
+#define CONFIG_SYS_CS1_CFG		0x8F48FF70
+#define SM501_MMIO_BASE		CONFIG_SYS_CS1_START + 0x03E00000
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
 
-#define CFG_RESET_ADDRESS	0xff000000
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
 
 /*-----------------------------------------------------------------------
  * USB stuff
@@ -501,23 +501,23 @@
 #define CONFIG_IDE_RESET		/* reset for ide supported	*/
 #define CONFIG_IDE_PREINIT
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(0x0060)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005C)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
 
 /* Interval between registers						     */
-#define CFG_ATA_STRIDE		4
+#define CONFIG_SYS_ATA_STRIDE		4
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index e06256d..0424e29 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -64,55 +64,54 @@
  */
 #define CONFIG_L2_CACHE                     /* toggle L2 cache         */
 #define  CONFIG_BTB                          /* toggle branch predition */
-#define  CONFIG_ADDR_STREAMING               /* toggle addr streaming   */
 
 #define CONFIG_BOARD_EARLY_INIT_F   1        /* Call board_pre_init      */
 
-#undef  CFG_DRAM_TEST                       /* memory test, takes time  */
-#define CFG_MEMTEST_START       0x00200000  /* memtest region */
-#define CFG_MEMTEST_END         0x00400000
+#undef  CONFIG_SYS_DRAM_TEST                       /* memory test, takes time  */
+#define CONFIG_SYS_MEMTEST_START       0x00200000  /* memtest region */
+#define CONFIG_SYS_MEMTEST_END         0x00400000
 
 
 /* Localbus SDRAM is an option, not all boards have it.
  * This address, however, is used to configure a 256M local bus
  * window that includes the Config latch below.
  */
-#define CFG_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
-#define CFG_LBC_SDRAM_SIZE	256		/* LBC SDRAM is 64MB	*/
+#define CONFIG_SYS_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	256		/* LBC SDRAM is 64MB	*/
 
-#define CFG_FLASH_BASE        0xff000000      /* start of FLASH 16M    */
-#define CFG_BR0_PRELIM        0xff001801      /* port size 32bit      */
+#define CONFIG_SYS_FLASH_BASE        0xff000000      /* start of FLASH 16M    */
+#define CONFIG_SYS_BR0_PRELIM        0xff001801      /* port size 32bit      */
 
-#define CFG_OR0_PRELIM          0xff000ff7      /* 16 MB Flash           */
-#define CFG_MAX_FLASH_BANKS	1		/* number of banks	*/
-#define CFG_MAX_FLASH_SECT	136		/* sectors per device   */
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_OR0_PRELIM          0xff000ff7      /* 16 MB Flash           */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	136		/* sectors per device   */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 /* The configuration latch is Chip Select 1.
  * It's an 8-bit latch in the lower 8 bits of the word.
  */
-#define CFG_BR1_PRELIM		0xfc001801	/* 32-bit port */
-#define CFG_OR1_PRELIM		0xffff0ff7      /* 64K is enough */
-#define CFG_LBC_LCLDEVS_BASE	0xfc000000	/* Base of localbus devices */
+#define CONFIG_SYS_BR1_PRELIM		0xfc001801	/* 32-bit port */
+#define CONFIG_SYS_OR1_PRELIM		0xffff0ff7      /* 64K is enough */
+#define CONFIG_SYS_LBC_LCLDEVS_BASE	0xfc000000	/* Base of localbus devices */
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef  CFG_RAMBOOT
+#undef  CONFIG_SYS_RAMBOOT
 #endif
 
-#ifdef CFG_RAMBOOT
-#define CFG_CCSRBAR_DEFAULT	0x40000000	/* CCSRBAR by BDI cfg	*/
+#ifdef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0x40000000	/* CCSRBAR by BDI cfg	*/
 #else
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
 #endif
-#define CFG_CCSRBAR             0xfdf00000      /* relocated CCSRBAR    */
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
+#define CONFIG_SYS_CCSRBAR             0xfdf00000      /* relocated CCSRBAR    */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR	*/
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR1
@@ -126,8 +125,8 @@
 
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
@@ -139,29 +138,28 @@
 #undef CONFIG_CLOCKS_IN_MHZ
 
 /* local bus definitions */
-#define CFG_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM  */
-#define CFG_OR2_PRELIM		0xfc006901
-#define CFG_LBC_LCRR		0x00030004	/* local bus freq	*/
-#define CFG_LBC_LBCR		0x00000000
-#define CFG_LBC_LSRT		0x20000000
-#define CFG_LBC_MRTPR		0x20000000
-#define CFG_LBC_LSDMR_1		0x2861b723
-#define CFG_LBC_LSDMR_2		0x0861b723
-#define CFG_LBC_LSDMR_3		0x0861b723
-#define CFG_LBC_LSDMR_4		0x1861b723
-#define CFG_LBC_LSDMR_5		0x4061b723
-
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR       0x60000000      /* Initial RAM address  */
-#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
-
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
+#define CONFIG_SYS_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM  */
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
+#define CONFIG_SYS_LBC_LCRR		0x00030004	/* local bus freq	*/
+#define CONFIG_SYS_LBC_LBCR		0x00000000
+#define CONFIG_SYS_LBC_LSRT		0x20000000
+#define CONFIG_SYS_LBC_MRTPR		0x20000000
+#define CONFIG_SYS_LBC_LSDMR_1		0x2861b723
+#define CONFIG_SYS_LBC_LSDMR_2		0x0861b723
+#define CONFIG_SYS_LBC_LSDMR_3		0x0861b723
+#define CONFIG_SYS_LBC_LSDMR_4		0x1861b723
+#define CONFIG_SYS_LBC_LSDMR_5		0x4061b723
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR       0x60000000      /* Initial RAM address  */
+#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_ON_SCC		/* define if console on SCC */
@@ -170,13 +168,13 @@
 
 #define CONFIG_BAUDRATE		38400
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /*
@@ -185,30 +183,30 @@
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 #if 0
-#define CFG_I2C_NOPROBES        {0x00}  /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_NOPROBES        {0x00}  /* Don't probe these addrs */
 #else
 /* I did the 'if 0' so we could keep the syntax above if ever needed. */
-#undef CFG_I2C_NOPROBES
+#undef CONFIG_SYS_I2C_NOPROBES
 #endif
-#define CFG_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C_OFFSET		0x3000
 
 /* RapdIO Map configuration, mapped 1:1.
 */
-#define CFG_RIO_MEM_BASE	0xc0000000
-#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
-#define CFG_RIO_MEM_SIZE	0x200000000	/* 512 M */
+#define CONFIG_SYS_RIO_MEM_BASE	0xc0000000
+#define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BASE
+#define CONFIG_SYS_RIO_MEM_SIZE	0x200000000	/* 512 M */
 
 /* Standard 8560 PCI addressing, mapped 1:1.
 */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0xe2000000
-#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE	0x01000000	/* 16 M */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_BASE	0xe2000000
+#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000	/* 16 M */
 
 #if defined(CONFIG_PCI)			/* PCI Ethernet card */
 
@@ -225,7 +223,7 @@
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW
-#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
 #endif /* CONFIG_PCI */
 
@@ -263,13 +261,13 @@
    * - Select bus for bd/buffers
    * - Full duplex
    */
-  #define CFG_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-  #define CFG_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-  #define CFG_CPMFCR_RAMTYPE    0
+  #define CONFIG_SYS_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+  #define CONFIG_SYS_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+  #define CONFIG_SYS_CPMFCR_RAMTYPE    0
 #if 0
-  #define CFG_FCC_PSMR          (FCC_PSMR_FDE)
+  #define CONFIG_SYS_FCC_PSMR          (FCC_PSMR_FDE)
 #else
-  #define CFG_FCC_PSMR          0
+  #define CONFIG_SYS_FCC_PSMR          0
 #endif
   #define FETH2_RST		0x01
 #elif (CONFIG_ETHER_INDEX == 3)
@@ -287,15 +285,15 @@
 /* Environment */
 /* We use the top boot sector flash, so we have some 16K sectors for env
  */
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
   #define CONFIG_ENV_IS_IN_FLASH	1
-  #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x60000)
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x60000)
   #define CONFIG_ENV_SECT_SIZE	0x4000	/* 16K (one top sector) for env */
   #define CONFIG_ENV_SIZE		0x2000
 #else
-  #define CFG_NO_FLASH		1	/* Flash is not usable now	*/
+  #define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now	*/
   #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
-  #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
   #define CONFIG_ENV_SIZE		0x2000
 #endif
 
@@ -304,7 +302,7 @@
 #define CONFIG_BOOTDELAY	3	/* -1 disable autoboot */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 /*
  * BOOTP options
@@ -323,8 +321,8 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
 
-#if defined(CFG_RAMBOOT)
-    #undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #else
     #define CONFIG_CMD_ELF
@@ -344,25 +342,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"GPPP=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"GPPP=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x1000000	/* default load address */
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*
  * Internal Definitions
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index 5926943..2783f9e 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -64,13 +64,12 @@
  */
 #define CONFIG_L2_CACHE				/* toggle L2 cache	       */
 #define  CONFIG_BTB				/* toggle branch predition */
-#define  CONFIG_ADDR_STREAMING			/* toggle addr streaming	*/
 
 #define CONFIG_BOARD_EARLY_INIT_F   1		/* Call board_pre_init	 */
 
-#undef	CFG_DRAM_TEST				/* memory test, takes time	*/
-#define CFG_MEMTEST_START	0x00200000	/* memtest region */
-#define CFG_MEMTEST_END		0x00400000
+#undef	CONFIG_SYS_DRAM_TEST				/* memory test, takes time	*/
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
 
 
 /* Localbus connector.	There are many options that can be
@@ -78,54 +77,54 @@
  * This address, however, is used to configure a 256M local bus
  * window that includes the Config latch below.
  */
-#define CFG_LBC_OPTION_BASE	0xF0000000	/* Localbus Extension */
-#define CFG_LBC_OPTION_SIZE	256		/* 256MB */
+#define CONFIG_SYS_LBC_OPTION_BASE	0xF0000000	/* Localbus Extension */
+#define CONFIG_SYS_LBC_OPTION_SIZE	256		/* 256MB */
 
 /* There are various flash options used, we configure for the largest,
  * which is 64Mbytes.  The CFI works fine and will discover the proper
  * sizes.
  */
 #ifdef CONFIG_STXSSA_4M
-#define CFG_FLASH_BASE		0xFFC00000	/* start of  4 MiB flash */
+#define CONFIG_SYS_FLASH_BASE		0xFFC00000	/* start of  4 MiB flash */
 #else
-#define CFG_FLASH_BASE		0xFC000000	/* start of 64 MiB flash */
+#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* start of 64 MiB flash */
 #endif
-#define CFG_BR0_PRELIM	(CFG_FLASH_BASE | 0x1801) /* port size 32bit	 */
-#define CFG_OR0_PRELIM	(CFG_FLASH_BASE | 0x0FF7)
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | 0x1801) /* port size 32bit	 */
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_FLASH_BASE | 0x0FF7)
 
-#define CFG_FLASH_CFI		1
+#define CONFIG_SYS_FLASH_CFI		1
 #define CONFIG_FLASH_CFI_DRIVER	1
-#undef CFG_FLASH_USE_BUFFER_WRITE	/* use buffered writes (20x faster) */
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	*/
+#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* use buffered writes (20x faster) */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	*/
 
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 
-#define CFG_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_PROTECTION
 
 /* The configuration latch is Chip Select 1.
  * It's an 8-bit latch in the lower 8 bits of the word.
  */
-#define CFG_LBC_CFGLATCH_BASE	0xFB000000	/* Base of config latch */
-#define CFG_BR1_PRELIM		0xFB001801	/* 32-bit port */
-#define CFG_OR1_PRELIM		0xFFFF0FF7	/* 64K is enough */
+#define CONFIG_SYS_LBC_CFGLATCH_BASE	0xFB000000	/* Base of config latch */
+#define CONFIG_SYS_BR1_PRELIM		0xFB001801	/* 32-bit port */
+#define CONFIG_SYS_OR1_PRELIM		0xFFFF0FF7	/* 64K is enough */
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef	CFG_RAMBOOT
+#undef	CONFIG_SYS_RAMBOOT
 #endif
 
-#ifdef CFG_RAMBOOT
-#define CFG_CCSRBAR_DEFAULT	0x40000000	/* CCSRBAR by BDI cfg	*/
+#ifdef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0x40000000	/* CCSRBAR by BDI cfg	*/
 #else
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
 #endif
-#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR	*/
-#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
+#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR	*/
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR	*/
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR1
@@ -139,8 +138,8 @@
 
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
@@ -152,48 +151,47 @@
 #undef CONFIG_CLOCKS_IN_MHZ
 
 /* local bus definitions */
-#define CFG_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM	*/
-#define CFG_OR2_PRELIM		0xfc006901
-#define CFG_LBC_LCRR		0x00030004	/* local bus freq	*/
-#define CFG_LBC_LBCR		0x00000000
-#define CFG_LBC_LSRT		0x20000000
-#define CFG_LBC_MRTPR		0x20000000
-#define CFG_LBC_LSDMR_1		0x2861b723
-#define CFG_LBC_LSDMR_2		0x0861b723
-#define CFG_LBC_LSDMR_3		0x0861b723
-#define CFG_LBC_LSDMR_4		0x1861b723
-#define CFG_LBC_LSDMR_5		0x4061b723
-
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0x60000000	/* Initial RAM address	*/
-#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
-
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */
+#define CONFIG_SYS_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM	*/
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
+#define CONFIG_SYS_LBC_LCRR		0x00030004	/* local bus freq	*/
+#define CONFIG_SYS_LBC_LBCR		0x00000000
+#define CONFIG_SYS_LBC_LSRT		0x20000000
+#define CONFIG_SYS_LBC_MRTPR		0x20000000
+#define CONFIG_SYS_LBC_LSDMR_1		0x2861b723
+#define CONFIG_SYS_LBC_LSDMR_2		0x0861b723
+#define CONFIG_SYS_LBC_LSDMR_3		0x0861b723
+#define CONFIG_SYS_LBC_LSDMR_4		0x1861b723
+#define CONFIG_SYS_LBC_LSDMR_5		0x4061b723
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x60000000	/* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     2
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 
-#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /*
@@ -202,40 +200,39 @@
 #define CONFIG_FSL_I2C			/* Use FSL common I2C driver */
 #define  CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-#undef CFG_I2C_NOPROBES
-#define CFG_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#undef CONFIG_SYS_I2C_NOPROBES
+#define CONFIG_SYS_I2C_OFFSET		0x3000
 
 /* I2C RTC */
 #define CONFIG_RTC_DS1337		/* This is really a DS1339 RTC	*/
-#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68		*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68		*/
 
 /* I2C EEPROM.	AT24C32, we keep our environment in here.
 */
-#define CFG_I2C_EEPROM_ADDR		0x51	/* 1010001x		*/
-#define CFG_I2C_EEPROM_ADDR_LEN		2
-#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write	*/
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x51	/* 1010001x		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
 
 /*
  * Standard 8555 PCI mapping.
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xe2000000
-#define CFG_PCI1_IO_SIZE	0x01000000	/* 16M */
-
-#define CFG_PCI2_MEM_BASE	0xa0000000
-#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI2_IO_BASE	0x00000000
-#define CFG_PCI2_IO_PHYS	0xe3000000
-#define CFG_PCI2_IO_SIZE	0x01000000	/* 16M */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000	/* 16M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS	0xe3000000
+#define CONFIG_SYS_PCI2_IO_SIZE	0x01000000	/* 16M */
 
 #if defined(CONFIG_PCI)			/* PCI Ethernet card */
 #define CONFIG_MPC85XX_PCI2	1
@@ -252,7 +249,7 @@
 #endif
 
 #define CONFIG_PCI_SCAN_SHOW
-#define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
 
 #endif /* CONFIG_PCI */
 
@@ -290,13 +287,13 @@
    * - Select bus for bd/buffers
    * - Full duplex
    */
-  #define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-  #define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-  #define CFG_CPMFCR_RAMTYPE	0
+  #define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+  #define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+  #define CONFIG_SYS_CPMFCR_RAMTYPE	0
 #if 0
-  #define CFG_FCC_PSMR		(FCC_PSMR_FDE)
+  #define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE)
 #else
-  #define CFG_FCC_PSMR		0
+  #define CONFIG_SYS_FCC_PSMR		0
 #endif
   #define FETH2_RST		0x01
 #elif (CONFIG_ETHER_INDEX == 3)
@@ -323,14 +320,14 @@
 # else	/* default configuration - 64 MiB flash */
 #  define CONFIG_ENV_SECT_SIZE	0x40000
 # endif
-# define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+# define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 # define CONFIG_ENV_SIZE		0x4000
 # define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 # define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define	CONFIG_TIMESTAMP		/* Print image info with ts	*/
 
@@ -365,8 +362,8 @@
     #define CONFIG_CMD_MII
 #endif
 
-#if defined(CFG_RAMBOOT)
-    #undef CONFIG_CMD_ENV
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #else
     #define CONFIG_CMD_ELF
@@ -378,25 +375,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"SSA=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"SSA=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x1000000	/* default load address */
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
 
 /*
  * Internal Definitions
diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
index 7ba8b77..5a5f772 100644
--- a/include/configs/stxxtc.h
+++ b/include/configs/stxxtc.h
@@ -70,7 +70,7 @@
 
 #define CONFIG_AUTOSCRIPT
 #define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -95,7 +95,7 @@
 
 #define	CONFIG_NET_MULTI	1	/* the only way to get the FEC in */
 #define	FEC_ENET		1	/* eth.c needs it that way... */
-#undef CFG_DISCOVER_PHY
+#undef CONFIG_SYS_DISCOVER_PHY
 #define CONFIG_MII		1
 #define CONFIG_MII_INIT		1
 #undef CONFIG_RMII
@@ -129,29 +129,29 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"xtc> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"xtc> "		/* Monitor Command Prompt	*/
 
-#define CFG_HUSH_PARSER	1
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER	1
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0300000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -161,42 +161,42 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFF000000
+#define CONFIG_SYS_IMMR		0xFF000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
 #if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
 
 /* yes this is weird, I know :) */
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE | 0x00F00000)
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE | 0x00F00000)
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
-#define CFG_RESET_ADDRESS	0x80000000
+#define CONFIG_SYS_RESET_ADDRESS	0x80000000
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
@@ -204,30 +204,30 @@
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SECT_SIZE	0x10000
 
-#define	CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00000000)
+#define	CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00000000)
 #define CONFIG_ENV_OFFSET		0
 #define	CONFIG_ENV_SIZE		0x4000
 
-#define CONFIG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + 0x00010000)
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + 0x00010000)
 #define CONFIG_ENV_OFFSET_REDUND	0
 #define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
 
-#define CFG_FLASH_CFI		1
+#define CONFIG_SYS_FLASH_CFI		1
 #define CONFIG_FLASH_CFI_DRIVER	1
-#undef CFG_FLASH_USE_BUFFER_WRITE	/* use buffered writes (20x faster) */
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
+#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* use buffered writes (20x faster) */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
 
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + 0x2000000 }
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x2000000 }
 
-#define CFG_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_PROTECTION
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -237,10 +237,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -248,27 +248,27 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -281,11 +281,11 @@
 #if CONFIG_XIN == 10000000
 
 #if MPC8XX_HZ == 50000000
-#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 66666666
-#define CFG_PLPRCR	((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
+#define CONFIG_SYS_PLPRCR	((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 			 PLPRCR_TEXPS)
 #else
@@ -308,12 +308,12 @@
 
 #define SCCR_MASK	SCCR_EBDF11
 #if MPC8XX_HZ > 66666666
-#define CFG_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00 | SCCR_EBDF01)
 #else
-#define CFG_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -324,8 +324,8 @@
  *-----------------------------------------------------------------------
  *
  */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -343,18 +343,18 @@
 
 #define FLASH_BANK_MAX_SIZE	0x01000000	/* max size per chip */
 
-#define CFG_REMAP_OR_AM		0x80000000
-#define CFG_PRELIM_OR_AM	(0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000
+#define CONFIG_SYS_PRELIM_OR_AM	(0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
 
 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 
-#define CFG_OR1_PRELIM	((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CFG_OR_TIMING_FLASH)
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_OR1_PRELIM	((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 
 /*
  * BR4 and OR4 (SDRAM)
@@ -364,10 +364,10 @@
 #define	SDRAM_MAX_SIZE		(256 << 20)	/* max 256MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
+#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
 
-#define CFG_OR4_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
-#define CFG_BR4_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
+#define CONFIG_SYS_OR4_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
+#define CONFIG_SYS_BR4_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
 
 /*
  * Memory Periodic Timer Prescaler
@@ -400,34 +400,34 @@
  * 80 Mhz => 80.000.000 / Divider = 156
  */
 
-#define CFG_MAMR_PTA		 234
+#define CONFIG_SYS_MAMR_PTA		 234
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
@@ -450,12 +450,12 @@
 
 /* NAND */
 #define CONFIG_NAND_LEGACY
-#define CFG_NAND_BASE		NAND_BASE
+#define CONFIG_SYS_NAND_BASE		NAND_BASE
 #define CONFIG_MTD_NAND_ECC_JFFS2
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_MTD_NAND_UNSAFE
 
-#define CFG_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
 #undef NAND_NO_RB
 
 #define SECTORSIZE		512
@@ -464,44 +464,43 @@
 #define ADDR_COLUMN_PAGE	3
 #define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS		1
-#define NAND_MAX_CHIPS		1
 
 /* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */
 #define NAND_DISABLE_CE(nand) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) |=  (1 << (15 - 7)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat) |=  (1 << (15 - 7)); \
 	} while(0)
 
 #define NAND_ENABLE_CE(nand) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \
 	} while(0)
 
 #define NAND_CTL_CLRALE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \
 	} while(0)
 
 #define NAND_CTL_SETALE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) |=  (1 << (15 - 15)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) |=  (1 << (15 - 15)); \
 	} while(0)
 
 #define NAND_CTL_CLRCLE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \
 	} while(0)
 
 #define NAND_CTL_SETCLE(nandptr) \
 	do { \
-		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) |=  (1 << (31 - 23)); \
+		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |=  (1 << (31 - 23)); \
 	} while(0)
 
 #ifndef NAND_NO_RB
 #define NAND_WAIT_READY(nand) \
 	do { \
 		int _tries = 0; \
-		while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \
+		while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \
 			if (++_tries > 100000) \
 				break; \
 	} while (0)
@@ -529,8 +528,8 @@
 
 /*****************************************************************************/
 
-#define CFG_DIRECT_FLASH_TFTP
-#define CFG_DIRECT_NAND_TFTP
+#define CONFIG_SYS_DIRECT_FLASH_TFTP
+#define CONFIG_SYS_DIRECT_NAND_TFTP
 
 /*****************************************************************************/
 
@@ -539,7 +538,7 @@
  */
 #define STATUS_LED_BIT		0x00000080		/* bit 24 */
 
-#define STATUS_LED_PERIOD	(CFG_HZ / 2)
+#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
 #define STATUS_LED_STATE	STATUS_LED_BLINKING
 
 #define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
@@ -554,15 +553,15 @@ typedef unsigned int led_id_t;
 
 #define __led_toggle(_msk) \
 	do { \
-		((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
+		((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
 	} while(0)
 
 #define __led_set(_msk, _st) \
 	do { \
 		if ((_st)) \
-			((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
+			((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
 		else \
-			((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
+			((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
 	} while(0)
 
 #define __led_init(msk, st) __led_set(msk, st)
@@ -571,9 +570,9 @@ typedef unsigned int led_id_t;
 
 /******************************************************************************/
 
-#define CFG_CONSOLE_IS_IN_ENV		1
-#define CFG_CONSOLE_OVERWRITE_ROUTINE	1
-#define CFG_CONSOLE_ENV_OVERWRITE	1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE	1
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE	1
 
 /******************************************************************************/
 
diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h
index cc9f6bd..353e8db 100644
--- a/include/configs/suzaku.h
+++ b/include/configs/suzaku.h
@@ -36,21 +36,21 @@
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x80000000
-#define CFG_SDRAM_SIZE		0x01000000
-#define CFG_FLASH_BASE		0xfff00000
-#define CFG_FLASH_SIZE		0x00400000
-#define CFG_RESET_ADDRESS	0xfff00100
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MONITOR_BASE	(CFG_SDRAM_BASE + CFG_SDRAM_SIZE - (1024 * 1024))
-#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - (1024 * 1024))
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_SDRAM_SIZE		0x01000000
+#define CONFIG_SYS_FLASH_BASE		0xfff00000
+#define CONFIG_SYS_FLASH_SIZE		0x00400000
+#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - (1024 * 1024))
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - (1024 * 1024))
 
 #define CONFIG_XILINX_UARTLITE
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
 
 /* System Register (GPIO) */
 #define MICROBLAZE_SYSREG_BASE_ADDR 0xFFFFA000
@@ -62,30 +62,30 @@
 #include <config_cmd_default.h>
 
 #undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
 #undef CONFIG_CMD_MEMORY
 #undef CONFIG_CMD_NET
 #undef CONFIG_CMD_MISC
 
-#define CFG_UART1_BASE		(0xFFFF2000)
-#define CONFIG_SERIAL_BASE	CFG_UART1_BASE
+#define CONFIG_SYS_UART1_BASE		(0xFFFF2000)
+#define CONFIG_SERIAL_BASE	CONFIG_SYS_UART1_BASE
 
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"SUZAKU> "	/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"SUZAKU> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
 
-#define CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* default load address		*/
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE	/* default load address		*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	1	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	1	/* max number of sectors on one chip	*/
 
 /*-----------------------------------------------------------------------
  * NVRAM organization
@@ -98,11 +98,11 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 
-#define CFG_INIT_RAM_ADDR	0x80000000	/* inside of SDRAM */
-#define CFG_INIT_RAM_END	0x2000		/* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000	/* inside of SDRAM */
+#define CONFIG_SYS_INIT_RAM_END	0x2000		/* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define XILINX_CLOCK_FREQ	50000000
 #define CONFIG_XILINX_CLOCK_FREQ	XILINX_CLOCK_FREQ
diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h
index 9507846..3917a1b 100644
--- a/include/configs/svm_sc8xx.h
+++ b/include/configs/svm_sc8xx.h
@@ -54,7 +54,7 @@
 /* #define CONFIG_SDRAM_16M */
 #define CONFIG_SDRAM_32M
 /* #define CONFIG_SDRAM_64M */
-#define CFG_RESET_ADDRESS 0xffffffff
+#define CONFIG_SYS_RESET_ADDRESS 0xffffffff
 /*
  * High Level Configuration Options
  * (easy to change)
@@ -114,7 +114,7 @@
 	"tftpboot 0x210000 pImage-sc855t;bootm 0x210000"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 
 #ifdef CONFIG_LCD
@@ -156,30 +156,30 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2     "> "
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -189,43 +189,43 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFF000000
+#define CONFIG_SYS_IMMR		0xFF000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(384 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 
@@ -248,16 +248,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x46454C38	/* 'SVM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x46454C38	/* 'SVM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -267,13 +267,13 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-/*#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+/*#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 */
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR 0xffffff88
+#define CONFIG_SYS_SYPCR 0xffffff88
 #endif
 
 /*-----------------------------------------------------------------------
@@ -282,10 +282,10 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef	CONFIG_CAN_DRIVER
-/*#define CFG_SIUMCR 0x00610c00	*/
-#define CFG_SIUMCR 0x00000000
+/*#define CONFIG_SYS_SIUMCR 0x00610c00	*/
+#define CONFIG_SYS_SIUMCR 0x00000000
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -293,20 +293,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	0x0001
+#define CONFIG_SYS_TBSCR	0x0001
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	0x00c3
+#define CONFIG_SYS_RTCSC	0x00c3
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	0x0000
+#define CONFIG_SYS_PISCR	0x0000
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -315,19 +315,19 @@
  * interrupt status bit
  */
 #if defined (CONFIG_100MHz)
-#define CFG_PLPRCR 0x06301000
+#define CONFIG_SYS_PLPRCR 0x06301000
 #define CONFIG_8xx_GCLK_FREQ 100000000
 #elif defined (CONFIG_80MHz)
-#define CFG_PLPRCR 0x04f01000
+#define CONFIG_SYS_PLPRCR 0x04f01000
 #define CONFIG_8xx_GCLK_FREQ 80000000
 #elif defined(CONFIG_75MHz)
-#define CFG_PLPRCR 0x04a00100
+#define CONFIG_SYS_PLPRCR 0x04a00100
 #define CONFIG_8xx_GCLK_FREQ 75000000
 #elif defined(CONFIG_66MHz)
-#define CFG_PLPRCR 0x04101000
+#define CONFIG_SYS_PLPRCR 0x04101000
 #define CONFIG_8xx_GCLK_FREQ 66000000
 #elif defined(CONFIG_50MHz)
-#define CFG_PLPRCR 0x03101000
+#define CONFIG_SYS_PLPRCR 0x03101000
 #define CONFIG_8xx_GCLK_FREQ 50000000
 #endif
 
@@ -339,9 +339,9 @@
  */
 #define SCCR_MASK	SCCR_EBDF11
 #ifdef	CONFIG_BUS_DIV2
-#define CFG_SCCR	0x02020000 | SCCR_RTSEL
+#define CONFIG_SYS_SCCR	0x02020000 | SCCR_RTSEL
 #else			/* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR    0x02000000 | SCCR_RTSEL
+#define CONFIG_SYS_SCCR    0x02000000 | SCCR_RTSEL
 #endif
 
 /*-----------------------------------------------------------------------
@@ -349,14 +349,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -369,28 +369,28 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_BASE_ADDR       0xFE100010
-#define CFG_ATA_IDE0_OFFSET     0x0000
-/*#define CFG_ATA_IDE1_OFFSET     0x0C00 */
-#define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O
+#define CONFIG_SYS_ATA_BASE_ADDR       0xFE100010
+#define CONFIG_SYS_ATA_IDE0_OFFSET     0x0000
+/*#define CONFIG_SYS_ATA_IDE1_OFFSET     0x0C00 */
+#define CONFIG_SYS_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O
 					   */
-#define CFG_ATA_REG_OFFSET      0x0200  /* Offset for normal register accesses
+#define CONFIG_SYS_ATA_REG_OFFSET      0x0200  /* Offset for normal register accesses
 					   */
-#define CFG_ATA_ALT_OFFSET      0x0210  /* Offset for alternate registers
+#define CONFIG_SYS_ATA_ALT_OFFSET      0x0210  /* Offset for alternate registers
 					   */
 #define CONFIG_ATAPI
-#define CFG_PIO_MODE 0
+#define CONFIG_SYS_PIO_MODE 0
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-/*#define	CFG_DER	0x2002000F*/
-#define CFG_DER	0x0
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0x0
 
 /*
  * Init Memory Controller:
@@ -405,55 +405,55 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
 #if defined(CONFIG_100MHz)
-#define CFG_OR_TIMING_FLASH 0x000002f4
-#define CFG_OR_TIMING_DOC   0x000002f4
-#define CFG_MxMR_PTx 0x61000000
-#define CFG_MPTPR 0x400
+#define CONFIG_SYS_OR_TIMING_FLASH 0x000002f4
+#define CONFIG_SYS_OR_TIMING_DOC   0x000002f4
+#define CONFIG_SYS_MxMR_PTx 0x61000000
+#define CONFIG_SYS_MPTPR 0x400
 
 #elif  defined(CONFIG_80MHz)
-#define CFG_OR_TIMING_FLASH 0x00000ff4
-#define CFG_OR_TIMING_DOC   0x000001f4
-#define CFG_MxMR_PTx 0x4e000000
-#define CFG_MPTPR 0x400
+#define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4
+#define CONFIG_SYS_OR_TIMING_DOC   0x000001f4
+#define CONFIG_SYS_MxMR_PTx 0x4e000000
+#define CONFIG_SYS_MPTPR 0x400
 
 #elif defined(CONFIG_75MHz)
-#define CFG_OR_TIMING_FLASH 0x000008f4
-#define CFG_OR_TIMING_DOC   0x000002f4
-#define CFG_MxMR_PTx 0x49000000
-#define CFG_MPTPR 0x400
+#define CONFIG_SYS_OR_TIMING_FLASH 0x000008f4
+#define CONFIG_SYS_OR_TIMING_DOC   0x000002f4
+#define CONFIG_SYS_MxMR_PTx 0x49000000
+#define CONFIG_SYS_MPTPR 0x400
 
 #elif defined(CONFIG_66MHz)
-#define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 	OR_SCY_3_CLK | OR_EHTR | OR_BI)
-/*#define CFG_OR_TIMING_FLASH 0x000001f4 */
-#define CFG_OR_TIMING_DOC   0x000003f4
-#define CFG_MxMR_PTx  0x40000000
-#define CFG_MPTPR 0x400
+/*#define CONFIG_SYS_OR_TIMING_FLASH 0x000001f4 */
+#define CONFIG_SYS_OR_TIMING_DOC   0x000003f4
+#define CONFIG_SYS_MxMR_PTx  0x40000000
+#define CONFIG_SYS_MPTPR 0x400
 
 #else		/*   50 MHz */
-#define CFG_OR_TIMING_FLASH 0x00000ff4
-#define CFG_OR_TIMING_DOC   0x000001f4
-#define CFG_MxMR_PTx  0x30000000
-#define CFG_MPTPR 0x400
+#define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4
+#define CONFIG_SYS_OR_TIMING_DOC   0x000001f4
+#define CONFIG_SYS_MxMR_PTx  0x30000000
+#define CONFIG_SYS_MPTPR 0x400
 #endif	/*CONFIG_??MHz */
 
 
 #if  defined (CONFIG_BOOT_8B)   /* 512K X 8 ,29F040 , 2MB space */
-#define CFG_OR0_PRELIM	(0xffe00000 | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)
+#define CONFIG_SYS_OR0_PRELIM	(0xffe00000 | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)
 #elif  defined (CONFIG_BOOT_16B)   /* 29lv160 X 16 , 4MB space */
-#define CFG_OR0_PRELIM	(0xffc00000 | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
+#define CONFIG_SYS_OR0_PRELIM	(0xffc00000 | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
 #elif defined( CONFIG_BOOT_32B )  /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */
-#define CFG_OR0_PRELIM	(0xfc000000 | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_PRELIM	(0xfc000000 | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 #else
 #error Boot device port size missing.
 #endif
@@ -462,12 +462,12 @@
  * Disk-On-Chip configuration
  */
 
-#define CFG_DOC_SHORT_TIMEOUT
-#define CFG_MAX_DOC_DEVICE      1       /* Max number of DOC devices    */
+#define CONFIG_SYS_DOC_SHORT_TIMEOUT
+#define CONFIG_SYS_MAX_DOC_DEVICE      1       /* Max number of DOC devices    */
 
-#define CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
-#define CFG_DOC_BASE 0x80000000
+#define CONFIG_SYS_DOC_SUPPORT_2000
+#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
+#define CONFIG_SYS_DOC_BASE 0x80000000
 
 
 /*
diff --git a/include/configs/taihu.h b/include/configs/taihu.h
index bcb8732..8c48c66 100644
--- a/include/configs/taihu.h
+++ b/include/configs/taihu.h
@@ -102,8 +102,8 @@
 #define CONFIG_CMD_SPI
 
 #undef CONFIG_SPD_EEPROM		/* use SPD EEPROM for setup */
-#define CFG_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
-#define CFG_SDRAM_BANKS	        2
+#define CONFIG_SYS_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
+#define CONFIG_SYS_SDRAM_BANKS	        2
 
 /*
  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
@@ -112,38 +112,38 @@
 #define CONFIG_SDRAM_BANK1	1	/* init onboard SDRAM bank 1 */
 
 /* SDRAM timings used in datasheet */
-#define CFG_SDRAM_CL            3	/* CAS latency */
-#define CFG_SDRAM_tRP           20	/* PRECHARGE command period */
-#define CFG_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE command period */
-#define CFG_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
-#define CFG_SDRAM_tRFC		66	/* Auto refresh period */
+#define CONFIG_SYS_SDRAM_CL            3	/* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE command period */
+#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC		66	/* Auto refresh period */
 
 /*
- * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
  * The Linux BASE_BAUD define should match this configuration.
  *    baseBaud = cpuClock/(uartDivisor*16)
- * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  * set Linux BASE_BAUD to 403200.
  */
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#undef  CFG_EXT_SERIAL_CLOCK           /* external serial clock */
-#undef  CFG_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD		691200
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
+#undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		691200
 #define CONFIG_UART1_CONSOLE	1
 
 /*-----------------------------------------------------------------------
  * I2C stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 
-#define CFG_I2C_NOPROBES	{ 0x69 } /* avoid iprobe hangup (why?) */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	6 /* 24C02 requires 5ms delay */
+#define CONFIG_SYS_I2C_NOPROBES	{ 0x69 } /* avoid iprobe hangup (why?) */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	6 /* 24C02 requires 5ms delay */
 
-#define CFG_I2C_EEPROM_ADDR	0x50	/* I2C boot EEPROM (24C02W)	*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* I2C boot EEPROM (24C02W)	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
 
 #define CONFIG_SOFT_SPI
 #define SPI_SCL  spi_scl
@@ -159,7 +159,7 @@ unsigned char spi_read(void);
 /* standard dtt sensor configuration */
 #define CONFIG_DTT_DS1775	1
 #define CONFIG_DTT_SENSORS	{ 0 }
-#define CFG_I2C_DTT_ADDR	0x49
+#define CONFIG_SYS_I2C_DTT_ADDR	0x49
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -175,39 +175,39 @@ unsigned char spi_read(void);
 					/* resource configuration      */
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
-#define CFG_PCI_CLASSCODE       0x0600  /* PCI Class Code: bridge/host */
-#define CFG_PCI_PTM1LA	    0x00000000	/* point to sdram              */
-#define CFG_PCI_PTM1MS      0x80000001	/* 2GB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI     0x00000000	/* Host: use this pci address  */
-#define CFG_PCI_PTM2LA      0x00000000	/* disabled                    */
-#define CFG_PCI_PTM2MS	    0x00000000	/* disabled                    */
-#define CFG_PCI_PTM2PCI     0x04000000	/* Host: use this pci address  */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0600  /* PCI Class Code: bridge/host */
+#define CONFIG_SYS_PCI_PTM1LA	    0x00000000	/* point to sdram              */
+#define CONFIG_SYS_PCI_PTM1MS      0x80000001	/* 2GB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI     0x00000000	/* Host: use this pci address  */
+#define CONFIG_SYS_PCI_PTM2LA      0x00000000	/* disabled                    */
+#define CONFIG_SYS_PCI_PTM2MS	    0x00000000	/* disabled                    */
+#define CONFIG_SYS_PCI_PTM2PCI     0x04000000	/* Host: use this pci address  */
 #define CONFIG_EEPRO100		1
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  */
-#define CFG_FLASH_BASE		0xFFE00000
+#define CONFIG_SYS_FLASH_BASE		0xFFE00000
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_ADDR0         0x555
-#define CFG_FLASH_ADDR1         0x2aa
-#define CFG_FLASH_WORD_SIZE     unsigned short
+#define CONFIG_SYS_FLASH_ADDR0         0x555
+#define CONFIG_SYS_FLASH_ADDR1         0x2aa
+#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned short
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -218,19 +218,19 @@ unsigned char spi_read(void);
 /*-----------------------------------------------------------------------
  * NVRAM organization
  */
-#define CFG_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address */
-#define CFG_NVRAM_SIZE		0x1ff8		/* NVRAM size */
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address */
+#define CONFIG_SYS_NVRAM_SIZE		0x1ff8		/* NVRAM size */
 
 #ifdef CONFIG_ENV_IS_IN_NVRAM
 #define CONFIG_ENV_SIZE		0x0ff8		/* Size of Environment vars */
 #define CONFIG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env*/
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env*/
 #endif
 
 /*-----------------------------------------------------------------------
  * PPC405 GPIO Configuration
  */
-#define CFG_4xx_GPIO_TABLE { /*				GPIO	Alternate1		*/	\
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*				GPIO	Alternate1		*/	\
 {												\
 /* GPIO Core 0 */										\
 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast    SPI CS	*/	\
@@ -274,48 +274,48 @@ unsigned char spi_read(void);
  * BR0/1 and OR0/1 (FLASH)
  */
 
-#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
 #define FLASH_BASE1_PRELIM  0xFC000000	/* FLASH bank #1 */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory (OCM) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
+#define CONFIG_SYS_TEMP_STACK_OCM        1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
 
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  */
 
 /* Memory Bank 0 (Flash/SRAM) initialization */
-#define CFG_EBC_PB0AP           0x03815600
-#define CFG_EBC_PB0CR           0xFFE3A000  /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP           0x03815600
+#define CONFIG_SYS_EBC_PB0CR           0xFFE3A000  /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 1 (NVRAM/RTC) initialization */
-#define CFG_EBC_PB1AP           0x05815600
-#define CFG_EBC_PB1CR           0xFC0BA000  /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB1AP           0x05815600
+#define CONFIG_SYS_EBC_PB1CR           0xFC0BA000  /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */
 
 /* Memory Bank 2 (USB device) initialization */
-#define CFG_EBC_PB2AP           0x03016600
-#define CFG_EBC_PB2CR           0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB2AP           0x03016600
+#define CONFIG_SYS_EBC_PB2CR           0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */
 
 /* Memory Bank 3 (LCM and D-flip-flop) initialization */
-#define CFG_EBC_PB3AP           0x158FF600
-#define CFG_EBC_PB3CR           0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB3AP           0x158FF600
+#define CONFIG_SYS_EBC_PB3CR           0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */
 
 /* Memory Bank 4 (not install) initialization */
-#define CFG_EBC_PB4AP           0x158FF600
-#define CFG_EBC_PB4CR           0x5021A000
+#define CONFIG_SYS_EBC_PB4AP           0x158FF600
+#define CONFIG_SYS_EBC_PB4CR           0x5021A000
 
 #define CPLD_REG0_ADDR	0x50100000
 #define CPLD_REG1_ADDR	0x50100001
diff --git a/include/configs/taishan.h b/include/configs/taishan.h
index 08ec14c..6423fd7 100644
--- a/include/configs/taishan.h
+++ b/include/configs/taishan.h
@@ -48,37 +48,37 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE		0xfc000000	/* start of FLASH	*/
-#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
-#define CFG_PERIPHERAL_BASE	0xe0000000	/* internal peripherals	*/
-#define CFG_ISRAM_BASE		0xc0000000	/* internal SRAM	*/
-#define CFG_PCI_BASE		0xd0000000	/* internal PCI regs	*/
+#define CONFIG_SYS_FLASH_BASE		0xfc000000	/* start of FLASH	*/
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CONFIG_SYS_PERIPHERAL_BASE	0xe0000000	/* internal peripherals	*/
+#define CONFIG_SYS_ISRAM_BASE		0xc0000000	/* internal SRAM	*/
+#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs	*/
 
-#define CFG_EBC0_FLASH_BASE	CFG_FLASH_BASE
-#define CFG_EBC1_FPGA_BASE	(CFG_PERIPHERAL_BASE + 0x01000000)
-#define CFG_EBC2_LCM_BASE	(CFG_PERIPHERAL_BASE + 0x02000000)
-#define CFG_EBC3_CONN_BASE	(CFG_PERIPHERAL_BASE + 0x08000000)
+#define CONFIG_SYS_EBC0_FLASH_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_EBC1_FPGA_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x01000000)
+#define CONFIG_SYS_EBC2_LCM_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x02000000)
+#define CONFIG_SYS_EBC3_CONN_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
 
-#define CFG_GPIO_BASE		(CFG_PERIPHERAL_BASE + 0x00000700)
+#define CONFIG_SYS_GPIO_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
-#define CFG_TEMP_STACK_OCM	1
-#define CFG_OCM_DATA_ADDR	CFG_ISRAM_BASE
-#define CFG_INIT_RAM_ADDR	CFG_ISRAM_BASE  /* Initial RAM address	*/
-#define CFG_INIT_RAM_END	0x2000		/* End of used area in RAM*/
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data*/
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_END	0x2000		/* End of used area in RAM*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data*/
 
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_POST_WORD_ADDR
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
 #define CONFIG_UART1_CONSOLE	1	/* use of UART1 as console	*/
-#define CFG_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
 
 /*-----------------------------------------------------------------------
  * Environment
@@ -88,21 +88,21 @@
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
 
-#define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
-#define CFG_MAX_FLASH_BANKS     1		    /* number of banks	    */
-#define CFG_MAX_FLASH_SECT	1024		    /* sectors per device   */
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS     1		    /* number of banks	    */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		    /* sectors per device   */
 
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define CONFIG_ENV_SECT_SIZE	0x40000 /* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -128,29 +128,28 @@
  *----------------------------------------------------------------------*/
 #undef CONFIG_SPD_EEPROM		/* Don't use SPD EEPROM for setup	*/
 #define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0	*/
-#define	CFG_SDRAM0_TR0		0xC10A401A
+#define	CONFIG_SYS_SDRAM0_TR0		0xC10A401A
 #undef CONFIG_SDRAM_ECC			/* enable ECC support			*/
 
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 
-#undef CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	0x50
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#undef CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 
-#define CFG_BOOTSTRAP_IIC_ADDR	0x50
+#define CONFIG_SYS_BOOTSTRAP_IIC_ADDR	0x50
 
 /* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
 #define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
 #define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
-#define CFG_DTT_MAX_TEMP	70
-#define CFG_DTT_LOW_TEMP	-30
-#define CFG_DTT_HYSTERESIS	3
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
 
 /*
  * Default environment variables
@@ -197,12 +196,12 @@
 #define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
 #define CONFIG_EEPRO100       1		/* include PCI EEPRO100		*/
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
-#define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
+#define CONFIG_SYS_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT		/* let board init pci target    */
+#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */
 
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h
index bfb32fb..9285c9d 100644
--- a/include/configs/tb0229.h
+++ b/include/configs/tb0229.h
@@ -38,7 +38,7 @@
 
 #define CONFIG_BAUDRATE		115200
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_TIMESTAMP		/* Print image info with timestamp */
 
@@ -112,46 +112,46 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory	     */
-#define CFG_PROMPT		"# "		/* Monitor Command Prompt    */
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size   */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args*/
+#define CONFIG_SYS_LONGHELP				/* undef to save memory	     */
+#define CONFIG_SYS_PROMPT		"# "		/* Monitor Command Prompt    */
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size   */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args*/
 
-#define CFG_MALLOC_LEN		128*1024
+#define CONFIG_SYS_MALLOC_LEN		128*1024
 
-#define CFG_BOOTPARAMS_LEN	128*1024
+#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024
 
-#define CFG_MIPS_TIMER_FREQ	(CPU_TCLOCK_RATE/4)
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CPU_TCLOCK_RATE/4)
 
-#define CFG_HZ			1000
+#define CONFIG_SYS_HZ			1000
 
-#define CFG_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
 
-#define CFG_LOAD_ADDR		0x80400000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x80400000	/* default load address */
 
-#define CFG_MEMTEST_START	0x80000000
-#define CFG_MEMTEST_END		0x80800000
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x80800000
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
 
 #define PHYS_FLASH_1		0xbfc00000 /* Flash Bank #1 */
 
 /* The following #defines are needed to get flash environment right */
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(192 << 10)
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)
 
-#define CFG_INIT_SP_OFFSET	0x400000
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(20 * CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(20 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 
@@ -159,25 +159,25 @@
 #define CONFIG_ENV_ADDR		0xBFC40000
 #define CONFIG_ENV_SIZE		0x20000
 
-#define CFG_DIRECT_FLASH_TFTP
+#define CONFIG_SYS_DIRECT_FLASH_TFTP
 
 #define CONFIG_NR_DRAM_BANKS	1
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		16384
-#define CFG_ICACHE_SIZE		16384
-#define CFG_CACHELINE_SIZE	16
+#define CONFIG_SYS_DCACHE_SIZE		16384
+#define CONFIG_SYS_ICACHE_SIZE		16384
+#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /*-----------------------------------------------------------------------
  * Serial Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	 1
-#define CFG_NS16550_CLK		 18432000
-#define CFG_NS16550_COM1	 0xaf000800
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	 1
+#define CONFIG_SYS_NS16550_CLK		 18432000
+#define CONFIG_SYS_NS16550_COM1	 0xaf000800
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -186,7 +186,7 @@
 #define CONFIG_PCI_PNP
 #define CONFIG_NET_MULTI
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
+#define CONFIG_SYS_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
 
 #define CONFIG_RTL8139
 
diff --git a/include/configs/trab.h b/include/configs/trab.h
index d6d463a..0a7a73d 100644
--- a/include/configs/trab.h
+++ b/include/configs/trab.h
@@ -44,7 +44,6 @@
 #define CONFIG_S3C2400		1	/* in a SAMSUNG S3C2400 SoC	*/
 #define CONFIG_TRAB		1	/* on a TRAB Board		*/
 #undef CONFIG_TRAB_50MHZ		/* run the CPU at 50 MHz	*/
-#define LITTLEENDIAN		1	/* used by usb_ohci.c		*/
 
 /* automatic software updates (see board/trab/auto_update.c) */
 #define CONFIG_AUTO_UPDATE	1
@@ -58,7 +57,7 @@
 #define CONFIG_SETUP_MEMORY_TAGS 1
 #define CONFIG_INITRD_TAG	 1
 
-#define CFG_DEVICE_NULLDEV	 1	/* enble null device		*/
+#define CONFIG_SYS_DEVICE_NULLDEV	 1	/* enble null device		*/
 #define CONFIG_SILENT_CONSOLE	 1	/* enable silent startup	*/
 
 #define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
@@ -69,33 +68,33 @@
  * address 0x54 with 8bit addressing
  ***********************************************************/
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
-#define CFG_I2C_SPEED		100000	/* I2C speed */
-#define CFG_I2C_SLAVE		0x7F	/* I2C slave addr */
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed */
+#define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave addr */
 
-#define CFG_I2C_EEPROM_ADDR	0x54	/* EEPROM address */
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* 1 address byte */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x54	/* EEPROM address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* 1 address byte */
 
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
-#define CFG_EEPROM_PAGE_WRITE_BITS 3	/* 8 bytes page write mode on 24C04 */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3	/* 8 bytes page write mode on 24C04 */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 
 /* USB stuff */
 #define CONFIG_USB_OHCI_NEW	1
 #define CONFIG_USB_STORAGE	1
 #define CONFIG_DOS_PARTITION	1
 
-#undef CFG_USB_OHCI_BOARD_INIT
-#define CFG_USB_OHCI_CPU_INIT	1
+#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
 
-#define CFG_USB_OHCI_REGS_BASE	0x14200000
-#define CFG_USB_OHCI_SLOT_NAME	"s3c2400"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS	15
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	0x14200000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"s3c2400"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
 
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -179,7 +178,7 @@
 
 
 /* moved up */
-#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
 
 #define CONFIG_BOOTDELAY	5
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow to break in always */
@@ -192,7 +191,7 @@
 #define CONFIG_BOOTCOMMAND	"burn_in"
 
 #ifndef CONFIG_FLASH_8MB	/* current config: 16 MB flash */
-#ifdef CFG_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
 #define	CONFIG_EXTRA_ENV_SETTINGS	\
 	"nfs_args=setenv bootargs root=/dev/nfs rw " \
 		"nfsroot=$serverip:$rootpath\0" \
@@ -214,7 +213,7 @@
 	"mdm_init1=ATZ\0" \
 	"mdm_init2=ATS0=1\0" \
 	"mdm_flow_control=rts/cts\0"
-#else /* !CFG_HUSH_PARSER */
+#else /* !CONFIG_SYS_HUSH_PARSER */
 #define	CONFIG_EXTRA_ENV_SETTINGS	\
 	"nfs_args=setenv bootargs root=/dev/nfs rw " \
 		"nfsroot=${serverip}:${rootpath}\0" \
@@ -236,9 +235,9 @@
 	"mdm_init1=ATZ\0" \
 	"mdm_init2=ATS0=1\0" \
 	"mdm_flow_control=rts/cts\0"
-#endif	/* CFG_HUSH_PARSER */
+#endif	/* CONFIG_SYS_HUSH_PARSER */
 #else	/* CONFIG_FLASH_8MB	 => 8 MB flash */
-#ifdef CFG_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
 #define	CONFIG_EXTRA_ENV_SETTINGS	\
 	"nfs_args=setenv bootargs root=/dev/nfs rw " \
 		"nfsroot=$serverip:$rootpath\0" \
@@ -261,7 +260,7 @@
 	"mdm_init1=ATZ\0" \
 	"mdm_init2=ATS0=1\0" \
 	"mdm_flow_control=rts/cts\0"
-#else /* !CFG_HUSH_PARSER */
+#else /* !CONFIG_SYS_HUSH_PARSER */
 #define	CONFIG_EXTRA_ENV_SETTINGS	\
 	"nfs_args=setenv bootargs root=/dev/nfs rw " \
 		"nfsroot=${serverip}:${rootpath}\0" \
@@ -284,7 +283,7 @@
 	"mdm_init1=ATZ\0" \
 	"mdm_init2=ATS0=1\0" \
 	"mdm_flow_control=rts/cts\0"
-#endif /* CFG_HUSH_PARSER */
+#endif /* CONFIG_SYS_HUSH_PARSER */
 #endif	/* CONFIG_FLASH_8MB */
 
 #if 1	/* feel free to disable for development */
@@ -303,38 +302,38 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"TRAB # "	/* Monitor Command Prompt	*/
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"TRAB # "	/* Monitor Command Prompt	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0C000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0D000000	/* 16 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0C000000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0D000000	/* 16 MB in DRAM	*/
 
-#undef CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0x0CF00000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x0CF00000	/* default load address	*/
 
 #ifdef CONFIG_TRAB_50MHZ
 /* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
 /* it to wrap 100 times (total 1562500) to get 1 sec. */
 /* this should _really_ be calculated !! */
-#define	CFG_HZ			1562500
+#define	CONFIG_SYS_HZ			1562500
 #else
 /* the PWM TImer 4 uses a counter of 10390 for 10 ms, so we need */
 /* it to wrap 100 times (total 1039000) to get 1 sec. */
 /* this should _really_ be calculated !! */
-#define	CFG_HZ			1039000
+#define	CONFIG_SYS_HZ			1039000
 #endif
 
 /* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_MISC_INIT_R		/* have misc_init_r() function	*/
 
@@ -369,11 +368,11 @@
 #define PHYS_SDRAM_1_SIZE	0x01000000	/* 16 MB */
 #endif
 
-#define CFG_FLASH_BASE		0x00000000	/* Flash Bank #1 */
+#define CONFIG_SYS_FLASH_BASE		0x00000000	/* Flash Bank #1 */
 
 /* The following #defines are needed to get flash environment right */
-#define	CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MONITOR_LEN		(256 << 10)
+#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)
 
 /* Dynamic MTD partition support */
 #define CONFIG_JFFS2_CMDLINE
@@ -392,26 +391,26 @@
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
 #ifndef CONFIG_FLASH_8MB
-#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
 #else
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
 #endif
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(15*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(15*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 
 /* Address and size of Primary Environment Sector	*/
 #ifndef CONFIG_FLASH_8MB
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x60000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x60000)
 #define CONFIG_ENV_SIZE		0x4000
 #define CONFIG_ENV_SECT_SIZE	0x20000
 #else
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x4000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
 #define CONFIG_ENV_SIZE		0x4000
 #define CONFIG_ENV_SECT_SIZE	0x4000
 #endif
@@ -420,9 +419,9 @@
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 /* Initial value of the on-board touch screen brightness */
-#define CFG_BRIGHTNESS 0x20
+#define CONFIG_SYS_BRIGHTNESS 0x20
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
index b24979b..70e5ce9 100644
--- a/include/configs/trizepsiv.h
+++ b/include/configs/trizepsiv.h
@@ -42,8 +42,6 @@
  */
 #define CONFIG_PXA27X		1	/* This is an PXA27x CPU    */
 
-#define LITTLEENDIAN		1	/* used by usb_ohci.c		*/
-
 #define CONFIG_MMC		1
 #define BOARD_LATE_INIT		1
 
@@ -54,8 +52,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -81,7 +79,6 @@
  */
 #include <config_cmd_default.h>
 
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_IMLS
 #define CONFIG_CMD_PING
@@ -148,35 +145,39 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_HUSH_PARSER		1
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
-#define CFG_LONGHELP				/* undef to save memory		*/
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT		"$ "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
 #else
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 #endif
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_DEVICE_NULLDEV	1
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1
 
-#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR		0xa1000000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0xa1000000	/* default load address */
 
-#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x207		/* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CPUSPEED		0x207		/* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define CFG_MMC_BASE		0xF0000000
+#ifdef CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_SYS_MMC_BASE		0xF0000000
+#endif
 
 /*
  * Stack sizes
@@ -204,76 +205,76 @@
 
 #define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
 
-#define CFG_DRAM_BASE		0xa0000000
-#define CFG_DRAM_SIZE		0x04000000
+#define CONFIG_SYS_DRAM_BASE		0xa0000000
+#define CONFIG_SYS_DRAM_SIZE		0x04000000
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*
  * GPIO settings
  */
-#define CFG_GPSR0_VAL		0x00018000
-#define CFG_GPSR1_VAL		0x00000000
-#define CFG_GPSR2_VAL		0x400dc000
-#define CFG_GPSR3_VAL		0x00000000
-#define CFG_GPCR0_VAL		0x00000000
-#define CFG_GPCR1_VAL		0x00000000
-#define CFG_GPCR2_VAL		0x00000000
-#define CFG_GPCR3_VAL		0x00000000
-#define CFG_GPDR0_VAL		0x00018000
-#define CFG_GPDR1_VAL		0x00028801
-#define CFG_GPDR2_VAL		0x520dc000
-#define CFG_GPDR3_VAL		0x0001E000
-#define CFG_GAFR0_L_VAL		0x801c0000
-#define CFG_GAFR0_U_VAL		0x00000013
-#define CFG_GAFR1_L_VAL		0x6990100A
-#define CFG_GAFR1_U_VAL		0x00000008
-#define CFG_GAFR2_L_VAL		0xA0000000
-#define CFG_GAFR2_U_VAL		0x010900F2
-#define CFG_GAFR3_L_VAL		0x54000003
-#define CFG_GAFR3_U_VAL		0x00002401
-#define CFG_GRER0_VAL		0x00000000
-#define CFG_GRER1_VAL		0x00000000
-#define CFG_GRER2_VAL		0x00000000
-#define CFG_GRER3_VAL		0x00000000
-#define CFG_GFER0_VAL		0x00000000
-#define CFG_GFER1_VAL		0x00000000
-#define CFG_GFER2_VAL		0x00000000
-#define CFG_GFER3_VAL		0x00000020
-
-
-#define CFG_PSSR_VAL		0x20	/* CHECK */
+#define CONFIG_SYS_GPSR0_VAL		0x00018000
+#define CONFIG_SYS_GPSR1_VAL		0x00000000
+#define CONFIG_SYS_GPSR2_VAL		0x400dc000
+#define CONFIG_SYS_GPSR3_VAL		0x00000000
+#define CONFIG_SYS_GPCR0_VAL		0x00000000
+#define CONFIG_SYS_GPCR1_VAL		0x00000000
+#define CONFIG_SYS_GPCR2_VAL		0x00000000
+#define CONFIG_SYS_GPCR3_VAL		0x00000000
+#define CONFIG_SYS_GPDR0_VAL		0x00018000
+#define CONFIG_SYS_GPDR1_VAL		0x00028801
+#define CONFIG_SYS_GPDR2_VAL		0x520dc000
+#define CONFIG_SYS_GPDR3_VAL		0x0001E000
+#define CONFIG_SYS_GAFR0_L_VAL		0x801c0000
+#define CONFIG_SYS_GAFR0_U_VAL		0x00000013
+#define CONFIG_SYS_GAFR1_L_VAL		0x6990100A
+#define CONFIG_SYS_GAFR1_U_VAL		0x00000008
+#define CONFIG_SYS_GAFR2_L_VAL		0xA0000000
+#define CONFIG_SYS_GAFR2_U_VAL		0x010900F2
+#define CONFIG_SYS_GAFR3_L_VAL		0x54000003
+#define CONFIG_SYS_GAFR3_U_VAL		0x00002401
+#define CONFIG_SYS_GRER0_VAL		0x00000000
+#define CONFIG_SYS_GRER1_VAL		0x00000000
+#define CONFIG_SYS_GRER2_VAL		0x00000000
+#define CONFIG_SYS_GRER3_VAL		0x00000000
+#define CONFIG_SYS_GFER0_VAL		0x00000000
+#define CONFIG_SYS_GFER1_VAL		0x00000000
+#define CONFIG_SYS_GFER2_VAL		0x00000000
+#define CONFIG_SYS_GFER3_VAL		0x00000020
+
+
+#define CONFIG_SYS_PSSR_VAL		0x20	/* CHECK */
 
 /*
  * Clock settings
  */
-#define CFG_CKEN		0x01FFFFFF	/* CHECK */
-#define CFG_CCCR		0x02000290 /*   520Mhz */
+#define CONFIG_SYS_CKEN		0x01FFFFFF	/* CHECK */
+#define CONFIG_SYS_CCCR		0x02000290 /*   520Mhz */
 
 /*
  * Memory settings
  */
 
-#define CFG_MSC0_VAL		0x4df84df0
-#define CFG_MSC1_VAL		0x7ff87ff4
-#define CFG_MSC2_VAL		0xa26936d4
-#define CFG_MDCNFG_VAL		0x880009C9
-#define CFG_MDREFR_VAL		0x20ca201e
-#define CFG_MDMRS_VAL		0x00220022
+#define CONFIG_SYS_MSC0_VAL		0x4df84df0
+#define CONFIG_SYS_MSC1_VAL		0x7ff87ff4
+#define CONFIG_SYS_MSC2_VAL		0xa26936d4
+#define CONFIG_SYS_MDCNFG_VAL		0x880009C9
+#define CONFIG_SYS_MDREFR_VAL		0x20ca201e
+#define CONFIG_SYS_MDMRS_VAL		0x00220022
 
-#define CFG_FLYCNFG_VAL		0x00000000
-#define CFG_SXCNFG_VAL		0x40044004
+#define CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define CONFIG_SYS_SXCNFG_VAL		0x40044004
 
 /*
  * PCMCIA and CF Interfaces
  */
-#define CFG_MECR_VAL		0x00000001
-#define CFG_MCMEM0_VAL		0x00004204
-#define CFG_MCMEM1_VAL		0x00010204
-#define CFG_MCATT0_VAL		0x00010504
-#define CFG_MCATT1_VAL		0x00010504
-#define CFG_MCIO0_VAL		0x00008407
-#define CFG_MCIO1_VAL		0x0000c108
+#define CONFIG_SYS_MECR_VAL		0x00000001
+#define CONFIG_SYS_MCMEM0_VAL		0x00004204
+#define CONFIG_SYS_MCMEM1_VAL		0x00010204
+#define CONFIG_SYS_MCATT0_VAL		0x00010504
+#define CONFIG_SYS_MCATT1_VAL		0x00010504
+#define CONFIG_SYS_MCIO0_VAL		0x00008407
+#define CONFIG_SYS_MCIO1_VAL		0x0000c108
 
 #define CONFIG_DRIVER_DM9000		1
 #define CONFIG_DM9000_BASE	0x08000000
@@ -281,36 +282,36 @@
 #define DM9000_DATA			(CONFIG_DM9000_BASE+0x8004)
 
 #define CONFIG_USB_OHCI_NEW	1
-#define CFG_USB_OHCI_BOARD_INIT	1
-#define CFG_USB_OHCI_MAX_ROOT_PORTS	3
-#define CFG_USB_OHCI_REGS_BASE	0x4C000000
-#define CFG_USB_OHCI_SLOT_NAME	"trizepsiv"
+#define CONFIG_SYS_USB_OHCI_BOARD_INIT	1
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	0x4C000000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"trizepsiv"
 #define CONFIG_USB_STORAGE	1
-#define CFG_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
 
 /*
  * FLASH and environment organization
  */
 
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER	1
 
-#define CFG_MONITOR_BASE	0
-#define CFG_MONITOR_LEN		0x40000
+#define CONFIG_SYS_MONITOR_BASE	0
+#define CONFIG_SYS_MONITOR_LEN		0x40000
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	4 + 255  /* max number of sectors on one chip   */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	4 + 255  /* max number of sectors on one chip   */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 /* write flash less slowly */
-#define CFG_FLASH_USE_BUFFER_WRITE 1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
 
 /* Flash environment locations */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector	*/
+#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector	*/
 #define CONFIG_ENV_SIZE		0x40000	/* Total Size of Environment		*/
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* Total Size of Environment Sector	*/
 
diff --git a/include/configs/uc100.h b/include/configs/uc100.h
index 22ebf07..23f4c82 100644
--- a/include/configs/uc100.h
+++ b/include/configs/uc100.h
@@ -92,7 +92,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -112,17 +112,17 @@
 #define CONFIG_DOS_PARTITION
 
 #undef CONFIG_RTC_MPC8xx
-#define CFG_I2C_RTC_ADDR	0x51	/* PCF8563 RTC			*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* PCF8563 RTC			*/
 #define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
 
 /*
  * Power On Self Test support
  */
-#define CONFIG_POST	      ( CFG_POST_CACHE		| \
-				CFG_POST_MEMORY		| \
-				CFG_POST_CPU		| \
-				CFG_POST_UART		| \
-				CFG_POST_SPR )
+#define CONFIG_POST	      ( CONFIG_SYS_POST_CACHE		| \
+				CONFIG_SYS_POST_MEMORY		| \
+				CONFIG_SYS_POST_CPU		| \
+				CONFIG_SYS_POST_UART		| \
+				CONFIG_SYS_POST_SPR )
 #undef  CONFIG_POST
 
 
@@ -154,33 +154,33 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #if 0
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
 #endif
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
 
@@ -192,57 +192,57 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR		0xF0000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	(CFG_FLASH_BASE+0x00700000) /* resetvec fff00100*/
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE+0x00700000) /* resetvec fff00100*/
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*-----------------------------------------------------------------------
  * Address accessed to reset the board - must not be mapped/assigned
  */
-#define CFG_RESET_ADDRESS       0x90000000
+#define CONFIG_SYS_RESET_ADDRESS       0x90000000
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_FLASH_CFI				/* The flash is CFI compatible  */
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible  */
 #define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
-#define CFG_FLASH_CFI_AMD_RESET	1		/* AMD RESET for STM 29W320DB!  */
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1		/* AMD RESET for STM 29W320DB!  */
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE+CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
 #define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
@@ -253,9 +253,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -265,10 +265,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -276,27 +276,27 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_FRC | SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_FRC | SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -304,7 +304,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit
  */
-#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
 				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
@@ -314,21 +314,21 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	0x00000000
-#define CFG_SCCR        (SCCR_EBDF11)
+#define CONFIG_SYS_SCCR        (SCCR_EBDF11)
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -341,28 +341,28 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -377,28 +377,28 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(0x00000d24)
+#define CONFIG_SYS_OR_TIMING_FLASH	(0x00000d24)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_BR1_PRELIM  0x00000081  /* Chip select for SDRAM (32 Bit, UPMA) */
-#define CFG_OR1_PRELIM  0xfc000a00
-#define CFG_BR2_PRELIM  0x80000001  /* Chip select for SRAM (32 Bit, GPCM) */
-#define CFG_OR2_PRELIM  0xfff00d24
-#define CFG_BR3_PRELIM  0x80600401  /* Chip select for Display (8 Bit, GPCM) */
-#define CFG_OR3_PRELIM  0xffff8f44
-#define CFG_BR4_PRELIM  0xc05108c1  /* Chip select for Interbus MPM (16 Bit, UPMB) */
-#define CFG_OR4_PRELIM  0xffff0300
-#define CFG_BR5_PRELIM  0xc0500401  /* Chip select for Interbus Status (8 Bit, GPCM) */
-#define CFG_OR5_PRELIM  0xffff8db0
+#define CONFIG_SYS_BR1_PRELIM  0x00000081  /* Chip select for SDRAM (32 Bit, UPMA) */
+#define CONFIG_SYS_OR1_PRELIM  0xfc000a00
+#define CONFIG_SYS_BR2_PRELIM  0x80000001  /* Chip select for SRAM (32 Bit, GPCM) */
+#define CONFIG_SYS_OR2_PRELIM  0xfff00d24
+#define CONFIG_SYS_BR3_PRELIM  0x80600401  /* Chip select for Display (8 Bit, GPCM) */
+#define CONFIG_SYS_OR3_PRELIM  0xffff8f44
+#define CONFIG_SYS_BR4_PRELIM  0xc05108c1  /* Chip select for Interbus MPM (16 Bit, UPMB) */
+#define CONFIG_SYS_OR4_PRELIM  0xffff0300
+#define CONFIG_SYS_BR5_PRELIM  0xc0500401  /* Chip select for Interbus Status (8 Bit, GPCM) */
+#define CONFIG_SYS_OR5_PRELIM  0xffff8db0
 
 /*
  * Memory Periodic Timer Prescaler
@@ -428,39 +428,39 @@
  * 100 Mhz => 100.000.000 / Divider = 195
  */
 
-#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
-#define CFG_MAMR_PTA	98
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
-#define	CFG_MAMR_VAL	0x30904114	/* for SDRAM */
-#define	CFG_MBMR_VAL	0xff001111	/* for Interbus-MPM */
+#define	CONFIG_SYS_MAMR_VAL	0x30904114	/* for SDRAM */
+#define	CONFIG_SYS_MBMR_VAL	0xff001111	/* for Interbus-MPM */
 
 /*-----------------------------------------------------------------------
  * I2C stuff
@@ -470,8 +470,8 @@
 #undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/
 
-#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
-#define CFG_I2C_SLAVE		0xFE
+#define CONFIG_SYS_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CONFIG_SYS_I2C_SLAVE		0xFE
 
 #ifdef CONFIG_SOFT_I2C
 /*
@@ -494,10 +494,10 @@
 /*-----------------------------------------------------------------------
  * I2C EEPROM (24C164)
  */
-#define CFG_I2C_EEPROM_ADDR	0x58	/* EEPROM AT24C164		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec	*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x58	/* EEPROM AT24C164		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
 
 /*
  * Internal Definitions
@@ -511,6 +511,6 @@
 #define FEC_ENET
 #define CONFIG_MII
 #define CONFIG_MII_INIT		1
-#define CFG_DISCOVER_PHY	1
+#define CONFIG_SYS_DISCOVER_PHY	1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/uc101.h b/include/configs/uc101.h
index c709033..87cb4e5 100644
--- a/include/configs/uc101.h
+++ b/include/configs/uc101.h
@@ -33,7 +33,7 @@
 #define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
 #define CONFIG_UC101		1	/* UC101 board			*/
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM		0x02	/* Software reboot			*/
@@ -47,7 +47,7 @@
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /* Partitions */
 #define CONFIG_DOS_PARTITION
@@ -84,7 +84,7 @@
 #define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
 
 #if (TEXT_BASE == 0xFFF00000) /* Boot low */
-#   define CFG_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT		1
 #endif
 
 /*
@@ -120,58 +120,56 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
 
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration
  */
-#define CFG_I2C_EEPROM_ADDR		0x58
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
-/* for LM81 */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 
 /*
  * RTC configuration
  */
 #define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR		0x51
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
 
 /* I2C SYSMON (LM75) */
 #define CONFIG_DTT_LM81			1	/* ON Semi's LM75		*/
 #define CONFIG_DTT_SENSORS		{0}	/* Sensor addresses		*/
-#define CFG_DTT_MAX_TEMP		70
-#define CFG_DTT_LOW_TEMP		-30
-#define CFG_DTT_HYSTERESIS		3
+#define CONFIG_SYS_DTT_MAX_TEMP		70
+#define CONFIG_SYS_DTT_LOW_TEMP		-30
+#define CONFIG_SYS_DTT_HYSTERESIS		3
 
 /*
  * Flash configuration
  */
-#define CFG_FLASH_BASE		0xFF800000
+#define CONFIG_SYS_FLASH_BASE		0xFF800000
 
-#define CFG_FLASH_SIZE		0x00800000 /* 8 MByte */
-#define CFG_MAX_FLASH_SECT	140	/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_SIZE		0x00800000 /* 8 MByte */
+#define CONFIG_SYS_MAX_FLASH_SECT	140	/* max num of sects on one chip */
 
 #define CONFIG_ENV_ADDR		(TEXT_BASE+0x40000) /* second sector */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
 					   (= chip selects) */
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
 
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_CFI_AMD_RESET
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
 
 /*
  * Environment settings
@@ -185,14 +183,14 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SRAM_BASE		0x80100000	/* CS 1 */
-#define CFG_DISPLAY_BASE	0x80600000	/* CS 3 */
-#define	CFG_IB_MASTER		0xc0510000	/* CS 6 */
-#define CFG_IB_EPLD		0xc0500000	/* CS 7 */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SRAM_BASE		0x80100000	/* CS 1 */
+#define CONFIG_SYS_DISPLAY_BASE	0x80600000	/* CS 3 */
+#define	CONFIG_SYS_IB_MASTER		0xc0510000	/* CS 6 */
+#define CONFIG_SYS_IB_EPLD		0xc0500000	/* CS 7 */
 
 /* Settings for XLB = 132 MHz */
 #define SDRAM_DDR	 1
@@ -204,44 +202,45 @@
 #define SDRAM_TAPDELAY  0x10000000
 
 /* SRAM */
-#define SRAM_BASE		CFG_SRAM_BASE	/* SRAM base address	*/
+#define SRAM_BASE		CONFIG_SYS_SRAM_BASE	/* SRAM base address	*/
 #define SRAM_LEN		0x1fffff
 #define SRAM_END		(SRAM_BASE + SRAM_LEN)
 
 /* Use ON-Chip SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
 #else
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
 #endif
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
 #define CONFIG_PHY_ADDR		0x00
 #define CONFIG_MII		1
 
 /*
  * GPIO configuration
  */
-#define CFG_GPS_PORT_CONFIG	0x4d558044
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x4d558044
 
 /*use  Hardware WDT */
 #define CONFIG_HW_WATCHDOG
@@ -249,30 +248,30 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
 /* Enable an alternate, more extensive memory test */
-#define CFG_ALT_MEMTEST
+#define CONFIG_SYS_ALT_MEMTEST
 
-#define CFG_MEMTEST_START	0x00300000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 3 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00300000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 3 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x300000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x300000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /*
@@ -284,41 +283,41 @@
  * Various low-level settings
  */
 #if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 #else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
 #endif
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x00045D00
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00045D00
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
 /* 8Mbit SRAM @0x80100000 */
-#define CFG_CS1_START		CFG_SRAM_BASE
-#define CFG_CS1_SIZE		0x00200000
-#define CFG_CS1_CFG		0x21D00
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_SRAM_BASE
+#define CONFIG_SYS_CS1_SIZE		0x00200000
+#define CONFIG_SYS_CS1_CFG		0x21D00
 
 /* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
-#define CFG_CS3_START		CFG_DISPLAY_BASE
-#define CFG_CS3_SIZE		0x00000100
-#define CFG_CS3_CFG		0x00081802
+#define CONFIG_SYS_CS3_START		CONFIG_SYS_DISPLAY_BASE
+#define CONFIG_SYS_CS3_SIZE		0x00000100
+#define CONFIG_SYS_CS3_CFG		0x00081802
 
 /* Interbus Master 16 Bit */
-#define CFG_CS6_START		CFG_IB_MASTER
-#define CFG_CS6_SIZE		0x00010000
-#define CFG_CS6_CFG		0x00FF3500
+#define CONFIG_SYS_CS6_START		CONFIG_SYS_IB_MASTER
+#define CONFIG_SYS_CS6_SIZE		0x00010000
+#define CONFIG_SYS_CS6_CFG		0x00FF3500
 
 /* Interbus EPLD 8 Bit */
-#define CFG_CS7_START		CFG_IB_EPLD
-#define CFG_CS7_SIZE		0x00010000
-#define CFG_CS7_CFG		0x00081800
+#define CONFIG_SYS_CS7_START		CONFIG_SYS_IB_EPLD
+#define CONFIG_SYS_CS7_SIZE		0x00010000
+#define CONFIG_SYS_CS7_CFG		0x00081800
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff Supports IDE harddisk
@@ -330,33 +329,33 @@
 #undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
 
 #define CONFIG_IDE_PREINIT	1
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(0x0060)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005C)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
 
 /* Interval between registers                                                */
-#define CFG_ATA_STRIDE          4
+#define CONFIG_SYS_ATA_STRIDE          4
 
 #define CONFIG_ATAPI            1
 
 /*---------------------------------------------------------------------*/
 /* Display addresses						       */
 /*---------------------------------------------------------------------*/
-#define CFG_DISP_CHR_RAM	(CFG_DISPLAY_BASE + 0x38)
-#define CFG_DISP_CWORD		(CFG_DISPLAY_BASE + 0x30)
+#define CONFIG_SYS_DISP_CHR_RAM	(CONFIG_SYS_DISPLAY_BASE + 0x38)
+#define CONFIG_SYS_DISP_CWORD		(CONFIG_SYS_DISPLAY_BASE + 0x30)
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h
index 4355e1c..1a47aad 100644
--- a/include/configs/utx8245.h
+++ b/include/configs/utx8245.h
@@ -55,7 +55,7 @@
 
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		57600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_BOOTDELAY	2
 #define CONFIG_AUTOBOOT_PROMPT	"autoboot in %d seconds\n", bootdelay
@@ -63,7 +63,7 @@
 #define CONFIG_BOOTARGS		"root=/dev/ram console=ttyS0,57600" /* RAMdisk */
 #define CONFIG_ETHADDR		00:AA:00:14:00:05	/* UTX5 */
 #define CONFIG_SERVERIP		10.8.17.105	/* Spree */
-#define CFG_TFTP_LOADADDR	10000
+#define CONFIG_SYS_TFTP_LOADADDR	10000
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"kernel_addr=FFA00000\0" \
@@ -105,7 +105,7 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_CONSOLE
 #define CONFIG_CMD_LOADS
 #define CONFIG_CMD_LOADB
@@ -121,16 +121,16 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT	"=> "			/* Monitor Command Prompt	*/
-#define CFG_CBSIZE	256				/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"=> "			/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE	256				/* Console I/O Buffer Size	*/
 
 /* Print Buffer Size */
-#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/
 
 
 /*-----------------------------------------------------------------------
@@ -142,7 +142,7 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
 #define CONFIG_PCI_SCAN_SHOW
 #define CONFIG_NET_MULTI
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
 #define CONFIG_EEPRO100_SROM_WRITE
 
 #define PCI_ENET0_IOADDR	0xF0000000
@@ -161,61 +161,61 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE	    0x00000000
-#define CFG_MAX_RAM_SIZE    0x10000000	/* 256MB  */
-/*#define CFG_VERY_BIG_RAM	1 */
+#define CONFIG_SYS_SDRAM_BASE	    0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE    0x10000000	/* 256MB  */
+/*#define CONFIG_SYS_VERY_BIG_RAM	1 */
 
 /* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector
  * is actually located at FFF00100.  Therefore, U-Boot is
  * physically located at 0xFFB0_0000, but is also mirrored at
  * 0xFFF0_0000.
  */
-#define CFG_RESET_ADDRESS   0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 
-#define CFG_EUMB_ADDR	    0xFC000000
+#define CONFIG_SYS_EUMB_ADDR	    0xFC000000
 
-#define CFG_MONITOR_BASE    TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
 
-#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
 
-/*#define CFG_DRAM_TEST		1 */
-#define CFG_MEMTEST_START   0x00003000	/* memtest works on	0...256 MB	*/
-#define CFG_MEMTEST_END	    0x0ff8ffa7	/* in SDRAM, skips exception */
+/*#define CONFIG_SYS_DRAM_TEST		1 */
+#define CONFIG_SYS_MEMTEST_START   0x00003000	/* memtest works on	0...256 MB	*/
+#define CONFIG_SYS_MEMTEST_END	    0x0ff8ffa7	/* in SDRAM, skips exception */
 										/* vectors and U-Boot */
 
 
 /*--------------------------------------------------------------------
  * Definitions for initial stack pointer and data area
  *------------------------------------------------------------------*/
-#define CFG_INIT_DATA_SIZE    128	/* Size in bytes reserved for */
+#define CONFIG_SYS_INIT_DATA_SIZE    128	/* Size in bytes reserved for */
 									/* initial data */
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_INIT_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
-#define CFG_GBL_DATA_SIZE	128
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_END      0x1000
+#define CONFIG_SYS_INIT_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 /*--------------------------------------------------------------------
  * NS16550 Configuration
  *------------------------------------------------------------------*/
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
 
-#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_REG_SIZE	1
 
 #if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2)
-#	define CFG_NS16550_CLK		get_bus_freq(0)
+#	define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 #else
-#	define CFG_NS16550_CLK 33000000
+#	define CONFIG_SYS_NS16550_CLK 33000000
 #endif
 
-#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
-#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4600)
-#define CFG_NS16550_COM3	0xFF000000
-#define CFG_NS16550_COM4	0xFF000008
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_EUMB_ADDR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4600)
+#define CONFIG_SYS_NS16550_COM3	0xFF000000
+#define CONFIG_SYS_NS16550_COM4	0xFF000008
 
 /*--------------------------------------------------------------------
  * Low Level Configuration Settings
@@ -225,10 +225,10 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
  *------------------------------------------------------------------*/
 
 #define CONFIG_SYS_CLK_FREQ  33000000
-#define CFG_HZ				1000
+#define CONFIG_SYS_HZ				1000
 
-/*#define CFG_ETH_DEV_FN	     0x7800 */
-/*#define CFG_ETH_IOBASE	     0x00104000 */
+/*#define CONFIG_SYS_ETH_DEV_FN	     0x7800 */
+/*#define CONFIG_SYS_ETH_IOBASE	     0x00104000 */
 
 /*--------------------------------------------------------------------
  * I2C Configuration
@@ -236,13 +236,13 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
 #if 1
 #define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
 #undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 #endif
 
 #define CONFIG_RTC_PCF8563	1		/* enable I2C support for */
 									/* Philips PCF8563 RTC */
-#define CFG_I2C_RTC_ADDR	0x51	/* Philips PCF8563 RTC address */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* Philips PCF8563 RTC address */
 
 /*--------------------------------------------------------------------
  *	Memory Control Configuration Register values
@@ -250,59 +250,59 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
  *------------------------------------------------------------------*/
 
 /**** MCCR1 ****/
-#define CFG_ROMNAL	    0
-#define CFG_ROMFAL	    10		/* (tacc=70ns)*mem_freq - 2,
+#define CONFIG_SYS_ROMNAL	    0
+#define CONFIG_SYS_ROMFAL	    10		/* (tacc=70ns)*mem_freq - 2,
 									mem_freq = 100MHz */
 
-#define CFG_BANK7_ROW	0		/* SDRAM bank 7-0 row address */
-#define CFG_BANK6_ROW	0		/*	bit count */
-#define CFG_BANK5_ROW	0
-#define CFG_BANK4_ROW	0
-#define CFG_BANK3_ROW	0
-#define CFG_BANK2_ROW	0
-#define CFG_BANK1_ROW	2
-#define CFG_BANK0_ROW	2
+#define CONFIG_SYS_BANK7_ROW	0		/* SDRAM bank 7-0 row address */
+#define CONFIG_SYS_BANK6_ROW	0		/*	bit count */
+#define CONFIG_SYS_BANK5_ROW	0
+#define CONFIG_SYS_BANK4_ROW	0
+#define CONFIG_SYS_BANK3_ROW	0
+#define CONFIG_SYS_BANK2_ROW	0
+#define CONFIG_SYS_BANK1_ROW	2
+#define CONFIG_SYS_BANK0_ROW	2
 
 /**** MCCR2, refresh interval clock cycles ****/
-#define CFG_REFINT	    480	    /* 33 MHz SDRAM clock was 480 */
+#define CONFIG_SYS_REFINT	    480	    /* 33 MHz SDRAM clock was 480 */
 
 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
-#define CFG_BSTOPRE	    1023	/* burst to precharge[0..9], */
+#define CONFIG_SYS_BSTOPRE	    1023	/* burst to precharge[0..9], */
 								/* sets open page interval */
 
 /**** MCCR3 ****/
-#define CFG_REFREC	    7	    /* Refresh to activate interval, trc */
+#define CONFIG_SYS_REFREC	    7	    /* Refresh to activate interval, trc */
 
 /**** MCCR4 ****/
-#define CFG_PRETOACT	    2	    /* trp */
-#define CFG_ACTTOPRE	    7	    /* trcd + (burst length - 1) + trdl */
-#define CFG_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
-#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type, sequential */
-#define CFG_ACTORW		2		/* trcd min */
-#define CFG_DBUS_SIZE2		1		/* set for 8-bit RCS1, clear for 32,64 */
-#define CFG_REGISTERD_TYPE_BUFFER 1
-#define CFG_EXTROM	    0			/* we don't need extended ROM space */
-#define CFG_REGDIMM	    0
+#define CONFIG_SYS_PRETOACT	    2	    /* trp */
+#define CONFIG_SYS_ACTTOPRE	    7	    /* trcd + (burst length - 1) + trdl */
+#define CONFIG_SYS_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
+#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type, sequential */
+#define CONFIG_SYS_ACTORW		2		/* trcd min */
+#define CONFIG_SYS_DBUS_SIZE2		1		/* set for 8-bit RCS1, clear for 32,64 */
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
+#define CONFIG_SYS_EXTROM	    0			/* we don't need extended ROM space */
+#define CONFIG_SYS_REGDIMM	    0
 
 /* calculate according to formula in sec. 6-22 of 8245 UM */
-#define CFG_PGMAX           50		/* how long the 8245 retains the */
+#define CONFIG_SYS_PGMAX           50		/* how long the 8245 retains the */
 									/* currently accessed page in memory */
 									/* was 45 */
 
-#define CFG_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note */
+#define CONFIG_SYS_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note */
 								/* bits 7,6, and 3-0 MUST be 0 */
 
 #if 0
-#define CFG_DLL_MAX_DELAY	0x04
+#define CONFIG_SYS_DLL_MAX_DELAY	0x04
 #else
-#define CFG_DLL_MAX_DELAY	0
+#define CONFIG_SYS_DLL_MAX_DELAY	0
 #endif
 #if 0							/* need for 33MHz SDRAM */
-#define CFG_DLL_EXTEND	0x80
+#define CONFIG_SYS_DLL_EXTEND	0x80
 #else
-#define CFG_DLL_EXTEND	0
+#define CONFIG_SYS_DLL_EXTEND	0
 #endif
-#define CFG_PCI_HOLD_DEL 0x20
+#define CONFIG_SYS_PCI_HOLD_DEL 0x20
 
 
 /* Memory bank settings.
@@ -312,94 +312,94 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
  * address. Refer to the MPC8245 user manual.
  */
 
-#define CFG_BANK0_START	    0x00000000
-#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE/2 - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START	    CFG_MAX_RAM_SIZE/2
-#define CFG_BANK1_END	    (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK1_ENABLE    1
-#define CFG_BANK2_START	    0x3ff00000		/* not available in this design */
-#define CFG_BANK2_END	    0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START	    0x3ff00000
-#define CFG_BANK3_END	    0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START	    0x3ff00000
-#define CFG_BANK4_END	    0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START	    0x3ff00000
-#define CFG_BANK5_END	    0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START	    0x3ff00000
-#define CFG_BANK6_END	    0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START	    0x3ff00000
-#define CFG_BANK7_END	    0x3fffffff
-#define CFG_BANK7_ENABLE    0
+#define CONFIG_SYS_BANK0_START	    0x00000000
+#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE/2 - 1)
+#define CONFIG_SYS_BANK0_ENABLE    1
+#define CONFIG_SYS_BANK1_START	    CONFIG_SYS_MAX_RAM_SIZE/2
+#define CONFIG_SYS_BANK1_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK1_ENABLE    1
+#define CONFIG_SYS_BANK2_START	    0x3ff00000		/* not available in this design */
+#define CONFIG_SYS_BANK2_END	    0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE    0
+#define CONFIG_SYS_BANK3_START	    0x3ff00000
+#define CONFIG_SYS_BANK3_END	    0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE    0
+#define CONFIG_SYS_BANK4_START	    0x3ff00000
+#define CONFIG_SYS_BANK4_END	    0x3fffffff
+#define CONFIG_SYS_BANK4_ENABLE    0
+#define CONFIG_SYS_BANK5_START	    0x3ff00000
+#define CONFIG_SYS_BANK5_END	    0x3fffffff
+#define CONFIG_SYS_BANK5_ENABLE    0
+#define CONFIG_SYS_BANK6_START	    0x3ff00000
+#define CONFIG_SYS_BANK6_END	    0x3fffffff
+#define CONFIG_SYS_BANK6_ENABLE    0
+#define CONFIG_SYS_BANK7_START	    0x3ff00000
+#define CONFIG_SYS_BANK7_END	    0x3fffffff
+#define CONFIG_SYS_BANK7_ENABLE    0
 
 /*--------------------------------------------------------------------*/
 /* 4.4 - Output Driver Control Register */
 /*--------------------------------------------------------------------*/
-#define CFG_ODCR	    0xe5
+#define CONFIG_SYS_ODCR	    0xe5
 
 /*--------------------------------------------------------------------*/
 /* 4.8 - Error Handling Registers */
-/*-------------------------------CFG_SDMODE_BURSTLEN-------------------------------------*/
-#define CFG_ERRENR1	0x11	/* enable SDRAM refresh overflow error */
+/*-------------------------------CONFIG_SYS_SDMODE_BURSTLEN-------------------------------------*/
+#define CONFIG_SYS_ERRENR1	0x11	/* enable SDRAM refresh overflow error */
 
 /* SDRAM 0-256 MB */
-#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-/*#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */
-#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+/*#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */
+#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* stack in dcache */
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 
 
-#define CFG_IBAT2L  (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT2U  (CFG_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L  (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U  (CONFIG_SYS_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* PCI memory */
-/*#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */
-/*#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */
+/*#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */
+/*#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */
 
 /*Flash, config addrs, etc. */
-#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L  CFG_IBAT0L
-#define CFG_DBAT0U  CFG_IBAT0U
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-#define CFG_DBAT2L  CFG_IBAT2L
-#define CFG_DBAT2U  CFG_IBAT2U
-#define CFG_DBAT3L  CFG_IBAT3L
-#define CFG_DBAT3U  CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE	    0xFF800000
-#define CFG_MAX_FLASH_BANKS	1			/* Max number of flash banks */
+#define CONFIG_SYS_FLASH_BASE	    0xFF800000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1			/* Max number of flash banks */
 
 /*	NOTE: environment is not EMBEDDED in the u-boot code.
 	It's stored in flash in its own separate sector.  */
 #define CONFIG_ENV_IS_IN_FLASH	    1
 
 #if 1	/* AMD AM29LV033C */
-#define CFG_MAX_FLASH_SECT	64		/* Max number of sectors in one bank */
+#define CONFIG_SYS_MAX_FLASH_SECT	64		/* Max number of sectors in one bank */
 #define CONFIG_ENV_ADDR		0xFFBF0000	/* flash sector SA63 */
 #define CONFIG_ENV_SECT_SIZE	(64*1024)	/* Size of the Environment Sector */
 #else	/* AMD AM29LV116D */
-#define CFG_MAX_FLASH_SECT	35	/* Max number of sectors in one bank */
+#define CONFIG_SYS_MAX_FLASH_SECT	35	/* Max number of sectors in one bank */
 #define CONFIG_ENV_ADDR		0xFF9FA000	/* flash sector SA33 */
 #define CONFIG_ENV_SECT_SIZE	(8*1024)	/* Size of the Environment Sector */
 #endif /* #if */
@@ -407,22 +407,22 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
 #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE		/* Size of the Environment */
 #define CONFIG_ENV_OFFSET		0			/* starting right at the beginning */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#undef CFG_RAMBOOT
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#undef CONFIG_SYS_RAMBOOT
 #else
-#define CFG_RAMBOOT
+#define CONFIG_SYS_RAMBOOT
 #endif
 
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SIZE	32
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /*
diff --git a/include/configs/v37.h b/include/configs/v37.h
index 7504fa3..a6b0f0d 100644
--- a/include/configs/v37.h
+++ b/include/configs/v37.h
@@ -45,7 +45,7 @@
  *-----------------------------------------------------------------------------
  */
 #define CONFIG_I2C              1
-#define CFG_I2C_SLAVE           0x2
+#define CONFIG_SYS_I2C_SLAVE           0x2
 
 #define	CONFIG_8xx_CONS_SMC1	1
 #undef	CONFIG_8xx_CONS_SMC2		/* Console is on SMC2		*/
@@ -70,7 +70,7 @@
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -122,25 +122,25 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -150,50 +150,50 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR		0xF0000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE0		0x40000000
-#define CFG_FLASH_BASE1		0x60000000
-#define CFG_FLASH_BASE		CFG_FLASH_BASE1
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE0		0x40000000
+#define CONFIG_SYS_FLASH_BASE1		0x60000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH_BASE1
 
 #if defined(DEBUG)
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE0
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE0
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	35	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	35	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_NVRAM	1
 #define	CONFIG_ENV_ADDR		0x80000000/* Address of Environment */
@@ -204,9 +204,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -216,10 +216,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	0xFFFFFF88
+#define CONFIG_SYS_SYPCR	0xFFFFFF88
 #endif
 
 /*-----------------------------------------------------------------------
@@ -227,30 +227,30 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_FRC | SIUMCR_GB5E)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_FRC | SIUMCR_GB5E)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-/*%%%#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_RTE)
+/*%%%#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
 /*
-#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
 */
 
 /*-----------------------------------------------------------------------
@@ -262,7 +262,7 @@
  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  */
 /* up to 50 MHz we use a 1:1 clock */
-#define CFG_PLPRCR	( (1524 << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TMIST | PLPRCR_TEXPS )
+#define CONFIG_SYS_PLPRCR	( (1524 << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TMIST | PLPRCR_TEXPS )
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -272,21 +272,21 @@
  */
 #define SCCR_MASK	SCCR_EBDF11
 /* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_COM00 | SCCR_TBS)
+#define CONFIG_SYS_SCCR	(SCCR_COM00 | SCCR_TBS)
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -299,28 +299,28 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -331,21 +331,21 @@
 #define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
 #define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #1	*/
 
-#define CFG_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
 
-#define CFG_OR_TIMING_FLASH	0xF56
+#define CONFIG_SYS_OR_TIMING_FLASH	0xF56
 
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V)
 
-#define CFG_OR5_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR5_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V)
+#define CONFIG_SYS_OR5_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR5_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V)
 
 /*
  * BR1 and OR1 (Battery backed SRAM)
  */
-#define	CFG_BR1_PRELIM	0x80000401
-#define CFG_OR1_PRELIM	0xFFC00736
+#define	CONFIG_SYS_BR1_PRELIM	0x80000401
+#define CONFIG_SYS_OR1_PRELIM	0xFFC00736
 
 /*
  * BR2 and OR2 (SDRAM)
@@ -353,21 +353,21 @@
 #define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB */
 
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 /* Marel V37 mem setting */
 
-#define	CFG_BR3_CAN	0xC0000401
-#define CFG_OR3_CAN	0xFFFF0724
+#define	CONFIG_SYS_BR3_CAN	0xC0000401
+#define CONFIG_SYS_OR3_CAN	0xFFFF0724
 
 /*
-#define	CFG_BR3_PRELIM	0xFA400001
-#define CFG_OR3_PRELIM	0xFFFF8910
-#define	CFG_BR4_PRELIM	0xFA000401
-#define CFG_OR4_PRELIM	0xFFFE0970
+#define	CONFIG_SYS_BR3_PRELIM	0xFA400001
+#define CONFIG_SYS_OR3_PRELIM	0xFFFF8910
+#define	CONFIG_SYS_BR4_PRELIM	0xFA000401
+#define CONFIG_SYS_OR4_PRELIM	0xFFFE0970
 */
 
 /*
@@ -375,19 +375,19 @@
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/
 
 /*
  * Refresh clock Prescalar
  */
-#define CFG_MPTPR	MPTPR_PTP_DIV16
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV16
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 10 column SDRAM */
-#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_10COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 |	\
 			 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
 
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index 0f8d5a9..fc7128e 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -29,7 +29,7 @@
 #define CONFIG_MPC5xxx			1	/* This is an MPC5xxx CPU */
 #define CONFIG_MPC5200			1	/* This is an MPC5200 CPU */
 #define CONFIG_V38B			1	/* ...on V38B board */
-#define CFG_MPC5XXX_CLKIN	33000000	/* ...running at 33.000000MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* ...running at 33.000000MHz */
 
 #define CONFIG_RTC_PCF8563		1	/* has PCF8563 RTC */
 #define CONFIG_MPC5200_DDR		1	/* has DDR SDRAM */
@@ -41,7 +41,7 @@
 #define CONFIG_BOARD_EARLY_INIT_R	1	/* do board-specific init */
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* do board-specific init */
 
-#define CFG_XLB_PIPELINING		1	/* gives better performance */
+#define CONFIG_SYS_XLB_PIPELINING		1	/* gives better performance */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot */
@@ -53,7 +53,7 @@
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*
  * DDR
@@ -121,8 +121,8 @@
 /*
  * Boot low with 16 MB Flash
  */
-#define CFG_LOWBOOT		1
-#define CFG_LOWBOOT16		1
+#define CONFIG_SYS_LOWBOOT		1
+#define CONFIG_SYS_LOWBOOT16		1
 
 /*
  * Autobooting
@@ -173,48 +173,48 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBCLK_EQUALS_XLBCLK			/* define for 133MHz speed */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK			/* define for 133MHz speed */
 #endif
 
 /*
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
-#define CFG_I2C_SPEED		100000	/* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration
  */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
 
 /*
  * RTC configuration
  */
-#define CFG_I2C_RTC_ADDR		0x51
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
 
 /*
  * Flash configuration - use CFI driver
  */
-#define CFG_FLASH_CFI		1		/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1		/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1		/* Use the common driver */
-#define CFG_FLASH_CFI_AMD_RESET	1
-#define CFG_FLASH_BASE		0xFF000000
-#define CFG_MAX_FLASH_BANKS	1		/* max num of flash banks */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
-#define CFG_FLASH_SIZE		0x01000000	/* 16 MiB */
-#define CFG_MAX_FLASH_SECT	256		/* max num of sects on one chip */
-#define CFG_FLASH_USE_BUFFER_WRITE	1	/* flash write speed-up */
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max num of flash banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_SIZE		0x01000000	/* 16 MiB */
+#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1	/* flash write speed-up */
 
 /*
  * Environment settings
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
 #define CONFIG_ENV_SIZE		0x10000
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #define CONFIG_ENV_OVERWRITE	1
@@ -222,81 +222,82 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128kB for malloc() */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Linux initial memory map */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128kB for malloc() */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Linux initial memory map */
 
 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
 #define CONFIG_PHY_ADDR		0x00
 #define CONFIG_MII		1
 
 /*
  * GPIO configuration
  */
-#define CFG_GPS_PORT_CONFIG	0x90001404
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x90001404
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM */
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*
  * Various low-level settings
  */
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x00047801
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047801
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
 
-#define CFG_RESET_ADDRESS	0xff000000
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
 
 /*
  * IDE/ATA (supports IDE harddisk)
@@ -308,20 +309,20 @@
 #define CONFIG_IDE_RESET		/* reset for ide supported */
 #define CONFIG_IDE_PREINIT
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus */
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus */
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
 
-#define CFG_ATA_DATA_OFFSET	(0x0060)	/* data I/O offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)	/* data I/O offset */
 
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)	/* normal register accesses offset */
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)	/* normal register accesses offset */
 
-#define CFG_ATA_ALT_OFFSET	(0x005C)	/* alternate registers offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)	/* alternate registers offset */
 
-#define CFG_ATA_STRIDE		4		/* Interval between registers */
+#define CONFIG_SYS_ATA_STRIDE		4		/* Interval between registers */
 
 /*
  * Status LED
@@ -329,26 +330,26 @@
 #define  CONFIG_STATUS_LED		/* Status LED enabled */
 #define  CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */
 
-#define CFG_LED_BASE	MPC5XXX_GPT7_ENABLE	/* Timer 7 GPIO */
+#define CONFIG_SYS_LED_BASE	MPC5XXX_GPT7_ENABLE	/* Timer 7 GPIO */
 #ifndef __ASSEMBLY__
 typedef unsigned int led_id_t;
 
 #define __led_toggle(_msk) \
 	do { \
-		*((volatile long *) (CFG_LED_BASE)) ^= (_msk); \
+		*((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
 	} while(0)
 
 #define __led_set(_msk, _st) \
 	do { \
 		if ((_st)) \
-			*((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \
+			*((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
 		else \
-			*((volatile long *) (CFG_LED_BASE)) |= (_msk); \
+			*((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \
 	} while(0)
 
 #define __led_init(_msk, st) \
 	do { \
-		*((volatile long *) (CFG_LED_BASE)) |= 0x34; \
+		*((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \
 	} while(0)
 #endif /* __ASSEMBLY__ */
 
diff --git a/include/configs/v5fx30teval.h b/include/configs/v5fx30teval.h
index 1636d42..d300c4b 100644
--- a/include/configs/v5fx30teval.h
+++ b/include/configs/v5fx30teval.h
@@ -24,7 +24,7 @@
 #include "../board/avnet/v5fx30teval/xparameters.h"
 
 /*Mem Map*/
-#define CFG_SDRAM_SIZE_MB	64
+#define CONFIG_SYS_SDRAM_SIZE_MB	64
 
 /*Env*/
 #define	CONFIG_ENV_IS_IN_FLASH	1
@@ -34,12 +34,12 @@
 #define CONFIG_ENV_ADDR		(XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
 
 /*Misc*/
-#define CFG_PROMPT		"v5fx30t:/# "	/* Monitor Command Prompt    */
+#define CONFIG_SYS_PROMPT		"v5fx30t:/# "	/* Monitor Command Prompt    */
 #define CONFIG_PREBOOT		"echo U-Boot is up and runnining;"
 
 /*Flash*/
-#define	CFG_FLASH_SIZE		(16*1024*1024)
-#define	CFG_MAX_FLASH_SECT	131
+#define	CONFIG_SYS_FLASH_SIZE		(16*1024*1024)
+#define	CONFIG_SYS_MAX_FLASH_SECT	131
 #define MTDIDS_DEFAULT		"nor0=v5fx30t-flash"
 #define MTDPARTS_DEFAULT	"mtdparts=v5fx30t-flash:-(user)"
 
diff --git a/include/configs/vct.h b/include/configs/vct.h
new file mode 100644
index 0000000..391535e
--- /dev/null
+++ b/include/configs/vct.h
@@ -0,0 +1,340 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for the VCT board
+ * family:
+ *
+ * vct_premium
+ * vct_premium_small
+ * vct_premium_onenand
+ * vct_premium_onenand_small
+ * vct_platinum
+ * vct_platinum_small
+ * vct_platinum_onenand
+ * vct_platinum_onenand_small
+ * vct_platinumavc
+ * vct_platinumavc_small
+ * vct_platinumavc_onenand
+ * vct_platinumavc_onenand_small
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS32				/* MIPS 4Kc CPU core	*/
+#define CPU_CLOCK_RATE			324000000 /* Clock for the MIPS core */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CPU_CLOCK_RATE / 2)
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* SDRAM is initialized by the bootstrap code */
+
+#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+#define CONFIG_STACKSIZE		(256 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(128 << 10)
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+
+#if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND)
+#define CONFIG_VCT_NOR
+#else
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+/*
+ * UART
+ */
+#define CONFIG_VCT_SERIAL
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * SDRAM
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_MBYTES_SDRAM		128
+#define CONFIG_SYS_MEMTEST_START	0x80200000
+#define CONFIG_SYS_MEMTEST_END		0x80400000
+#define CONFIG_SYS_LOAD_ADDR		0x80400000	/* default load address */
+
+#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
+/*
+ * SMSC91C11x Network Card
+ */
+#define CONFIG_DRIVER_SMC911X
+#define CONFIG_DRIVER_SMC911X_BASE	0x00000000
+#define CONFIG_DRIVER_SMC911X_32_BIT
+#define CONFIG_NET_RETRY_COUNT		20
+#endif
+
+/*
+ * Commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+
+/*
+ * Only Premium/Platinum have ethernet support right now
+ */
+#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+#else
+#undef CONFIG_CMD_NET
+#endif
+
+/*
+ * Only Premium/Platinum have USB-EHCI support right now
+ */
+#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#endif
+
+#if defined(CONFIG_CMD_USB)
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+/*
+ * USB/EHCI
+ */
+#define CONFIG_USB_EHCI			/* Enable EHCI USB support	*/
+#define CONFIG_USB_EHCI_VCT		/* on VCT platform		*/
+#define CONFIG_EHCI_DCACHE		/* with dcache handling support	*/
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
+#endif /* CONFIG_CMD_USB */
+
+#if !defined(CONFIG_VCT_NOR)
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#endif
+
+#if defined(CONFIG_VCT_NAND)
+#define CONFIG_CMD_NAND
+#endif
+
+#if defined(CONFIG_VCT_ONENAND)
+#define CONFIG_CMD_ONENAND
+#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"VCT# "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+				 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_TIMESTAMP			/* Print image info with timestamp */
+#define CONFIG_CMDLINE_EDITING			/* add command line history	*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET		/* don't print console @ startup*/
+
+/*
+ * FLASH and environment organization
+ */
+#if defined(CONFIG_VCT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_FLASH_NOT_MEM_MAPPED
+
+/*
+ * We need special accessor functions for the CFI FLASH driver. This
+ * can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option.
+ */
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+
+/*
+ * For the non-memory-mapped NOR FLASH, we need to define the
+ * NOR FLASH area. This can't be detected via the addr2info()
+ * function, since we check for flash access in the very early
+ * U-Boot code, before the NOR FLASH is detected.
+ */
+#define CONFIG_FLASH_BASE		0xb0000000
+#define CONFIG_FLASH_END		0xbfffffff
+
+/*
+ * CFI driver settings
+ */
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1	/* Use AMD (Spansion) reset cmd */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/
+
+#define CONFIG_SYS_FLASH_BASE		0xb0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+#endif /* CONFIG_VCT_NOR */
+
+#if defined(CONFIG_VCT_ONENAND)
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define	CONFIG_ENV_IS_IN_ONENAND
+#define	CONFIG_SYS_ONENAND_BASE		0x00000000	/* this is not real address */
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_ENV_ADDR			(128 << 10)	/* after compr. U-Boot image */
+#define	CONFIG_ENV_SIZE			(128 << 10)	/* erase size */
+#endif /* CONFIG_VCT_ONENAND */
+
+/*
+ * Cache Configuration
+ */
+#define CONFIG_SYS_DCACHE_SIZE		16384
+#define CONFIG_SYS_ICACHE_SIZE		16384
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+/*
+ * I2C/EEPROM
+ */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+
+#define CONFIG_SYS_I2C_SPEED		83000	/* 83 kHz is supposed to work	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7f
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define CONFIG_SYS_GPIO_I2C_SCL		11
+#define CONFIG_SYS_GPIO_I2C_SDA		10
+
+#ifndef __ASSEMBLY__
+int vct_gpio_dir(int pin, int dir);
+void vct_gpio_set(int pin, int val);
+int vct_gpio_get(int pin);
+#endif
+
+#define I2C_INIT	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1)
+#define I2C_ACTIVE	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1)
+#define I2C_TRISTATE	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0)
+#define I2C_READ	vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA)
+#define I2C_SDA(bit)	vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit)
+#define I2C_SCL(bit)	vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit)
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+/* CAT24WC32 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
+					/* 32 byte page write mode using*/
+					/* last 5 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+#define CONFIG_BOOTCOMMAND	"run test3"
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+/*
+ * Needed for 64bit printf format
+ */
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
+
+/*
+ * UBI configuration
+ */
+#if defined(CONFIG_VCT_ONENAND)
+#define CONFIG_SYS_USE_UBI
+#define	CONFIG_CMD_JFFS2
+#define	CONFIG_CMD_UBI
+#define	CONFIG_RBTREE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_JFFS2_CMDLINE
+
+#define MTDIDS_DEFAULT		"onenand0=onenand"
+#define MTDPARTS_DEFAULT	"mtdparts=onenand:128k(u-boot),"	\
+					"128k(env),"		\
+					"20m(kernel),"		\
+					"-(rootfs)"
+#endif
+
+/*
+ * We need a small, stripped down image to fit into the first 128k OneNAND
+ * erase block (gzipped). This image only needs basic commands for FLASH
+ * (NOR/OneNAND) usage and Linux kernel booting.
+ */
+#if defined(CONFIG_VCT_SMALL_IMAGE)
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_PING
+#undef CONFIG_CMD_SNTP
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_CONSOLE
+#undef CONFIG_CMD_CACHE
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_IRQ
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_REGINFO
+#undef CONFIG_CMD_STRINGS
+#undef CONFIG_CMD_TERMINAL
+#undef CONFIG_CMD_ASKENV
+#undef CONFIG_CMD_CRC32
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADY
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_FAT
+
+#undef CONFIG_DRIVER_SMC911X
+#undef CONFIG_SOFT_I2C
+#undef CONFIG_AUTOSCRIPT
+#undef CONFIG_SYS_LONGHELP
+#undef CONFIG_TIMESTAMP
+#endif /* CONFIG_VCT_SMALL_IMAGE */
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/versatile.h b/include/configs/versatile.h
index 6034cb7..852becb 100644
--- a/include/configs/versatile.h
+++ b/include/configs/versatile.h
@@ -40,14 +40,14 @@
 #define CONFIG_ARCH_VERSATILE   1	/* Specifically, a Versatile	*/
 
 
-#define CFG_MEMTEST_START       0x100000
-#define CFG_MEMTEST_END         0x10000000
-#define CFG_HZ                  (1000000 / 256)
-#define CFG_TIMERBASE           0x101E2000	/* Timer 0 and 1 base */
+#define CONFIG_SYS_MEMTEST_START       0x100000
+#define CONFIG_SYS_MEMTEST_END         0x10000000
+#define CONFIG_SYS_HZ                  (1000000 / 256)
+#define CONFIG_SYS_TIMERBASE           0x101E2000	/* Timer 0 and 1 base */
 
-#define CFG_TIMER_INTERVAL	10000
-#define CFG_TIMER_RELOAD	(CFG_TIMER_INTERVAL >> 4)	/* Divide by 16 */
-#define CFG_TIMER_CTRL          0x84				/* Enable, Clock / 16 */
+#define CONFIG_SYS_TIMER_INTERVAL	10000
+#define CONFIG_SYS_TIMER_RELOAD	(CONFIG_SYS_TIMER_INTERVAL >> 4)	/* Divide by 16 */
+#define CONFIG_SYS_TIMER_CTRL          0x84				/* Enable, Clock / 16 */
 
 /*
  * control registers
@@ -71,8 +71,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -88,13 +88,13 @@
  */
 #define CONFIG_PL011_SERIAL
 #define CONFIG_PL011_CLOCK	24000000
-#define CONFIG_PL01x_PORTS	{ (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
+#define CONFIG_PL01x_PORTS	{ (void *)CONFIG_SYS_SERIAL0, (void *)CONFIG_SYS_SERIAL1 }
 #define CONFIG_CONS_INDEX	0
 
 #define CONFIG_BAUDRATE         38400
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
-#define CFG_SERIAL0		0x101F1000
-#define CFG_SERIAL1		0x101F2000
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_SERIAL0		0x101F1000
+#define CONFIG_SYS_SERIAL1		0x101F2000
 
 
 /*
@@ -108,7 +108,7 @@
 #define CONFIG_CMD_BDI
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_FLASH
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 
 
 /*
@@ -136,16 +136,16 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP	/* undef to save memory     */
-#define CFG_PROMPT	"Versatile # "	/* Monitor Command Prompt   */
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_LONGHELP	/* undef to save memory     */
+#define CONFIG_SYS_PROMPT	"Versatile # "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size  */
 /* Print Buffer Size */
-#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS	16		/* max number of command args   */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-#define CFG_LOAD_ADDR	0x7fc0	/* default load address */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#define CONFIG_SYS_LOAD_ADDR	0x7fc0	/* default load address */
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -165,7 +165,7 @@
 #define PHYS_SDRAM_1            0x00000000	/* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE       0x08000000	/* 128 MB */
 
-#define CFG_FLASH_BASE          0x34000000
+#define CONFIG_SYS_FLASH_BASE          0x34000000
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
@@ -176,19 +176,19 @@
 #define VERSATILE_FLASHCTRL		      (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
 #define VERSATILE_FLASHPROG_FLVPPEN	      (1 << 0)	/* Enable writing to flash */
 
-#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of memory banks */
 #define PHYS_FLASH_SIZE         0x34000000	/* 64MB */
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Write */
-#define CFG_MAX_FLASH_SECT	(256)
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(20*CONFIG_SYS_HZ)	/* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(20*CONFIG_SYS_HZ)	/* Timeout for Flash Write */
+#define CONFIG_SYS_MAX_FLASH_SECT	(256)
 
-#define PHYS_FLASH_1		(CFG_FLASH_BASE)
+#define PHYS_FLASH_1		(CONFIG_SYS_FLASH_BASE)
 
 #define CONFIG_ENV_IS_IN_FLASH     1               /* env in flash instead of CONFIG_ENV_IS_NOWHERE */
 #define CONFIG_ENV_SECT_SIZE       0x00020000      /* 256 KB sectors (x2) */
 #define CONFIG_ENV_SIZE            0x10000         /* Total Size of Environment Sector */
 #define CONFIG_ENV_OFFSET          0x01f00000      /* environment starts here  */
-#define CONFIG_ENV_ADDR            (CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR            (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 
 #endif							/* __CONFIG_H */
diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h
index f3f43c3..7b61c82 100644
--- a/include/configs/virtlab2.h
+++ b/include/configs/virtlab2.h
@@ -81,7 +81,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -117,6 +117,7 @@
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_NFS
@@ -132,32 +133,32 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -167,47 +168,47 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0x40000000
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 
 /* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE	1
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
@@ -217,7 +218,7 @@
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
 #define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
 
@@ -236,16 +237,16 @@
 /*-----------------------------------------------------------------------
  * Hardware Information Block
  */
-#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -255,10 +256,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -267,9 +268,9 @@
  * PCMCIA config., multi-function pin tri-state
  */
 #ifndef	CONFIG_CAN_DRIVER
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
 
 /*-----------------------------------------------------------------------
@@ -277,20 +278,20 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * RTCSC - Real-Time Clock Status and Control Register		11-27
  *-----------------------------------------------------------------------
  */
-#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
@@ -298,7 +299,7 @@
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit
  */
-#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -307,7 +308,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 
@@ -316,14 +317,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
@@ -336,28 +337,28 @@
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
 
 /*-----------------------------------------------------------------------
  *
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CONFIG_SYS_DER	0
 
 /*
  * Init Memory Controller:
@@ -372,22 +373,22 @@
  * restrict access enough to keep SRAM working (if any)
  * but not too much to meddle with FLASH accesses
  */
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
 
 /*
  * FLASH timing:
  */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
 
-#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 
-#define CFG_OR1_REMAP	CFG_OR0_REMAP
-#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 
 /*
  * BR2/3 and OR2/3 (SDRAM)
@@ -398,19 +399,19 @@
 #define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CFG_OR_TIMING_SDRAM	0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
 
-#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 
 #ifndef	CONFIG_CAN_DRIVER
-#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 #else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 					BR_PS_8 | BR_MS_UPMB | BR_V )
 #endif	/* CONFIG_CAN_DRIVER */
 
@@ -441,34 +442,34 @@
  * 80 Mhz => 80.000.000 / Divider = 156
  */
 
-#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
-#define CFG_MAMR_PTA	98
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us
  * (= 64 ms / 2K = 125 / quad bursts).
  * For a simpler initialization, 15.6 us is used instead.
  *
- * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
- * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
  */
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 
 /*
  * MAMR settings for SDRAM
  */
 
 /* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
@@ -482,10 +483,10 @@
 #define BOOTFLAG_WARM	0x02		/* Software reboot			*/
 
 /* Map peripheral control registers on CS4 */
-#define CFG_PERIPHERAL_BASE 0xA0000000
-#define CFG_PERIPHERAL_OR_AM 0xFFFF8000 /* 32 kB address mask */
-#define CFG_OR4_PRELIM (CFG_PERIPHERAL_OR_AM | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_PERIPHERAL_BASE 0xA0000000
+#define CONFIG_SYS_PERIPHERAL_OR_AM 0xFFFF8000 /* 32 kB address mask */
+#define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PERIPHERAL_OR_AM | OR_TRLX | OR_CSNT_SAM | \
 						OR_SCY_2_CLK)
-#define CFG_BR4_PRELIM ((CFG_PERIPHERAL_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define PCMCIA_CTRL (CFG_PERIPHERAL_BASE + 0xB00)
+#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_PERIPHERAL_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define PCMCIA_CTRL (CONFIG_SYS_PERIPHERAL_BASE + 0xB00)
 #endif	/* __CONFIG_H */
diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h
index 312f720..f460610 100644
--- a/include/configs/voiceblue.h
+++ b/include/configs/voiceblue.h
@@ -54,28 +54,28 @@
 
 #define PHYS_FLASH_1		0x00000000	/* Flash Bank #1 */
 
-#define CFG_LOAD_ADDR		PHYS_SDRAM_1 + 0x400000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM_1 + 0x400000	/* default load address */
 
 /*
  * FLASH organization
  */
-#define CFG_FLASH_CFI			/* Flash is CFI conformant */
+#define CONFIG_SYS_FLASH_CFI			/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER		/* Use the common driver */
-#define CFG_MAX_FLASH_BANKS	1
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /* FIXME: Does not work on AMD flash */
-/* #define CFG_FLASH_USE_BUFFER_WRITE 1 */	/* use buffered writes (20x faster) */
-#define CFG_MAX_FLASH_SECT	512	/* max # of sectors on one chip */
+/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 */	/* use buffered writes (20x faster) */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max # of sectors on one chip */
 
-#define CFG_MONITOR_BASE	PHYS_FLASH_1
-#define CFG_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MONITOR_BASE	PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
 
 /*
  * Environment settings
  */
 #define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_ENV_SIZE		(8 * 1024)
 #define CONFIG_ENV_SECT_SIZE	(64 * 1024)
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
@@ -86,10 +86,10 @@
 /*
  * Size of malloc() pool and stack
  */
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_MALLOC_LEN		(4 * 1024 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 #define CONFIG_STACKSIZE	(1 * 1024 * 1024)
-#define PHYS_SDRAM_1_RESERVED	(CFG_MONITOR_LEN + CFG_MALLOC_LEN + CONFIG_STACKSIZE)
+#define PHYS_SDRAM_1_RESERVED	(CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE)
 
 /*
  * Hardware drivers
@@ -98,25 +98,25 @@
 #define CONFIG_SMC91111_BASE	0x08000300
 
 #define CONFIG_HARD_I2C
-#define CFG_I2C_SPEED		100000
-#define CFG_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
 #define CONFIG_DRIVER_OMAP1510_I2C
 
 #define CONFIG_RTC_DS1307
-#define CFG_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
 
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	(-4)
-#define CFG_NS16550_CLK		(CONFIG_XTAL_FREQ)	/* can be 12M/32Khz or 48Mhz  */
-#define CFG_NS16550_COM1	OMAP1510_UART1_BASE	/* uart1 */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		(CONFIG_XTAL_FREQ)	/* can be 12M/32Khz or 48Mhz  */
+#define CONFIG_SYS_NS16550_COM1	OMAP1510_UART1_BASE	/* uart1 */
 
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 
 /*
@@ -127,7 +127,7 @@
 #define CONFIG_CMD_BDI
 #define CONFIG_CMD_BOOTD
 #define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_IMI
 #define CONFIG_CMD_JFFS2
@@ -152,7 +152,7 @@
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow to break in always */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs*/
-#define CFG_AUTOLOAD		"n"		/* No autoload */
+#define CONFIG_SYS_AUTOLOAD		"n"		/* No autoload */
 #define CONFIG_BOOTCOMMAND	"run nboot"
 #define CONFIG_PREBOOT		"run setup"
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
@@ -197,27 +197,27 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_AUTO_COMPLETE
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"# "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"# "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	PHYS_SDRAM_1
-#define CFG_MEMTEST_END		PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - PHYS_SDRAM_1_RESERVED
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - PHYS_SDRAM_1_RESERVED
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
 /* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
  * This time is further subdivided by a local divisor.
  */
-#define CFG_TIMERBASE		OMAP1510_TIMER1_BASE
-#define CFG_PVT			7		/* 2^(pvt+1), divide by 256 */
-#define CFG_HZ			((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+#define CONFIG_SYS_TIMERBASE		OMAP1510_TIMER1_BASE
+#define CONFIG_SYS_PVT			7		/* 2^(pvt+1), divide by 256 */
+#define CONFIG_SYS_HZ			((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
 
 #define OMAP5910_DPLL_DIV	1
 #define OMAP5910_DPLL_MUL	((CONFIG_SYS_CLK_FREQ * \
diff --git a/include/configs/walnut.h b/include/configs/walnut.h
index 9676cd6..630c0d3 100644
--- a/include/configs/walnut.h
+++ b/include/configs/walnut.h
@@ -76,31 +76,30 @@
 #define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
 
 /*
- * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
  * The Linux BASE_BAUD define should match this configuration.
  *    baseBaud = cpuClock/(uartDivisor*16)
- * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  * set Linux BASE_BAUD to 403200.
  */
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#undef	CFG_EXT_SERIAL_CLOCK	       /* external serial clock */
-#undef	CFG_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* external serial clock */
+#undef	CONFIG_SYS_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD	    691200
 
 /*-----------------------------------------------------------------------
  * I2C stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -116,20 +115,20 @@
 					/* resource configuration	*/
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  */
-#define CFG_FLASH_BASE		0xFFF80000
+#define CONFIG_SYS_FLASH_BASE		0xFFF80000
 
 /*
  * Define here the location of the environment variables (FLASH or NVRAM).
@@ -145,24 +144,24 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0		*/
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0		*/
 #define FLASH_BASE1_PRELIM	0		/* FLASH bank #1		*/
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-#define CFG_FLASH_ADDR0		0x5555
-#define CFG_FLASH_ADDR1		0x2aaa
-#define CFG_FLASH_WORD_SIZE	unsigned char
+#define CONFIG_SYS_FLASH_ADDR0		0x5555
+#define CONFIG_SYS_FLASH_ADDR1		0x2aaa
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -173,13 +172,13 @@
 /*-----------------------------------------------------------------------
  * NVRAM organization
  */
-#define CFG_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
 
 #ifdef CONFIG_ENV_IS_IN_NVRAM
 #define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
 #define CONFIG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -187,39 +186,39 @@
  */
 
 /* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x9B015480
-#define CFG_EBC_PB0CR		0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB0AP		0x9B015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit	*/
 
-#define CFG_EBC_PB1AP		0x02815480
-#define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB1AP		0x02815480
+#define CONFIG_SYS_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
-#define CFG_EBC_PB2AP		0x04815A80
-#define CFG_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2AP		0x04815A80
+#define CONFIG_SYS_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
 
-#define CFG_EBC_PB3AP		0x01815280
-#define CFG_EBC_PB3CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB3AP		0x01815280
+#define CONFIG_SYS_EBC_PB3CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
 
-#define CFG_EBC_PB7AP		0x01815280
-#define CFG_EBC_PB7CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB7AP		0x01815280
+#define CONFIG_SYS_EBC_PB7CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
 
 /*-----------------------------------------------------------------------
  * External peripheral base address
  *-----------------------------------------------------------------------
  */
-#define CFG_KEY_REG_BASE_ADDR	0xF0100000
-#define CFG_IR_REG_BASE_ADDR	0xF0200000
-#define CFG_FPGA_REG_BASE_ADDR	0xF0300000
+#define CONFIG_SYS_KEY_REG_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_IR_REG_BASE_ADDR	0xF0200000
+#define CONFIG_SYS_FPGA_REG_BASE_ADDR	0xF0300000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area
  */
-#define CFG_INIT_DCACHE_CS	4	/* use cs # 4 for data cache memory    */
+#define CONFIG_SYS_INIT_DCACHE_CS	4	/* use cs # 4 for data cache memory    */
 
-#define CFG_INIT_RAM_ADDR	0x40000000  /* inside of SDRAM			   */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* inside of SDRAM			   */
+#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for Serial Presence Detect EEPROM address
diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h
index 2072f6e..d0afd29 100644
--- a/include/configs/wepep250.h
+++ b/include/configs/wepep250.h
@@ -69,22 +69,22 @@
 /*
  * General options for u-boot. Modify to save memory foot print
  */
-#define CFG_LONGHELP                                  /* undef saves memory  */
-#define CFG_PROMPT              "WEP> "               /* prompt string       */
-#define CFG_CBSIZE              256                   /* console I/O buffer  */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size   */
-#define CFG_MAXARGS             16                    /* max command args    */
-#define CFG_BARGSIZE            CFG_CBSIZE            /* boot args buf size  */
+#define CONFIG_SYS_LONGHELP                                  /* undef saves memory  */
+#define CONFIG_SYS_PROMPT              "WEP> "               /* prompt string       */
+#define CONFIG_SYS_CBSIZE              256                   /* console I/O buffer  */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size   */
+#define CONFIG_SYS_MAXARGS             16                    /* max command args    */
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE            /* boot args buf size  */
 
-#define CFG_MEMTEST_START       0xa0400000            /* memtest test area   */
-#define CFG_MEMTEST_END         0xa0800000
+#define CONFIG_SYS_MEMTEST_START       0xa0400000            /* memtest test area   */
+#define CONFIG_SYS_MEMTEST_END         0xa0800000
 
-#undef  CFG_CLKS_IN_HZ                       /* use HZ for freq. display     */
+#undef  CONFIG_SYS_CLKS_IN_HZ                       /* use HZ for freq. display     */
 
-#define CFG_HZ                  3686400      /* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED            0x141        /* core clock - register value  */
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CPUSPEED            0x141        /* core clock - register value  */
 
-#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Definitions related to passing arguments to kernel.
@@ -98,8 +98,8 @@
 /*
  * Malloc pool need to host env + 128 Kb reserve for other allocations.
  */
-#define CFG_MALLOC_LEN	  (CONFIG_ENV_SIZE + (128<<10) )
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN	  (CONFIG_ENV_SIZE + (128<<10) )
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 #define CONFIG_STACKSIZE        (120<<10)      /* stack size */
 
@@ -121,8 +121,8 @@
 #define WEP_SDRAM_4            0xac000000        /* SDRAM bank #4           */
 #define WEP_SDRAM_4_SIZE       0x00000000        /* 0 MB                    */
 
-#define CFG_DRAM_BASE           0xa0000000
-#define CFG_DRAM_SIZE           0x02000000
+#define CONFIG_SYS_DRAM_BASE           0xa0000000
+#define CONFIG_SYS_DRAM_SIZE           0x02000000
 
 /* Uncomment used SDRAM chip */
 #define WEP_SDRAM_K4S281633
@@ -132,8 +132,8 @@
 /*
  * Configuration for FLASH memory
  */
-#define CFG_MAX_FLASH_BANKS	1	/* FLASH banks count (not chip count)*/
-#define CFG_MAX_FLASH_SECT	128	/* number of sector in FLASH bank    */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* FLASH banks count (not chip count)*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* number of sector in FLASH bank    */
 #define WEP_FLASH_BUS_WIDTH	4	/* we use 32 bit FLASH memory...     */
 #define WEP_FLASH_INTERLEAVE	2	/* ... made of 2 chips */
 #define WEP_FLASH_BANK_SIZE  0x2000000  /* size of one flash bank*/
@@ -146,12 +146,12 @@
    is not so clear to me. In other words we can provide more informations
    to user, but this expects more complex flash handling we do not provide
    now.*/
-#undef  CFG_FLASH_CFI
+#undef  CONFIG_SYS_FLASH_CFI
 
-#define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ)    /* timeout for Erase operation */
-#define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ)    /* timeout for Write operation */
+#define CONFIG_SYS_FLASH_ERASE_TOUT    (2*CONFIG_SYS_HZ)    /* timeout for Erase operation */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    (2*CONFIG_SYS_HZ)    /* timeout for Write operation */
 
-#define CFG_FLASH_BASE          WEP_FLASH_BASE
+#define CONFIG_SYS_FLASH_BASE          WEP_FLASH_BASE
 
 /*
  * This is setting for JFFS2 support in u-boot.
@@ -160,9 +160,9 @@
  * footprint.
  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
  */
-#define CFG_JFFS2_FIRST_BANK		0
-#define CFG_JFFS2_FIRST_SECTOR		5
-#define CFG_JFFS2_NUM_BANKS		1
+#define CONFIG_SYS_JFFS2_FIRST_BANK		0
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR		5
+#define CONFIG_SYS_JFFS2_NUM_BANKS		1
 
 /*
  * Environment setup. Definitions of monitor location and size with
@@ -176,8 +176,8 @@
  * env. has no sense to us.
  */
 
-#define CFG_MONITOR_BASE	PHYS_FLASH_1
-#define CFG_MONITOR_LEN		0x20000		/* 128kb ( 1 flash sector )  */
+#define CONFIG_SYS_MONITOR_BASE	PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_LEN		0x20000		/* 128kb ( 1 flash sector )  */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		0x20000	        /* absolute address for now  */
 #define CONFIG_ENV_SIZE		0x2000
@@ -189,6 +189,6 @@
  * one may expect. For instance loadb command do not cares :-)
  * So advice is - do not relay on this...
  */
-#define CFG_LOAD_ADDR        0x40000
+#define CONFIG_SYS_LOAD_ADDR        0x40000
 
 #endif  /* __CONFIG_H */
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
index ec73224..250247c 100644
--- a/include/configs/xaeniax.h
+++ b/include/configs/xaeniax.h
@@ -62,7 +62,7 @@
 
 #define CONFIG_BAUDRATE		115200
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */
 
 
 /*
@@ -109,37 +109,37 @@
  * Size of malloc() pool; this lives below the uppermost 128 KiB which are
  * used for the RAM copy of the uboot code
  */
-#define CFG_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory	*/
-#define CFG_HUSH_PARSER		1
+#define CONFIG_SYS_LONGHELP				/* undef to save memory	*/
+#define CONFIG_SYS_HUSH_PARSER		1
 
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT		"u-boot$ "	/* Monitor Command Prompt */
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"u-boot$ "	/* Monitor Command Prompt */
 #else
-#define CFG_PROMPT		"u-boot=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT		"u-boot=> "	/* Monitor Command Prompt */
 #endif
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_DEVICE_NULLDEV	1
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1
 
-#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
 
-#undef	CFG_CLKS_IN_HZ				/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ				/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR		0xa1000000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0xa1000000	/* default load address */
 
-#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x141		/* set core clock to 400/200/100 MHz */
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CPUSPEED		0x141		/* set core clock to 400/200/100 MHz */
 
 /*
  * Physical Memory Map
@@ -160,20 +160,20 @@
 #define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
 #define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
 
-#define CFG_DRAM_BASE		0xa0000000
-#define CFG_DRAM_SIZE		0x04000000
+#define CONFIG_SYS_DRAM_BASE		0xa0000000
+#define CONFIG_SYS_DRAM_SIZE		0x04000000
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1    /* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1    /* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 
 /* FIXME */
 #define CONFIG_ENV_IS_IN_FLASH	1
@@ -235,9 +235,9 @@
  * GP82 == NSSPSFRM  is 1
  * GP83 == NSSPTXD   is 1
  */
-#define CFG_GPSR0_VAL		0x8320E420
-#define CFG_GPSR1_VAL		0x00FFAA82
-#define CFG_GPSR2_VAL		0x000DC000
+#define CONFIG_SYS_GPSR0_VAL		0x8320E420
+#define CONFIG_SYS_GPSR1_VAL		0x00FFAA82
+#define CONFIG_SYS_GPSR2_VAL		0x000DC000
 
 /*
  * GP03 == LANReset  is 0
@@ -250,9 +250,9 @@
  * GP30 == SDATA_OUT is 0
  * GP81 == NSSPCLK   is 0
  */
-#define CFG_GPCR0_VAL		0x40C31848
-#define CFG_GPCR1_VAL		0x00000000
-#define CFG_GPCR2_VAL		0x00020000
+#define CONFIG_SYS_GPCR0_VAL		0x40C31848
+#define CONFIG_SYS_GPCR1_VAL		0x00000000
+#define CONFIG_SYS_GPCR2_VAL		0x00020000
 
 /*
  * GP00 == CPUWakeUpUSB is input
@@ -340,9 +340,9 @@
  * GP83 == NSSPTXD   is output
  * GP84 == NSSPRXD   is input
  */
-#define CFG_GPDR0_VAL		0xD3E3FC68
-#define CFG_GPDR1_VAL		0xFCFFAB83
-#define CFG_GPDR2_VAL		0x000FFFFF
+#define CONFIG_SYS_GPDR0_VAL		0xD3E3FC68
+#define CONFIG_SYS_GPDR1_VAL		0xFCFFAB83
+#define CONFIG_SYS_GPDR2_VAL		0x000FFFFF
 
 /*
  * GP01 == GP reset is AF01
@@ -413,12 +413,12 @@
  * GP83 == NSSPTXD  is AF01
  * GP84 == NSSPRXD  is AF10
  */
-#define CFG_GAFR0_L_VAL		0x80000004
-#define CFG_GAFR0_U_VAL		0x595A801A
-#define CFG_GAFR1_L_VAL		0x699A9559
-#define CFG_GAFR1_U_VAL		0xAAA5AAAA
-#define CFG_GAFR2_L_VAL		0xAAAAAAAA
-#define CFG_GAFR2_U_VAL		0x00000256
+#define CONFIG_SYS_GAFR0_L_VAL		0x80000004
+#define CONFIG_SYS_GAFR0_U_VAL		0x595A801A
+#define CONFIG_SYS_GAFR1_L_VAL		0x699A9559
+#define CONFIG_SYS_GAFR1_U_VAL		0xAAA5AAAA
+#define CONFIG_SYS_GAFR2_L_VAL		0xAAAAAAAA
+#define CONFIG_SYS_GAFR2_U_VAL		0x00000256
 
 /*
  * clock settings
@@ -429,10 +429,10 @@
  * BFS = 0
  * SSS = 0
  */
-#define CFG_PSSR_VAL		0x00000030
+#define CONFIG_SYS_PSSR_VAL		0x00000030
 
-#define CFG_CKEN_VAL            0x00000080  /*  */
-#define CFG_ICMR_VAL            0x00000000  /* No interrupts enabled        */
+#define CONFIG_SYS_CKEN_VAL            0x00000080  /*  */
+#define CONFIG_SYS_ICMR_VAL            0x00000000  /* No interrupts enabled        */
 
 
 /*
@@ -454,7 +454,7 @@
  * [03]    0    - 32 Bit bus width
  * [02:00] 010  - burst OF 4 ROM or FLASH
 */
-#define CFG_MSC0_VAL		0x000023D2
+#define CONFIG_SYS_MSC0_VAL		0x000023D2
 
 /* This is the configuration for nCS2/3 -> USB controller, LAN
  * configuration for nCS3: LAN
@@ -472,7 +472,7 @@
  * [03]    1    - 16 Bit bus width
  * [02:00] 100  - variable latency I/O
  */
-#define CFG_MSC1_VAL		0x1224A26C
+#define CONFIG_SYS_MSC1_VAL		0x1224A26C
 
 /* This is the configuration for nCS4/5 -> LAN
  * configuration for nCS5:
@@ -490,7 +490,7 @@
  * [03]    0    - 32 Bit bus width
  * [02:00] 100  - variable latency I/O
  */
-#define CFG_MSC2_VAL		0x00001224
+#define CONFIG_SYS_MSC2_VAL		0x00001224
 
 /* MDCNFG: SDRAM Configuration Register
  *
@@ -518,7 +518,7 @@
  * [00]      1   - enable  SDRAM partition 0
  */
 /* use the configuration above but disable partition 0 */
-#define CFG_MDCNFG_VAL		0x00000AC9
+#define CONFIG_SYS_MDCNFG_VAL		0x00000AC9
 
 /* MDREFR: SDRAM Refresh Control Register
  *
@@ -539,7 +539,7 @@
  * [12]    0     - E0PIN: disable SDCKE0
  * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
  */
-#define CFG_MDREFR_VAL		0x00138018 /* mh: was 0x00118018 */
+#define CONFIG_SYS_MDREFR_VAL		0x00138018 /* mh: was 0x00118018 */
 
 /* MDMRS: Mode Register Set Configuration Register
  *
@@ -554,18 +554,18 @@
  * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
  * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
  */
-#define CFG_MDMRS_VAL		0x00320032
+#define CONFIG_SYS_MDMRS_VAL		0x00320032
 
 /*
  * PCMCIA and CF Interfaces
  */
-#define CFG_MECR_VAL		0x00000000
-#define CFG_MCMEM0_VAL		0x00010504
-#define CFG_MCMEM1_VAL		0x00010504
-#define CFG_MCATT0_VAL		0x00010504
-#define CFG_MCATT1_VAL		0x00010504
-#define CFG_MCIO0_VAL		0x00004715
-#define CFG_MCIO1_VAL		0x00004715
+#define CONFIG_SYS_MECR_VAL		0x00000000
+#define CONFIG_SYS_MCMEM0_VAL		0x00010504
+#define CONFIG_SYS_MCMEM1_VAL		0x00010504
+#define CONFIG_SYS_MCATT0_VAL		0x00010504
+#define CONFIG_SYS_MCATT1_VAL		0x00010504
+#define CONFIG_SYS_MCIO0_VAL		0x00004715
+#define CONFIG_SYS_MCIO1_VAL		0x00004715
 
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h
new file mode 100644
index 0000000..e7daa07
--- /dev/null
+++ b/include/configs/xilinx-ppc.h
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2008
+ *  Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ *  This work has been supported by: QTechnology  http://qtec.com/
+ *
+ *  (C) Copyright 2008
+ *  Georg Schardt <schardt@team-ctech.de>
+ *
+ *  This program is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef __CONFIG_XLX_H
+#define __CONFIG_XLX_H
+/*
+#define DEBUG
+#define ET_DEBUG
+*/
+
+/*Mem Map*/
+#define CONFIG_SYS_SDRAM_BASE		0x0
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+
+/*Cmd*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_REGINFO
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_JFFS2_CMDLINE
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_PING
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_IMLS
+
+/*Misc*/
+#define CONFIG_BOOTDELAY		5/* autoboot after 5 seconds     */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory         */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024/* Console I/O Buffer Size      */
+#else
+#define CONFIG_SYS_CBSIZE		256/* Console I/O Buffer Size      */
+#endif
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +\
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+					/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+					/* Boot Argument Buffer Size */
+#define CONFIG_SYS_MEMTEST_START	0x00400000
+					/* memtest works on           */
+#define CONFIG_SYS_MEMTEST_END		0x00C00000
+					/* 4 ... 12 MB in DRAM        */
+#define CONFIG_SYS_LOAD_ADDR		0x00400000
+					/* default load address       */
+#define CONFIG_SYS_EXTBDINFO		1
+					/* Extended board_into (bd_t) */
+#define CONFIG_SYS_HZ			1000
+					/* decrementer freq: 1 ms ticks */
+#define CONFIG_CMDLINE_EDITING		/* add command line history     */
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
+#define CONFIG_LOOPW			/* enable loopw command         */
+#define CONFIG_MX_CYCLIC		/* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE		/* include version env variable */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
+#define CONFIG_SYS_HUSH_PARSER		/* Use the HUSH parser          */
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_LOADS_ECHO		/* echo on for serial download  */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change        */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+				/* Initial Memory map for Linux */
+
+/*Stack*/
+#define CONFIG_SYS_INIT_RAM_ADDR	0x800000/* Initial RAM address    */
+#define CONFIG_SYS_INIT_RAM_END		0x2000	/* End of used area in RAM  */
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data   */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END \
+				- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+/*Speed*/
+#define CONFIG_SYS_CLK_FREQ	XPAR_CORE_CLOCK_FREQ_HZ
+
+/*Flash*/
+#ifdef XPAR_FLASH_MEM0_BASEADDR
+#define	CONFIG_SYS_FLASH_BASE		XPAR_FLASH_MEM0_BASEADDR
+#define	CONFIG_SYS_FLASH_CFI		1
+#define	CONFIG_FLASH_CFI_DRIVER	1
+#define	CONFIG_SYS_FLASH_EMPTY_INFO	1
+#define	CONFIG_SYS_MAX_FLASH_BANKS	1
+#define	CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_CMDLINE
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+/* serial communication */
+#ifdef XPAR_UARTLITE_0_BASEADDR
+#define CONFIG_XILINX_UARTLITE
+#define CONFIG_SERIAL_BASE		XPAR_UARTLITE_0_BASEADDR
+#define CONFIG_BAUDRATE			XPAR_UARTLITE_0_BAUDRATE
+#define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
+#else
+#ifdef XPAR_UARTNS550_0_BASEADDR
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	4
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550_COM1		XPAR_UARTNS550_0_BASEADDR
+#define CONFIG_SYS_NS16550_CLK		XPAR_UARTNS550_0_CLOCK_FREQ_HZ
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 115200 }
+#endif
+#endif
+
+#endif						/* __CONFIG_H */
diff --git a/include/configs/xilinx-ppc405-generic.h b/include/configs/xilinx-ppc405-generic.h
new file mode 100644
index 0000000..5036c62
--- /dev/null
+++ b/include/configs/xilinx-ppc405-generic.h
@@ -0,0 +1,58 @@
+/*
+ *
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ *
+ * (C) Copyright 2008
+ * Georg Schardt <schardt@team-ctech.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_GEN_H
+#define __CONFIG_GEN_H
+
+#include "../board/xilinx/ppc405-generic/xparameters.h"
+
+/* sdram */
+#define CONFIG_SYS_SDRAM_SIZE_MB	256
+
+/* environment */
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_SIZE			0x10000
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#define CONFIG_SYS_ENV_OFFSET		0x3F0000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET)
+#define CONFIG_ENV_OVERWRITE		1
+
+/*Misc*/
+#define CONFIG_SYS_PROMPT	"xlx-ppc405:/# " /* Monitor Command Prompt */
+#define CONFIG_PREBOOT		"echo U-Boot is up and runnining;"
+
+/*Flash*/
+#define CONFIG_SYS_FLASH_BASE			XPAR_FLASH_MEM0_BASEADDR
+#define CONFIG_SYS_FLASH_SIZE		(32*1024*1024)
+#define CONFIG_SYS_MAX_FLASH_SECT	71
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1
+#define MTDIDS_DEFAULT			"nor0=ppc405-flash"
+#define MTDPARTS_DEFAULT		"mtdpartsa=ppc405-flash:-(user)"
+
+#include <configs/xilinx-ppc405.h>
+#endif			/* __CONFIG_H */
diff --git a/include/configs/xilinx-ppc405.h b/include/configs/xilinx-ppc405.h
new file mode 100644
index 0000000..d335f1e
--- /dev/null
+++ b/include/configs/xilinx-ppc405.h
@@ -0,0 +1,39 @@
+/*
+ *
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ *
+ * (C) Copyright 2008
+ * Georg Schardt <schardt@team-ctech.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* cpu parameter */
+#define CONFIG_405		1
+#define CONFIG_4xx		1
+#define CONFIG_XILINX_405	1
+
+#include <configs/xilinx-ppc.h>
+
+#endif
diff --git a/include/configs/xilinx-ppc440-generic.h b/include/configs/xilinx-ppc440-generic.h
index e968651..fc0f932 100644
--- a/include/configs/xilinx-ppc440-generic.h
+++ b/include/configs/xilinx-ppc440-generic.h
@@ -24,7 +24,7 @@
 #include "../board/xilinx/ppc440-generic/xparameters.h"
 
 /*Mem Map*/
-#define CFG_SDRAM_SIZE_MB	256
+#define CONFIG_SYS_SDRAM_SIZE_MB	256
 
 /*Env*/
 #define	CONFIG_ENV_IS_IN_FLASH	1
@@ -34,12 +34,12 @@
 #define CONFIG_ENV_ADDR		(XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
 
 /*Misc*/
-#define CFG_PROMPT		"board:/# "	/* Monitor Command Prompt    */
+#define CONFIG_SYS_PROMPT		"board:/# "	/* Monitor Command Prompt    */
 #define CONFIG_PREBOOT		"echo U-Boot is up and runnining;"
 
 /*Flash*/
-#define	CFG_FLASH_SIZE		(32*1024*1024)
-#define	CFG_MAX_FLASH_SECT	259
+#define	CONFIG_SYS_FLASH_SIZE		(32*1024*1024)
+#define	CONFIG_SYS_MAX_FLASH_SECT	259
 #define MTDIDS_DEFAULT		"nor0=ml507-flash"
 #define MTDPARTS_DEFAULT	"mtdparts=ml507-flash:-(user)"
 
diff --git a/include/configs/xilinx-ppc440.h b/include/configs/xilinx-ppc440.h
index 6c7abb2..6e938dc 100644
--- a/include/configs/xilinx-ppc440.h
+++ b/include/configs/xilinx-ppc440.h
@@ -17,90 +17,12 @@
 
 #ifndef __CONFIG_GEN_H
 #define __CONFIG_GEN_H
-/*
-#define DEBUG
-#define ET_DEBUG
-*/
- /*CPU*/
-#define CONFIG_XILINX_440	1
-#define CONFIG_440		1
-#define CONFIG_4xx		1
-
-/*Mem Map*/
-#define CFG_SDRAM_BASE		0x0
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(192 * 1024)
-#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
 
-/*Uart*/
-#define CONFIG_XILINX_UARTLITE
-#define CONFIG_BAUDRATE		XPAR_UARTLITE_0_BAUDRATE
-#define CFG_BAUDRATE_TABLE	{ XPAR_UARTLITE_0_BAUDRATE }
-#define CONFIG_SERIAL_BASE	XPAR_UARTLITE_0_BASEADDR
-
-/*Cmd*/
-#include <config_cmd_default.h>
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_JFFS2
-#define CONFIG_JFFS2_CMDLINE
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_I2C
-#undef CONFIG_CMD_DTT
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_PING
-#undef CONFIG_CMD_DHCP
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_IMLS
-
-/*Misc*/
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds     */
-#define CFG_LONGHELP			/* undef to save memory         */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size      */
-#else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size      */
-#endif
-#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS		16	/* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on           */
-#define CFG_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM        */
-#define CFG_LOAD_ADDR		0x00400000	/* default load address       */
-#define CFG_EXTBDINFO		1	/* Extended board_into (bd_t) */
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
-#define CONFIG_CMDLINE_EDITING		/* add command line history     */
-#define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
-#define CONFIG_LOOPW			/* enable loopw command         */
-#define CONFIG_MX_CYCLIC		/* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE		/* include version env variable */
-#define CFG_CONSOLE_INFO_QUIET		/* don't print console @ startup */
-#define CFG_HUSH_PARSER			/* Use the HUSH parser          */
-#define	CFG_PROMPT_HUSH_PS2	"> "
-#define CONFIG_LOADS_ECHO		/* echo on for serial download  */
-#define CFG_LOADS_BAUD_CHANGE		/* allow baudrate change        */
-#define CFG_BOOTMAPSZ		(8 << 20)/* Initial Memory map for Linux */
-
-/*Stack*/
-#define CFG_INIT_RAM_ADDR	0x800000	/* Initial RAM address    */
-#define CFG_INIT_RAM_END	0x2000		/* End of used area in RAM  */
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data   */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-/*Speed*/
-#define CONFIG_SYS_CLK_FREQ	XPAR_CORE_CLOCK_FREQ_HZ
+/*CPU*/
+#define CONFIG_4xx		1
+#define CONFIG_440		1
+#define CONFIG_XILINX_440	1
 
-/*Flash*/
-#define	CFG_FLASH_BASE		XPAR_FLASH_MEM0_BASEADDR
-#define	CFG_FLASH_CFI		1
-#define	CONFIG_FLASH_CFI_DRIVER	1
-#define	CFG_FLASH_EMPTY_INFO	1
-#define	CFG_MAX_FLASH_BANKS	1
-#define	CFG_FLASH_PROTECTION
+#include <configs/xilinx-ppc.h>
 
 #endif						/* __CONFIG_H */
diff --git a/include/configs/xm250.h b/include/configs/xm250.h
index aac03a1..8e9d5ab 100644
--- a/include/configs/xm250.h
+++ b/include/configs/xm250.h
@@ -41,8 +41,8 @@
  * used for the RAM copy of the uboot code
  *
  */
-#define CFG_MALLOC_LEN		(256*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(256*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -58,18 +58,18 @@
  * I2C bus
  */
 #define CONFIG_HARD_I2C			1
-#define CFG_I2C_SPEED			50000
-#define CFG_I2C_SLAVE			0xfe
+#define CONFIG_SYS_I2C_SPEED			50000
+#define CONFIG_SYS_I2C_SLAVE			0xfe
 
 #define CONFIG_RTC_PCF8563		1
-#define CFG_I2C_RTC_ADDR		0x51
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
 
-#define CFG_I2C_EEPROM_ADDR		0x58	/* A0 = 0 (hardwired)		*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	4	/* 4 bits = 16 octets		*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* between stop and start	*/
-#define CFG_I2C_EEPROM_ADDR_LEN		1	/* length of address		*/
-#define CFG_EEPROM_SIZE			2048	/* size in bytes		*/
-#undef	CFG_I2C_INIT_BOARD			/* board has no own init	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58	/* A0 = 0 (hardwired)		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4	/* 4 bits = 16 octets		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* between stop and start	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1	/* length of address		*/
+#define CONFIG_SYS_EEPROM_SIZE			2048	/* size in bytes		*/
+#undef	CONFIG_SYS_I2C_INIT_BOARD			/* board has no own init	*/
 
 /*
  * select serial console configuration
@@ -107,26 +107,26 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0xa0400000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM		*/
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR		0xa3000000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0xa3000000	/* default load address */
 
-#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x161		/* set core clock to 400/400/100 MHz */
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CPUSPEED		0x161		/* set core clock to 400/400/100 MHz */
 
 						/* valid baudrates */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Definitions related to passing arguments to kernel.
@@ -166,29 +166,29 @@
 #define PHYS_FLASH_BANK_SIZE	0x01000000 /* 16 MB Banks	*/
 #define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
 
-#define CFG_DRAM_BASE		0xa0000000
-#define CFG_DRAM_SIZE		0x04000000
+#define CONFIG_SYS_DRAM_BASE		0xa0000000
+#define CONFIG_SYS_DRAM_SIZE		0x04000000
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1     /* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128   /* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1     /* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128   /* max number of sectors on one chip	*/
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Erase	*/
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Write	*/
-#define CFG_FLASH_LOCK_TOUT	(2*CFG_HZ)	/* Timeout for Flash Set Lock Bit */
-#define CFG_FLASH_UNLOCK_TOUT	(2*CFG_HZ)	/* Timeout for Flash Clear Lock Bits */
-#define CFG_FLASH_PROTECTION			/* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Erase	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Write	*/
+#define CONFIG_SYS_FLASH_LOCK_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Set Lock Bit */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Clear Lock Bits */
+#define CONFIG_SYS_FLASH_PROTECTION			/* "Real" (hardware) sectors protection */
 
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x40000)	/* Addr of Environment Sector	*/
 #define CONFIG_ENV_SIZE		0x4000
 #define CONFIG_ENV_SECT_SIZE	0x40000				/* Size of the Environment Sector	*/
-#define CFG_MONITOR_LEN		0x20000				/* 128 KiB */
+#define CONFIG_SYS_MONITOR_LEN		0x20000				/* 128 KiB */
 
 /******************************************************************************
  *
@@ -287,38 +287,38 @@
  *
  */
 /* Pin direction control */
-#define CFG_GPDR0_VAL	    0xd3808000
-#define CFG_GPDR1_VAL	    0xfcffab83
-#define CFG_GPDR2_VAL	    0x0001ffff
+#define CONFIG_SYS_GPDR0_VAL	    0xd3808000
+#define CONFIG_SYS_GPDR1_VAL	    0xfcffab83
+#define CONFIG_SYS_GPDR2_VAL	    0x0001ffff
 /* Set and Clear registers */
-#define CFG_GPSR0_VAL	    0x00008000
-#define CFG_GPSR1_VAL	    0x00ff0002
-#define CFG_GPSR2_VAL	    0x0001c000
-#define CFG_GPCR0_VAL	    0x00000000
-#define CFG_GPCR1_VAL	    0x00000000
-#define CFG_GPCR2_VAL	    0x00000000
+#define CONFIG_SYS_GPSR0_VAL	    0x00008000
+#define CONFIG_SYS_GPSR1_VAL	    0x00ff0002
+#define CONFIG_SYS_GPSR2_VAL	    0x0001c000
+#define CONFIG_SYS_GPCR0_VAL	    0x00000000
+#define CONFIG_SYS_GPCR1_VAL	    0x00000000
+#define CONFIG_SYS_GPCR2_VAL	    0x00000000
 /* Edge detect registers (these are set by the kernel) */
-#define CFG_GRER0_VAL	    0x00002180
-#define CFG_GRER1_VAL	    0x00000000
-#define CFG_GRER2_VAL	    0x00000000
-#define CFG_GFER0_VAL	    0x000043e0
-#define CFG_GFER1_VAL	    0x00000000
-#define CFG_GFER2_VAL	    0x00000000
+#define CONFIG_SYS_GRER0_VAL	    0x00002180
+#define CONFIG_SYS_GRER1_VAL	    0x00000000
+#define CONFIG_SYS_GRER2_VAL	    0x00000000
+#define CONFIG_SYS_GFER0_VAL	    0x000043e0
+#define CONFIG_SYS_GFER1_VAL	    0x00000000
+#define CONFIG_SYS_GFER2_VAL	    0x00000000
 /* Alternate function registers */
-#define CFG_GAFR0_L_VAL	    0x80000004
-#define CFG_GAFR0_U_VAL	    0x595a8010
-#define CFG_GAFR1_L_VAL	    0x699a9559
-#define CFG_GAFR1_U_VAL	    0xaaa5aaaa
-#define CFG_GAFR2_L_VAL	    0xaaaaaaaa
-#define CFG_GAFR2_U_VAL	    0x00000002
+#define CONFIG_SYS_GAFR0_L_VAL	    0x80000004
+#define CONFIG_SYS_GAFR0_U_VAL	    0x595a8010
+#define CONFIG_SYS_GAFR1_L_VAL	    0x699a9559
+#define CONFIG_SYS_GAFR1_U_VAL	    0xaaa5aaaa
+#define CONFIG_SYS_GAFR2_L_VAL	    0xaaaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL	    0x00000002
 
 /*
  * Clocks, power control and interrupts
  */
-#define CFG_PSSR_VAL	    0x00000030
-#define CFG_CCCR_VAL	    0x00000161	/* 100 MHz memory, 400 MHz CPU, 400 Turbo  */
-#define CFG_CKEN_VAL	    0x000141ec	/* FFUART and STUART enabled	*/
-#define CFG_ICMR_VAL	    0x00000000	/* No interrupts enabled	*/
+#define CONFIG_SYS_PSSR_VAL	    0x00000030
+#define CONFIG_SYS_CCCR_VAL	    0x00000161	/* 100 MHz memory, 400 MHz CPU, 400 Turbo  */
+#define CONFIG_SYS_CKEN_VAL	    0x000141ec	/* FFUART and STUART enabled	*/
+#define CONFIG_SYS_ICMR_VAL	    0x00000000	/* No interrupts enabled	*/
 
 /* FIXME
  *
@@ -331,23 +331,23 @@
  * Memory settings
  *
  */
-#define CFG_MSC0_VAL	    0x122423f0	/* FLASH   / LAN	    (cs0)/(cS1)	  */
-#define CFG_MSC1_VAL	    0x35f4aa4c	/* USB	   / ST3+ST5	    (cs2)/(cS3)	  */
-#define CFG_MSC2_VAL	    0x35f435fc	/* IDE	   / BCR + WatchDog (cs4)/(cS5)	  */
-#define CFG_MDCNFG_VAL	    0x000009c9
-#define CFG_MDMRS_VAL	    0x00220022
-#define CFG_MDREFR_VAL	    0x000da018	/* Initial setting, individual bits set in lowlevel_init.S */
+#define CONFIG_SYS_MSC0_VAL	    0x122423f0	/* FLASH   / LAN	    (cs0)/(cS1)	  */
+#define CONFIG_SYS_MSC1_VAL	    0x35f4aa4c	/* USB	   / ST3+ST5	    (cs2)/(cS3)	  */
+#define CONFIG_SYS_MSC2_VAL	    0x35f435fc	/* IDE	   / BCR + WatchDog (cs4)/(cS5)	  */
+#define CONFIG_SYS_MDCNFG_VAL	    0x000009c9
+#define CONFIG_SYS_MDMRS_VAL	    0x00220022
+#define CONFIG_SYS_MDREFR_VAL	    0x000da018	/* Initial setting, individual bits set in lowlevel_init.S */
 
 /*
  * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
  */
-#define CFG_MECR_VAL	      0x00000000
-#define CFG_MCMEM0_VAL	      0x00010504
-#define CFG_MCMEM1_VAL	      0x00010504
-#define CFG_MCATT0_VAL	      0x00010504
-#define CFG_MCATT1_VAL	      0x00010504
-#define CFG_MCIO0_VAL	      0x00004715
-#define CFG_MCIO1_VAL	      0x00004715
+#define CONFIG_SYS_MECR_VAL	      0x00000000
+#define CONFIG_SYS_MCMEM0_VAL	      0x00010504
+#define CONFIG_SYS_MCMEM1_VAL	      0x00010504
+#define CONFIG_SYS_MCATT0_VAL	      0x00010504
+#define CONFIG_SYS_MCATT1_VAL	      0x00010504
+#define CONFIG_SYS_MCIO0_VAL	      0x00004715
+#define CONFIG_SYS_MCIO1_VAL	      0x00004715
 
 /* Board specific defines */
 
diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h
index 443392f..6761438 100644
--- a/include/configs/xsengine.h
+++ b/include/configs/xsengine.h
@@ -35,11 +35,8 @@
 #define CONFIG_DOS_PARTITION		1
 #define BOARD_LATE_INIT			1
 #undef  CONFIG_USE_IRQ					/* we don't need IRQ/FIQ stuff */
-#define CFG_HZ				3686400		/* incrementer freq: 3.6864 MHz */
-
-#undef  CONFIG_USE_IRQ					/* we don't need IRQ/FIQ stuff */
-#define CFG_HZ				3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED			0x161           /* set core clock to 400/200/100 MHz */
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CPUSPEED			0x161           /* set core clock to 400/200/100 MHz */
 
 #define CONFIG_NR_DRAM_BANKS		1		/* we have 1 bank of DRAM */
 #define PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
@@ -50,16 +47,16 @@
 #define PHYS_SDRAM_3_SIZE		0x00000000	/* 0 MB */
 #define PHYS_SDRAM_4			0xac000000	/* SDRAM Bank #4 */
 #define PHYS_SDRAM_4_SIZE		0x00000000	/* 0 MB */
-#define CFG_DRAM_BASE			0xa0000000
-#define CFG_DRAM_SIZE			0x04000000
+#define CONFIG_SYS_DRAM_BASE			0xa0000000
+#define CONFIG_SYS_DRAM_SIZE			0x04000000
 
 /* FLASH organization */
-#define CFG_MAX_FLASH_BANKS		1		/* max number of memory banks           */
-#define CFG_MAX_FLASH_SECT		128		/* max number of sectors on one chip    */
+#define CONFIG_SYS_MAX_FLASH_BANKS		1		/* max number of memory banks           */
+#define CONFIG_SYS_MAX_FLASH_SECT		128		/* max number of sectors on one chip    */
 #define PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
 #define PHYS_FLASH_2			0x00000000	/* Flash Bank #2 */
 #define PHYS_FLASH_SECT_SIZE		0x00020000	/* 127 KB sectors */
-#define CFG_FLASH_BASE			PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
 
 /*
  * JFFS2 partitions
@@ -86,12 +83,12 @@
 #define CONFIG_ENV_SIZE                    0x4000				/* 16kB Total Size of Environment Sector */
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT		(75*CFG_HZ)	/* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT		(50*CFG_HZ)	/* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT		(75*CONFIG_SYS_HZ)	/* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT		(50*CONFIG_SYS_HZ)	/* Timeout for Flash Write */
 
 /* Size of malloc() pool */
-#define CFG_MALLOC_LEN			(CONFIG_ENV_SIZE + 256*1024)
-#define CFG_GBL_DATA_SIZE		128		/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 256*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE		128		/* size in bytes reserved for initial data */
 
 /* Hardware drivers */
 #define CONFIG_DRIVER_SMC91111
@@ -118,7 +115,6 @@
  */
 #include <config_cmd_default.h>
 
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_JFFS2
@@ -133,20 +129,25 @@
 #define CONFIG_CMDLINE_TAG
 
 /* Miscellaneous configurable options */
-#define CFG_HUSH_PARSER			1
-#define CFG_PROMPT_HUSH_PS2		"> "
-#define CFG_LONGHELP								/* undef to save memory	*/
-#define CFG_PROMPT			"XS-Engine u-boot> "			/* Monitor Command Prompt */
-#define CFG_CBSIZE			256					/* Console I/O Buffer Size */
-#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS			16					/* max number of command args */
-#define CFG_BARGSIZE			CFG_CBSIZE				/* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START		0xA0400000				/* memtest works on     */
-#define CFG_MEMTEST_END			0xA0800000				/* 4 ... 8 MB in DRAM   */
-#undef  CFG_CLKS_IN_HZ								/* everything, incl board info, in Hz */
-#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }	/* valid baudrates */
-#define CFG_MMC_BASE			0xF0000000
-#define CFG_LOAD_ADDR			0xA0000000				/* load kernel to this address   */
+#define CONFIG_SYS_HUSH_PARSER			1
+#define CONFIG_SYS_PROMPT_HUSH_PS2		"> "
+#define CONFIG_SYS_LONGHELP								/* undef to save memory	*/
+#define CONFIG_SYS_PROMPT			"XS-Engine u-boot> "			/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE			256					/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS			16					/* max number of command args */
+#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE				/* Boot Argument Buffer Size */
+#define CONFIG_SYS_MEMTEST_START		0xA0400000				/* memtest works on     */
+#define CONFIG_SYS_MEMTEST_END			0xA0800000				/* 4 ... 8 MB in DRAM   */
+#undef  CONFIG_SYS_CLKS_IN_HZ								/* everything, incl board info, in Hz */
+#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }	/* valid baudrates */
+#define CONFIG_SYS_LOAD_ADDR			0xA0000000				/* load kernel to this address   */
+
+#ifdef CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_SYS_MMC_BASE			0xF0000000
+#endif
 
 /* Stack sizes - The stack sizes are set up in start.S using the settings below */
 #define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
@@ -156,53 +157,53 @@
 #endif
 
 /* GP set register */
-#define CFG_GPSR0_VAL			0x0000A000	/* CS1, PROG(FPGA) */
-#define CFG_GPSR1_VAL			0x00020000	/* nPWE */
-#define CFG_GPSR2_VAL			0x0000C000	/* CS2, CS3 */
+#define CONFIG_SYS_GPSR0_VAL			0x0000A000	/* CS1, PROG(FPGA) */
+#define CONFIG_SYS_GPSR1_VAL			0x00020000	/* nPWE */
+#define CONFIG_SYS_GPSR2_VAL			0x0000C000	/* CS2, CS3 */
 
 /* GP clear register */
-#define CFG_GPCR0_VAL			0x00000000
-#define CFG_GPCR1_VAL			0x00000000
-#define CFG_GPCR2_VAL			0x00000000
+#define CONFIG_SYS_GPCR0_VAL			0x00000000
+#define CONFIG_SYS_GPCR1_VAL			0x00000000
+#define CONFIG_SYS_GPCR2_VAL			0x00000000
 
 /* GP direction register */
-#define CFG_GPDR0_VAL			0x0000A000	/* CS1, PROG(FPGA) */
-#define CFG_GPDR1_VAL			0x00022A80	/* nPWE, FFUART + BTUART pins */
-#define CFG_GPDR2_VAL			0x0000C000	/* CS2, CS3 */
+#define CONFIG_SYS_GPDR0_VAL			0x0000A000	/* CS1, PROG(FPGA) */
+#define CONFIG_SYS_GPDR1_VAL			0x00022A80	/* nPWE, FFUART + BTUART pins */
+#define CONFIG_SYS_GPDR2_VAL			0x0000C000	/* CS2, CS3 */
 
 /* GP rising edge detect register */
-#define CFG_GRER0_VAL			0x00000000
-#define CFG_GRER1_VAL			0x00000000
-#define CFG_GRER2_VAL			0x00000000
+#define CONFIG_SYS_GRER0_VAL			0x00000000
+#define CONFIG_SYS_GRER1_VAL			0x00000000
+#define CONFIG_SYS_GRER2_VAL			0x00000000
 
 /* GP falling edge detect register */
-#define CFG_GFER0_VAL			0x00000000
-#define CFG_GFER1_VAL			0x00000000
-#define CFG_GFER2_VAL			0x00000000
+#define CONFIG_SYS_GFER0_VAL			0x00000000
+#define CONFIG_SYS_GFER1_VAL			0x00000000
+#define CONFIG_SYS_GFER2_VAL			0x00000000
 
 /* GP alternate function register */
-#define CFG_GAFR0_L_VAL			0x80000000	/* CS1 */
-#define CFG_GAFR0_U_VAL			0x00000010	/* RDY */
-#define CFG_GAFR1_L_VAL			0x09988050	/* FFUART + BTUART pins */
-#define CFG_GAFR1_U_VAL			0x00000008	/* nPWE */
-#define CFG_GAFR2_L_VAL			0xA0000000	/* CS2, CS3 */
-#define CFG_GAFR2_U_VAL			0x00000000
-
-#define CFG_PSSR_VAL			0x00000020	/* Power manager sleep status */
-#define CFG_CCCR_VAL			0x00000161	/* 100 MHz memory, 400 MHz CPU  */
-#define CFG_CKEN_VAL			0x000000C0	/* BTUART and FFUART enabled    */
-#define CFG_ICMR_VAL			0x00000000	/* No interrupts enabled        */
+#define CONFIG_SYS_GAFR0_L_VAL			0x80000000	/* CS1 */
+#define CONFIG_SYS_GAFR0_U_VAL			0x00000010	/* RDY */
+#define CONFIG_SYS_GAFR1_L_VAL			0x09988050	/* FFUART + BTUART pins */
+#define CONFIG_SYS_GAFR1_U_VAL			0x00000008	/* nPWE */
+#define CONFIG_SYS_GAFR2_L_VAL			0xA0000000	/* CS2, CS3 */
+#define CONFIG_SYS_GAFR2_U_VAL			0x00000000
+
+#define CONFIG_SYS_PSSR_VAL			0x00000020	/* Power manager sleep status */
+#define CONFIG_SYS_CCCR_VAL			0x00000161	/* 100 MHz memory, 400 MHz CPU  */
+#define CONFIG_SYS_CKEN_VAL			0x000000C0	/* BTUART and FFUART enabled    */
+#define CONFIG_SYS_ICMR_VAL			0x00000000	/* No interrupts enabled        */
 
 /* Memory settings */
-#define CFG_MSC0_VAL			0x25F425F0
+#define CONFIG_SYS_MSC0_VAL			0x25F425F0
 
 /* MDCNFG: SDRAM Configuration Register */
-#define CFG_MDCNFG_VAL			0x000009C9
+#define CONFIG_SYS_MDCNFG_VAL			0x000009C9
 
 /* MDREFR: SDRAM Refresh Control Register */
-#define CFG_MDREFR_VAL			0x00018018
+#define CONFIG_SYS_MDREFR_VAL			0x00018018
 
 /* MDMRS: Mode Register Set Configuration Register */
-#define CFG_MDMRS_VAL			0x00220022
+#define CONFIG_SYS_MDMRS_VAL			0x00220022
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h
deleted file mode 100644
index 0e33714..0000000
--- a/include/configs/xupv2p.h
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * (C) Copyright 2007-2008 Michal Simek
- *
- * Michal SIMEK <monstr@monstr.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "../board/xilinx/xupv2p/xparameters.h"
-
-#define	CONFIG_MICROBLAZE	1	/* MicroBlaze CPU */
-#define	CONFIG_XUPV2P		1
-
-/* uart */
-#ifdef XILINX_UARTLITE_BASEADDR
-#define	CONFIG_XILINX_UARTLITE
-#define	CONFIG_SERIAL_BASE	XILINX_UARTLITE_BASEADDR
-#define	CONFIG_BAUDRATE		XILINX_UARTLITE_BAUDRATE
-#define	CFG_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
-#else
-#ifdef XILINX_UART16550_BASEADDR
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	4
-#define CONFIG_CONS_INDEX	1
-#define CFG_NS16550_COM1	XILINX_UART16550_BASEADDR
-#define CFG_NS16550_CLK		XILINX_UART16550_CLOCK_HZ
-#define	CONFIG_BAUDRATE		115200
-#define	CFG_BAUDRATE_TABLE	{ 9600, 115200 }
-#endif
-#endif
-
-/*
- * setting reset address
- *
- * TEXT_BASE is set to place, where the U-BOOT run in RAM, but
- * if you want to store U-BOOT in flash, set CFG_RESET_ADDRESS
- * to FLASH memory and after loading bitstream jump to FLASH.
- * U-BOOT auto-relocate to TEXT_BASE. After RESET command Microblaze
- * jump to CFG_RESET_ADDRESS where is the original U-BOOT code.
- */
-/* #define	CFG_RESET_ADDRESS	0x36000000 */
-
-/* ethernet */
-#ifdef XILINX_EMAC_BASEADDR
-#define CONFIG_XILINX_EMAC	1
-#define CFG_ENET
-#else
-#ifdef XILINX_EMACLITE_BASEADDR
-#define CONFIG_XILINX_EMACLITE	1
-#define CFG_ENET
-#endif
-#endif
-#undef ET_DEBUG
-
-/* gpio */
-#ifdef XILINX_GPIO_BASEADDR
-#define	CFG_GPIO_0		1
-#define	CFG_GPIO_0_ADDR		XILINX_GPIO_BASEADDR
-#endif
-
-/* interrupt controller */
-#ifdef XILINX_INTC_BASEADDR
-#define	CFG_INTC_0		1
-#define	CFG_INTC_0_ADDR		XILINX_INTC_BASEADDR
-#define	CFG_INTC_0_NUM		XILINX_INTC_NUM_INTR_INPUTS
-#endif
-
-/* timer */
-#ifdef XILINX_TIMER_BASEADDR
-#if (XILINX_TIMER_IRQ != -1)
-#define	CFG_TIMER_0		1
-#define	CFG_TIMER_0_ADDR	XILINX_TIMER_BASEADDR
-#define	CFG_TIMER_0_IRQ		XILINX_TIMER_IRQ
-#define	FREQUENCE		XILINX_CLOCK_FREQ
-#define	CFG_TIMER_0_PRELOAD	( FREQUENCE/1000 )
-#endif
-#else
-#ifdef XILINX_CLOCK_FREQ
-#define	CONFIG_XILINX_CLOCK_FREQ	XILINX_CLOCK_FREQ
-#else
-#error BAD CLOCK FREQ
-#endif
-#endif
-/*
- * memory layout - Example
- * TEXT_BASE = 0x3600_0000;
- * CFG_SRAM_BASE = 0x3000_0000;
- * CFG_SRAM_SIZE = 0x1000_0000;
- *
- * CFG_GBL_DATA_OFFSET = 0x3000_0000 + 0x1000_0000 - 0x1000 = 0x3FFF_F000
- * CFG_MONITOR_BASE = 0x3FFF_F000 - 0x40000 = 0x3FFB_F000
- * CFG_MALLOC_BASE = 0x3FFB_F000 - 0x40000 = 0x3FF7_F000
- *
- * 0x3000_0000	CFG_SDRAM_BASE
- *					FREE
- * 0x3600_0000	TEXT_BASE
- *		U-BOOT code
- * 0x3602_0000
- *					FREE
- *
- *					STACK
- * 0x3FF7_F000	CFG_MALLOC_BASE
- *					MALLOC_AREA	256kB	Alloc
- * 0x3FFB_F000	CFG_MONITOR_BASE
- *					MONITOR_CODE	256kB	Env
- * 0x3FFF_F000	CFG_GBL_DATA_OFFSET
- *					GLOBAL_DATA	4kB	bd, gd
- * 0x4000_0000	CFG_SDRAM_BASE + CFG_SDRAM_SIZE
- */
-
-/* ddr sdram - main memory */
-#define	CFG_SDRAM_BASE		XILINX_RAM_START
-#define	CFG_SDRAM_SIZE		XILINX_RAM_SIZE
-#define	CFG_MEMTEST_START	CFG_SDRAM_BASE
-#define	CFG_MEMTEST_END		(CFG_SDRAM_BASE + 0x1000)
-
-/* global pointer */
-#define	CFG_GBL_DATA_SIZE	0x1000	/* size of global data */
-#define	CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */
-
-/* monitor code */
-#define	SIZE			0x40000
-#define	CFG_MONITOR_LEN		SIZE
-#define	CFG_MONITOR_BASE	(CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
-#define	CFG_MONITOR_END		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define	CFG_MALLOC_LEN		SIZE
-#define	CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-
-/* stack */
-#define	CFG_INIT_SP_OFFSET	CFG_MALLOC_BASE
-
-#define	CFG_NO_FLASH		1
-#define	CONFIG_ENV_IS_NOWHERE	1
-#define	CONFIG_ENV_SIZE		0x1000
-#define	CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - CONFIG_ENV_SIZE)
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_IMLS
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_IRQ
-
-#ifndef CFG_ENET
-	#undef CONFIG_CMD_NET
-#else
-	#define CONFIG_CMD_PING
-#endif
-
-#ifdef XILINX_SYSACE_BASEADDR
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#endif
-
-/* Miscellaneous configurable options */
-#define	CFG_PROMPT	"U-Boot-mONStR> "
-#define	CFG_CBSIZE	512	/* size of console buffer */
-#define	CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
-#define	CFG_MAXARGS	15	/* max number of command args */
-#define	CFG_LONGHELP
-#define	CFG_LOAD_ADDR	0x12000000 /* default load address */
-
-#define	CONFIG_BOOTDELAY	30
-#define	CONFIG_BOOTARGS		"root=romfs"
-#define	CONFIG_HOSTNAME		"xupv2p"
-#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
-#define	CONFIG_IPADDR		192.168.0.3
-#define	CONFIG_SERVERIP		192.168.0.5
-#define	CONFIG_GATEWAYIP	192.168.0.1
-#define	CONFIG_ETHADDR		00:E0:0C:00:00:FD
-
-/* architecture dependent code */
-#define	CFG_USR_EXCEP	/* user exception */
-#define CFG_HZ	1000
-
-#define CONFIG_PREBOOT	"echo U-BOOT by mONStR;"	\
-	"base 0;" \
-	"echo"
-
-/* system ace */
-#ifdef XILINX_SYSACE_BASEADDR
-#define	CONFIG_SYSTEMACE
-/* #define DEBUG_SYSTEMACE */
-#define	SYSTEMACE_CONFIG_FPGA
-#define	CFG_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
-#define	CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
-#define	CONFIG_DOS_PARTITION
-#endif
-
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_OF_LIBFDT	1 /* flat device tree */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index afdce82..b66ab58 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -55,36 +55,36 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE	        0xfc000000	    /* start of FLASH	*/
-#define CFG_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
-#define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
-#define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
+#define CONFIG_SYS_FLASH_BASE	        0xfc000000	    /* start of FLASH	*/
+#define CONFIG_SYS_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
+#define CONFIG_SYS_PCI_MEMBASE1        CONFIG_SYS_PCI_MEMBASE  + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2        CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3        CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
 
 /*Don't change either of these*/
-#define CFG_PERIPHERAL_BASE     0xef600000	    /* internal peripherals*/
-#define CFG_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
+#define CONFIG_SYS_PERIPHERAL_BASE     0xef600000	    /* internal peripherals*/
+#define CONFIG_SYS_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
 /*Don't change either of these*/
 
-#define CFG_USB_DEVICE          0x50000000
-#define CFG_NVRAM_BASE_ADDR     0x80000000
-#define CFG_BCSR_BASE	        (CFG_NVRAM_BASE_ADDR | 0x2000)
-#define CFG_BOOT_BASE_ADDR      0xf0000000
+#define CONFIG_SYS_USB_DEVICE          0x50000000
+#define CONFIG_SYS_NVRAM_BASE_ADDR     0x80000000
+#define CONFIG_SYS_BCSR_BASE	        (CONFIG_SYS_NVRAM_BASE_ADDR | 0x2000)
+#define CONFIG_SYS_BOOT_BASE_ADDR      0xf0000000
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
-#define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
-#define CFG_INIT_RAM_END	(4 << 10)
-#define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
+#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000		/* DCache       */
+#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_SIZE	256			/* num bytes initial data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#define CFG_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
 /*define this if you want console on UART1*/
 #undef CONFIG_UART1_CONSOLE
 
@@ -104,23 +104,23 @@
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
 #define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
-#define CFG_FLASH_CFI_AMD_RESET 1		/* AMD RESET for STM 29W320DB!	*/
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1		/* AMD RESET for STM 29W320DB!	*/
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -132,20 +132,19 @@
  * DDR SDRAM
  *----------------------------------------------------------------------*/
 #undef CONFIG_SPD_EEPROM	       /* Don't use SPD EEPROM for setup    */
-#define CFG_KBYTES_SDRAM        (128 * 1024)    /* 128MB		    */
-#define CFG_SDRAM_BANKS	        (2)
+#define CONFIG_SYS_KBYTES_SDRAM        (128 * 1024)    /* 128MB		    */
+#define CONFIG_SYS_SDRAM_BANKS	        (2)
 
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 
 #ifdef CONFIG_ENV_IS_IN_EEPROM
 #define CONFIG_ENV_SIZE		0x200	    /* Size of Environment vars */
@@ -156,9 +155,9 @@
 #define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
 #define CONFIG_DTT_AD7414	1		/* use AD7414		*/
 #define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
-#define CFG_DTT_MAX_TEMP	70
-#define CFG_DTT_LOW_TEMP	-30
-#define CFG_DTT_HYSTERESIS	3
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
 
 /*
  * Default environment variables
@@ -186,13 +185,13 @@
 /* USB */
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_STORAGE
-#define CFG_OHCI_BE_CONTROLLER
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
 
-#undef CFG_USB_OHCI_BOARD_INIT
-#define CFG_USB_OHCI_CPU_INIT	1
-#define CFG_USB_OHCI_REGS_BASE	(CFG_PERIPHERAL_BASE | 0x1000)
-#define CFG_USB_OHCI_SLOT_NAME	"ppc440"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS	15
+#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	(CONFIG_SYS_PERIPHERAL_BASE | 0x1000)
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ppc440"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
 
 /* Comment this out to enable USB 1.1 device */
 #define USB_2_0_DEVICE
@@ -226,29 +225,29 @@
 #define CONFIG_PCI			/* include pci support	        */
 #undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
-#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+#define CONFIG_SYS_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT
-#define CFG_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
 
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever */
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
-#define CFG_FLASH		CFG_FLASH_BASE
-#define CFG_CPLD		0x80000000
+#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CPLD		0x80000000
 
 /* Memory Bank 0 (NOR-FLASH) initialization					*/
-#define CFG_EBC_PB0AP		0x03017300
-#define CFG_EBC_PB0CR		(CFG_FLASH | 0xda000)
+#define CONFIG_SYS_EBC_PB0AP		0x03017300
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH | 0xda000)
 
 /* Memory Bank 2 (CPLD) initialization						*/
-#define CFG_EBC_PB2AP		0x04814500
-#define CFG_EBC_PB2CR		(CFG_CPLD | 0x18000)
+#define CONFIG_SYS_EBC_PB2AP		0x04814500
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_CPLD | 0x18000)
 
-#define CFG_BCSR5_PCI66EN	0x80
+#define CONFIG_SYS_BCSR5_PCI66EN	0x80
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index 92d45d0..b165bd7 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -58,49 +58,49 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE		0xfff00000	/* start of FLASH	*/
-#define CFG_PERIPHERAL_BASE	0xa0000000	/* internal peripherals	*/
-#define CFG_ISRAM_BASE		0x90000000	/* internal SRAM	*/
+#define CONFIG_SYS_FLASH_BASE		0xfff00000	/* start of FLASH	*/
+#define CONFIG_SYS_PERIPHERAL_BASE	0xa0000000	/* internal peripherals	*/
+#define CONFIG_SYS_ISRAM_BASE		0x90000000	/* internal SRAM	*/
 
-#define CFG_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
-#define CFG_PCI_BASE		0xd0000000	/* internal PCI regs	*/
-#define CFG_PCI_TARGBASE	CFG_PCI_MEMBASE
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
+#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs	*/
+#define CONFIG_SYS_PCI_TARGBASE	CONFIG_SYS_PCI_MEMBASE
 
-#define CFG_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
-#define CFG_PCIE_MEMSIZE	0x08000000	/* smallest incr for PCIe port */
-#define CFG_PCIE_BASE		0xe0000000	/* PCIe UTL regs */
+#define CONFIG_SYS_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
+#define CONFIG_SYS_PCIE_MEMSIZE	0x08000000	/* smallest incr for PCIe port */
+#define CONFIG_SYS_PCIE_BASE		0xe0000000	/* PCIe UTL regs */
 
-#define CFG_PCIE0_CFGBASE	0xc0000000
-#define CFG_PCIE1_CFGBASE	0xc1000000
-#define CFG_PCIE2_CFGBASE	0xc2000000
-#define CFG_PCIE0_XCFGBASE	0xc3000000
-#define CFG_PCIE1_XCFGBASE	0xc3001000
-#define CFG_PCIE2_XCFGBASE	0xc3002000
+#define CONFIG_SYS_PCIE0_CFGBASE	0xc0000000
+#define CONFIG_SYS_PCIE1_CFGBASE	0xc1000000
+#define CONFIG_SYS_PCIE2_CFGBASE	0xc2000000
+#define CONFIG_SYS_PCIE0_XCFGBASE	0xc3000000
+#define CONFIG_SYS_PCIE1_XCFGBASE	0xc3001000
+#define CONFIG_SYS_PCIE2_XCFGBASE	0xc3002000
 
 /* base address of inbound PCIe window */
-#define CFG_PCIE_INBOUND_BASE	0x0000000400000000ULL
+#define CONFIG_SYS_PCIE_INBOUND_BASE	0x0000000400000000ULL
 
 /* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
 
-#define CFG_FPGA_BASE		0xe2000000	/* epld			*/
-#define CFG_OPER_FLASH		0xe7000000	/* SRAM - OPER Flash	*/
+#define CONFIG_SYS_FPGA_BASE		0xe2000000	/* epld			*/
+#define CONFIG_SYS_OPER_FLASH		0xe7000000	/* SRAM - OPER Flash	*/
 
-/* #define CFG_NVRAM_BASE_ADDR 0x08000000 */
+/* #define CONFIG_SYS_NVRAM_BASE_ADDR 0x08000000 */
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
-#define CFG_TEMP_STACK_OCM	1
-#define CFG_OCM_DATA_ADDR	CFG_ISRAM_BASE
-#define CFG_INIT_RAM_ADDR	CFG_ISRAM_BASE	/* Initial RAM address	*/
-#define CFG_INIT_RAM_END	0x2000		/* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_END	0x2000		/* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
 
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_POST_WORD_ADDR
 
 /*-----------------------------------------------------------------------
  * Serial Port
@@ -108,8 +108,8 @@
 #undef CONFIG_UART1_CONSOLE
 
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#undef CFG_EXT_SERIAL_CLOCK
-/* #define CFG_EXT_SERIAL_CLOCK	(1843200 * 6) */ /* Ext clk @ 11.059 MHz */
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK
+/* #define CONFIG_SYS_EXT_SERIAL_CLOCK	(1843200 * 6) */ /* Ext clk @ 11.059 MHz */
 
 /*-----------------------------------------------------------------------
  * DDR SDRAM
@@ -121,23 +121,23 @@
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 
 #define IIC0_BOOTPROM_ADDR	0x50
 #define IIC0_ALT_BOOTPROM_ADDR	0x54
 
 /* Don't probe these addrs */
-#define CFG_I2C_NOPROBES	{0x50, 0x52, 0x53, 0x54}
+#define CONFIG_SYS_I2C_NOPROBES	{0x50, 0x52, 0x53, 0x54}
 
 /* #if defined(CONFIG_CMD_EEPROM) */
-/* #define CFG_I2C_EEPROM_ADDR	0x50 */	/* I2C boot EEPROM		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
+/* #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50 */	/* I2C boot EEPROM		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
 /* #endif */
 
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
-/* #define CFG_NVRAM_SIZE	(0x2000 - 8) */	/* NVRAM size(8k)- RTC regs */
+/* #define CONFIG_SYS_NVRAM_SIZE	(0x2000 - 8) */	/* NVRAM size(8k)- RTC regs */
 
 #undef  CONFIG_ENV_IS_IN_NVRAM		/* ... not in NVRAM		*/
 #define	CONFIG_ENV_IS_IN_FLASH	1	/* Environment uses flash	*/
@@ -174,24 +174,24 @@
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS	3	/* number of banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* sectors per device		*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* number of banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* sectors per device		*/
 
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
 
-#define CFG_FLASH_ADDR0		0x5555
-#define CFG_FLASH_ADDR1		0x2aaa
-#define CFG_FLASH_WORD_SIZE	unsigned char
+#define CONFIG_SYS_FLASH_ADDR0		0x5555
+#define CONFIG_SYS_FLASH_ADDR1		0x2aaa
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char
 
-#define CFG_FLASH_2ND_16BIT_DEV	1	/* evb440SPe has 8 and 16bit device */
-#define CFG_FLASH_2ND_ADDR	0xe7c00000 /* evb440SPe has 8 and 16bit device*/
+#define CONFIG_SYS_FLASH_2ND_16BIT_DEV	1	/* evb440SPe has 8 and 16bit device */
+#define CONFIG_SYS_FLASH_2ND_ADDR	0xe7c00000 /* evb440SPe has 8 and 16bit device*/
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
 #define CONFIG_ENV_ADDR		0xfffa0000
-/* #define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) */
+/* #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) */
 #define CONFIG_ENV_SIZE		0x10000	/* Size of Environment vars	*/
 #endif /* CONFIG_ENV_IS_IN_FLASH */
 /*-----------------------------------------------------------------------
@@ -205,12 +205,12 @@
 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 
 /* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT		/* let board init pci target    */
-#undef	CFG_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */
+#undef	CONFIG_SYS_PCI_MASTER_INIT
 
-#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
-/* #define CFG_PCI_SUBSYS_ID	CFG_PCI_SUBSYS_DEVICEID */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
+/* #define CONFIG_SYS_PCI_SUBSYS_ID	CONFIG_SYS_PCI_SUBSYS_DEVICEID */
 
 /*
  *  NETWORK Support (PCI):
diff --git a/include/configs/zeus.h b/include/configs/zeus.h
index d427095..1a77c71 100644
--- a/include/configs/zeus.h
+++ b/include/configs/zeus.h
@@ -46,12 +46,13 @@
 
 #define CONFIG_OVERWRITE_ETHADDR_ONCE	1
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0x01	/* PHY address			*/
 #define CONFIG_HAS_ETH1		1
 #define CONFIG_PHY1_ADDR	0x11	/* EMAC1 PHY address		*/
 #define CONFIG_NET_MULTI	1
-#define CFG_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
 #define CONFIG_PHY_RESET	1
 #define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/
 
@@ -84,21 +85,21 @@
 #define CONFIG_CMD_REGINFO
 
 /* POST support */
-#define CONFIG_POST		(CFG_POST_MEMORY   | \
-				 CFG_POST_CPU	   | \
-				 CFG_POST_CACHE	   | \
-				 CFG_POST_UART	   | \
-				 CFG_POST_ETHER)
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_CACHE	   | \
+				 CONFIG_SYS_POST_UART	   | \
+				 CONFIG_SYS_POST_ETHER)
 
-#define CFG_POST_ETHER_EXT_LOOPBACK	/* eth POST using ext loopack connector	*/
+#define CONFIG_SYS_POST_ETHER_EXT_LOOPBACK	/* eth POST using ext loopack connector	*/
 
 /* Define here the base-addresses of the UARTs to test in POST */
-#define CFG_POST_UART_TABLE	{UART0_BASE}
+#define CONFIG_SYS_POST_UART_TABLE	{UART0_BASE}
 
 #define CONFIG_LOGBUFFER
-#define CFG_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/
+#define CONFIG_SYS_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/
 
-#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -112,48 +113,48 @@
 #define CONFIG_SDRAM_BANK1	1	/* init onboard SDRAM bank 1 */
 
 /* SDRAM timings used in datasheet */
-#define CFG_SDRAM_CL            3	/* CAS latency */
-#define CFG_SDRAM_tRP           20	/* PRECHARGE command period */
-#define CFG_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE command period */
-#define CFG_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
-#define CFG_SDRAM_tRFC		66	/* Auto refresh period */
+#define CONFIG_SYS_SDRAM_CL            3	/* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE command period */
+#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC		66	/* Auto refresh period */
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#undef	CFG_EXT_SERIAL_CLOCK			/* external serial clock */
-#define CFG_BASE_BAUD		691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK			/* external serial clock */
+#define CONFIG_SYS_BASE_BAUD		691200
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SERIAL_MULTI
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
+#define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  *----------------------------------------------------------------------*/
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
+#define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
@@ -166,18 +167,17 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C		1		/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /* these are for the ST M24C02 2kbit serial i2c eeprom */
-#define CFG_I2C_EEPROM_ADDR	0x50		/* base address */
-#define CFG_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
 /* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
 
-#define CFG_EEPROM_PAGE_WRITE_ENABLE	1	/* write eeprom in pages */
-#define CFG_EEPROM_PAGE_WRITE_BITS	3	/* 8 byte write page size */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3	/* 8 byte write page size */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
 /*
  * The layout of the I2C EEPROM, used for bootstrap setup and for board-
@@ -191,44 +191,44 @@
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFF000000
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	(-CONFIG_SYS_MONITOR_LEN)
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
 #define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
 
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection	*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
-#define CONFIG_ENV_ADDR		((-CFG_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 #define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -240,31 +240,31 @@
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory (OCM) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	1
+#define CONFIG_SYS_TEMP_STACK_OCM	1
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR	0xF8000000
-#define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of OCM		*/
-#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM		*/
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
 
-#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 /* reserve some memory for POST and BOOT limit info */
-#define CFG_INIT_SP_OFFSET	(CFG_GBL_DATA_OFFSET - 16)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 16)
 
 /* extra data in OCM */
-#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 4)
-#define CFG_POST_MAGIC		(CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 8)
-#define CFG_POST_VAL		(CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 12)
+#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 4)
+#define CONFIG_SYS_POST_MAGIC		(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 8)
+#define CONFIG_SYS_POST_VAL		(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 12)
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  */
 
 /* Memory Bank 0 (Flash 16M) initialization					*/
-#define CFG_EBC_PB0AP		0x05815600
-#define CFG_EBC_PB0CR		0xFF09A000  /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit  */
+#define CONFIG_SYS_EBC_PB0AP		0x05815600
+#define CONFIG_SYS_EBC_PB0CR		0xFF09A000  /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit  */
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup (PPC405EP specific)
@@ -278,23 +278,23 @@
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  */
-#define CFG_GPIO0_OSRH		0x15555550	/* Chip selects */
-#define CFG_GPIO0_OSRL		0x00000110	/* UART_DTR-pin 27 alt out */
-#define CFG_GPIO0_ISR1H		0x10000041	/* Pin 2, 12 is input */
-#define CFG_GPIO0_ISR1L		0x15505440	/* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
-#define CFG_GPIO0_TSRH		0x00000000
-#define CFG_GPIO0_TSRL		0x00000000
-#define CFG_GPIO0_TCR		0xBFF68317	/* 3-state OUT: 22/23/29; 12,2 is not 3-state */
-#define CFG_GPIO0_ODR		0x00000000
-
-#define CFG_GPIO_SW_RESET	1
-#define CFG_GPIO_ZEUS_PE	12
-#define CFG_GPIO_LED_RED	22
-#define CFG_GPIO_LED_GREEN	23
+#define CONFIG_SYS_GPIO0_OSRH		0x15555550	/* Chip selects */
+#define CONFIG_SYS_GPIO0_OSRL		0x00000110	/* UART_DTR-pin 27 alt out */
+#define CONFIG_SYS_GPIO0_ISR1H		0x10000041	/* Pin 2, 12 is input */
+#define CONFIG_SYS_GPIO0_ISR1L		0x15505440	/* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0xBFF68317	/* 3-state OUT: 22/23/29; 12,2 is not 3-state */
+#define CONFIG_SYS_GPIO0_ODR		0x00000000
+
+#define CONFIG_SYS_GPIO_SW_RESET	1
+#define CONFIG_SYS_GPIO_ZEUS_PE	12
+#define CONFIG_SYS_GPIO_LED_RED	22
+#define CONFIG_SYS_GPIO_LED_GREEN	23
 
 /* Time in milli-seconds */
-#define CFG_TIME_POST		5000
-#define CFG_TIME_FACTORY_RESET	10000
+#define CONFIG_SYS_TIME_POST		5000
+#define CONFIG_SYS_TIME_FACTORY_RESET	10000
 
 /*
  * Internal Definitions
diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h
index 148079c..6febeea 100644
--- a/include/configs/zylonite.h
+++ b/include/configs/zylonite.h
@@ -41,7 +41,7 @@
 #ifdef CONFIG_LCD
 #define CONFIG_SHARP_LM8V31
 #endif
-/* #define CONFIG_MMC		1 */
+#undef CONFIG_MMC
 #define BOARD_LATE_INIT		1
 
 #undef CONFIG_SKIP_RELOCATE_UBOOT
@@ -50,8 +50,8 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -94,7 +94,7 @@
 #ifdef TURN_ON_ETHERNET
     #define CONFIG_CMD_PING
 #else
-    #define CONFIG_CMD_ENV
+    #define CONFIG_CMD_SAVEENV
     #define CONFIG_CMD_NAND
 
     #undef CONFIG_CMD_NET
@@ -121,38 +121,42 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_HUSH_PARSER		1
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
-#define CFG_LONGHELP				/* undef to save memory		*/
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT		"$ "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
 #else
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 #endif
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_DEVICE_NULLDEV	1
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1
 
-#define CFG_MEMTEST_START	0x9c000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x9c400000	/* 4 ... 8 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x9c000000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x9c400000	/* 4 ... 8 MB in DRAM	*/
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR	(CFG_DRAM_BASE + 0x8000) /* default load address */
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
 
-#define CFG_HZ			3250000		/* incrementer freq: 3.25 MHz */
+#define CONFIG_SYS_HZ			1000
 
 /* Monahans Core Frequency */
-#define CFG_MONAHANS_RUN_MODE_OSC_RATIO		16 /* valid values: 8, 16, 24, 31 */
-#define CFG_MONAHANS_TURBO_RUN_MODE_RATIO	1  /* valid values: 1, 2 */
+#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO		16 /* valid values: 8, 16, 24, 31 */
+#define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO	1  /* valid values: 1, 2 */
 
 						/* valid baudrates */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-/* #define CFG_MMC_BASE		0xF0000000 */
+#ifdef CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_SYS_MMC_BASE		0xF0000000
+#endif
 
 /*
  * Stack sizes
@@ -178,26 +182,26 @@
 #define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
 #define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
 
-#define CFG_DRAM_BASE		0x80000000 /* at CS0 */
-#define CFG_DRAM_SIZE		0x04000000 /* 64 MB Ram */
+#define CONFIG_SYS_DRAM_BASE		0x80000000 /* at CS0 */
+#define CONFIG_SYS_DRAM_SIZE		0x04000000 /* 64 MB Ram */
 
-#undef CFG_SKIP_DRAM_SCRUB
+#undef CONFIG_SYS_SKIP_DRAM_SCRUB
 
 
 /*
  * NAND Flash
  */
 #define CONFIG_NEW_NAND_CODE
-#define CFG_NAND0_BASE		0x0
-#undef CFG_NAND1_BASE
+#define CONFIG_SYS_NAND0_BASE		0x0
+#undef CONFIG_SYS_NAND1_BASE
 
-#define CFG_NAND_BASE_LIST	{ CFG_NAND0_BASE }
-#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND0_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
 
 /* nand timeout values */
-#define CFG_NAND_PROG_ERASE_TO	3000
-#define CFG_NAND_OTHER_TO	100
-#define CFG_NAND_SENDCMD_RETRY	3
+#define CONFIG_SYS_NAND_PROG_ERASE_TO	3000
+#define CONFIG_SYS_NAND_OTHER_TO	100
+#define CONFIG_SYS_NAND_SENDCMD_RETRY	3
 #undef NAND_ALLOW_ERASE_ALL	/* Allow erasing bad blocks - don't use */
 
 /* NAND Timing Parameters (in ns) */
@@ -214,9 +218,9 @@
 #define NAND_TIMING_tAR		10
 
 /* NAND debugging */
-#define CFG_DFC_DEBUG1 /* usefull */
-#undef CFG_DFC_DEBUG2  /* noisy */
-#undef CFG_DFC_DEBUG3  /* extremly noisy  */
+#define CONFIG_SYS_DFC_DEBUG1 /* usefull */
+#undef CONFIG_SYS_DFC_DEBUG2  /* noisy */
+#undef CONFIG_SYS_DFC_DEBUG3  /* extremly noisy  */
 
 #define CONFIG_MTD_DEBUG
 #define CONFIG_MTD_DEBUG_VERBOSE 1
@@ -227,9 +231,8 @@
 
 #define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS		1
-#define NAND_MAX_CHIPS		1
 
-#define CFG_NO_FLASH		1
+#define CONFIG_SYS_NO_FLASH		1
 
 #define CONFIG_ENV_IS_IN_NAND	1
 #define CONFIG_ENV_OFFSET		0x40000
diff --git a/include/dataflash.h b/include/dataflash.h
index de04139..63b3bf9 100644
--- a/include/dataflash.h
+++ b/include/dataflash.h
@@ -40,7 +40,7 @@
 /*number of protected area*/
 #define NB_DATAFLASH_AREA		5
 
-#ifdef CFG_NO_FLASH
+#ifdef CONFIG_SYS_NO_FLASH
 
 /*-----------------------------------------------------------------------
  * return codes from flash_write():
@@ -66,7 +66,7 @@
  * Set Environment according to label:
  */
 # define	FLAG_SETENV		0x80
-#endif /* CFG_NO_FLASH */
+#endif /* CONFIG_SYS_NO_FLASH */
 
 /*define the area structure*/
 typedef struct {
@@ -213,7 +213,7 @@ extern void dataflash_print_info (void);
 extern void dataflash_perror (int err);
 extern void AT91F_DataflashSetEnv (void);
 
-extern struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS];
+extern struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS];
 extern dataflash_protect_t area_list[NB_DATAFLASH_AREA];
 extern AT91S_DATAFLASH_INFO dataflash_info[];
 #endif
diff --git a/include/devices.h b/include/devices.h
index 6b78d58..3a9881b 100644
--- a/include/devices.h
+++ b/include/devices.h
@@ -91,11 +91,16 @@ extern char *stdio_names[MAX_FILES];
  */
 int	device_register (device_t * dev);
 int	devices_init (void);
+#ifdef CONFIG_SYS_DEVICE_DEREGISTER
 int	device_deregister(char *devname);
+#endif
 struct list_head* device_get_list(void);
 device_t* device_get_by_name(char* name);
 device_t* device_clone(device_t *dev);
 
+#ifdef CONFIG_ARM_DCC_MULTI
+int drv_arm_dcc_init(void);
+#endif
 #ifdef CONFIG_LCD
 int	drv_lcd_init (void);
 #endif
@@ -114,5 +119,8 @@ int	drv_usbtty_init (void);
 #ifdef CONFIG_NETCONSOLE
 int	drv_nc_init (void);
 #endif
+#ifdef CONFIG_JTAG_CONSOLE
+int drv_jtag_console_init (void);
+#endif
 
 #endif	/* _DEVICES_H_ */
diff --git a/include/div64.h b/include/div64.h
index c495aef..d833144 100644
--- a/include/div64.h
+++ b/include/div64.h
@@ -36,4 +36,14 @@ extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
 	__rem;						\
  })
 
+/* Wrapper for do_div(). Doesn't modify dividend and returns
+ * the result, not reminder.
+ */
+static inline uint64_t lldiv(uint64_t dividend, uint32_t divisor)
+{
+	uint64_t __res = dividend;
+	do_div(__res, divisor);
+	return(__res);
+}
+
 #endif /* _ASM_GENERIC_DIV64_H */
diff --git a/include/ds4510.h b/include/ds4510.h
new file mode 100644
index 0000000..40480af
--- /dev/null
+++ b/include/ds4510.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __DS4510_H_
+#define __DS4510_H_
+
+/* General defines */
+#define DS4510_NUM_IO				0x04
+#define DS4510_IO_MASK				((1 << DS4510_NUM_IO) - 1)
+#define DS4510_EEPROM_PAGE_WRITE_DELAY_MS	20
+
+/* EEPROM from 0x00 - 0x39 */
+#define DS4510_EEPROM				0x00
+#define DS4510_EEPROM_SIZE			0x40
+#define DS4510_EEPROM_PAGE_SIZE			0x08
+#define DS4510_EEPROM_PAGE_OFFSET(x)	((x) & (DS4510_EEPROM_PAGE_SIZE - 1))
+
+/* SEEPROM from 0xf0 - 0xf7 */
+#define DS4510_SEEPROM				0xf0
+#define DS4510_SEEPROM_SIZE			0x08
+
+/* Registers overlapping SEEPROM from 0xf0 - 0xf7 */
+#define DS4510_PULLUP				0xF0
+#define DS4510_PULLUP_DIS			0x00
+#define DS4510_PULLUP_EN			0x01
+#define DS4510_RSTDELAY				0xF1
+#define DS4510_RSTDELAY_MASK			0x03
+#define DS4510_RSTDELAY_125			0x00
+#define DS4510_RSTDELAY_250			0x01
+#define DS4510_RSTDELAY_500			0x02
+#define DS4510_RSTDELAY_1000			0x03
+#define DS4510_IO3				0xF4
+#define DS4510_IO2				0xF5
+#define DS4510_IO1				0xF6
+#define DS4510_IO0				0xF7
+
+/* Status configuration registers from 0xf8 - 0xf9*/
+#define DS4510_IO_STATUS			0xF8
+#define DS4510_CFG				0xF9
+#define DS4510_CFG_READY			0x80
+#define DS4510_CFG_TRIP_POINT			0x40
+#define DS4510_CFG_RESET			0x20
+#define DS4510_CFG_SEE				0x10
+#define DS4510_CFG_SWRST			0x08
+
+/* SRAM from 0xfa - 0xff */
+#define DS4510_SRAM				0xfa
+#define DS4510_SRAM_SIZE			0x06
+
+int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count);
+int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count);
+int ds4510_see_write(uint8_t chip, uint8_t nv);
+int ds4510_rstdelay_write(uint8_t chip, uint8_t delay);
+int ds4510_pullup_write(uint8_t chip, uint8_t val);
+int ds4510_pullup_read(uint8_t chip);
+int ds4510_gpio_write(uint8_t chip, uint8_t val);
+int ds4510_gpio_read(uint8_t chip);
+int ds4510_gpio_read_val(uint8_t chip);
+
+#endif /* __DS4510_H_ */
diff --git a/include/dtt.h b/include/dtt.h
index 0c8ee76..399b64a 100644
--- a/include/dtt.h
+++ b/include/dtt.h
@@ -31,6 +31,7 @@
     defined(CONFIG_DTT_ADT7460)	|| \
     defined(CONFIG_DTT_DS1621)	|| \
     defined(CONFIG_DTT_DS1775)	|| \
+    defined(CONFIG_DTT_LM63)	|| \
     defined(CONFIG_DTT_LM73)	|| \
     defined(CONFIG_DTT_LM75)	|| \
     defined(CONFIG_DTT_LM81)
@@ -42,12 +43,12 @@
 #define DTT_INDUSTRIAL_MAX_TEMP	85		/* -40 - +85 C */
 #define DTT_AUTOMOTIVE_MAX_TEMP	105		/* -40 - +105 C */
 
-#ifndef CFG_DTT_MAX_TEMP
-#define CFG_DTT_MAX_TEMP DTT_COMMERCIAL_MAX_TEMP
+#ifndef CONFIG_SYS_DTT_MAX_TEMP
+#define CONFIG_SYS_DTT_MAX_TEMP DTT_COMMERCIAL_MAX_TEMP
 #endif
 
-#ifndef CFG_DTT_HYSTERESIS
-#define CFG_DTT_HYSTERESIS	5		/* 5 C */
+#ifndef CONFIG_SYS_DTT_HYSTERESIS
+#define CONFIG_SYS_DTT_HYSTERESIS	5		/* 5 C */
 #endif
 #endif /* CONFIG_DTT_ADM1021 */
 
diff --git a/include/e500.h b/include/e500.h
index 1971eee..4c5eeb7 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -8,11 +8,16 @@
 
 #ifndef __ASSEMBLY__
 
+#ifndef CONFIG_NUM_CPUS
+#define CONFIG_NUM_CPUS 1
+#endif
+
 typedef struct
 {
-  unsigned long freqProcessor;
+  unsigned long freqProcessor[CONFIG_NUM_CPUS];
   unsigned long freqSystemBus;
   unsigned long freqDDRBus;
+  unsigned long freqLocalBus;
 } MPC85xx_SYS_INFO;
 
 #endif  /* _ASMLANGUAGE */
diff --git a/include/environment.h b/include/environment.h
index 1479eb6..ea6b4d1 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -39,13 +39,13 @@
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_OFFSET
-#  define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CFG_FLASH_BASE)
+#  define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
 # endif
 # if !defined(CONFIG_ENV_ADDR_REDUND) && defined(CONFIG_ENV_OFFSET_REDUND)
-#  define CONFIG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET_REDUND)
+#  define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET_REDUND)
 # endif
 # if defined(CONFIG_ENV_SECT_SIZE) || defined(CONFIG_ENV_SIZE)
 #  ifndef  CONFIG_ENV_SECT_SIZE
@@ -60,12 +60,12 @@
 # if defined(CONFIG_ENV_ADDR_REDUND) && !defined(CONFIG_ENV_SIZE_REDUND)
 #  define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
 # endif
-# if (CONFIG_ENV_ADDR >= CFG_MONITOR_BASE) && \
-     (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) <= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+# if (CONFIG_ENV_ADDR >= CONFIG_SYS_MONITOR_BASE) && \
+     (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) <= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #  define ENV_IS_EMBEDDED	1
 # endif
 # if defined(CONFIG_ENV_ADDR_REDUND) || defined(CONFIG_ENV_OFFSET_REDUND)
-#  define CFG_REDUNDAND_ENVIRONMENT	1
+#  define CONFIG_SYS_REDUNDAND_ENVIRONMENT	1
 # endif
 #endif	/* CONFIG_ENV_IS_IN_FLASH */
 
@@ -77,7 +77,7 @@
 #  error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_NAND"
 # endif
 # ifdef CONFIG_ENV_OFFSET_REDUND
-#  define CFG_REDUNDAND_ENVIRONMENT
+#  define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 # endif
 # ifdef CONFIG_ENV_IS_EMBEDDED
 #  define ENV_IS_EMBEDDED	1
@@ -90,7 +90,7 @@
 # include <linux/types.h>
 #endif
 
-#ifdef CFG_REDUNDAND_ENVIRONMENT
+#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
 # define ENV_HEADER_SIZE	(sizeof(uint32_t) + 1)
 #else
 # define ENV_HEADER_SIZE	(sizeof(uint32_t))
@@ -101,7 +101,7 @@
 
 typedef	struct environment_s {
 	uint32_t	crc;		/* CRC32 over data bytes	*/
-#ifdef CFG_REDUNDAND_ENVIRONMENT
+#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
 	unsigned char	flags;		/* active/obsolete flags	*/
 #endif
 	unsigned char	data[ENV_SIZE]; /* Environment data		*/
diff --git a/include/exports.h b/include/exports.h
index 6377875..0620e9e 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -25,6 +25,7 @@ char *getenv (char *name);
 int setenv (char *varname, char *varvalue);
 long simple_strtol(const char *cp,char **endp,unsigned int base);
 int strcmp(const char * cs,const char * ct);
+int ustrtoul(const char *cp, char **endp, unsigned int base);
 #ifdef CONFIG_HAS_UID
 void forceenv (char *varname, char *varvalue);
 #endif
diff --git a/include/fat.h b/include/fat.h
index 59de3fb..c8b9493 100644
--- a/include/fat.h
+++ b/include/fat.h
@@ -67,7 +67,7 @@
 #define ATTR_VFAT     (ATTR_RO | ATTR_HIDDEN | ATTR_SYS | ATTR_VOLUME)
 
 #define DELETED_FLAG	((char)0xe5) /* Marks deleted files when in name[0] */
-#define aRING		0x05	     /* Used to represent 'å' in name[0] */
+#define aRING		0x05	     /* Used as special character in name[0] */
 
 /* Indicates that the entry is the last long entry in a set of long
  * dir entries
diff --git a/include/fdt_support.h b/include/fdt_support.h
index ceaadc2..6062df9 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -28,6 +28,8 @@
 
 #include <fdt.h>
 
+u32 fdt_getprop_u32_default(void *fdt, const char *path, const char *prop,
+				const u32 dflt);
 int fdt_chosen(void *fdt, int force);
 int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force);
 void do_fixup_by_path(void *fdt, const char *path, const char *prop,
@@ -63,6 +65,11 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev);
 static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {}
 #endif
 
+#ifdef CONFIG_PCI
+#include <pci.h>
+int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose);
+#endif
+
 #ifdef CONFIG_OF_BOARD_SETUP
 void ft_board_setup(void *blob, bd_t *bd);
 void ft_cpu_setup(void *blob, bd_t *bd);
diff --git a/include/flash.h b/include/flash.h
index af8a7c0..8b8979e 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -24,7 +24,7 @@
 #ifndef _FLASH_H_
 #define _FLASH_H_
 
-#ifndef CFG_NO_FLASH
+#ifndef CONFIG_SYS_NO_FLASH
 /*-----------------------------------------------------------------------
  * FLASH Info: contains chip specific data, per FLASH bank
  */
@@ -33,9 +33,9 @@ typedef struct {
 	ulong	size;			/* total bank size in bytes		*/
 	ushort	sector_count;		/* number of erase units		*/
 	ulong	flash_id;		/* combined device & manufacturer code	*/
-	ulong	start[CFG_MAX_FLASH_SECT];   /* physical sector start addresses */
-	uchar	protect[CFG_MAX_FLASH_SECT]; /* sector protection status	*/
-#ifdef CFG_FLASH_CFI
+	ulong	start[CONFIG_SYS_MAX_FLASH_SECT];   /* virtual sector start address */
+	uchar	protect[CONFIG_SYS_MAX_FLASH_SECT]; /* sector protection status	*/
+#ifdef CONFIG_SYS_FLASH_CFI
 	uchar	portwidth;		/* the width of the port		*/
 	uchar	chipwidth;		/* the width of the chip		*/
 	ushort	buffer_size;		/* # of bytes in write buffer		*/
@@ -58,6 +58,8 @@ typedef struct {
 #endif
 } flash_info_t;
 
+typedef unsigned long flash_sect_t;
+
 /*
  * Values for the width of the port
  */
@@ -84,6 +86,9 @@ typedef struct {
 
 /* convert between bit value and numeric value */
 #define CFI_FLASH_SHIFT_WIDTH	3
+
+/* cfi-mtd device name */
+#define	CFI_MTD_DEV_NAME	"cfi-mtd"
 /* Prototypes */
 
 extern unsigned long flash_init (void);
@@ -91,6 +96,9 @@ extern void flash_print_info (flash_info_t *);
 extern int flash_erase	(flash_info_t *, int, int);
 extern int flash_sect_erase (ulong addr_first, ulong addr_last);
 extern int flash_sect_protect (int flag, ulong addr_first, ulong addr_last);
+extern int flash_sect_roundb (ulong *addr);
+extern unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect);
+extern void flash_set_verbose(uint);
 
 /* common/flash.c */
 extern void flash_protect (int flag, ulong from, ulong to, flash_info_t *info);
@@ -98,12 +106,17 @@ extern int flash_write (char *, ulong, ulong);
 extern flash_info_t *addr2info (ulong);
 extern int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
 
+/* drivers/mtd/cfi_mtd.c */
+#ifdef CONFIG_FLASH_CFI_MTD
+extern int cfi_mtd_init(void);
+#endif
+
 /* board/?/flash.c */
-#if defined(CFG_FLASH_PROTECTION)
+#if defined(CONFIG_SYS_FLASH_PROTECTION)
 extern int flash_real_protect(flash_info_t *info, long sector, int prot);
 extern void flash_read_user_serial(flash_info_t * info, void * buffer, int offset, int len);
 extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len);
-#endif	/* CFG_FLASH_PROTECTION */
+#endif	/* CONFIG_SYS_FLASH_PROTECTION */
 
 #ifdef CONFIG_FLASH_CFI_LEGACY
 extern ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info);
@@ -111,6 +124,9 @@ extern int jedec_flash_match(flash_info_t *info, ulong base);
 #define CFI_CMDSET_AMD_LEGACY		0xFFF0
 #endif
 
+#if defined(CONFIG_SYS_FLASH_CFI)
+extern flash_info_t *flash_get_info(ulong base);
+#endif
 
 /*-----------------------------------------------------------------------
  * return codes from flash_write():
@@ -485,6 +501,6 @@ extern int jedec_flash_match(flash_info_t *info, ulong base);
 #define FLASH_ERASE_TIMEOUT	120000	/* timeout for erasing in ms		*/
 #define FLASH_WRITE_TIMEOUT	500	/* timeout for writes  in ms		*/
 
-#endif /* !CFG_NO_FLASH */
+#endif /* !CONFIG_SYS_NO_FLASH */
 
 #endif /* _FLASH_H_ */
diff --git a/include/fpga.h b/include/fpga.h
index 52d93b1..a48b89b 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -40,13 +40,13 @@
 #endif
 
 /* CONFIG_FPGA bit assignments */
-#define CFG_FPGA_MAN(x)		(x)
-#define CFG_FPGA_DEV(x)		((x) << 8 )
-#define CFG_FPGA_IF(x)		((x) << 16 )
+#define CONFIG_SYS_FPGA_MAN(x)		(x)
+#define CONFIG_SYS_FPGA_DEV(x)		((x) << 8 )
+#define CONFIG_SYS_FPGA_IF(x)		((x) << 16 )
 
 /* FPGA Manufacturer bits in CONFIG_FPGA */
-#define CFG_FPGA_XILINX		CFG_FPGA_MAN( 0x1 )
-#define CFG_FPGA_ALTERA		CFG_FPGA_MAN( 0x2 )
+#define CONFIG_SYS_FPGA_XILINX		CONFIG_SYS_FPGA_MAN( 0x1 )
+#define CONFIG_SYS_FPGA_ALTERA		CONFIG_SYS_FPGA_MAN( 0x2 )
 
 
 /* fpga_xxxx function return value definitions */
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
new file mode 100644
index 0000000..0a5c5d6
--- /dev/null
+++ b/include/fsl_esdhc.h
@@ -0,0 +1,145 @@
+/*
+ * FSL SD/MMC Defines
+ *-------------------------------------------------------------------
+ *
+ * Copyright 2007-2008, Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *-------------------------------------------------------------------
+ *
+ */
+
+#ifndef  __FSL_ESDHC_H__
+#define	__FSL_ESDHC_H__
+
+/* FSL eSDHC-specific constants */
+#define SYSCTL			0x0002e02c
+#define SYSCTL_INITA		0x08000000
+#define SYSCTL_TIMEOUT_MASK	0x000f0000
+#define SYSCTL_CLOCK_MASK	0x00000fff
+#define SYSCTL_PEREN		0x00000004
+#define SYSCTL_HCKEN		0x00000002
+#define SYSCTL_IPGEN		0x00000001
+
+#define IRQSTAT			0x0002e030
+#define IRQSTAT_DMAE		(0x10000000)
+#define IRQSTAT_AC12E		(0x01000000)
+#define IRQSTAT_DEBE		(0x00400000)
+#define IRQSTAT_DCE		(0x00200000)
+#define IRQSTAT_DTOE		(0x00100000)
+#define IRQSTAT_CIE		(0x00080000)
+#define IRQSTAT_CEBE		(0x00040000)
+#define IRQSTAT_CCE		(0x00020000)
+#define IRQSTAT_CTOE		(0x00010000)
+#define IRQSTAT_CINT		(0x00000100)
+#define IRQSTAT_CRM		(0x00000080)
+#define IRQSTAT_CINS		(0x00000040)
+#define IRQSTAT_BRR		(0x00000020)
+#define IRQSTAT_BWR		(0x00000010)
+#define IRQSTAT_DINT		(0x00000008)
+#define IRQSTAT_BGE		(0x00000004)
+#define IRQSTAT_TC		(0x00000002)
+#define IRQSTAT_CC		(0x00000001)
+
+#define CMD_ERR		(IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
+#define DATA_ERR	(IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE)
+
+#define IRQSTATEN		0x0002e034
+#define IRQSTATEN_DMAE		(0x10000000)
+#define IRQSTATEN_AC12E		(0x01000000)
+#define IRQSTATEN_DEBE		(0x00400000)
+#define IRQSTATEN_DCE		(0x00200000)
+#define IRQSTATEN_DTOE		(0x00100000)
+#define IRQSTATEN_CIE		(0x00080000)
+#define IRQSTATEN_CEBE		(0x00040000)
+#define IRQSTATEN_CCE		(0x00020000)
+#define IRQSTATEN_CTOE		(0x00010000)
+#define IRQSTATEN_CINT		(0x00000100)
+#define IRQSTATEN_CRM		(0x00000080)
+#define IRQSTATEN_CINS		(0x00000040)
+#define IRQSTATEN_BRR		(0x00000020)
+#define IRQSTATEN_BWR		(0x00000010)
+#define IRQSTATEN_DINT		(0x00000008)
+#define IRQSTATEN_BGE		(0x00000004)
+#define IRQSTATEN_TC		(0x00000002)
+#define IRQSTATEN_CC		(0x00000001)
+
+#define PRSSTAT			0x0002e024
+#define PRSSTAT_CLSL		(0x00800000)
+#define PRSSTAT_WPSPL		(0x00080000)
+#define PRSSTAT_CDPL		(0x00040000)
+#define PRSSTAT_CINS		(0x00010000)
+#define PRSSTAT_BREN		(0x00000800)
+#define PRSSTAT_DLA		(0x00000004)
+#define PRSSTAT_CICHB		(0x00000002)
+#define PRSSTAT_CIDHB		(0x00000001)
+
+#define PROCTL			0x0002e028
+#define PROCTL_INIT		0x00000020
+#define PROCTL_DTW_4		0x00000002
+#define PROCTL_DTW_8		0x00000004
+
+#define CMDARG			0x0002e008
+
+#define XFERTYP			0x0002e00c
+#define XFERTYP_CMD(x)		((x & 0x3f) << 24)
+#define XFERTYP_CMDTYP_NORMAL	0x0
+#define XFERTYP_CMDTYP_SUSPEND	0x00400000
+#define XFERTYP_CMDTYP_RESUME	0x00800000
+#define XFERTYP_CMDTYP_ABORT	0x00c00000
+#define XFERTYP_DPSEL		0x00200000
+#define XFERTYP_CICEN		0x00100000
+#define XFERTYP_CCCEN		0x00080000
+#define XFERTYP_RSPTYP_NONE	0
+#define XFERTYP_RSPTYP_136	0x00010000
+#define XFERTYP_RSPTYP_48	0x00020000
+#define XFERTYP_RSPTYP_48_BUSY	0x00030000
+#define XFERTYP_MSBSEL		0x00000020
+#define XFERTYP_DTDSEL		0x00000010
+#define XFERTYP_AC12EN		0x00000004
+#define XFERTYP_BCEN		0x00000002
+#define XFERTYP_DMAEN		0x00000001
+
+#define CINS_TIMEOUT		1000
+
+#define DSADDR		0x2e004
+
+#define CMDRSP0		0x2e010
+#define CMDRSP1		0x2e014
+#define CMDRSP2		0x2e018
+#define CMDRSP3		0x2e01c
+
+#define DATPORT		0x2e020
+
+#define WML		0x2e044
+#define WML_WRITE	0x00010000
+
+#define BLKATTR		0x2e004
+#define BLKATTR_CNT(x)	((x & 0xffff) << 16)
+#define BLKATTR_SIZE(x)	(x & 0x1fff)
+#define MAX_BLK_CNT	0x7fff	/* so malloc will have enough room with 32M */
+
+#define ESDHC_HOSTCAPBLT_VS18	0x04000000
+#define ESDHC_HOSTCAPBLT_VS30	0x02000000
+#define ESDHC_HOSTCAPBLT_VS33	0x01000000
+#define ESDHC_HOSTCAPBLT_SRS	0x00800000
+#define ESDHC_HOSTCAPBLT_DMAS	0x00400000
+#define ESDHC_HOSTCAPBLT_HSS	0x00200000
+
+int fsl_esdhc_mmc_init(bd_t *bis);
+
+#endif  /* __FSL_ESDHC_H__ */
diff --git a/include/galileo/core.h b/include/galileo/core.h
index 49f4dd2..c277509 100644
--- a/include/galileo/core.h
+++ b/include/galileo/core.h
@@ -23,13 +23,13 @@ extern unsigned int INTERNAL_REG_BASE_ADDR;
 #define GT_64260	0  /* includes both 64260A and 64260B */
 #define GT_64261	1
 
-#if (CFG_GT_6426x == GT_64260)
+#if (CONFIG_SYS_GT_6426x == GT_64260)
 #ifdef CONFIG_ETHER_PORT_MII
 #define GAL_ETH_DEVS 2
 #else
 #define GAL_ETH_DEVS 3
 #endif
-#elif (CFG_GT_6426x == GT_64261)
+#elif (CONFIG_SYS_GT_6426x == GT_64261)
 #define GAL_ETH_DEVS 2
 #else
 #define GAL_ETH_DEVS 3	/* default to a 64260 */
diff --git a/include/hush.h b/include/hush.h
index 20e48db..0805ff3 100644
--- a/include/hush.h
+++ b/include/hush.h
@@ -32,4 +32,10 @@ extern int u_boot_hush_start(void);
 extern int parse_string_outer(char *, int);
 extern int parse_file_outer(void);
 
+int set_local_var(const char *s, int flg_export);
+void unset_local_var(const char *name);
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+extern int hush_init_var (void);
+#endif
 #endif
diff --git a/include/i2c.h b/include/i2c.h
index a51c164..f8a59a6 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -47,24 +47,47 @@
 #define I2C_RXTX_LEN	128	/* maximum tx/rx buffer length */
 
 #if defined(CONFIG_I2C_MULTI_BUS)
-#define CFG_MAX_I2C_BUS		2
+#define CONFIG_SYS_MAX_I2C_BUS		2
 #define I2C_GET_BUS()		i2c_get_bus_num()
 #define I2C_SET_BUS(a)		i2c_set_bus_num(a)
 #else
-#define CFG_MAX_I2C_BUS		1
+#define CONFIG_SYS_MAX_I2C_BUS		1
 #define I2C_GET_BUS()		0
 #define I2C_SET_BUS(a)
 #endif
 
 /* define the I2C bus number for RTC and DTT if not already done */
-#if !defined(CFG_RTC_BUS_NUM)
-#define CFG_RTC_BUS_NUM		0
+#if !defined(CONFIG_SYS_RTC_BUS_NUM)
+#define CONFIG_SYS_RTC_BUS_NUM		0
 #endif
-#if !defined(CFG_DTT_BUS_NUM)
-#define CFG_DTT_BUS_NUM		0
+#if !defined(CONFIG_SYS_DTT_BUS_NUM)
+#define CONFIG_SYS_DTT_BUS_NUM		0
+#endif
+#if !defined(CONFIG_SYS_SPD_BUS_NUM)
+#define CONFIG_SYS_SPD_BUS_NUM		0
+#endif
+
+#ifndef I2C_SOFT_DECLARATIONS
+# if defined(CONFIG_MPC8260)
+#  define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
+# elif defined(CONFIG_8xx)
+#  define I2C_SOFT_DECLARATIONS	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+# else
+#  define I2C_SOFT_DECLARATIONS
+# endif
+#endif
+
+#ifdef CONFIG_8xx
+/* Set default values for the I2C bus speed and slave address on 8xx. In the
+ * future, we'll define these in all 8xx board config files.
+ */
+#ifndef	CONFIG_SYS_I2C_SPEED
+#define	CONFIG_SYS_I2C_SPEED	50000
+#endif
+
+#ifndef	CONFIG_SYS_I2C_SLAVE
+#define	CONFIG_SYS_I2C_SLAVE	0xFE
 #endif
-#if !defined(CFG_SPD_BUS_NUM)
-#define CFG_SPD_BUS_NUM		0
 #endif
 
 /*
@@ -72,10 +95,33 @@
  * repeatedly to change the speed and slave addresses.
  */
 void i2c_init(int speed, int slaveaddr);
-#ifdef CFG_I2C_INIT_BOARD
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
 void i2c_init_board(void);
 #endif
 
+#if defined(CONFIG_I2C_MUX)
+
+typedef struct _mux {
+	uchar	chip;
+	uchar	channel;
+	char	*name;
+	struct _mux	*next;
+} I2C_MUX;
+
+typedef struct _mux_device {
+	int	busid;
+	I2C_MUX	*mux;	/* List of muxes, to reach the device */
+	struct _mux_device	*next;
+} I2C_MUX_DEVICE;
+
+int	i2c_mux_add_device(I2C_MUX_DEVICE *dev);
+
+I2C_MUX_DEVICE	*i2c_mux_search_device(int id);
+I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf);
+int i2x_mux_select_mux(int bus);
+int i2c_mux_ident_muxstring_f (uchar *buf);
+#endif
+
 /*
  * Probe the given I2C chip address.  Returns 0 if a chip responded,
  * not 0 on failure.
@@ -100,8 +146,38 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
 /*
  * Utility routines to read/write registers.
  */
-uchar i2c_reg_read (uchar chip, uchar reg);
-void  i2c_reg_write(uchar chip, uchar reg, uchar val);
+static inline u8 i2c_reg_read(u8 addr, u8 reg)
+{
+	u8 buf;
+
+#ifdef CONFIG_8xx
+	/* MPC8xx needs this.  Maybe one day we can get rid of it. */
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+#ifdef DEBUG
+	printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg);
+#endif
+
+	i2c_read(addr, reg, 1, &buf, 1);
+
+	return buf;
+}
+
+static inline void i2c_reg_write(u8 addr, u8 reg, u8 val)
+{
+#ifdef CONFIG_8xx
+	/* MPC8xx needs this.  Maybe one day we can get rid of it. */
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+#ifdef DEBUG
+	printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n",
+	       __func__, addr, reg, val);
+#endif
+
+	i2c_write(addr, reg, 1, &val, 1);
+}
 
 /*
  * Functions for setting the current I2C bus and its speed
diff --git a/include/i8042.h b/include/i8042.h
index f77239f..1395289 100644
--- a/include/i8042.h
+++ b/include/i8042.h
@@ -35,9 +35,9 @@
 
 /* defines */
 
-#define I8042_DATA_REG      (CFG_ISA_IO + 0x0060)    /* keyboard i/o buffer */
-#define I8042_STATUS_REG    (CFG_ISA_IO + 0x0064)    /* keyboard status read */
-#define I8042_COMMAND_REG   (CFG_ISA_IO + 0x0064)    /* keyboard ctrl write */
+#define I8042_DATA_REG      (CONFIG_SYS_ISA_IO + 0x0060)    /* keyboard i/o buffer */
+#define I8042_STATUS_REG    (CONFIG_SYS_ISA_IO + 0x0064)    /* keyboard status read */
+#define I8042_COMMAND_REG   (CONFIG_SYS_ISA_IO + 0x0064)    /* keyboard ctrl write */
 
 #define KBD_US              0        /* default US layout */
 #define KBD_GER             1        /* german layout */
diff --git a/include/ide.h b/include/ide.h
index 222f4f8..ddb9579 100644
--- a/include/ide.h
+++ b/include/ide.h
@@ -26,7 +26,7 @@
 
 #define	IDE_BUS(dev)	(dev >> 1)
 
-#define	ATA_CURR_BASE(dev)	(CFG_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])
+#define	ATA_CURR_BASE(dev)	(CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])
 
 #ifdef CONFIG_IDE_LED
 
@@ -40,7 +40,7 @@
 
 #endif /* CONFIG_IDE_LED */
 
-#ifdef CFG_64BIT_LBA
+#ifdef CONFIG_SYS_64BIT_LBA
 typedef uint64_t lbaint_t;
 #else
 typedef ulong lbaint_t;
diff --git a/include/image.h b/include/image.h
index 82e6345..74a1240 100644
--- a/include/image.h
+++ b/include/image.h
@@ -33,26 +33,24 @@
 #ifndef __IMAGE_H__
 #define __IMAGE_H__
 
-#include <asm/byteorder.h>
-#include <command.h>
-
-#ifndef USE_HOSTCC
-#include <lmb.h>
-#include <linux/string.h>
-#include <asm/u-boot.h>
-
-#else
+#if USE_HOSTCC
+#include <endian.h>
 
 /* new uImage format support enabled on host */
 #define CONFIG_FIT		1
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
 
+#else
+
+#include <lmb.h>
+#include <linux/string.h>
+#include <asm/u-boot.h>
+#include <asm/byteorder.h>
+
 #endif /* USE_HOSTCC */
 
-#if defined(CONFIG_FIT) && !defined(CONFIG_OF_LIBFDT)
-#error "CONFIG_OF_LIBFDT not enabled, required by CONFIG_FIT!"
-#endif
+#include <command.h>
 
 #if defined(CONFIG_FIT)
 #include <fdt.h>
@@ -228,6 +226,7 @@ typedef struct bootm_headers {
 #endif
 #endif
 
+#ifndef USE_HOSTCC
 	image_info_t	os;		/* os image info */
 	ulong		ep;		/* entry point of OS */
 
@@ -238,8 +237,25 @@ typedef struct bootm_headers {
 #endif
 	ulong		ft_len;		/* length of flat device tree */
 
+	ulong		initrd_start;
+	ulong		initrd_end;
+	ulong		cmdline_start;
+	ulong		cmdline_end;
+	bd_t		*kbd;
+#endif
+
 	int		verify;		/* getenv("verify")[0] != 'n' */
-	int		valid;		/* set to 1 if we've set values in the header */
+
+#define	BOOTM_STATE_START	(0x00000001)
+#define	BOOTM_STATE_LOADOS	(0x00000002)
+#define	BOOTM_STATE_RAMDISK	(0x00000004)
+#define	BOOTM_STATE_FDT		(0x00000008)
+#define	BOOTM_STATE_OS_CMDLINE	(0x00000010)
+#define	BOOTM_STATE_OS_BD_T	(0x00000020)
+#define	BOOTM_STATE_OS_PREP	(0x00000040)
+#define	BOOTM_STATE_OS_GO	(0x00000080)
+	int		state;
+
 #ifndef USE_HOSTCC
 	struct lmb	lmb;		/* for memory mgmt */
 #endif
@@ -322,23 +338,23 @@ static inline uint32_t image_get_header_size (void)
 	{ \
 		return uimage_to_cpu (hdr->ih_##f); \
 	}
-image_get_hdr_l (magic);
-image_get_hdr_l (hcrc);
-image_get_hdr_l (time);
-image_get_hdr_l (size);
-image_get_hdr_l (load);
-image_get_hdr_l (ep);
-image_get_hdr_l (dcrc);
+image_get_hdr_l (magic);	/* image_get_magic */
+image_get_hdr_l (hcrc);		/* image_get_hcrc */
+image_get_hdr_l (time);		/* image_get_time */
+image_get_hdr_l (size);		/* image_get_size */
+image_get_hdr_l (load);		/* image_get_load */
+image_get_hdr_l (ep);		/* image_get_ep */
+image_get_hdr_l (dcrc);		/* image_get_dcrc */
 
 #define image_get_hdr_b(f) \
 	static inline uint8_t image_get_##f(image_header_t *hdr) \
 	{ \
 		return hdr->ih_##f; \
 	}
-image_get_hdr_b (os);
-image_get_hdr_b (arch);
-image_get_hdr_b (type);
-image_get_hdr_b (comp);
+image_get_hdr_b (os);		/* image_get_os */
+image_get_hdr_b (arch);		/* image_get_arch */
+image_get_hdr_b (type);		/* image_get_type */
+image_get_hdr_b (comp);		/* image_get_comp */
 
 static inline char *image_get_name (image_header_t *hdr)
 {
@@ -380,23 +396,23 @@ static inline ulong image_get_image_end (image_header_t *hdr)
 	{ \
 		hdr->ih_##f = cpu_to_uimage (val); \
 	}
-image_set_hdr_l (magic);
-image_set_hdr_l (hcrc);
-image_set_hdr_l (time);
-image_set_hdr_l (size);
-image_set_hdr_l (load);
-image_set_hdr_l (ep);
-image_set_hdr_l (dcrc);
+image_set_hdr_l (magic);	/* image_set_magic */
+image_set_hdr_l (hcrc);		/* image_set_hcrc */
+image_set_hdr_l (time);		/* image_set_time */
+image_set_hdr_l (size);		/* image_set_size */
+image_set_hdr_l (load);		/* image_set_load */
+image_set_hdr_l (ep);		/* image_set_ep */
+image_set_hdr_l (dcrc);		/* image_set_dcrc */
 
 #define image_set_hdr_b(f) \
 	static inline void image_set_##f(image_header_t *hdr, uint8_t val) \
 	{ \
 		hdr->ih_##f = val; \
 	}
-image_set_hdr_b (os);
-image_set_hdr_b (arch);
-image_set_hdr_b (type);
-image_set_hdr_b (comp);
+image_set_hdr_b (os);		/* image_set_os */
+image_set_hdr_b (arch);		/* image_set_arch */
+image_set_hdr_b (type);		/* image_set_type */
+image_set_hdr_b (comp);		/* image_set_comp */
 
 static inline void image_set_name (image_header_t *hdr, const char *name)
 {
diff --git a/include/iomux.h b/include/iomux.h
new file mode 100644
index 0000000..257c1f7
--- /dev/null
+++ b/include/iomux.h
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ *This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _IO_MUX_H
+#define _IO_MUX_H
+
+#include <devices.h>
+
+/*
+ * Stuff required to support console multiplexing.
+ */
+
+/*
+ * Pointers to devices used for each file type.  Defined in console.c
+ * but storage is allocated in iomux.c.
+ */
+extern device_t **console_devices[MAX_FILES];
+/*
+ * The count of devices assigned to each FILE.  Defined in console.c
+ * and populated in iomux.c.
+ */
+extern int cd_count[MAX_FILES];
+
+int iomux_doenv(const int, const char *);
+void iomux_printdevs(const int);
+device_t *search_device(int, char *);
+
+#endif /* _IO_MUX_H */
diff --git a/include/jffs2/jffs2.h b/include/jffs2/jffs2.h
index d142cd1..ed96bab 100644
--- a/include/jffs2/jffs2.h
+++ b/include/jffs2/jffs2.h
@@ -50,6 +50,9 @@
 #define JFFS2_EMPTY_BITMASK 0xffff
 #define JFFS2_DIRTY_BITMASK 0x0000
 
+/* Summary node MAGIC marker */
+#define JFFS2_SUM_MAGIC	0x02851885
+
 /* We only allow a single char for length, and 0xFF is empty flash so
    we don't want it confused with a real length. Hence max 254.
 */
@@ -89,6 +92,7 @@
 #define JFFS2_NODETYPE_INODE (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 2)
 #define JFFS2_NODETYPE_CLEANMARKER (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3)
 #define JFFS2_NODETYPE_PADDING (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 4)
+#define JFFS2_NODETYPE_SUMMARY (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 6)
 
 /* Maybe later... */
 /*#define JFFS2_NODETYPE_CHECKPOINT (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3) */
@@ -166,9 +170,24 @@ struct jffs2_raw_inode
 /*	__u8 data[dsize]; */
 } __attribute__((packed));
 
+struct jffs2_raw_summary
+{
+	__u16 magic;
+	__u16 nodetype; 	/* = JFFS2_NODETYPE_SUMMARY */
+	__u32 totlen;
+	__u32 hdr_crc;
+	__u32 sum_num;	/* number of sum entries*/
+	__u32 cln_mkr;	/* clean marker size, 0 = no cleanmarker */
+	__u32 padded;	/* sum of the size of padding nodes */
+	__u32 sum_crc;	/* summary information crc */
+	__u32 node_crc; 	/* node crc */
+	__u32 sum[0]; 	/* inode summary info */
+};
+
 union jffs2_node_union {
 	struct jffs2_raw_inode i;
 	struct jffs2_raw_dirent d;
+	struct jffs2_raw_summary s;
 	struct jffs2_unknown_node u;
 } __attribute__((packed));
 
diff --git a/include/jffs2/load_kernel.h b/include/jffs2/load_kernel.h
index 551fd0c..8b2720e 100644
--- a/include/jffs2/load_kernel.h
+++ b/include/jffs2/load_kernel.h
@@ -50,6 +50,7 @@ struct part_info {
 	u32 offset;			/* offset within device */
 	void *jffs2_priv;		/* used internaly by jffs2 */
 	u32 mask_flags;			/* kernel MTD mask flags */
+	u32 sector_size;		/* size of sector */
 	struct mtd_device *dev;		/* parent device */
 };
 
@@ -73,4 +74,9 @@ struct mtdids {
 #define putLabeledWord(x, y)	printf("%s %08x\n", x, (unsigned int)y)
 #define led_blink(x, y, z, a)
 
+/* common/cmd_jffs2.c */
+extern int mtdparts_init(void);
+extern int find_dev_and_part(const char *id, struct mtd_device **dev,
+				u8 *part_num, struct part_info **part);
+
 #endif /* load_kernel_h */
diff --git a/include/lcd.h b/include/lcd.h
index 44ac8ef..512221e 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -197,6 +197,8 @@ void	lcd_putc	(const char c);
 void	lcd_puts	(const char *s);
 void	lcd_printf	(const char *fmt, ...);
 
+/* Allow boards to customize the information displayed */
+void lcd_show_board_info(void);
 
 /************************************************************************/
 /* ** BITMAP DISPLAY SUPPORT						*/
@@ -211,8 +213,8 @@ void	lcd_printf	(const char *fmt, ...);
  *  the LCD controller and memory allocation. Someone has to know what
  *  is connected, as we can't autodetect anything.
  */
-#define CFG_HIGH	0	/* Pins are active high			*/
-#define CFG_LOW		1	/* Pins are active low			*/
+#define CONFIG_SYS_HIGH	0	/* Pins are active high			*/
+#define CONFIG_SYS_LOW		1	/* Pins are active low			*/
 
 #define LCD_MONOCHROME	0
 #define LCD_COLOR2	1
diff --git a/include/lh7a40x.h b/include/lh7a40x.h
index c897a7c..09a463c 100644
--- a/include/lh7a40x.h
+++ b/include/lh7a40x.h
@@ -273,7 +273,7 @@ typedef struct {
 #define LH7A40X_GPIOINT_PTR     ((lh7a40x_gpioint_t*) LH7A40X_GPIOINT_BASE)
 
 /* Embedded SRAM */
-#define CFG_SRAM_BASE	(0xB0000000)
-#define CFG_SRAM_SIZE	(80*1024)	/* 80kB */
+#define CONFIG_SYS_SRAM_BASE	(0xB0000000)
+#define CONFIG_SYS_SRAM_SIZE	(80*1024)	/* 80kB */
 
 #endif  /* __LH7A40X_H__ */
diff --git a/include/libfdt.h b/include/libfdt.h
index 94c35e3..ce374fd 100644
--- a/include/libfdt.h
+++ b/include/libfdt.h
@@ -122,7 +122,7 @@
 /* Low-level functions (you probably don't need these)                */
 /**********************************************************************/
 
-const void *fdt_offset_ptr(const void *fdt, int offset, int checklen);
+const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen);
 static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen)
 {
 	return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen);
@@ -459,6 +459,32 @@ static inline void *fdt_getprop_w(void *fdt, int nodeoffset,
 uint32_t fdt_get_phandle(const void *fdt, int nodeoffset);
 
 /**
+ * fdt_get_alias_namelen - get alias based on substring
+ * @fdt: pointer to the device tree blob
+ * @name: name of the alias th look up
+ * @namelen: number of characters of name to consider
+ *
+ * Identical to fdt_get_alias(), but only examine the first namelen
+ * characters of name for matching the alias name.
+ */
+const char *fdt_get_alias_namelen(const void *fdt,
+				  const char *name, int namelen);
+
+/**
+ * fdt_get_alias - retreive the path referenced by a given alias
+ * @fdt: pointer to the device tree blob
+ * @name: name of the alias th look up
+ *
+ * fdt_get_alias() retrieves the value of a given alias.  That is, the
+ * value of the property named 'name' in the node /aliases.
+ *
+ * returns:
+ *	a pointer to the expansion of the alias named 'name', of it exists
+ *	NULL, if the given alias or the /aliases node does not exist
+ */
+const char *fdt_get_alias(const void *fdt, const char *name);
+
+/**
  * fdt_get_path - determine the full path of a node
  * @fdt: pointer to the device tree blob
  * @nodeoffset: offset of the node whose path to find
diff --git a/include/libfdt_env.h b/include/libfdt_env.h
index 671c3a8..ea474a5 100644
--- a/include/libfdt_env.h
+++ b/include/libfdt_env.h
@@ -24,20 +24,30 @@
 #ifdef USE_HOSTCC
 #include <stdint.h>
 #include <string.h>
+#include <endian.h>
+#include <byteswap.h>
 #else
 #include <linux/string.h>
 #include <linux/types.h>
+#include <asm/byteorder.h>
 #endif /* USE_HOSTCC */
 
 #include <stddef.h>
-#include <asm/byteorder.h>
 extern struct fdt_header *working_fdt;  /* Pointer to the working fdt */
 
-#define fdt32_to_cpu(x)		__be32_to_cpu(x)
-#define cpu_to_fdt32(x)		__cpu_to_be32(x)
-#define fdt64_to_cpu(x)		__be64_to_cpu(x)
-#define cpu_to_fdt64(x)		__cpu_to_be64(x)
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#define fdt32_to_cpu(x)		bswap_32(x)
+#define cpu_to_fdt32(x)		bswap_32(x)
+#define fdt64_to_cpu(x)		bswap_64(x)
+#define cpu_to_fdt64(x)		bswap_64(x)
+#else
+#define fdt32_to_cpu(x)		(x)
+#define cpu_to_fdt32(x)		(x)
+#define fdt64_to_cpu(x)		(x)
+#define cpu_to_fdt64(x)		(x)
+#endif
 
+#ifndef USE_HOSTCC
 /*
  * Types for `void *' pointers.
  *
@@ -49,5 +59,6 @@ typedef unsigned long int       uintptr_t;
 #else
 typedef unsigned int            uintptr_t;
 #endif
+#endif /* not USE_HOSTCC */
 
 #endif /* _LIBFDT_ENV_H */
diff --git a/include/linux/crc32.h b/include/linux/crc32.h
new file mode 100644
index 0000000..ac4aed1
--- /dev/null
+++ b/include/linux/crc32.h
@@ -0,0 +1,27 @@
+/*
+ * crc32.h
+ * See linux/lib/crc32.c for license and changes
+ */
+#ifndef _LINUX_CRC32_H
+#define _LINUX_CRC32_H
+
+#include <linux/types.h>
+/* #include <linux/bitrev.h> */
+
+extern u32  crc32_le(u32 crc, unsigned char const *p, size_t len);
+/* extern u32  crc32_be(u32 crc, unsigned char const *p, size_t len); */
+
+#define crc32(seed, data, length)  crc32_le(seed, (unsigned char const *)data, length)
+
+/*
+ * Helpers for hash table generation of ethernet nics:
+ *
+ * Ethernet sends the least significant bit of a byte first, thus crc32_le
+ * is used. The output of crc32_le is bit reversed [most significant bit
+ * is in bit nr 0], thus it must be reversed before use. Except for
+ * nics that bit swap the result internally...
+ */
+/* #define ether_crc(length, data)    bitrev32(crc32_le(~0, data, length)) */
+/* #define ether_crc_le(length, data) crc32_le(~0, data, length) */
+
+#endif /* _LINUX_CRC32_H */
diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h
index abf8f1a..7db2546 100644
--- a/include/linux/mtd/bbm.h
+++ b/include/linux/mtd/bbm.h
@@ -18,8 +18,8 @@
 #define __LINUX_MTD_BBM_H
 
 /* The maximum number of NAND chips in an array */
-#ifndef NAND_MAX_CHIPS
-#define NAND_MAX_CHIPS		8
+#ifndef CONFIG_SYS_NAND_MAX_CHIPS
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
 #endif
 
 /**
@@ -48,10 +48,10 @@
  */
 struct nand_bbt_descr {
 	int options;
-	int pages[NAND_MAX_CHIPS];
+	int pages[CONFIG_SYS_NAND_MAX_CHIPS];
 	int offs;
 	int veroffs;
-	uint8_t version[NAND_MAX_CHIPS];
+	uint8_t version[CONFIG_SYS_NAND_MAX_CHIPS];
 	int len;
 	int maxblocks;
 	int reserved_block_code;
diff --git a/include/linux/mtd/blktrans.h b/include/linux/mtd/blktrans.h
index d1ded51..32acb6c 100644
--- a/include/linux/mtd/blktrans.h
+++ b/include/linux/mtd/blktrans.h
@@ -1,6 +1,4 @@
 /*
- * $Id: blktrans.h,v 1.6 2005/11/07 11:14:54 gleixner Exp $
- *
  * (C) 2003 David Woodhouse <dwmw2@infradead.org>
  *
  * Interface to Linux block layer for MTD 'translation layers'.
diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h
index 12de284..ba29d53 100644
--- a/include/linux/mtd/doc2000.h
+++ b/include/linux/mtd/doc2000.h
@@ -6,8 +6,6 @@
  * Copyright (C) 2002-2003 Greg Ungerer <gerg@snapgear.com>
  * Copyright (C) 2002-2003 SnapGear Inc
  *
- * $Id: doc2000.h,v 1.25 2005/11/07 11:14:54 gleixner Exp $
- *
  * Released under GPL
  */
 
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 55d33dd..354e3a0 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -1,6 +1,4 @@
 /*
- * $Id: mtd.h,v 1.61 2005/11/07 11:14:54 gleixner Exp $
- *
  * Copyright (C) 1999-2003 David Woodhouse <dwmw2@infradead.org> et al.
  *
  * Released under GPL
@@ -132,7 +130,7 @@ struct mtd_info {
 	u_int32_t oobavail;  /* Available OOB bytes per block */
 
 	/* Kernel-only stuff starts here. */
-	char *name;
+	const char *name;
 	int index;
 
 	/* ecc layout structure pointer - read only ! */
@@ -144,18 +142,36 @@ struct mtd_info {
 	int numeraseregions;
 	struct mtd_erase_region_info *eraseregions;
 
+	/*
+	 * Erase is an asynchronous operation.  Device drivers are supposed
+	 * to call instr->callback() whenever the operation completes, even
+	 * if it completes with a failure.
+	 * Callers are supposed to pass a callback function and wait for it
+	 * to be called before writing to the block.
+	 */
 	int (*erase) (struct mtd_info *mtd, struct erase_info *instr);
 
 	/* This stuff for eXecute-In-Place */
-	int (*point) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char **mtdbuf);
+	/* phys is optional and may be set to NULL */
+	int (*point) (struct mtd_info *mtd, loff_t from, size_t len,
+			size_t *retlen, void **virt, phys_addr_t *phys);
 
 	/* We probably shouldn't allow XIP if the unpoint isn't a NULL */
-	void (*unpoint) (struct mtd_info *mtd, u_char * addr, loff_t from, size_t len);
+	void (*unpoint) (struct mtd_info *mtd, loff_t from, size_t len);
 
 
 	int (*read) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
 	int (*write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf);
 
+	/* In blackbox flight recorder like scenarios we want to make successful
+	   writes in interrupt context. panic_write() is only intended to be
+	   called when its known the kernel is about to panic and we need the
+	   write to succeed. Since the kernel is not going to be running for much
+	   longer, this function can break locks and delay to ensure the write
+	   succeeds (but not sleep). */
+
+	int (*panic_write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf);
+
 	int (*read_oob) (struct mtd_info *mtd, loff_t from,
 			 struct mtd_oob_ops *ops);
 	int (*write_oob) (struct mtd_info *mtd, loff_t to,
@@ -274,7 +290,11 @@ static inline void mtd_erase_callback(struct erase_info *instr)
 			printk(KERN_INFO args);		\
 	} while(0)
 #else /* CONFIG_MTD_DEBUG */
-#define MTDDEBUG(n, args...) do { } while(0)
+#define MTDDEBUG(n, args...)				\
+	do {						\
+		if (0)					\
+			printk(KERN_INFO args);		\
+	} while(0)
 #endif /* CONFIG_MTD_DEBUG */
 
 #endif /* __MTD_MTD_H__ */
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 7ac72de..a4ad571 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -1,12 +1,10 @@
 /*
  *  linux/include/linux/mtd/nand.h
  *
- *  Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
+ *  Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org>
  *                     Steven J. Hill <sjhill@realitydiluted.com>
  *		       Thomas Gleixner <tglx@linutronix.de>
  *
- * $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
@@ -31,6 +29,7 @@
 
 #include "linux/mtd/compat.h"
 #include "linux/mtd/mtd.h"
+#include "linux/mtd/bbm.h"
 
 
 struct mtd_info;
@@ -47,11 +46,6 @@ extern void nand_release (struct mtd_info *mtd);
 /* Internal helper for board drivers which need to override command function */
 extern void nand_wait_ready(struct mtd_info *mtd);
 
-/* The maximum number of NAND chips in an array */
-#ifndef NAND_MAX_CHIPS
-#define NAND_MAX_CHIPS		8
-#endif
-
 /* This constant declares the max. oobsize / page, which
  * is supported now. If you add a chip with bigger oobsize/page
  * adjust this accordingly.
@@ -190,6 +184,9 @@ typedef enum {
 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
+/* Large page NAND with SOFT_ECC should support subpage reads */
+#define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
+					&& (chip->page_shift > 9))
 
 /* Mask to zero out the chip options, which come from the id table */
 #define NAND_CHIPOPTIONS_MSK	(0x0000ffff & ~NAND_NO_AUTOINCR)
@@ -278,6 +275,10 @@ struct nand_ecc_ctrl {
 	int			(*read_page)(struct mtd_info *mtd,
 					     struct nand_chip *chip,
 					     uint8_t *buf);
+	int			(*read_subpage)(struct mtd_info *mtd,
+					     struct nand_chip *chip,
+					     uint32_t offs, uint32_t len,
+					     uint8_t *buf);
 	void			(*write_page)(struct mtd_info *mtd,
 					      struct nand_chip *chip,
 					      const uint8_t *buf);
@@ -435,6 +436,7 @@ struct nand_chip {
 #define NAND_MFR_STMICRO	0x20
 #define NAND_MFR_HYNIX		0xad
 #define NAND_MFR_MICRON		0x2c
+#define NAND_MFR_AMD		0x01
 
 /**
  * struct nand_flash_dev - NAND Flash Device ID Structure
@@ -470,79 +472,6 @@ struct nand_manufacturers {
 extern struct nand_flash_dev nand_flash_ids[];
 extern struct nand_manufacturers nand_manuf_ids[];
 
-#ifndef NAND_MAX_CHIPS
-#define NAND_MAX_CHIPS 8
-#endif
-
-/**
- * struct nand_bbt_descr - bad block table descriptor
- * @options:	options for this descriptor
- * @pages:	the page(s) where we find the bbt, used with option BBT_ABSPAGE
- *		when bbt is searched, then we store the found bbts pages here.
- *		Its an array and supports up to 8 chips now
- * @offs:	offset of the pattern in the oob area of the page
- * @veroffs:	offset of the bbt version counter in the oob are of the page
- * @version:	version read from the bbt page during scan
- * @len:	length of the pattern, if 0 no pattern check is performed
- * @maxblocks:	maximum number of blocks to search for a bbt. This number of
- *		blocks is reserved at the end of the device where the tables are
- *		written.
- * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
- *              bad) block in the stored bbt
- * @pattern:	pattern to identify bad block table or factory marked good /
- *		bad blocks, can be NULL, if len = 0
- *
- * Descriptor for the bad block table marker and the descriptor for the
- * pattern which identifies good and bad blocks. The assumption is made
- * that the pattern and the version count are always located in the oob area
- * of the first block.
- */
-struct nand_bbt_descr {
-	int	options;
-	int	pages[NAND_MAX_CHIPS];
-	int	offs;
-	int	veroffs;
-	uint8_t	version[NAND_MAX_CHIPS];
-	int	len;
-	int	maxblocks;
-	int	reserved_block_code;
-	uint8_t	*pattern;
-};
-
-/* Options for the bad block table descriptors */
-
-/* The number of bits used per block in the bbt on the device */
-#define NAND_BBT_NRBITS_MSK	0x0000000F
-#define NAND_BBT_1BIT		0x00000001
-#define NAND_BBT_2BIT		0x00000002
-#define NAND_BBT_4BIT		0x00000004
-#define NAND_BBT_8BIT		0x00000008
-/* The bad block table is in the last good block of the device */
-#define	NAND_BBT_LASTBLOCK	0x00000010
-/* The bbt is at the given page, else we must scan for the bbt */
-#define NAND_BBT_ABSPAGE	0x00000020
-/* The bbt is at the given page, else we must scan for the bbt */
-#define NAND_BBT_SEARCH		0x00000040
-/* bbt is stored per chip on multichip devices */
-#define NAND_BBT_PERCHIP	0x00000080
-/* bbt has a version counter at offset veroffs */
-#define NAND_BBT_VERSION	0x00000100
-/* Create a bbt if none axists */
-#define NAND_BBT_CREATE		0x00000200
-/* Search good / bad pattern through all pages of a block */
-#define NAND_BBT_SCANALLPAGES	0x00000400
-/* Scan block empty during good / bad block scan */
-#define NAND_BBT_SCANEMPTY	0x00000800
-/* Write bbt if neccecary */
-#define NAND_BBT_WRITE		0x00001000
-/* Read and write back block contents when writing bbt */
-#define NAND_BBT_SAVECONTENT	0x00002000
-/* Search good / bad pattern on the first and the second page */
-#define NAND_BBT_SCAN2NDPAGE	0x00004000
-
-/* The maximum number of blocks to scan for a bbt */
-#define NAND_BBT_SCAN_MAXBLOCKS	4
-
 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
 extern int nand_default_bbt(struct mtd_info *mtd);
diff --git a/include/linux/mtd/nand_ecc.h b/include/linux/mtd/nand_ecc.h
index 12c5bc3..090da50 100644
--- a/include/linux/mtd/nand_ecc.h
+++ b/include/linux/mtd/nand_ecc.h
@@ -3,8 +3,6 @@
  *
  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  *
- * $Id: nand_ecc.h,v 1.4 2004/06/17 02:35:02 dbrown Exp $
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
diff --git a/include/linux/mtd/nand_legacy.h b/include/linux/mtd/nand_legacy.h
index 99eafbb..4334448 100644
--- a/include/linux/mtd/nand_legacy.h
+++ b/include/linux/mtd/nand_legacy.h
@@ -40,6 +40,11 @@
 #error This module is for the legacy NAND support
 #endif
 
+/* The maximum number of NAND chips in an array */
+#ifndef CONFIG_SYS_NAND_MAX_CHIPS
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+#endif
+
 /*
  * Standard NAND flash commands
  */
diff --git a/include/linux/mtd/nftl.h b/include/linux/mtd/nftl.h
index 6731a16..fe22e0d 100644
--- a/include/linux/mtd/nftl.h
+++ b/include/linux/mtd/nftl.h
@@ -1,6 +1,4 @@
 /*
- * $Id: nftl.h,v 1.16 2004/06/30 14:49:00 dbrown Exp $
- *
  * (C) 1999-2003 David Woodhouse <dwmw2@infradead.org>
  */
 
@@ -43,6 +41,11 @@ struct NFTLrecord {
 int NFTL_mount(struct NFTLrecord *s);
 int NFTL_formatblock(struct NFTLrecord *s, int block);
 
+int nftl_read_oob(struct mtd_info *mtd, loff_t offs, size_t len,
+		  size_t *retlen, uint8_t *buf);
+int nftl_write_oob(struct mtd_info *mtd, loff_t offs, size_t len,
+		   size_t *retlen, uint8_t *buf);
+
 #ifndef NFTL_MAJOR
 #define NFTL_MAJOR 93
 #endif
diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h
index 420eb14..2597e34 100644
--- a/include/linux/mtd/onenand.h
+++ b/include/linux/mtd/onenand.h
@@ -30,14 +30,10 @@ extern void onenand_release (struct mtd_info *mtd);
 
 /**
  * struct onenand_bufferram - OneNAND BufferRAM Data
- * @param block		block address in BufferRAM
- * @param page		page address in BufferRAM
- * @param valid		valid flag
+ * @param blockpage	block & page address in BufferRAM
  */
 struct onenand_bufferram {
-	int block;
-	int page;
-	int valid;
+	int blockpage;
 };
 
 /**
@@ -51,6 +47,7 @@ struct onenand_bufferram {
  * @param page_shift	[INTERN] number of address bits in a page
  * @param ppb_shift	[INTERN] number of address bits in a pages per block
  * @param page_mask	[INTERN] a page per block mask
+ * @param writesize	[INTERN] a real page size
  * @param bufferam_index	[INTERN] BufferRAM index
  * @param bufferam	[INTERN] BufferRAM info
  * @param readw		[REPLACEABLE] hardware specific function for read short
@@ -69,6 +66,8 @@ struct onenand_chip {
 	void __iomem *base;
 	unsigned int chipsize;
 	unsigned int device_id;
+	unsigned int version_id;
+	unsigned int density_mask;
 	unsigned int options;
 
 	unsigned int erase_shift;
@@ -80,26 +79,36 @@ struct onenand_chip {
 	unsigned int bufferram_index;
 	struct onenand_bufferram bufferram[MAX_BUFFERRAM];
 
-	int (*command) (struct mtd_info * mtd, int cmd, loff_t address,
+	int (*command) (struct mtd_info *mtd, int cmd, loff_t address,
 			size_t len);
-	int (*wait) (struct mtd_info * mtd, int state);
-	int (*read_bufferram) (struct mtd_info * mtd, int area,
+	int (*wait) (struct mtd_info *mtd, int state);
+	int (*bbt_wait) (struct mtd_info *mtd, int state);
+	int (*read_bufferram) (struct mtd_info *mtd, loff_t addr, int area,
 			       unsigned char *buffer, int offset, size_t count);
-	int (*write_bufferram) (struct mtd_info * mtd, int area,
+	int (*read_spareram) (struct mtd_info *mtd, loff_t addr, int area,
+			       unsigned char *buffer, int offset, size_t count);
+	int (*write_bufferram) (struct mtd_info *mtd, loff_t addr, int area,
 				const unsigned char *buffer, int offset,
 				size_t count);
-	unsigned short (*read_word) (void __iomem * addr);
-	void (*write_word) (unsigned short value, void __iomem * addr);
-	void (*mmcontrol) (struct mtd_info * mtd, int sync_read);
+	unsigned short (*read_word) (void __iomem *addr);
+	void (*write_word) (unsigned short value, void __iomem *addr);
+	void (*mmcontrol) (struct mtd_info *mtd, int sync_read);
 	int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 	int (*scan_bbt)(struct mtd_info *mtd);
 
+	unsigned char		*main_buf;
+	unsigned char		*spare_buf;
+#ifdef DONT_USE_UBOOT
+	spinlock_t chip_lock;
+	wait_queue_head_t wq;
+#endif
 	int state;
-	unsigned char *page_buf;
-	unsigned char *oob_buf;
+	unsigned char		*page_buf;
+	unsigned char		*oob_buf;
 
 	struct nand_oobinfo *autooob;
-	struct nand_ecclayout *ecclayout;
+	int			subpagesize;
+	struct nand_ecclayout	*ecclayout;
 
 	void *bbm;
 
@@ -124,7 +133,9 @@ struct onenand_chip {
 /*
  * Options bits
  */
-#define ONENAND_CONT_LOCK		(0x0001)
+#define ONENAND_HAS_CONT_LOCK		(0x0001)
+#define ONENAND_HAS_UNLOCK_ALL		(0x0002)
+#define ONENAND_HAS_2PLANE		(0x0004)
 #define ONENAND_PAGEBUF_ALLOC		(0x1000)
 #define ONENAND_OOBBUF_ALLOC		(0x2000)
 
@@ -132,7 +143,6 @@ struct onenand_chip {
  * OneNAND Flash Manufacturer ID Codes
  */
 #define ONENAND_MFR_SAMSUNG	0xec
-#define ONENAND_MFR_UNKNOWN	0x00
 
 /**
  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h
index 6a8aa28..fc63380 100644
--- a/include/linux/mtd/onenand_regs.h
+++ b/include/linux/mtd/onenand_regs.h
@@ -67,12 +67,16 @@
 /*
  * Device ID Register F001h (R)
  */
+#define ONENAND_DEVICE_DENSITY_MASK	(0xf)
 #define ONENAND_DEVICE_DENSITY_SHIFT	(4)
 #define ONENAND_DEVICE_IS_DDP		(1 << 3)
 #define ONENAND_DEVICE_IS_DEMUX		(1 << 2)
 #define ONENAND_DEVICE_VCC_MASK		(0x3)
 
 #define ONENAND_DEVICE_DENSITY_512Mb	(0x002)
+#define ONENAND_DEVICE_DENSITY_1Gb	(0x003)
+#define ONENAND_DEVICE_DENSITY_2Gb	(0x004)
+#define ONENAND_DEVICE_DENSITY_4Gb	(0x005)
 
 /*
  * Version ID Register F002h (R)
@@ -110,9 +114,12 @@
 #define ONENAND_CMD_READOOB		(0x13)
 #define ONENAND_CMD_PROG		(0x80)
 #define ONENAND_CMD_PROGOOB		(0x1A)
+#define ONENAND_CMD_2X_PROG		(0x7D)
+#define ONENAND_CMD_2X_CACHE_PROG	(0x7F)
 #define ONENAND_CMD_UNLOCK		(0x23)
 #define ONENAND_CMD_LOCK		(0x2A)
 #define ONENAND_CMD_LOCK_TIGHT		(0x2C)
+#define ONENAND_CMD_UNLOCK_ALL		(0x27)
 #define ONENAND_CMD_ERASE		(0x94)
 #define ONENAND_CMD_RESET		(0xF0)
 #define ONENAND_CMD_READID		(0x90)
diff --git a/include/linux/mtd/partitions.h b/include/linux/mtd/partitions.h
new file mode 100644
index 0000000..1016675
--- /dev/null
+++ b/include/linux/mtd/partitions.h
@@ -0,0 +1,84 @@
+/*
+ * MTD partitioning layer definitions
+ *
+ * (C) 2000 Nicolas Pitre <nico@cam.org>
+ *
+ * This code is GPL
+ *
+ * $Id: partitions.h,v 1.17 2005/11/07 11:14:55 gleixner Exp $
+ */
+
+#ifndef MTD_PARTITIONS_H
+#define MTD_PARTITIONS_H
+
+#include <linux/types.h>
+
+
+/*
+ * Partition definition structure:
+ *
+ * An array of struct partition is passed along with a MTD object to
+ * add_mtd_partitions() to create them.
+ *
+ * For each partition, these fields are available:
+ * name: string that will be used to label the partition's MTD device.
+ * size: the partition size; if defined as MTDPART_SIZ_FULL, the partition
+ * 	will extend to the end of the master MTD device.
+ * offset: absolute starting position within the master MTD device; if
+ * 	defined as MTDPART_OFS_APPEND, the partition will start where the
+ * 	previous one ended; if MTDPART_OFS_NXTBLK, at the next erase block.
+ * mask_flags: contains flags that have to be masked (removed) from the
+ * 	master MTD flag set for the corresponding MTD partition.
+ * 	For example, to force a read-only partition, simply adding
+ * 	MTD_WRITEABLE to the mask_flags will do the trick.
+ *
+ * Note: writeable partitions require their size and offset be
+ * erasesize aligned (e.g. use MTDPART_OFS_NEXTBLK).
+ */
+
+struct mtd_partition {
+	char *name;			/* identifier string */
+	u_int32_t size;			/* partition size */
+	u_int32_t offset;		/* offset within the master MTD space */
+	u_int32_t mask_flags;		/* master MTD flags to mask out for this partition */
+	struct nand_ecclayout *ecclayout;	/* out of band layout for this partition (NAND only)*/
+	struct mtd_info **mtdp;		/* pointer to store the MTD object */
+};
+
+#define MTDPART_OFS_NXTBLK	(-2)
+#define MTDPART_OFS_APPEND	(-1)
+#define MTDPART_SIZ_FULL	(0)
+
+
+int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int);
+int del_mtd_partitions(struct mtd_info *);
+
+#if 0
+/*
+ * Functions dealing with the various ways of partitioning the space
+ */
+
+struct mtd_part_parser {
+	struct list_head list;
+	struct module *owner;
+	const char *name;
+	int (*parse_fn)(struct mtd_info *, struct mtd_partition **, unsigned long);
+};
+
+extern int register_mtd_parser(struct mtd_part_parser *parser);
+extern int deregister_mtd_parser(struct mtd_part_parser *parser);
+extern int parse_mtd_partitions(struct mtd_info *master, const char **types,
+				struct mtd_partition **pparts, unsigned long origin);
+
+#define put_partition_parser(p) do { module_put((p)->owner); } while(0)
+
+struct device;
+struct device_node;
+
+int __devinit of_mtd_parse_partitions(struct device *dev,
+				      struct mtd_info *mtd,
+				      struct device_node *node,
+				      struct mtd_partition **pparts);
+#endif
+
+#endif
diff --git a/include/linux/mtd/ubi-header.h b/include/linux/mtd/ubi-header.h
deleted file mode 100644
index fa479c7..0000000
--- a/include/linux/mtd/ubi-header.h
+++ /dev/null
@@ -1,360 +0,0 @@
-/*
- * Copyright (c) International Business Machines Corp., 2006
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
- * the GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Authors: Artem Bityutskiy (Битюцкий �ртём)
- *          Thomas Gleixner
- *          Frank Haverkamp
- *          Oliver Lohmann
- *          Andreas Arnez
- */
-
-/*
- * This file defines the layout of UBI headers and all the other UBI on-flash
- * data structures. May be included by user-space.
- */
-
-#ifndef __UBI_HEADER_H__
-#define __UBI_HEADER_H__
-
-#include <asm/byteorder.h>
-
-/* The version of UBI images supported by this implementation */
-#define UBI_VERSION 1
-
-/* The highest erase counter value supported by this implementation */
-#define UBI_MAX_ERASECOUNTER 0x7FFFFFFF
-
-/* The initial CRC32 value used when calculating CRC checksums */
-#define UBI_CRC32_INIT 0xFFFFFFFFU
-
-/* Erase counter header magic number (ASCII "UBI#") */
-#define UBI_EC_HDR_MAGIC  0x55424923
-/* Volume identifier header magic number (ASCII "UBI!") */
-#define UBI_VID_HDR_MAGIC 0x55424921
-
-/*
- * Volume type constants used in the volume identifier header.
- *
- * @UBI_VID_DYNAMIC: dynamic volume
- * @UBI_VID_STATIC: static volume
- */
-enum {
-	UBI_VID_DYNAMIC = 1,
-	UBI_VID_STATIC  = 2
-};
-
-/*
- * Compatibility constants used by internal volumes.
- *
- * @UBI_COMPAT_DELETE: delete this internal volume before anything is written
- * to the flash
- * @UBI_COMPAT_RO: attach this device in read-only mode
- * @UBI_COMPAT_PRESERVE: preserve this internal volume - do not touch its
- * physical eraseblocks, don't allow the wear-leveling unit to move them
- * @UBI_COMPAT_REJECT: reject this UBI image
- */
-enum {
-	UBI_COMPAT_DELETE   = 1,
-	UBI_COMPAT_RO       = 2,
-	UBI_COMPAT_PRESERVE = 4,
-	UBI_COMPAT_REJECT   = 5
-};
-
-/*
- * ubi16_t/ubi32_t/ubi64_t - 16, 32, and 64-bit integers used in UBI on-flash
- * data structures.
- */
-typedef struct {
-	uint16_t int16;
-} __attribute__ ((packed)) ubi16_t;
-
-typedef struct {
-	uint32_t int32;
-} __attribute__ ((packed)) ubi32_t;
-
-typedef struct {
-	uint64_t int64;
-} __attribute__ ((packed)) ubi64_t;
-
-/*
- * In this implementation of UBI uses the big-endian format for on-flash
- * integers. The below are the corresponding conversion macros.
- */
-#define cpu_to_ubi16(x) ((ubi16_t){__cpu_to_be16(x)})
-#define ubi16_to_cpu(x) ((uint16_t)__be16_to_cpu((x).int16))
-
-#define cpu_to_ubi32(x) ((ubi32_t){__cpu_to_be32(x)})
-#define ubi32_to_cpu(x) ((uint32_t)__be32_to_cpu((x).int32))
-
-#define cpu_to_ubi64(x) ((ubi64_t){__cpu_to_be64(x)})
-#define ubi64_to_cpu(x) ((uint64_t)__be64_to_cpu((x).int64))
-
-/* Sizes of UBI headers */
-#define UBI_EC_HDR_SIZE  sizeof(struct ubi_ec_hdr)
-#define UBI_VID_HDR_SIZE sizeof(struct ubi_vid_hdr)
-
-/* Sizes of UBI headers without the ending CRC */
-#define UBI_EC_HDR_SIZE_CRC  (UBI_EC_HDR_SIZE  - sizeof(ubi32_t))
-#define UBI_VID_HDR_SIZE_CRC (UBI_VID_HDR_SIZE - sizeof(ubi32_t))
-
-/**
- * struct ubi_ec_hdr - UBI erase counter header.
- * @magic: erase counter header magic number (%UBI_EC_HDR_MAGIC)
- * @version: version of UBI implementation which is supposed to accept this
- * UBI image
- * @padding1: reserved for future, zeroes
- * @ec: the erase counter
- * @vid_hdr_offset: where the VID header starts
- * @data_offset: where the user data start
- * @padding2: reserved for future, zeroes
- * @hdr_crc: erase counter header CRC checksum
- *
- * The erase counter header takes 64 bytes and has a plenty of unused space for
- * future usage. The unused fields are zeroed. The @version field is used to
- * indicate the version of UBI implementation which is supposed to be able to
- * work with this UBI image. If @version is greater then the current UBI
- * version, the image is rejected. This may be useful in future if something
- * is changed radically. This field is duplicated in the volume identifier
- * header.
- *
- * The @vid_hdr_offset and @data_offset fields contain the offset of the the
- * volume identifier header and user data, relative to the beginning of the
- * physical eraseblock. These values have to be the same for all physical
- * eraseblocks.
- */
-struct ubi_ec_hdr {
-	ubi32_t magic;
-	uint8_t version;
-	uint8_t padding1[3];
-	ubi64_t ec; /* Warning: the current limit is 31-bit anyway! */
-	ubi32_t vid_hdr_offset;
-	ubi32_t data_offset;
-	uint8_t padding2[36];
-	ubi32_t hdr_crc;
-} __attribute__ ((packed));
-
-/**
- * struct ubi_vid_hdr - on-flash UBI volume identifier header.
- * @magic: volume identifier header magic number (%UBI_VID_HDR_MAGIC)
- * @version: UBI implementation version which is supposed to accept this UBI
- * image (%UBI_VERSION)
- * @vol_type: volume type (%UBI_VID_DYNAMIC or %UBI_VID_STATIC)
- * @copy_flag: if this logical eraseblock was copied from another physical
- * eraseblock (for wear-leveling reasons)
- * @compat: compatibility of this volume (%0, %UBI_COMPAT_DELETE,
- * %UBI_COMPAT_IGNORE, %UBI_COMPAT_PRESERVE, or %UBI_COMPAT_REJECT)
- * @vol_id: ID of this volume
- * @lnum: logical eraseblock number
- * @leb_ver: version of this logical eraseblock (IMPORTANT: obsolete, to be
- * removed, kept only for not breaking older UBI users)
- * @data_size: how many bytes of data this logical eraseblock contains
- * @used_ebs: total number of used logical eraseblocks in this volume
- * @data_pad: how many bytes at the end of this physical eraseblock are not
- * used
- * @data_crc: CRC checksum of the data stored in this logical eraseblock
- * @padding1: reserved for future, zeroes
- * @sqnum: sequence number
- * @padding2: reserved for future, zeroes
- * @hdr_crc: volume identifier header CRC checksum
- *
- * The @sqnum is the value of the global sequence counter at the time when this
- * VID header was created. The global sequence counter is incremented each time
- * UBI writes a new VID header to the flash, i.e. when it maps a logical
- * eraseblock to a new physical eraseblock. The global sequence counter is an
- * unsigned 64-bit integer and we assume it never overflows. The @sqnum
- * (sequence number) is used to distinguish between older and newer versions of
- * logical eraseblocks.
- *
- * There are 2 situations when there may be more then one physical eraseblock
- * corresponding to the same logical eraseblock, i.e., having the same @vol_id
- * and @lnum values in the volume identifier header. Suppose we have a logical
- * eraseblock L and it is mapped to the physical eraseblock P.
- *
- * 1. Because UBI may erase physical eraseblocks asynchronously, the following
- * situation is possible: L is asynchronously erased, so P is scheduled for
- * erasure, then L is written to,i.e. mapped to another physical eraseblock P1,
- * so P1 is written to, then an unclean reboot happens. Result - there are 2
- * physical eraseblocks P and P1 corresponding to the same logical eraseblock
- * L. But P1 has greater sequence number, so UBI picks P1 when it attaches the
- * flash.
- *
- * 2. From time to time UBI moves logical eraseblocks to other physical
- * eraseblocks for wear-leveling reasons. If, for example, UBI moves L from P
- * to P1, and an unclean reboot happens before P is physically erased, there
- * are two physical eraseblocks P and P1 corresponding to L and UBI has to
- * select one of them when the flash is attached. The @sqnum field says which
- * PEB is the original (obviously P will have lower @sqnum) and the copy. But
- * it is not enough to select the physical eraseblock with the higher sequence
- * number, because the unclean reboot could have happen in the middle of the
- * copying process, so the data in P is corrupted. It is also not enough to
- * just select the physical eraseblock with lower sequence number, because the
- * data there may be old (consider a case if more data was added to P1 after
- * the copying). Moreover, the unclean reboot may happen when the erasure of P
- * was just started, so it result in unstable P, which is "mostly" OK, but
- * still has unstable bits.
- *
- * UBI uses the @copy_flag field to indicate that this logical eraseblock is a
- * copy. UBI also calculates data CRC when the data is moved and stores it at
- * the @data_crc field of the copy (P1). So when UBI needs to pick one physical
- * eraseblock of two (P or P1), the @copy_flag of the newer one (P1) is
- * examined. If it is cleared, the situation* is simple and the newer one is
- * picked. If it is set, the data CRC of the copy (P1) is examined. If the CRC
- * checksum is correct, this physical eraseblock is selected (P1). Otherwise
- * the older one (P) is selected.
- *
- * Note, there is an obsolete @leb_ver field which was used instead of @sqnum
- * in the past. But it is not used anymore and we keep it in order to be able
- * to deal with old UBI images. It will be removed at some point.
- *
- * There are 2 sorts of volumes in UBI: user volumes and internal volumes.
- * Internal volumes are not seen from outside and are used for various internal
- * UBI purposes. In this implementation there is only one internal volume - the
- * layout volume. Internal volumes are the main mechanism of UBI extensions.
- * For example, in future one may introduce a journal internal volume. Internal
- * volumes have their own reserved range of IDs.
- *
- * The @compat field is only used for internal volumes and contains the "degree
- * of their compatibility". It is always zero for user volumes. This field
- * provides a mechanism to introduce UBI extensions and to be still compatible
- * with older UBI binaries. For example, if someone introduced a journal in
- * future, he would probably use %UBI_COMPAT_DELETE compatibility for the
- * journal volume.  And in this case, older UBI binaries, which know nothing
- * about the journal volume, would just delete this volume and work perfectly
- * fine. This is similar to what Ext2fs does when it is fed by an Ext3fs image
- * - it just ignores the Ext3fs journal.
- *
- * The @data_crc field contains the CRC checksum of the contents of the logical
- * eraseblock if this is a static volume. In case of dynamic volumes, it does
- * not contain the CRC checksum as a rule. The only exception is when the
- * data of the physical eraseblock was moved by the wear-leveling unit, then
- * the wear-leveling unit calculates the data CRC and stores it in the
- * @data_crc field. And of course, the @copy_flag is %in this case.
- *
- * The @data_size field is used only for static volumes because UBI has to know
- * how many bytes of data are stored in this eraseblock. For dynamic volumes,
- * this field usually contains zero. The only exception is when the data of the
- * physical eraseblock was moved to another physical eraseblock for
- * wear-leveling reasons. In this case, UBI calculates CRC checksum of the
- * contents and uses both @data_crc and @data_size fields. In this case, the
- * @data_size field contains data size.
- *
- * The @used_ebs field is used only for static volumes and indicates how many
- * eraseblocks the data of the volume takes. For dynamic volumes this field is
- * not used and always contains zero.
- *
- * The @data_pad is calculated when volumes are created using the alignment
- * parameter. So, effectively, the @data_pad field reduces the size of logical
- * eraseblocks of this volume. This is very handy when one uses block-oriented
- * software (say, cramfs) on top of the UBI volume.
- */
-struct ubi_vid_hdr {
-	ubi32_t magic;
-	uint8_t version;
-	uint8_t vol_type;
-	uint8_t copy_flag;
-	uint8_t compat;
-	ubi32_t vol_id;
-	ubi32_t lnum;
-	ubi32_t leb_ver; /* obsolete, to be removed, don't use */
-	ubi32_t data_size;
-	ubi32_t used_ebs;
-	ubi32_t data_pad;
-	ubi32_t data_crc;
-	uint8_t padding1[4];
-	ubi64_t sqnum;
-	uint8_t padding2[12];
-	ubi32_t hdr_crc;
-} __attribute__ ((packed));
-
-/* Internal UBI volumes count */
-#define UBI_INT_VOL_COUNT 1
-
-/*
- * Starting ID of internal volumes. There is reserved room for 4096 internal
- * volumes.
- */
-#define UBI_INTERNAL_VOL_START (0x7FFFFFFF - 4096)
-
-/* The layout volume contains the volume table */
-
-#define UBI_LAYOUT_VOL_ID        UBI_INTERNAL_VOL_START
-#define UBI_LAYOUT_VOLUME_EBS    2
-#define UBI_LAYOUT_VOLUME_NAME   "layout volume"
-#define UBI_LAYOUT_VOLUME_COMPAT UBI_COMPAT_REJECT
-
-/* The maximum number of volumes per one UBI device */
-#define UBI_MAX_VOLUMES 128
-
-/* The maximum volume name length */
-#define UBI_VOL_NAME_MAX 127
-
-/* Size of the volume table record */
-#define UBI_VTBL_RECORD_SIZE sizeof(struct ubi_vtbl_record)
-
-/* Size of the volume table record without the ending CRC */
-#define UBI_VTBL_RECORD_SIZE_CRC (UBI_VTBL_RECORD_SIZE - sizeof(ubi32_t))
-
-/**
- * struct ubi_vtbl_record - a record in the volume table.
- * @reserved_pebs: how many physical eraseblocks are reserved for this volume
- * @alignment: volume alignment
- * @data_pad: how many bytes are unused at the end of the each physical
- * eraseblock to satisfy the requested alignment
- * @vol_type: volume type (%UBI_DYNAMIC_VOLUME or %UBI_STATIC_VOLUME)
- * @upd_marker: if volume update was started but not finished
- * @name_len: volume name length
- * @name: the volume name
- * @padding2: reserved, zeroes
- * @crc: a CRC32 checksum of the record
- *
- * The volume table records are stored in the volume table, which is stored in
- * the layout volume. The layout volume consists of 2 logical eraseblock, each
- * of which contains a copy of the volume table (i.e., the volume table is
- * duplicated). The volume table is an array of &struct ubi_vtbl_record
- * objects indexed by the volume ID.
- *
- * If the size of the logical eraseblock is large enough to fit
- * %UBI_MAX_VOLUMES records, the volume table contains %UBI_MAX_VOLUMES
- * records. Otherwise, it contains as many records as it can fit (i.e., size of
- * logical eraseblock divided by sizeof(struct ubi_vtbl_record)).
- *
- * The @upd_marker flag is used to implement volume update. It is set to %1
- * before update and set to %0 after the update. So if the update operation was
- * interrupted, UBI knows that the volume is corrupted.
- *
- * The @alignment field is specified when the volume is created and cannot be
- * later changed. It may be useful, for example, when a block-oriented file
- * system works on top of UBI. The @data_pad field is calculated using the
- * logical eraseblock size and @alignment. The alignment must be multiple to the
- * minimal flash I/O unit. If @alignment is 1, all the available space of
- * the physical eraseblocks is used.
- *
- * Empty records contain all zeroes and the CRC checksum of those zeroes.
- */
-struct ubi_vtbl_record {
-	ubi32_t reserved_pebs;
-	ubi32_t alignment;
-	ubi32_t data_pad;
-	uint8_t vol_type;
-	uint8_t upd_marker;
-	ubi16_t name_len;
-	uint8_t name[UBI_VOL_NAME_MAX+1];
-	uint8_t padding2[24];
-	ubi32_t crc;
-} __attribute__ ((packed));
-
-#endif /* !__UBI_HEADER_H__ */
diff --git a/include/linux/mtd/ubi.h b/include/linux/mtd/ubi.h
new file mode 100644
index 0000000..4b3e06c
--- /dev/null
+++ b/include/linux/mtd/ubi.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) International Business Machines Corp., 2006
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ * the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Author: Artem Bityutskiy (Битюцкий �ртём)
+ */
+
+#ifndef __LINUX_UBI_H__
+#define __LINUX_UBI_H__
+
+/* #include <asm/ioctl.h> */
+#include <linux/types.h>
+#include <mtd/ubi-user.h>
+
+/*
+ * enum ubi_open_mode - UBI volume open mode constants.
+ *
+ * UBI_READONLY: read-only mode
+ * UBI_READWRITE: read-write mode
+ * UBI_EXCLUSIVE: exclusive mode
+ */
+enum {
+	UBI_READONLY = 1,
+	UBI_READWRITE,
+	UBI_EXCLUSIVE
+};
+
+/**
+ * struct ubi_volume_info - UBI volume description data structure.
+ * @vol_id: volume ID
+ * @ubi_num: UBI device number this volume belongs to
+ * @size: how many physical eraseblocks are reserved for this volume
+ * @used_bytes: how many bytes of data this volume contains
+ * @used_ebs: how many physical eraseblocks of this volume actually contain any
+ * data
+ * @vol_type: volume type (%UBI_DYNAMIC_VOLUME or %UBI_STATIC_VOLUME)
+ * @corrupted: non-zero if the volume is corrupted (static volumes only)
+ * @upd_marker: non-zero if the volume has update marker set
+ * @alignment: volume alignment
+ * @usable_leb_size: how many bytes are available in logical eraseblocks of
+ * this volume
+ * @name_len: volume name length
+ * @name: volume name
+ * @cdev: UBI volume character device major and minor numbers
+ *
+ * The @corrupted flag is only relevant to static volumes and is always zero
+ * for dynamic ones. This is because UBI does not care about dynamic volume
+ * data protection and only cares about protecting static volume data.
+ *
+ * The @upd_marker flag is set if the volume update operation was interrupted.
+ * Before touching the volume data during the update operation, UBI first sets
+ * the update marker flag for this volume. If the volume update operation was
+ * further interrupted, the update marker indicates this. If the update marker
+ * is set, the contents of the volume is certainly damaged and a new volume
+ * update operation has to be started.
+ *
+ * To put it differently, @corrupted and @upd_marker fields have different
+ * semantics:
+ *     o the @corrupted flag means that this static volume is corrupted for some
+ *       reasons, but not because an interrupted volume update
+ *     o the @upd_marker field means that the volume is damaged because of an
+ *       interrupted update operation.
+ *
+ * I.e., the @corrupted flag is never set if the @upd_marker flag is set.
+ *
+ * The @used_bytes and @used_ebs fields are only really needed for static
+ * volumes and contain the number of bytes stored in this static volume and how
+ * many eraseblock this data occupies. In case of dynamic volumes, the
+ * @used_bytes field is equivalent to @size*@usable_leb_size, and the @used_ebs
+ * field is equivalent to @size.
+ *
+ * In general, logical eraseblock size is a property of the UBI device, not
+ * of the UBI volume. Indeed, the logical eraseblock size depends on the
+ * physical eraseblock size and on how much bytes UBI headers consume. But
+ * because of the volume alignment (@alignment), the usable size of logical
+ * eraseblocks if a volume may be less. The following equation is true:
+ * 	@usable_leb_size = LEB size - (LEB size mod @alignment),
+ * where LEB size is the logical eraseblock size defined by the UBI device.
+ *
+ * The alignment is multiple to the minimal flash input/output unit size or %1
+ * if all the available space is used.
+ *
+ * To put this differently, alignment may be considered is a way to change
+ * volume logical eraseblock sizes.
+ */
+struct ubi_volume_info {
+	int ubi_num;
+	int vol_id;
+	int size;
+	long long used_bytes;
+	int used_ebs;
+	int vol_type;
+	int corrupted;
+	int upd_marker;
+	int alignment;
+	int usable_leb_size;
+	int name_len;
+	const char *name;
+	dev_t cdev;
+};
+
+/**
+ * struct ubi_device_info - UBI device description data structure.
+ * @ubi_num: ubi device number
+ * @leb_size: logical eraseblock size on this UBI device
+ * @min_io_size: minimal I/O unit size
+ * @ro_mode: if this device is in read-only mode
+ * @cdev: UBI character device major and minor numbers
+ *
+ * Note, @leb_size is the logical eraseblock size offered by the UBI device.
+ * Volumes of this UBI device may have smaller logical eraseblock size if their
+ * alignment is not equivalent to %1.
+ */
+struct ubi_device_info {
+	int ubi_num;
+	int leb_size;
+	int min_io_size;
+	int ro_mode;
+	dev_t cdev;
+};
+
+/* UBI descriptor given to users when they open UBI volumes */
+struct ubi_volume_desc;
+
+int ubi_get_device_info(int ubi_num, struct ubi_device_info *di);
+void ubi_get_volume_info(struct ubi_volume_desc *desc,
+			 struct ubi_volume_info *vi);
+struct ubi_volume_desc *ubi_open_volume(int ubi_num, int vol_id, int mode);
+struct ubi_volume_desc *ubi_open_volume_nm(int ubi_num, const char *name,
+					   int mode);
+void ubi_close_volume(struct ubi_volume_desc *desc);
+int ubi_leb_read(struct ubi_volume_desc *desc, int lnum, char *buf, int offset,
+		 int len, int check);
+int ubi_leb_write(struct ubi_volume_desc *desc, int lnum, const void *buf,
+		  int offset, int len, int dtype);
+int ubi_leb_change(struct ubi_volume_desc *desc, int lnum, const void *buf,
+		   int len, int dtype);
+int ubi_leb_erase(struct ubi_volume_desc *desc, int lnum);
+int ubi_leb_unmap(struct ubi_volume_desc *desc, int lnum);
+int ubi_leb_map(struct ubi_volume_desc *desc, int lnum, int dtype);
+int ubi_is_mapped(struct ubi_volume_desc *desc, int lnum);
+
+/*
+ * This function is the same as the 'ubi_leb_read()' function, but it does not
+ * provide the checking capability.
+ */
+static inline int ubi_read(struct ubi_volume_desc *desc, int lnum, char *buf,
+			   int offset, int len)
+{
+	return ubi_leb_read(desc, lnum, buf, offset, len, 0);
+}
+
+/*
+ * This function is the same as the 'ubi_leb_write()' functions, but it does
+ * not have the data type argument.
+ */
+static inline int ubi_write(struct ubi_volume_desc *desc, int lnum,
+			    const void *buf, int offset, int len)
+{
+	return ubi_leb_write(desc, lnum, buf, offset, len, UBI_UNKNOWN);
+}
+
+/*
+ * This function is the same as the 'ubi_leb_change()' functions, but it does
+ * not have the data type argument.
+ */
+static inline int ubi_change(struct ubi_volume_desc *desc, int lnum,
+				    const void *buf, int len)
+{
+	return ubi_leb_change(desc, lnum, buf, len, UBI_UNKNOWN);
+}
+
+#endif /* !__LINUX_UBI_H__ */
diff --git a/include/linux/rbtree.h b/include/linux/rbtree.h
new file mode 100644
index 0000000..6ff28e0
--- /dev/null
+++ b/include/linux/rbtree.h
@@ -0,0 +1,160 @@
+/*
+  Red Black Trees
+  (C) 1999  Andrea Arcangeli <andrea@suse.de>
+
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; if not, write to the Free Software
+  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+  linux/include/linux/rbtree.h
+
+  To use rbtrees you'll have to implement your own insert and search cores.
+  This will avoid us to use callbacks and to drop drammatically performances.
+  I know it's not the cleaner way,  but in C (not in C++) to get
+  performances and genericity...
+
+  Some example of insert and search follows here. The search is a plain
+  normal search over an ordered tree. The insert instead must be implemented
+  int two steps: as first thing the code must insert the element in
+  order as a red leaf in the tree, then the support library function
+  rb_insert_color() must be called. Such function will do the
+  not trivial work to rebalance the rbtree if necessary.
+
+-----------------------------------------------------------------------
+static inline struct page * rb_search_page_cache(struct inode * inode,
+						 unsigned long offset)
+{
+	struct rb_node * n = inode->i_rb_page_cache.rb_node;
+	struct page * page;
+
+	while (n)
+	{
+		page = rb_entry(n, struct page, rb_page_cache);
+
+		if (offset < page->offset)
+			n = n->rb_left;
+		else if (offset > page->offset)
+			n = n->rb_right;
+		else
+			return page;
+	}
+	return NULL;
+}
+
+static inline struct page * __rb_insert_page_cache(struct inode * inode,
+						   unsigned long offset,
+						   struct rb_node * node)
+{
+	struct rb_node ** p = &inode->i_rb_page_cache.rb_node;
+	struct rb_node * parent = NULL;
+	struct page * page;
+
+	while (*p)
+	{
+		parent = *p;
+		page = rb_entry(parent, struct page, rb_page_cache);
+
+		if (offset < page->offset)
+			p = &(*p)->rb_left;
+		else if (offset > page->offset)
+			p = &(*p)->rb_right;
+		else
+			return page;
+	}
+
+	rb_link_node(node, parent, p);
+
+	return NULL;
+}
+
+static inline struct page * rb_insert_page_cache(struct inode * inode,
+						 unsigned long offset,
+						 struct rb_node * node)
+{
+	struct page * ret;
+	if ((ret = __rb_insert_page_cache(inode, offset, node)))
+		goto out;
+	rb_insert_color(node, &inode->i_rb_page_cache);
+ out:
+	return ret;
+}
+-----------------------------------------------------------------------
+*/
+
+#ifndef	_LINUX_RBTREE_H
+#define	_LINUX_RBTREE_H
+
+#include <linux/stddef.h>
+
+struct rb_node
+{
+	unsigned long  rb_parent_color;
+#define	RB_RED		0
+#define	RB_BLACK	1
+	struct rb_node *rb_right;
+	struct rb_node *rb_left;
+} __attribute__((aligned(sizeof(long))));
+    /* The alignment might seem pointless, but allegedly CRIS needs it */
+
+struct rb_root
+{
+	struct rb_node *rb_node;
+};
+
+
+#define rb_parent(r)   ((struct rb_node *)((r)->rb_parent_color & ~3))
+#define rb_color(r)   ((r)->rb_parent_color & 1)
+#define rb_is_red(r)   (!rb_color(r))
+#define rb_is_black(r) rb_color(r)
+#define rb_set_red(r)  do { (r)->rb_parent_color &= ~1; } while (0)
+#define rb_set_black(r)  do { (r)->rb_parent_color |= 1; } while (0)
+
+static inline void rb_set_parent(struct rb_node *rb, struct rb_node *p)
+{
+	rb->rb_parent_color = (rb->rb_parent_color & 3) | (unsigned long)p;
+}
+static inline void rb_set_color(struct rb_node *rb, int color)
+{
+	rb->rb_parent_color = (rb->rb_parent_color & ~1) | color;
+}
+
+#define RB_ROOT	(struct rb_root) { NULL, }
+#define	rb_entry(ptr, type, member) container_of(ptr, type, member)
+
+#define RB_EMPTY_ROOT(root)	((root)->rb_node == NULL)
+#define RB_EMPTY_NODE(node)	(rb_parent(node) == node)
+#define RB_CLEAR_NODE(node)	(rb_set_parent(node, node))
+
+extern void rb_insert_color(struct rb_node *, struct rb_root *);
+extern void rb_erase(struct rb_node *, struct rb_root *);
+
+/* Find logical next and previous nodes in a tree */
+extern struct rb_node *rb_next(struct rb_node *);
+extern struct rb_node *rb_prev(struct rb_node *);
+extern struct rb_node *rb_first(struct rb_root *);
+extern struct rb_node *rb_last(struct rb_root *);
+
+/* Fast replacement of a single node without remove/rebalance/add/rebalance */
+extern void rb_replace_node(struct rb_node *victim, struct rb_node *new,
+			    struct rb_root *root);
+
+static inline void rb_link_node(struct rb_node * node, struct rb_node * parent,
+				struct rb_node ** rb_link)
+{
+	node->rb_parent_color = (unsigned long )parent;
+	node->rb_left = node->rb_right = NULL;
+
+	*rb_link = node;
+}
+
+#endif	/* _LINUX_RBTREE_H */
diff --git a/include/linux/types.h b/include/linux/types.h
index df4808f..1b0b4a4 100644
--- a/include/linux/types.h
+++ b/include/linux/types.h
@@ -119,6 +119,30 @@ typedef		__s64		int64_t;
  * Below are truly Linux-specific types that should never collide with
  * any application/library that wants linux/types.h.
  */
+#ifdef __CHECKER__
+#define __bitwise__ __attribute__((bitwise))
+#else
+#define __bitwise__
+#endif
+#ifdef __CHECK_ENDIAN__
+#define __bitwise __bitwise__
+#else
+#define __bitwise
+#endif
+
+typedef __u16 __bitwise __le16;
+typedef __u16 __bitwise __be16;
+typedef __u32 __bitwise __le32;
+typedef __u32 __bitwise __be32;
+#if defined(__GNUC__)
+typedef __u64 __bitwise __le64;
+typedef __u64 __bitwise __be64;
+#endif
+typedef __u16 __bitwise __sum16;
+typedef __u32 __bitwise __wsum;
+
+
+typedef unsigned __bitwise__	gfp_t;
 
 struct ustat {
 	__kernel_daddr_t	f_tfree;
diff --git a/include/mb862xx.h b/include/mb862xx.h
index 1af5670..164305f 100644
--- a/include/mb862xx.h
+++ b/include/mb862xx.h
@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
diff --git a/include/miiphy.h b/include/miiphy.h
index 5518a0a..32f0a61 100644
--- a/include/miiphy.h
+++ b/include/miiphy.h
@@ -42,7 +42,7 @@ int miiphy_reset (char *devname, unsigned char addr);
 int miiphy_speed (char *devname, unsigned char addr);
 int miiphy_duplex (char *devname, unsigned char addr);
 int miiphy_is_1000base_x (char *devname, unsigned char addr);
-#ifdef CFG_FAULT_ECHO_LINK_DOWN
+#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 int miiphy_link (char *devname, unsigned char addr);
 #endif
 
diff --git a/include/mk48t59.h b/include/mk48t59.h
index a4459c0..e213fb8 100644
--- a/include/mk48t59.h
+++ b/include/mk48t59.h
@@ -28,9 +28,9 @@
 
 #if defined(CONFIG_RTC_MK48T59) && defined(CONFIG_CMD_DATE)
 
-#define RTC_PORT_ADDR0		CFG_ISA_IO +  0x70
+#define RTC_PORT_ADDR0		CONFIG_SYS_ISA_IO +  0x70
 #define RTC_PORT_ADDR1		RTC_PORT_ADDR0 +  0x1
-#define RTC_PORT_DATA		CFG_ISA_IO +  0x76
+#define RTC_PORT_DATA		CONFIG_SYS_ISA_IO +  0x76
 
 /* RTC Offsets */
 #define RTC_SECONDS             0x1FF9
diff --git a/include/mmc.h b/include/mmc.h
index 19c76fe..b9b27ba 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -1,6 +1,8 @@
 /*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Copyright 2008, Freescale Semiconductor, Inc
+ * Andy Fleming
+ *
+ * Based (loosely) on the Linux code
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -23,35 +25,255 @@
 
 #ifndef _MMC_H_
 #define _MMC_H_
-#include <asm/arch/mmc.h>
 
-/* MMC command numbers */
+#include <linux/list.h>
+
+#define SD_VERSION_SD	0x20000
+#define SD_VERSION_2	(SD_VERSION_SD | 0x20)
+#define SD_VERSION_1_0	(SD_VERSION_SD | 0x10)
+#define SD_VERSION_1_10	(SD_VERSION_SD | 0x1a)
+#define MMC_VERSION_MMC		0x10000
+#define MMC_VERSION_UNKNOWN	(MMC_VERSION_MMC)
+#define MMC_VERSION_1_2		(MMC_VERSION_MMC | 0x12)
+#define MMC_VERSION_1_4		(MMC_VERSION_MMC | 0x14)
+#define MMC_VERSION_2_2		(MMC_VERSION_MMC | 0x22)
+#define MMC_VERSION_3		(MMC_VERSION_MMC | 0x30)
+#define MMC_VERSION_4		(MMC_VERSION_MMC | 0x40)
+
+#define MMC_MODE_HS		0x001
+#define MMC_MODE_HS_52MHz	0x010
+#define MMC_MODE_4BIT		0x100
+#define MMC_MODE_8BIT		0x200
+
+#define SD_DATA_4BIT	0x00040000
+
+#define IS_SD(x) (mmc->version & SD_VERSION_SD)
+
+#define MMC_DATA_READ		1
+#define MMC_DATA_WRITE		2
+
+#define NO_CARD_ERR		-16 /* No SD/MMC card inserted */
+#define UNUSABLE_ERR		-17 /* Unusable Card */
+#define COMM_ERR		-18 /* Communications Error */
+#define TIMEOUT			-19
+
 #define MMC_CMD_GO_IDLE_STATE		0
 #define MMC_CMD_SEND_OP_COND		1
 #define MMC_CMD_ALL_SEND_CID		2
 #define MMC_CMD_SET_RELATIVE_ADDR	3
 #define MMC_CMD_SET_DSR			4
+#define MMC_CMD_SWITCH			6
 #define MMC_CMD_SELECT_CARD		7
+#define MMC_CMD_SEND_EXT_CSD		8
 #define MMC_CMD_SEND_CSD		9
 #define MMC_CMD_SEND_CID		10
+#define MMC_CMD_STOP_TRANSMISSION	12
 #define MMC_CMD_SEND_STATUS		13
 #define MMC_CMD_SET_BLOCKLEN		16
 #define MMC_CMD_READ_SINGLE_BLOCK	17
 #define MMC_CMD_READ_MULTIPLE_BLOCK	18
-#define MMC_CMD_WRITE_BLOCK		24
+#define MMC_CMD_WRITE_SINGLE_BLOCK	24
+#define MMC_CMD_WRITE_MULTIPLE_BLOCK	25
 #define MMC_CMD_APP_CMD			55
 
-/* SD Card command numbers */
 #define SD_CMD_SEND_RELATIVE_ADDR	3
-#define SD_CMD_SWITCH			6
+#define SD_CMD_SWITCH_FUNC		6
 #define SD_CMD_SEND_IF_COND		8
 
 #define SD_CMD_APP_SET_BUS_WIDTH	6
 #define SD_CMD_APP_SEND_OP_COND		41
+#define SD_CMD_APP_SEND_SCR		51
+
+/* SCR definitions in different words */
+#define SD_HIGHSPEED_BUSY	0x00020000
+#define SD_HIGHSPEED_SUPPORTED	0x00020000
+
+#define MMC_HS_TIMING		0x00000100
+#define MMC_HS_52MHZ		0x2
+
+#define OCR_BUSY	0x80
+#define OCR_HCS		0x40000000
+
+#define MMC_VDD_165_195		0x00000080	/* VDD voltage 1.65 - 1.95 */
+#define MMC_VDD_20_21		0x00000100	/* VDD voltage 2.0 ~ 2.1 */
+#define MMC_VDD_21_22		0x00000200	/* VDD voltage 2.1 ~ 2.2 */
+#define MMC_VDD_22_23		0x00000400	/* VDD voltage 2.2 ~ 2.3 */
+#define MMC_VDD_23_24		0x00000800	/* VDD voltage 2.3 ~ 2.4 */
+#define MMC_VDD_24_25		0x00001000	/* VDD voltage 2.4 ~ 2.5 */
+#define MMC_VDD_25_26		0x00002000	/* VDD voltage 2.5 ~ 2.6 */
+#define MMC_VDD_26_27		0x00004000	/* VDD voltage 2.6 ~ 2.7 */
+#define MMC_VDD_27_28		0x00008000	/* VDD voltage 2.7 ~ 2.8 */
+#define MMC_VDD_28_29		0x00010000	/* VDD voltage 2.8 ~ 2.9 */
+#define MMC_VDD_29_30		0x00020000	/* VDD voltage 2.9 ~ 3.0 */
+#define MMC_VDD_30_31		0x00040000	/* VDD voltage 3.0 ~ 3.1 */
+#define MMC_VDD_31_32		0x00080000	/* VDD voltage 3.1 ~ 3.2 */
+#define MMC_VDD_32_33		0x00100000	/* VDD voltage 3.2 ~ 3.3 */
+#define MMC_VDD_33_34		0x00200000	/* VDD voltage 3.3 ~ 3.4 */
+#define MMC_VDD_34_35		0x00400000	/* VDD voltage 3.4 ~ 3.5 */
+#define MMC_VDD_35_36		0x00800000	/* VDD voltage 3.5 ~ 3.6 */
+
+#define MMC_SWITCH_MODE_CMD_SET		0x00 /* Change the command set */
+#define MMC_SWITCH_MODE_SET_BITS	0x01 /* Set bits in EXT_CSD byte
+						addressed by index which are
+						1 in value field */
+#define MMC_SWITCH_MODE_CLEAR_BITS	0x02 /* Clear bits in EXT_CSD byte
+						addressed by index, which are
+						1 in value field */
+#define MMC_SWITCH_MODE_WRITE_BYTE	0x03 /* Set target byte to value */
+
+#define SD_SWITCH_CHECK		0
+#define SD_SWITCH_SWITCH	1
+
+/*
+ * EXT_CSD fields
+ */
+
+#define EXT_CSD_BUS_WIDTH	183	/* R/W */
+#define EXT_CSD_HS_TIMING	185	/* R/W */
+#define EXT_CSD_CARD_TYPE	196	/* RO */
+#define EXT_CSD_REV		192	/* RO */
+#define EXT_CSD_SEC_CNT		212	/* RO, 4 bytes */
+
+/*
+ * EXT_CSD field definitions
+ */
+
+#define EXT_CSD_CMD_SET_NORMAL		(1<<0)
+#define EXT_CSD_CMD_SET_SECURE		(1<<1)
+#define EXT_CSD_CMD_SET_CPSECURE	(1<<2)
+
+#define EXT_CSD_CARD_TYPE_26	(1<<0)	/* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52	(1<<1)	/* Card can run at 52MHz */
+
+#define EXT_CSD_BUS_WIDTH_1	0	/* Card is in 1 bit mode */
+#define EXT_CSD_BUS_WIDTH_4	1	/* Card is in 4 bit mode */
+#define EXT_CSD_BUS_WIDTH_8	2	/* Card is in 8 bit mode */
+
+#define R1_ILLEGAL_COMMAND		(1 << 22)
+#define R1_APP_CMD			(1 << 5)
+
+#define MMC_RSP_PRESENT (1 << 0)
+#define MMC_RSP_136     (1 << 1)                /* 136 bit response */
+#define MMC_RSP_CRC     (1 << 2)                /* expect valid crc */
+#define MMC_RSP_BUSY    (1 << 3)                /* card may send busy */
+#define MMC_RSP_OPCODE  (1 << 4)                /* response contains opcode */
+
+#define MMC_RSP_NONE    (0)
+#define MMC_RSP_R1      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_R1b	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
+			MMC_RSP_BUSY)
+#define MMC_RSP_R2      (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
+#define MMC_RSP_R3      (MMC_RSP_PRESENT)
+#define MMC_RSP_R4      (MMC_RSP_PRESENT)
+#define MMC_RSP_R5      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_R6      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_R7      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+
+
+struct mmc_cid {
+	unsigned long psn;
+	unsigned short oid;
+	unsigned char mid;
+	unsigned char prv;
+	unsigned char mdt;
+	char pnm[7];
+};
+
+struct mmc_csd
+{
+	u8	csd_structure:2,
+		spec_vers:4,
+		rsvd1:2;
+	u8	taac;
+	u8	nsac;
+	u8	tran_speed;
+	u16	ccc:12,
+		read_bl_len:4;
+	u64	read_bl_partial:1,
+		write_blk_misalign:1,
+		read_blk_misalign:1,
+		dsr_imp:1,
+		rsvd2:2,
+		c_size:12,
+		vdd_r_curr_min:3,
+		vdd_r_curr_max:3,
+		vdd_w_curr_min:3,
+		vdd_w_curr_max:3,
+		c_size_mult:3,
+		sector_size:5,
+		erase_grp_size:5,
+		wp_grp_size:5,
+		wp_grp_enable:1,
+		default_ecc:2,
+		r2w_factor:3,
+		write_bl_len:4,
+		write_bl_partial:1,
+		rsvd3:5;
+	u8	file_format_grp:1,
+		copy:1,
+		perm_write_protect:1,
+		tmp_write_protect:1,
+		file_format:2,
+		ecc:2;
+	u8	crc:7;
+	u8	one:1;
+};
+
+struct mmc_cmd {
+	ushort cmdidx;
+	uint resp_type;
+	uint cmdarg;
+	char response[18];
+	uint flags;
+};
+
+struct mmc_data {
+	union {
+		char *dest;
+		const char *src; /* src buffers don't get written to */
+	};
+	uint flags;
+	uint blocks;
+	uint blocksize;
+};
+
+struct mmc {
+	struct list_head link;
+	char name[32];
+	void *priv;
+	uint voltages;
+	uint version;
+	uint f_min;
+	uint f_max;
+	int high_capacity;
+	uint bus_width;
+	uint clock;
+	uint card_caps;
+	uint host_caps;
+	uint ocr;
+	uint scr[2];
+	uint csd[4];
+	char cid[16];
+	ushort rca;
+	uint tran_speed;
+	uint read_bl_len;
+	uint write_bl_len;
+	u64 capacity;
+	block_dev_desc_t block_dev;
+	int (*send_cmd)(struct mmc *mmc,
+			struct mmc_cmd *cmd, struct mmc_data *data);
+	void (*set_ios)(struct mmc *mmc);
+	int (*init)(struct mmc *mmc);
+};
 
-int mmc_init(int verbose);
-int mmc_read(ulong src, uchar *dst, int size);
-int mmc_write(uchar *src, ulong dst, int size);
-int mmc2info(ulong addr);
+int mmc_register(struct mmc *mmc);
+int mmc_initialize(bd_t *bis);
+int mmc_init(struct mmc *mmc);
+int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
+struct mmc *find_mmc_device(int dev_num);
+void print_mmc_devices(char separator);
 
+#ifndef CONFIG_GENERIC_MMC
+int mmc_legacy_init(int verbose);
+#endif
 #endif /* _MMC_H_ */
diff --git a/include/mpc106.h b/include/mpc106.h
index 10ed0f4..ef5a95f 100644
--- a/include/mpc106.h
+++ b/include/mpc106.h
@@ -35,7 +35,7 @@
  */
 #define	MPC106_REG			0x80000000
 
-#ifdef CFG_ADDRESS_MAP_A
+#ifdef CONFIG_SYS_ADDRESS_MAP_A
 #define MPC106_REG_ADDR			0x80000cf8
 #define	MPC106_REG_DATA			0x80000cfc
 #define MPC106_ISA_IO_PHYS		0x80000000
diff --git a/include/mpc512x.h b/include/mpc512x.h
index cb418d1..0f02293 100644
--- a/include/mpc512x.h
+++ b/include/mpc512x.h
@@ -572,7 +572,32 @@ void iopin_initialize(iopin_t *,int);
 #define IOCTRL_MUX_DDR		0x00000036
 
  /* Register Offset Base */
-#define MPC512X_FEC		(CFG_IMMR + 0x02800)
+#define MPC512X_FEC		(CONFIG_SYS_IMMR + 0x02800)
+#define MPC512X_PATA		(CONFIG_SYS_IMMR + 0x10200)
+
+/* IIM control */
+#define IIM_SET_UA(bk, f)	((bk << 3) | (f >> 5))
+#define IIM_SET_LA(f, bit)	(((f & 0x0000001f) << 3) | bit)
+#define IIM_STAT_BUSY		0x00000080
+#define IIM_STAT_PRGD		0x00000002
+#define IIM_STAT_SNSD		0x00000001
+#define IIM_ERR_WPE		0x00000040
+#define IIM_ERR_OPE		0x00000020
+#define IIM_ERR_RPE		0x00000010
+#define IIM_ERR_WLRE		0x00000008
+#define IIM_ERR_SNSE		0x00000004
+#define IIM_ERR_PARITYE		0x00000002
+#define IIM_PRG_P_SET		0x000000aa
+#define IIM_PRG_P_UNSET		0
+#define IIM_FCTL_PROG_PULSE	0x00000020
+#define IIM_FCTL_PROG		0x00000001
+#define IIM_FCTL_ESNS_N		0x00000008
+#define	IIM_FBAC_FBWP		0x00000080
+#define IIM_FBAC_FBOP		0x00000040
+#define IIM_FBAC_FBRP		0x00000020
+#define	IIM_FBAC_FBESP		0x00000008
+#define IIM_PROTECTION		0x000000e8
+#define IIM_FMAX			31
 
 /* Number of I2C buses */
 #define I2C_BUS_CNT	3
diff --git a/include/mpc5xx.h b/include/mpc5xx.h
index 414651f..de6d215 100644
--- a/include/mpc5xx.h
+++ b/include/mpc5xx.h
@@ -42,7 +42,7 @@
  * ISB bit in IMMR to set internal memory map
  */
 
-#define CFG_ISB			((CFG_IMMR / 0x00400000) << 1)
+#define CONFIG_SYS_ISB			((CONFIG_SYS_IMMR / 0x00400000) << 1)
 
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control Register
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
index 0f5bee5..3a32821 100644
--- a/include/mpc5xxx.h
+++ b/include/mpc5xxx.h
@@ -52,75 +52,75 @@
 
 /* Internal memory map */
 
-#define MPC5XXX_CS0_START	(CFG_MBAR + 0x0004)
-#define MPC5XXX_CS0_STOP	(CFG_MBAR + 0x0008)
-#define MPC5XXX_CS1_START	(CFG_MBAR + 0x000c)
-#define MPC5XXX_CS1_STOP	(CFG_MBAR + 0x0010)
-#define MPC5XXX_CS2_START	(CFG_MBAR + 0x0014)
-#define MPC5XXX_CS2_STOP	(CFG_MBAR + 0x0018)
-#define MPC5XXX_CS3_START	(CFG_MBAR + 0x001c)
-#define MPC5XXX_CS3_STOP	(CFG_MBAR + 0x0020)
-#define MPC5XXX_CS4_START	(CFG_MBAR + 0x0024)
-#define MPC5XXX_CS4_STOP	(CFG_MBAR + 0x0028)
-#define MPC5XXX_CS5_START	(CFG_MBAR + 0x002c)
-#define MPC5XXX_CS5_STOP	(CFG_MBAR + 0x0030)
-#define MPC5XXX_BOOTCS_START	(CFG_MBAR + 0x004c)
-#define MPC5XXX_BOOTCS_STOP	(CFG_MBAR + 0x0050)
-#define MPC5XXX_ADDECR		(CFG_MBAR + 0x0054)
+#define MPC5XXX_CS0_START	(CONFIG_SYS_MBAR + 0x0004)
+#define MPC5XXX_CS0_STOP	(CONFIG_SYS_MBAR + 0x0008)
+#define MPC5XXX_CS1_START	(CONFIG_SYS_MBAR + 0x000c)
+#define MPC5XXX_CS1_STOP	(CONFIG_SYS_MBAR + 0x0010)
+#define MPC5XXX_CS2_START	(CONFIG_SYS_MBAR + 0x0014)
+#define MPC5XXX_CS2_STOP	(CONFIG_SYS_MBAR + 0x0018)
+#define MPC5XXX_CS3_START	(CONFIG_SYS_MBAR + 0x001c)
+#define MPC5XXX_CS3_STOP	(CONFIG_SYS_MBAR + 0x0020)
+#define MPC5XXX_CS4_START	(CONFIG_SYS_MBAR + 0x0024)
+#define MPC5XXX_CS4_STOP	(CONFIG_SYS_MBAR + 0x0028)
+#define MPC5XXX_CS5_START	(CONFIG_SYS_MBAR + 0x002c)
+#define MPC5XXX_CS5_STOP	(CONFIG_SYS_MBAR + 0x0030)
+#define MPC5XXX_BOOTCS_START	(CONFIG_SYS_MBAR + 0x004c)
+#define MPC5XXX_BOOTCS_STOP	(CONFIG_SYS_MBAR + 0x0050)
+#define MPC5XXX_ADDECR		(CONFIG_SYS_MBAR + 0x0054)
 
 #if defined(CONFIG_MGT5100)
-#define MPC5XXX_SDRAM_START	(CFG_MBAR + 0x0034)
-#define MPC5XXX_SDRAM_STOP	(CFG_MBAR + 0x0038)
-#define MPC5XXX_PCI1_START	(CFG_MBAR + 0x003c)
-#define MPC5XXX_PCI1_STOP	(CFG_MBAR + 0x0040)
-#define MPC5XXX_PCI2_START	(CFG_MBAR + 0x0044)
-#define MPC5XXX_PCI2_STOP	(CFG_MBAR + 0x0048)
+#define MPC5XXX_SDRAM_START	(CONFIG_SYS_MBAR + 0x0034)
+#define MPC5XXX_SDRAM_STOP	(CONFIG_SYS_MBAR + 0x0038)
+#define MPC5XXX_PCI1_START	(CONFIG_SYS_MBAR + 0x003c)
+#define MPC5XXX_PCI1_STOP	(CONFIG_SYS_MBAR + 0x0040)
+#define MPC5XXX_PCI2_START	(CONFIG_SYS_MBAR + 0x0044)
+#define MPC5XXX_PCI2_STOP	(CONFIG_SYS_MBAR + 0x0048)
 #elif defined(CONFIG_MPC5200)
-#define MPC5XXX_CS6_START	(CFG_MBAR + 0x0058)
-#define MPC5XXX_CS6_STOP	(CFG_MBAR + 0x005c)
-#define MPC5XXX_CS7_START	(CFG_MBAR + 0x0060)
-#define MPC5XXX_CS7_STOP	(CFG_MBAR + 0x0064)
-#define MPC5XXX_SDRAM_CS0CFG	(CFG_MBAR + 0x0034)
-#define MPC5XXX_SDRAM_CS1CFG	(CFG_MBAR + 0x0038)
+#define MPC5XXX_CS6_START	(CONFIG_SYS_MBAR + 0x0058)
+#define MPC5XXX_CS6_STOP	(CONFIG_SYS_MBAR + 0x005c)
+#define MPC5XXX_CS7_START	(CONFIG_SYS_MBAR + 0x0060)
+#define MPC5XXX_CS7_STOP	(CONFIG_SYS_MBAR + 0x0064)
+#define MPC5XXX_SDRAM_CS0CFG	(CONFIG_SYS_MBAR + 0x0034)
+#define MPC5XXX_SDRAM_CS1CFG	(CONFIG_SYS_MBAR + 0x0038)
 #endif
 
-#define MPC5XXX_SDRAM		(CFG_MBAR + 0x0100)
-#define MPC5XXX_CDM		(CFG_MBAR + 0x0200)
-#define MPC5XXX_LPB		(CFG_MBAR + 0x0300)
-#define MPC5XXX_ICTL		(CFG_MBAR + 0x0500)
-#define MPC5XXX_GPT		(CFG_MBAR + 0x0600)
-#define MPC5XXX_GPIO		(CFG_MBAR + 0x0b00)
-#define MPC5XXX_WU_GPIO         (CFG_MBAR + 0x0c00)
-#define MPC5XXX_PCI		(CFG_MBAR + 0x0d00)
-#define MPC5XXX_SPI		(CFG_MBAR + 0x0f00)
-#define MPC5XXX_USB		(CFG_MBAR + 0x1000)
-#define MPC5XXX_SDMA		(CFG_MBAR + 0x1200)
-#define MPC5XXX_XLBARB		(CFG_MBAR + 0x1f00)
+#define MPC5XXX_SDRAM		(CONFIG_SYS_MBAR + 0x0100)
+#define MPC5XXX_CDM		(CONFIG_SYS_MBAR + 0x0200)
+#define MPC5XXX_LPB		(CONFIG_SYS_MBAR + 0x0300)
+#define MPC5XXX_ICTL		(CONFIG_SYS_MBAR + 0x0500)
+#define MPC5XXX_GPT		(CONFIG_SYS_MBAR + 0x0600)
+#define MPC5XXX_GPIO		(CONFIG_SYS_MBAR + 0x0b00)
+#define MPC5XXX_WU_GPIO         (CONFIG_SYS_MBAR + 0x0c00)
+#define MPC5XXX_PCI		(CONFIG_SYS_MBAR + 0x0d00)
+#define MPC5XXX_SPI		(CONFIG_SYS_MBAR + 0x0f00)
+#define MPC5XXX_USB		(CONFIG_SYS_MBAR + 0x1000)
+#define MPC5XXX_SDMA		(CONFIG_SYS_MBAR + 0x1200)
+#define MPC5XXX_XLBARB		(CONFIG_SYS_MBAR + 0x1f00)
 
 #if defined(CONFIG_MGT5100)
-#define	MPC5XXX_PSC1		(CFG_MBAR + 0x2000)
-#define	MPC5XXX_PSC2		(CFG_MBAR + 0x2400)
-#define	MPC5XXX_PSC3		(CFG_MBAR + 0x2800)
+#define	MPC5XXX_PSC1		(CONFIG_SYS_MBAR + 0x2000)
+#define	MPC5XXX_PSC2		(CONFIG_SYS_MBAR + 0x2400)
+#define	MPC5XXX_PSC3		(CONFIG_SYS_MBAR + 0x2800)
 #elif defined(CONFIG_MPC5200)
-#define	MPC5XXX_PSC1		(CFG_MBAR + 0x2000)
-#define	MPC5XXX_PSC2		(CFG_MBAR + 0x2200)
-#define	MPC5XXX_PSC3		(CFG_MBAR + 0x2400)
-#define	MPC5XXX_PSC4		(CFG_MBAR + 0x2600)
-#define	MPC5XXX_PSC5		(CFG_MBAR + 0x2800)
-#define	MPC5XXX_PSC6		(CFG_MBAR + 0x2c00)
+#define	MPC5XXX_PSC1		(CONFIG_SYS_MBAR + 0x2000)
+#define	MPC5XXX_PSC2		(CONFIG_SYS_MBAR + 0x2200)
+#define	MPC5XXX_PSC3		(CONFIG_SYS_MBAR + 0x2400)
+#define	MPC5XXX_PSC4		(CONFIG_SYS_MBAR + 0x2600)
+#define	MPC5XXX_PSC5		(CONFIG_SYS_MBAR + 0x2800)
+#define	MPC5XXX_PSC6		(CONFIG_SYS_MBAR + 0x2c00)
 #endif
 
-#define	MPC5XXX_FEC		(CFG_MBAR + 0x3000)
-#define MPC5XXX_ATA             (CFG_MBAR + 0x3A00)
+#define	MPC5XXX_FEC		(CONFIG_SYS_MBAR + 0x3000)
+#define MPC5XXX_ATA             (CONFIG_SYS_MBAR + 0x3A00)
 
-#define MPC5XXX_I2C1		(CFG_MBAR + 0x3D00)
-#define MPC5XXX_I2C2		(CFG_MBAR + 0x3D40)
+#define MPC5XXX_I2C1		(CONFIG_SYS_MBAR + 0x3D00)
+#define MPC5XXX_I2C2		(CONFIG_SYS_MBAR + 0x3D40)
 
 #if defined(CONFIG_MGT5100)
-#define MPC5XXX_SRAM		(CFG_MBAR + 0x4000)
+#define MPC5XXX_SRAM		(CONFIG_SYS_MBAR + 0x4000)
 #define MPC5XXX_SRAM_SIZE	(8*1024)
 #elif defined(CONFIG_MPC5200)
-#define MPC5XXX_SRAM		(CFG_MBAR + 0x8000)
+#define MPC5XXX_SRAM		(CONFIG_SYS_MBAR + 0x8000)
 #define MPC5XXX_SRAM_SIZE	(16*1024)
 #endif
 
diff --git a/include/mpc8220.h b/include/mpc8220.h
index d3b1457..c4900a0 100644
--- a/include/mpc8220.h
+++ b/include/mpc8220.h
@@ -39,37 +39,37 @@
 
 /* Internal memory map */
 /* MPC8220 Internal Register MMAP */
-#define MMAP_MBAR	(CFG_MBAR + 0x00000000) /* chip selects		     */
-#define MMAP_MEMCTL	(CFG_MBAR + 0x00000100) /* sdram controller	     */
-#define MMAP_XLBARB	(CFG_MBAR + 0x00000200) /* xlb arbitration control   */
-#define MMAP_CDM	(CFG_MBAR + 0x00000300) /* clock distribution module */
-#define MMAP_VDOPLL	(CFG_MBAR + 0x00000400) /* video PLL		     */
-#define MMAP_FB		(CFG_MBAR + 0x00000500) /* flex bus controller	     */
-#define MMAP_PCFG	(CFG_MBAR + 0x00000600) /* port config		     */
-#define MMAP_ICTL	(CFG_MBAR + 0x00000700) /* interrupt controller	     */
-#define MMAP_GPTMR	(CFG_MBAR + 0x00000800) /* general purpose timers    */
-#define MMAP_SLTMR	(CFG_MBAR + 0x00000900) /* slice timers		     */
-#define MMAP_GPIO	(CFG_MBAR + 0x00000A00) /* gpio module		     */
-#define MMAP_XCPCI	(CFG_MBAR + 0x00000B00) /* pci controller	     */
-#define MMAP_PCIARB	(CFG_MBAR + 0x00000C00) /* pci arbiter		     */
-#define MMAP_EXTDMA1	(CFG_MBAR + 0x00000D00) /* external dma1	     */
-#define MMAP_EXTDMA2	(CFG_MBAR + 0x00000E00) /* external dma1	     */
-#define MMAP_USBH	(CFG_MBAR + 0x00001000) /* usb host		     */
-#define MMAP_CMTMR	(CFG_MBAR + 0x00007f00) /* comm timers		     */
-#define MMAP_DMA	(CFG_MBAR + 0x00008000) /* dma			     */
-#define MMAP_USBD	(CFG_MBAR + 0x00008200) /* usb device		     */
-#define MMAP_COMMPCI	(CFG_MBAR + 0x00008400) /* pci comm Bus regs	     */
-#define MMAP_1284	(CFG_MBAR + 0x00008500) /* 1284			     */
-#define MMAP_PEV	(CFG_MBAR + 0x00008600) /* print engine video	     */
-#define MMAP_PSC1	(CFG_MBAR + 0x00008800) /* psc1 block		     */
-#define MMAP_I2C	(CFG_MBAR + 0x00008f00) /* i2c controller	     */
-#define MMAP_FEC1	(CFG_MBAR + 0x00009000) /* fast ethernet 1	     */
-#define MMAP_FEC2	(CFG_MBAR + 0x00009800) /* fast ethernet 2	     */
-#define MMAP_JBIGRAM	(CFG_MBAR + 0x0000a000) /* jbig RAM		     */
-#define MMAP_JBIG	(CFG_MBAR + 0x0000c000) /* jbig			     */
-#define MMAP_PDLA	(CFG_MBAR + 0x00010000) /*			     */
-#define MMAP_SRAMCFG	(CFG_MBAR + 0x0001ff00) /* SRAM config		     */
-#define MMAP_SRAM	(CFG_MBAR + 0x00020000) /* SRAM			     */
+#define MMAP_MBAR	(CONFIG_SYS_MBAR + 0x00000000) /* chip selects		     */
+#define MMAP_MEMCTL	(CONFIG_SYS_MBAR + 0x00000100) /* sdram controller	     */
+#define MMAP_XLBARB	(CONFIG_SYS_MBAR + 0x00000200) /* xlb arbitration control   */
+#define MMAP_CDM	(CONFIG_SYS_MBAR + 0x00000300) /* clock distribution module */
+#define MMAP_VDOPLL	(CONFIG_SYS_MBAR + 0x00000400) /* video PLL		     */
+#define MMAP_FB		(CONFIG_SYS_MBAR + 0x00000500) /* flex bus controller	     */
+#define MMAP_PCFG	(CONFIG_SYS_MBAR + 0x00000600) /* port config		     */
+#define MMAP_ICTL	(CONFIG_SYS_MBAR + 0x00000700) /* interrupt controller	     */
+#define MMAP_GPTMR	(CONFIG_SYS_MBAR + 0x00000800) /* general purpose timers    */
+#define MMAP_SLTMR	(CONFIG_SYS_MBAR + 0x00000900) /* slice timers		     */
+#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00000A00) /* gpio module		     */
+#define MMAP_XCPCI	(CONFIG_SYS_MBAR + 0x00000B00) /* pci controller	     */
+#define MMAP_PCIARB	(CONFIG_SYS_MBAR + 0x00000C00) /* pci arbiter		     */
+#define MMAP_EXTDMA1	(CONFIG_SYS_MBAR + 0x00000D00) /* external dma1	     */
+#define MMAP_EXTDMA2	(CONFIG_SYS_MBAR + 0x00000E00) /* external dma1	     */
+#define MMAP_USBH	(CONFIG_SYS_MBAR + 0x00001000) /* usb host		     */
+#define MMAP_CMTMR	(CONFIG_SYS_MBAR + 0x00007f00) /* comm timers		     */
+#define MMAP_DMA	(CONFIG_SYS_MBAR + 0x00008000) /* dma			     */
+#define MMAP_USBD	(CONFIG_SYS_MBAR + 0x00008200) /* usb device		     */
+#define MMAP_COMMPCI	(CONFIG_SYS_MBAR + 0x00008400) /* pci comm Bus regs	     */
+#define MMAP_1284	(CONFIG_SYS_MBAR + 0x00008500) /* 1284			     */
+#define MMAP_PEV	(CONFIG_SYS_MBAR + 0x00008600) /* print engine video	     */
+#define MMAP_PSC1	(CONFIG_SYS_MBAR + 0x00008800) /* psc1 block		     */
+#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00008f00) /* i2c controller	     */
+#define MMAP_FEC1	(CONFIG_SYS_MBAR + 0x00009000) /* fast ethernet 1	     */
+#define MMAP_FEC2	(CONFIG_SYS_MBAR + 0x00009800) /* fast ethernet 2	     */
+#define MMAP_JBIGRAM	(CONFIG_SYS_MBAR + 0x0000a000) /* jbig RAM		     */
+#define MMAP_JBIG	(CONFIG_SYS_MBAR + 0x0000c000) /* jbig			     */
+#define MMAP_PDLA	(CONFIG_SYS_MBAR + 0x00010000) /*			     */
+#define MMAP_SRAMCFG	(CONFIG_SYS_MBAR + 0x0001ff00) /* SRAM config		     */
+#define MMAP_SRAM	(CONFIG_SYS_MBAR + 0x00020000) /* SRAM			     */
 
 #define SRAM_SIZE	0x8000			/* 32 KB */
 
@@ -301,23 +301,23 @@
 /*
  * Port configuration
  */
-#define CFG_FEC1_PORT0_CONFIG	0x00000000
-#define CFG_FEC1_PORT1_CONFIG	0x00000000
-#define CFG_1284_PORT0_CONFIG  0x00000000
-#define CFG_1284_PORT1_CONFIG  0x00000000
-#define CFG_FEC2_PORT2_CONFIG	0x00000000
-#define CFG_PEV_PORT2_CONFIG   0x00000000
-#define CFG_GP0_PORT0_CONFIG   0x00000000
-#define CFG_GP1_PORT2_CONFIG   0xaaaaaac0
-#define CFG_PSC_PORT3_CONFIG   0x00020000
-#define CFG_CS1_PORT3_CONFIG   0x00000000
-#define CFG_CS2_PORT3_CONFIG	0x10000000
-#define CFG_CS3_PORT3_CONFIG	0x40000000
-#define CFG_CS4_PORT3_CONFIG	0x00000400
-#define CFG_CS5_PORT3_CONFIG	0x00000200
-#define CFG_PCI_PORT3_CONFIG   0x01400180
-#define CFG_I2C_PORT3_CONFIG   0x00000000
-#define CFG_GP2_PORT3_CONFIG   0x000200a0
+#define CONFIG_SYS_FEC1_PORT0_CONFIG	0x00000000
+#define CONFIG_SYS_FEC1_PORT1_CONFIG	0x00000000
+#define CONFIG_SYS_1284_PORT0_CONFIG  0x00000000
+#define CONFIG_SYS_1284_PORT1_CONFIG  0x00000000
+#define CONFIG_SYS_FEC2_PORT2_CONFIG	0x00000000
+#define CONFIG_SYS_PEV_PORT2_CONFIG   0x00000000
+#define CONFIG_SYS_GP0_PORT0_CONFIG   0x00000000
+#define CONFIG_SYS_GP1_PORT2_CONFIG   0xaaaaaac0
+#define CONFIG_SYS_PSC_PORT3_CONFIG   0x00020000
+#define CONFIG_SYS_CS1_PORT3_CONFIG   0x00000000
+#define CONFIG_SYS_CS2_PORT3_CONFIG	0x10000000
+#define CONFIG_SYS_CS3_PORT3_CONFIG	0x40000000
+#define CONFIG_SYS_CS4_PORT3_CONFIG	0x00000400
+#define CONFIG_SYS_CS5_PORT3_CONFIG	0x00000200
+#define CONFIG_SYS_PCI_PORT3_CONFIG   0x01400180
+#define CONFIG_SYS_I2C_PORT3_CONFIG   0x00000000
+#define CONFIG_SYS_GP2_PORT3_CONFIG   0x000200a0
 
 /* ------------------------------------------------------------------------ */
 /*
@@ -571,9 +571,9 @@ typedef struct mpc8220_xcpci {
 /* PCI->XLB space translation (MPC8220 target), reg0 can address max 256MB,
    reg1 - 1GB */
 #define PCI_BASE_ADDR_REG0			0x40000000
-#define PCI_BASE_ADDR_REG1			(CFG_SDRAM_BASE)
-#define PCI_TARGET_BASE_ADDR_REG0		(CFG_MBAR)
-#define PCI_TARGET_BASE_ADDR_REG1		(CFG_SDRAM_BASE)
+#define PCI_BASE_ADDR_REG1			(CONFIG_SYS_SDRAM_BASE)
+#define PCI_TARGET_BASE_ADDR_REG0		(CONFIG_SYS_MBAR)
+#define PCI_TARGET_BASE_ADDR_REG1		(CONFIG_SYS_SDRAM_BASE)
 #define PCI_TARGET_BASE_ADDR_EN			1<<0
 
 
diff --git a/include/mpc824x.h b/include/mpc824x.h
index 30f01d5..fca9371 100644
--- a/include/mpc824x.h
+++ b/include/mpc824x.h
@@ -154,7 +154,7 @@
 #define MAP_B_CONFIG_DATA_LOW	0x0000	/* Lower half of CONFIG_DAT for Map B */
 
 
-#if defined(CFG_ADDR_MAP_A)
+#if defined(CONFIG_SYS_ADDR_MAP_A)
 #define CONFIG_ADDR_HIGH    MAP_A_CONFIG_ADDR_HIGH  /* Upper half of CONFIG_ADDR */
 #define CONFIG_ADDR_LOW	    MAP_A_CONFIG_ADDR_LOW   /* Lower half of CONFIG_ADDR */
 #define CONFIG_DATA_HIGH    MAP_A_CONFIG_DATA_HIGH  /* Upper half of CONFIG_DAT */
@@ -451,45 +451,6 @@
 #define MICR_EADDR_MASK		0x30000000
 #define MICR_EADDR_SHIFT	28
 
-#define BATU_BEPI_MSK		0xfffe0000
-#define BATU_BL_MSK		0x00001ffc
-
-#define BATU_BL_128K		0x00000000
-#define BATU_BL_256K		0x00000004
-#define BATU_BL_512K		0x0000000c
-#define BATU_BL_1M		0x0000001c
-#define BATU_BL_2M		0x0000003c
-#define BATU_BL_4M		0x0000007c
-#define BATU_BL_8M		0x000000fc
-#define BATU_BL_16M		0x000001fc
-#define BATU_BL_32M		0x000003fc
-#define BATU_BL_64M		0x000007fc
-#define BATU_BL_128M		0x00000ffc
-#define BATU_BL_256M		0x00001ffc
-
-#define BATU_VS			0x00000002
-#define BATU_VP			0x00000001
-
-#define BATL_BRPN_MSK		0xfffe0000
-#define BATL_WIMG_MSK		0x00000078
-
-#define BATL_WRITETHROUGH	0x00000040
-#define BATL_CACHEINHIBIT	0x00000020
-#define BATL_MEMCOHERENCE	0x00000010
-#define BATL_GUARDEDSTORAGE	0x00000008
-
-#define BATL_PP_MSK		0x00000003
-#define BATL_PP_00		0x00000000 /* No access */
-#define BATL_PP_01		0x00000001 /* Read-only */
-#define BATL_PP_10		0x00000002 /* Read-write */
-#define BATL_PP_11		0x00000003
-
-/*
- * I'd attempt to do defines for the PP bits, but it's use is a bit
- * too complex, see the PowerPC Operating Environment Architecture
- * section in the PowerPc arch book, chapter 4.
- */
-
 /*eumb and epic config*/
 
 #define EPIC_FPR		0x00041000
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 5d82bb4..3554fdd 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -266,6 +266,7 @@
 /* SICRL bits - MPC837x specific */
 #define SICRL_USB_A			0xC0000000
 #define SICRL_USB_B			0x30000000
+#define SICRL_USB_B_SD			0x20000000
 #define SICRL_UART			0x0C000000
 #define SICRL_GPIO_A			0x02000000
 #define SICRL_GPIO_B			0x01000000
@@ -307,10 +308,12 @@
 #define SICRH_GPIO2_C			0x00002000
 #define SICRH_GPIO2_D			0x00001000
 #define SICRH_GPIO2_E			0x00000C00
+#define SICRH_GPIO2_E_SD		0x00000800
 #define SICRH_GPIO2_F			0x00000300
 #define SICRH_GPIO2_G			0x000000C0
 #define SICRH_GPIO2_H			0x00000030
 #define SICRH_SPI			0x00000003
+#define SICRH_SPI_SD			0x00000001
 #endif
 
 /* SWCRR - System Watchdog Control Register
@@ -528,7 +531,7 @@
 #if defined(CONFIG_MPC834X)
 #define HRCWH_ROM_LOC_PCI2		0x00200000
 #endif
-#if defined(CONIFG_MPC837X)
+#if defined(CONFIG_MPC837X)
 #define HRCWH_ROM_LOC_ON_CHIP_ROM	0x00300000
 #endif
 #define HRCWH_ROM_LOC_LOCAL_8BIT	0x00500000
@@ -544,12 +547,14 @@
 #define HRCWH_RL_EXT_LEGACY		0x00000000
 #define HRCWH_RL_EXT_NAND		0x00040000
 
+#define HRCWH_TSEC1M_MASK		0x0000E000
 #define HRCWH_TSEC1M_IN_MII		0x00000000
 #define HRCWH_TSEC1M_IN_RMII		0x00002000
 #define HRCWH_TSEC1M_IN_RGMII		0x00006000
 #define HRCWH_TSEC1M_IN_RTBI		0x0000A000
 #define HRCWH_TSEC1M_IN_SGMII		0x0000C000
 
+#define HRCWH_TSEC2M_MASK		0x00001C00
 #define HRCWH_TSEC2M_IN_MII		0x00000000
 #define HRCWH_TSEC2M_IN_RMII		0x00000400
 #define HRCWH_TSEC2M_IN_RGMII		0x00000C00
@@ -749,9 +754,6 @@
 #define SCCR_USBDRCM_2			0x00800000
 #define SCCR_USBDRCM_3			0x00c00000
 
-#define SCCR_PCIEXP1CM			0x00300000
-#define SCCR_PCIEXP2CM			0x000c0000
-
 #define SCCR_SATA1CM			0x00003000
 #define SCCR_SATA1CM_SHIFT		12
 #define SCCR_SATACM			0x00003c00
@@ -798,6 +800,17 @@
 #define SCCR_USBDRCM_2			0x00800000
 #define SCCR_USBDRCM_3			0x00c00000
 
+/* All of the four SATA controllers must have the same clock ratio */
+#define SCCR_SATA1CM			0x000000c0
+#define SCCR_SATA1CM_SHIFT		6
+#define SCCR_SATACM			0x000000ff
+#define SCCR_SATACM_SHIFT		0
+#define SCCR_SATACM_0			0x00000000
+#define SCCR_SATACM_1			0x00000055
+#define SCCR_SATACM_2			0x000000aa
+#define SCCR_SATACM_3			0x000000ff
+#endif
+
 #define SCCR_PCIEXP1CM			0x00300000
 #define SCCR_PCIEXP1CM_SHIFT		20
 #define SCCR_PCIEXP1CM_0		0x00000000
@@ -812,17 +825,6 @@
 #define SCCR_PCIEXP2CM_2		0x00080000
 #define SCCR_PCIEXP2CM_3		0x000c0000
 
-/* All of the four SATA controllers must have the same clock ratio */
-#define SCCR_SATA1CM			0x000000c0
-#define SCCR_SATA1CM_SHIFT		6
-#define SCCR_SATACM			0x000000ff
-#define SCCR_SATACM_SHIFT		0
-#define SCCR_SATACM_0			0x00000000
-#define SCCR_SATACM_1			0x00000055
-#define SCCR_SATACM_2			0x000000aa
-#define SCCR_SATACM_3			0x000000ff
-#endif
-
 /* CSn_BDNS - Chip Select memory Bounds Register
  */
 #define CSBNDS_SA			0x00FF0000
@@ -885,7 +887,9 @@
 #define TIMING_CFG1_WRTORD_SHIFT	0
 #define TIMING_CFG1_CASLAT_20		0x00030000	/* CAS latency = 2.0 */
 #define TIMING_CFG1_CASLAT_25		0x00040000	/* CAS latency = 2.5 */
-#define TIMING_CFG1_CASLAT_30		0x00050000	/* CAS latency = 2.5 */
+#define TIMING_CFG1_CASLAT_30		0x00050000	/* CAS latency = 3.0 */
+#define TIMING_CFG1_CASLAT_35		0x00060000	/* CAS latency = 3.5 */
+#define TIMING_CFG1_CASLAT_40		0x00070000	/* CAS latency = 4.0 */
 
 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
  */
@@ -1145,91 +1149,6 @@
  */
 #define PMCCR1_POWER_OFF		0x00000020
 
-/* FMR - Flash Mode Register
- */
-#define FMR_CWTO		0x0000F000
-#define FMR_CWTO_SHIFT		12
-#define FMR_BOOT		0x00000800
-#define FMR_ECCM		0x00000100
-#define FMR_AL			0x00000030
-#define FMR_AL_SHIFT		4
-#define FMR_OP			0x00000003
-#define FMR_OP_SHIFT		0
-
-/* FIR - Flash Instruction Register
- */
-#define FIR_OP0			0xF0000000
-#define FIR_OP0_SHIFT		28
-#define FIR_OP1			0x0F000000
-#define FIR_OP1_SHIFT		24
-#define FIR_OP2			0x00F00000
-#define FIR_OP2_SHIFT		20
-#define FIR_OP3			0x000F0000
-#define FIR_OP3_SHIFT		16
-#define FIR_OP4			0x0000F000
-#define FIR_OP4_SHIFT		12
-#define FIR_OP5			0x00000F00
-#define FIR_OP5_SHIFT		8
-#define FIR_OP6			0x000000F0
-#define FIR_OP6_SHIFT		4
-#define FIR_OP7			0x0000000F
-#define FIR_OP7_SHIFT		0
-#define FIR_OP_NOP		0x0 /* No operation and end of sequence */
-#define FIR_OP_CA		0x1 /* Issue current column address */
-#define FIR_OP_PA		0x2 /* Issue current block+page address */
-#define FIR_OP_UA		0x3 /* Issue user defined address */
-#define FIR_OP_CM0		0x4 /* Issue command from FCR[CMD0] */
-#define FIR_OP_CM1		0x5 /* Issue command from FCR[CMD1] */
-#define FIR_OP_CM2		0x6 /* Issue command from FCR[CMD2] */
-#define FIR_OP_CM3		0x7 /* Issue command from FCR[CMD3] */
-#define FIR_OP_WB		0x8 /* Write FBCR bytes from FCM buffer */
-#define FIR_OP_WS		0x9 /* Write 1 or 2 bytes from MDR[AS] */
-#define FIR_OP_RB		0xA /* Read FBCR bytes to FCM buffer */
-#define FIR_OP_RS		0xB /* Read 1 or 2 bytes to MDR[AS] */
-#define FIR_OP_CW0		0xC /* Wait then issue FCR[CMD0] */
-#define FIR_OP_CW1		0xD /* Wait then issue FCR[CMD1] */
-#define FIR_OP_RBW		0xE /* Wait then read FBCR bytes */
-#define FIR_OP_RSW		0xF /* Wait then read 1 or 2 bytes */
-
-/* FCR - Flash Command Register
- */
-#define FCR_CMD0		0xFF000000
-#define FCR_CMD0_SHIFT		24
-#define FCR_CMD1		0x00FF0000
-#define FCR_CMD1_SHIFT		16
-#define FCR_CMD2		0x0000FF00
-#define FCR_CMD2_SHIFT		8
-#define FCR_CMD3		0x000000FF
-#define FCR_CMD3_SHIFT		0
-
-/* FBAR - Flash Block Address Register
- */
-#define FBAR_BLK		0x00FFFFFF
-
-/* FPAR - Flash Page Address Register
- */
-#define FPAR_SP_PI		0x00007C00
-#define FPAR_SP_PI_SHIFT	10
-#define FPAR_SP_MS		0x00000200
-#define FPAR_SP_CI		0x000001FF
-#define FPAR_SP_CI_SHIFT	0
-#define FPAR_LP_PI		0x0003F000
-#define FPAR_LP_PI_SHIFT	12
-#define FPAR_LP_MS		0x00000800
-#define FPAR_LP_CI		0x000007FF
-#define FPAR_LP_CI_SHIFT	0
-
-/* LTESR - Transfer Error Status Register
- */
-#define LTESR_BM		0x80000000
-#define LTESR_FCT		0x40000000
-#define LTESR_PAR		0x20000000
-#define LTESR_WP		0x04000000
-#define LTESR_ATMW		0x00800000
-#define LTESR_ATMR		0x00400000
-#define LTESR_CS		0x00080000
-#define LTESR_CC		0x00000001
-
 /* DDRCDR - DDR Control Driver Register
  */
 #define DDRCDR_DHC_EN		0x80000000
@@ -1251,9 +1170,52 @@
 #define DDRCDR_M_ODR		0x00000002
 #define DDRCDR_Q_DRN		0x00000001
 
+/* PCIE Bridge Register
+*/
+#define PEX_CSB_CTRL_OBPIOE	0x00000001
+#define PEX_CSB_CTRL_IBPIOE	0x00000002
+#define PEX_CSB_CTRL_WDMAE	0x00000004
+#define PEX_CSB_CTRL_RDMAE	0x00000008
+
+#define PEX_CSB_OBCTRL_PIOE	0x00000001
+#define PEX_CSB_OBCTRL_MEMWE	0x00000002
+#define PEX_CSB_OBCTRL_IOWE	0x00000004
+#define PEX_CSB_OBCTRL_CFGWE	0x00000008
+
+#define PEX_CSB_IBCTRL_PIOE	0x00000001
+
+#define PEX_OWAR_EN		0x00000001
+#define PEX_OWAR_TYPE_CFG	0x00000000
+#define PEX_OWAR_TYPE_IO	0x00000002
+#define PEX_OWAR_TYPE_MEM	0x00000004
+#define PEX_OWAR_RLXO		0x00000008
+#define PEX_OWAR_NANP		0x00000010
+#define PEX_OWAR_SIZE		0xFFFFF000
+
+#define PEX_IWAR_EN		0x00000001
+#define PEX_IWAR_TYPE_INT	0x00000000
+#define PEX_IWAR_TYPE_PF	0x00000004
+#define PEX_IWAR_TYPE_NO_PF	0x00000006
+#define PEX_IWAR_NSOV		0x00000008
+#define PEX_IWAR_NSNP		0x00000010
+#define PEX_IWAR_SIZE		0xFFFFF000
+#define PEX_IWAR_SIZE_1M	0x000FF000
+#define PEX_IWAR_SIZE_2M	0x001FF000
+#define PEX_IWAR_SIZE_4M	0x003FF000
+#define PEX_IWAR_SIZE_8M	0x007FF000
+#define PEX_IWAR_SIZE_16M	0x00FFF000
+#define PEX_IWAR_SIZE_32M	0x01FFF000
+#define PEX_IWAR_SIZE_64M	0x03FFF000
+#define PEX_IWAR_SIZE_128M	0x07FFF000
+#define PEX_IWAR_SIZE_256M	0x0FFFF000
+
+#define PEX_GCLK_RATIO		0x440
+
 #ifndef __ASSEMBLY__
 struct pci_region;
 void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot);
+void mpc83xx_pcislave_unlock(int bus);
+void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot);
 #endif
 
 #endif	/* __MPC83XX_H__ */
diff --git a/include/mpc86xx.h b/include/mpc86xx.h
index ce3d784..c6f30f9 100644
--- a/include/mpc86xx.h
+++ b/include/mpc86xx.h
@@ -16,9 +16,9 @@
  * platform register addresses
  */
 
-#define GUTS_SVR	(CFG_CCSRBAR + 0xE00A4)
-#define MCM_ABCR	(CFG_CCSRBAR + 0x01000)
-#define MCM_DBCR	(CFG_CCSRBAR + 0x01008)
+#define GUTS_SVR	(CONFIG_SYS_CCSRBAR + 0xE00A4)
+#define MCM_ABCR	(CONFIG_SYS_CCSRBAR + 0x01000)
+#define MCM_DBCR	(CONFIG_SYS_CCSRBAR + 0x01008)
 
 /*
  * l2cr values.  Look in config_<BOARD>.h for the actual setup
@@ -34,47 +34,6 @@
 #define L2CR_HWF         0x00000800 /* bit 20 - hardware flush */
 #define L2CR_L2IP        0x00000001 /* global invalidate in progress */
 
-/*
- * BAT settings.  Look in config_<BOARD>.h for the actual setup
- */
-
-#define BATU_BL_128K            0x00000000
-#define BATU_BL_256K            0x00000004
-#define BATU_BL_512K            0x0000000c
-#define BATU_BL_1M              0x0000001c
-#define BATU_BL_2M              0x0000003c
-#define BATU_BL_4M              0x0000007c
-#define BATU_BL_8M              0x000000fc
-#define BATU_BL_16M             0x000001fc
-#define BATU_BL_32M             0x000003fc
-#define BATU_BL_64M             0x000007fc
-#define BATU_BL_128M            0x00000ffc
-#define BATU_BL_256M            0x00001ffc
-#define BATU_BL_512M            0x00003ffc
-#define BATU_BL_1G              0x00007ffc
-#define BATU_BL_2G              0x0000fffc
-#define BATU_BL_4G              0x0001fffc
-
-#define BATU_VS                 0x00000002
-#define BATU_VP                 0x00000001
-#define BATU_INVALID            0x00000000
-
-#define BATL_WRITETHROUGH       0x00000040
-#define BATL_CACHEINHIBIT       0x00000020
-#define BATL_MEMCOHERENCE	0x00000010
-#define BATL_GUARDEDSTORAGE     0x00000008
-#define BATL_NO_ACCESS		0x00000000
-
-#define BATL_PP_MSK		0x00000003
-#define BATL_PP_00		0x00000000 /* No access */
-#define BATL_PP_01		0x00000001 /* Read-only */
-#define BATL_PP_10		0x00000002 /* Read-write */
-#define BATL_PP_11		0x00000003
-
-#define BATL_PP_NO_ACCESS	BATL_PP_00
-#define BATL_PP_RO		BATL_PP_01
-#define BATL_PP_RW		BATL_PP_10
-
 #define HID0_XBSEN              0x00000100
 #define HID0_HIGH_BAT_EN        0x00800000
 #define HID0_XAEN               0x00020000
@@ -84,6 +43,7 @@
 typedef struct {
 	unsigned long freqProcessor;
 	unsigned long freqSystemBus;
+	unsigned long freqLocalBus;
 } MPC86xx_SYS_INFO;
 
 #define l1icache_enable	icache_enable
diff --git a/include/mpc8xx_irq.h b/include/mpc8xx_irq.h
index d2a81c0..15cf693 100644
--- a/include/mpc8xx_irq.h
+++ b/include/mpc8xx_irq.h
@@ -45,8 +45,8 @@
  * MBX PCI/ISA/IDE interrupts.
  */
 
-#ifdef CFG_CPM_INTERRUPT
-# define CPM_INTERRUPT		CFG_CPM_INTERRUPT
+#ifdef CONFIG_SYS_CPM_INTERRUPT
+# define CPM_INTERRUPT		CONFIG_SYS_CPM_INTERRUPT
 #else
 # define CPM_INTERRUPT		SIU_LEVEL2
 #endif
diff --git a/include/linux/mtd/ubi-user.h b/include/mtd/ubi-user.h
index fe06ded..a7421f1 100644
--- a/include/linux/mtd/ubi-user.h
+++ b/include/mtd/ubi-user.h
@@ -22,6 +22,21 @@
 #define __UBI_USER_H__
 
 /*
+ * UBI device creation (the same as MTD device attachment)
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * MTD devices may be attached using %UBI_IOCATT ioctl command of the UBI
+ * control device. The caller has to properly fill and pass
+ * &struct ubi_attach_req object - UBI will attach the MTD device specified in
+ * the request and return the newly created UBI device number as the ioctl
+ * return value.
+ *
+ * UBI device deletion (the same as MTD device detachment)
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * An UBI device maybe deleted with %UBI_IOCDET ioctl command of the UBI
+ * control device.
+ *
  * UBI volume creation
  * ~~~~~~~~~~~~~~~~~~~
  *
@@ -48,7 +63,7 @@
  *
  * Volume update should be done via the %UBI_IOCVOLUP IOCTL command of the
  * corresponding UBI volume character device. A pointer to a 64-bit update
- * size should be passed to the IOCTL. After then, UBI expects user to write
+ * size should be passed to the IOCTL. After this, UBI expects user to write
  * this number of bytes to the volume character device. The update is finished
  * when the claimed number of bytes is passed. So, the volume update sequence
  * is something like:
@@ -57,14 +72,24 @@
  * ioctl(fd, UBI_IOCVOLUP, &image_size);
  * write(fd, buf, image_size);
  * close(fd);
+ *
+ * Atomic eraseblock change
+ * ~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * Atomic eraseblock change operation is done via the %UBI_IOCEBCH IOCTL
+ * command of the corresponding UBI volume character device. A pointer to
+ * &struct ubi_leb_change_req has to be passed to the IOCTL. Then the user is
+ * expected to write the requested amount of bytes. This is similar to the
+ * "volume update" IOCTL.
  */
 
 /*
- * When a new volume is created, users may either specify the volume number they
- * want to create or to let UBI automatically assign a volume number using this
- * constant.
+ * When a new UBI volume or UBI device is created, users may either specify the
+ * volume/device number they want to create or to let UBI automatically assign
+ * the number using these constants.
  */
 #define UBI_VOL_NUM_AUTO (-1)
+#define UBI_DEV_NUM_AUTO (-1)
 
 /* Maximum volume name length */
 #define UBI_MAX_VOLUME_NAME 127
@@ -80,6 +105,15 @@
 /* Re-size an UBI volume */
 #define UBI_IOCRSVOL _IOW(UBI_IOC_MAGIC, 2, struct ubi_rsvol_req)
 
+/* IOCTL commands of the UBI control character device */
+
+#define UBI_CTRL_IOC_MAGIC 'o'
+
+/* Attach an MTD device */
+#define UBI_IOCATT _IOW(UBI_CTRL_IOC_MAGIC, 64, struct ubi_attach_req)
+/* Detach an MTD device */
+#define UBI_IOCDET _IOW(UBI_CTRL_IOC_MAGIC, 65, int32_t)
+
 /* IOCTL commands of UBI volume character devices */
 
 #define UBI_VOL_IOC_MAGIC 'O'
@@ -88,6 +122,28 @@
 #define UBI_IOCVOLUP _IOW(UBI_VOL_IOC_MAGIC, 0, int64_t)
 /* An eraseblock erasure command, used for debugging, disabled by default */
 #define UBI_IOCEBER _IOW(UBI_VOL_IOC_MAGIC, 1, int32_t)
+/* An atomic eraseblock change command */
+#define UBI_IOCEBCH _IOW(UBI_VOL_IOC_MAGIC, 2, int32_t)
+
+/* Maximum MTD device name length supported by UBI */
+#define MAX_UBI_MTD_NAME_LEN 127
+
+/*
+ * UBI data type hint constants.
+ *
+ * UBI_LONGTERM: long-term data
+ * UBI_SHORTTERM: short-term data
+ * UBI_UNKNOWN: data persistence is unknown
+ *
+ * These constants are used when data is written to UBI volumes in order to
+ * help the UBI wear-leveling unit to find more appropriate physical
+ * eraseblocks.
+ */
+enum {
+	UBI_LONGTERM  = 1,
+	UBI_SHORTTERM = 2,
+	UBI_UNKNOWN   = 3,
+};
 
 /*
  * UBI volume type constants.
@@ -97,22 +153,58 @@
  */
 enum {
 	UBI_DYNAMIC_VOLUME = 3,
-	UBI_STATIC_VOLUME = 4
+	UBI_STATIC_VOLUME  = 4,
+};
+
+/**
+ * struct ubi_attach_req - attach MTD device request.
+ * @ubi_num: UBI device number to create
+ * @mtd_num: MTD device number to attach
+ * @vid_hdr_offset: VID header offset (use defaults if %0)
+ * @padding: reserved for future, not used, has to be zeroed
+ *
+ * This data structure is used to specify MTD device UBI has to attach and the
+ * parameters it has to use. The number which should be assigned to the new UBI
+ * device is passed in @ubi_num. UBI may automatically assign the number if
+ * @UBI_DEV_NUM_AUTO is passed. In this case, the device number is returned in
+ * @ubi_num.
+ *
+ * Most applications should pass %0 in @vid_hdr_offset to make UBI use default
+ * offset of the VID header within physical eraseblocks. The default offset is
+ * the next min. I/O unit after the EC header. For example, it will be offset
+ * 512 in case of a 512 bytes page NAND flash with no sub-page support. Or
+ * it will be 512 in case of a 2KiB page NAND flash with 4 512-byte sub-pages.
+ *
+ * But in rare cases, if this optimizes things, the VID header may be placed to
+ * a different offset. For example, the boot-loader might do things faster if the
+ * VID header sits at the end of the first 2KiB NAND page with 4 sub-pages. As
+ * the boot-loader would not normally need to read EC headers (unless it needs
+ * UBI in RW mode), it might be faster to calculate ECC. This is weird example,
+ * but it real-life example. So, in this example, @vid_hdr_offer would be
+ * 2KiB-64 bytes = 1984. Note, that this position is not even 512-bytes
+ * aligned, which is OK, as UBI is clever enough to realize this is 4th sub-page
+ * of the first page and add needed padding.
+ */
+struct ubi_attach_req {
+	int32_t ubi_num;
+	int32_t mtd_num;
+	int32_t vid_hdr_offset;
+	uint8_t padding[12];
 };
 
 /**
  * struct ubi_mkvol_req - volume description data structure used in
- * volume creation requests.
+ *                        volume creation requests.
  * @vol_id: volume number
  * @alignment: volume alignment
  * @bytes: volume size in bytes
  * @vol_type: volume type (%UBI_DYNAMIC_VOLUME or %UBI_STATIC_VOLUME)
- * @padding1: reserved for future, not used
+ * @padding1: reserved for future, not used, has to be zeroed
  * @name_len: volume name length
- * @padding2: reserved for future, not used
+ * @padding2: reserved for future, not used, has to be zeroed
  * @name: volume name
  *
- * This structure is used by userspace programs when creating new volumes. The
+ * This structure is used by user-space programs when creating new volumes. The
  * @used_bytes field is only necessary when creating static volumes.
  *
  * The @alignment field specifies the required alignment of the volume logical
@@ -139,7 +231,7 @@ struct ubi_mkvol_req {
 	int8_t padding1;
 	int16_t name_len;
 	int8_t padding2[4];
-	char name[UBI_MAX_VOLUME_NAME+1];
+	char name[UBI_MAX_VOLUME_NAME + 1];
 } __attribute__ ((packed));
 
 /**
@@ -158,4 +250,19 @@ struct ubi_rsvol_req {
 	int32_t vol_id;
 } __attribute__ ((packed));
 
+/**
+ * struct ubi_leb_change_req - a data structure used in atomic logical
+ *                             eraseblock change requests.
+ * @lnum: logical eraseblock number to change
+ * @bytes: how many bytes will be written to the logical eraseblock
+ * @dtype: data type (%UBI_LONGTERM, %UBI_SHORTTERM, %UBI_UNKNOWN)
+ * @padding: reserved for future, not used, has to be zeroed
+ */
+struct ubi_leb_change_req {
+	int32_t lnum;
+	int32_t bytes;
+	uint8_t dtype;
+	uint8_t padding[7];
+} __attribute__ ((packed));
+
 #endif /* __UBI_USER_H__ */
diff --git a/include/nand.h b/include/nand.h
index 3296e10..065a42c 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -31,6 +31,8 @@ extern void nand_init(void);
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 
+extern int board_nand_init(struct nand_chip *nand);
+
 typedef struct mtd_info nand_info_t;
 
 extern int nand_curr_device;
@@ -122,7 +124,7 @@ int nand_lock( nand_info_t *meminfo, int tight );
 int nand_unlock( nand_info_t *meminfo, ulong start, ulong length );
 int nand_get_lock_status(nand_info_t *meminfo, ulong offset);
 
-#ifdef CFG_NAND_SELECT_DEVICE
+#ifdef CONFIG_SYS_NAND_SELECT_DEVICE
 void board_nand_select_device(struct nand_chip *nand, int chip);
 #endif
 
diff --git a/include/net.h b/include/net.h
index 79ddfa2..b192db1 100644
--- a/include/net.h
+++ b/include/net.h
@@ -38,16 +38,16 @@
 #define CONFIG_NET_MULTI
 #if (CONFIG_ETHER_INDEX == 1)
 #define	CONFIG_ETHER_ON_FCC1
-# define CFG_CMXFCR_MASK1	CFG_CMXFCR_MASK
-# define CFG_CMXFCR_VALUE1	CFG_CMXFCR_VALUE
+# define CONFIG_SYS_CMXFCR_MASK1	CONFIG_SYS_CMXFCR_MASK
+# define CONFIG_SYS_CMXFCR_VALUE1	CONFIG_SYS_CMXFCR_VALUE
 #elif (CONFIG_ETHER_INDEX == 2)
 #define	CONFIG_ETHER_ON_FCC2
-# define CFG_CMXFCR_MASK2	CFG_CMXFCR_MASK
-# define CFG_CMXFCR_VALUE2	CFG_CMXFCR_VALUE
+# define CONFIG_SYS_CMXFCR_MASK2	CONFIG_SYS_CMXFCR_MASK
+# define CONFIG_SYS_CMXFCR_VALUE2	CONFIG_SYS_CMXFCR_VALUE
 #elif (CONFIG_ETHER_INDEX == 3)
 #define	CONFIG_ETHER_ON_FCC3
-# define CFG_CMXFCR_MASK3	CFG_CMXFCR_MASK
-# define CFG_CMXFCR_VALUE3	CFG_CMXFCR_VALUE
+# define CONFIG_SYS_CMXFCR_MASK3	CONFIG_SYS_CMXFCR_MASK
+# define CONFIG_SYS_CMXFCR_VALUE3	CONFIG_SYS_CMXFCR_VALUE
 #endif /* CONFIG_ETHER_INDEX */
 #endif /* CONFIG_ETHER_ON_FCC */
 #endif /* !CONFIG_NET_MULTI && CONFIG_8260 */
@@ -61,8 +61,8 @@
  *
  */
 
-#ifdef CFG_RX_ETH_BUFFER
-# define PKTBUFSRX	CFG_RX_ETH_BUFFER
+#ifdef CONFIG_SYS_RX_ETH_BUFFER
+# define PKTBUFSRX	CONFIG_SYS_RX_ETH_BUFFER
 #else
 # define PKTBUFSRX	4
 #endif
@@ -109,25 +109,26 @@ struct eth_device {
 	void *priv;
 };
 
-extern int eth_initialize(bd_t *bis);		/* Initialize network subsystem */
-extern int eth_register(struct eth_device* dev);/* Register network device	*/
-extern void eth_try_another(int first_restart);	/* Change the device		*/
+extern int eth_initialize(bd_t *bis);	/* Initialize network subsystem */
+extern int eth_register(struct eth_device* dev);/* Register network device */
+extern void eth_try_another(int first_restart);	/* Change the device */
 #ifdef CONFIG_NET_MULTI
-extern void eth_set_current(void);		/* set nterface to ethcur var.  */
+extern void eth_set_current(void);		/* set nterface to ethcur var */
 #endif
-extern struct eth_device *eth_get_dev(void);	/* get the current device MAC	*/
-extern struct eth_device *eth_get_dev_by_name(char *devname); /* get device	*/
-extern int eth_get_dev_index (void);		/* get the device index         */
-extern void eth_set_enetaddr(int num, char* a);	/* Set new MAC address		*/
-
-extern int eth_init(bd_t *bis);			/* Initialize the device	*/
-extern int eth_send(volatile void *packet, int length);	   /* Send a packet	*/
+extern struct eth_device *eth_get_dev(void);	/* get the current device MAC */
+extern struct eth_device *eth_get_dev_by_name(char *devname); /* get device */
+extern struct eth_device *eth_get_dev_by_index(int index); /* get dev @ index */
+extern int eth_get_dev_index (void);		/* get the device index */
+extern void eth_set_enetaddr(int num, char* a);	/* Set new MAC address */
+
+extern int eth_init(bd_t *bis);			/* Initialize the device */
+extern int eth_send(volatile void *packet, int length);	   /* Send a packet */
 #ifdef CONFIG_API
-extern int eth_receive(volatile void *packet, int length); /* Receive a packet	*/
+extern int eth_receive(volatile void *packet, int length); /* Receive a packet*/
 #endif
-extern int eth_rx(void);			/* Check for received packets	*/
-extern void eth_halt(void);			/* stop SCC			*/
-extern char *eth_get_name(void);		/* get name of current device	*/
+extern int eth_rx(void);			/* Check for received packets */
+extern void eth_halt(void);			/* stop SCC */
+extern char *eth_get_name(void);		/* get name of current device */
 
 #ifdef CONFIG_MCAST_TFTP
 int eth_mcast_join( IPaddr_t mcast_addr, u8 join);
@@ -200,6 +201,12 @@ typedef struct {
 	ushort		udp_xsum;	/* Checksum			*/
 } IP_t;
 
+#define IP_OFFS		0x1fff /* ip offset *= 8 */
+#define IP_FLAGS	0xe000 /* first 3 bits */
+#define IP_FLAGS_RES	0x8000 /* reserved */
+#define IP_FLAGS_DFRAG	0x4000 /* don't fragments */
+#define IP_FLAGS_MFRAG	0x2000 /* more fragments */
+
 #define IP_HDR_SIZE_NO_UDP	(sizeof (IP_t) - 8)
 #define IP_HDR_SIZE		(sizeof (IP_t))
 
@@ -468,6 +475,22 @@ static inline int is_multicast_ether_addr(const u8 *addr)
 	return (0x01 & addr[0]);
 }
 
+/**
+ * is_valid_ether_addr - Determine if the given Ethernet address is valid
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Check that the Ethernet address (MAC) is not 00:00:00:00:00:00, is not
+ * a multicast address, and is not FF:FF:FF:FF:FF:FF.
+ *
+ * Return true if the address is valid.
+ */
+static inline int is_valid_ether_addr(const u8 * addr)
+{
+	/* FF:FF:FF:FF:FF:FF is a multicast address so we don't need to
+	 * explicitly check for it here. */
+	return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr);
+}
+
 /* Convert an IP address to a string */
 extern void	ip_to_string (IPaddr_t x, char *s);
 
diff --git a/include/netdev.h b/include/netdev.h
index 87d578c..2794ddd 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -41,11 +41,14 @@ int board_eth_init(bd_t *bis);
 int cpu_eth_init(bd_t *bis);
 
 /* Driver initialization prototypes */
+int au1x00_enet_initialize(bd_t*);
 int bfin_EMAC_initialize(bd_t *bis);
 int dc21x4x_initialize(bd_t *bis);
+int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
 int e1000_initialize(bd_t *bis);
 int eepro100_initialize(bd_t *bis);
 int eth_3com_initialize (bd_t * bis);
+int fec_initialize (bd_t *bis);
 int greth_initialize(bd_t *bis);
 void gt6426x_eth_initialize(bd_t *bis);
 int inca_switch_initialize(bd_t *bis);
@@ -54,15 +57,22 @@ int mcdmafec_initialize(bd_t *bis);
 int mcffec_initialize(bd_t *bis);
 int mpc512x_fec_initialize(bd_t *bis);
 int mpc5xxx_fec_initialize(bd_t *bis);
+int mpc8220_fec_initialize(bd_t *bis);
+int mpc82xx_scc_enet_initialize(bd_t *bis);
 int natsemi_initialize(bd_t *bis);
+int npe_initialize(bd_t *bis);
 int ns8382x_initialize(bd_t *bis);
 int pcnet_initialize(bd_t *bis);
 int plb2800_eth_initialize(bd_t *bis);
+int ppc_4xx_eth_initialize (bd_t *bis);
 int rtl8139_initialize(bd_t *bis);
 int rtl8169_initialize(bd_t *bis);
+int scc_initialize(bd_t *bis);
 int skge_initialize(bd_t *bis);
 int tsi108_eth_initialize(bd_t *bis);
+int uec_initialize(int index);
 int uli526x_initialize(bd_t *bis);
+int sh_eth_initialize(bd_t *bis);
 
 /* Boards with PCI network controllers can call this from their board_eth_init()
  * function to initialize whatever's on board.
diff --git a/include/nomadik.h b/include/nomadik.h
new file mode 100644
index 0000000..d9405fd
--- /dev/null
+++ b/include/nomadik.h
@@ -0,0 +1,39 @@
+/* Collection of constants used to access Nomadik registers */
+
+#ifndef __NOMADIK_H__
+#define __NOMADIK_H__
+
+/* Base addresses of our peripherals */
+#define NOMADIK_SRC_BASE	0x101E0000	/* System and Reset Cnt */
+#define NOMADIK_PMU_BASE	0x101E9000	/* Power Management Unit */
+#define NOMADIK_MPMC_BASE	0x10110000	/* SDRAM Controller */
+#define NOMADIK_FSMC_BASE	0x10100000	/* FSMC Controller */
+#define NOMADIK_1NAND_BASE	0x30000000
+#define NOMADIK_GPIO0_BASE	0x101E4000
+#define NOMADIK_GPIO1_BASE	0x101E5000
+#define NOMADIK_GPIO2_BASE	0x101E6000
+#define NOMADIK_GPIO3_BASE	0x101E7000
+#define NOMADIK_CPLD_BASE	0x36000000
+#define NOMADIK_UART0_BASE	0x101FD000
+#define NOMADIK_UART1_BASE	0x101FB000
+#define NOMADIK_UART2_BASE	0x101F2000
+
+#define NOMADIK_I2C1_BASE	0x101F7000	/* I2C1 interface */
+#define NOMADIK_I2C0_BASE	0x101F8000	/* I2C0 interface */
+
+#define NOMADIK_RTC_BASE	0x101E8000
+#define NOMADIK_ETH0_BASE	0x36800300
+#define NOMADIK_CPLD_UART_BASE	0x36480000
+
+/* Chip select registers ("Flexible Static Memory Controller") */
+
+#define REG_FSMC_BCR0	(NOMADIK_FSMC_BASE + 0x00)
+#define REG_FSMC_BTR0	(NOMADIK_FSMC_BASE + 0x04)
+#define REG_FSMC_BCR1	(NOMADIK_FSMC_BASE + 0x08)
+#define REG_FSMC_BTR1	(NOMADIK_FSMC_BASE + 0x0c)
+#define REG_FSMC_PCR0	(NOMADIK_FSMC_BASE + 0x40)
+#define REG_FSMC_PMEM0	(NOMADIK_FSMC_BASE + 0x48)
+#define REG_FSMC_PATT0	(NOMADIK_FSMC_BASE + 0x4c)
+#define REG_FSMC_ECCR0	(NOMADIK_FSMC_BASE + 0x54)
+
+#endif /* __NOMADIK_H__ */
diff --git a/include/ns16550.h b/include/ns16550.h
index 34888a1..e6ade61 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -2,7 +2,7 @@
  * NS16550 Serial Port
  * originally from linux source (arch/ppc/boot/ns16550.h)
  * modified slightly to
- * have addresses as offsets from CFG_ISA_BASE
+ * have addresses as offsets from CONFIG_SYS_ISA_BASE
  * added a few more definitions
  * added prototypes for ns16550.c
  * reduced no of com ports to 2
@@ -12,7 +12,7 @@
  * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
  */
 
-#if (CFG_NS16550_REG_SIZE == 1)
+#if (CONFIG_SYS_NS16550_REG_SIZE == 1)
 struct NS16550 {
 	unsigned char rbr;		/* 0 */
 	unsigned char ier;		/* 1 */
@@ -35,7 +35,7 @@ struct NS16550 {
 	unsigned char ssr;		/* 11*/
 #endif
 } __attribute__ ((packed));
-#elif (CFG_NS16550_REG_SIZE == 2)
+#elif (CONFIG_SYS_NS16550_REG_SIZE == 2)
 struct NS16550 {
 	unsigned short rbr;		/* 0 */
 	unsigned short ier;		/* 1 */
@@ -46,7 +46,7 @@ struct NS16550 {
 	unsigned short msr;		/* 6 */
 	unsigned short scr;		/* 7 */
 } __attribute__ ((packed));
-#elif (CFG_NS16550_REG_SIZE == 4)
+#elif (CONFIG_SYS_NS16550_REG_SIZE == 4)
 struct NS16550 {
 	unsigned long rbr;		/* 0 r  */
 	unsigned long ier;		/* 1 rw */
@@ -57,7 +57,7 @@ struct NS16550 {
 	unsigned long msr;		/* 6 r  */
 	unsigned long scr;		/* 7 rw */
 }; /* No need to pack an already aligned struct */
-#elif (CFG_NS16550_REG_SIZE == -4)
+#elif (CONFIG_SYS_NS16550_REG_SIZE == -4)
 struct NS16550 {
 	unsigned char rbr;		/* 0 */
 	int pad1:24;
@@ -85,7 +85,7 @@ struct NS16550 {
 	int pad10:24;
 #endif
 } __attribute__ ((packed));
-#elif (CFG_NS16550_REG_SIZE == -8)
+#elif (CONFIG_SYS_NS16550_REG_SIZE == -8)
 struct NS16550 {
 	unsigned char rbr;		/* 0 */
 	unsigned char pad0[7];
diff --git a/include/ns87308.h b/include/ns87308.h
index feeb940..6177bb4 100644
--- a/include/ns87308.h
+++ b/include/ns87308.h
@@ -74,15 +74,15 @@ struct GPIO
 #define IO_DATA_OFFSET_10  0x015D  /* PnP motherboard mode */
 #define IO_DATA_OFFSET_11  0x002F  /* PnP motherboard mode */
 
-#if defined(CFG_NS87308_BADDR_0x)
-#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_0x)
-#define IO_DATA  (CFG_ISA_IO + IO_DATA_OFFSET_0x)
-#elif defined(CFG_NS87308_BADDR_10)
-#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_10)
-#define IO_DATA  (CFG_ISA_IO + IO_DATA_OFFSET_10)
-#elif defined(CFG_NS87308_BADDR_11)
-#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_11)
-#define IO_DATA  (CFG_ISA_IO + IO_DATA_OFFSET_11)
+#if defined(CONFIG_SYS_NS87308_BADDR_0x)
+#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_0x)
+#define IO_DATA  (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_0x)
+#elif defined(CONFIG_SYS_NS87308_BADDR_10)
+#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_10)
+#define IO_DATA  (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_10)
+#elif defined(CONFIG_SYS_NS87308_BADDR_11)
+#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_11)
+#define IO_DATA  (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_11)
 #endif
 
 /* PnP register definitions */
@@ -132,16 +132,16 @@ struct GPIO
 #define LDEV_GPIO           0x07    /*General Purpose IO and chip select output signals*/
 #define LDEV_POWRMAN        0x08    /*Power Managment*/
 
-#define CFG_NS87308_KBC1	(1 << LDEV_KBC1)
-#define CFG_NS87308_KBC2	(1 << LDEV_KBC2)
-#define CFG_NS87308_MOUSE	(1 << LDEV_MOUSE)
-#define CFG_NS87308_RTC_APC	(1 << LDEV_RTC_APC)
-#define CFG_NS87308_FDC		(1 << LDEV_FDC)
-#define CFG_NS87308_PARP	(1 << LDEV_PARP)
-#define CFG_NS87308_UART2	(1 << LDEV_UART2)
-#define CFG_NS87308_UART1	(1 << LDEV_UART1)
-#define CFG_NS87308_GPIO	(1 << LDEV_GPIO)
-#define CFG_NS87308_POWRMAN	(1 << LDEV_POWRMAN)
+#define CONFIG_SYS_NS87308_KBC1	(1 << LDEV_KBC1)
+#define CONFIG_SYS_NS87308_KBC2	(1 << LDEV_KBC2)
+#define CONFIG_SYS_NS87308_MOUSE	(1 << LDEV_MOUSE)
+#define CONFIG_SYS_NS87308_RTC_APC	(1 << LDEV_RTC_APC)
+#define CONFIG_SYS_NS87308_FDC		(1 << LDEV_FDC)
+#define CONFIG_SYS_NS87308_PARP	(1 << LDEV_PARP)
+#define CONFIG_SYS_NS87308_UART2	(1 << LDEV_UART2)
+#define CONFIG_SYS_NS87308_UART1	(1 << LDEV_UART1)
+#define CONFIG_SYS_NS87308_GPIO	(1 << LDEV_GPIO)
+#define CONFIG_SYS_NS87308_POWRMAN	(1 << LDEV_POWRMAN)
 
 /*some functions and macro's for doing configuration */
 
@@ -164,9 +164,9 @@ static inline void pnp_set_device(unsigned char dev)
 
 static inline void write_pm_reg(unsigned short base, unsigned char index, unsigned char data)
 {
-    pci_writeb(index, CFG_ISA_IO + base);
+    pci_writeb(index, CONFIG_SYS_ISA_IO + base);
     eieio();
-    pci_writeb(data, CFG_ISA_IO + base + 1);
+    pci_writeb(data, CONFIG_SYS_ISA_IO + base + 1);
 }
 
 /*void write_pnp_config(unsigned char index, unsigned char data);
@@ -228,23 +228,23 @@ static inline void write_pgcs_config(unsigned char index, unsigned char data)
 /*
  * Default NS87308 configuration
  */
-#ifndef CFG_NS87308_KBC1_BASE
-#define CFG_NS87308_KBC1_BASE	0x0060
+#ifndef CONFIG_SYS_NS87308_KBC1_BASE
+#define CONFIG_SYS_NS87308_KBC1_BASE	0x0060
 #endif
-#ifndef CFG_NS87308_RTC_BASE
-#define CFG_NS87308_RTC_BASE	0x0070
+#ifndef CONFIG_SYS_NS87308_RTC_BASE
+#define CONFIG_SYS_NS87308_RTC_BASE	0x0070
 #endif
-#ifndef CFG_NS87308_FDC_BASE
-#define CFG_NS87308_FDC_BASE	0x03F0
+#ifndef CONFIG_SYS_NS87308_FDC_BASE
+#define CONFIG_SYS_NS87308_FDC_BASE	0x03F0
 #endif
-#ifndef CFG_NS87308_LPT_BASE
-#define CFG_NS87308_LPT_BASE	0x0278
+#ifndef CONFIG_SYS_NS87308_LPT_BASE
+#define CONFIG_SYS_NS87308_LPT_BASE	0x0278
 #endif
-#ifndef CFG_NS87308_UART1_BASE
-#define CFG_NS87308_UART1_BASE	0x03F8
+#ifndef CONFIG_SYS_NS87308_UART1_BASE
+#define CONFIG_SYS_NS87308_UART1_BASE	0x03F8
 #endif
-#ifndef CFG_NS87308_UART2_BASE
-#define CFG_NS87308_UART2_BASE	0x02F8
+#ifndef CONFIG_SYS_NS87308_UART2_BASE
+#define CONFIG_SYS_NS87308_UART2_BASE	0x02F8
 #endif
 
 #endif /*_NS87308_H_*/
diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h
index e960257..49da9d0 100644
--- a/include/onenand_uboot.h
+++ b/include/onenand_uboot.h
@@ -15,25 +15,31 @@
 #define __UBOOT_ONENAND_H
 
 #include <linux/types.h>
-#include <linux/mtd/mtd.h>
 
+/* Forward declarations */
 struct mtd_info;
+struct mtd_oob_ops;
 struct erase_info;
+struct onenand_chip;
 
 extern struct mtd_info onenand_mtd;
 
+/* board */
+extern void onenand_board_init(struct mtd_info *);
+
 /* Functions */
 extern void onenand_init(void);
 extern int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
 			size_t * retlen, u_char * buf);
-extern int onenand_read_oob(struct mtd_info *mtd, loff_t from,
-			    struct mtd_oob_ops *ops);
+extern int onenand_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops);
 extern int onenand_write(struct mtd_info *mtd, loff_t from, size_t len,
 			 size_t * retlen, const u_char * buf);
 extern int onenand_erase(struct mtd_info *mtd, struct erase_info *instr);
 
-extern int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len);
+extern char *onenand_print_device_info(int device, int version);
 
-extern char *onenand_print_device_info(int device);
+/* S3C64xx */
+extern void s3c64xx_onenand_init(struct mtd_info *);
+extern void s3c64xx_set_width_regs(struct onenand_chip *);
 
 #endif /* __UBOOT_ONENAND_H */
diff --git a/include/part.h b/include/part.h
index b22a637..980fd04 100644
--- a/include/part.h
+++ b/include/part.h
@@ -69,6 +69,7 @@ typedef struct block_dev_desc {
 #define PART_TYPE_DOS		0x02
 #define PART_TYPE_ISO		0x03
 #define PART_TYPE_AMIGA		0x04
+#define PART_TYPE_EFI		0x05
 
 /*
  * Type string for U-Boot bootable partitions
@@ -135,4 +136,11 @@ void print_part_amiga (block_dev_desc_t *dev_desc);
 int   test_part_amiga (block_dev_desc_t *dev_desc);
 #endif
 
+#ifdef CONFIG_EFI_PARTITION
+/* disk/part_efi.c */
+int get_partition_info_efi (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+void print_part_efi (block_dev_desc_t *dev_desc);
+int   test_part_efi (block_dev_desc_t *dev_desc);
+#endif
+
 #endif /* _PART_H */
diff --git a/include/pca953x.h b/include/pca953x.h
new file mode 100644
index 0000000..6c2b58c
--- /dev/null
+++ b/include/pca953x.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __PCA953X_H_
+#define __PCA953X_H_
+
+#define PCA953X_IN		0x00
+#define PCA953X_OUT		0x01
+#define PCA953X_POL		0x02
+#define PCA953X_CONF		0x03
+
+#define PCA953X_OUT_LOW		0
+#define PCA953X_OUT_HIGH	1
+#define PCA953X_POL_NORMAL	0
+#define PCA953X_POL_INVERT	1
+#define PCA953X_DIR_OUT		0
+#define PCA953X_DIR_IN		1
+
+int pca953x_set_val(u8 chip, uint mask, uint data);
+int pca953x_set_pol(u8 chip, uint mask, uint data);
+int pca953x_set_dir(u8 chip, uint mask, uint data);
+int pca953x_get_val(u8 chip);
+
+#endif /* __PCA953X_H_ */
diff --git a/include/pci.h b/include/pci.h
index 1c8e216..d0594e3 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -101,8 +101,8 @@
 #define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
 #define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
 #define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
-#define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fUL)
-#define  PCI_BASE_ADDRESS_IO_MASK	(~0x03UL)
+#define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fULL)
+#define  PCI_BASE_ADDRESS_IO_MASK	(~0x03ULL)
 /* bit 1 is reserved if address_space = 1 */
 
 /* Header type 0 (normal devices) */
@@ -111,7 +111,7 @@
 #define PCI_SUBSYSTEM_ID	0x2e
 #define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
 #define  PCI_ROM_ADDRESS_ENABLE 0x01
-#define PCI_ROM_ADDRESS_MASK	(~0x7ffUL)
+#define PCI_ROM_ADDRESS_MASK	(~0x7ffULL)
 
 #define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */
 
@@ -312,13 +312,21 @@
 
 #include <pci_ids.h>
 
+#ifdef CONFIG_SYS_PCI_64BIT
+typedef u64 pci_addr_t;
+typedef u64 pci_size_t;
+#else
+typedef u32 pci_addr_t;
+typedef u32 pci_size_t;
+#endif
+
 struct pci_region {
-	unsigned long bus_start;		/* Start on the bus */
-	phys_addr_t phys_start;			/* Start in physical address space */
-	unsigned long size;			/* Size */
-	unsigned long flags;			/* Resource flags */
+	pci_addr_t bus_start;	/* Start on the bus */
+	phys_addr_t phys_start;	/* Start in physical address space */
+	pci_size_t size;	/* Size */
+	unsigned long flags;	/* Resource flags */
 
-	unsigned long bus_lower;
+	pci_addr_t bus_lower;
 };
 
 #define PCI_REGION_MEM		0x00000000	/* PCI memory space */
@@ -326,13 +334,13 @@ struct pci_region {
 #define PCI_REGION_TYPE		0x00000001
 #define PCI_REGION_PREFETCH	0x00000008	/* prefetchable PCI memory */
 
-#define PCI_REGION_MEMORY	0x00000100	/* System memory */
+#define PCI_REGION_SYS_MEMORY	0x00000100	/* System memory */
 #define PCI_REGION_RO		0x00000200	/* Read-only memory */
 
 extern __inline__ void pci_set_region(struct pci_region *reg,
-				      unsigned long bus_start,
+				      pci_addr_t bus_start,
 				      phys_addr_t phys_start,
-				      unsigned long size,
+				      pci_size_t size,
 				      unsigned long flags) {
 	reg->bus_start	= bus_start;
 	reg->phys_start = phys_start;
@@ -374,6 +382,8 @@ extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev
 
 #define MAX_PCI_REGIONS		7
 
+#define INDIRECT_TYPE_NO_PCIE_LINK	1
+
 /*
  * Structure of a PCI controller (host bridge)
  */
@@ -386,6 +396,8 @@ struct pci_controller {
 	volatile unsigned int *cfg_addr;
 	volatile unsigned char *cfg_data;
 
+	int indirect_type;
+
 	struct pci_region regions[MAX_PCI_REGIONS];
 	int region_count;
 
@@ -433,19 +445,38 @@ extern __inline__ void pci_set_ops(struct pci_controller *hose,
 extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
 
 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
-					unsigned long addr, unsigned long flags);
-extern unsigned long pci_hose_phys_to_bus(struct pci_controller* hose,
-					  phys_addr_t addr, unsigned long flags);
+					pci_addr_t addr, unsigned long flags);
+extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
+					phys_addr_t addr, unsigned long flags);
 
 #define pci_phys_to_bus(dev, addr, flags) \
 	pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
 #define pci_bus_to_phys(dev, addr, flags) \
 	pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
 
-#define pci_phys_to_mem(dev, addr)	pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
-#define pci_mem_to_phys(dev, addr)	pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
-#define pci_phys_to_io(dev, addr)	pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
-#define pci_io_to_phys(dev, addr)	pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
+#define pci_virt_to_bus(dev, addr, flags) \
+	pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
+			     (virt_to_phys(addr)), (flags))
+#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
+	map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
+					 (addr), (flags)), \
+		    (len), (map_flags))
+
+#define pci_phys_to_mem(dev, addr) \
+	pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
+#define pci_mem_to_phys(dev, addr) \
+	pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
+#define pci_phys_to_io(dev, addr)  pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
+#define pci_io_to_phys(dev, addr)  pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
+
+#define pci_virt_to_mem(dev, addr) \
+	pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
+#define pci_mem_to_virt(dev, addr, len, map_flags) \
+	pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
+#define pci_virt_to_io(dev, addr) \
+	pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
+#define pci_io_to_virt(dev, addr, len, map_flags) \
+	pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
 
 extern int pci_hose_read_config_byte(struct pci_controller *hose,
 				     pci_dev_t dev, int where, u8 *val);
@@ -476,6 +507,7 @@ extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
 extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
 						pci_dev_t dev, int where, u16 val);
 
+extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
 extern void pci_register_hose(struct pci_controller* hose);
 extern struct pci_controller* pci_bus_to_hose(int bus);
 
@@ -483,8 +515,8 @@ extern int pci_hose_scan(struct pci_controller *hose);
 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
 
 extern void pciauto_region_init(struct pci_region* res);
-extern void pciauto_region_align(struct pci_region *res, unsigned long size);
-extern int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar);
+extern void pciauto_region_align(struct pci_region *res, pci_size_t size);
+extern int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar);
 extern void pciauto_setup_device(struct pci_controller *hose,
 				 pci_dev_t dev, int bars_num,
 				 struct pci_region *mem,
@@ -500,7 +532,7 @@ extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
 extern int pci_hose_config_device(struct pci_controller *hose,
 				  pci_dev_t dev,
 				  unsigned long io,
-				  unsigned long mem,
+				  pci_addr_t mem,
 				  unsigned long command);
 
 #ifdef CONFIG_MPC824X
diff --git a/include/pcmcia.h b/include/pcmcia.h
index 7305805..b60323d 100644
--- a/include/pcmcia.h
+++ b/include/pcmcia.h
@@ -138,8 +138,8 @@ typedef struct {
  *	Common Memory Space
  */
 
-#define CFG_PCMCIA_PBR0		0xFE100000
-#define CFG_PCMCIA_POR0	    (	PCMCIA_BSIZE_2	\
+#define CONFIG_SYS_PCMCIA_PBR0		0xFE100000
+#define CONFIG_SYS_PCMCIA_POR0	    (	PCMCIA_BSIZE_2	\
 			    |	PCMCIA_PPS_16	\
 			    |	PCMCIA_PRS_MEM	\
 			    |	PCMCIA_SLOT_x	\
@@ -153,8 +153,8 @@ typedef struct {
  *	Common Memory Space
  */
 
-#define CFG_PCMCIA_PBR1		0xFE100080
-#define CFG_PCMCIA_POR1	    (	PCMCIA_BSIZE_8	\
+#define CONFIG_SYS_PCMCIA_PBR1		0xFE100080
+#define CONFIG_SYS_PCMCIA_POR1	    (	PCMCIA_BSIZE_8	\
 			    |	PCMCIA_PPS_8	\
 			    |	PCMCIA_PRS_MEM	\
 			    |	PCMCIA_SLOT_x	\
@@ -168,8 +168,8 @@ typedef struct {
  *	Common Memory Space
  */
 
-#define CFG_PCMCIA_PBR2		0xFE100100
-#define CFG_PCMCIA_POR2	    (	PCMCIA_BSIZE_8	\
+#define CONFIG_SYS_PCMCIA_PBR2		0xFE100100
+#define CONFIG_SYS_PCMCIA_POR2	    (	PCMCIA_BSIZE_8	\
 			    |	PCMCIA_PPS_8	\
 			    |	PCMCIA_PRS_MEM	\
 			    |	PCMCIA_SLOT_x	\
@@ -179,8 +179,8 @@ typedef struct {
 /* Window 3:
  *	not used
  */
-#define CFG_PCMCIA_PBR3		0
-#define CFG_PCMCIA_POR3		0
+#define CONFIG_SYS_PCMCIA_PBR3		0
+#define CONFIG_SYS_PCMCIA_POR3		0
 
 /* Window 4:
  *	Base: 0xFE100C00	CS1
@@ -189,8 +189,8 @@ typedef struct {
  *	Common Memory Space
  */
 
-#define CFG_PCMCIA_PBR4		0xFE100C00
-#define CFG_PCMCIA_POR4	    (	PCMCIA_BSIZE_2	\
+#define CONFIG_SYS_PCMCIA_PBR4		0xFE100C00
+#define CONFIG_SYS_PCMCIA_POR4	    (	PCMCIA_BSIZE_2	\
 			    |	PCMCIA_PPS_16	\
 			    |	PCMCIA_PRS_MEM	\
 			    |	PCMCIA_SLOT_x	\
@@ -204,8 +204,8 @@ typedef struct {
  *	Common Memory Space
  */
 
-#define CFG_PCMCIA_PBR5		0xFE100C80
-#define CFG_PCMCIA_POR5	    (	PCMCIA_BSIZE_8	\
+#define CONFIG_SYS_PCMCIA_PBR5		0xFE100C80
+#define CONFIG_SYS_PCMCIA_POR5	    (	PCMCIA_BSIZE_8	\
 			    |	PCMCIA_PPS_8	\
 			    |	PCMCIA_PRS_MEM	\
 			    |	PCMCIA_SLOT_x	\
@@ -219,8 +219,8 @@ typedef struct {
  *	Common Memory Space
  */
 
-#define CFG_PCMCIA_PBR6		0xFE100D00
-#define CFG_PCMCIA_POR6	    (	PCMCIA_BSIZE_8	\
+#define CONFIG_SYS_PCMCIA_PBR6		0xFE100D00
+#define CONFIG_SYS_PCMCIA_POR6	    (	PCMCIA_BSIZE_8	\
 			    |	PCMCIA_PPS_8	\
 			    |	PCMCIA_PRS_MEM	\
 			    |	PCMCIA_SLOT_x	\
@@ -230,8 +230,8 @@ typedef struct {
 /* Window 7:
  *	not used
  */
-#define CFG_PCMCIA_PBR7		0
-#define CFG_PCMCIA_POR7		0
+#define CONFIG_SYS_PCMCIA_PBR7		0
+#define CONFIG_SYS_PCMCIA_POR7		0
 
 /**********************************************************************/
 
diff --git a/include/post.h b/include/post.h
index 123623f..fe96312 100644
--- a/include/post.h
+++ b/include/post.h
@@ -80,30 +80,43 @@ extern struct post_test post_list[];
 extern unsigned int post_list_size;
 extern int post_hotkeys_pressed(void);
 
+/*
+ *  If GCC is configured to use a version of GAS that supports
+ * the .gnu_attribute directive, it will use that directive to
+ * record certain properties of the output code.
+ *  This feature is new to GCC 4.3.0.
+ *  .gnu_attribute is new to GAS 2.18.
+ */
+#if (__GNUC__ >= 4 && __GNUC_MINOR__ >= 3)
+/* Tag_GNU_Power_ABI_FP/soft-float */
+#define GNU_FPOST_ATTR	asm(".gnu_attribute	4, 2");
+#else
+#define GNU_FPOST_ATTR
+#endif /* __GNUC__ */
 #endif /* __ASSEMBLY__ */
 
-#define CFG_POST_RTC		0x00000001
-#define CFG_POST_WATCHDOG	0x00000002
-#define CFG_POST_MEMORY		0x00000004
-#define CFG_POST_CPU		0x00000008
-#define CFG_POST_I2C		0x00000010
-#define CFG_POST_CACHE		0x00000020
-#define CFG_POST_UART		0x00000040
-#define CFG_POST_ETHER		0x00000080
-#define CFG_POST_SPI		0x00000100
-#define CFG_POST_USB		0x00000200
-#define CFG_POST_SPR		0x00000400
-#define CFG_POST_SYSMON		0x00000800
-#define CFG_POST_DSP		0x00001000
-#define CFG_POST_OCM		0x00002000
-#define CFG_POST_FPU		0x00004000
-#define CFG_POST_ECC		0x00008000
-#define CFG_POST_BSPEC1		0x00010000
-#define CFG_POST_BSPEC2		0x00020000
-#define CFG_POST_BSPEC3		0x00040000
-#define CFG_POST_BSPEC4		0x00080000
-#define CFG_POST_BSPEC5		0x00100000
-#define CFG_POST_CODEC		0x00200000
+#define CONFIG_SYS_POST_RTC		0x00000001
+#define CONFIG_SYS_POST_WATCHDOG	0x00000002
+#define CONFIG_SYS_POST_MEMORY		0x00000004
+#define CONFIG_SYS_POST_CPU		0x00000008
+#define CONFIG_SYS_POST_I2C		0x00000010
+#define CONFIG_SYS_POST_CACHE		0x00000020
+#define CONFIG_SYS_POST_UART		0x00000040
+#define CONFIG_SYS_POST_ETHER		0x00000080
+#define CONFIG_SYS_POST_SPI		0x00000100
+#define CONFIG_SYS_POST_USB		0x00000200
+#define CONFIG_SYS_POST_SPR		0x00000400
+#define CONFIG_SYS_POST_SYSMON		0x00000800
+#define CONFIG_SYS_POST_DSP		0x00001000
+#define CONFIG_SYS_POST_OCM		0x00002000
+#define CONFIG_SYS_POST_FPU		0x00004000
+#define CONFIG_SYS_POST_ECC		0x00008000
+#define CONFIG_SYS_POST_BSPEC1		0x00010000
+#define CONFIG_SYS_POST_BSPEC2		0x00020000
+#define CONFIG_SYS_POST_BSPEC3		0x00040000
+#define CONFIG_SYS_POST_BSPEC4		0x00080000
+#define CONFIG_SYS_POST_BSPEC5		0x00100000
+#define CONFIG_SYS_POST_CODEC		0x00200000
 
 #endif /* CONFIG_POST */
 
diff --git a/include/ppc405.h b/include/ppc405.h
index f19b67f..917afec 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -27,9 +27,9 @@
 #define PPC_128MB_SACR_VALUE(addr)	PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
 
 #ifndef CONFIG_IOP480
-#define CFG_DCACHE_SIZE		(16 << 10)	/* For AMCC 405 CPUs	*/
+#define CONFIG_SYS_DCACHE_SIZE		(16 << 10)	/* For AMCC 405 CPUs	*/
 #else
-#define CFG_DCACHE_SIZE		(2 << 10)	/* For PLX IOP480 (403)	*/
+#define CONFIG_SYS_DCACHE_SIZE		(2 << 10)	/* For PLX IOP480 (403)	*/
 #endif
 
 /*--------------------------------------------------------------------- */
diff --git a/include/ppc440.h b/include/ppc440.h
index be8d3ff..01f6eaf 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -46,7 +46,7 @@
 #ifndef __PPC440_H__
 #define __PPC440_H__
 
-#define CFG_DCACHE_SIZE		(32 << 10)	/* For AMCC 440 CPUs	*/
+#define CONFIG_SYS_DCACHE_SIZE		(32 << 10)	/* For AMCC 440 CPUs	*/
 
 /*--------------------------------------------------------------------- */
 /* Special Purpose Registers						*/
@@ -169,18 +169,9 @@
 #define sdr_ecid1	0x0081
 #define sdr_ecid2	0x0082
 #define sdr_jtag	0x00c0
-#if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
-#define sdr_ddrdl	0x00e0
-#else
-#define sdr_cfg		0x00e0
-#define SDR_CFG_LT2_MASK          0x01000000 /* Leakage test 2*/
-#define SDR_CFG_64_32BITS_MASK    0x01000000 /* Switch DDR 64 bits or 32 bits */
-#define SDR_CFG_32BITS            0x00000000  /* 32 bits */
-#define SDR_CFG_64BITS            0x01000000  /* 64 bits */
-#define SDR_CFG_MC_V2518_MASK     0x02000000 /* Low VDD2518 (2.5 or 1.8V) */
-#define SDR_CFG_MC_V25            0x00000000  /* 2.5 V */
-#define SDR_CFG_MC_V18            0x02000000  /* 1.8 V */
-#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR0_DDRCFG	0x00e0
+#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
 #define sdr_ebc		0x0100
 #define sdr_uart0	0x0120	/* UART0 Config */
 #define sdr_uart1	0x0121	/* UART1 Config */
@@ -616,45 +607,6 @@
 
 #endif /* 440EP || 440GR || 440EPX || 440GRX */
 
-/*-----------------------------------------------------------------------------
- | L2 Cache
- +----------------------------------------------------------------------------*/
-#if defined (CONFIG_440GX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
-#define L2_CACHE_BASE	0x030
-#define l2_cache_cfg	(L2_CACHE_BASE+0x00)	/* L2 Cache Config	*/
-#define l2_cache_cmd	(L2_CACHE_BASE+0x01)	/* L2 Cache Command	*/
-#define l2_cache_addr	(L2_CACHE_BASE+0x02)	/* L2 Cache Address	*/
-#define l2_cache_data	(L2_CACHE_BASE+0x03)	/* L2 Cache Data	*/
-#define l2_cache_stat	(L2_CACHE_BASE+0x04)	/* L2 Cache Status	*/
-#define l2_cache_cver	(L2_CACHE_BASE+0x05)	/* L2 Cache Revision ID */
-#define l2_cache_snp0	(L2_CACHE_BASE+0x06)	/* L2 Cache Snoop reg 0 */
-#define l2_cache_snp1	(L2_CACHE_BASE+0x07)	/* L2 Cache Snoop reg 1 */
-
-#endif /* CONFIG_440GX */
-
-/*-----------------------------------------------------------------------------
- | Internal SRAM
- +----------------------------------------------------------------------------*/
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define ISRAM0_DCR_BASE 0x380
-#else
-#define ISRAM0_DCR_BASE 0x020
-#endif
-#define isram0_sb0cr	(ISRAM0_DCR_BASE+0x00)	/* SRAM bank config 0*/
-#define isram0_sb1cr	(ISRAM0_DCR_BASE+0x01)	/* SRAM bank config 1*/
-#define isram0_sb2cr	(ISRAM0_DCR_BASE+0x02)	/* SRAM bank config 2*/
-#define isram0_sb3cr	(ISRAM0_DCR_BASE+0x03)	/* SRAM bank config 3*/
-#define isram0_bear	(ISRAM0_DCR_BASE+0x04)	/* SRAM bus error addr reg */
-#define isram0_besr0	(ISRAM0_DCR_BASE+0x05)	/* SRAM bus error status reg 0 */
-#define isram0_besr1	(ISRAM0_DCR_BASE+0x06)	/* SRAM bus error status reg 1 */
-#define isram0_pmeg	(ISRAM0_DCR_BASE+0x07)	/* SRAM power management */
-#define isram0_cid	(ISRAM0_DCR_BASE+0x08)	/* SRAM bus core id reg */
-#define isram0_revid	(ISRAM0_DCR_BASE+0x09)	/* SRAM bus revision id reg */
-#define isram0_dpc	(ISRAM0_DCR_BASE+0x0a)	/* SRAM data parity check reg */
-
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
@@ -1349,6 +1301,9 @@
 #define SDR0_ETH_CFG_ZMII_RMII_MODE_10M		0x10
 #define SDR0_ETH_CFG_ZMII_RMII_MODE_100M	0x11
 
+/* Ethernet Status Register */
+#define SDR0_ETH_STS		0x4104
+
 /* Miscealleneaous Function Reg. (SDR0_MFR) */
 #define SDR0_MFR		0x4300
 #define SDR0_MFR_T0TxFL		0x00800000	/* force parity error TAHOE0 Tx FIFO bits 0:63 */
@@ -1886,17 +1841,17 @@
 /*-----------------------------------------------------------------------------
 | PCI Internal Registers et. al. (accessed via plb)
 +----------------------------------------------------------------------------*/
-#define PCIX0_CFGADR		(CFG_PCI_BASE + 0x0ec00000)
-#define PCIX0_CFGDATA		(CFG_PCI_BASE + 0x0ec00004)
-#define PCIX0_CFGBASE		(CFG_PCI_BASE + 0x0ec80000)
-#define PCIX0_IOBASE		(CFG_PCI_BASE + 0x08000000)
+#define PCIX0_CFGADR		(CONFIG_SYS_PCI_BASE + 0x0ec00000)
+#define PCIX0_CFGDATA		(CONFIG_SYS_PCI_BASE + 0x0ec00004)
+#define PCIX0_CFGBASE		(CONFIG_SYS_PCI_BASE + 0x0ec80000)
+#define PCIX0_IOBASE		(CONFIG_SYS_PCI_BASE + 0x08000000)
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 
 /* PCI Local Configuration Registers
    --------------------------------- */
-#define PCI_MMIO_LCR_BASE (CFG_PCI_BASE + 0x0f400000)    /* Real => 0x0EF400000 */
+#define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000)    /* Real => 0x0EF400000 */
 
 /* PCI Master Local Configuration Registers */
 #define PCIX0_PMM0LA         (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
@@ -1981,7 +1936,7 @@
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 
 /* USB2.0 Device */
-#define USB2D0_BASE         CFG_USB2D0_BASE
+#define USB2D0_BASE         CONFIG_SYS_USB2D0_BASE
 
 #define USB2D0_INTRIN       (USB2D0_BASE + 0x00000000)
 
@@ -2011,7 +1966,7 @@
 #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460SX)
-#define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000700)
+#define GPIO0_BASE             (CONFIG_SYS_PERIPHERAL_BASE+0x00000700)
 
 #define GPIO0_OR               (GPIO0_BASE+0x0)
 #define GPIO0_TCR              (GPIO0_BASE+0x4)
@@ -2022,8 +1977,8 @@
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000B00)
-#define GPIO1_BASE             (CFG_PERIPHERAL_BASE+0x00000C00)
+#define GPIO0_BASE             (CONFIG_SYS_PERIPHERAL_BASE+0x00000B00)
+#define GPIO1_BASE             (CONFIG_SYS_PERIPHERAL_BASE+0x00000C00)
 
 #define GPIO0_OR               (GPIO0_BASE+0x0)
 #define GPIO0_TCR              (GPIO0_BASE+0x4)
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index e216663..f147885 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -107,8 +107,8 @@
  * Enable long long (%ll ...) printf format on 440 PPC's since most of
  * them support 36bit physical addressing
  */
-#define CFG_64BIT_VSPRINTF
-#define CFG_64BIT_STRTOUL
+#define CONFIG_SYS_64BIT_VSPRINTF
+#define CONFIG_SYS_64BIT_STRTOUL
 #include <ppc440.h>
 #else
 #include <ppc405.h>
@@ -143,7 +143,7 @@
 #define _START_OFFSET		(EXC_OFF_SYS_RESET + 0x2000)
 
 #define RESET_VECTOR	0xfffffffc
-#define CACHELINE_MASK	(CFG_CACHELINE_SIZE - 1) /* Address mask for cache
+#define CACHELINE_MASK	(CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache
 						     line aligned data. */
 
 #define CPR0_DCR_BASE	0x0C
@@ -218,4 +218,7 @@ static inline void set_mcsr(u32 val)
 
 #endif	/* __ASSEMBLY__ */
 
+/* for multi-cpu support */
+#define NA_OR_UNKNOWN_CPU	-1
+
 #endif	/* __PPC4XX_H__ */
diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
index 00669a7..3e10883 100644
--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@@ -171,9 +171,9 @@ typedef struct emac_4xx_hw_st {
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define ZMII_BASE		(CFG_PERIPHERAL_BASE + 0x0D00)
+#define ZMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0D00)
 #else
-#define ZMII_BASE		(CFG_PERIPHERAL_BASE + 0x0780)
+#define ZMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0780)
 #endif
 #define ZMII_FER		(ZMII_BASE)
 #define ZMII_SSR		(ZMII_BASE + 4)
@@ -216,13 +216,13 @@ typedef struct emac_4xx_hw_st {
 
 /* RGMII Register Addresses */
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define RGMII_BASE		(CFG_PERIPHERAL_BASE + 0x1000)
+#define RGMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x1000)
 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define RGMII_BASE		(CFG_PERIPHERAL_BASE + 0x1500)
+#define RGMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x1500)
 #elif defined(CONFIG_405EX)
-#define RGMII_BASE		(CFG_PERIPHERAL_BASE + 0xB00)
+#define RGMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0xB00)
 #else
-#define RGMII_BASE		(CFG_PERIPHERAL_BASE + 0x0790)
+#define RGMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0790)
 #endif
 #define RGMII_FER		(RGMII_BASE + 0x00)
 #define RGMII_SSR		(RGMII_BASE + 0x04)
@@ -260,7 +260,7 @@ typedef struct emac_4xx_hw_st {
 |  TCP/IP Acceleration Hardware (TAH) 440GX Only
 +---------------------------------------------------------------------------*/
 #if defined(CONFIG_440GX)
-#define TAH_BASE		(CFG_PERIPHERAL_BASE + 0x0B50)
+#define TAH_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0B50)
 #define TAH_REVID		(TAH_BASE + 0x0)    /* Revision ID (RO)*/
 #define TAH_MR			(TAH_BASE + 0x10)   /* Mode Register (R/W) */
 #define TAH_SSR0		(TAH_BASE + 0x14)   /* Segment Size Reg 0 (R/W) */
@@ -326,9 +326,9 @@ typedef struct emac_4xx_hw_st {
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define EMAC_BASE		(CFG_PERIPHERAL_BASE + 0x0E00)
+#define EMAC_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0E00)
 #else
-#define EMAC_BASE		(CFG_PERIPHERAL_BASE + 0x0800)
+#define EMAC_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
 #endif
 #else
 #if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
diff --git a/include/ps2mult.h b/include/ps2mult.h
index e685817..599cb6d 100644
--- a/include/ps2mult.h
+++ b/include/ps2mult.h
@@ -22,7 +22,7 @@
 #define	PS2BUF_SIZE			512	/* power of 2, please */
 
 #ifndef CONFIG_PS2MULT_DELAY
-#define CONFIG_PS2MULT_DELAY	(CFG_HZ/2)	/* Initial delay	*/
+#define CONFIG_PS2MULT_DELAY	(CONFIG_SYS_HZ/2)	/* Initial delay	*/
 #endif
 
   /* PS/2 controller interface (include/asm/keyboard.h)
diff --git a/include/radeon.h b/include/radeon.h
index 35875f1..da6c26b 100644
--- a/include/radeon.h
+++ b/include/radeon.h
@@ -513,11 +513,11 @@
 #define PLL_WR_EN			0x00000080
 
 /* CONFIG_CNTL bit constants */
-#define CFG_VGA_RAM_EN			0x00000100
-#define CFG_ATI_REV_ID_MASK		(0xf << 16)
-#define CFG_ATI_REV_A11			(0 << 16)
-#define CFG_ATI_REV_A12			(1 << 16)
-#define CFG_ATI_REV_A13			(2 << 16)
+#define CONFIG_SYS_VGA_RAM_EN			0x00000100
+#define CONFIG_SYS_ATI_REV_ID_MASK		(0xf << 16)
+#define CONFIG_SYS_ATI_REV_A11			(0 << 16)
+#define CONFIG_SYS_ATI_REV_A12			(1 << 16)
+#define CONFIG_SYS_ATI_REV_A13			(2 << 16)
 
 /* CRTC_EXT_CNTL bit constants */
 #define VGA_ATI_LINEAR			0x00000008
diff --git a/include/sata.h b/include/sata.h
index 57ee9ac..37573cf 100644
--- a/include/sata.h
+++ b/include/sata.h
@@ -7,5 +7,6 @@ ulong sata_read(int dev, ulong blknr, ulong blkcnt, void *buffer);
 ulong sata_write(int dev, ulong blknr, ulong blkcnt, const void *buffer);
 
 int sata_initialize(void);
+int __sata_initialize(void);
 
 #endif
diff --git a/include/serial.h b/include/serial.h
index 2b99e53..e3d8b36 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -27,12 +27,12 @@ extern struct serial_device * default_serial_console (void);
     defined(CONFIG_MPC5xxx)
 extern struct serial_device serial0_device;
 extern struct serial_device serial1_device;
-#if defined(CFG_NS16550_SERIAL)
+#if defined(CONFIG_SYS_NS16550_SERIAL)
 extern struct serial_device eserial1_device;
 extern struct serial_device eserial2_device;
 extern struct serial_device eserial3_device;
 extern struct serial_device eserial4_device;
-#endif /* CFG_NS16550_SERIAL */
+#endif /* CONFIG_SYS_NS16550_SERIAL */
 
 #endif
 
diff --git a/include/status_led.h b/include/status_led.h
index d12bb67..175972a 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -50,7 +50,7 @@ void status_led_set  (int led, int state);
 # define STATUS_LED_DAT		im_cpm.cp_pbdat
 
 # define STATUS_LED_BIT		0x00000001
-# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
 # define STATUS_LED_STATE	STATUS_LED_BLINKING
 
 # define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
@@ -65,7 +65,7 @@ void status_led_set  (int led, int state);
 # define STATUS_LED_DAT		im_ioport.iop_pddat
 
 # define STATUS_LED_BIT		0x00000001
-# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
 # define STATUS_LED_STATE	STATUS_LED_BLINKING
 
 # define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
@@ -81,7 +81,7 @@ void status_led_set  (int led, int state);
 # define STATUS_LED_DAT		im_ioport.iop_pddat
 
 # define STATUS_LED_BIT		0x00000001
-# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
 # define STATUS_LED_STATE	STATUS_LED_BLINKING
 
 # define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
@@ -97,16 +97,16 @@ void status_led_set  (int led, int state);
 # define STATUS_LED_DAT			im_ioport.iop_padat
 
 # define STATUS_LED_BIT			0x0800	/* Red LED 0 is on PA.4	*/
-# define STATUS_LED_PERIOD		(CFG_HZ / 4)
+# define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 4)
 # define STATUS_LED_STATE		STATUS_LED_OFF
 # define STATUS_LED_BIT1		0x0400	/* Grn LED 1 is on PA.5	*/
-# define STATUS_LED_PERIOD1		(CFG_HZ / 8)
+# define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 8)
 # define STATUS_LED_STATE1		STATUS_LED_BLINKING
 # define STATUS_LED_BIT2		0x0080	/* Red LED 2 is on PA.8	*/
-# define STATUS_LED_PERIOD2		(CFG_HZ / 4)
+# define STATUS_LED_PERIOD2		(CONFIG_SYS_HZ / 4)
 # define STATUS_LED_STATE2		STATUS_LED_OFF
 # define STATUS_LED_BIT3		0x0040	/* Grn LED 3 is on PA.9	*/
-# define STATUS_LED_PERIOD3		(CFG_HZ / 4)
+# define STATUS_LED_PERIOD3		(CONFIG_SYS_HZ / 4)
 # define STATUS_LED_STATE3		STATUS_LED_OFF
 
 # define STATUS_LED_ACTIVE		1	/* LED on for bit == 1	*/
@@ -121,21 +121,21 @@ void status_led_set  (int led, int state);
 # define STATUS_LED_DAT		im_cpm.cp_pbdat
 
 # define STATUS_LED_BIT		0x00000010	/* LED 0 is on PB.27	*/
-# define STATUS_LED_PERIOD	(1 * CFG_HZ)
+# define STATUS_LED_PERIOD	(1 * CONFIG_SYS_HZ)
 # define STATUS_LED_STATE	STATUS_LED_OFF
 # define STATUS_LED_BIT1	0x00000020	/* LED 1 is on PB.26	*/
-# define STATUS_LED_PERIOD1	(1 * CFG_HZ)
+# define STATUS_LED_PERIOD1	(1 * CONFIG_SYS_HZ)
 # define STATUS_LED_STATE1	STATUS_LED_OFF
 /* IDE LED usable for other purposes, too */
 # define STATUS_LED_BIT2	0x00000008	/* LED 2 is on PB.28	*/
-# define STATUS_LED_PERIOD2	(1 * CFG_HZ)
+# define STATUS_LED_PERIOD2	(1 * CONFIG_SYS_HZ)
 # define STATUS_LED_STATE2	STATUS_LED_OFF
 
 # define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
 
 # define STATUS_ILOCK_SWITCH	0x00800000	/* ILOCK switch in IRQ4	*/
 
-# define STATUS_ILOCK_PERIOD	(CFG_HZ / 10)	/* about every 100 ms	*/
+# define STATUS_ILOCK_PERIOD	(CONFIG_SYS_HZ / 10)	/* about every 100 ms	*/
 
 # define STATUS_LED_YELLOW	0
 # define STATUS_LED_GREEN	1
@@ -150,21 +150,21 @@ void status_led_set  (int led, int state);
 # define STATUS_LED_DAT		im_cpm.cp_pbdat
 
 # define STATUS_LED_BIT		0x00000010	/* LED 0 is on PB.27	*/
-# define STATUS_LED_PERIOD	(1 * CFG_HZ)
+# define STATUS_LED_PERIOD	(1 * CONFIG_SYS_HZ)
 # define STATUS_LED_STATE	STATUS_LED_OFF
 # define STATUS_LED_BIT1	0x00000020	/* LED 1 is on PB.26	*/
-# define STATUS_LED_PERIOD1	(1 * CFG_HZ)
+# define STATUS_LED_PERIOD1	(1 * CONFIG_SYS_HZ)
 # define STATUS_LED_STATE1	STATUS_LED_OFF
 /* IDE LED usable for other purposes, too */
 # define STATUS_LED_BIT2	0x00000008	/* LED 2 is on PB.28	*/
-# define STATUS_LED_PERIOD2	(1 * CFG_HZ)
+# define STATUS_LED_PERIOD2	(1 * CONFIG_SYS_HZ)
 # define STATUS_LED_STATE2	STATUS_LED_OFF
 
 # define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
 
 # define STATUS_ILOCK_SWITCH	0x00004000	/* ILOCK is on PB.17	*/
 
-# define STATUS_ILOCK_PERIOD	(CFG_HZ / 10)	/* about every 100 ms	*/
+# define STATUS_ILOCK_PERIOD	(CONFIG_SYS_HZ / 10)	/* about every 100 ms	*/
 
 # define STATUS_LED_YELLOW	0
 # define STATUS_LED_GREEN	1
@@ -183,7 +183,7 @@ void status_led_set  (int led, int state);
 # else
 #  define STATUS_LED_BIT	0x0800
 # endif
-# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
 # define STATUS_LED_STATE	STATUS_LED_BLINKING
 
 # define STATUS_LED_ACTIVE	0		/* LED on for bit == 0 */
@@ -199,7 +199,7 @@ void status_led_set  (int led, int state);
 # define STATUS_LED_DAT		im_cpm.cp_pbdat
 
 # define STATUS_LED_BIT		0x00010000	/* green LED is on PB.15 */
-# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
 # define STATUS_LED_STATE	STATUS_LED_BLINKING
 
 # define STATUS_LED_ACTIVE	1		/* LED on for bit == 1 */
@@ -215,10 +215,10 @@ void status_led_set  (int led, int state);
 # define STATUS_LED_DAT		im_ioport.iop_padat
 
 # define STATUS_LED_BIT		0x4000		/* LED 0 is on PA.1 */
-# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
 # define STATUS_LED_STATE	STATUS_LED_BLINKING
 # define STATUS_LED_BIT1	0x1000		/* LED 1 is on PA.3 */
-# define STATUS_LED_PERIOD1	(CFG_HZ)
+# define STATUS_LED_PERIOD1	(CONFIG_SYS_HZ)
 # define STATUS_LED_STATE1	STATUS_LED_OFF
 
 # define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
@@ -244,11 +244,11 @@ void status_led_set  (int led, int state);
 #define STATUS_LED_DAT		im_ioport.iop_pddat
 
 # define STATUS_LED_BIT		0x0080			/* PD.8 */
-# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
 # define STATUS_LED_STATE	STATUS_LED_BLINKING
 
 # define STATUS_LED_BIT1	0x0040			/* PD.9 */
-# define STATUS_LED_PERIOD1	(CFG_HZ / 2)
+# define STATUS_LED_PERIOD1	(CONFIG_SYS_HZ / 2)
 # define STATUS_LED_STATE1	STATUS_LED_OFF
 
 # define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
@@ -263,7 +263,7 @@ void status_led_set  (int led, int state);
 
 # define STATUS_LED_BIT		0x2000		/* Select one of the 16 possible*/
 						/* MIOS outputs */
-# define STATUS_LED_PERIOD	(CFG_HZ / 2)	/* Blinking periode is 500 ms */
+# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)	/* Blinking periode is 500 ms */
 # define STATUS_LED_STATE	STATUS_LED_BLINKING
 
 # define STATUS_LED_ACTIVE	1		/* LED on for bit == 0	*/
@@ -278,7 +278,7 @@ void status_led_set  (int led, int state);
 # define STATUS_LED_DAT		im_ioport.iop_padat
 
 # define STATUS_LED_BIT		0x00000300  /*  green + red    PA[8]=yellow,  PA[7]=red,  PA[6]=green */
-# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
 # define STATUS_LED_STATE	STATUS_LED_BLINKING
 
 # define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
@@ -292,7 +292,7 @@ void status_led_set  (int led, int state);
 # define STATUS_LED_DAT         im_cpm.cp_pbdat
 
 # define STATUS_LED_BIT         0x00000001
-# define STATUS_LED_PERIOD      (CFG_HZ / 2)
+# define STATUS_LED_PERIOD      (CONFIG_SYS_HZ / 2)
 # define STATUS_LED_STATE       STATUS_LED_BLINKING
 
 # define STATUS_LED_ACTIVE      1               /* LED on for bit == 1  */
@@ -308,10 +308,10 @@ void status_led_set  (int led, int state);
 # define STATUS_LED_DAT         im_ioport.iop_pcdat
 
 # define STATUS_LED_BIT         0x0002          /* LED 0 is on PC.14 */
-# define STATUS_LED_PERIOD      (CFG_HZ / 2)
+# define STATUS_LED_PERIOD      (CONFIG_SYS_HZ / 2)
 # define STATUS_LED_STATE       STATUS_LED_BLINKING
 # define STATUS_LED_BIT1        0x0004          /* LED 1 is on PC.13 */
-# define STATUS_LED_PERIOD1     (CFG_HZ)
+# define STATUS_LED_PERIOD1     (CONFIG_SYS_HZ)
 # define STATUS_LED_STATE1      STATUS_LED_OFF
 
 # define STATUS_LED_ACTIVE      1               /* LED on for bit == 1  */
@@ -326,7 +326,7 @@ void status_led_set  (int led, int state);
 # define STATUS_LED_DAT		im_ioport.iop_padat
 
 # define STATUS_LED_BIT		0x00000001	/* LED is on PA15 */
-# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
 # define STATUS_LED_STATE	STATUS_LED_BLINKING
 
 # define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
@@ -346,10 +346,13 @@ void status_led_set  (int led, int state);
 #elif defined(CONFIG_NIOS2)
 /* XXX empty just to avoid the error */
 /************************************************************************/
+#elif defined(CONFIG_BLACKFIN)
+/* XXX empty just to avoid the error */
+/************************************************************************/
 #elif defined(CONFIG_V38B)
 
 # define STATUS_LED_BIT		0x0010			/* Timer7 GPIO */
-# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
 # define STATUS_LED_STATE	STATUS_LED_BLINKING
 
 # define STATUS_LED_ACTIVE	0		/* LED on for bit == 0 */
@@ -358,11 +361,11 @@ void status_led_set  (int led, int state);
 #elif defined(CONFIG_MOTIONPRO)
 
 #define STATUS_LED_BIT		((vu_long *) MPC5XXX_GPT6_ENABLE)
-#define STATUS_LED_PERIOD	(CFG_HZ / 10)
+#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 10)
 #define STATUS_LED_STATE	STATUS_LED_BLINKING
 
 #define STATUS_LED_BIT1		((vu_long *) MPC5XXX_GPT7_ENABLE)
-#define STATUS_LED_PERIOD1	(CFG_HZ / 10)
+#define STATUS_LED_PERIOD1	(CONFIG_SYS_HZ / 10)
 #define STATUS_LED_STATE1	STATUS_LED_OFF
 
 #define STATUS_LED_BOOT		0	/* LED 0 used for boot status */
diff --git a/include/timestamp.h b/include/timestamp.h
new file mode 100644
index 0000000..b2f4cf4
--- /dev/null
+++ b/include/timestamp.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__TIMESTAMP_H__
+#define	__TIMESTAMP_H__
+
+#ifndef DO_DEPS_ONLY
+#include "timestamp_autogenerated.h"
+#endif
+
+#endif	/* __TIMESTAMP_H__ */
diff --git a/include/tsec.h b/include/tsec.h
index f7e5857..7b52e06 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -20,8 +20,8 @@
 #include <net.h>
 #include <config.h>
 
-#ifndef CFG_TSEC1_OFFSET
-    #define CFG_TSEC1_OFFSET	(0x24000)
+#ifndef CONFIG_SYS_TSEC1_OFFSET
+    #define CONFIG_SYS_TSEC1_OFFSET	(0x24000)
 #endif
 
 #define TSEC_SIZE	0x01000
@@ -29,7 +29,7 @@
 /* FIXME:  Should these be pushed back to 83xx and 85xx config files? */
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \
 	|| defined(CONFIG_MPC83XX)
-    #define TSEC_BASE_ADDR	(CFG_IMMR + CFG_TSEC1_OFFSET)
+    #define TSEC_BASE_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 #endif
 
 #define STD_TSEC_INFO(num) \
@@ -107,8 +107,8 @@
 #define miim_end -2
 #define miim_read -1
 
-#ifndef CFG_TBIPA_VALUE
-    #define CFG_TBIPA_VALUE	0x1f
+#ifndef CONFIG_SYS_TBIPA_VALUE
+    #define CONFIG_SYS_TBIPA_VALUE	0x1f
 #endif
 #define MIIMCFG_INIT_VALUE	0x00000003
 #define MIIMCFG_RESET		0x80000000
@@ -226,6 +226,10 @@
 #define MIIM_88E1121_PHY_LED_PAGE	3
 #define MIIM_88E1121_PHY_LED_DEF	0x0030
 
+/* 88E1121 PHY IRQ Enable/Status Register */
+#define MIIM_88E1121_PHY_IRQ_EN		18
+#define MIIM_88E1121_PHY_IRQ_STATUS	19
+
 #define MIIM_88E1121_PHY_PAGE		22
 
 /* 88E1145 Extended PHY Specific Control Register */
diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h
new file mode 100644
index 0000000..b415219
--- /dev/null
+++ b/include/ubi_uboot.h
@@ -0,0 +1,218 @@
+/*
+ * Header file for UBI support for U-Boot
+ *
+ * Adaptation from kernel to U-Boot
+ *
+ *  Copyright (C) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __UBOOT_UBI_H
+#define __UBOOT_UBI_H
+
+#include <common.h>
+#include <malloc.h>
+#include <div64.h>
+#include <linux/crc32.h>
+#include <linux/mtd/mtd.h>
+
+#ifdef CONFIG_CMD_ONENAND
+#include <onenand_uboot.h>
+#endif
+
+#include <asm/errno.h>
+
+#define DPRINTK(format, args...)					\
+do {									\
+	printf("%s[%d]: " format "\n", __func__, __LINE__, ##args);	\
+} while (0)
+
+/* configurable */
+#define CONFIG_MTD_UBI_WL_THRESHOLD	4096
+#define CONFIG_MTD_UBI_BEB_RESERVE	1
+#define UBI_IO_DEBUG			0
+
+/* debug options (Linux: drivers/mtd/ubi/Kconfig.debug) */
+#undef CONFIG_MTD_UBI_DEBUG
+#undef CONFIG_MTD_UBI_DEBUG_PARANOID
+#undef CONFIG_MTD_UBI_DEBUG_MSG
+#undef CONFIG_MTD_UBI_DEBUG_MSG_EBA
+#undef CONFIG_MTD_UBI_DEBUG_MSG_WL
+#undef CONFIG_MTD_UBI_DEBUG_MSG_IO
+#undef CONFIG_MTD_UBI_DEBUG_MSG_BLD
+#define CONFIG_MTD_UBI_DEBUG_DISABLE_BGT
+
+/* compiler options */
+#define uninitialized_var(x)		x = x
+
+/* build.c */
+#define get_device(...)
+#define put_device(...)
+#define ubi_sysfs_init(...)		0
+#define ubi_sysfs_close(...)		do { } while (0)
+static inline int is_power_of_2(unsigned long n)
+{
+	return (n != 0 && ((n & (n - 1)) == 0));
+}
+
+/* FIXME */
+#define MKDEV(...)			0
+#define MAJOR(dev)			0
+#define MINOR(dev)			0
+
+#define alloc_chrdev_region(...)	0
+#define unregister_chrdev_region(...)
+
+#define class_create(...)		__builtin_return_address(0)
+#define class_create_file(...)		0
+#define class_remove_file(...)
+#define class_destroy(...)
+#define misc_register(...)		0
+#define misc_deregister(...)
+
+/* vmt.c */
+#define device_register(...)		0
+#define volume_sysfs_init(...)		0
+#define volume_sysfs_close(...)		do { } while (0)
+
+/* kapi.c */
+
+/* eba.c */
+
+/* io.c */
+#define init_waitqueue_head(...)	do { } while (0)
+#define wait_event_interruptible(...)	0
+#define wake_up_interruptible(...)	do { } while (0)
+#define print_hex_dump(...)		do { } while (0)
+#define dump_stack(...)			do { } while (0)
+
+/* wl.c */
+#define task_pid_nr(x)			0
+#define set_freezable(...)		do { } while (0)
+#define try_to_freeze(...)		0
+#define set_current_state(...)		do { } while (0)
+#define kthread_should_stop(...)	0
+#define schedule()			do { } while (0)
+
+/* upd.c */
+static inline unsigned long copy_from_user(void *dest, const void *src,
+					   unsigned long count)
+{
+	memcpy((void *)dest, (void *)src, count);
+	return 0;
+}
+
+/* common */
+typedef int	spinlock_t;
+typedef int	wait_queue_head_t;
+#define spin_lock_init(...)
+#define spin_lock(...)
+#define spin_unlock(...)
+
+#define mutex_init(...)
+#define mutex_lock(...)
+#define mutex_unlock(...)
+
+#define init_rwsem(...)			do { } while (0)
+#define down_read(...)			do { } while (0)
+#define down_write(...)			do { } while (0)
+#define down_write_trylock(...)		0
+#define up_read(...)			do { } while (0)
+#define up_write(...)			do { } while (0)
+
+struct kmem_cache { int i; };
+#define kmem_cache_create(...)		1
+#define kmem_cache_alloc(obj, gfp)	malloc(sizeof(struct ubi_wl_entry))
+#define kmem_cache_free(obj, size)	free(size)
+#define kmem_cache_destroy(...)
+
+#define cond_resched()			do { } while (0)
+#define yield()				do { } while (0)
+
+#define KERN_WARNING
+#define KERN_ERR
+#define KERN_NOTICE
+#define KERN_DEBUG
+
+#define GFP_KERNEL			0
+#define GFP_NOFS			1
+
+#define __user
+#define __init
+#define __exit
+
+#define kthread_create(...)	__builtin_return_address(0)
+#define kthread_stop(...)	do { } while (0)
+#define wake_up_process(...)	do { } while (0)
+
+#define BUS_ID_SIZE		20
+
+struct rw_semaphore { int i; };
+struct device {
+	struct device		*parent;
+	struct class		*class;
+	char	bus_id[BUS_ID_SIZE];	/* position on parent bus */
+	dev_t			devt;	/* dev_t, creates the sysfs "dev" */
+	void	(*release)(struct device *dev);
+};
+struct mutex { int i; };
+struct kernel_param { int i; };
+
+struct cdev {
+	int owner;
+	dev_t dev;
+};
+#define cdev_init(...)		do { } while (0)
+#define cdev_add(...)		0
+#define cdev_del(...)		do { } while (0)
+
+#define MAX_ERRNO		4095
+#define IS_ERR_VALUE(x)		((x) >= (unsigned long)-MAX_ERRNO)
+
+static inline void *ERR_PTR(long error)
+{
+	return (void *) error;
+}
+
+static inline long PTR_ERR(const void *ptr)
+{
+	return (long) ptr;
+}
+
+static inline long IS_ERR(const void *ptr)
+{
+	return IS_ERR_VALUE((unsigned long)ptr);
+}
+
+/* Force a compilation error if condition is true */
+#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
+
+/* module */
+#define THIS_MODULE		0
+#define try_module_get(...)	0
+#define module_put(...)		do { } while (0)
+#define module_init(...)
+#define module_exit(...)
+#define EXPORT_SYMBOL(...)
+#define EXPORT_SYMBOL_GPL(...)
+#define module_param_call(...)
+#define MODULE_PARM_DESC(...)
+#define MODULE_VERSION(...)
+#define MODULE_DESCRIPTION(...)
+#define MODULE_AUTHOR(...)
+#define MODULE_LICENSE(...)
+
+#include "../drivers/mtd/ubi/ubi.h"
+
+/* functions */
+extern int ubi_mtd_param_parse(const char *val, struct kernel_param *kp);
+extern int ubi_init(void);
+extern void ubi_exit(void);
+
+extern struct ubi_device *ubi_devices[];
+
+#endif
diff --git a/include/usb.h b/include/usb.h
index e68e98e..7c47098 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -43,104 +43,114 @@
 
 /* String descriptor */
 struct usb_string_descriptor {
-	unsigned char  bLength;
-	unsigned char  bDescriptorType;
-	unsigned short wData[1];
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned short	wData[1];
 } __attribute__ ((packed));
 
 /* device request (setup) */
 struct devrequest {
-	unsigned char requesttype;
-	unsigned char request;
-	unsigned short value;
-	unsigned short index;
-	unsigned short length;
+	unsigned char	requesttype;
+	unsigned char	request;
+	unsigned short	value;
+	unsigned short	index;
+	unsigned short	length;
 } __attribute__ ((packed));
 
-
 /* All standard descriptors have these 2 fields in common */
 struct usb_descriptor_header {
-	unsigned char  bLength;
-	unsigned char  bDescriptorType;
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
 } __attribute__ ((packed));
 
 /* Device descriptor */
 struct usb_device_descriptor {
-	unsigned char  bLength;
-	unsigned char  bDescriptorType;
-	unsigned short bcdUSB;
-	unsigned char  bDeviceClass;
-	unsigned char  bDeviceSubClass;
-	unsigned char  bDeviceProtocol;
-	unsigned char  bMaxPacketSize0;
-	unsigned short idVendor;
-	unsigned short idProduct;
-	unsigned short bcdDevice;
-	unsigned char  iManufacturer;
-	unsigned char  iProduct;
-	unsigned char  iSerialNumber;
-	unsigned char  bNumConfigurations;
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned short	bcdUSB;
+	unsigned char	bDeviceClass;
+	unsigned char	bDeviceSubClass;
+	unsigned char	bDeviceProtocol;
+	unsigned char	bMaxPacketSize0;
+	unsigned short	idVendor;
+	unsigned short	idProduct;
+	unsigned short	bcdDevice;
+	unsigned char	iManufacturer;
+	unsigned char	iProduct;
+	unsigned char	iSerialNumber;
+	unsigned char	bNumConfigurations;
 } __attribute__ ((packed));
 
-
 /* Endpoint descriptor */
 struct usb_endpoint_descriptor {
-	unsigned char  bLength;
-	unsigned char  bDescriptorType;
-	unsigned char  bEndpointAddress;
-	unsigned char  bmAttributes;
-	unsigned short wMaxPacketSize;
-	unsigned char  bInterval;
-	unsigned char  bRefresh;
-	unsigned char  bSynchAddress;
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned char	bEndpointAddress;
+	unsigned char	bmAttributes;
+	unsigned short	wMaxPacketSize;
+	unsigned char	bInterval;
+	unsigned char	bRefresh;
+	unsigned char	bSynchAddress;
+} __attribute__ ((packed)) __attribute__ ((aligned(2)));
 
-} __attribute__ ((packed));
 /* Interface descriptor */
 struct usb_interface_descriptor {
-	unsigned char  bLength;
-	unsigned char  bDescriptorType;
-	unsigned char  bInterfaceNumber;
-	unsigned char  bAlternateSetting;
-	unsigned char  bNumEndpoints;
-	unsigned char  bInterfaceClass;
-	unsigned char  bInterfaceSubClass;
-	unsigned char  bInterfaceProtocol;
-	unsigned char  iInterface;
-
-	unsigned char  no_of_ep;
-	unsigned char  num_altsetting;
-	unsigned char  act_altsetting;
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned char	bInterfaceNumber;
+	unsigned char	bAlternateSetting;
+	unsigned char	bNumEndpoints;
+	unsigned char	bInterfaceClass;
+	unsigned char	bInterfaceSubClass;
+	unsigned char	bInterfaceProtocol;
+	unsigned char	iInterface;
+
+	unsigned char	no_of_ep;
+	unsigned char	num_altsetting;
+	unsigned char	act_altsetting;
+
 	struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
 } __attribute__ ((packed));
 
 
 /* Configuration descriptor information.. */
 struct usb_config_descriptor {
-	unsigned char  bLength;
-	unsigned char  bDescriptorType;
-	unsigned short wTotalLength;
-	unsigned char  bNumInterfaces;
-	unsigned char  bConfigurationValue;
-	unsigned char  iConfiguration;
-	unsigned char  bmAttributes;
-	unsigned char  MaxPower;
-
-	unsigned char  no_of_if;		/* number of interfaces */
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned short	wTotalLength;
+	unsigned char	bNumInterfaces;
+	unsigned char	bConfigurationValue;
+	unsigned char	iConfiguration;
+	unsigned char	bmAttributes;
+	unsigned char	MaxPower;
+
+	unsigned char	no_of_if;	/* number of interfaces */
 	struct usb_interface_descriptor if_desc[USB_MAXINTERFACES];
 } __attribute__ ((packed));
 
+enum {
+	/* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */
+	PACKET_SIZE_8   = 0,
+	PACKET_SIZE_16  = 1,
+	PACKET_SIZE_32  = 2,
+	PACKET_SIZE_64  = 3,
+};
 
 struct usb_device {
-	int devnum;			/* Device number on USB bus */
-	int slow;			/* Slow device? */
-	char mf[32];			/* manufacturer */
-	char prod[32];			/* product */
-	char serial[32];		/* serial number */
-
-	int maxpacketsize;		/* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */
-	unsigned int toggle[2];		/* one bit for each endpoint ([0] = IN, [1] = OUT) */
-	unsigned int halted[2];		/* endpoint halts; one bit per endpoint # & direction; */
-			    /* [0] = IN, [1] = OUT */
+	int	devnum;			/* Device number on USB bus */
+	int	speed;			/* full/low/high */
+	char	mf[32];			/* manufacturer */
+	char	prod[32];		/* product */
+	char	serial[32];		/* serial number */
+
+	/* Maximum packet size; one of: PACKET_SIZE_* */
+	int maxpacketsize;
+	/* one bit for each endpoint ([0] = IN, [1] = OUT) */
+	unsigned int toggle[2];
+	/* endpoint halts; one bit per endpoint # & direction;
+	 * [0] = IN, [1] = OUT
+	 */
+	unsigned int halted[2];
 	int epmaxpacketin[16];		/* INput endpoint specific maximums */
 	int epmaxpacketout[16];		/* OUTput endpoint specific maximums */
 
@@ -161,6 +171,7 @@ struct usb_device {
 	unsigned long status;
 	int act_len;			/* transfered bytes */
 	int maxchild;			/* Number of ports if hub */
+	int portnr;
 	struct usb_device *parent;
 	struct usb_device *children[USB_MAXCHILDREN];
 };
@@ -170,21 +181,23 @@ struct usb_device {
  */
 
 #if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \
-	defined(CONFIG_USB_OHCI_NEW) || defined (CONFIG_USB_SL811HS) || \
-	defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_R8A66597_HCD)
+	defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_OHCI_NEW) || \
+	defined(CONFIG_USB_SL811HS) || defined(CONFIG_USB_ISP116X_HCD) || \
+	defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI)
 
 int usb_lowlevel_init(void);
 int usb_lowlevel_stop(void);
-int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len);
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
+			void *buffer, int transfer_len);
 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-			int transfer_len,struct devrequest *setup);
+			int transfer_len, struct devrequest *setup);
 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 			int transfer_len, int interval);
 void usb_event_poll(void);
 
 /* Defines */
-#define USB_UHCI_VEND_ID 0x8086
-#define USB_UHCI_DEV_ID	 0x7112
+#define USB_UHCI_VEND_ID	0x8086
+#define USB_UHCI_DEV_ID		0x7112
 
 #else
 #error USB Lowlevel not defined
@@ -211,8 +224,9 @@ int usb_stop(void); /* stop the USB Controller */
 
 
 int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol);
-int usb_set_idle(struct usb_device *dev, int ifnum, int duration, int report_id);
-struct usb_device * usb_get_dev_index(int index);
+int usb_set_idle(struct usb_device *dev, int ifnum, int duration,
+			int report_id);
+struct usb_device *usb_get_dev_index(int index);
 int usb_control_msg(struct usb_device *dev, unsigned int pipe,
 			unsigned char request, unsigned char requesttype,
 			unsigned short value, unsigned short index,
@@ -220,14 +234,17 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe,
 int usb_bulk_msg(struct usb_device *dev, unsigned int pipe,
 			void *data, int len, int *actual_length, int timeout);
 int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe,
-			void *buffer,int transfer_len, int interval);
+			void *buffer, int transfer_len, int interval);
 void usb_disable_asynch(int disable);
-int usb_maxpacket(struct usb_device *dev,unsigned long pipe);
-void __inline__ wait_ms(unsigned long ms);
-int usb_get_configuration_no(struct usb_device *dev,unsigned char *buffer,int cfgno);
-int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type, unsigned char id, void *buf, int size);
+int usb_maxpacket(struct usb_device *dev, unsigned long pipe);
+inline void wait_ms(unsigned long ms);
+int usb_get_configuration_no(struct usb_device *dev, unsigned char *buffer,
+				int cfgno);
+int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type,
+			unsigned char id, void *buf, int size);
 int usb_get_class_descriptor(struct usb_device *dev, int ifnum,
-		unsigned char type, unsigned char id, void *buf, int size);
+			unsigned char type, unsigned char id, void *buf,
+			int size);
 int usb_clear_halt(struct usb_device *dev, int pipe);
 int usb_string(struct usb_device *dev, int index, char *buf, size_t size);
 int usb_set_interface(struct usb_device *dev, int interface, int alternate);
@@ -237,7 +254,7 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate);
 #define __swap_16(x) \
 	({ unsigned short x_ = (unsigned short)x; \
 	 (unsigned short)( \
-		((x_ & 0x00FFU) << 8) | ((x_ & 0xFF00U) >> 8) ); \
+		((x_ & 0x00FFU) << 8) | ((x_ & 0xFF00U) >> 8)); \
 	})
 #define __swap_32(x) \
 	({ unsigned long x_ = (unsigned long)x; \
@@ -245,16 +262,16 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate);
 		((x_ & 0x000000FFUL) << 24) | \
 		((x_ & 0x0000FF00UL) <<	 8) | \
 		((x_ & 0x00FF0000UL) >>	 8) | \
-		((x_ & 0xFF000000UL) >> 24) ); \
+		((x_ & 0xFF000000UL) >> 24)); \
 	})
 
-#ifdef LITTLEENDIAN
+#ifdef __LITTLE_ENDIAN
 # define swap_16(x) (x)
 # define swap_32(x) (x)
 #else
 # define swap_16(x) __swap_16(x)
 # define swap_32(x) __swap_32(x)
-#endif /* LITTLEENDIAN */
+#endif
 
 /*
  * Calling this entity a "pipe" is glorifying it. A USB pipe
@@ -264,7 +281,7 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate);
  *  - endpoint number (4 bits)
  *  - current Data0/1 state (1 bit)
  *  - direction (1 bit)
- *  - speed (1 bit)
+ *  - speed (2 bits)
  *  - max packet size (2 bits: 8, 16, 32 or 64)
  *  - pipe type (2 bits: control, interrupt, bulk, isochronous)
  *
@@ -276,12 +293,14 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate);
  * unsigned int. The encoding is:
  *
  *  - max size:		bits 0-1	(00 = 8, 01 = 16, 10 = 32, 11 = 64)
- *  - direction:	bit 7		(0 = Host-to-Device [Out], 1 = Device-to-Host [In])
+ *  - direction:	bit 7		(0 = Host-to-Device [Out],
+ *					(1 = Device-to-Host [In])
  *  - device:		bits 8-14
  *  - endpoint:		bits 15-18
  *  - Data0/1:		bit 19
- *  - speed:		bit 26		(0 = Full, 1 = Low Speed)
- *  - pipe type:	bits 30-31	(00 = isochronous, 01 = interrupt, 10 = control, 11 = bulk)
+ *  - speed:		bit 26		(0 = Full, 1 = Low Speed, 2 = High)
+ *  - pipe type:	bits 30-31	(00 = isochronous, 01 = interrupt,
+ *					 10 = control, 11 = bulk)
  *
  * Why? Because it's arbitrary, and whatever encoding we select is really
  * up to us. This one happens to share a lot of bit positions with the UHCI
@@ -290,24 +309,42 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate);
  */
 /* Create various pipes... */
 #define create_pipe(dev,endpoint) \
-		(((dev)->devnum << 8) | (endpoint << 15) | ((dev)->slow << 26) | (dev)->maxpacketsize)
-#define default_pipe(dev) ((dev)->slow <<26)
-
-#define usb_sndctrlpipe(dev,endpoint)	((PIPE_CONTROL << 30) | create_pipe(dev,endpoint))
-#define usb_rcvctrlpipe(dev,endpoint)	((PIPE_CONTROL << 30) | create_pipe(dev,endpoint) | USB_DIR_IN)
-#define usb_sndisocpipe(dev,endpoint)	((PIPE_ISOCHRONOUS << 30) | create_pipe(dev,endpoint))
-#define usb_rcvisocpipe(dev,endpoint)	((PIPE_ISOCHRONOUS << 30) | create_pipe(dev,endpoint) | USB_DIR_IN)
-#define usb_sndbulkpipe(dev,endpoint)	((PIPE_BULK << 30) | create_pipe(dev,endpoint))
-#define usb_rcvbulkpipe(dev,endpoint)	((PIPE_BULK << 30) | create_pipe(dev,endpoint) | USB_DIR_IN)
-#define usb_sndintpipe(dev,endpoint)	((PIPE_INTERRUPT << 30) | create_pipe(dev,endpoint))
-#define usb_rcvintpipe(dev,endpoint)	((PIPE_INTERRUPT << 30) | create_pipe(dev,endpoint) | USB_DIR_IN)
-#define usb_snddefctrl(dev)		((PIPE_CONTROL << 30) | default_pipe(dev))
-#define usb_rcvdefctrl(dev)		((PIPE_CONTROL << 30) | default_pipe(dev) | USB_DIR_IN)
+		(((dev)->devnum << 8) | (endpoint << 15) | \
+		((dev)->speed << 26) | (dev)->maxpacketsize)
+#define default_pipe(dev) ((dev)->speed << 26)
+
+#define usb_sndctrlpipe(dev, endpoint)	((PIPE_CONTROL << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvctrlpipe(dev, endpoint)	((PIPE_CONTROL << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_sndisocpipe(dev, endpoint)	((PIPE_ISOCHRONOUS << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvisocpipe(dev, endpoint)	((PIPE_ISOCHRONOUS << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_sndbulkpipe(dev, endpoint)	((PIPE_BULK << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvbulkpipe(dev, endpoint)	((PIPE_BULK << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_sndintpipe(dev, endpoint)	((PIPE_INTERRUPT << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvintpipe(dev, endpoint)	((PIPE_INTERRUPT << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_snddefctrl(dev)		((PIPE_CONTROL << 30) | \
+					 default_pipe(dev))
+#define usb_rcvdefctrl(dev)		((PIPE_CONTROL << 30) | \
+					 default_pipe(dev) | \
+					 USB_DIR_IN)
 
 /* The D0/D1 toggle bits */
 #define usb_gettoggle(dev, ep, out) (((dev)->toggle[out] >> ep) & 1)
 #define usb_dotoggle(dev, ep, out)  ((dev)->toggle[out] ^= (1 << ep))
-#define usb_settoggle(dev, ep, out, bit) ((dev)->toggle[out] = ((dev)->toggle[out] & ~(1 << ep)) | ((bit) << ep))
+#define usb_settoggle(dev, ep, out, bit) ((dev)->toggle[out] = \
+						((dev)->toggle[out] & \
+						 ~(1 << ep)) | ((bit) << ep))
 
 /* Endpoint halt control/status */
 #define usb_endpoint_out(ep_dir)	(((ep_dir >> 7) & 1) ^ 1)
@@ -315,7 +352,8 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate);
 #define usb_endpoint_running(dev, ep, out) ((dev)->halted[out] &= ~(1 << (ep)))
 #define usb_endpoint_halted(dev, ep, out) ((dev)->halted[out] & (1 << (ep)))
 
-#define usb_packetid(pipe)	(((pipe) & USB_DIR_IN) ? USB_PID_IN : USB_PID_OUT)
+#define usb_packetid(pipe)	(((pipe) & USB_DIR_IN) ? USB_PID_IN : \
+				 USB_PID_OUT)
 
 #define usb_pipeout(pipe)	((((pipe) >> 7) & 1) ^ 1)
 #define usb_pipein(pipe)	(((pipe) >> 7) & 1)
@@ -323,7 +361,8 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate);
 #define usb_pipe_endpdev(pipe)	(((pipe) >> 8) & 0x7ff)
 #define usb_pipeendpoint(pipe)	(((pipe) >> 15) & 0xf)
 #define usb_pipedata(pipe)	(((pipe) >> 19) & 1)
-#define usb_pipeslow(pipe)	(((pipe) >> 26) & 1)
+#define usb_pipespeed(pipe)	(((pipe) >> 26) & 3)
+#define usb_pipeslow(pipe)	(usb_pipespeed(pipe) == USB_SPEED_LOW)
 #define usb_pipetype(pipe)	(((pipe) >> 30) & 3)
 #define usb_pipeisoc(pipe)	(usb_pipetype((pipe)) == PIPE_ISOCHRONOUS)
 #define usb_pipeint(pipe)	(usb_pipetype((pipe)) == PIPE_INTERRUPT)
@@ -355,7 +394,7 @@ struct usb_hub_descriptor {
 	unsigned char  bHubContrCurrent;
 	unsigned char  DeviceRemovable[(USB_MAXCHILDREN+1+7)/8];
 	unsigned char  PortPowerCtrlMask[(USB_MAXCHILDREN+1+7)/8];
-		/* DeviceRemovable and PortPwrCtrlMask want to be variable-length
+	/* DeviceRemovable and PortPwrCtrlMask want to be variable-length
 	   bitmaps that hold max 255 entries. (bit0 is ignored) */
 } __attribute__ ((packed));
 
diff --git a/include/usb_defs.h b/include/usb_defs.h
index 353019f..8032e57 100644
--- a/include/usb_defs.h
+++ b/include/usb_defs.h
@@ -80,6 +80,12 @@
 #define USB_DIR_OUT           0
 #define USB_DIR_IN            0x80
 
+/* USB device speeds */
+#define USB_SPEED_FULL		0x0	/* 12Mbps */
+#define USB_SPEED_LOW		0x1	/* 1.5Mbps */
+#define USB_SPEED_HIGH		0x2	/* 480Mbps */
+#define USB_SPEED_RESERVED	0x3
+
 /* Descriptor types */
 #define USB_DT_DEVICE        0x01
 #define USB_DT_CONFIG        0x02
@@ -202,6 +208,7 @@
 #define USB_PORT_FEAT_RESET          4
 #define USB_PORT_FEAT_POWER          8
 #define USB_PORT_FEAT_LOWSPEED       9
+#define USB_PORT_FEAT_HIGHSPEED      10
 #define USB_PORT_FEAT_C_CONNECTION   16
 #define USB_PORT_FEAT_C_ENABLE       17
 #define USB_PORT_FEAT_C_SUSPEND      18
@@ -216,6 +223,9 @@
 #define USB_PORT_STAT_RESET         0x0010
 #define USB_PORT_STAT_POWER         0x0100
 #define USB_PORT_STAT_LOW_SPEED     0x0200
+#define USB_PORT_STAT_HIGH_SPEED    0x0400	/* support for EHCI */
+#define USB_PORT_STAT_SPEED	\
+	(USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED)
 
 /* wPortChange bits */
 #define USB_PORT_STAT_C_CONNECTION  0x0001
diff --git a/include/usbdcore.h b/include/usbdcore.h
index cb2be72..206dbbc 100644
--- a/include/usbdcore.h
+++ b/include/usbdcore.h
@@ -126,14 +126,6 @@
 				})
 #endif
 
-#ifndef MIN
-#define MIN(a,b) ((a) < (b) ? (a) : (b))
-#endif
-#ifndef MAX
-#define MAX(a,b) ((a) > (b) ? (a) : (b))
-#endif
-
-
 /*
  * Structure member address manipulation macros.
  * These are used by client code (code using the urb_link routines), since
diff --git a/include/usbdcore_omap1510.h b/include/usbdcore_omap1510.h
index 526fcd9..ece0e95 100644
--- a/include/usbdcore_omap1510.h
+++ b/include/usbdcore_omap1510.h
@@ -168,8 +168,8 @@
 #define UDC_IN_ENDPOINT	1
 #define UDC_IN_PACKET_SIZE 64
 #define UDC_INT_ENDPOINT 5
-#define UDC_INT_PKTSIZE	16
-#define UDC_BULK_PKTSIZE 16
+#define UDC_INT_PACKET_SIZE	16
+#define UDC_BULK_PACKET_SIZE 16
 
 void udc_irq (void);
 /* Flow control */
@@ -177,7 +177,7 @@ void udc_set_nak(int epid);
 void udc_unset_nak (int epid);
 
 /* Higher level functions for abstracting away from specific device */
-void udc_endpoint_write(struct usb_endpoint_instance *endpoint);
+int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
 
 int  udc_init (void);
 
diff --git a/include/vxworks.h b/include/vxworks.h
new file mode 100644
index 0000000..1633904
--- /dev/null
+++ b/include/vxworks.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2008
+ * Niklaus Giger, niklaus.giger@member.fsf.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _VXWORKS_H_
+#define _VXWORKS_H_
+
+int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+/*
+ * Use bootaddr to find the location in memory that VxWorks
+ * will look for the bootline string. The default value for
+ * PowerPC is LOCAL_MEM_LOCAL_ADRS + BOOT_LINE_OFFSET which
+ * defaults to 0x4200
+ */
+#ifndef CONFIG_SYS_VXWORKS_BOOT_ADDR
+#define CONFIG_SYS_VXWORKS_BOOT_ADDR 0x4200
+#endif
+
+#ifndef CONFIG_SYS_VXWORKS_BOOT_DEVICE
+#if defined(CONFIG_4xx)
+#define		CONFIG_SYS_VXWORKS_BOOT_DEVICE "emac(0,0)"
+#elif defined(CONFIG_IOP480)
+#define		CONFIG_SYS_VXWORKS_BOOT_DEVICE "dc(0,0)"
+#else
+#define		CONFIG_SYS_VXWORKS_BOOT_DEVICE "eth(0,0)"
+#endif
+#endif
+
+#ifndef CONFIG_SYS_VXWORKS_SERVERNAME
+#define CONFIG_SYS_VXWORKS_SERVERNAME	"srv"
+#endif
+
+#endif
diff --git a/include/w83c553f.h b/include/w83c553f.h
index 88ea9da..6a76f5a 100644
--- a/include/w83c553f.h
+++ b/include/w83c553f.h
@@ -73,30 +73,30 @@
 /*
  * Interrupt controller
  */
-#define W83C553F_PIC1_ICW1	CFG_ISA_IO + 0x20
-#define W83C553F_PIC1_ICW2	CFG_ISA_IO + 0x21
-#define W83C553F_PIC1_ICW3	CFG_ISA_IO + 0x21
-#define W83C553F_PIC1_ICW4	CFG_ISA_IO + 0x21
-#define W83C553F_PIC1_OCW1	CFG_ISA_IO + 0x21
-#define W83C553F_PIC1_OCW2	CFG_ISA_IO + 0x20
-#define W83C553F_PIC1_OCW3	CFG_ISA_IO + 0x20
-#define W83C553F_PIC1_ELC	CFG_ISA_IO + 0x4D0
-#define W83C553F_PIC2_ICW1	CFG_ISA_IO + 0xA0
-#define W83C553F_PIC2_ICW2	CFG_ISA_IO + 0xA1
-#define W83C553F_PIC2_ICW3	CFG_ISA_IO + 0xA1
-#define W83C553F_PIC2_ICW4	CFG_ISA_IO + 0xA1
-#define W83C553F_PIC2_OCW1	CFG_ISA_IO + 0xA1
-#define W83C553F_PIC2_OCW2	CFG_ISA_IO + 0xA0
-#define W83C553F_PIC2_OCW3	CFG_ISA_IO + 0xA0
-#define W83C553F_PIC2_ELC	CFG_ISA_IO + 0x4D1
-
-#define W83C553F_TMR1_CMOD	CFG_ISA_IO + 0x43
+#define W83C553F_PIC1_ICW1	CONFIG_SYS_ISA_IO + 0x20
+#define W83C553F_PIC1_ICW2	CONFIG_SYS_ISA_IO + 0x21
+#define W83C553F_PIC1_ICW3	CONFIG_SYS_ISA_IO + 0x21
+#define W83C553F_PIC1_ICW4	CONFIG_SYS_ISA_IO + 0x21
+#define W83C553F_PIC1_OCW1	CONFIG_SYS_ISA_IO + 0x21
+#define W83C553F_PIC1_OCW2	CONFIG_SYS_ISA_IO + 0x20
+#define W83C553F_PIC1_OCW3	CONFIG_SYS_ISA_IO + 0x20
+#define W83C553F_PIC1_ELC	CONFIG_SYS_ISA_IO + 0x4D0
+#define W83C553F_PIC2_ICW1	CONFIG_SYS_ISA_IO + 0xA0
+#define W83C553F_PIC2_ICW2	CONFIG_SYS_ISA_IO + 0xA1
+#define W83C553F_PIC2_ICW3	CONFIG_SYS_ISA_IO + 0xA1
+#define W83C553F_PIC2_ICW4	CONFIG_SYS_ISA_IO + 0xA1
+#define W83C553F_PIC2_OCW1	CONFIG_SYS_ISA_IO + 0xA1
+#define W83C553F_PIC2_OCW2	CONFIG_SYS_ISA_IO + 0xA0
+#define W83C553F_PIC2_OCW3	CONFIG_SYS_ISA_IO + 0xA0
+#define W83C553F_PIC2_ELC	CONFIG_SYS_ISA_IO + 0x4D1
+
+#define W83C553F_TMR1_CMOD	CONFIG_SYS_ISA_IO + 0x43
 
 /*
  * DMA controller
  */
-#define W83C553F_DMA1	CFG_ISA_IO + 0x000	/* channel 0 - 3 */
-#define W83C553F_DMA2	CFG_ISA_IO + 0x0C0	/* channel 4 - 7 */
+#define W83C553F_DMA1	CONFIG_SYS_ISA_IO + 0x000	/* channel 0 - 3 */
+#define W83C553F_DMA2	CONFIG_SYS_ISA_IO + 0x0C0	/* channel 4 - 7 */
 
 /* command/status register bit definitions */
 
diff --git a/include/xilinx.h b/include/xilinx.h
index ad33e1f..fdc3587 100644
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -29,25 +29,25 @@
 
 /* Xilinx Model definitions
  *********************************************************************/
-#define CFG_SPARTAN2			CFG_FPGA_DEV( 0x1 )
-#define CFG_VIRTEX_E			CFG_FPGA_DEV( 0x2 )
-#define CFG_VIRTEX2			CFG_FPGA_DEV( 0x4 )
-#define CFG_SPARTAN3			CFG_FPGA_DEV( 0x8 )
-#define CFG_XILINX_SPARTAN2	(CFG_FPGA_XILINX | CFG_SPARTAN2)
-#define CFG_XILINX_VIRTEX_E	(CFG_FPGA_XILINX | CFG_VIRTEX_E)
-#define CFG_XILINX_VIRTEX2	(CFG_FPGA_XILINX | CFG_VIRTEX2)
-#define CFG_XILINX_SPARTAN3	(CFG_FPGA_XILINX | CFG_SPARTAN3)
+#define CONFIG_SYS_SPARTAN2			CONFIG_SYS_FPGA_DEV( 0x1 )
+#define CONFIG_SYS_VIRTEX_E			CONFIG_SYS_FPGA_DEV( 0x2 )
+#define CONFIG_SYS_VIRTEX2			CONFIG_SYS_FPGA_DEV( 0x4 )
+#define CONFIG_SYS_SPARTAN3			CONFIG_SYS_FPGA_DEV( 0x8 )
+#define CONFIG_SYS_XILINX_SPARTAN2	(CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN2)
+#define CONFIG_SYS_XILINX_VIRTEX_E	(CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX_E)
+#define CONFIG_SYS_XILINX_VIRTEX2	(CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX2)
+#define CONFIG_SYS_XILINX_SPARTAN3	(CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN3)
 /* XXX - Add new models here */
 
 
 /* Xilinx Interface definitions
  *********************************************************************/
-#define CFG_XILINX_IF_SS	CFG_FPGA_IF( 0x1 )	/* slave serial		*/
-#define CFG_XILINX_IF_MS	CFG_FPGA_IF( 0x2 )	/* master serial	*/
-#define CFG_XILINX_IF_SP	CFG_FPGA_IF( 0x4 )	/* slave parallel	*/
-#define CFG_XILINX_IF_JTAG	CFG_FPGA_IF( 0x8 )	/* jtag			*/
-#define CFG_XILINX_IF_MSM	CFG_FPGA_IF( 0x10 )	/* master selectmap	*/
-#define CFG_XILINX_IF_SSM	CFG_FPGA_IF( 0x20 )	/* slave selectmap	*/
+#define CONFIG_SYS_XILINX_IF_SS	CONFIG_SYS_FPGA_IF( 0x1 )	/* slave serial		*/
+#define CONFIG_SYS_XILINX_IF_MS	CONFIG_SYS_FPGA_IF( 0x2 )	/* master serial	*/
+#define CONFIG_SYS_XILINX_IF_SP	CONFIG_SYS_FPGA_IF( 0x4 )	/* slave parallel	*/
+#define CONFIG_SYS_XILINX_IF_JTAG	CONFIG_SYS_FPGA_IF( 0x8 )	/* jtag			*/
+#define CONFIG_SYS_XILINX_IF_MSM	CONFIG_SYS_FPGA_IF( 0x10 )	/* master selectmap	*/
+#define CONFIG_SYS_XILINX_IF_SSM	CONFIG_SYS_FPGA_IF( 0x20 )	/* slave selectmap	*/
 
 /* Xilinx types
  *********************************************************************/