diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/bios_emul.h | 66 | ||||
| -rw-r--r-- | include/common.h | 3 | ||||
| -rw-r--r-- | include/configs/chromebook_link.h | 30 | ||||
| -rw-r--r-- | include/configs/dbau1x00.h | 3 | ||||
| -rw-r--r-- | include/configs/pb1x00.h | 3 | ||||
| -rw-r--r-- | include/configs/qemu-mips.h | 3 | ||||
| -rw-r--r-- | include/configs/qemu-mips64.h | 3 | ||||
| -rw-r--r-- | include/configs/uniphier-common.h | 15 | ||||
| -rw-r--r-- | include/configs/vct.h | 3 | ||||
| -rw-r--r-- | include/fdtdec.h | 3 | ||||
| -rw-r--r-- | include/linux/kernel.h | 2 | ||||
| -rw-r--r-- | include/pci.h | 23 | ||||
| -rw-r--r-- | include/pci_ids.h | 187 | ||||
| -rw-r--r-- | include/pci_rom.h | 58 | ||||
| -rw-r--r-- | include/rtc.h | 5 | ||||
| -rw-r--r-- | include/vbe.h | 103 | ||||
| -rw-r--r-- | include/video_fb.h | 2 |
17 files changed, 475 insertions, 37 deletions
diff --git a/include/bios_emul.h b/include/bios_emul.h new file mode 100644 index 0000000..3643b82 --- /dev/null +++ b/include/bios_emul.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 1996-1999 SciTech Software, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _BIOS_EMUL_H +#define _BIOS_EMUL_H + +/* Include the register header directly here */ +#include "../drivers/bios_emulator/include/x86emu/regs.h" +#include <pci.h> + +/**************************************************************************** +REMARKS: +Data structure used to describe the details for the BIOS emulator system +environment as used by the X86 emulator library. + +HEADER: +biosemu.h + +MEMBERS: +vgaInfo - VGA BIOS information structure +biosmem_base - Base of the BIOS image +biosmem_limit - Limit of the BIOS image +busmem_base - Base of the VGA bus memory +****************************************************************************/ +typedef struct { + int function; + int device; + int bus; + u32 VendorID; + u32 DeviceID; + pci_dev_t pcidev; + void *BIOSImage; + u32 BIOSImageLen; + u8 LowMem[1536]; +} BE_VGAInfo; + +struct vbe_mode_info; + +int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int cleanUp); + +/* Run a BIOS ROM natively (only supported on x86 machines) */ +void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode, + struct vbe_mode_info *mode_info); + +/** + * bios_set_interrupt_handler() - Install an interrupt handler for the BIOS + * + * This installs an interrupt handler that the BIOS will call when needed. + * + * @intnum: Interrupt number to install a handler for + * @int_handler_func: Function to call to handle interrupt + */ +void bios_set_interrupt_handler(int intnum, int (*int_handler_func)(void)); + +void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void)); + +int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo); + +int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len, + BE_VGAInfo *vga_info, int clean_up, int vesa_mode, + struct vbe_mode_info *mode_info); + +#endif diff --git a/include/common.h b/include/common.h index f1ab2cf..94c354b 100644 --- a/include/common.h +++ b/include/common.h @@ -73,6 +73,9 @@ typedef volatile unsigned char vu_char; #ifdef CONFIG_ARM #define asmlinkage /* nothing */ #endif +#ifdef CONFIG_X86 +#define asmlinkage __attribute__((regparm(0))) +#endif #ifdef CONFIG_BLACKFIN #include <asm/blackfin.h> #endif diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 8caeca6..645b31c 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -21,7 +21,6 @@ #define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 #define CONFIG_SYS_X86_START16 0xfffff800 #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_DISPLAY_CPUINFO #define CONFIG_X86_RESET_VECTOR @@ -40,20 +39,9 @@ {PCI_VENDOR_ID_INTEL, \ PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} -/* - * These common x86 features are not yet supported, but are added in - * follow-on patches in this series. Add undefs here to avoid every patch - * having to put things back into x86-common.h - */ -#undef CONFIG_VIDEO -#undef CONFIG_CFB_CONSOLE -#undef CONFIG_ICH_SPI -#undef CONFIG_SPI -#undef CONFIG_CMD_SPI -#undef CONFIG_CMD_SF -#undef CONFIG_USB_EHCI -#undef CONFIG_CMD_USB -#undef CONFIG_CMD_SCSI +#define CONFIG_X86_OPTION_ROM_FILENAME pci8086,0166.bin +#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 +#define CONFIG_VIDEO_X86 #define CONFIG_PCI_MEM_BUS 0xe0000000 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS @@ -67,6 +55,18 @@ #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS #define CONFIG_PCI_IO_SIZE 0xefff +#define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_PCI_PNP + +#define CONFIG_BIOSEMU +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO + +#define CONFIG_CROS_EC +#define CONFIG_CROS_EC_LPC +#define CONFIG_CMD_CROS_EC +#define CONFIG_ARCH_EARLY_INIT_R + #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ "stdout=vga,serial\0" \ "stderr=vga,serial\0" diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index e0bf3dc..8a7447d 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -15,6 +15,9 @@ #define CONFIG_DBAU1X00 1 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #ifdef CONFIG_DBAU1000 /* Also known as Merlot */ #define CONFIG_SOC_AU1000 1 diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 1c04a58..61e6af3 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -15,6 +15,9 @@ #define CONFIG_PB1X00 1 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #ifdef CONFIG_PB1000 #define CONFIG_SOC_AU1000 1 #else diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index 98ed8bc..1548d3e 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -13,6 +13,9 @@ #define __CONFIG_H #define CONFIG_QEMU_MIPS + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_MISC_INIT_R #define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h index e8f5a4c..61cafad 100644 --- a/include/configs/qemu-mips64.h +++ b/include/configs/qemu-mips64.h @@ -13,6 +13,9 @@ #define __CONFIG_H #define CONFIG_QEMU_MIPS + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_MISC_INIT_R #define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ diff --git a/include/configs/uniphier-common.h b/include/configs/uniphier-common.h index 7c4dba0..2140fcc 100644 --- a/include/configs/uniphier-common.h +++ b/include/configs/uniphier-common.h @@ -112,7 +112,6 @@ are defined. Select only one of them." #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_CMDLINE_EDITING /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) @@ -143,15 +142,6 @@ are defined. Select only one of them." */ #define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */ -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_PING -#define CONFIG_CMD_TIME -#define CONFIG_CMD_NAND /* NAND flash suppport */ - #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_MAX_CHIPS 2 #define CONFIG_SYS_NAND_ONFI_DETECTION @@ -167,7 +157,6 @@ are defined. Select only one of them." #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 /* USB */ -#define CONFIG_CMD_USB #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_CMD_FAT #define CONFIG_FAT_WRITE @@ -225,10 +214,6 @@ are defined. Select only one of them." "add_default_bootargs=setenv bootargs $bootargs" \ " console=ttyS0,$baudrate\0" \ -/* FIT support */ -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ - /* Open Firmware flat tree */ #define CONFIG_OF_LIBFDT diff --git a/include/configs/vct.h b/include/configs/vct.h index 217ba2f..83e4163 100644 --- a/include/configs/vct.h +++ b/include/configs/vct.h @@ -25,6 +25,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */ #define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2) diff --git a/include/fdtdec.h b/include/fdtdec.h index 911f216..d2b665c 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -120,6 +120,9 @@ enum fdt_compat_id { COMPAT_INTEL_LPC, /* Intel Low Pin Count I/F */ COMPAT_INTEL_MICROCODE, /* Intel microcode update */ COMPAT_MEMORY_SPD, /* Memory SPD information */ + COMPAT_INTEL_PANTHERPOINT_AHCI, /* Intel Pantherpoint AHCI */ + COMPAT_INTEL_MODEL_206AX, /* Intel Model 206AX CPU */ + COMPAT_INTEL_GMA, /* Intel Graphics Media Accelerator */ COMPAT_COUNT, }; diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 89fcae0..0b61671 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -16,7 +16,9 @@ #define LLONG_MAX ((long long)(~0ULL>>1)) #define LLONG_MIN (-LLONG_MAX - 1) #define ULLONG_MAX (~0ULL) +#ifndef SIZE_MAX #define SIZE_MAX (~(size_t)0) +#endif #define U8_MAX ((u8)~0U) #define S8_MAX ((s8)(U8_MAX>>1)) diff --git a/include/pci.h b/include/pci.h index d211351..216f448 100644 --- a/include/pci.h +++ b/include/pci.h @@ -678,5 +678,28 @@ extern void pci_mpc824x_init (struct pci_controller *hose); extern void pci_mpc85xx_init (struct pci_controller *hose); #endif +/** + * pci_write_bar32() - Write the address of a BAR including control bits + * + * This writes a raw address (with control bits) to a bar + * + * @hose: PCI hose to use + * @dev: PCI device to update + * @barnum: BAR number (0-5) + * @addr: BAR address with control bits + */ +void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, + u32 addr_and_ctrl); + +/** + * pci_read_bar32() - read the address of a bar + * + * @hose: PCI hose to use + * @dev: PCI device to inspect + * @barnum: BAR number (0-5) + * @return address of the bar, masking out any control bits + * */ +u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); + #endif /* __ASSEMBLY__ */ #endif /* _PCI_H */ diff --git a/include/pci_ids.h b/include/pci_ids.h index f84c13a..ee98bee 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -526,7 +526,19 @@ #define PCI_DEVICE_ID_AMD_11H_NB_DRAM 0x1302 #define PCI_DEVICE_ID_AMD_11H_NB_MISC 0x1303 #define PCI_DEVICE_ID_AMD_11H_NB_LINK 0x1304 -#define PCI_DEVICE_ID_AMD_15H_NB_MISC 0x1603 +#define PCI_DEVICE_ID_AMD_15H_M10H_F3 0x1403 +#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F3 0x141d +#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F4 0x141e +#define PCI_DEVICE_ID_AMD_15H_NB_F0 0x1600 +#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601 +#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602 +#define PCI_DEVICE_ID_AMD_15H_NB_F3 0x1603 +#define PCI_DEVICE_ID_AMD_15H_NB_F4 0x1604 +#define PCI_DEVICE_ID_AMD_15H_NB_F5 0x1605 +#define PCI_DEVICE_ID_AMD_16H_NB_F3 0x1533 +#define PCI_DEVICE_ID_AMD_16H_NB_F4 0x1534 +#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F3 0x1583 +#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F4 0x1584 #define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703 #define PCI_DEVICE_ID_AMD_LANCE 0x2000 #define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 @@ -569,8 +581,9 @@ #define PCI_DEVICE_ID_AMD_CS5536_IDE 0x209A #define PCI_DEVICE_ID_AMD_LX_VIDEO 0x2081 #define PCI_DEVICE_ID_AMD_LX_AES 0x2082 -#define PCI_DEVICE_ID_AMD_HUDSON2_IDE 0x780c #define PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE 0x7800 +#define PCI_DEVICE_ID_AMD_HUDSON2_SMBUS 0x780b +#define PCI_DEVICE_ID_AMD_HUDSON2_IDE 0x780c #define PCI_VENDOR_ID_TRIDENT 0x1023 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000 @@ -616,6 +629,8 @@ #define PCI_DEVICE_ID_MATROX_G550 0x2527 #define PCI_DEVICE_ID_MATROX_VIA 0x4536 +#define PCI_VENDOR_ID_MOBILITY_ELECTRONICS 0x14f2 + #define PCI_VENDOR_ID_CT 0x102c #define PCI_DEVICE_ID_CT_69000 0x00c0 #define PCI_DEVICE_ID_CT_65545 0x00d8 @@ -724,6 +739,7 @@ #define PCI_DEVICE_ID_SI_7018 0x7018 #define PCI_VENDOR_ID_HP 0x103c +#define PCI_VENDOR_ID_HP_3PAR 0x1590 #define PCI_DEVICE_ID_HP_VISUALIZE_EG 0x1005 #define PCI_DEVICE_ID_HP_VISUALIZE_FX6 0x1006 #define PCI_DEVICE_ID_HP_VISUALIZE_FX4 0x1008 @@ -755,6 +771,8 @@ #define PCI_DEVICE_ID_HP_CISSD 0x3238 #define PCI_DEVICE_ID_HP_CISSE 0x323a #define PCI_DEVICE_ID_HP_CISSF 0x323b +#define PCI_DEVICE_ID_HP_CISSH 0x323c +#define PCI_DEVICE_ID_HP_CISSI 0x3239 #define PCI_DEVICE_ID_HP_ZX2_IOC 0x4031 #define PCI_VENDOR_ID_PCTECH 0x1042 @@ -779,6 +797,29 @@ #define PCI_DEVICE_ID_ELSA_QS3000 0x3000 #define PCI_VENDOR_ID_STMICRO 0x104A +#define PCI_DEVICE_ID_STMICRO_USB_HOST 0xCC00 +#define PCI_DEVICE_ID_STMICRO_USB_OHCI 0xCC01 +#define PCI_DEVICE_ID_STMICRO_USB_OTG 0xCC02 +#define PCI_DEVICE_ID_STMICRO_UART_HWFC 0xCC03 +#define PCI_DEVICE_ID_STMICRO_UART_NO_HWFC 0xCC04 +#define PCI_DEVICE_ID_STMICRO_SOC_DMA 0xCC05 +#define PCI_DEVICE_ID_STMICRO_SATA 0xCC06 +#define PCI_DEVICE_ID_STMICRO_I2C 0xCC07 +#define PCI_DEVICE_ID_STMICRO_SPI_HS 0xCC08 +#define PCI_DEVICE_ID_STMICRO_MAC 0xCC09 +#define PCI_DEVICE_ID_STMICRO_SDIO_EMMC 0xCC0A +#define PCI_DEVICE_ID_STMICRO_SDIO 0xCC0B +#define PCI_DEVICE_ID_STMICRO_GPIO 0xCC0C +#define PCI_DEVICE_ID_STMICRO_VIP 0xCC0D +#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_DMA 0xCC0E +#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_SRCS 0xCC0F +#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_MSPS 0xCC10 +#define PCI_DEVICE_ID_STMICRO_CAN 0xCC11 +#define PCI_DEVICE_ID_STMICRO_MLB 0xCC12 +#define PCI_DEVICE_ID_STMICRO_DBP 0xCC13 +#define PCI_DEVICE_ID_STMICRO_SATA_PHY 0xCC14 +#define PCI_DEVICE_ID_STMICRO_ESRAM 0xCC15 +#define PCI_DEVICE_ID_STMICRO_VIC 0xCC16 #define PCI_VENDOR_ID_BUSLOGIC 0x104B #define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 @@ -1294,6 +1335,8 @@ #define PCI_VENDOR_ID_TUNDRA 0x10e3 #define PCI_DEVICE_ID_TUNDRA_CA91C042 0x0000 +#define PCI_VENDOR_ID_AMCC 0x10e8 + #define PCI_VENDOR_ID_INTERG 0x10ea #define PCI_DEVICE_ID_INTERG_1682 0x1682 #define PCI_DEVICE_ID_INTERG_2000 0x2000 @@ -1322,6 +1365,7 @@ #define PCI_SUBDEVICE_ID_CREATIVE_SB08801 0x0041 #define PCI_SUBDEVICE_ID_CREATIVE_SB08802 0x0042 #define PCI_SUBDEVICE_ID_CREATIVE_SB08803 0x0043 +#define PCI_SUBDEVICE_ID_CREATIVE_SB1270 0x0062 #define PCI_SUBDEVICE_ID_CREATIVE_HENDRIX 0x6000 #define PCI_VENDOR_ID_ECTIVA 0x1102 /* duplicate: CREATIVE */ @@ -1411,6 +1455,7 @@ #define PCI_DEVICE_ID_VIA_CX700_IDE 0x0581 #define PCI_DEVICE_ID_VIA_VX800 0x8353 #define PCI_DEVICE_ID_VIA_VX855 0x8409 +#define PCI_DEVICE_ID_VIA_VX900 0x8410 #define PCI_DEVICE_ID_VIA_8371_1 0x8391 #define PCI_DEVICE_ID_VIA_82C598_1 0x8598 #define PCI_DEVICE_ID_VIA_838X_1 0xB188 @@ -1551,6 +1596,8 @@ #define PCI_DEVICE_ID_RICOH_RL5C476 0x0476 #define PCI_DEVICE_ID_RICOH_RL5C478 0x0478 #define PCI_DEVICE_ID_RICOH_R5C822 0x0822 +#define PCI_DEVICE_ID_RICOH_R5CE822 0xe822 +#define PCI_DEVICE_ID_RICOH_R5CE823 0xe823 #define PCI_DEVICE_ID_RICOH_R5C832 0x0832 #define PCI_DEVICE_ID_RICOH_R5C843 0x0843 @@ -1586,6 +1633,7 @@ #define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334 #define PCI_VENDOR_ID_MARVELL 0x11ab +#define PCI_VENDOR_ID_MARVELL_EXT 0x1b4b #define PCI_DEVICE_ID_MARVELL_GT64111 0x4146 #define PCI_DEVICE_ID_MARVELL_GT64260 0x6430 #define PCI_DEVICE_ID_MARVELL_MV64360 0x6460 @@ -1798,6 +1846,8 @@ #define PCI_VENDOR_ID_ESDGMBH 0x12fe #define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111 +#define PCI_VENDOR_ID_CB 0x1307 /* Measurement Computing */ + #define PCI_VENDOR_ID_SIIG 0x131f #define PCI_SUBVENDOR_ID_SIIG 0x131f #define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000 @@ -1860,8 +1910,23 @@ #define PCI_VENDOR_ID_QUATECH 0x135C #define PCI_DEVICE_ID_QUATECH_QSC100 0x0010 #define PCI_DEVICE_ID_QUATECH_DSC100 0x0020 +#define PCI_DEVICE_ID_QUATECH_DSC200 0x0030 +#define PCI_DEVICE_ID_QUATECH_QSC200 0x0040 #define PCI_DEVICE_ID_QUATECH_ESC100D 0x0050 #define PCI_DEVICE_ID_QUATECH_ESC100M 0x0060 +#define PCI_DEVICE_ID_QUATECH_QSCP100 0x0120 +#define PCI_DEVICE_ID_QUATECH_DSCP100 0x0130 +#define PCI_DEVICE_ID_QUATECH_QSCP200 0x0140 +#define PCI_DEVICE_ID_QUATECH_DSCP200 0x0150 +#define PCI_DEVICE_ID_QUATECH_QSCLP100 0x0170 +#define PCI_DEVICE_ID_QUATECH_DSCLP100 0x0180 +#define PCI_DEVICE_ID_QUATECH_DSC100E 0x0181 +#define PCI_DEVICE_ID_QUATECH_SSCLP100 0x0190 +#define PCI_DEVICE_ID_QUATECH_QSCLP200 0x01A0 +#define PCI_DEVICE_ID_QUATECH_DSCLP200 0x01B0 +#define PCI_DEVICE_ID_QUATECH_DSC200E 0x01B1 +#define PCI_DEVICE_ID_QUATECH_SSCLP200 0x01C0 +#define PCI_DEVICE_ID_QUATECH_ESCLP100 0x01E0 #define PCI_DEVICE_ID_QUATECH_SPPXP_100 0x0278 #define PCI_VENDOR_ID_SEALEVEL 0x135e @@ -1978,6 +2043,9 @@ #define PCI_DEVICE_ID_EXAR_XR17C152 0x0152 #define PCI_DEVICE_ID_EXAR_XR17C154 0x0154 #define PCI_DEVICE_ID_EXAR_XR17C158 0x0158 +#define PCI_DEVICE_ID_EXAR_XR17V352 0x0352 +#define PCI_DEVICE_ID_EXAR_XR17V354 0x0354 +#define PCI_DEVICE_ID_EXAR_XR17V358 0x0358 #define PCI_VENDOR_ID_MICROGATE 0x13c0 #define PCI_DEVICE_ID_MICROGATE_USC 0x0010 @@ -2002,6 +2070,10 @@ #define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111 #define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112 +#define PCI_VENDOR_ID_ADVANTECH 0x13fe + +#define PCI_VENDOR_ID_MEILHAUS 0x1402 + #define PCI_VENDOR_ID_LAVA 0x1407 #define PCI_DEVICE_ID_LAVA_DSERIAL 0x0100 /* 2x 16550 */ #define PCI_DEVICE_ID_LAVA_QUATRO_A 0x0101 /* 2x 16550, half of 4 port */ @@ -2047,6 +2119,8 @@ #define PCI_VENDOR_ID_CHELSIO 0x1425 +#define PCI_VENDOR_ID_ADLINK 0x144a + #define PCI_VENDOR_ID_SAMSUNG 0x144d #define PCI_VENDOR_ID_GIGABYTE 0x1458 @@ -2080,6 +2154,8 @@ #define PCI_DEVICE_ID_AFAVLAB_P030 0x2182 #define PCI_SUBDEVICE_ID_AFAVLAB_P061 0x2150 +#define PCI_VENDOR_ID_AMPLICON 0x14dc + #define PCI_VENDOR_ID_BCM_GVC 0x14a4 #define PCI_VENDOR_ID_BROADCOM 0x14e4 #define PCI_DEVICE_ID_TIGON3_5752 0x1600 @@ -2100,19 +2176,25 @@ #define PCI_DEVICE_ID_NX2_57711E 0x1650 #define PCI_DEVICE_ID_TIGON3_5705 0x1653 #define PCI_DEVICE_ID_TIGON3_5705_2 0x1654 +#define PCI_DEVICE_ID_TIGON3_5719 0x1657 #define PCI_DEVICE_ID_TIGON3_5721 0x1659 #define PCI_DEVICE_ID_TIGON3_5722 0x165a #define PCI_DEVICE_ID_TIGON3_5723 0x165b #define PCI_DEVICE_ID_TIGON3_5705M 0x165d #define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e +#define PCI_DEVICE_ID_NX2_57712 0x1662 +#define PCI_DEVICE_ID_NX2_57712E 0x1663 +#define PCI_DEVICE_ID_NX2_57712_MF 0x1663 #define PCI_DEVICE_ID_TIGON3_5714 0x1668 #define PCI_DEVICE_ID_TIGON3_5714S 0x1669 #define PCI_DEVICE_ID_TIGON3_5780 0x166a #define PCI_DEVICE_ID_TIGON3_5780S 0x166b #define PCI_DEVICE_ID_TIGON3_5705F 0x166e +#define PCI_DEVICE_ID_NX2_57712_VF 0x166f #define PCI_DEVICE_ID_TIGON3_5754M 0x1672 #define PCI_DEVICE_ID_TIGON3_5755M 0x1673 #define PCI_DEVICE_ID_TIGON3_5756 0x1674 +#define PCI_DEVICE_ID_TIGON3_5750 0x1676 #define PCI_DEVICE_ID_TIGON3_5751 0x1677 #define PCI_DEVICE_ID_TIGON3_5715 0x1678 #define PCI_DEVICE_ID_TIGON3_5715S 0x1679 @@ -2124,6 +2206,9 @@ #define PCI_DEVICE_ID_TIGON3_5761E 0x1680 #define PCI_DEVICE_ID_TIGON3_5761 0x1681 #define PCI_DEVICE_ID_TIGON3_5764 0x1684 +#define PCI_DEVICE_ID_NX2_57800 0x168a +#define PCI_DEVICE_ID_NX2_57840 0x168d +#define PCI_DEVICE_ID_NX2_57810 0x168e #define PCI_DEVICE_ID_TIGON3_5787M 0x1693 #define PCI_DEVICE_ID_TIGON3_5782 0x1696 #define PCI_DEVICE_ID_TIGON3_5784 0x1698 @@ -2131,11 +2216,19 @@ #define PCI_DEVICE_ID_TIGON3_5787 0x169b #define PCI_DEVICE_ID_TIGON3_5788 0x169c #define PCI_DEVICE_ID_TIGON3_5789 0x169d +#define PCI_DEVICE_ID_NX2_57840_4_10 0x16a1 +#define PCI_DEVICE_ID_NX2_57840_2_20 0x16a2 +#define PCI_DEVICE_ID_NX2_57840_MF 0x16a4 +#define PCI_DEVICE_ID_NX2_57800_MF 0x16a5 #define PCI_DEVICE_ID_TIGON3_5702X 0x16a6 #define PCI_DEVICE_ID_TIGON3_5703X 0x16a7 #define PCI_DEVICE_ID_TIGON3_5704S 0x16a8 +#define PCI_DEVICE_ID_NX2_57800_VF 0x16a9 #define PCI_DEVICE_ID_NX2_5706S 0x16aa #define PCI_DEVICE_ID_NX2_5708S 0x16ac +#define PCI_DEVICE_ID_NX2_57840_VF 0x16ad +#define PCI_DEVICE_ID_NX2_57810_MF 0x16ae +#define PCI_DEVICE_ID_NX2_57810_VF 0x16af #define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6 #define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7 #define PCI_DEVICE_ID_TIGON3_5781 0x16dd @@ -2307,6 +2400,8 @@ #define PCI_VENDOR_ID_TOPSPIN 0x1867 +#define PCI_VENDOR_ID_COMMTECH 0x18f7 + #define PCI_VENDOR_ID_SILAN 0x1904 #define PCI_VENDOR_ID_RENESAS 0x1912 @@ -2316,6 +2411,11 @@ #define PCI_DEVICE_ID_RENESAS_SH7785 0x0007 #define PCI_DEVICE_ID_RENESAS_SH7786 0x0010 +#define PCI_VENDOR_ID_SOLARFLARE 0x1924 +#define PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0 0x0703 +#define PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1 0x6703 +#define PCI_DEVICE_ID_SOLARFLARE_SFC4000B 0x0710 + #define PCI_VENDOR_ID_TDI 0x192E #define PCI_DEVICE_ID_TDI_EHCI 0x0101 @@ -2414,6 +2514,11 @@ #define PCI_VENDOR_ID_AZWAVE 0x1a3b +#define PCI_VENDOR_ID_ASMEDIA 0x1b21 + +#define PCI_VENDOR_ID_CIRCUITCO 0x1cc8 +#define PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD 0x0001 + #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 @@ -2463,6 +2568,9 @@ #define PCI_VENDOR_ID_INTEL 0x8086 #define PCI_DEVICE_ID_INTEL_EESSC 0x0008 +#define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100 +#define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154 +#define PCI_DEVICE_ID_INTEL_HSW_IMC 0x0c00 #define PCI_DEVICE_ID_INTEL_PXHD_0 0x0320 #define PCI_DEVICE_ID_INTEL_PXHD_1 0x0321 #define PCI_DEVICE_ID_INTEL_PXH_0 0x0329 @@ -2485,6 +2593,7 @@ #define PCI_DEVICE_ID_INTEL_MRST_SD2 0x084F #define PCI_DEVICE_ID_INTEL_I960 0x0960 #define PCI_DEVICE_ID_INTEL_I960RM 0x0962 +#define PCI_DEVICE_ID_INTEL_CENTERTON_ILB 0x0c60 #define PCI_DEVICE_ID_INTEL_82541ER 0x1078 #define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c #define PCI_DEVICE_ID_INTEL_82542 0x1000 @@ -2564,13 +2673,50 @@ #define PCI_DEVICE_ID_INTEL_COUGARPOINT_HDA 0x1c20 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Z68 0x1c44 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_P67 0x1c46 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_UM67 0x1c47 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM65 0x1c49 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_H67 0x1c4a +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM67 0x1c4b +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Q65 0x1c4c +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_QS67 0x1c4d +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Q67 0x1c4e +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_QM67 0x1c4f +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_B65 0x1c50 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C202 0x1c52 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C204 0x1c54 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C206 0x1c56 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_H61 0x1c5c #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f -#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE 0x1e03 -#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_HDA 0x1e20 -#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41 -#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 #define PCI_DEVICE_ID_INTEL_PATSBURG_LPC 0x1d40 +#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0 0x1d40 +#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1 0x1d41 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE 0x1e03 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_HDA 0x1e20 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI 0x1e31 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_B75 0x1e49 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_C216 0x1e53 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_H77 0x1e4A +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM70 0x1e5e +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM75 0x1e5d +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM76 0x1e59 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM77 0x1e57 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MBL_SAMPLE 0x1e42 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_NM70 0x1e5f +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Q75 0x1e48 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Q77 0x1e47 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_QM77 0x1e55 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_QS77 0x1e56 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_SFF_SAMPLE 0x1e43 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_UM77 0x1e58 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Z75 0x1e46 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Z77 0x1e44 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f +#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN 0x2310 +#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX 0x231f #define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410 #define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411 #define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413 @@ -2783,8 +2929,30 @@ #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN 0x3b00 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX 0x3b1f #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB0 0x3c20 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB1 0x3c21 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB2 0x3c22 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB3 0x3c23 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB4 0x3c24 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB5 0x3c25 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB6 0x3c26 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB7 0x3c27 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB8 0x3c2e +#define PCI_DEVICE_ID_INTEL_IOAT_SNB9 0x3c2f +#define PCI_DEVICE_ID_INTEL_UNC_HA 0x3c46 +#define PCI_DEVICE_ID_INTEL_UNC_IMC0 0x3cb0 +#define PCI_DEVICE_ID_INTEL_UNC_IMC1 0x3cb1 +#define PCI_DEVICE_ID_INTEL_UNC_IMC2 0x3cb4 +#define PCI_DEVICE_ID_INTEL_UNC_IMC3 0x3cb5 +#define PCI_DEVICE_ID_INTEL_UNC_QPI0 0x3c41 +#define PCI_DEVICE_ID_INTEL_UNC_QPI1 0x3c42 +#define PCI_DEVICE_ID_INTEL_UNC_R2PCIE 0x3c43 +#define PCI_DEVICE_ID_INTEL_UNC_R3QPI0 0x3c44 +#define PCI_DEVICE_ID_INTEL_UNC_R3QPI1 0x3c45 +#define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX 0x3ce0 #define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f #define PCI_DEVICE_ID_INTEL_5100_16 0x65f0 +#define PCI_DEVICE_ID_INTEL_5100_19 0x65f3 #define PCI_DEVICE_ID_INTEL_5100_21 0x65f5 #define PCI_DEVICE_ID_INTEL_5100_22 0x65f6 #define PCI_DEVICE_ID_INTEL_5400_ERR 0x4030 @@ -2823,6 +2991,7 @@ #define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601 #define PCI_DEVICE_ID_INTEL_SCH_LPC 0x8119 #define PCI_DEVICE_ID_INTEL_SCH_IDE 0x811a +#define PCI_DEVICE_ID_INTEL_ITC_LPC 0x8186 #define PCI_DEVICE_ID_INTEL_82454GX 0x84c4 #define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 #define PCI_DEVICE_ID_INTEL_82451NX 0x84ca @@ -2905,7 +3074,11 @@ #define PCI_DEVICE_ID_NETMOS_9845 0x9845 #define PCI_DEVICE_ID_NETMOS_9855 0x9855 #define PCI_DEVICE_ID_NETMOS_9865 0x9865 +#define PCI_DEVICE_ID_NETMOS_9900 0x9900 #define PCI_DEVICE_ID_NETMOS_9901 0x9901 +#define PCI_DEVICE_ID_NETMOS_9904 0x9904 +#define PCI_DEVICE_ID_NETMOS_9912 0x9912 +#define PCI_DEVICE_ID_NETMOS_9922 0x9922 #define PCI_VENDOR_ID_3COM_2 0xa727 @@ -2927,3 +3100,5 @@ #define PCI_VENDOR_ID_XEN 0x5853 #define PCI_DEVICE_ID_XEN_PLATFORM 0x0001 + +#define PCI_VENDOR_ID_OCZ 0x1b85 diff --git a/include/pci_rom.h b/include/pci_rom.h new file mode 100644 index 0000000..8b2674c --- /dev/null +++ b/include/pci_rom.h @@ -0,0 +1,58 @@ +/* + * From coreboot file of same name + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PCI_ROM_H +#define _PCI_ROM_H + +#define PCI_ROM_HDR 0xaa55 +#define PCI_VGA_RAM_IMAGE_START 0xc0000 + +struct pci_rom_header { + uint16_t signature; + uint8_t size; + uint8_t init[3]; + uint8_t reserved[0x12]; + uint16_t data; +}; + +struct pci_rom_data { + uint32_t signature; + uint16_t vendor; + uint16_t device; + uint16_t reserved_1; + uint16_t dlen; + uint8_t drevision; + uint8_t class_lo; + uint16_t class_hi; + uint16_t ilen; + uint16_t irevision; + uint8_t type; + uint8_t indicator; + uint16_t reserved_2; +}; + + /** + * pci_run_vga_bios() - Run the VGA BIOS in an x86 PC + * + * @dev: Video device containing the BIOS + * @int15_handler: Function to call to handle int 0x15 + * @emulate: true to use the x86 emulator, false to run native + */ +int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate); + +/** + * board_map_oprom_vendev() - map several PCI IDs to the one the ROM expects + * + * Some VGA option roms are used for several chipsets but they only have one + * PCI ID in their header. If we encounter such an option rom, we need to do + * the mapping ourselves. + * + * @vendev: Vendor and device for the video device + * @return standard vendor and device expected by the ROM + */ +uint32_t board_map_oprom_vendev(uint32_t vendev); + +#endif diff --git a/include/rtc.h b/include/rtc.h index c034966..d11aa8b 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -50,4 +50,9 @@ void to_tm (int, struct rtc_time *); unsigned long mktime (unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); +/** + * rtc_init() - Set up the real time clock ready for use + */ +void rtc_init(void); + #endif /* _RTC_H_ */ diff --git a/include/vbe.h b/include/vbe.h new file mode 100644 index 0000000..d405691 --- /dev/null +++ b/include/vbe.h @@ -0,0 +1,103 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * Copyright (c) 2009 Pattrick Hueper <phueper@hueper.net> + * All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ +#ifndef _VBE_H +#define _VBE_H + +/* these structs are for input from and output to OF */ +struct __packed screen_info { + u8 display_type; /* 0=NONE, 1= analog, 2=digital */ + u16 screen_width; + u16 screen_height; + /* bytes per line in framebuffer, may be more than screen_width */ + u16 screen_linebytes; + u8 color_depth; /* color depth in bits per pixel */ + u32 framebuffer_address; + u8 edid_block_zero[128]; +}; + +struct __packed screen_info_input { + u8 signature[4]; + u16 size_reserved; + u8 monitor_number; + u16 max_screen_width; + u8 color_depth; +}; + +/* these structs only store the required a subset of the VBE-defined fields */ +struct __packed vbe_info { + char signature[4]; + u16 version; + u8 *oem_string_ptr; + u32 capabilities; + u16 video_mode_list[256]; + u16 total_memory; +}; + +struct __packed vesa_mode_info { + u16 mode_attributes; /* 00 */ + u8 win_a_attributes; /* 02 */ + u8 win_b_attributes; /* 03 */ + u16 win_granularity; /* 04 */ + u16 win_size; /* 06 */ + u16 win_a_segment; /* 08 */ + u16 win_b_segment; /* 0a */ + u32 win_func_ptr; /* 0c */ + u16 bytes_per_scanline; /* 10 */ + u16 x_resolution; /* 12 */ + u16 y_resolution; /* 14 */ + u8 x_charsize; /* 16 */ + u8 y_charsize; /* 17 */ + u8 number_of_planes; /* 18 */ + u8 bits_per_pixel; /* 19 */ + u8 number_of_banks; /* 20 */ + u8 memory_model; /* 21 */ + u8 bank_size; /* 22 */ + u8 number_of_image_pages; /* 23 */ + u8 reserved_page; + u8 red_mask_size; + u8 red_mask_pos; + u8 green_mask_size; + u8 green_mask_pos; + u8 blue_mask_size; + u8 blue_mask_pos; + u8 reserved_mask_size; + u8 reserved_mask_pos; + u8 direct_color_mode_info; + u32 phys_base_ptr; + u32 offscreen_mem_offset; + u16 offscreen_mem_size; + u8 reserved[206]; +}; + +struct vbe_mode_info { + u16 video_mode; + bool valid; + union { + struct vesa_mode_info vesa; + u8 mode_info_block[256]; + }; +}; + +struct vbe_ddc_info { + u8 port_number; /* i.e. monitor number */ + u8 edid_transfer_time; + u8 ddc_level; + u8 edid_block_zero[128]; +}; + +#define VESA_GET_INFO 0x4f00 +#define VESA_GET_MODE_INFO 0x4f01 +#define VESA_SET_MODE 0x4f02 + +struct graphic_device; +int vbe_get_video_info(struct graphic_device *gdev); + +#endif diff --git a/include/video_fb.h b/include/video_fb.h index 6cd4e37..55ec24d 100644 --- a/include/video_fb.h +++ b/include/video_fb.h @@ -40,7 +40,7 @@ /* Export Graphic Driver Control */ /******************************************************************************/ -typedef struct { +typedef struct graphic_device { unsigned int isaBase; unsigned int pciBase; unsigned int dprBase; |