diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/Alaska8220.h | 46 | ||||
| -rw-r--r-- | include/configs/sorcery.h | 86 | ||||
| -rw-r--r-- | include/mpc8220.h | 177 |
3 files changed, 252 insertions, 57 deletions
diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h index 49c7820..dc01f0c 100644 --- a/include/configs/Alaska8220.h +++ b/include/configs/Alaska8220.h @@ -48,38 +48,45 @@ /* * Serial console configuration */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC */ + +/* Define this for PSC console +#define CONFIG_PSC_CONSOLE 1 +*/ + #define CONFIG_EXTUART_CONSOLE 1 #ifdef CONFIG_EXTUART_CONSOLE +# define CONFIG_CONS_INDEX 1 +# define CFG_NS16550_SERIAL # define CFG_NS16550 # define CFG_NS16550_REG_SIZE 1 # define CFG_NS16550_COM1 (CFG_CPLD_BASE + 0x1008) +# define CFG_NS16550_CLK 18432000 #endif #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ /* * Supported commands */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BOOTD | \ - CFG_CMD_CACHE | \ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BOOTD | \ + CFG_CMD_CACHE | \ CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_NET | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_NET | \ CFG_CMD_NFS | \ - CFG_CMD_PING | \ CFG_CMD_PCI | \ + CFG_CMD_PING | \ CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ + CFG_CMD_SDRAM | \ CFG_CMD_SNTP ) #define CONFIG_NET_MULTI @@ -260,10 +267,17 @@ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* SDRAM configuration */ -#define CFG_SDRAM_TOTAL_BANKS 2 -#define CFG_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */ -#define CFG_SDRAM_SPD_SIZE 0x40 -#define CFG_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */ +#define CFG_SDRAM_TOTAL_BANKS 2 +#define CFG_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */ +#define CFG_SDRAM_SPD_SIZE 0x40 +#define CFG_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */ + +/* SDRAM drive strength register */ +#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \ + (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \ + (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \ + (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \ + (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT)) /* * Ethernet configuration diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h index dcb4092..3d907f8 100644 --- a/include/configs/sorcery.h +++ b/include/configs/sorcery.h @@ -53,6 +53,22 @@ #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +/* PCI */ +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 + +#define CONFIG_PCI_MEM_BUS 0x80000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x71000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CONFIG_PCI_CFG_BUS 0x70000000 +#define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS +#define CONFIG_PCI_CFG_SIZE 0x01000000 + /* * Supported commands */ @@ -65,6 +81,7 @@ CFG_CMD_I2C | \ CFG_CMD_NET | \ CFG_CMD_NFS | \ + CFG_CMD_PCI | \ CFG_CMD_PING | \ CFG_CMD_REGINFO | \ CFG_CMD_SDRAM | \ @@ -72,7 +89,6 @@ 0) /* CFG_CMD_MII | \ */ -/* CFG_CMD_PCI | \ */ /* CFG_CMD_USB | \ */ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ @@ -113,6 +129,7 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ #define CONFIG_NET_MULTI +#define CONFIG_EEPRO100 /* * I2C configuration @@ -138,49 +155,38 @@ /* Flash */ #define CFG_CS0_BASE 0xf800 #define CFG_CS0_MASK 0x08000000 /* 128 MB (two chips) */ - -/* Workaround of hang-up after setting ctrl register for flash - After reset this register has value 0x003ffd80, which differs - from suggested only by the number of wait states. -#define CFG_CS0_CTRL 0x003f1580 -*/ +#define CFG_CS0_CTRL 0x001019c0 /* NVM */ -#define CFG_CS1_BASE 0xf100 -#define CFG_CS1_MASK 0x00080000 /* 512K */ -#define CFG_CS1_CTRL 0x003ffd40 /* 8bit port size? */ +#define CFG_CS1_BASE 0xf7e8 +#define CFG_CS1_MASK 0x00040000 /* 256K */ +#define CFG_CS1_CTRL 0x00101940 /* 8bit port size */ /* Atlas2 + Gemini */ -/* This CS# is mandatory? */ -#define CFG_CS2_BASE 0xf10A -#define CFG_CS2_MASK 0x00020000 /* 2x64K*/ -#define CFG_CS2_CTRL 0x003ffd00 /* 32bit port size? */ +#define CFG_CS2_BASE 0xf7e7 +#define CFG_CS2_MASK 0x00010000 /* 64K*/ +#define CFG_CS2_CTRL 0x001011c0 /* 16bit port size */ /* CAN Controller */ -/* This CS# is mandatory? */ -#define CFG_CS3_BASE 0xf10C +#define CFG_CS3_BASE 0xf7e6 #define CFG_CS3_MASK 0x00010000 /* 64K */ -#define CFG_CS3_CTRL 0x003ffd40 /* 8Bit port size */ +#define CFG_CS3_CTRL 0x00102140 /* 8Bit port size */ /* Foreign interface */ -#define CFG_CS4_BASE 0xF10D +#define CFG_CS4_BASE 0xf7e5 #define CFG_CS4_MASK 0x00010000 /* 64K */ -#define CFG_CS4_CTRL 0x003ffd80 /* 16bit port size */ +#define CFG_CS4_CTRL 0x00101dc0 /* 16bit port size */ -/* CPLD? */ -/* This CS# is mandatory? */ -#define CFG_CS5_BASE 0xF108 -#define CFG_CS5_MASK 0x00010000 -#define CFG_CS5_CTRL 0x003ffd80 /* 16bit port size */ +/* CPLD */ +#define CFG_CS5_BASE 0xf7e4 +#define CFG_CS5_MASK 0x00010000 /* 64K */ +#define CFG_CS5_CTRL 0x001000c0 /* 16bit port size */ #define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) -#define CFG_FLASH_BASE CFG_FLASH0_BASE +#define CFG_FLASH_BASE (CFG_FLASH0_BASE) -#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks (actually 4? (at least 2)) */ -#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip (actually 256) */ - - -#define PHYS_AMD_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */ +#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI @@ -191,9 +197,11 @@ * Environment settings */ #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_FLASH0_BASE) -#define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE -#define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x8000000 - 0x40000) +#define CFG_ENV_SIZE 0x4000 /* 16K */ +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + 0x20000) +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE #define CONFIG_ENV_OVERWRITE 1 @@ -240,6 +248,13 @@ #define CFG_SDRAM_SPD_SIZE 0x100 #define CFG_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */ +/* SDRAM drive strength register (for SSTL_2 class II)*/ +#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \ + (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \ + (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \ + (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \ + (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT)) + /* * Ethernet configuration */ @@ -274,4 +289,9 @@ #define CFG_HID0_INIT 0 #define CFG_HID0_FINAL 0 +/* +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +*/ + #endif /* __CONFIG_H */ diff --git a/include/mpc8220.h b/include/mpc8220.h index d8d8bd3..ff7acc6 100644 --- a/include/mpc8220.h +++ b/include/mpc8220.h @@ -259,10 +259,12 @@ #define PSC_TFLWFPTR(x) (x&0x1ff) /* last write frame pointer */ /* PCI configuration (only for PLL determination)*/ -#define PCI_REG_PCIGSCR (MMAP_XCPCI + 0x60) /* Global status/control register */ +#define PCI_REG_PCIGSCR (MMAP_XCPCI + 0x60) /* Global status/control register */ #define PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK 0x07000000 #define PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT 24 +#define PCI_REG_PCICAR (MMAP_XCPCI + 0xF8) /* Configuration Address Register */ + /* ------------------------------------------------------------------------ */ /* * Macro for General Purpose Timer @@ -300,18 +302,21 @@ */ #define CFG_FEC1_PORT0_CONFIG 0x00000000 #define CFG_FEC1_PORT1_CONFIG 0x00000000 -#define CFG_1284_PORT0_CONFIG 0x55555557 -#define CFG_1284_PORT1_CONFIG 0x80000000 +#define CFG_1284_PORT0_CONFIG 0x00000000 +#define CFG_1284_PORT1_CONFIG 0x00000000 #define CFG_FEC2_PORT2_CONFIG 0x00000000 -#define CFG_PEV_PORT2_CONFIG 0x55555540 -#define CFG_GP0_PORT0_CONFIG 0xaaaaaaa0 -#define CFG_GP1_PORT2_CONFIG 0xaaaaa000 -#define CFG_PSC_PORT3_CONFIG 0x00000000 +#define CFG_PEV_PORT2_CONFIG 0x00000000 +#define CFG_GP0_PORT0_CONFIG 0x00000000 +#define CFG_GP1_PORT2_CONFIG 0xaaaaaac0 +#define CFG_PSC_PORT3_CONFIG 0x00020000 +#define CFG_CS1_PORT3_CONFIG 0x00000000 #define CFG_CS2_PORT3_CONFIG 0x10000000 #define CFG_CS3_PORT3_CONFIG 0x40000000 #define CFG_CS4_PORT3_CONFIG 0x00000400 #define CFG_CS5_PORT3_CONFIG 0x00000200 -#define CFG_I2C_PORT3_CONFIG 0x003c0000 +#define CFG_PCI_PORT3_CONFIG 0x01400180 +#define CFG_I2C_PORT3_CONFIG 0x00000000 +#define CFG_GP2_PORT3_CONFIG 0x000200a0 /* ------------------------------------------------------------------------ */ /* @@ -527,6 +532,162 @@ struct mpc8220_dma { u32 EU37; /* DMA + 0xfc */ }; +/* + * PCI Header Registers + */ +typedef struct mpc8220_xcpci { + u32 dev_ven_id; /* 0xb00 - device/vendor ID */ + u32 stat_cmd_reg; /* 0xb04 - status command register */ + u32 class_code_rev_id; /* 0xb08 - class code / revision ID */ + u32 bist_htyp_lat_cshl; /* 0xb0c - BIST/HeaderType/Latency/cache line */ + u32 base0; /* 0xb10 - base address 0 */ + u32 base1; /* 0xb14 - base address 1 */ + u32 reserved1[4]; /* 0xb18->0xd27 - base address 2 - 5 */ + u32 cis; /* 0xb28 - cardBus CIS pointer */ + u32 sub_sys_ven_id; /* 0xb2c - sub system ID/ subsystem vendor ID */ + u32 reserved2; /* 0xb30 - expansion ROM base address */ + u32 reserved3; /* 0xb00 - reserved */ + u32 reserved4; /* 0xb00 - reserved */ + u32 mlat_mgnt_ipl; /* 0xb3c - MaxLat/MinGnt/ int pin/int line */ + u32 reserved5[8]; + /* MPC8220 specific - not accessible in PCI header space externally */ + u32 glb_stat_ctl; /* 0xb60 - Global Status Control */ + u32 target_bar0; /* 0xb64 - Target Base Address 0 */ + u32 target_bar1; /* 0xb68 - Target Base Address 1 */ + u32 target_ctrl; /* 0xb6c - Target Control */ + u32 init_win0; /* 0xb70 - Initiator Window 0 Base/Translation */ + u32 init_win1; /* 0xb74 - Initiator Window 1 Base/Translation */ + u32 init_win2; /* 0xb78 - Initiator Window 2 Base/Translation */ + u32 reserved6; /* 0xb7c - reserved */ + u32 init_win_cfg; /* 0xb80 */ + u32 init_ctrl; /* 0xb84 */ + u32 init_stat; /* 0xb88 */ + u32 reserved7[27]; + u32 cfg_adr; /* 0xbf8 */ + u32 reserved8; +} mpc8220_xcpci_t; + +/* PCI->XLB space translation (MPC8220 target), reg0 can address max 256MB, + reg1 - 1GB */ +#define PCI_BASE_ADDR_REG0 0x40000000 +#define PCI_BASE_ADDR_REG1 (CFG_SDRAM_BASE) +#define PCI_TARGET_BASE_ADDR_REG0 (CFG_MBAR) +#define PCI_TARGET_BASE_ADDR_REG1 (CFG_SDRAM_BASE) +#define PCI_TARGET_BASE_ADDR_EN 1<<0 + + +/* PCI Global Status/Control Register (PCIGSCR) */ +#define PCI_GLB_STAT_CTRL_PE_SHIFT 29 +#define PCI_GLB_STAT_CTRL_SE_SHIFT 28 +#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_SHIFT 24 +#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_MASK 0x7 +#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_SHIFT 16 +#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_MASK 0x7 +#define PCI_GLB_STAT_CTRL_PEE_SHIFT 13 +#define PCI_GLB_STAT_CTRL_SEE_SHIFT 12 +#define PCI_GLB_STAT_CTRL_PR_SHIFT 0 + +#define PCI_GLB_STAT_CTRL_PE (1<<PCI_GLB_STAT_CTRL_PE_SHIFT) +#define PCI_GLB_STAT_CTRL_SE (1<<PCI_GLB_STAT_CTRL_SE_SHIFT) +#define PCI_GLB_STAT_CTRL_PEE (1<<PCI_GLB_STAT_CTRL_PEE_SHIFT) +#define PCI_GLB_STAT_CTRL_SEE (1<<PCI_GLB_STAT_CTRL_SEE_SHIFT) +#define PCI_GLB_STAT_CTRL_PR (1<<PCI_GLB_STAT_CTRL_PR_SHIFT) + +/* PCI Target Control Register (PCITCR) */ +#define PCI_TARGET_CTRL_LD_SHIFT 24 +#define PCI_TARGET_CTRL_P_SHIFT 16 + +#define PCI_TARGET_CTRL_LD (1<<PCI_TARGET_CTRL_LD_SHIFT) +#define PCI_TARGET_CTRL_P (1<<PCI_TARGET_CTRL_P_SHIFT) + +/* PCI Initiator Window Configuration Register (PCIIWCR) */ +#define PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT 27 +#define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_SHIFT 25 +#define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_MASK 0x3 +#define PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT 24 +#define PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT 19 +#define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_SHIFT 17 +#define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_MASK 0x3 +#define PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT 16 +#define PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT 11 +#define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_SHIFT 9 +#define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_MASK 0x3 +#define PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT 8 + +#define PCI_INIT_WIN_CFG_WIN_MEM_READ 0x0 +#define PCI_INIT_WIN_CFG_WIN_MEM_READ_LINE 0x1 +#define PCI_INIT_WIN_CFG_WIN_MEM_READ_MULTIPLE 0x2 + +#define PCI_INIT_WIN_CFG_WIN0_CTRL_IO (1<<PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT) +#define PCI_INIT_WIN_CFG_WIN0_CTRL_EN (1<<PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT) +#define PCI_INIT_WIN_CFG_WIN1_CTRL_IO (1<<PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT) +#define PCI_INIT_WIN_CFG_WIN1_CTRL_EN (1<<PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT) +#define PCI_INIT_WIN_CFG_WIN2_CTRL_IO (1<<PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT) +#define PCI_INIT_WIN_CFG_WIN2_CTRL_EN (1<<PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT) + +/* PCI Initiator Control Register (PCIICR) */ +#define PCI_INIT_CTRL_REE_SHIFT 26 +#define PCI_INIT_CTRL_IAE_SHIFT 25 +#define PCI_INIT_CTRL_TAE_SHIFT 24 +#define PCI_INIT_CTRL_MAX_RETRIES_SHIFT 0 +#define PCI_INIT_CTRL_MAX_RETRIES_MASK 0xff + +#define PCI_INIT_CTRL_REE (1<<PCI_INIT_CTRL_REE_SHIFT) +#define PCI_INIT_CTRL_IAE (1<<PCI_INIT_CTRL_IAE_SHIFT) +#define PCI_INIT_CTRL_TAE (1<<PCI_INIT_CTRL_TAE_SHIFT) + +/* PCI Status/Command Register (PCISCR) - PCI Dword 1 */ +#define PCI_STAT_CMD_PE_SHIFT 31 +#define PCI_STAT_CMD_SE_SHIFT 30 +#define PCI_STAT_CMD_MA_SHIFT 29 +#define PCI_STAT_CMD_TR_SHIFT 28 +#define PCI_STAT_CMD_TS_SHIFT 27 +#define PCI_STAT_CMD_DT_SHIFT 25 +#define PCI_STAT_CMD_DT_MASK 0x3 +#define PCI_STAT_CMD_DP_SHIFT 24 +#define PCI_STAT_CMD_FC_SHIFT 23 +#define PCI_STAT_CMD_R_SHIFT 22 +#define PCI_STAT_CMD_66M_SHIFT 21 +#define PCI_STAT_CMD_C_SHIFT 20 +#define PCI_STAT_CMD_F_SHIFT 9 +#define PCI_STAT_CMD_S_SHIFT 8 +#define PCI_STAT_CMD_ST_SHIFT 7 +#define PCI_STAT_CMD_PER_SHIFT 6 +#define PCI_STAT_CMD_V_SHIFT 5 +#define PCI_STAT_CMD_MW_SHIFT 4 +#define PCI_STAT_CMD_SP_SHIFT 3 +#define PCI_STAT_CMD_B_SHIFT 2 +#define PCI_STAT_CMD_M_SHIFT 1 +#define PCI_STAT_CMD_IO_SHIFT 0 + +#define PCI_STAT_CMD_PE (1<<PCI_STAT_CMD_PE_SHIFT) +#define PCI_STAT_CMD_SE (1<<PCI_STAT_CMD_SE_SHIFT) +#define PCI_STAT_CMD_MA (1<<PCI_STAT_CMD_MA_SHIFT) +#define PCI_STAT_CMD_TR (1<<PCI_STAT_CMD_TR_SHIFT) +#define PCI_STAT_CMD_TS (1<<PCI_STAT_CMD_TS_SHIFT) +#define PCI_STAT_CMD_DP (1<<PCI_STAT_CMD_DP_SHIFT) +#define PCI_STAT_CMD_FC (1<<PCI_STAT_CMD_FC_SHIFT) +#define PCI_STAT_CMD_R (1<<PCI_STAT_CMD_R_SHIFT) +#define PCI_STAT_CMD_66M (1<<PCI_STAT_CMD_66M_SHIFT) +#define PCI_STAT_CMD_C (1<<PCI_STAT_CMD_C_SHIFT) +#define PCI_STAT_CMD_F (1<<PCI_STAT_CMD_F_SHIFT) +#define PCI_STAT_CMD_S (1<<PCI_STAT_CMD_S_SHIFT) +#define PCI_STAT_CMD_ST (1<<PCI_STAT_CMD_ST_SHIFT) +#define PCI_STAT_CMD_PER (1<<PCI_STAT_CMD_PER_SHIFT) +#define PCI_STAT_CMD_V (1<<PCI_STAT_CMD_V_SHIFT) +#define PCI_STAT_CMD_MW (1<<PCI_STAT_CMD_MW_SHIFT) +#define PCI_STAT_CMD_SP (1<<PCI_STAT_CMD_SP_SHIFT) +#define PCI_STAT_CMD_B (1<<PCI_STAT_CMD_B_SHIFT) +#define PCI_STAT_CMD_M (1<<PCI_STAT_CMD_M_SHIFT) +#define PCI_STAT_CMD_IO (1<<PCI_STAT_CMD_IO_SHIFT) + +/* PCI Configuration 1 Register (PCICR1) - PCI Dword 3 */ +#define PCI_CFG1_HT_SHIFT 16 +#define PCI_CFG1_HT_MASK 0xff +#define PCI_CFG1_LT_SHIFT 8 +#define PCI_CFG1_LT_MASK 0xff +#define PCI_CFG1_CLS_SHIFT 0 +#define PCI_CFG1_CLS_MASK 0xf /* function prototypes */ void loadtask(int basetask, int tasks); |