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-rw-r--r--include/asm-arm/arch-at91/at91_pmc.h23
-rw-r--r--include/asm-arm/arch-s5pc1xx/clk.h6
-rw-r--r--include/asm-arm/arch-s5pc1xx/gpio.h29
-rw-r--r--include/asm-arm/arch-s5pc1xx/smc.h53
-rw-r--r--include/configs/meesc.h1
-rw-r--r--include/configs/otc570.h1
-rw-r--r--include/configs/smdkc100.h12
7 files changed, 117 insertions, 8 deletions
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
index 680fe33..5b1a85d 100644
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ b/include/asm-arm/arch-at91/at91_pmc.h
@@ -108,11 +108,12 @@ typedef struct at91_pmc {
#define AT91_PMC_IXR_PCKRDY3 0x00000800
#ifdef CONFIG_AT91_LEGACY
-
#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
+#endif
+
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
@@ -128,27 +129,34 @@ typedef struct at91_pmc {
#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
+#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
+#endif
+
#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
+#ifdef CONFIG_AT91_LEGACY
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
+#endif
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
-
+#ifdef CONFIG_AT91_LEGACY
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
+#endif
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
-
+#ifdef CONFIG_AT91_LEGACY
#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
+#endif
#define AT91_PMC_DIV (0xff << 0) /* Divider */
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
@@ -160,7 +168,9 @@ typedef struct at91_pmc {
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
+#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
+#endif
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
#define AT91_PMC_CSS_SLOW (0 << 0)
#define AT91_PMC_CSS_MAIN (1 << 0)
@@ -188,11 +198,13 @@ typedef struct at91_pmc {
#define AT91_PMC_PDIV_1 (0 << 12)
#define AT91_PMC_PDIV_2 (1 << 12)
+#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
+#endif
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
@@ -203,12 +215,13 @@ typedef struct at91_pmc {
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
+#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
+#endif
#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
-
+#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
-
#endif /* CONFIG_AT91_LEGACY */
#endif
diff --git a/include/asm-arm/arch-s5pc1xx/clk.h b/include/asm-arm/arch-s5pc1xx/clk.h
index f1aa44f..3e59abe 100644
--- a/include/asm-arm/arch-s5pc1xx/clk.h
+++ b/include/asm-arm/arch-s5pc1xx/clk.h
@@ -23,6 +23,12 @@
#ifndef __ASM_ARM_ARCH_CLK_H_
#define __ASM_ARM_ARCH_CLK_H_
+#define APLL 0
+#define MPLL 1
+#define EPLL 2
+#define HPLL 3
+#define VPLL 4
+
void s5pc1xx_clock_init(void);
extern unsigned long (*get_pll_clk)(int pllreg);
diff --git a/include/asm-arm/arch-s5pc1xx/gpio.h b/include/asm-arm/arch-s5pc1xx/gpio.h
index afbc7ea..8e4bb86 100644
--- a/include/asm-arm/arch-s5pc1xx/gpio.h
+++ b/include/asm-arm/arch-s5pc1xx/gpio.h
@@ -124,6 +124,35 @@ struct s5pc110_gpio {
struct s5pc1xx_gpio_bank gpio_h2;
struct s5pc1xx_gpio_bank gpio_h3;
};
+
+/* functions */
+void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg);
+void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en);
+void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio);
+void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en);
+unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio);
+void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode);
+void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode);
+void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode);
#endif
+/* Pin configurations */
+#define GPIO_INPUT 0x0
+#define GPIO_OUTPUT 0x1
+#define GPIO_IRQ 0xf
+#define GPIO_FUNC(x) (x)
+
+/* Pull mode */
+#define GPIO_PULL_NONE 0x0
+#define GPIO_PULL_DOWN 0x1
+#define GPIO_PULL_UP 0x2
+
+/* Drive Strength level */
+#define GPIO_DRV_1X 0x0
+#define GPIO_DRV_2X 0x1
+#define GPIO_DRV_3X 0x2
+#define GPIO_DRV_4X 0x3
+#define GPIO_DRV_FAST 0x0
+#define GPIO_DRV_SLOW 0x1
+
#endif
diff --git a/include/asm-arm/arch-s5pc1xx/smc.h b/include/asm-arm/arch-s5pc1xx/smc.h
new file mode 100644
index 0000000..88f4ffe
--- /dev/null
+++ b/include/asm-arm/arch-s5pc1xx/smc.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Naveen Krishna Ch <ch.naveen@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: This file contains the register description for Memory subsystem
+ * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
+ *
+ * Only SROMC is defined as of now
+ */
+
+#ifndef __ASM_ARCH_SMC_H_
+#define __ASM_ARCH_SMC_H_
+
+#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0))
+#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
+ /* 1-> Byte base address*/
+#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2))
+#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3))
+
+#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */
+#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */
+#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */
+#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */
+#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */
+#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */
+#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
+
+#ifndef __ASSEMBLY__
+struct s5pc1xx_smc {
+ unsigned int bw;
+ unsigned int bc[6];
+};
+#endif /* __ASSEMBLY__ */
+
+/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
+void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
+
+#endif /* __ASM_ARCH_SMC_H_ */
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index d002b97..e085f4a 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -82,7 +82,6 @@
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
diff --git a/include/configs/otc570.h b/include/configs/otc570.h
index 4fde012..fb0f576 100644
--- a/include/configs/otc570.h
+++ b/include/configs/otc570.h
@@ -131,7 +131,6 @@
* Command line configuration.
*/
#include <config_cmd_default.h>
-#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index a8ba052..09bce6d 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -83,7 +83,6 @@
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_NET
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_REGINFO
@@ -235,4 +234,15 @@
#define CONFIG_DOS_PARTITION 1
+/*
+ * Ethernet Contoller driver
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X 1 /* we have a SMC9115 on-board */
+#define CONFIG_SMC911X_16_BIT 1 /* SMC911X_16_BIT Mode */
+#define CONFIG_SMC911X_BASE 0x98800300 /* SMC911X Drive Base */
+#define CONFIG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/
+#endif /* CONFIG_CMD_NET */
+
#endif /* __CONFIG_H */
generated by cgit v1.1 at 2024-11-13 04:35:11 +0000