diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-at91sam9/at91cap9.h | 1 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91sam9/at91sam9260.h | 124 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91sam9/at91sam9260_matrix.h | 78 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91sam9/at91sam926x_mc.h | 1 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91sam9/gpio.h | 2 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91sam9/hardware.h | 4 | ||||
| -rw-r--r-- | include/configs/at91sam9260ek.h | 191 |
7 files changed, 397 insertions, 4 deletions
diff --git a/include/asm-arm/arch-at91sam9/at91cap9.h b/include/asm-arm/arch-at91sam9/at91cap9.h index bac83ad..e16909c 100644 --- a/include/asm-arm/arch-at91sam9/at91cap9.h +++ b/include/asm-arm/arch-at91sam9/at91cap9.h @@ -107,7 +107,6 @@ #define AT91_USART1 AT91CAP9_BASE_US1 #define AT91_USART2 AT91CAP9_BASE_US2 - /* * Internal Memory. */ diff --git a/include/asm-arm/arch-at91sam9/at91sam9260.h b/include/asm-arm/arch-at91sam9/at91sam9260.h new file mode 100644 index 0000000..1bf4598 --- /dev/null +++ b/include/asm-arm/arch-at91sam9/at91sam9260.h @@ -0,0 +1,124 @@ +/* + * include/asm-arm/arch-at91/at91sam9260.h + * + * (C) 2006 Andrew Victor + * + * Common definitions. + * Based on AT91SAM9260 datasheet revision A (Preliminary). + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9260_H +#define AT91SAM9260_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Peripherals */ +#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ +#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ +#define AT91SAM9260_ID_US0 6 /* USART 0 */ +#define AT91SAM9260_ID_US1 7 /* USART 1 */ +#define AT91SAM9260_ID_US2 8 /* USART 2 */ +#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ +#define AT91SAM9260_ID_UDP 10 /* USB Device Port */ +#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ +#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ +#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ +#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ +#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ +#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ +#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ +#define AT91SAM9260_ID_UHP 20 /* USB Host port */ +#define AT91SAM9260_ID_EMAC 21 /* Ethernet */ +#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ +#define AT91SAM9260_ID_US3 23 /* USART 3 */ +#define AT91SAM9260_ID_US4 24 /* USART 4 */ +#define AT91SAM9260_ID_US5 25 /* USART 5 */ +#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ +#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ +#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ +#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ + +/* + * User Peripheral physical base addresses. + */ +#define AT91SAM9260_BASE_TCB0 0xfffa0000 +#define AT91SAM9260_BASE_TC0 0xfffa0000 +#define AT91SAM9260_BASE_TC1 0xfffa0040 +#define AT91SAM9260_BASE_TC2 0xfffa0080 +#define AT91SAM9260_BASE_UDP 0xfffa4000 +#define AT91SAM9260_BASE_MCI 0xfffa8000 +#define AT91SAM9260_BASE_TWI 0xfffac000 +#define AT91SAM9260_BASE_US0 0xfffb0000 +#define AT91SAM9260_BASE_US1 0xfffb4000 +#define AT91SAM9260_BASE_US2 0xfffb8000 +#define AT91SAM9260_BASE_SSC 0xfffbc000 +#define AT91SAM9260_BASE_ISI 0xfffc0000 +#define AT91SAM9260_BASE_EMAC 0xfffc4000 +#define AT91SAM9260_BASE_SPI0 0xfffc8000 +#define AT91SAM9260_BASE_SPI1 0xfffcc000 +#define AT91SAM9260_BASE_US3 0xfffd0000 +#define AT91SAM9260_BASE_US4 0xfffd4000 +#define AT91SAM9260_BASE_US5 0xfffd8000 +#define AT91SAM9260_BASE_TCB1 0xfffdc000 +#define AT91SAM9260_BASE_TC3 0xfffdc000 +#define AT91SAM9260_BASE_TC4 0xfffdc040 +#define AT91SAM9260_BASE_TC5 0xfffdc080 +#define AT91SAM9260_BASE_ADC 0xfffe0000 +#define AT91_BASE_SYS 0xffffe800 + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) +#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) +#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) +#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) +#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) +#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) +#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) +#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) +#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) +#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) + +#define AT91_USART0 AT91SAM9260_BASE_US0 +#define AT91_USART1 AT91SAM9260_BASE_US1 +#define AT91_USART2 AT91SAM9260_BASE_US2 +#define AT91_USART3 AT91SAM9260_BASE_US3 +#define AT91_USART4 AT91SAM9260_BASE_US4 +#define AT91_USART5 AT91SAM9260_BASE_US5 + +/* + * Internal Memory. + */ +#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ +#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ + +#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ +#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ +#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ +#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ + +#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ + +#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ +#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ + +#endif diff --git a/include/asm-arm/arch-at91sam9/at91sam9260_matrix.h b/include/asm-arm/arch-at91sam9/at91sam9260_matrix.h new file mode 100644 index 0000000..a8e9fec --- /dev/null +++ b/include/asm-arm/arch-at91sam9/at91sam9260_matrix.h @@ -0,0 +1,78 @@ +/* + * include/asm-arm/arch-at91/at91sam9260_matrix.h + * + * Memory Controllers (MATRIX, EBI) - System peripherals registers. + * Based on AT91SAM9260 datasheet revision B. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9260_MATRIX_H +#define AT91SAM9260_MATRIX_H + +#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ +#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ +#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ +#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ +#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ +#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ +#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) + +#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ +#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ +#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ +#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ +#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ +#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ +#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ +#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) + +#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ +#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ +#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ +#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ +#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ +#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ +#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ +#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ +#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ +#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ +#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ + +#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ +#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ +#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ + +#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ +#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ +#define AT91_MATRIX_CS1A_SMC (0 << 1) +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ +#define AT91_MATRIX_CS3A_SMC (0 << 3) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ +#define AT91_MATRIX_CS4A_SMC (0 << 4) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ +#define AT91_MATRIX_CS5A_SMC (0 << 5) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ +#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) + +#endif diff --git a/include/asm-arm/arch-at91sam9/at91sam926x_mc.h b/include/asm-arm/arch-at91sam9/at91sam926x_mc.h index d82631c..041138f 100644 --- a/include/asm-arm/arch-at91sam9/at91sam926x_mc.h +++ b/include/asm-arm/arch-at91sam9/at91sam926x_mc.h @@ -79,7 +79,6 @@ #define AT91_SDRAMC_MD_SDRAM 0 #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 - /* Static Memory Controller (SMC) registers */ #define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ diff --git a/include/asm-arm/arch-at91sam9/gpio.h b/include/asm-arm/arch-at91sam9/gpio.h index cdd9cc2..2500eae 100644 --- a/include/asm-arm/arch-at91sam9/gpio.h +++ b/include/asm-arm/arch-at91sam9/gpio.h @@ -200,7 +200,6 @@ static unsigned long at91_pios[] = { #endif }; - static inline void *pin_to_controller(unsigned pin) { pin -= PIN_BASE; @@ -228,7 +227,6 @@ static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup) return 0; } - /* * mux the pin to the "A" internal peripheral role. */ diff --git a/include/asm-arm/arch-at91sam9/hardware.h b/include/asm-arm/arch-at91sam9/hardware.h index 0d889ff..80b334f 100644 --- a/include/asm-arm/arch-at91sam9/hardware.h +++ b/include/asm-arm/arch-at91sam9/hardware.h @@ -20,6 +20,10 @@ #include <asm/arch/at91rm9200.h> #elif defined(CONFIG_AT91SAM9260) #include <asm/arch/at91sam9260.h> +#define AT91_BASE_EMAC AT91SAM9260_BASE_EMAC +#define AT91_BASE_SPI AT91SAM9260_BASE_SPI0 +#define AT91_ID_UHP AT91SAM9260_ID_UHP +#define AT91_PMC_UHP AT91SAM926x_PMC_UHP #elif defined(CONFIG_AT91SAM9261) #include <asm/arch/at91sam9261.h> #elif defined(CONFIG_AT91SAM9263) diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h new file mode 100644 index 0000000..96d1b8d --- /dev/null +++ b/include/configs/at91sam9260ek.h @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop <at> leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * Configuation settings for the AT91SAM9260EK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91_MAIN_CLOCK 198656000 /* from 18.432 MHz crystal */ +#define AT91_MASTER_CLOCK 99328000 /* peripheral = main / 2 */ +#define CFG_HZ 1000000 /* 1us resolution */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/ +#define CONFIG_AT91SAM9260EK 1 /* on an AT91SAM9260EK Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 rw rootfstype=jffs2" + +/* #define CONFIG_ENV_OVERWRITE 1 */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* DataFlash */ +#define CONFIG_HAS_DATAFLASH 1 +#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) +#define CFG_MAX_DATAFLASH_BANKS 2 +#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define CFG_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */ +#define AT91_SPI_CLK 33000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* NAND flash */ +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 +#define CFG_NAND_BASE 0x40000000 + +/* NOR flash - no real flash on this board */ +#define CFG_NO_FLASH 1 + +/* Ethernet */ +#define CONFIG_MACB 1 +#define CONFIG_RMII 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R 1 + +/* USB */ +#define CONFIG_USB_OHCI_NEW 1 +#define LITTLEENDIAN 1 +#define CONFIG_DOS_PARTITION 1 +#define CFG_USB_OHCI_CPU_INIT 1 +#define CFG_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ +#define CFG_USB_OHCI_SLOT_NAME "at91sam9260" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 + +#define CFG_LOAD_ADDR 0x22000000 /* load address */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END 0x23e00000 + +#undef CFG_USE_DATAFLASH_CS0 +#define CFG_USE_DATAFLASH_CS1 1 +#undef CFG_USE_NANDFLASH + +#ifdef CFG_USE_DATAFLASH_CS0 + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CFG_ENV_IS_IN_DATAFLASH 1 +#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) +#define CFG_ENV_OFFSET 0x4200 +#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) +#define CFG_ENV_SIZE 0x4200 +#define CONFIG_BOOTCOMMAND "cp.b 0xC003DE00 0x22000000 0x200040; bootm" + +#elif CFG_USE_DATAFLASH_CS1 + +/* bootstrap + u-boot + env + linux in dataflash on CS1 */ +#define CFG_ENV_IS_IN_DATAFLASH 1 +#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400) +#define CFG_ENV_OFFSET 0x4200 +#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS1 + CFG_ENV_OFFSET) +#define CFG_ENV_SIZE 0x4200 +#define CONFIG_BOOTCOMMAND "cp.b 0xD003DE00 0x22000000 0x200040; bootm" + +#else /* CFG_USE_NANDFLASH */ + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_OFFSET 0x60000 +#define CFG_ENV_OFFSET_REDUND 0x80000 +#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" + +#endif + +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CFG_PROMPT "U-Boot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000) +#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif |